| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
| 96.23 | 95.53 | 94.17 | 95.47 | 95.13 | 97.53 | 99.57 |
| T2762 | /workspace/coverage/cover_reg_top/7.chip_csr_rw.3716615492 | Jun 23 07:22:28 PM PDT 24 | Jun 23 07:28:03 PM PDT 24 | 4539974625 ps | ||
| T2763 | /workspace/coverage/cover_reg_top/12.xbar_access_same_device_slow_rsp.618388594 | Jun 23 07:23:43 PM PDT 24 | Jun 23 07:37:13 PM PDT 24 | 44610297316 ps | ||
| T2764 | /workspace/coverage/cover_reg_top/90.xbar_access_same_device.3423715762 | Jun 23 07:40:02 PM PDT 24 | Jun 23 07:40:23 PM PDT 24 | 226988704 ps | ||
| T2765 | /workspace/coverage/cover_reg_top/1.chip_csr_rw.2692320385 | Jun 23 07:21:19 PM PDT 24 | Jun 23 07:30:07 PM PDT 24 | 5307532473 ps | ||
| T2766 | /workspace/coverage/cover_reg_top/46.xbar_stress_all_with_error.2310381800 | Jun 23 07:32:38 PM PDT 24 | Jun 23 07:35:12 PM PDT 24 | 2402268386 ps | ||
| T2767 | /workspace/coverage/cover_reg_top/49.xbar_random.615292830 | Jun 23 07:32:34 PM PDT 24 | Jun 23 07:33:28 PM PDT 24 | 560221631 ps | ||
| T2768 | /workspace/coverage/cover_reg_top/44.xbar_unmapped_addr.3263633735 | Jun 23 07:31:44 PM PDT 24 | Jun 23 07:32:14 PM PDT 24 | 240348933 ps | ||
| T2769 | /workspace/coverage/cover_reg_top/59.xbar_random.3624082386 | Jun 23 07:34:23 PM PDT 24 | Jun 23 07:35:19 PM PDT 24 | 1538704819 ps | ||
| T2770 | /workspace/coverage/cover_reg_top/93.xbar_stress_all_with_rand_reset.385708723 | Jun 23 07:40:14 PM PDT 24 | Jun 23 07:42:17 PM PDT 24 | 337110911 ps | ||
| T2771 | /workspace/coverage/cover_reg_top/10.xbar_access_same_device_slow_rsp.1409618041 | Jun 23 07:23:06 PM PDT 24 | Jun 23 08:08:17 PM PDT 24 | 141602958570 ps | ||
| T2772 | /workspace/coverage/cover_reg_top/46.xbar_random_zero_delays.3975963402 | Jun 23 07:32:28 PM PDT 24 | Jun 23 07:32:39 PM PDT 24 | 80099363 ps | ||
| T2773 | /workspace/coverage/cover_reg_top/16.xbar_smoke_zero_delays.3846281582 | Jun 23 07:25:09 PM PDT 24 | Jun 23 07:25:16 PM PDT 24 | 49787123 ps | ||
| T2774 | /workspace/coverage/cover_reg_top/8.chip_tl_errors.2661691825 | Jun 23 07:22:27 PM PDT 24 | Jun 23 07:27:13 PM PDT 24 | 3378627379 ps | ||
| T2775 | /workspace/coverage/cover_reg_top/87.xbar_unmapped_addr.946294962 | Jun 23 07:39:19 PM PDT 24 | Jun 23 07:39:40 PM PDT 24 | 498939700 ps | ||
| T2776 | /workspace/coverage/cover_reg_top/36.xbar_same_source.979118442 | Jun 23 07:30:06 PM PDT 24 | Jun 23 07:30:36 PM PDT 24 | 351605998 ps | ||
| T2777 | /workspace/coverage/cover_reg_top/9.xbar_smoke_zero_delays.2028616228 | Jun 23 07:22:45 PM PDT 24 | Jun 23 07:22:52 PM PDT 24 | 48667959 ps | ||
| T2778 | /workspace/coverage/cover_reg_top/23.xbar_stress_all_with_error.3180833992 | Jun 23 07:27:34 PM PDT 24 | Jun 23 07:29:36 PM PDT 24 | 1574842714 ps | ||
| T2779 | /workspace/coverage/cover_reg_top/18.xbar_smoke_large_delays.1941841810 | Jun 23 07:25:46 PM PDT 24 | Jun 23 07:27:26 PM PDT 24 | 9057895330 ps | ||
| T2780 | /workspace/coverage/cover_reg_top/65.xbar_random_slow_rsp.2879692207 | Jun 23 07:35:25 PM PDT 24 | Jun 23 07:45:04 PM PDT 24 | 35440516069 ps | ||
| T2781 | /workspace/coverage/cover_reg_top/48.xbar_smoke_zero_delays.4019114866 | Jun 23 07:32:39 PM PDT 24 | Jun 23 07:32:46 PM PDT 24 | 49734580 ps | ||
| T2782 | /workspace/coverage/cover_reg_top/92.xbar_smoke_large_delays.1093729790 | Jun 23 07:40:01 PM PDT 24 | Jun 23 07:41:35 PM PDT 24 | 9304917800 ps | ||
| T2783 | /workspace/coverage/cover_reg_top/17.xbar_smoke_large_delays.2601487184 | Jun 23 07:25:24 PM PDT 24 | Jun 23 07:27:05 PM PDT 24 | 9365585466 ps | ||
| T2784 | /workspace/coverage/cover_reg_top/51.xbar_unmapped_addr.1729290780 | Jun 23 07:33:08 PM PDT 24 | Jun 23 07:33:44 PM PDT 24 | 828869871 ps | ||
| T2785 | /workspace/coverage/cover_reg_top/28.xbar_smoke_zero_delays.3157056340 | Jun 23 07:28:14 PM PDT 24 | Jun 23 07:28:20 PM PDT 24 | 45978136 ps | ||
| T2786 | /workspace/coverage/cover_reg_top/62.xbar_smoke_large_delays.210419170 | Jun 23 07:35:18 PM PDT 24 | Jun 23 07:36:57 PM PDT 24 | 8865432301 ps | ||
| T138 | /workspace/coverage/cover_reg_top/4.chip_csr_hw_reset.2992766466 | Jun 23 07:21:28 PM PDT 24 | Jun 23 07:27:50 PM PDT 24 | 5450088104 ps | ||
| T2787 | /workspace/coverage/cover_reg_top/14.xbar_access_same_device_slow_rsp.3700363009 | Jun 23 07:24:39 PM PDT 24 | Jun 23 07:37:04 PM PDT 24 | 45305867253 ps | ||
| T2788 | /workspace/coverage/cover_reg_top/51.xbar_stress_all_with_reset_error.2834332723 | Jun 23 07:33:07 PM PDT 24 | Jun 23 07:34:58 PM PDT 24 | 122098430 ps | ||
| T2789 | /workspace/coverage/cover_reg_top/75.xbar_unmapped_addr.416327291 | Jun 23 07:37:29 PM PDT 24 | Jun 23 07:38:11 PM PDT 24 | 990970372 ps | ||
| T2790 | /workspace/coverage/cover_reg_top/78.xbar_random_large_delays.3152281918 | Jun 23 07:37:50 PM PDT 24 | Jun 23 07:41:11 PM PDT 24 | 19648183359 ps | ||
| T2791 | /workspace/coverage/cover_reg_top/93.xbar_unmapped_addr.1835583163 | Jun 23 07:40:13 PM PDT 24 | Jun 23 07:40:34 PM PDT 24 | 185041878 ps | ||
| T2792 | /workspace/coverage/cover_reg_top/6.xbar_stress_all_with_rand_reset.993690452 | Jun 23 07:21:49 PM PDT 24 | Jun 23 07:29:23 PM PDT 24 | 2606135606 ps | ||
| T2793 | /workspace/coverage/cover_reg_top/97.xbar_random_slow_rsp.1356259345 | Jun 23 07:40:57 PM PDT 24 | Jun 23 07:43:07 PM PDT 24 | 7876914754 ps | ||
| T2794 | /workspace/coverage/cover_reg_top/0.xbar_smoke_large_delays.1887857195 | Jun 23 07:20:56 PM PDT 24 | Jun 23 07:22:24 PM PDT 24 | 8460225847 ps | ||
| T2795 | /workspace/coverage/cover_reg_top/24.xbar_access_same_device.1954204496 | Jun 23 07:27:32 PM PDT 24 | Jun 23 07:28:11 PM PDT 24 | 565146058 ps | ||
| T2796 | /workspace/coverage/cover_reg_top/14.chip_csr_rw.2120642140 | Jun 23 07:24:39 PM PDT 24 | Jun 23 07:33:49 PM PDT 24 | 4918954617 ps | ||
| T2797 | /workspace/coverage/cover_reg_top/70.xbar_error_and_unmapped_addr.3900027440 | Jun 23 07:36:19 PM PDT 24 | Jun 23 07:36:38 PM PDT 24 | 169055227 ps | ||
| T2798 | /workspace/coverage/cover_reg_top/15.xbar_random.1905571679 | Jun 23 07:25:03 PM PDT 24 | Jun 23 07:25:45 PM PDT 24 | 1152002005 ps | ||
| T2799 | /workspace/coverage/cover_reg_top/90.xbar_access_same_device_slow_rsp.705990933 | Jun 23 07:40:02 PM PDT 24 | Jun 23 07:53:50 PM PDT 24 | 48271295047 ps | ||
| T2800 | /workspace/coverage/cover_reg_top/53.xbar_same_source.2751520364 | Jun 23 07:33:43 PM PDT 24 | Jun 23 07:34:06 PM PDT 24 | 736334399 ps | ||
| T2801 | /workspace/coverage/cover_reg_top/53.xbar_access_same_device.3257143532 | Jun 23 07:33:19 PM PDT 24 | Jun 23 07:34:34 PM PDT 24 | 1814388450 ps | ||
| T2802 | /workspace/coverage/cover_reg_top/24.xbar_stress_all.170532745 | Jun 23 07:27:32 PM PDT 24 | Jun 23 07:38:01 PM PDT 24 | 15187379045 ps | ||
| T2803 | /workspace/coverage/cover_reg_top/14.xbar_access_same_device.2154892383 | Jun 23 07:24:41 PM PDT 24 | Jun 23 07:25:57 PM PDT 24 | 937513626 ps | ||
| T2804 | /workspace/coverage/cover_reg_top/88.xbar_access_same_device.2984075070 | Jun 23 07:39:25 PM PDT 24 | Jun 23 07:39:40 PM PDT 24 | 212669468 ps | ||
| T2805 | /workspace/coverage/cover_reg_top/61.xbar_stress_all_with_error.3806024355 | Jun 23 07:35:27 PM PDT 24 | Jun 23 07:39:00 PM PDT 24 | 6233558657 ps | ||
| T2806 | /workspace/coverage/cover_reg_top/89.xbar_stress_all_with_error.2018498797 | Jun 23 07:39:38 PM PDT 24 | Jun 23 07:39:58 PM PDT 24 | 228373739 ps | ||
| T2807 | /workspace/coverage/cover_reg_top/55.xbar_stress_all.617242341 | Jun 23 07:33:57 PM PDT 24 | Jun 23 07:39:30 PM PDT 24 | 4329976292 ps | ||
| T2808 | /workspace/coverage/cover_reg_top/50.xbar_stress_all.3114661897 | Jun 23 07:33:02 PM PDT 24 | Jun 23 07:33:44 PM PDT 24 | 444417622 ps | ||
| T2809 | /workspace/coverage/cover_reg_top/57.xbar_stress_all_with_rand_reset.3528641922 | Jun 23 07:34:13 PM PDT 24 | Jun 23 07:50:42 PM PDT 24 | 18472145314 ps | ||
| T2810 | /workspace/coverage/cover_reg_top/65.xbar_smoke_large_delays.3638832494 | Jun 23 07:35:24 PM PDT 24 | Jun 23 07:37:05 PM PDT 24 | 9906828490 ps | ||
| T2811 | /workspace/coverage/cover_reg_top/49.xbar_random_zero_delays.2036965678 | Jun 23 07:32:39 PM PDT 24 | Jun 23 07:33:02 PM PDT 24 | 257927338 ps | ||
| T2812 | /workspace/coverage/cover_reg_top/3.xbar_smoke.816365928 | Jun 23 07:21:21 PM PDT 24 | Jun 23 07:21:29 PM PDT 24 | 134171636 ps | ||
| T2813 | /workspace/coverage/cover_reg_top/53.xbar_random_large_delays.3421048292 | Jun 23 07:33:19 PM PDT 24 | Jun 23 07:37:19 PM PDT 24 | 21990337847 ps | ||
| T2814 | /workspace/coverage/cover_reg_top/18.xbar_random_large_delays.2441683250 | Jun 23 07:25:50 PM PDT 24 | Jun 23 07:27:14 PM PDT 24 | 7557427820 ps | ||
| T2815 | /workspace/coverage/cover_reg_top/6.xbar_access_same_device_slow_rsp.2648864731 | Jun 23 07:21:41 PM PDT 24 | Jun 23 07:32:58 PM PDT 24 | 41872054827 ps | ||
| T2816 | /workspace/coverage/cover_reg_top/20.xbar_unmapped_addr.99120966 | Jun 23 07:26:29 PM PDT 24 | Jun 23 07:26:58 PM PDT 24 | 261901211 ps | ||
| T2817 | /workspace/coverage/cover_reg_top/92.xbar_error_and_unmapped_addr.4032666512 | Jun 23 07:40:05 PM PDT 24 | Jun 23 07:40:52 PM PDT 24 | 1296268794 ps | ||
| T2818 | /workspace/coverage/cover_reg_top/63.xbar_smoke.2755725123 | Jun 23 07:35:16 PM PDT 24 | Jun 23 07:35:25 PM PDT 24 | 189668186 ps | ||
| T2819 | /workspace/coverage/cover_reg_top/80.xbar_stress_all_with_rand_reset.2425937520 | Jun 23 07:38:08 PM PDT 24 | Jun 23 07:41:36 PM PDT 24 | 3850253115 ps | ||
| T2820 | /workspace/coverage/cover_reg_top/79.xbar_error_random.987075689 | Jun 23 07:38:00 PM PDT 24 | Jun 23 07:38:13 PM PDT 24 | 129255475 ps | ||
| T2821 | /workspace/coverage/cover_reg_top/40.xbar_random_slow_rsp.2111510369 | Jun 23 07:30:48 PM PDT 24 | Jun 23 07:40:12 PM PDT 24 | 36851732662 ps | ||
| T2822 | /workspace/coverage/cover_reg_top/18.xbar_stress_all_with_rand_reset.4104527926 | Jun 23 07:25:54 PM PDT 24 | Jun 23 07:33:15 PM PDT 24 | 1992568386 ps | ||
| T2823 | /workspace/coverage/cover_reg_top/23.xbar_error_random.1145369476 | Jun 23 07:27:34 PM PDT 24 | Jun 23 07:27:57 PM PDT 24 | 303194661 ps | ||
| T2824 | /workspace/coverage/cover_reg_top/16.xbar_random.1832155070 | Jun 23 07:25:09 PM PDT 24 | Jun 23 07:25:34 PM PDT 24 | 243527172 ps | ||
| T2825 | /workspace/coverage/cover_reg_top/11.xbar_access_same_device.196672368 | Jun 23 07:23:40 PM PDT 24 | Jun 23 07:25:01 PM PDT 24 | 2201694866 ps | ||
| T2826 | /workspace/coverage/cover_reg_top/84.xbar_random_large_delays.3804143533 | Jun 23 07:38:38 PM PDT 24 | Jun 23 07:49:43 PM PDT 24 | 62668486110 ps | ||
| T2827 | /workspace/coverage/cover_reg_top/45.xbar_stress_all_with_reset_error.3555660501 | Jun 23 07:32:28 PM PDT 24 | Jun 23 07:37:16 PM PDT 24 | 2272869132 ps | ||
| T2828 | /workspace/coverage/cover_reg_top/1.xbar_same_source.97203531 | Jun 23 07:21:04 PM PDT 24 | Jun 23 07:21:22 PM PDT 24 | 195295322 ps | ||
| T2829 | /workspace/coverage/cover_reg_top/67.xbar_random_zero_delays.1299020390 | Jun 23 07:35:46 PM PDT 24 | Jun 23 07:36:03 PM PDT 24 | 165827333 ps | ||
| T2830 | /workspace/coverage/cover_reg_top/32.xbar_random.2879287848 | Jun 23 07:29:17 PM PDT 24 | Jun 23 07:30:43 PM PDT 24 | 2306002462 ps | ||
| T2831 | /workspace/coverage/cover_reg_top/13.xbar_smoke_zero_delays.1520946410 | Jun 23 07:24:08 PM PDT 24 | Jun 23 07:24:15 PM PDT 24 | 52068430 ps | ||
| T2832 | /workspace/coverage/cover_reg_top/94.xbar_random.378526615 | Jun 23 07:40:43 PM PDT 24 | Jun 23 07:41:13 PM PDT 24 | 316525158 ps | ||
| T2833 | /workspace/coverage/cover_reg_top/61.xbar_smoke_slow_rsp.1333419824 | Jun 23 07:35:10 PM PDT 24 | Jun 23 07:36:27 PM PDT 24 | 4455147876 ps | ||
| T2834 | /workspace/coverage/cover_reg_top/79.xbar_stress_all_with_reset_error.2208293371 | Jun 23 07:38:10 PM PDT 24 | Jun 23 07:38:46 PM PDT 24 | 91270635 ps | ||
| T2835 | /workspace/coverage/cover_reg_top/54.xbar_unmapped_addr.1039737071 | Jun 23 07:33:59 PM PDT 24 | Jun 23 07:34:35 PM PDT 24 | 884153161 ps | ||
| T2836 | /workspace/coverage/cover_reg_top/1.chip_tl_errors.3942277563 | Jun 23 07:21:07 PM PDT 24 | Jun 23 07:23:44 PM PDT 24 | 3286628992 ps | ||
| T2837 | /workspace/coverage/cover_reg_top/74.xbar_smoke_slow_rsp.1438640977 | Jun 23 07:36:59 PM PDT 24 | Jun 23 07:38:17 PM PDT 24 | 4625825555 ps | ||
| T2838 | /workspace/coverage/cover_reg_top/11.xbar_access_same_device_slow_rsp.1968855580 | Jun 23 07:23:28 PM PDT 24 | Jun 23 07:45:23 PM PDT 24 | 78925831385 ps | ||
| T2839 | /workspace/coverage/cover_reg_top/81.xbar_error_and_unmapped_addr.3258673704 | Jun 23 07:38:30 PM PDT 24 | Jun 23 07:38:41 PM PDT 24 | 75487803 ps | ||
| T2840 | /workspace/coverage/cover_reg_top/38.xbar_error_and_unmapped_addr.3200883080 | Jun 23 07:30:42 PM PDT 24 | Jun 23 07:31:09 PM PDT 24 | 636565980 ps | ||
| T2841 | /workspace/coverage/cover_reg_top/85.xbar_stress_all.515626251 | Jun 23 07:38:57 PM PDT 24 | Jun 23 07:39:49 PM PDT 24 | 630873370 ps | ||
| T2842 | /workspace/coverage/cover_reg_top/9.xbar_unmapped_addr.3668779675 | Jun 23 07:22:54 PM PDT 24 | Jun 23 07:23:25 PM PDT 24 | 870153109 ps | ||
| T2843 | /workspace/coverage/cover_reg_top/2.xbar_stress_all.3972403226 | Jun 23 07:21:17 PM PDT 24 | Jun 23 07:24:58 PM PDT 24 | 2930575769 ps | ||
| T2844 | /workspace/coverage/cover_reg_top/51.xbar_smoke.3462436115 | Jun 23 07:32:56 PM PDT 24 | Jun 23 07:33:07 PM PDT 24 | 227038965 ps | ||
| T2845 | /workspace/coverage/cover_reg_top/8.xbar_error_random.631765067 | Jun 23 07:22:34 PM PDT 24 | Jun 23 07:23:56 PM PDT 24 | 2398004435 ps | ||
| T2846 | /workspace/coverage/cover_reg_top/56.xbar_stress_all_with_rand_reset.182992081 | Jun 23 07:33:54 PM PDT 24 | Jun 23 07:41:55 PM PDT 24 | 4129121020 ps | ||
| T2847 | /workspace/coverage/cover_reg_top/53.xbar_stress_all.1711338540 | Jun 23 07:33:49 PM PDT 24 | Jun 23 07:35:18 PM PDT 24 | 1033208113 ps | ||
| T2848 | /workspace/coverage/cover_reg_top/28.xbar_smoke.1846681277 | Jun 23 07:28:10 PM PDT 24 | Jun 23 07:28:20 PM PDT 24 | 225355812 ps | ||
| T2849 | /workspace/coverage/cover_reg_top/3.xbar_unmapped_addr.528183417 | Jun 23 07:21:22 PM PDT 24 | Jun 23 07:22:25 PM PDT 24 | 1501638989 ps | ||
| T2850 | /workspace/coverage/cover_reg_top/59.xbar_access_same_device_slow_rsp.795391460 | Jun 23 07:34:20 PM PDT 24 | Jun 23 08:11:01 PM PDT 24 | 122382734133 ps | ||
| T2851 | /workspace/coverage/cover_reg_top/95.xbar_random.2165806970 | Jun 23 07:40:51 PM PDT 24 | Jun 23 07:41:38 PM PDT 24 | 543131653 ps | ||
| T2852 | /workspace/coverage/cover_reg_top/6.xbar_error_and_unmapped_addr.3070179137 | Jun 23 07:21:51 PM PDT 24 | Jun 23 07:22:27 PM PDT 24 | 813056226 ps | ||
| T2853 | /workspace/coverage/cover_reg_top/23.xbar_stress_all_with_rand_reset.2533829772 | Jun 23 07:27:31 PM PDT 24 | Jun 23 07:33:32 PM PDT 24 | 1989249379 ps | ||
| T2854 | /workspace/coverage/cover_reg_top/1.xbar_stress_all_with_rand_reset.194219802 | Jun 23 07:21:07 PM PDT 24 | Jun 23 07:23:24 PM PDT 24 | 232090644 ps | ||
| T2855 | /workspace/coverage/cover_reg_top/1.chip_csr_bit_bash.2475875204 | Jun 23 07:21:15 PM PDT 24 | Jun 23 07:28:45 PM PDT 24 | 5623341676 ps | ||
| T2856 | /workspace/coverage/cover_reg_top/93.xbar_smoke.3782493125 | Jun 23 07:40:05 PM PDT 24 | Jun 23 07:40:14 PM PDT 24 | 184759395 ps | ||
| T2857 | /workspace/coverage/cover_reg_top/90.xbar_random.3409221323 | Jun 23 07:39:56 PM PDT 24 | Jun 23 07:40:17 PM PDT 24 | 217833134 ps | ||
| T2858 | /workspace/coverage/cover_reg_top/75.xbar_same_source.3635079755 | Jun 23 07:37:30 PM PDT 24 | Jun 23 07:38:00 PM PDT 24 | 902892807 ps | ||
| T2859 | /workspace/coverage/cover_reg_top/68.xbar_error_random.212589876 | Jun 23 07:35:57 PM PDT 24 | Jun 23 07:36:43 PM PDT 24 | 1260976834 ps | ||
| T2860 | /workspace/coverage/cover_reg_top/82.xbar_same_source.888000857 | Jun 23 07:38:57 PM PDT 24 | Jun 23 07:39:31 PM PDT 24 | 447545362 ps | ||
| T2861 | /workspace/coverage/cover_reg_top/80.xbar_random_slow_rsp.3085966860 | Jun 23 07:38:05 PM PDT 24 | Jun 23 07:50:16 PM PDT 24 | 41213122317 ps | ||
| T2862 | /workspace/coverage/cover_reg_top/78.xbar_random.2273738221 | Jun 23 07:37:38 PM PDT 24 | Jun 23 07:38:00 PM PDT 24 | 502318730 ps | ||
| T2863 | /workspace/coverage/cover_reg_top/37.xbar_unmapped_addr.1887167704 | Jun 23 07:30:40 PM PDT 24 | Jun 23 07:30:49 PM PDT 24 | 150981146 ps | ||
| T2864 | /workspace/coverage/cover_reg_top/31.xbar_random_zero_delays.3068670698 | Jun 23 07:28:59 PM PDT 24 | Jun 23 07:29:44 PM PDT 24 | 474277732 ps | ||
| T2865 | /workspace/coverage/cover_reg_top/3.chip_tl_errors.965284672 | Jun 23 07:21:31 PM PDT 24 | Jun 23 07:29:35 PM PDT 24 | 5539731120 ps | ||
| T2866 | /workspace/coverage/cover_reg_top/71.xbar_random.3473034549 | Jun 23 07:36:20 PM PDT 24 | Jun 23 07:37:19 PM PDT 24 | 1665720941 ps | ||
| T2867 | /workspace/coverage/cover_reg_top/77.xbar_stress_all_with_rand_reset.2160422274 | Jun 23 07:37:37 PM PDT 24 | Jun 23 07:45:38 PM PDT 24 | 5852366041 ps | ||
| T2868 | /workspace/coverage/cover_reg_top/79.xbar_stress_all.3352970324 | Jun 23 07:38:00 PM PDT 24 | Jun 23 07:39:59 PM PDT 24 | 1383098511 ps | ||
| T2869 | /workspace/coverage/cover_reg_top/10.xbar_error_random.4151134311 | Jun 23 07:23:11 PM PDT 24 | Jun 23 07:24:04 PM PDT 24 | 1642548370 ps | ||
| T2870 | /workspace/coverage/cover_reg_top/53.xbar_unmapped_addr.1157775683 | Jun 23 07:33:47 PM PDT 24 | Jun 23 07:34:18 PM PDT 24 | 783282806 ps | ||
| T2871 | /workspace/coverage/cover_reg_top/74.xbar_smoke.3223682772 | Jun 23 07:36:56 PM PDT 24 | Jun 23 07:37:02 PM PDT 24 | 39373764 ps | ||
| T2872 | /workspace/coverage/cover_reg_top/71.xbar_stress_all.2465738723 | Jun 23 07:36:28 PM PDT 24 | Jun 23 07:46:15 PM PDT 24 | 14365643930 ps | ||
| T2873 | /workspace/coverage/cover_reg_top/7.xbar_error_random.8897727 | Jun 23 07:22:25 PM PDT 24 | Jun 23 07:23:31 PM PDT 24 | 1774353820 ps | ||
| T2874 | /workspace/coverage/cover_reg_top/88.xbar_stress_all.1444168214 | Jun 23 07:39:24 PM PDT 24 | Jun 23 07:44:25 PM PDT 24 | 7722616209 ps | ||
| T2875 | /workspace/coverage/cover_reg_top/21.xbar_smoke_zero_delays.985093421 | Jun 23 07:26:31 PM PDT 24 | Jun 23 07:26:37 PM PDT 24 | 45900670 ps | ||
| T2876 | /workspace/coverage/cover_reg_top/86.xbar_stress_all_with_rand_reset.393900248 | Jun 23 07:39:00 PM PDT 24 | Jun 23 07:42:38 PM PDT 24 | 5155762446 ps | ||
| T2877 | /workspace/coverage/cover_reg_top/83.xbar_smoke_large_delays.4091255040 | Jun 23 07:38:42 PM PDT 24 | Jun 23 07:39:37 PM PDT 24 | 5494030683 ps | ||
| T2878 | /workspace/coverage/cover_reg_top/25.xbar_access_same_device_slow_rsp.98933557 | Jun 23 07:27:46 PM PDT 24 | Jun 23 07:33:56 PM PDT 24 | 20726385593 ps | ||
| T2879 | /workspace/coverage/cover_reg_top/41.xbar_random_slow_rsp.4010136440 | Jun 23 07:31:06 PM PDT 24 | Jun 23 07:39:09 PM PDT 24 | 30153352715 ps | ||
| T2880 | /workspace/coverage/cover_reg_top/0.xbar_stress_all.3436852985 | Jun 23 07:21:00 PM PDT 24 | Jun 23 07:23:38 PM PDT 24 | 1979001497 ps | ||
| T2881 | /workspace/coverage/cover_reg_top/24.xbar_random_large_delays.2082650224 | Jun 23 07:27:31 PM PDT 24 | Jun 23 07:32:01 PM PDT 24 | 26404030059 ps | ||
| T2882 | /workspace/coverage/cover_reg_top/1.xbar_access_same_device.53461001 | Jun 23 07:21:07 PM PDT 24 | Jun 23 07:23:01 PM PDT 24 | 2666984270 ps | ||
| T42 | /workspace/coverage/pad_ctrl_test_mode/9.chip_padctrl_attributes.507002124 | Jun 23 08:20:04 PM PDT 24 | Jun 23 08:24:33 PM PDT 24 | 4345715478 ps | ||
| T43 | /workspace/coverage/pad_ctrl_test_mode/4.chip_padctrl_attributes.3948511355 | Jun 23 08:19:58 PM PDT 24 | Jun 23 08:24:59 PM PDT 24 | 5673061766 ps | ||
| T44 | /workspace/coverage/pad_ctrl_test_mode/1.chip_padctrl_attributes.587047245 | Jun 23 08:19:42 PM PDT 24 | Jun 23 08:25:15 PM PDT 24 | 5031524168 ps | ||
| T180 | /workspace/coverage/pad_ctrl_test_mode/2.chip_padctrl_attributes.3676098104 | Jun 23 08:19:41 PM PDT 24 | Jun 23 08:24:06 PM PDT 24 | 4491296904 ps | ||
| T181 | /workspace/coverage/pad_ctrl_test_mode/6.chip_padctrl_attributes.2449375178 | Jun 23 08:20:00 PM PDT 24 | Jun 23 08:25:08 PM PDT 24 | 5078961780 ps | ||
| T182 | /workspace/coverage/pad_ctrl_test_mode/8.chip_padctrl_attributes.2027880926 | Jun 23 08:20:02 PM PDT 24 | Jun 23 08:25:29 PM PDT 24 | 4730408265 ps | ||
| T183 | /workspace/coverage/pad_ctrl_test_mode/3.chip_padctrl_attributes.3888883063 | Jun 23 08:19:49 PM PDT 24 | Jun 23 08:23:35 PM PDT 24 | 4973085734 ps | ||
| T184 | /workspace/coverage/pad_ctrl_test_mode/7.chip_padctrl_attributes.1602427009 | Jun 23 08:20:06 PM PDT 24 | Jun 23 08:27:31 PM PDT 24 | 5013919410 ps | ||
| T188 | /workspace/coverage/pad_ctrl_test_mode/5.chip_padctrl_attributes.4242834143 | Jun 23 08:20:00 PM PDT 24 | Jun 23 08:24:34 PM PDT 24 | 4588023057 ps | ||
| T185 | /workspace/coverage/pad_ctrl_test_mode/0.chip_padctrl_attributes.692698897 | Jun 23 08:19:31 PM PDT 24 | Jun 23 08:24:27 PM PDT 24 | 5011361976 ps |
| Test location | /workspace/coverage/default/0.chip_sw_pwrmgr_normal_sleep_all_reset_reqs.1967370869 |
| Short name | T62 |
| Test name | |
| Test status | |
| Simulation time | 13571422731 ps |
| CPU time | 1781.8 seconds |
| Started | Jun 23 07:49:50 PM PDT 24 |
| Finished | Jun 23 08:19:32 PM PDT 24 |
| Peak memory | 608904 kb |
| Host | smart-9720f37f-842e-48fb-993a-44e6515e3b7b |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_normal_sleep_all_reset_reqs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1967370869 -assert nop ostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_deep_sleep_all_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_normal_sleep_all_reset_reqs.1967370869 |
| Directory | /workspace/0.chip_sw_pwrmgr_normal_sleep_all_reset_reqs/latest |
| Test location | /workspace/coverage/cover_reg_top/4.chip_csr_rw.2071467829 |
| Short name | T142 |
| Test name | |
| Test status | |
| Simulation time | 6207831214 ps |
| CPU time | 691.38 seconds |
| Started | Jun 23 07:21:30 PM PDT 24 |
| Finished | Jun 23 07:33:02 PM PDT 24 |
| Peak memory | 596556 kb |
| Host | smart-9b19efee-f1ec-4833-8727-cfc37880f18d |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2071467829 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.chip_csr_rw.2071467829 |
| Directory | /workspace/4.chip_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/53.xbar_stress_all_with_error.1390979639 |
| Short name | T356 |
| Test name | |
| Test status | |
| Simulation time | 11214660913 ps |
| CPU time | 357.21 seconds |
| Started | Jun 23 07:33:52 PM PDT 24 |
| Finished | Jun 23 07:39:49 PM PDT 24 |
| Peak memory | 574308 kb |
| Host | smart-0f944ace-be68-47e7-9a6b-fb8997b1529f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1390979639 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 53.xbar_stress_all_with_error.1390979639 |
| Directory | /workspace/53.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/default/0.chip_plic_all_irqs_20.1653152517 |
| Short name | T296 |
| Test name | |
| Test status | |
| Simulation time | 4676722524 ps |
| CPU time | 749.09 seconds |
| Started | Jun 23 07:51:25 PM PDT 24 |
| Finished | Jun 23 08:03:54 PM PDT 24 |
| Peak memory | 606828 kb |
| Host | smart-0836d1c7-05d9-44f0-a9e8-c10081451c26 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=plic_all_irqs_test_20:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1653152517 -assert nopostproc +UVM_TESTN AME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log / dev/null -cm_name 0.chip_plic_all_irqs_20.1653152517 |
| Directory | /workspace/0.chip_plic_all_irqs_20/latest |
| Test location | /workspace/coverage/cover_reg_top/3.xbar_access_same_device_slow_rsp.3817591361 |
| Short name | T439 |
| Test name | |
| Test status | |
| Simulation time | 103884245924 ps |
| CPU time | 1921.95 seconds |
| Started | Jun 23 07:21:23 PM PDT 24 |
| Finished | Jun 23 07:53:26 PM PDT 24 |
| Peak memory | 574284 kb |
| Host | smart-c518ec1d-4b7c-4886-84f9-fda886326a50 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3817591361 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.xbar_access_same_d evice_slow_rsp.3817591361 |
| Directory | /workspace/3.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/pad_ctrl_test_mode/9.chip_padctrl_attributes.507002124 |
| Short name | T42 |
| Test name | |
| Test status | |
| Simulation time | 4345715478 ps |
| CPU time | 268.11 seconds |
| Started | Jun 23 08:20:04 PM PDT 24 |
| Finished | Jun 23 08:24:33 PM PDT 24 |
| Peak memory | 643776 kb |
| Host | smart-6355f070-d845-474b-a268-59112e518254 |
| User | root |
| Command | /workspace/pad_ctrl_test_mode/simv +use_otp_image=OtpTypeLcStProd +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=507002124 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TES T_SEQ=chip_padctrl_attributes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/pad_ctrl_test_mode.vdb -cm_log /dev/n ull -cm_name 9.chip_padctrl_attributes.507002124 |
| Directory | /workspace/9.chip_padctrl_attributes/latest |
| Test location | /workspace/coverage/default/0.chip_sw_keymgr_sideload_kmac.3829212844 |
| Short name | T45 |
| Test name | |
| Test status | |
| Simulation time | 6208484472 ps |
| CPU time | 1471.83 seconds |
| Started | Jun 23 07:52:09 PM PDT 24 |
| Finished | Jun 23 08:16:42 PM PDT 24 |
| Peak memory | 607992 kb |
| Host | smart-c54561cb-565f-430b-8b2e-aefc14201e5a |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=20_000_000 +sw_build_device=sim_dv +sw_images=keymgr_sideload_kmac_test:1:new_rules,test_rom:0 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38292 12844 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_keymgr_sideload_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_keymgr_sideload_kmac.3829212844 |
| Directory | /workspace/0.chip_sw_keymgr_sideload_kmac/latest |
| Test location | /workspace/coverage/cover_reg_top/22.xbar_access_same_device_slow_rsp.3805829972 |
| Short name | T849 |
| Test name | |
| Test status | |
| Simulation time | 85558994714 ps |
| CPU time | 1565.31 seconds |
| Started | Jun 23 07:26:59 PM PDT 24 |
| Finished | Jun 23 07:53:05 PM PDT 24 |
| Peak memory | 574224 kb |
| Host | smart-3ea19269-6abd-45b4-8739-628244c5f4b7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3805829972 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.xbar_access_same_ device_slow_rsp.3805829972 |
| Directory | /workspace/22.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/31.xbar_access_same_device_slow_rsp.1654011567 |
| Short name | T867 |
| Test name | |
| Test status | |
| Simulation time | 106460402410 ps |
| CPU time | 1957.1 seconds |
| Started | Jun 23 07:29:00 PM PDT 24 |
| Finished | Jun 23 08:01:38 PM PDT 24 |
| Peak memory | 573524 kb |
| Host | smart-54b4a584-fd1a-4772-8251-e62e7bc76083 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1654011567 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.xbar_access_same_ device_slow_rsp.1654011567 |
| Directory | /workspace/31.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/default/1.chip_sw_alert_test.935743305 |
| Short name | T59 |
| Test name | |
| Test status | |
| Simulation time | 3166056700 ps |
| CPU time | 279.78 seconds |
| Started | Jun 23 07:58:17 PM PDT 24 |
| Finished | Jun 23 08:02:57 PM PDT 24 |
| Peak memory | 606916 kb |
| Host | smart-f3e1d201-6622-4bd9-bf48-373569fd2a13 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=alert_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=935743305 -assert nopostproc +UVM_TESTNAME=chip_bas e_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm _name 1.chip_sw_alert_test.935743305 |
| Directory | /workspace/1.chip_sw_alert_test/latest |
| Test location | /workspace/coverage/default/2.chip_sw_sleep_pin_mio_dio_val.3350780587 |
| Short name | T23 |
| Test name | |
| Test status | |
| Simulation time | 3821851202 ps |
| CPU time | 383.03 seconds |
| Started | Jun 23 08:06:20 PM PDT 24 |
| Finished | Jun 23 08:12:44 PM PDT 24 |
| Peak memory | 607020 kb |
| Host | smart-d6e39749-4a77-4c08-b96e-f40775703a12 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStProd +sw_build_device=sim_dv +sw_images=sleep_pin_mio_dio_val_test:1:new_rules,test_rom:0 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3350 780587 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sleep_pin_mio_dio_val_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_sleep_pin_mio_dio_val.3350780587 |
| Directory | /workspace/2.chip_sw_sleep_pin_mio_dio_val/latest |
| Test location | /workspace/coverage/default/1.chip_sw_lc_walkthrough_testunlocks.3053508796 |
| Short name | T163 |
| Test name | |
| Test status | |
| Simulation time | 34092636088 ps |
| CPU time | 2654.92 seconds |
| Started | Jun 23 07:57:24 PM PDT 24 |
| Finished | Jun 23 08:41:40 PM PDT 24 |
| Peak memory | 618260 kb |
| Host | smart-92f8229e-b03d-4908-8f85-8e1eec56628f |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStRaw +dest_dec_state=DecLcStTestUnlock7 +sw_build_device=sim_dv +sw_images=lc_walkthrough_testunlocks _test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=3053508796 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_walkthrough_testunlocks_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_lc_walkthrough_testun locks.3053508796 |
| Directory | /workspace/1.chip_sw_lc_walkthrough_testunlocks/latest |
| Test location | /workspace/coverage/default/1.chip_sw_pwrmgr_deep_sleep_all_wake_ups.2928812518 |
| Short name | T2 |
| Test name | |
| Test status | |
| Simulation time | 18920686426 ps |
| CPU time | 1338.06 seconds |
| Started | Jun 23 08:02:17 PM PDT 24 |
| Finished | Jun 23 08:24:36 PM PDT 24 |
| Peak memory | 608664 kb |
| Host | smart-076afe94-3b42-426a-a119-5eb504ffcfab |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=pwrmgr_deep_sleep_all_wake_ups:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 2928812518 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_pwrmgr_deep_sleep_all_wake_ups_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_deep_sleep_all_wake_ups.2928812518 |
| Directory | /workspace/1.chip_sw_pwrmgr_deep_sleep_all_wake_ups/latest |
| Test location | /workspace/coverage/default/2.chip_plic_all_irqs_0.1348436019 |
| Short name | T313 |
| Test name | |
| Test status | |
| Simulation time | 6059751650 ps |
| CPU time | 1161.22 seconds |
| Started | Jun 23 08:13:03 PM PDT 24 |
| Finished | Jun 23 08:32:25 PM PDT 24 |
| Peak memory | 608036 kb |
| Host | smart-fbb3865b-9471-4b70-a209-3b3fec5ca7d7 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=plic_all_irqs_test_0:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1348436019 -assert nopostproc +UVM_TESTNA ME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 2.chip_plic_all_irqs_0.1348436019 |
| Directory | /workspace/2.chip_plic_all_irqs_0/latest |
| Test location | /workspace/coverage/cover_reg_top/77.xbar_stress_all_with_reset_error.1072370827 |
| Short name | T577 |
| Test name | |
| Test status | |
| Simulation time | 10907102955 ps |
| CPU time | 993.57 seconds |
| Started | Jun 23 07:37:40 PM PDT 24 |
| Finished | Jun 23 07:54:14 PM PDT 24 |
| Peak memory | 582560 kb |
| Host | smart-1542e752-562f-4616-a3d7-015434588104 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1072370827 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 77.xbar_stress_al l_with_reset_error.1072370827 |
| Directory | /workspace/77.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/default/2.rom_e2e_keymgr_init_rom_ext_invalid_meas.1793081053 |
| Short name | T54 |
| Test name | |
| Test status | |
| Simulation time | 15277169376 ps |
| CPU time | 3117.33 seconds |
| Started | Jun 23 08:19:51 PM PDT 24 |
| Finished | Jun 23 09:11:49 PM PDT 24 |
| Peak memory | 606876 kb |
| Host | smart-1a52b8de-f6b3-4b9c-9727-24dab5ca5d5e |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=40_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=rom_e2e_keymgr_init_otp_invalid _meas:1:new_rules,otp_img_keymgr_otp_invalid_meas:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1793081053 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip _sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_e2e_keymgr_in it_rom_ext_invalid_meas.1793081053 |
| Directory | /workspace/2.rom_e2e_keymgr_init_rom_ext_invalid_meas/latest |
| Test location | /workspace/coverage/cover_reg_top/76.xbar_access_same_device_slow_rsp.3253089725 |
| Short name | T854 |
| Test name | |
| Test status | |
| Simulation time | 105580673995 ps |
| CPU time | 1896.28 seconds |
| Started | Jun 23 07:37:33 PM PDT 24 |
| Finished | Jun 23 08:09:10 PM PDT 24 |
| Peak memory | 574264 kb |
| Host | smart-d529be10-4b74-4aa4-a315-13844c9e898b |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3253089725 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 76.xbar_access_same_ device_slow_rsp.3253089725 |
| Directory | /workspace/76.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/default/2.chip_sw_rv_core_ibex_address_translation.3072872742 |
| Short name | T171 |
| Test name | |
| Test status | |
| Simulation time | 3006240270 ps |
| CPU time | 330.83 seconds |
| Started | Jun 23 08:13:12 PM PDT 24 |
| Finished | Jun 23 08:18:43 PM PDT 24 |
| Peak memory | 606952 kb |
| Host | smart-8902c150-ffc4-4936-a996-58d92526e730 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=7_000_000 +sw_build_device=sim_dv +sw_images=rv_core_ibex_address_translation_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=3072872742 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_rv_core_ibex_address_translation.3072872742 |
| Directory | /workspace/2.chip_sw_rv_core_ibex_address_translation/latest |
| Test location | /workspace/coverage/cover_reg_top/96.xbar_access_same_device_slow_rsp.3493312971 |
| Short name | T872 |
| Test name | |
| Test status | |
| Simulation time | 44361834303 ps |
| CPU time | 796.4 seconds |
| Started | Jun 23 07:40:50 PM PDT 24 |
| Finished | Jun 23 07:54:07 PM PDT 24 |
| Peak memory | 574200 kb |
| Host | smart-0b719ccc-52d6-4a00-ba91-263695be5268 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3493312971 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 96.xbar_access_same_ device_slow_rsp.3493312971 |
| Directory | /workspace/96.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/97.xbar_access_same_device_slow_rsp.4134490635 |
| Short name | T437 |
| Test name | |
| Test status | |
| Simulation time | 109972369165 ps |
| CPU time | 2061.5 seconds |
| Started | Jun 23 07:40:50 PM PDT 24 |
| Finished | Jun 23 08:15:12 PM PDT 24 |
| Peak memory | 574188 kb |
| Host | smart-4b022ca9-7f7b-4a95-a660-5248eaf83bfb |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4134490635 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 97.xbar_access_same_ device_slow_rsp.4134490635 |
| Directory | /workspace/97.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/default/1.chip_jtag_csr_rw.1814489329 |
| Short name | T7 |
| Test name | |
| Test status | |
| Simulation time | 22417668988 ps |
| CPU time | 2777.81 seconds |
| Started | Jun 23 07:55:21 PM PDT 24 |
| Finished | Jun 23 08:41:40 PM PDT 24 |
| Peak memory | 607828 kb |
| Host | smart-8956fc3a-884a-4f8b-8a22-968da81fcbce |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +csr_rw +create_jtag_riscv_map=1 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1814489329 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_T EST_SEQ=chip_jtag_csr_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.c hip_jtag_csr_rw.1814489329 |
| Directory | /workspace/1.chip_jtag_csr_rw/latest |
| Test location | /workspace/coverage/default/1.chip_sw_gpio.865095488 |
| Short name | T39 |
| Test name | |
| Test status | |
| Simulation time | 4580735776 ps |
| CPU time | 587.08 seconds |
| Started | Jun 23 07:54:54 PM PDT 24 |
| Finished | Jun 23 08:04:42 PM PDT 24 |
| Peak memory | 607580 kb |
| Host | smart-20818b47-4a94-4add-a849-a3d4265789a0 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=gpio_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=865095488 -assert nopostproc +UVM_TESTNAME=chip_base _test +UVM_TEST_SEQ=chip_sw_gpio_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 1.chip_sw_gpio.865095488 |
| Directory | /workspace/1.chip_sw_gpio/latest |
| Test location | /workspace/coverage/cover_reg_top/11.xbar_stress_all_with_error.811485543 |
| Short name | T71 |
| Test name | |
| Test status | |
| Simulation time | 1361280336 ps |
| CPU time | 96.94 seconds |
| Started | Jun 23 07:23:41 PM PDT 24 |
| Finished | Jun 23 07:25:18 PM PDT 24 |
| Peak memory | 574252 kb |
| Host | smart-652421c1-daa9-44c4-b94c-44e2aa609e3a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=811485543 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.xbar_stress_all_with_error.811485543 |
| Directory | /workspace/11.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/62.xbar_access_same_device_slow_rsp.3364644031 |
| Short name | T875 |
| Test name | |
| Test status | |
| Simulation time | 141786042333 ps |
| CPU time | 2646 seconds |
| Started | Jun 23 07:35:20 PM PDT 24 |
| Finished | Jun 23 08:19:27 PM PDT 24 |
| Peak memory | 574224 kb |
| Host | smart-28215490-a047-467e-bb71-613396ff0bb6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3364644031 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 62.xbar_access_same_ device_slow_rsp.3364644031 |
| Directory | /workspace/62.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/22.chip_tl_errors.1999838385 |
| Short name | T556 |
| Test name | |
| Test status | |
| Simulation time | 4956550669 ps |
| CPU time | 476.77 seconds |
| Started | Jun 23 07:26:52 PM PDT 24 |
| Finished | Jun 23 07:34:49 PM PDT 24 |
| Peak memory | 597356 kb |
| Host | smart-f45a421d-24b1-4aaa-9979-1a5d498b8d4d |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1999838385 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.chip_tl_errors.1999838385 |
| Directory | /workspace/22.chip_tl_errors/latest |
| Test location | /workspace/coverage/default/0.chip_plic_all_irqs_10.1640755943 |
| Short name | T152 |
| Test name | |
| Test status | |
| Simulation time | 3616661568 ps |
| CPU time | 552.25 seconds |
| Started | Jun 23 07:52:32 PM PDT 24 |
| Finished | Jun 23 08:01:45 PM PDT 24 |
| Peak memory | 606908 kb |
| Host | smart-b8d30b03-1b63-4251-ad48-16326443e12b |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=plic_all_irqs_test_10:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1640755943 -assert nopostproc +UVM_TESTN AME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log / dev/null -cm_name 0.chip_plic_all_irqs_10.1640755943 |
| Directory | /workspace/0.chip_plic_all_irqs_10/latest |
| Test location | /workspace/coverage/default/3.chip_sw_csrng_edn_concurrency.1155178979 |
| Short name | T249 |
| Test name | |
| Test status | |
| Simulation time | 11060336824 ps |
| CPU time | 2181.65 seconds |
| Started | Jun 23 08:19:34 PM PDT 24 |
| Finished | Jun 23 08:55:57 PM PDT 24 |
| Peak memory | 607252 kb |
| Host | smart-945b133e-e141-43b1-9449-6092b033373a |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=140_000_000 +rng_srate_value_min=15 +rng_srate_value_max=20 +accelerate_cold_power_up_time=3 +accelerate_r egulators_power_up_time=2 +sw_build_device=sim_dv +sw_images=csrng_edn_concurrency_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1155178979 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd b -cm_log /dev/null -cm_name 3.chip_sw_csrng_edn_concurrency.1155178979 |
| Directory | /workspace/3.chip_sw_csrng_edn_concurrency/latest |
| Test location | /workspace/coverage/cover_reg_top/74.xbar_access_same_device.1548153067 |
| Short name | T486 |
| Test name | |
| Test status | |
| Simulation time | 1495271458 ps |
| CPU time | 65.7 seconds |
| Started | Jun 23 07:36:54 PM PDT 24 |
| Finished | Jun 23 07:38:00 PM PDT 24 |
| Peak memory | 574056 kb |
| Host | smart-d5b1d106-6caa-4ac3-b197-2f33cf4ae267 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1548153067 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 74.xbar_access_same_device .1548153067 |
| Directory | /workspace/74.xbar_access_same_device/latest |
| Test location | /workspace/coverage/default/1.chip_sw_alert_handler_lpg_sleep_mode_pings.2098742878 |
| Short name | T78 |
| Test name | |
| Test status | |
| Simulation time | 10458867080 ps |
| CPU time | 1250.63 seconds |
| Started | Jun 23 07:58:34 PM PDT 24 |
| Finished | Jun 23 08:19:25 PM PDT 24 |
| Peak memory | 608524 kb |
| Host | smart-17dd77f8-7674-493a-9c8f-0d2e66625e91 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=alert_handler _lpg_sleep_mode_pings_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2098742878 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_alert_han dler_shorten_ping_wait_cycle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_alert_handler_lpg_sleep_mode_pings.2098742878 |
| Directory | /workspace/1.chip_sw_alert_handler_lpg_sleep_mode_pings/latest |
| Test location | /workspace/coverage/cover_reg_top/76.xbar_random_large_delays.3714974541 |
| Short name | T416 |
| Test name | |
| Test status | |
| Simulation time | 120747645853 ps |
| CPU time | 1202.43 seconds |
| Started | Jun 23 07:37:35 PM PDT 24 |
| Finished | Jun 23 07:57:38 PM PDT 24 |
| Peak memory | 574216 kb |
| Host | smart-8d54d4e9-ec88-47aa-97ab-481bd5c2781e |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3714974541 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 76.xbar_random_large_delays.3714974541 |
| Directory | /workspace/76.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/default/2.chip_sw_spi_host_tx_rx.777649895 |
| Short name | T46 |
| Test name | |
| Test status | |
| Simulation time | 2472039346 ps |
| CPU time | 228.88 seconds |
| Started | Jun 23 08:06:53 PM PDT 24 |
| Finished | Jun 23 08:10:42 PM PDT 24 |
| Peak memory | 606908 kb |
| Host | smart-e6171497-9b9b-4aa9-9d6b-799bb0f20c85 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=spi_host_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=777649895 -assert nopostproc +UVM_TESTNAME =chip_base_test +UVM_TEST_SEQ=chip_sw_spi_host_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -c m_log /dev/null -cm_name 2.chip_sw_spi_host_tx_rx.777649895 |
| Directory | /workspace/2.chip_sw_spi_host_tx_rx/latest |
| Test location | /workspace/coverage/default/1.chip_sw_exit_test_unlocked_bootstrap.3638080882 |
| Short name | T22 |
| Test name | |
| Test status | |
| Simulation time | 58747480000 ps |
| CPU time | 10651.6 seconds |
| Started | Jun 23 07:55:06 PM PDT 24 |
| Finished | Jun 23 10:52:40 PM PDT 24 |
| Peak memory | 623392 kb |
| Host | smart-079ba5d7-4167-4b06-b558-0c6595e6834e |
| User | root |
| Command | /workspace/default/simv +flash_program_latency=5 +sw_test_timeout_ns=150_000_000 +sw_build_device=sim_dv +sw_images=exit_test_unlocked_bootstrap:1:new _rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/s im.tcl +ntb_random_seed=3638080882 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_exit_test_unlocked_bootstrap_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_exit_test_unlocked_bootstrap.3638080882 |
| Directory | /workspace/1.chip_sw_exit_test_unlocked_bootstrap/latest |
| Test location | /workspace/coverage/cover_reg_top/47.xbar_access_same_device.2585980290 |
| Short name | T430 |
| Test name | |
| Test status | |
| Simulation time | 1974946051 ps |
| CPU time | 79.45 seconds |
| Started | Jun 23 07:32:34 PM PDT 24 |
| Finished | Jun 23 07:33:54 PM PDT 24 |
| Peak memory | 574148 kb |
| Host | smart-d9979da3-23d8-42fb-88b5-c412ace2b9e1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2585980290 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.xbar_access_same_device .2585980290 |
| Directory | /workspace/47.xbar_access_same_device/latest |
| Test location | /workspace/coverage/default/1.chip_sw_flash_init.3369540857 |
| Short name | T166 |
| Test name | |
| Test status | |
| Simulation time | 22127273774 ps |
| CPU time | 2130.54 seconds |
| Started | Jun 23 07:53:16 PM PDT 24 |
| Finished | Jun 23 08:28:47 PM PDT 24 |
| Peak memory | 609212 kb |
| Host | smart-2e97f1bc-3235-49e5-b1ac-10f3c91f8228 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=25_000_000 +sw_build_device=sim_dv +sw_images=flash_init_test:0:test_in_rom:new_rules +cdc_instrumentation _enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3369540857 -as sert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_flash_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac e/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_flash_init.3369540857 |
| Directory | /workspace/1.chip_sw_flash_init/latest |
| Test location | /workspace/coverage/cover_reg_top/11.chip_same_csr_outstanding.363318229 |
| Short name | T144 |
| Test name | |
| Test status | |
| Simulation time | 32247553409 ps |
| CPU time | 3905.72 seconds |
| Started | Jun 23 07:23:17 PM PDT 24 |
| Finished | Jun 23 08:28:24 PM PDT 24 |
| Peak memory | 590416 kb |
| Host | smart-39373a45-f6dc-4f4f-985c-f142469b3bd6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +run_same_csr_outstanding +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=363318229 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c m_log /dev/null -cm_name 11.chip_same_csr_outstanding.363318229 |
| Directory | /workspace/11.chip_same_csr_outstanding/latest |
| Test location | /workspace/coverage/default/0.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup.3338728825 |
| Short name | T104 |
| Test name | |
| Test status | |
| Simulation time | 5280392750 ps |
| CPU time | 482.96 seconds |
| Started | Jun 23 07:54:19 PM PDT 24 |
| Finished | Jun 23 08:02:22 PM PDT 24 |
| Peak memory | 607064 kb |
| Host | smart-80a390eb-e1a1-4b43-be54-02b1cbd19f29 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=8_000_000 +sw_build_device=sim_dv +sw_images=sensor_ctrl_wakeup_test:1:new_rules,test_rom:0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33387288 25 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac e/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup.3338728825 |
| Directory | /workspace/0.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup/latest |
| Test location | /workspace/coverage/default/1.chip_sw_sleep_pin_mio_dio_val.2453059250 |
| Short name | T24 |
| Test name | |
| Test status | |
| Simulation time | 2905612827 ps |
| CPU time | 267.32 seconds |
| Started | Jun 23 07:55:43 PM PDT 24 |
| Finished | Jun 23 08:00:12 PM PDT 24 |
| Peak memory | 607032 kb |
| Host | smart-93bf45f7-7cb9-4a5a-b59d-a5d6d44acfbe |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStProd +sw_build_device=sim_dv +sw_images=sleep_pin_mio_dio_val_test:1:new_rules,test_rom:0 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2453 059250 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sleep_pin_mio_dio_val_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_sleep_pin_mio_dio_val.2453059250 |
| Directory | /workspace/1.chip_sw_sleep_pin_mio_dio_val/latest |
| Test location | /workspace/coverage/default/0.chip_sw_sram_ctrl_scrambled_access_jitter_en.4120630537 |
| Short name | T112 |
| Test name | |
| Test status | |
| Simulation time | 4017377811 ps |
| CPU time | 461.52 seconds |
| Started | Jun 23 07:52:06 PM PDT 24 |
| Finished | Jun 23 07:59:48 PM PDT 24 |
| Peak memory | 608112 kb |
| Host | smart-a2c7e4f9-030f-41ae-85af-74e53063f4de |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=12_000_000 +bypass_alert_ready_to_end_check=1 +en_jitter=1 +en_scb_tl_err_chk=0 +sw_build_device=sim_dv +s w_images=sram_ctrl_scrambled_access_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4120630537 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chi p_sw_sram_ctrl_scrambled_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n ame 0.chip_sw_sram_ctrl_scrambled_access_jitter_en.4120630537 |
| Directory | /workspace/0.chip_sw_sram_ctrl_scrambled_access_jitter_en/latest |
| Test location | /workspace/coverage/default/2.chip_sw_ast_clk_rst_inputs.2030925660 |
| Short name | T106 |
| Test name | |
| Test status | |
| Simulation time | 14600002499 ps |
| CPU time | 1532.59 seconds |
| Started | Jun 23 08:15:56 PM PDT 24 |
| Finished | Jun 23 08:41:30 PM PDT 24 |
| Peak memory | 608504 kb |
| Host | smart-a563948e-18f8-4f5b-9f9f-9bd3e7dae042 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=200_000_000 +sw_build_device=sim_dv +sw_images=ast_clk_rst_inputs:1:new_rules,test_rom:0 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2030925660 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_ast_clk_rst_inputs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_ast_clk_rst_inputs.2030925660 |
| Directory | /workspace/2.chip_sw_ast_clk_rst_inputs/latest |
| Test location | /workspace/coverage/default/1.chip_sw_flash_rma_unlocked.27961527 |
| Short name | T178 |
| Test name | |
| Test status | |
| Simulation time | 43590955911 ps |
| CPU time | 5305.69 seconds |
| Started | Jun 23 07:55:40 PM PDT 24 |
| Finished | Jun 23 09:24:07 PM PDT 24 |
| Peak memory | 623412 kb |
| Host | smart-47f14133-be9d-4824-b89f-d351cc3f22f2 |
| User | root |
| Command | /workspace/default/simv +flash_program_latency=5 +sw_test_timeout_ns=150_000_000 +sw_build_device=sim_dv +sw_images=flash_rma_unlocked_test:0:test_in_ rom:new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t cl +ntb_random_seed=27961527 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_flash_rma_unlocked_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_flash_rma_unlocked.27961527 |
| Directory | /workspace/1.chip_sw_flash_rma_unlocked/latest |
| Test location | /workspace/coverage/default/37.chip_sw_all_escalation_resets.3892562821 |
| Short name | T160 |
| Test name | |
| Test status | |
| Simulation time | 5123156204 ps |
| CPU time | 525 seconds |
| Started | Jun 23 08:21:26 PM PDT 24 |
| Finished | Jun 23 08:30:11 PM PDT 24 |
| Peak memory | 617420 kb |
| Host | smart-e076e6f4-03f2-4e25-b1af-66d00abfb444 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 3892562821 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.chip_sw_all_escalation_resets.3892562821 |
| Directory | /workspace/37.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/cover_reg_top/21.chip_tl_errors.1994148545 |
| Short name | T521 |
| Test name | |
| Test status | |
| Simulation time | 4218353168 ps |
| CPU time | 367.78 seconds |
| Started | Jun 23 07:26:37 PM PDT 24 |
| Finished | Jun 23 07:32:45 PM PDT 24 |
| Peak memory | 603496 kb |
| Host | smart-f30daffc-cbda-4d6e-aabf-984d4a840db1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1994148545 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.chip_tl_errors.1994148545 |
| Directory | /workspace/21.chip_tl_errors/latest |
| Test location | /workspace/coverage/default/4.chip_tap_straps_rma.1025058184 |
| Short name | T64 |
| Test name | |
| Test status | |
| Simulation time | 7067603826 ps |
| CPU time | 744.39 seconds |
| Started | Jun 23 08:17:54 PM PDT 24 |
| Finished | Jun 23 08:30:20 PM PDT 24 |
| Peak memory | 622452 kb |
| Host | smart-3eeb8e7b-a5c7-46b8-b249-a5aac54f5fe9 |
| User | root |
| Command | /workspace/default/simv +create_jtag_riscv_map=1 +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:test_in_rom:new_rules +cdc_instrumentation _enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1025058184 -as sert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_tap_straps_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/c overage/default.vdb -cm_log /dev/null -cm_name 4.chip_tap_straps_rma.1025058184 |
| Directory | /workspace/4.chip_tap_straps_rma/latest |
| Test location | /workspace/coverage/default/24.chip_sw_all_escalation_resets.4065101475 |
| Short name | T345 |
| Test name | |
| Test status | |
| Simulation time | 5638712048 ps |
| CPU time | 646.73 seconds |
| Started | Jun 23 08:20:44 PM PDT 24 |
| Finished | Jun 23 08:31:31 PM PDT 24 |
| Peak memory | 647736 kb |
| Host | smart-3b1906d6-7827-43d9-a92a-5e760cecef43 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 4065101475 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.chip_sw_all_escalation_resets.4065101475 |
| Directory | /workspace/24.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/0.chip_sw_sleep_pin_mio_dio_val.2403994906 |
| Short name | T25 |
| Test name | |
| Test status | |
| Simulation time | 2757676618 ps |
| CPU time | 297.12 seconds |
| Started | Jun 23 07:48:58 PM PDT 24 |
| Finished | Jun 23 07:53:56 PM PDT 24 |
| Peak memory | 607984 kb |
| Host | smart-3553d203-2594-43bd-a372-6af118f45ea1 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStProd +sw_build_device=sim_dv +sw_images=sleep_pin_mio_dio_val_test:1:new_rules,test_rom:0 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2403 994906 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sleep_pin_mio_dio_val_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_sleep_pin_mio_dio_val.2403994906 |
| Directory | /workspace/0.chip_sw_sleep_pin_mio_dio_val/latest |
| Test location | /workspace/coverage/cover_reg_top/99.xbar_stress_all_with_rand_reset.3612432568 |
| Short name | T446 |
| Test name | |
| Test status | |
| Simulation time | 8002191238 ps |
| CPU time | 394.9 seconds |
| Started | Jun 23 07:41:12 PM PDT 24 |
| Finished | Jun 23 07:47:48 PM PDT 24 |
| Peak memory | 576356 kb |
| Host | smart-8fe107b2-e7f1-430c-9705-2a5d93a8cdfc |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3612432568 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 99.xbar_stress_all _with_rand_reset.3612432568 |
| Directory | /workspace/99.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/1.chip_sw_flash_ctrl_lc_rw_en.3940174054 |
| Short name | T20 |
| Test name | |
| Test status | |
| Simulation time | 5395106098 ps |
| CPU time | 575.37 seconds |
| Started | Jun 23 07:56:05 PM PDT 24 |
| Finished | Jun 23 08:05:40 PM PDT 24 |
| Peak memory | 608668 kb |
| Host | smart-492e1142-af94-4eb9-a9c4-5410d2977ffd |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=flash_ctrl_lc_rw_en_test:1:new_rules,test_rom:0 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39 40174054 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_flash_ctrl_lc_rw_en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_flash_ctrl_lc_rw_en.3940174054 |
| Directory | /workspace/1.chip_sw_flash_ctrl_lc_rw_en/latest |
| Test location | /workspace/coverage/default/1.chip_sw_sysrst_ctrl_reset.2664720526 |
| Short name | T36 |
| Test name | |
| Test status | |
| Simulation time | 21522728410 ps |
| CPU time | 1883.33 seconds |
| Started | Jun 23 07:57:06 PM PDT 24 |
| Finished | Jun 23 08:28:30 PM PDT 24 |
| Peak memory | 611332 kb |
| Host | smart-6946e142-185f-460f-b7a2-352380149bd6 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=36_000_000 +sw_build_device=sim_dv +sw_images=sysrst_ctrl_reset_test:1:new_rules,test_rom:0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26647205 26 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_sysrst_ctrl_reset.2664720526 |
| Directory | /workspace/1.chip_sw_sysrst_ctrl_reset/latest |
| Test location | /workspace/coverage/default/1.chip_sw_all_escalation_resets.1350454021 |
| Short name | T218 |
| Test name | |
| Test status | |
| Simulation time | 5889620994 ps |
| CPU time | 642.09 seconds |
| Started | Jun 23 07:54:23 PM PDT 24 |
| Finished | Jun 23 08:05:05 PM PDT 24 |
| Peak memory | 647880 kb |
| Host | smart-0a229add-b903-4593-ad57-2bd2b303bbfd |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 1350454021 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_all_escalation_resets.1350454021 |
| Directory | /workspace/1.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/cover_reg_top/69.xbar_stress_all_with_rand_reset.2613015211 |
| Short name | T456 |
| Test name | |
| Test status | |
| Simulation time | 7982536367 ps |
| CPU time | 536.74 seconds |
| Started | Jun 23 07:36:13 PM PDT 24 |
| Finished | Jun 23 07:45:10 PM PDT 24 |
| Peak memory | 576332 kb |
| Host | smart-8897c850-557f-4349-8080-beedcd5432df |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2613015211 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 69.xbar_stress_all _with_rand_reset.2613015211 |
| Directory | /workspace/69.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/13.chip_tl_errors.2503773243 |
| Short name | T520 |
| Test name | |
| Test status | |
| Simulation time | 3788952965 ps |
| CPU time | 308.65 seconds |
| Started | Jun 23 07:24:01 PM PDT 24 |
| Finished | Jun 23 07:29:09 PM PDT 24 |
| Peak memory | 597400 kb |
| Host | smart-0bd0ce65-0f02-4f30-ac81-262586814d6c |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2503773243 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.chip_tl_errors.2503773243 |
| Directory | /workspace/13.chip_tl_errors/latest |
| Test location | /workspace/coverage/default/2.chip_sw_csrng_lc_hw_debug_en_test.664117344 |
| Short name | T102 |
| Test name | |
| Test status | |
| Simulation time | 5559798687 ps |
| CPU time | 613.07 seconds |
| Started | Jun 23 08:11:03 PM PDT 24 |
| Finished | Jun 23 08:21:17 PM PDT 24 |
| Peak memory | 609348 kb |
| Host | smart-cdae38f8-2011-4d57-9808-49bd485196b5 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=15_000_000 +rng_srate_value_min=15 +use_otp_image=OtpTypeLcStTestUnlocked0 +sw_build_device=sim_dv +sw_ima ges=csrng_lc_hw_debug_en_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=664117344 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_csrng_l c_hw_debug_en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_csrn g_lc_hw_debug_en_test.664117344 |
| Directory | /workspace/2.chip_sw_csrng_lc_hw_debug_en_test/latest |
| Test location | /workspace/coverage/default/12.chip_sw_all_escalation_resets.2017361009 |
| Short name | T85 |
| Test name | |
| Test status | |
| Simulation time | 5214509032 ps |
| CPU time | 721.78 seconds |
| Started | Jun 23 08:21:14 PM PDT 24 |
| Finished | Jun 23 08:33:17 PM PDT 24 |
| Peak memory | 643992 kb |
| Host | smart-1f9890a6-1ab0-48f5-b1f8-cced5904ff98 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 2017361009 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.chip_sw_all_escalation_resets.2017361009 |
| Directory | /workspace/12.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/44.chip_sw_all_escalation_resets.2252395505 |
| Short name | T94 |
| Test name | |
| Test status | |
| Simulation time | 6143706200 ps |
| CPU time | 700.73 seconds |
| Started | Jun 23 08:23:35 PM PDT 24 |
| Finished | Jun 23 08:35:17 PM PDT 24 |
| Peak memory | 647904 kb |
| Host | smart-c8d81af1-a20f-4c79-a5d9-0047002e9629 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 2252395505 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.chip_sw_all_escalation_resets.2252395505 |
| Directory | /workspace/44.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/27.chip_sw_alert_handler_lpg_sleep_mode_alerts.2002544495 |
| Short name | T240 |
| Test name | |
| Test status | |
| Simulation time | 3763978120 ps |
| CPU time | 376.05 seconds |
| Started | Jun 23 08:22:12 PM PDT 24 |
| Finished | Jun 23 08:28:28 PM PDT 24 |
| Peak memory | 642468 kb |
| Host | smart-0e760455-91de-4d28-9c24-ac3b72340a94 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2002544495 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.chip_ sw_alert_handler_lpg_sleep_mode_alerts.2002544495 |
| Directory | /workspace/27.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/4.chip_sw_data_integrity_escalation.409655681 |
| Short name | T267 |
| Test name | |
| Test status | |
| Simulation time | 6083014088 ps |
| CPU time | 820.51 seconds |
| Started | Jun 23 08:17:26 PM PDT 24 |
| Finished | Jun 23 08:31:07 PM PDT 24 |
| Peak memory | 608396 kb |
| Host | smart-f3101245-84cf-4e07-a3b5-484f683efaad |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=data_integrity_escalation_reset_test:1:new_rules,test_ro m:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=409655681 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_data_integrity_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.chip_sw_data_integrity_escalation.409655681 |
| Directory | /workspace/4.chip_sw_data_integrity_escalation/latest |
| Test location | /workspace/coverage/default/1.chip_sw_edn_entropy_reqs.2722517912 |
| Short name | T150 |
| Test name | |
| Test status | |
| Simulation time | 6785551516 ps |
| CPU time | 1389.86 seconds |
| Started | Jun 23 07:59:00 PM PDT 24 |
| Finished | Jun 23 08:22:11 PM PDT 24 |
| Peak memory | 608852 kb |
| Host | smart-f694c574-9a3d-4746-a01c-7f751a00c669 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=15000000 +rng_srate_value_min=15 +rng_srate_value_max=30 +sw_build_device=sim_dv +sw_images=entropy_src_ed n_reqs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2722517912 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_edn_entropy_reqs.2722517912 |
| Directory | /workspace/1.chip_sw_edn_entropy_reqs/latest |
| Test location | /workspace/coverage/default/2.chip_sw_sleep_pin_retention.1385416794 |
| Short name | T12 |
| Test name | |
| Test status | |
| Simulation time | 3538633410 ps |
| CPU time | 381.31 seconds |
| Started | Jun 23 08:08:23 PM PDT 24 |
| Finished | Jun 23 08:14:45 PM PDT 24 |
| Peak memory | 607076 kb |
| Host | smart-f008a385-a1c8-4482-afca-95f24b960902 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=sleep_pin_retention_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1385416794 -assert nopostproc +UVM_TE STNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sleep_pin_retention_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def ault.vdb -cm_log /dev/null -cm_name 2.chip_sw_sleep_pin_retention.1385416794 |
| Directory | /workspace/2.chip_sw_sleep_pin_retention/latest |
| Test location | /workspace/coverage/default/14.chip_sw_uart_rand_baudrate.2381582176 |
| Short name | T29 |
| Test name | |
| Test status | |
| Simulation time | 4337011592 ps |
| CPU time | 525.56 seconds |
| Started | Jun 23 08:21:22 PM PDT 24 |
| Finished | Jun 23 08:30:09 PM PDT 24 |
| Peak memory | 619368 kb |
| Host | smart-50ca27b1-6b40-468e-a751-168aa8a1d2a1 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=2381582176 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.chip_sw_uart_rand_baudrate.2381582176 |
| Directory | /workspace/14.chip_sw_uart_rand_baudrate/latest |
| Test location | /workspace/coverage/default/2.chip_sw_sensor_ctrl_alert.2519033464 |
| Short name | T130 |
| Test name | |
| Test status | |
| Simulation time | 7679327900 ps |
| CPU time | 811.07 seconds |
| Started | Jun 23 08:11:35 PM PDT 24 |
| Finished | Jun 23 08:25:07 PM PDT 24 |
| Peak memory | 608424 kb |
| Host | smart-ade9ee88-77c6-4981-a5e0-0e135a9f663c |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=40_000_000 +sw_build_device=sim_dv +sw_images=sensor_ctrl_alert_test:1:new_rules,test_rom:0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25190334 64 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac e/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_sensor_ctrl_alert.2519033464 |
| Directory | /workspace/2.chip_sw_sensor_ctrl_alert/latest |
| Test location | /workspace/coverage/cover_reg_top/33.xbar_stress_all_with_rand_reset.2806978679 |
| Short name | T72 |
| Test name | |
| Test status | |
| Simulation time | 9525862440 ps |
| CPU time | 519.36 seconds |
| Started | Jun 23 07:29:34 PM PDT 24 |
| Finished | Jun 23 07:38:14 PM PDT 24 |
| Peak memory | 574304 kb |
| Host | smart-1279d6f9-528c-4ea6-8aef-7a04ecf4834f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2806978679 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.xbar_stress_all _with_rand_reset.2806978679 |
| Directory | /workspace/33.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/4.chip_csr_hw_reset.2992766466 |
| Short name | T138 |
| Test name | |
| Test status | |
| Simulation time | 5450088104 ps |
| CPU time | 381.35 seconds |
| Started | Jun 23 07:21:28 PM PDT 24 |
| Finished | Jun 23 07:27:50 PM PDT 24 |
| Peak memory | 660936 kb |
| Host | smart-438340b8-bf5b-4bb1-a66b-80357ec8aedd |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2992766466 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.chip_csr_hw_r eset.2992766466 |
| Directory | /workspace/4.chip_csr_hw_reset/latest |
| Test location | /workspace/coverage/default/2.chip_sw_lc_ctrl_rand_to_scrap.3223968371 |
| Short name | T21 |
| Test name | |
| Test status | |
| Simulation time | 2575888078 ps |
| CPU time | 130.78 seconds |
| Started | Jun 23 08:07:43 PM PDT 24 |
| Finished | Jun 23 08:09:54 PM PDT 24 |
| Peak memory | 617948 kb |
| Host | smart-5a9a8ba3-89fb-4165-88d9-8404fec17d6b |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=lc_ctrl_scrap_test:1:new_rules,test_rom:0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32239683 71 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_scrap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_lc_ctrl_rand_to_scrap.3223968371 |
| Directory | /workspace/2.chip_sw_lc_ctrl_rand_to_scrap/latest |
| Test location | /workspace/coverage/default/1.chip_sw_aes_enc.2639712620 |
| Short name | T726 |
| Test name | |
| Test status | |
| Simulation time | 3261978196 ps |
| CPU time | 302.57 seconds |
| Started | Jun 23 07:58:00 PM PDT 24 |
| Finished | Jun 23 08:03:03 PM PDT 24 |
| Peak memory | 606856 kb |
| Host | smart-0df83c4c-bd39-4fb4-9167-0a4e73653808 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=22_000_000 +sw_build_device=sim_dv +sw_images=aes_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2639712620 -asser t nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag e/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_aes_enc.2639712620 |
| Directory | /workspace/1.chip_sw_aes_enc/latest |
| Test location | /workspace/coverage/default/1.chip_sw_sleep_pin_wake.3202334990 |
| Short name | T16 |
| Test name | |
| Test status | |
| Simulation time | 6518194696 ps |
| CPU time | 445.79 seconds |
| Started | Jun 23 07:54:36 PM PDT 24 |
| Finished | Jun 23 08:02:03 PM PDT 24 |
| Peak memory | 608520 kb |
| Host | smart-24cd5ca6-6dbb-4f8e-a3a1-02c902bbd997 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStProd +sw_build_device=sim_dv +sw_images=sleep_pin_wake_test:1:new_rules,test_rom:0 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3202334990 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sleep_pin_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_sleep_pin_wake.3202334990 |
| Directory | /workspace/1.chip_sw_sleep_pin_wake/latest |
| Test location | /workspace/coverage/default/0.chip_sw_spi_device_pass_through_collision.4106233640 |
| Short name | T27 |
| Test name | |
| Test status | |
| Simulation time | 4605090633 ps |
| CPU time | 678.21 seconds |
| Started | Jun 23 07:50:22 PM PDT 24 |
| Finished | Jun 23 08:01:42 PM PDT 24 |
| Peak memory | 623444 kb |
| Host | smart-50ff1515-7c53-42f1-b071-0b4f39ea2bd6 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=spi_passthrough_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4106233640 -assert nopostproc +UVM_TESTNA ME=chip_base_test +UVM_TEST_SEQ=chip_sw_spi_passthrough_collision_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/d efault.vdb -cm_log /dev/null -cm_name 0.chip_sw_spi_device_pass_through_collision.4106233640 |
| Directory | /workspace/0.chip_sw_spi_device_pass_through_collision/latest |
| Test location | /workspace/coverage/cover_reg_top/7.chip_tl_errors.3430531681 |
| Short name | T635 |
| Test name | |
| Test status | |
| Simulation time | 4476082816 ps |
| CPU time | 368.28 seconds |
| Started | Jun 23 07:22:05 PM PDT 24 |
| Finished | Jun 23 07:28:13 PM PDT 24 |
| Peak memory | 597444 kb |
| Host | smart-6ca7868d-44aa-4455-b3b6-d4d1241843d5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3430531681 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.chip_tl_errors.3430531681 |
| Directory | /workspace/7.chip_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/19.xbar_stress_all_with_rand_reset.2415384509 |
| Short name | T428 |
| Test name | |
| Test status | |
| Simulation time | 13949366582 ps |
| CPU time | 639.27 seconds |
| Started | Jun 23 07:26:24 PM PDT 24 |
| Finished | Jun 23 07:37:04 PM PDT 24 |
| Peak memory | 576332 kb |
| Host | smart-a337376e-7ca5-46e1-a41f-666ccd174fae |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2415384509 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.xbar_stress_all _with_rand_reset.2415384509 |
| Directory | /workspace/19.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/0.chip_sw_usbdev_aon_pullup.1145513768 |
| Short name | T69 |
| Test name | |
| Test status | |
| Simulation time | 4019199308 ps |
| CPU time | 527.25 seconds |
| Started | Jun 23 07:50:25 PM PDT 24 |
| Finished | Jun 23 07:59:13 PM PDT 24 |
| Peak memory | 607656 kb |
| Host | smart-d975981d-774b-46d7-afee-e195515f7617 |
| User | root |
| Command | /workspace/default/simv +uart_idx=0 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=usbdev_aon_pullup_test:1:new_rules,test_rom:0 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=114551 3768 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_usbdev_dpi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_usbdev_aon_pullup.1145513768 |
| Directory | /workspace/0.chip_sw_usbdev_aon_pullup/latest |
| Test location | /workspace/coverage/default/0.chip_plic_all_irqs_0.101973462 |
| Short name | T320 |
| Test name | |
| Test status | |
| Simulation time | 5703618116 ps |
| CPU time | 1318.02 seconds |
| Started | Jun 23 07:50:53 PM PDT 24 |
| Finished | Jun 23 08:12:51 PM PDT 24 |
| Peak memory | 607824 kb |
| Host | smart-47f699a3-fccd-4d04-8ac4-6533a788557c |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=plic_all_irqs_test_0:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=101973462 -assert nopostproc +UVM_TESTNAM E=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 0.chip_plic_all_irqs_0.101973462 |
| Directory | /workspace/0.chip_plic_all_irqs_0/latest |
| Test location | /workspace/coverage/cover_reg_top/3.chip_same_csr_outstanding.1756028307 |
| Short name | T1472 |
| Test name | |
| Test status | |
| Simulation time | 27470175538 ps |
| CPU time | 3711.61 seconds |
| Started | Jun 23 07:21:18 PM PDT 24 |
| Finished | Jun 23 08:23:10 PM PDT 24 |
| Peak memory | 591172 kb |
| Host | smart-7a416af3-d210-43a9-a561-acf6cade0fe0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +run_same_csr_outstanding +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1756028307 -assert nopostproc +UVM_TE STNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb - cm_log /dev/null -cm_name 3.chip_same_csr_outstanding.1756028307 |
| Directory | /workspace/3.chip_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/24.xbar_stress_all_with_rand_reset.4241690685 |
| Short name | T473 |
| Test name | |
| Test status | |
| Simulation time | 20518621256 ps |
| CPU time | 900.92 seconds |
| Started | Jun 23 07:27:29 PM PDT 24 |
| Finished | Jun 23 07:42:31 PM PDT 24 |
| Peak memory | 576356 kb |
| Host | smart-11922942-2032-4f63-84b3-8eec92ec1e86 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4241690685 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.xbar_stress_all _with_rand_reset.4241690685 |
| Directory | /workspace/24.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/1.chip_sw_uart_tx_rx_alt_clk_freq.3497176999 |
| Short name | T100 |
| Test name | |
| Test status | |
| Simulation time | 4303752874 ps |
| CPU time | 581.26 seconds |
| Started | Jun 23 07:54:57 PM PDT 24 |
| Finished | Jun 23 08:04:39 PM PDT 24 |
| Peak memory | 618764 kb |
| Host | smart-69841291-d19c-4e83-a5f6-07cffd09d91b |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=80_000_000 +chip_clock_source=ChipClockSourceExternal96Mhz +calibrate_usb_clk=1 +sw_build_device=sim_dv +s w_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3497176999 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_b audrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_uart_tx_rx _alt_clk_freq.3497176999 |
| Directory | /workspace/1.chip_sw_uart_tx_rx_alt_clk_freq/latest |
| Test location | /workspace/coverage/default/2.chip_sw_flash_rma_unlocked.1148975318 |
| Short name | T175 |
| Test name | |
| Test status | |
| Simulation time | 43550818231 ps |
| CPU time | 4977.83 seconds |
| Started | Jun 23 08:06:19 PM PDT 24 |
| Finished | Jun 23 09:29:18 PM PDT 24 |
| Peak memory | 619480 kb |
| Host | smart-30ef52b8-0297-4ad1-be4b-018f5f2b0a07 |
| User | root |
| Command | /workspace/default/simv +flash_program_latency=5 +sw_test_timeout_ns=150_000_000 +sw_build_device=sim_dv +sw_images=flash_rma_unlocked_test:0:test_in_ rom:new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t cl +ntb_random_seed=1148975318 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_flash_rma_unlocked_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_flash_rma_unlocked.1148975318 |
| Directory | /workspace/2.chip_sw_flash_rma_unlocked/latest |
| Test location | /workspace/coverage/default/4.chip_sw_uart_tx_rx_idx2.2599794931 |
| Short name | T145 |
| Test name | |
| Test status | |
| Simulation time | 4257539052 ps |
| CPU time | 630.41 seconds |
| Started | Jun 23 08:18:28 PM PDT 24 |
| Finished | Jun 23 08:28:59 PM PDT 24 |
| Peak memory | 614064 kb |
| Host | smart-3ee5ce95-8d85-4deb-9569-056c553c2cc0 |
| User | root |
| Command | /workspace/default/simv +uart_idx=2 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2599794931 -a ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/default.vdb -cm_log /dev/null -cm_name 4.chip_sw_uart_tx_rx_idx2.2599794931 |
| Directory | /workspace/4.chip_sw_uart_tx_rx_idx2/latest |
| Test location | /workspace/coverage/cover_reg_top/29.xbar_stress_all_with_rand_reset.623442364 |
| Short name | T544 |
| Test name | |
| Test status | |
| Simulation time | 7242222554 ps |
| CPU time | 528.65 seconds |
| Started | Jun 23 07:28:39 PM PDT 24 |
| Finished | Jun 23 07:37:28 PM PDT 24 |
| Peak memory | 576372 kb |
| Host | smart-8689965c-49f4-4a30-afd1-6e4d0440d160 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=623442364 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_res et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.xbar_stress_all_ with_rand_reset.623442364 |
| Directory | /workspace/29.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/0.chip_sw_sleep_pin_wake.1285471188 |
| Short name | T17 |
| Test name | |
| Test status | |
| Simulation time | 3342690392 ps |
| CPU time | 237.57 seconds |
| Started | Jun 23 07:48:33 PM PDT 24 |
| Finished | Jun 23 07:52:32 PM PDT 24 |
| Peak memory | 606988 kb |
| Host | smart-64c13a6a-d2ac-42f3-96b5-cdd881495377 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStProd +sw_build_device=sim_dv +sw_images=sleep_pin_wake_test:1:new_rules,test_rom:0 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1285471188 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sleep_pin_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_sleep_pin_wake.1285471188 |
| Directory | /workspace/0.chip_sw_sleep_pin_wake/latest |
| Test location | /workspace/coverage/default/17.chip_sw_all_escalation_resets.2983295245 |
| Short name | T5 |
| Test name | |
| Test status | |
| Simulation time | 5038122236 ps |
| CPU time | 542.66 seconds |
| Started | Jun 23 08:18:53 PM PDT 24 |
| Finished | Jun 23 08:27:56 PM PDT 24 |
| Peak memory | 648084 kb |
| Host | smart-d6305d7b-c6cc-4e4c-9394-f4e5512896dc |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 2983295245 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.chip_sw_all_escalation_resets.2983295245 |
| Directory | /workspace/17.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/cover_reg_top/4.chip_tl_errors.698645019 |
| Short name | T702 |
| Test name | |
| Test status | |
| Simulation time | 5071771446 ps |
| CPU time | 459.6 seconds |
| Started | Jun 23 07:21:27 PM PDT 24 |
| Finished | Jun 23 07:29:06 PM PDT 24 |
| Peak memory | 596356 kb |
| Host | smart-c16b6bee-f39e-4cf9-af90-846c821d1e73 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=698645019 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.chip_tl_errors.698645019 |
| Directory | /workspace/4.chip_tl_errors/latest |
| Test location | /workspace/coverage/default/1.chip_plic_all_irqs_0.1361554494 |
| Short name | T322 |
| Test name | |
| Test status | |
| Simulation time | 6190159480 ps |
| CPU time | 1264.01 seconds |
| Started | Jun 23 08:01:00 PM PDT 24 |
| Finished | Jun 23 08:22:05 PM PDT 24 |
| Peak memory | 607820 kb |
| Host | smart-3a88e037-0030-4d33-a14b-ae10e58d552a |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=plic_all_irqs_test_0:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1361554494 -assert nopostproc +UVM_TESTNA ME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 1.chip_plic_all_irqs_0.1361554494 |
| Directory | /workspace/1.chip_plic_all_irqs_0/latest |
| Test location | /workspace/coverage/cover_reg_top/30.xbar_stress_all_with_rand_reset.3774914312 |
| Short name | T444 |
| Test name | |
| Test status | |
| Simulation time | 2031818179 ps |
| CPU time | 357.97 seconds |
| Started | Jun 23 07:28:56 PM PDT 24 |
| Finished | Jun 23 07:34:55 PM PDT 24 |
| Peak memory | 574256 kb |
| Host | smart-47406f31-24f6-4e1f-a8b0-a19b7b4608c7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3774914312 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.xbar_stress_all _with_rand_reset.3774914312 |
| Directory | /workspace/30.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/0.chip_sw_sensor_ctrl_alert.2836231831 |
| Short name | T132 |
| Test name | |
| Test status | |
| Simulation time | 7313708186 ps |
| CPU time | 956.77 seconds |
| Started | Jun 23 07:50:53 PM PDT 24 |
| Finished | Jun 23 08:06:50 PM PDT 24 |
| Peak memory | 608464 kb |
| Host | smart-f514a1ab-9dfb-4b21-8a18-9c3e4257961c |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=40_000_000 +sw_build_device=sim_dv +sw_images=sensor_ctrl_alert_test:1:new_rules,test_rom:0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28362318 31 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac e/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_sensor_ctrl_alert.2836231831 |
| Directory | /workspace/0.chip_sw_sensor_ctrl_alert/latest |
| Test location | /workspace/coverage/default/3.chip_sw_sensor_ctrl_alert.4037338814 |
| Short name | T133 |
| Test name | |
| Test status | |
| Simulation time | 5132628904 ps |
| CPU time | 552.76 seconds |
| Started | Jun 23 08:18:15 PM PDT 24 |
| Finished | Jun 23 08:27:28 PM PDT 24 |
| Peak memory | 607444 kb |
| Host | smart-4b25980a-7623-4153-aab8-b16f2c1a2bc1 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=40_000_000 +sw_build_device=sim_dv +sw_images=sensor_ctrl_alert_test:1:new_rules,test_rom:0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40373388 14 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac e/coverage/default.vdb -cm_log /dev/null -cm_name 3.chip_sw_sensor_ctrl_alert.4037338814 |
| Directory | /workspace/3.chip_sw_sensor_ctrl_alert/latest |
| Test location | /workspace/coverage/cover_reg_top/88.xbar_stress_all_with_rand_reset.2978446638 |
| Short name | T447 |
| Test name | |
| Test status | |
| Simulation time | 5799225906 ps |
| CPU time | 742.7 seconds |
| Started | Jun 23 07:39:23 PM PDT 24 |
| Finished | Jun 23 07:51:46 PM PDT 24 |
| Peak memory | 574288 kb |
| Host | smart-e29f2207-c339-4cb7-8c19-a41d7c40654e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2978446638 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 88.xbar_stress_all _with_rand_reset.2978446638 |
| Directory | /workspace/88.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/2.chip_plic_all_irqs_20.2084085949 |
| Short name | T312 |
| Test name | |
| Test status | |
| Simulation time | 5118765980 ps |
| CPU time | 974.04 seconds |
| Started | Jun 23 08:12:10 PM PDT 24 |
| Finished | Jun 23 08:28:24 PM PDT 24 |
| Peak memory | 606928 kb |
| Host | smart-551efea6-0498-4f00-8f05-a35bd3786033 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=plic_all_irqs_test_20:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2084085949 -assert nopostproc +UVM_TESTN AME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log / dev/null -cm_name 2.chip_plic_all_irqs_20.2084085949 |
| Directory | /workspace/2.chip_plic_all_irqs_20/latest |
| Test location | /workspace/coverage/default/0.chip_sw_otp_ctrl_vendor_test_csr_access.2491310126 |
| Short name | T157 |
| Test name | |
| Test status | |
| Simulation time | 3100276298 ps |
| CPU time | 252.98 seconds |
| Started | Jun 23 07:51:57 PM PDT 24 |
| Finished | Jun 23 07:56:11 PM PDT 24 |
| Peak memory | 615276 kb |
| Host | smart-15e90fdc-257b-4747-8e99-89ff4d793a01 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=otp_ctrl_vendor_test_csr_access_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2491310126 -assert nopost proc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_otp_ctrl_vendor_test_csr_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_otp_ctrl_vendor_test_csr_access.2491310126 |
| Directory | /workspace/0.chip_sw_otp_ctrl_vendor_test_csr_access/latest |
| Test location | /workspace/coverage/cover_reg_top/38.xbar_stress_all_with_rand_reset.1312950101 |
| Short name | T484 |
| Test name | |
| Test status | |
| Simulation time | 5204545946 ps |
| CPU time | 405.29 seconds |
| Started | Jun 23 07:30:41 PM PDT 24 |
| Finished | Jun 23 07:37:27 PM PDT 24 |
| Peak memory | 576364 kb |
| Host | smart-210ef1eb-faa9-40d1-88c0-481b518bca7e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1312950101 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.xbar_stress_all _with_rand_reset.1312950101 |
| Directory | /workspace/38.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/0.chip_sw_lc_walkthrough_dev.670487943 |
| Short name | T229 |
| Test name | |
| Test status | |
| Simulation time | 47807262488 ps |
| CPU time | 5439.41 seconds |
| Started | Jun 23 07:52:04 PM PDT 24 |
| Finished | Jun 23 09:22:45 PM PDT 24 |
| Peak memory | 617132 kb |
| Host | smart-68d45d25-d680-4df7-8231-1ef3be35cd8f |
| User | root |
| Command | /workspace/default/simv +flash_program_latency=5 +use_otp_image=OtpTypeLcStRaw +dest_dec_state=DecLcStDev +sw_test_timeout_ns=200_000_000 +sw_build_de vice=sim_dv +sw_images=lc_walkthrough_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=670487943 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=ch ip_sw_lc_walkthrough_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_ sw_lc_walkthrough_dev.670487943 |
| Directory | /workspace/0.chip_sw_lc_walkthrough_dev/latest |
| Test location | /workspace/coverage/default/1.chip_plic_all_irqs_10.2895396233 |
| Short name | T154 |
| Test name | |
| Test status | |
| Simulation time | 3891958476 ps |
| CPU time | 507.75 seconds |
| Started | Jun 23 08:01:11 PM PDT 24 |
| Finished | Jun 23 08:09:39 PM PDT 24 |
| Peak memory | 606880 kb |
| Host | smart-b24250cc-475a-483b-9e3c-bf30810be34c |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=plic_all_irqs_test_10:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2895396233 -assert nopostproc +UVM_TESTN AME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log / dev/null -cm_name 1.chip_plic_all_irqs_10.2895396233 |
| Directory | /workspace/1.chip_plic_all_irqs_10/latest |
| Test location | /workspace/coverage/cover_reg_top/63.xbar_stress_all_with_reset_error.3366078983 |
| Short name | T886 |
| Test name | |
| Test status | |
| Simulation time | 11567600717 ps |
| CPU time | 569.63 seconds |
| Started | Jun 23 07:35:11 PM PDT 24 |
| Finished | Jun 23 07:44:41 PM PDT 24 |
| Peak memory | 574300 kb |
| Host | smart-b70362f9-59e3-45cc-98d3-1e22f54247cd |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3366078983 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 63.xbar_stress_al l_with_reset_error.3366078983 |
| Directory | /workspace/63.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/17.xbar_stress_all.3290409088 |
| Short name | T1887 |
| Test name | |
| Test status | |
| Simulation time | 4413390563 ps |
| CPU time | 397.26 seconds |
| Started | Jun 23 07:25:27 PM PDT 24 |
| Finished | Jun 23 07:32:05 PM PDT 24 |
| Peak memory | 574300 kb |
| Host | smart-1fad6cc9-b61b-410b-9df5-d71099567ce4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3290409088 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.xbar_stress_all.3290409088 |
| Directory | /workspace/17.xbar_stress_all/latest |
| Test location | /workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_slow_rma.3104754838 |
| Short name | T58 |
| Test name | |
| Test status | |
| Simulation time | 4484333736 ps |
| CPU time | 643.67 seconds |
| Started | Jun 23 07:50:52 PM PDT 24 |
| Finished | Jun 23 08:01:36 PM PDT 24 |
| Peak memory | 611500 kb |
| Host | smart-d4c9ae64-0140-4a05-8bc3-929b0289a0ea |
| User | root |
| Command | /workspace/default/simv +chip_clock_source=ChipClockSourceExternal48Mhz +calibrate_usb_clk=1 +src_dec_state=DecLcStRma +sw_build_device=sim_dv +sw_ima ges=clkmgr_external_clk_src_for_sw_slow_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3104754838 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ =chip_sw_lc_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_c lkmgr_external_clk_src_for_sw_slow_rma.3104754838 |
| Directory | /workspace/0.chip_sw_clkmgr_external_clk_src_for_sw_slow_rma/latest |
| Test location | /workspace/coverage/default/28.chip_sw_all_escalation_resets.1023854295 |
| Short name | T396 |
| Test name | |
| Test status | |
| Simulation time | 4909545008 ps |
| CPU time | 480.01 seconds |
| Started | Jun 23 08:21:36 PM PDT 24 |
| Finished | Jun 23 08:29:36 PM PDT 24 |
| Peak memory | 647932 kb |
| Host | smart-b969bff2-691d-43e0-bf95-d5b67f09caeb |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 1023854295 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.chip_sw_all_escalation_resets.1023854295 |
| Directory | /workspace/28.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/cover_reg_top/3.xbar_stress_all_with_rand_reset.3198788888 |
| Short name | T531 |
| Test name | |
| Test status | |
| Simulation time | 6779210489 ps |
| CPU time | 531.08 seconds |
| Started | Jun 23 07:21:22 PM PDT 24 |
| Finished | Jun 23 07:30:13 PM PDT 24 |
| Peak memory | 574316 kb |
| Host | smart-42f52ead-c5e9-4d88-b8f0-eceab664220c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3198788888 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.xbar_stress_all_ with_rand_reset.3198788888 |
| Directory | /workspace/3.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/64.xbar_access_same_device_slow_rsp.510727656 |
| Short name | T461 |
| Test name | |
| Test status | |
| Simulation time | 157568753712 ps |
| CPU time | 2896.88 seconds |
| Started | Jun 23 07:35:21 PM PDT 24 |
| Finished | Jun 23 08:23:39 PM PDT 24 |
| Peak memory | 574256 kb |
| Host | smart-efaba20c-341b-498d-9167-dd804de506a0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=510727656 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 64.xbar_access_same_d evice_slow_rsp.510727656 |
| Directory | /workspace/64.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/default/1.chip_sw_flash_ctrl_ops_jitter_en_reduced_freq.2654478397 |
| Short name | T341 |
| Test name | |
| Test status | |
| Simulation time | 4112057960 ps |
| CPU time | 721.31 seconds |
| Started | Jun 23 08:04:04 PM PDT 24 |
| Finished | Jun 23 08:16:05 PM PDT 24 |
| Peak memory | 607816 kb |
| Host | smart-fd6a3ab3-6100-4468-b6a9-b1beddb76b0f |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=50_000_000 +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=flash_ctrl_ops_test:1:new_ rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si m.tcl +ntb_random_seed=2654478397 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_flash_ctrl_ops_jitter_en_reduced_freq.2654478397 |
| Directory | /workspace/1.chip_sw_flash_ctrl_ops_jitter_en_reduced_freq/latest |
| Test location | /workspace/coverage/cover_reg_top/2.chip_csr_hw_reset.3316610752 |
| Short name | T127 |
| Test name | |
| Test status | |
| Simulation time | 3685738270 ps |
| CPU time | 181.63 seconds |
| Started | Jun 23 07:21:17 PM PDT 24 |
| Finished | Jun 23 07:24:19 PM PDT 24 |
| Peak memory | 661628 kb |
| Host | smart-44377016-eff2-4cc9-adc3-4158cc6df129 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3316610752 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.chip_csr_hw_r eset.3316610752 |
| Directory | /workspace/2.chip_csr_hw_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/1.xbar_stress_all_with_reset_error.212379697 |
| Short name | T895 |
| Test name | |
| Test status | |
| Simulation time | 1066774312 ps |
| CPU time | 249.4 seconds |
| Started | Jun 23 07:21:12 PM PDT 24 |
| Finished | Jun 23 07:25:22 PM PDT 24 |
| Peak memory | 574324 kb |
| Host | smart-aeeda1a9-d3c3-44b3-89db-70418cc005d6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=212379697 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.xbar_stress_all_ with_reset_error.212379697 |
| Directory | /workspace/1.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/default/0.chip_sw_sram_ctrl_execution_main.3807038759 |
| Short name | T300 |
| Test name | |
| Test status | |
| Simulation time | 7631932061 ps |
| CPU time | 856.86 seconds |
| Started | Jun 23 07:50:55 PM PDT 24 |
| Finished | Jun 23 08:05:12 PM PDT 24 |
| Peak memory | 608136 kb |
| Host | smart-1299c6bd-ec95-4319-be48-a2cf17e85cba |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=sram_ctrl_execution_main_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3807038759 -assert nopostproc +U VM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sram_ctrl_execution_main_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co verage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_sram_ctrl_execution_main.3807038759 |
| Directory | /workspace/0.chip_sw_sram_ctrl_execution_main/latest |
| Test location | /workspace/coverage/default/0.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted.2863734810 |
| Short name | T357 |
| Test name | |
| Test status | |
| Simulation time | 4623328728 ps |
| CPU time | 514.75 seconds |
| Started | Jun 23 07:53:16 PM PDT 24 |
| Finished | Jun 23 08:01:51 PM PDT 24 |
| Peak memory | 615264 kb |
| Host | smart-57d7d8eb-621e-459e-9bff-e3ac40136944 |
| User | root |
| Command | /workspace/default/simv +use_jtag_dmi=1 +sw_build_device=sim_dv +sw_images=rv_dm_ndm_reset_req_when_cpu_halted_rma:1:new_rules,test_rom:0 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=286373 4810 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rv_dm_ndm_reset_when_cpu_halted_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted.2863734810 |
| Directory | /workspace/0.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted/latest |
| Test location | /workspace/coverage/cover_reg_top/2.chip_same_csr_outstanding.20969733 |
| Short name | T391 |
| Test name | |
| Test status | |
| Simulation time | 29600297294 ps |
| CPU time | 3946.33 seconds |
| Started | Jun 23 07:21:08 PM PDT 24 |
| Finished | Jun 23 08:26:55 PM PDT 24 |
| Peak memory | 591172 kb |
| Host | smart-c28f143b-6856-42bd-a446-0192bd874186 |
| User | root |
| Command | /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +run_same_csr_outstanding +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20969733 -assert nopostproc +UVM_TEST NAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm _log /dev/null -cm_name 2.chip_same_csr_outstanding.20969733 |
| Directory | /workspace/2.chip_same_csr_outstanding/latest |
| Test location | /workspace/coverage/default/0.chip_sw_entropy_src_csrng.1895538472 |
| Short name | T304 |
| Test name | |
| Test status | |
| Simulation time | 6193859496 ps |
| CPU time | 1458.96 seconds |
| Started | Jun 23 07:51:17 PM PDT 24 |
| Finished | Jun 23 08:15:37 PM PDT 24 |
| Peak memory | 607304 kb |
| Host | smart-9f28dc68-ed9c-4be4-a8b8-563c322e59bb |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=50_000_000 +rng_srate_value_min=15 +rng_srate_value_max=30 +sw_build_device=sim_dv +sw_images=entropy_src_ csrng_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1895538472 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_entropy_src_csrng.1895538472 |
| Directory | /workspace/0.chip_sw_entropy_src_csrng/latest |
| Test location | /workspace/coverage/default/0.chip_sw_gpio.832503055 |
| Short name | T40 |
| Test name | |
| Test status | |
| Simulation time | 3782581620 ps |
| CPU time | 542.53 seconds |
| Started | Jun 23 07:50:07 PM PDT 24 |
| Finished | Jun 23 07:59:10 PM PDT 24 |
| Peak memory | 606964 kb |
| Host | smart-4ef9fe9e-1170-4d1b-8a9a-a67cd102df58 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=gpio_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=832503055 -assert nopostproc +UVM_TESTNAME=chip_base _test +UVM_TEST_SEQ=chip_sw_gpio_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 0.chip_sw_gpio.832503055 |
| Directory | /workspace/0.chip_sw_gpio/latest |
| Test location | /workspace/coverage/default/0.chip_sw_uart_tx_rx.886637274 |
| Short name | T1032 |
| Test name | |
| Test status | |
| Simulation time | 3719590568 ps |
| CPU time | 541.49 seconds |
| Started | Jun 23 07:48:05 PM PDT 24 |
| Finished | Jun 23 07:57:07 PM PDT 24 |
| Peak memory | 614996 kb |
| Host | smart-e7b9f84f-a4c5-4a84-b797-a3486122d836 |
| User | root |
| Command | /workspace/default/simv +uart_idx=0 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=886637274 -as sert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac e/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_uart_tx_rx.886637274 |
| Directory | /workspace/0.chip_sw_uart_tx_rx/latest |
| Test location | /workspace/coverage/default/1.chip_plic_all_irqs_20.3399992839 |
| Short name | T314 |
| Test name | |
| Test status | |
| Simulation time | 4994739000 ps |
| CPU time | 778.65 seconds |
| Started | Jun 23 08:01:21 PM PDT 24 |
| Finished | Jun 23 08:14:20 PM PDT 24 |
| Peak memory | 606936 kb |
| Host | smart-9e2c24c6-ba47-4736-af26-a7494f799c40 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=plic_all_irqs_test_20:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3399992839 -assert nopostproc +UVM_TESTN AME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log / dev/null -cm_name 1.chip_plic_all_irqs_20.3399992839 |
| Directory | /workspace/1.chip_plic_all_irqs_20/latest |
| Test location | /workspace/coverage/default/2.chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up.3569693352 |
| Short name | T121 |
| Test name | |
| Test status | |
| Simulation time | 6133285520 ps |
| CPU time | 369.74 seconds |
| Started | Jun 23 08:14:21 PM PDT 24 |
| Finished | Jun 23 08:20:31 PM PDT 24 |
| Peak memory | 608712 kb |
| Host | smart-f6c72472-09f0-4630-8fc0-12495c2c207f |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +do_random=1 +sw_build_device=sim_dv +sw_images=pwrmgr_sensor_ctrl_deep_sleep_wake_up:1:new_rul es,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t cl +ntb_random_seed=3569693352 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_sensor_ctrl_deep_s leep_wake_up.3569693352 |
| Directory | /workspace/2.chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up/latest |
| Test location | /workspace/coverage/default/53.chip_sw_all_escalation_resets.4264518190 |
| Short name | T753 |
| Test name | |
| Test status | |
| Simulation time | 5198366550 ps |
| CPU time | 519.02 seconds |
| Started | Jun 23 08:22:05 PM PDT 24 |
| Finished | Jun 23 08:30:45 PM PDT 24 |
| Peak memory | 648040 kb |
| Host | smart-a0728eec-f488-499d-9b0c-df1e7f017c7e |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 4264518190 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.chip_sw_all_escalation_resets.4264518190 |
| Directory | /workspace/53.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/1.chip_sw_otp_ctrl_vendor_test_csr_access.4137467222 |
| Short name | T158 |
| Test name | |
| Test status | |
| Simulation time | 1735400771 ps |
| CPU time | 104.47 seconds |
| Started | Jun 23 07:56:47 PM PDT 24 |
| Finished | Jun 23 07:58:32 PM PDT 24 |
| Peak memory | 614300 kb |
| Host | smart-232d2b74-5fca-493c-a156-256f91bc5ef9 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=otp_ctrl_vendor_test_csr_access_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4137467222 -assert nopost proc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_otp_ctrl_vendor_test_csr_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_otp_ctrl_vendor_test_csr_access.4137467222 |
| Directory | /workspace/1.chip_sw_otp_ctrl_vendor_test_csr_access/latest |
| Test location | /workspace/coverage/default/0.chip_sw_plic_sw_irq.2233088734 |
| Short name | T242 |
| Test name | |
| Test status | |
| Simulation time | 2703449780 ps |
| CPU time | 221.46 seconds |
| Started | Jun 23 07:50:34 PM PDT 24 |
| Finished | Jun 23 07:54:15 PM PDT 24 |
| Peak memory | 606868 kb |
| Host | smart-ac80668b-68d8-4054-aae5-1074cd0bbd55 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=plic_sw_irq_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2233088734 -assert nopostproc +UVM_TESTNAME=c hip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n ull -cm_name 0.chip_sw_plic_sw_irq.2233088734 |
| Directory | /workspace/0.chip_sw_plic_sw_irq/latest |
| Test location | /workspace/coverage/default/39.chip_sw_all_escalation_resets.3813788762 |
| Short name | T836 |
| Test name | |
| Test status | |
| Simulation time | 4442019740 ps |
| CPU time | 573.14 seconds |
| Started | Jun 23 08:20:44 PM PDT 24 |
| Finished | Jun 23 08:30:17 PM PDT 24 |
| Peak memory | 647636 kb |
| Host | smart-5fd53b5b-879c-40db-9904-04138ac44e85 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 3813788762 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.chip_sw_all_escalation_resets.3813788762 |
| Directory | /workspace/39.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/0.chip_sw_hmac_enc_jitter_en.1230851247 |
| Short name | T19 |
| Test name | |
| Test status | |
| Simulation time | 3377737114 ps |
| CPU time | 308.22 seconds |
| Started | Jun 23 07:50:52 PM PDT 24 |
| Finished | Jun 23 07:56:01 PM PDT 24 |
| Peak memory | 607668 kb |
| Host | smart-b17e409e-e55f-4fc8-84a6-68c9f50b62fa |
| User | root |
| Command | /workspace/default/simv +en_jitter=1 +sw_build_device=sim_dv +sw_images=hmac_enc_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1230851247 -assert nopostproc +UVM_ TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_ log /dev/null -cm_name 0.chip_sw_hmac_enc_jitter_en.1230851247 |
| Directory | /workspace/0.chip_sw_hmac_enc_jitter_en/latest |
| Test location | /workspace/coverage/default/2.chip_sw_rv_dm_access_after_escalation_reset.2651594479 |
| Short name | T57 |
| Test name | |
| Test status | |
| Simulation time | 4480819249 ps |
| CPU time | 671.17 seconds |
| Started | Jun 23 08:14:03 PM PDT 24 |
| Finished | Jun 23 08:25:15 PM PDT 24 |
| Peak memory | 617964 kb |
| Host | smart-acb50ebd-0a17-45f0-bf88-ad43d17b3372 |
| User | root |
| Command | /workspace/default/simv +use_jtag_dmi=1 +sw_build_device=sim_dv +sw_images=alert_handler_escalation_test:1:new_rules,test_rom:0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2651594479 -asse rt nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rv_dm_access_after_escalation_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_rv_dm_access_after_escalation_reset.2651594479 |
| Directory | /workspace/2.chip_sw_rv_dm_access_after_escalation_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/2.xbar_stress_all_with_rand_reset.3298260086 |
| Short name | T452 |
| Test name | |
| Test status | |
| Simulation time | 6746347659 ps |
| CPU time | 367.82 seconds |
| Started | Jun 23 07:21:13 PM PDT 24 |
| Finished | Jun 23 07:27:21 PM PDT 24 |
| Peak memory | 574172 kb |
| Host | smart-9ead3ed8-d137-4235-aa89-12cf2acbbefc |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3298260086 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.xbar_stress_all_ with_rand_reset.3298260086 |
| Directory | /workspace/2.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/1.chip_sw_flash_ctrl_ops.1602644174 |
| Short name | T329 |
| Test name | |
| Test status | |
| Simulation time | 3884174850 ps |
| CPU time | 682.35 seconds |
| Started | Jun 23 07:56:30 PM PDT 24 |
| Finished | Jun 23 08:07:52 PM PDT 24 |
| Peak memory | 607856 kb |
| Host | smart-d19d869c-4b25-45ad-a48c-0f4d9c15b094 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=50_000_000 +sw_build_device=sim_dv +sw_images=flash_ctrl_ops_test:1:new_rules,test_rom:0 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1602644174 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/c overage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_flash_ctrl_ops.1602644174 |
| Directory | /workspace/1.chip_sw_flash_ctrl_ops/latest |
| Test location | /workspace/coverage/default/2.chip_plic_all_irqs_10.4250801672 |
| Short name | T153 |
| Test name | |
| Test status | |
| Simulation time | 4438778150 ps |
| CPU time | 582 seconds |
| Started | Jun 23 08:12:26 PM PDT 24 |
| Finished | Jun 23 08:22:08 PM PDT 24 |
| Peak memory | 606844 kb |
| Host | smart-d04f298f-631f-4790-9acd-9c7d4155746a |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=plic_all_irqs_test_10:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4250801672 -assert nopostproc +UVM_TESTN AME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log / dev/null -cm_name 2.chip_plic_all_irqs_10.4250801672 |
| Directory | /workspace/2.chip_plic_all_irqs_10/latest |
| Test location | /workspace/coverage/default/0.chip_sw_flash_rma_unlocked.4243746210 |
| Short name | T179 |
| Test name | |
| Test status | |
| Simulation time | 44948653016 ps |
| CPU time | 5161.36 seconds |
| Started | Jun 23 07:48:22 PM PDT 24 |
| Finished | Jun 23 09:14:24 PM PDT 24 |
| Peak memory | 618100 kb |
| Host | smart-f598eaaf-f917-46dd-a620-c61c8c3a3c5e |
| User | root |
| Command | /workspace/default/simv +flash_program_latency=5 +sw_test_timeout_ns=150_000_000 +sw_build_device=sim_dv +sw_images=flash_rma_unlocked_test:0:test_in_ rom:new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t cl +ntb_random_seed=4243746210 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_flash_rma_unlocked_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_flash_rma_unlocked.4243746210 |
| Directory | /workspace/0.chip_sw_flash_rma_unlocked/latest |
| Test location | /workspace/coverage/default/0.chip_sw_lc_walkthrough_prod.139034753 |
| Short name | T168 |
| Test name | |
| Test status | |
| Simulation time | 51131218085 ps |
| CPU time | 5635.42 seconds |
| Started | Jun 23 07:49:22 PM PDT 24 |
| Finished | Jun 23 09:23:19 PM PDT 24 |
| Peak memory | 614356 kb |
| Host | smart-e0d22c71-b0be-4fdc-bd63-56a2ed89ff48 |
| User | root |
| Command | /workspace/default/simv +flash_program_latency=5 +use_otp_image=OtpTypeLcStRaw +dest_dec_state=DecLcStProd +sw_test_timeout_ns=200_000_000 +sw_build_d evice=sim_dv +sw_images=lc_walkthrough_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=139034753 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=c hip_sw_lc_walkthrough_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip _sw_lc_walkthrough_prod.139034753 |
| Directory | /workspace/0.chip_sw_lc_walkthrough_prod/latest |
| Test location | /workspace/coverage/default/0.chip_sw_usbdev_config_host.411542874 |
| Short name | T34 |
| Test name | |
| Test status | |
| Simulation time | 7865370134 ps |
| CPU time | 1931.14 seconds |
| Started | Jun 23 07:49:00 PM PDT 24 |
| Finished | Jun 23 08:21:12 PM PDT 24 |
| Peak memory | 607836 kb |
| Host | smart-3153b641-22fd-401e-adb0-20cb899ad0bd |
| User | root |
| Command | /workspace/default/simv +uart_idx=0 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=usbdev_config_host_test:1:new_rules,test_rom:0 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41154 2874 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_usbdev_dpi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_usbdev_config_host.411542874 |
| Directory | /workspace/0.chip_sw_usbdev_config_host/latest |
| Test location | /workspace/coverage/default/0.chip_sw_i2c_host_tx_rx_idx2.2036270891 |
| Short name | T323 |
| Test name | |
| Test status | |
| Simulation time | 4576761976 ps |
| CPU time | 698.8 seconds |
| Started | Jun 23 07:48:55 PM PDT 24 |
| Finished | Jun 23 08:00:34 PM PDT 24 |
| Peak memory | 608008 kb |
| Host | smart-e8db2e60-6ff7-480c-aa0d-28f11dd499bf |
| User | root |
| Command | /workspace/default/simv +i2c_idx=2 +sw_build_device=sim_dv +sw_images=i2c_host_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2036270891 -assert nopostproc + UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_i2c_host_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de fault.vdb -cm_log /dev/null -cm_name 0.chip_sw_i2c_host_tx_rx_idx2.2036270891 |
| Directory | /workspace/0.chip_sw_i2c_host_tx_rx_idx2/latest |
| Test location | /workspace/coverage/default/1.chip_sw_i2c_host_tx_rx.227976469 |
| Short name | T207 |
| Test name | |
| Test status | |
| Simulation time | 5773374720 ps |
| CPU time | 857.88 seconds |
| Started | Jun 23 07:54:26 PM PDT 24 |
| Finished | Jun 23 08:08:45 PM PDT 24 |
| Peak memory | 608024 kb |
| Host | smart-12f3d2fe-1d5c-4b80-8cfb-5c85f3b36eee |
| User | root |
| Command | /workspace/default/simv +i2c_idx=0 +sw_build_device=sim_dv +sw_images=i2c_host_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=227976469 -assert nopostproc +U VM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_i2c_host_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def ault.vdb -cm_log /dev/null -cm_name 1.chip_sw_i2c_host_tx_rx.227976469 |
| Directory | /workspace/1.chip_sw_i2c_host_tx_rx/latest |
| Test location | /workspace/coverage/default/0.chip_sw_pattgen_ios.1972312358 |
| Short name | T409 |
| Test name | |
| Test status | |
| Simulation time | 3279147516 ps |
| CPU time | 345.17 seconds |
| Started | Jun 23 07:48:28 PM PDT 24 |
| Finished | Jun 23 07:54:15 PM PDT 24 |
| Peak memory | 608344 kb |
| Host | smart-aa405f2b-ab7c-4449-a904-7a512dfae150 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=5_000_000 +sw_build_device=sim_dv +sw_images=pattgen_ios_test:1:new_rules,test_rom:0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1972312358 -ass ert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_patt_ios_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/c overage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pattgen_ios.1972312358 |
| Directory | /workspace/0.chip_sw_pattgen_ios/latest |
| Test location | /workspace/coverage/cover_reg_top/11.xbar_stress_all_with_reset_error.3142317555 |
| Short name | T601 |
| Test name | |
| Test status | |
| Simulation time | 15681546548 ps |
| CPU time | 787.12 seconds |
| Started | Jun 23 07:23:35 PM PDT 24 |
| Finished | Jun 23 07:36:43 PM PDT 24 |
| Peak memory | 574340 kb |
| Host | smart-09c72f69-a9d1-4e70-973e-a02ea28aefe4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3142317555 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.xbar_stress_al l_with_reset_error.3142317555 |
| Directory | /workspace/11.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/19.chip_tl_errors.3364708103 |
| Short name | T721 |
| Test name | |
| Test status | |
| Simulation time | 4056288143 ps |
| CPU time | 327.13 seconds |
| Started | Jun 23 07:26:00 PM PDT 24 |
| Finished | Jun 23 07:31:27 PM PDT 24 |
| Peak memory | 601556 kb |
| Host | smart-baa2a9e0-f3eb-4a71-8a57-8d6e8924235b |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3364708103 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.chip_tl_errors.3364708103 |
| Directory | /workspace/19.chip_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/20.xbar_stress_all_with_reset_error.792414194 |
| Short name | T1505 |
| Test name | |
| Test status | |
| Simulation time | 319253934 ps |
| CPU time | 200.01 seconds |
| Started | Jun 23 07:26:34 PM PDT 24 |
| Finished | Jun 23 07:29:54 PM PDT 24 |
| Peak memory | 575304 kb |
| Host | smart-40fc79b4-f9e9-46a4-a889-c85135923008 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=792414194 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.xbar_stress_all _with_reset_error.792414194 |
| Directory | /workspace/20.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/default/0.chip_sw_alert_handler_lpg_sleep_mode_alerts.1996867590 |
| Short name | T768 |
| Test name | |
| Test status | |
| Simulation time | 3614271818 ps |
| CPU time | 455.02 seconds |
| Started | Jun 23 07:50:43 PM PDT 24 |
| Finished | Jun 23 07:58:19 PM PDT 24 |
| Peak memory | 642860 kb |
| Host | smart-4f070675-a2c2-4cd7-ad23-f87e3a4062e4 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1996867590 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_s w_alert_handler_lpg_sleep_mode_alerts.1996867590 |
| Directory | /workspace/0.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/0.chip_sw_all_escalation_resets.2220271400 |
| Short name | T801 |
| Test name | |
| Test status | |
| Simulation time | 5690693644 ps |
| CPU time | 738.94 seconds |
| Started | Jun 23 07:49:40 PM PDT 24 |
| Finished | Jun 23 08:02:00 PM PDT 24 |
| Peak memory | 648088 kb |
| Host | smart-2a1de5f3-e54e-4de8-b7db-1bff23eece50 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 2220271400 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_all_escalation_resets.2220271400 |
| Directory | /workspace/0.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/1.chip_sw_alert_handler_lpg_sleep_mode_alerts.94757292 |
| Short name | T711 |
| Test name | |
| Test status | |
| Simulation time | 3870948956 ps |
| CPU time | 430.42 seconds |
| Started | Jun 23 07:57:35 PM PDT 24 |
| Finished | Jun 23 08:04:45 PM PDT 24 |
| Peak memory | 642408 kb |
| Host | smart-931b29ea-e84d-46b7-bac3-e3b5372648e4 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94757292 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_ escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_ alert_handler_lpg_sleep_mode_alerts.94757292 |
| Directory | /workspace/1.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/10.chip_sw_alert_handler_lpg_sleep_mode_alerts.2462464434 |
| Short name | T1261 |
| Test name | |
| Test status | |
| Simulation time | 3206063032 ps |
| CPU time | 434.2 seconds |
| Started | Jun 23 08:21:00 PM PDT 24 |
| Finished | Jun 23 08:28:14 PM PDT 24 |
| Peak memory | 642448 kb |
| Host | smart-0626d090-7579-4806-9dd1-3a45cacb32fe |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2462464434 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.chip_ sw_alert_handler_lpg_sleep_mode_alerts.2462464434 |
| Directory | /workspace/10.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/10.chip_sw_all_escalation_resets.2354238969 |
| Short name | T788 |
| Test name | |
| Test status | |
| Simulation time | 5389787150 ps |
| CPU time | 719.69 seconds |
| Started | Jun 23 08:20:35 PM PDT 24 |
| Finished | Jun 23 08:32:35 PM PDT 24 |
| Peak memory | 648032 kb |
| Host | smart-6668d1e6-914b-43a2-bd9f-a967eb7a590e |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 2354238969 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.chip_sw_all_escalation_resets.2354238969 |
| Directory | /workspace/10.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/11.chip_sw_alert_handler_lpg_sleep_mode_alerts.1470156751 |
| Short name | T690 |
| Test name | |
| Test status | |
| Simulation time | 4078171920 ps |
| CPU time | 424.53 seconds |
| Started | Jun 23 08:18:46 PM PDT 24 |
| Finished | Jun 23 08:25:51 PM PDT 24 |
| Peak memory | 642700 kb |
| Host | smart-6fa8a81b-bede-4984-a29f-e328ca6760e4 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1470156751 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.chip_ sw_alert_handler_lpg_sleep_mode_alerts.1470156751 |
| Directory | /workspace/11.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/12.chip_sw_alert_handler_lpg_sleep_mode_alerts.1985500727 |
| Short name | T830 |
| Test name | |
| Test status | |
| Simulation time | 4248926056 ps |
| CPU time | 473.55 seconds |
| Started | Jun 23 08:20:53 PM PDT 24 |
| Finished | Jun 23 08:28:47 PM PDT 24 |
| Peak memory | 642672 kb |
| Host | smart-4676a66e-35a0-4d46-ae85-9bedee0c349b |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1985500727 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.chip_ sw_alert_handler_lpg_sleep_mode_alerts.1985500727 |
| Directory | /workspace/12.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/13.chip_sw_alert_handler_lpg_sleep_mode_alerts.2454990399 |
| Short name | T795 |
| Test name | |
| Test status | |
| Simulation time | 4317741858 ps |
| CPU time | 503.56 seconds |
| Started | Jun 23 08:20:22 PM PDT 24 |
| Finished | Jun 23 08:28:46 PM PDT 24 |
| Peak memory | 643072 kb |
| Host | smart-145583a8-f180-4b19-8156-0f5540625e75 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2454990399 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.chip_ sw_alert_handler_lpg_sleep_mode_alerts.2454990399 |
| Directory | /workspace/13.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/13.chip_sw_all_escalation_resets.2343250863 |
| Short name | T796 |
| Test name | |
| Test status | |
| Simulation time | 5121214048 ps |
| CPU time | 632.75 seconds |
| Started | Jun 23 08:18:48 PM PDT 24 |
| Finished | Jun 23 08:29:21 PM PDT 24 |
| Peak memory | 647968 kb |
| Host | smart-d33726b4-1b85-4cb5-bb50-efb86c4ae6e3 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 2343250863 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.chip_sw_all_escalation_resets.2343250863 |
| Directory | /workspace/13.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/14.chip_sw_alert_handler_lpg_sleep_mode_alerts.283126643 |
| Short name | T833 |
| Test name | |
| Test status | |
| Simulation time | 3774705206 ps |
| CPU time | 319.63 seconds |
| Started | Jun 23 08:19:21 PM PDT 24 |
| Finished | Jun 23 08:24:41 PM PDT 24 |
| Peak memory | 642460 kb |
| Host | smart-e3dc9bd6-14d4-488e-a50f-6e397515cadd |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=283126643 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all _escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.chip_s w_alert_handler_lpg_sleep_mode_alerts.283126643 |
| Directory | /workspace/14.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/14.chip_sw_all_escalation_resets.1425428898 |
| Short name | T824 |
| Test name | |
| Test status | |
| Simulation time | 6212143516 ps |
| CPU time | 601.77 seconds |
| Started | Jun 23 08:19:19 PM PDT 24 |
| Finished | Jun 23 08:29:21 PM PDT 24 |
| Peak memory | 647736 kb |
| Host | smart-72e37504-eb60-48a1-aac7-1632f6430e56 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 1425428898 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.chip_sw_all_escalation_resets.1425428898 |
| Directory | /workspace/14.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/15.chip_sw_alert_handler_lpg_sleep_mode_alerts.1538347165 |
| Short name | T815 |
| Test name | |
| Test status | |
| Simulation time | 3852518990 ps |
| CPU time | 407.45 seconds |
| Started | Jun 23 08:20:39 PM PDT 24 |
| Finished | Jun 23 08:27:27 PM PDT 24 |
| Peak memory | 642668 kb |
| Host | smart-af865b3b-9087-4b4b-b6c9-4580bbcbf60f |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1538347165 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.chip_ sw_alert_handler_lpg_sleep_mode_alerts.1538347165 |
| Directory | /workspace/15.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/15.chip_sw_all_escalation_resets.636637358 |
| Short name | T710 |
| Test name | |
| Test status | |
| Simulation time | 6161325500 ps |
| CPU time | 654.19 seconds |
| Started | Jun 23 08:19:05 PM PDT 24 |
| Finished | Jun 23 08:30:00 PM PDT 24 |
| Peak memory | 647860 kb |
| Host | smart-10d180a8-341a-4274-9f81-54482ca6df77 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 636637358 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.chip_sw_all_escalation_resets.636637358 |
| Directory | /workspace/15.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/16.chip_sw_alert_handler_lpg_sleep_mode_alerts.1962635643 |
| Short name | T736 |
| Test name | |
| Test status | |
| Simulation time | 3858321368 ps |
| CPU time | 435.02 seconds |
| Started | Jun 23 08:21:51 PM PDT 24 |
| Finished | Jun 23 08:29:07 PM PDT 24 |
| Peak memory | 642752 kb |
| Host | smart-9cd8eb12-7a44-49e0-9161-cd30e88b5077 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1962635643 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.chip_ sw_alert_handler_lpg_sleep_mode_alerts.1962635643 |
| Directory | /workspace/16.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/16.chip_sw_all_escalation_resets.3341359085 |
| Short name | T812 |
| Test name | |
| Test status | |
| Simulation time | 5144382980 ps |
| CPU time | 686.81 seconds |
| Started | Jun 23 08:21:10 PM PDT 24 |
| Finished | Jun 23 08:32:37 PM PDT 24 |
| Peak memory | 648004 kb |
| Host | smart-29575862-6ebb-4122-b787-c839a96b4d07 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 3341359085 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.chip_sw_all_escalation_resets.3341359085 |
| Directory | /workspace/16.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/17.chip_sw_alert_handler_lpg_sleep_mode_alerts.3262914389 |
| Short name | T752 |
| Test name | |
| Test status | |
| Simulation time | 3711868370 ps |
| CPU time | 380.2 seconds |
| Started | Jun 23 08:19:21 PM PDT 24 |
| Finished | Jun 23 08:25:42 PM PDT 24 |
| Peak memory | 642512 kb |
| Host | smart-2ad75f45-fd9b-46d4-ab87-f7d673634717 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3262914389 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.chip_ sw_alert_handler_lpg_sleep_mode_alerts.3262914389 |
| Directory | /workspace/17.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/19.chip_sw_all_escalation_resets.3127719896 |
| Short name | T253 |
| Test name | |
| Test status | |
| Simulation time | 4800446736 ps |
| CPU time | 519.12 seconds |
| Started | Jun 23 08:20:22 PM PDT 24 |
| Finished | Jun 23 08:29:02 PM PDT 24 |
| Peak memory | 648136 kb |
| Host | smart-7ea6f43f-c048-49da-ac59-c0f6e85b7cec |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 3127719896 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.chip_sw_all_escalation_resets.3127719896 |
| Directory | /workspace/19.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/2.chip_sw_alert_handler_lpg_sleep_mode_alerts.3877118948 |
| Short name | T789 |
| Test name | |
| Test status | |
| Simulation time | 3840647170 ps |
| CPU time | 425.02 seconds |
| Started | Jun 23 08:12:10 PM PDT 24 |
| Finished | Jun 23 08:19:15 PM PDT 24 |
| Peak memory | 642624 kb |
| Host | smart-0a8ebf83-f132-44ba-8c20-41007ab56868 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3877118948 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_s w_alert_handler_lpg_sleep_mode_alerts.3877118948 |
| Directory | /workspace/2.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/2.chip_sw_all_escalation_resets.1762327017 |
| Short name | T754 |
| Test name | |
| Test status | |
| Simulation time | 5889617250 ps |
| CPU time | 812.4 seconds |
| Started | Jun 23 08:08:18 PM PDT 24 |
| Finished | Jun 23 08:21:51 PM PDT 24 |
| Peak memory | 648000 kb |
| Host | smart-051b974f-1293-4188-b401-f3607dfab537 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 1762327017 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_all_escalation_resets.1762327017 |
| Directory | /workspace/2.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/20.chip_sw_alert_handler_lpg_sleep_mode_alerts.4259008418 |
| Short name | T759 |
| Test name | |
| Test status | |
| Simulation time | 3987569032 ps |
| CPU time | 428.23 seconds |
| Started | Jun 23 08:20:24 PM PDT 24 |
| Finished | Jun 23 08:27:33 PM PDT 24 |
| Peak memory | 646848 kb |
| Host | smart-35946122-c9fa-4e29-8d77-2afb9bf3e85e |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4259008418 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.chip_ sw_alert_handler_lpg_sleep_mode_alerts.4259008418 |
| Directory | /workspace/20.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/20.chip_sw_all_escalation_resets.713377987 |
| Short name | T338 |
| Test name | |
| Test status | |
| Simulation time | 5654135858 ps |
| CPU time | 720.61 seconds |
| Started | Jun 23 08:19:32 PM PDT 24 |
| Finished | Jun 23 08:31:34 PM PDT 24 |
| Peak memory | 643956 kb |
| Host | smart-2ad5c085-9c7b-44db-b52c-43aed41dd12f |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 713377987 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.chip_sw_all_escalation_resets.713377987 |
| Directory | /workspace/20.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/21.chip_sw_alert_handler_lpg_sleep_mode_alerts.3370384623 |
| Short name | T844 |
| Test name | |
| Test status | |
| Simulation time | 3653410858 ps |
| CPU time | 343.65 seconds |
| Started | Jun 23 08:21:01 PM PDT 24 |
| Finished | Jun 23 08:26:45 PM PDT 24 |
| Peak memory | 642532 kb |
| Host | smart-131d9edb-9002-498e-9be3-4255639a57b2 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3370384623 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.chip_ sw_alert_handler_lpg_sleep_mode_alerts.3370384623 |
| Directory | /workspace/21.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/21.chip_sw_all_escalation_resets.2971240476 |
| Short name | T838 |
| Test name | |
| Test status | |
| Simulation time | 4828900028 ps |
| CPU time | 834.68 seconds |
| Started | Jun 23 08:20:23 PM PDT 24 |
| Finished | Jun 23 08:34:18 PM PDT 24 |
| Peak memory | 647876 kb |
| Host | smart-e3510e2e-cb3d-42e9-87ef-a59929b6bec6 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 2971240476 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.chip_sw_all_escalation_resets.2971240476 |
| Directory | /workspace/21.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/22.chip_sw_alert_handler_lpg_sleep_mode_alerts.1883108817 |
| Short name | T777 |
| Test name | |
| Test status | |
| Simulation time | 3961289450 ps |
| CPU time | 497.68 seconds |
| Started | Jun 23 08:22:02 PM PDT 24 |
| Finished | Jun 23 08:30:20 PM PDT 24 |
| Peak memory | 642508 kb |
| Host | smart-d0b2da4e-ad84-4ddc-a5c0-b9ec46c8167b |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1883108817 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.chip_ sw_alert_handler_lpg_sleep_mode_alerts.1883108817 |
| Directory | /workspace/22.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/22.chip_sw_all_escalation_resets.909466842 |
| Short name | T784 |
| Test name | |
| Test status | |
| Simulation time | 5112834178 ps |
| CPU time | 714.54 seconds |
| Started | Jun 23 08:20:30 PM PDT 24 |
| Finished | Jun 23 08:32:25 PM PDT 24 |
| Peak memory | 643564 kb |
| Host | smart-b449a72c-0a0a-43d7-86b3-e1a41639d16a |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 909466842 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.chip_sw_all_escalation_resets.909466842 |
| Directory | /workspace/22.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/23.chip_sw_alert_handler_lpg_sleep_mode_alerts.4056800036 |
| Short name | T832 |
| Test name | |
| Test status | |
| Simulation time | 3545758140 ps |
| CPU time | 414.86 seconds |
| Started | Jun 23 08:19:58 PM PDT 24 |
| Finished | Jun 23 08:26:54 PM PDT 24 |
| Peak memory | 642500 kb |
| Host | smart-e6f19ede-bed2-4fda-a44d-68ffdeebf135 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4056800036 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.chip_ sw_alert_handler_lpg_sleep_mode_alerts.4056800036 |
| Directory | /workspace/23.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/24.chip_sw_alert_handler_lpg_sleep_mode_alerts.3291648683 |
| Short name | T692 |
| Test name | |
| Test status | |
| Simulation time | 3240904404 ps |
| CPU time | 341.33 seconds |
| Started | Jun 23 08:21:50 PM PDT 24 |
| Finished | Jun 23 08:27:31 PM PDT 24 |
| Peak memory | 642596 kb |
| Host | smart-e816672d-bc5c-4ef7-98e2-4d6065f016fb |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3291648683 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.chip_ sw_alert_handler_lpg_sleep_mode_alerts.3291648683 |
| Directory | /workspace/24.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/25.chip_sw_all_escalation_resets.1447384169 |
| Short name | T708 |
| Test name | |
| Test status | |
| Simulation time | 4391536728 ps |
| CPU time | 554.16 seconds |
| Started | Jun 23 08:22:30 PM PDT 24 |
| Finished | Jun 23 08:31:45 PM PDT 24 |
| Peak memory | 647652 kb |
| Host | smart-83b448d1-7ae4-40d9-bf41-c5ba7382dda8 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 1447384169 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.chip_sw_all_escalation_resets.1447384169 |
| Directory | /workspace/25.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/26.chip_sw_alert_handler_lpg_sleep_mode_alerts.2336238842 |
| Short name | T755 |
| Test name | |
| Test status | |
| Simulation time | 3763177420 ps |
| CPU time | 379.67 seconds |
| Started | Jun 23 08:21:54 PM PDT 24 |
| Finished | Jun 23 08:28:14 PM PDT 24 |
| Peak memory | 646768 kb |
| Host | smart-fbd1c466-0a39-4280-87b3-629a6751e1d9 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2336238842 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.chip_ sw_alert_handler_lpg_sleep_mode_alerts.2336238842 |
| Directory | /workspace/26.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/27.chip_sw_all_escalation_resets.3100150675 |
| Short name | T415 |
| Test name | |
| Test status | |
| Simulation time | 5572123288 ps |
| CPU time | 809.38 seconds |
| Started | Jun 23 08:21:18 PM PDT 24 |
| Finished | Jun 23 08:34:48 PM PDT 24 |
| Peak memory | 647696 kb |
| Host | smart-48d00f3f-1d91-44d6-a942-c2d9221592b8 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 3100150675 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.chip_sw_all_escalation_resets.3100150675 |
| Directory | /workspace/27.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/28.chip_sw_alert_handler_lpg_sleep_mode_alerts.2077365730 |
| Short name | T1225 |
| Test name | |
| Test status | |
| Simulation time | 3234449108 ps |
| CPU time | 431.41 seconds |
| Started | Jun 23 08:22:58 PM PDT 24 |
| Finished | Jun 23 08:30:10 PM PDT 24 |
| Peak memory | 642740 kb |
| Host | smart-65237c02-ae67-465a-b344-4be2ba79905c |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2077365730 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.chip_ sw_alert_handler_lpg_sleep_mode_alerts.2077365730 |
| Directory | /workspace/28.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/29.chip_sw_alert_handler_lpg_sleep_mode_alerts.352954739 |
| Short name | T841 |
| Test name | |
| Test status | |
| Simulation time | 3224808038 ps |
| CPU time | 353.62 seconds |
| Started | Jun 23 08:21:23 PM PDT 24 |
| Finished | Jun 23 08:27:17 PM PDT 24 |
| Peak memory | 646820 kb |
| Host | smart-672fbc19-a089-4f9c-9153-9a9ae5ab677b |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=352954739 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all _escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.chip_s w_alert_handler_lpg_sleep_mode_alerts.352954739 |
| Directory | /workspace/29.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/29.chip_sw_all_escalation_resets.2074681230 |
| Short name | T101 |
| Test name | |
| Test status | |
| Simulation time | 5334318656 ps |
| CPU time | 656.21 seconds |
| Started | Jun 23 08:21:46 PM PDT 24 |
| Finished | Jun 23 08:32:42 PM PDT 24 |
| Peak memory | 647624 kb |
| Host | smart-72ebacbc-d666-4c6e-b538-99e32a8ee51a |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 2074681230 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.chip_sw_all_escalation_resets.2074681230 |
| Directory | /workspace/29.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/3.chip_sw_all_escalation_resets.3704355534 |
| Short name | T822 |
| Test name | |
| Test status | |
| Simulation time | 5235136244 ps |
| CPU time | 730.47 seconds |
| Started | Jun 23 08:16:27 PM PDT 24 |
| Finished | Jun 23 08:28:38 PM PDT 24 |
| Peak memory | 643512 kb |
| Host | smart-c9f9552d-a4f8-465f-a82b-79d1f1a77e88 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 3704355534 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.chip_sw_all_escalation_resets.3704355534 |
| Directory | /workspace/3.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/30.chip_sw_all_escalation_resets.3597894717 |
| Short name | T773 |
| Test name | |
| Test status | |
| Simulation time | 5283860516 ps |
| CPU time | 546.27 seconds |
| Started | Jun 23 08:20:29 PM PDT 24 |
| Finished | Jun 23 08:29:36 PM PDT 24 |
| Peak memory | 643500 kb |
| Host | smart-ddd18759-391e-4286-922f-45265e837b95 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 3597894717 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.chip_sw_all_escalation_resets.3597894717 |
| Directory | /workspace/30.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/32.chip_sw_alert_handler_lpg_sleep_mode_alerts.3708630039 |
| Short name | T837 |
| Test name | |
| Test status | |
| Simulation time | 3663522832 ps |
| CPU time | 455.55 seconds |
| Started | Jun 23 08:21:30 PM PDT 24 |
| Finished | Jun 23 08:29:06 PM PDT 24 |
| Peak memory | 642380 kb |
| Host | smart-607fa6c4-4433-4716-88f1-cf1bddbbce9a |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3708630039 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.chip_ sw_alert_handler_lpg_sleep_mode_alerts.3708630039 |
| Directory | /workspace/32.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/33.chip_sw_alert_handler_lpg_sleep_mode_alerts.3441708908 |
| Short name | T820 |
| Test name | |
| Test status | |
| Simulation time | 3126931640 ps |
| CPU time | 322.24 seconds |
| Started | Jun 23 08:21:49 PM PDT 24 |
| Finished | Jun 23 08:27:11 PM PDT 24 |
| Peak memory | 642620 kb |
| Host | smart-55960809-13c6-4731-9c39-115a3866d2c0 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3441708908 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.chip_ sw_alert_handler_lpg_sleep_mode_alerts.3441708908 |
| Directory | /workspace/33.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/35.chip_sw_all_escalation_resets.719794742 |
| Short name | T767 |
| Test name | |
| Test status | |
| Simulation time | 5413940470 ps |
| CPU time | 542.9 seconds |
| Started | Jun 23 08:21:02 PM PDT 24 |
| Finished | Jun 23 08:30:05 PM PDT 24 |
| Peak memory | 648008 kb |
| Host | smart-b5314cf5-01e5-4f07-9408-f1912b675a74 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 719794742 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.chip_sw_all_escalation_resets.719794742 |
| Directory | /workspace/35.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/36.chip_sw_all_escalation_resets.1935175148 |
| Short name | T834 |
| Test name | |
| Test status | |
| Simulation time | 4288344620 ps |
| CPU time | 713.93 seconds |
| Started | Jun 23 08:23:06 PM PDT 24 |
| Finished | Jun 23 08:35:01 PM PDT 24 |
| Peak memory | 647712 kb |
| Host | smart-8e542a2e-ccc6-4390-8d83-60621ca9e5be |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 1935175148 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.chip_sw_all_escalation_resets.1935175148 |
| Directory | /workspace/36.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/38.chip_sw_all_escalation_resets.1903769 |
| Short name | T781 |
| Test name | |
| Test status | |
| Simulation time | 6065723446 ps |
| CPU time | 684.5 seconds |
| Started | Jun 23 08:21:00 PM PDT 24 |
| Finished | Jun 23 08:32:26 PM PDT 24 |
| Peak memory | 647712 kb |
| Host | smart-bc817076-d9a1-4c2c-b43a-ecae0b6d6737 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 1903769 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.chip_sw_all_escalation_resets.1903769 |
| Directory | /workspace/38.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/39.chip_sw_alert_handler_lpg_sleep_mode_alerts.3336354325 |
| Short name | T297 |
| Test name | |
| Test status | |
| Simulation time | 4196417200 ps |
| CPU time | 393.39 seconds |
| Started | Jun 23 08:22:22 PM PDT 24 |
| Finished | Jun 23 08:28:56 PM PDT 24 |
| Peak memory | 642432 kb |
| Host | smart-be948842-fd72-405f-a5c4-516477b20768 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3336354325 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.chip_ sw_alert_handler_lpg_sleep_mode_alerts.3336354325 |
| Directory | /workspace/39.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/4.chip_sw_all_escalation_resets.3146168057 |
| Short name | T829 |
| Test name | |
| Test status | |
| Simulation time | 4370102180 ps |
| CPU time | 564.25 seconds |
| Started | Jun 23 08:18:02 PM PDT 24 |
| Finished | Jun 23 08:27:27 PM PDT 24 |
| Peak memory | 648120 kb |
| Host | smart-98e0d4a2-086f-4caa-a887-af29b15d356d |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 3146168057 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.chip_sw_all_escalation_resets.3146168057 |
| Directory | /workspace/4.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/40.chip_sw_alert_handler_lpg_sleep_mode_alerts.1166062577 |
| Short name | T286 |
| Test name | |
| Test status | |
| Simulation time | 4335298752 ps |
| CPU time | 490.83 seconds |
| Started | Jun 23 08:21:14 PM PDT 24 |
| Finished | Jun 23 08:29:25 PM PDT 24 |
| Peak memory | 642884 kb |
| Host | smart-4b68df48-64ba-4f3c-9513-b97f231e80c6 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1166062577 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.chip_ sw_alert_handler_lpg_sleep_mode_alerts.1166062577 |
| Directory | /workspace/40.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/40.chip_sw_all_escalation_resets.2431955149 |
| Short name | T257 |
| Test name | |
| Test status | |
| Simulation time | 5625877882 ps |
| CPU time | 755.12 seconds |
| Started | Jun 23 08:21:29 PM PDT 24 |
| Finished | Jun 23 08:34:04 PM PDT 24 |
| Peak memory | 648264 kb |
| Host | smart-a394bb02-a9a3-425e-8d8e-5f81bb9ea097 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 2431955149 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.chip_sw_all_escalation_resets.2431955149 |
| Directory | /workspace/40.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/42.chip_sw_alert_handler_lpg_sleep_mode_alerts.3385906020 |
| Short name | T763 |
| Test name | |
| Test status | |
| Simulation time | 4005028872 ps |
| CPU time | 390.94 seconds |
| Started | Jun 23 08:22:51 PM PDT 24 |
| Finished | Jun 23 08:29:22 PM PDT 24 |
| Peak memory | 642500 kb |
| Host | smart-7d8f0588-9928-41e6-9f66-0870efd6c021 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3385906020 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.chip_ sw_alert_handler_lpg_sleep_mode_alerts.3385906020 |
| Directory | /workspace/42.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/45.chip_sw_alert_handler_lpg_sleep_mode_alerts.2890658937 |
| Short name | T86 |
| Test name | |
| Test status | |
| Simulation time | 3618379460 ps |
| CPU time | 431.41 seconds |
| Started | Jun 23 08:22:03 PM PDT 24 |
| Finished | Jun 23 08:29:15 PM PDT 24 |
| Peak memory | 642436 kb |
| Host | smart-201ecc2c-7271-4adc-b513-caf386ea701b |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2890658937 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.chip_ sw_alert_handler_lpg_sleep_mode_alerts.2890658937 |
| Directory | /workspace/45.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/45.chip_sw_all_escalation_resets.1441132396 |
| Short name | T793 |
| Test name | |
| Test status | |
| Simulation time | 4594508796 ps |
| CPU time | 803.98 seconds |
| Started | Jun 23 08:23:09 PM PDT 24 |
| Finished | Jun 23 08:36:33 PM PDT 24 |
| Peak memory | 647752 kb |
| Host | smart-4a9a6891-1357-4133-afab-e98f636d41b5 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 1441132396 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.chip_sw_all_escalation_resets.1441132396 |
| Directory | /workspace/45.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/47.chip_sw_alert_handler_lpg_sleep_mode_alerts.3652646537 |
| Short name | T813 |
| Test name | |
| Test status | |
| Simulation time | 3824927968 ps |
| CPU time | 336.04 seconds |
| Started | Jun 23 08:21:56 PM PDT 24 |
| Finished | Jun 23 08:27:33 PM PDT 24 |
| Peak memory | 646888 kb |
| Host | smart-743b998b-6905-44a0-80a7-35f073f397ad |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3652646537 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.chip_ sw_alert_handler_lpg_sleep_mode_alerts.3652646537 |
| Directory | /workspace/47.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/5.chip_sw_alert_handler_lpg_sleep_mode_alerts.4028738323 |
| Short name | T809 |
| Test name | |
| Test status | |
| Simulation time | 3859775810 ps |
| CPU time | 531.9 seconds |
| Started | Jun 23 08:18:23 PM PDT 24 |
| Finished | Jun 23 08:27:15 PM PDT 24 |
| Peak memory | 642460 kb |
| Host | smart-08b0cea0-5dcb-4e79-af1b-1079b3757c4a |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4028738323 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.chip_s w_alert_handler_lpg_sleep_mode_alerts.4028738323 |
| Directory | /workspace/5.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/51.chip_sw_alert_handler_lpg_sleep_mode_alerts.680088824 |
| Short name | T367 |
| Test name | |
| Test status | |
| Simulation time | 3299637490 ps |
| CPU time | 423.43 seconds |
| Started | Jun 23 08:22:16 PM PDT 24 |
| Finished | Jun 23 08:29:19 PM PDT 24 |
| Peak memory | 642428 kb |
| Host | smart-681f0c6d-32c9-499c-9b91-ea1912ea50ce |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=680088824 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all _escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.chip_s w_alert_handler_lpg_sleep_mode_alerts.680088824 |
| Directory | /workspace/51.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/52.chip_sw_alert_handler_lpg_sleep_mode_alerts.2241481281 |
| Short name | T258 |
| Test name | |
| Test status | |
| Simulation time | 4121250000 ps |
| CPU time | 374.07 seconds |
| Started | Jun 23 08:22:40 PM PDT 24 |
| Finished | Jun 23 08:28:54 PM PDT 24 |
| Peak memory | 646828 kb |
| Host | smart-fbf14845-62d0-4e91-8d68-bc04ab69c3ac |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2241481281 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.chip_ sw_alert_handler_lpg_sleep_mode_alerts.2241481281 |
| Directory | /workspace/52.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/52.chip_sw_all_escalation_resets.805127363 |
| Short name | T807 |
| Test name | |
| Test status | |
| Simulation time | 5555118470 ps |
| CPU time | 747.69 seconds |
| Started | Jun 23 08:22:33 PM PDT 24 |
| Finished | Jun 23 08:35:01 PM PDT 24 |
| Peak memory | 643548 kb |
| Host | smart-ae91cbdd-3755-413c-968f-afcb89157486 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 805127363 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.chip_sw_all_escalation_resets.805127363 |
| Directory | /workspace/52.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/56.chip_sw_alert_handler_lpg_sleep_mode_alerts.491087385 |
| Short name | T742 |
| Test name | |
| Test status | |
| Simulation time | 3629840788 ps |
| CPU time | 360.22 seconds |
| Started | Jun 23 08:22:33 PM PDT 24 |
| Finished | Jun 23 08:28:34 PM PDT 24 |
| Peak memory | 647020 kb |
| Host | smart-eeb101c5-3507-4a4c-9091-517441cbd623 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=491087385 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all _escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.chip_s w_alert_handler_lpg_sleep_mode_alerts.491087385 |
| Directory | /workspace/56.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/57.chip_sw_alert_handler_lpg_sleep_mode_alerts.364486512 |
| Short name | T758 |
| Test name | |
| Test status | |
| Simulation time | 4113851500 ps |
| CPU time | 441.92 seconds |
| Started | Jun 23 08:24:19 PM PDT 24 |
| Finished | Jun 23 08:31:41 PM PDT 24 |
| Peak memory | 646812 kb |
| Host | smart-ac84edca-189d-4aec-bbd3-d58b5002f415 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=364486512 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all _escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.chip_s w_alert_handler_lpg_sleep_mode_alerts.364486512 |
| Directory | /workspace/57.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/6.chip_sw_alert_handler_lpg_sleep_mode_alerts.841911589 |
| Short name | T791 |
| Test name | |
| Test status | |
| Simulation time | 3800789960 ps |
| CPU time | 513.12 seconds |
| Started | Jun 23 08:18:59 PM PDT 24 |
| Finished | Jun 23 08:27:33 PM PDT 24 |
| Peak memory | 642508 kb |
| Host | smart-37979325-c92a-4f90-aff5-3f26421836ab |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=841911589 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all _escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.chip_sw _alert_handler_lpg_sleep_mode_alerts.841911589 |
| Directory | /workspace/6.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/62.chip_sw_all_escalation_resets.962274016 |
| Short name | T798 |
| Test name | |
| Test status | |
| Simulation time | 5698948374 ps |
| CPU time | 573.44 seconds |
| Started | Jun 23 08:28:01 PM PDT 24 |
| Finished | Jun 23 08:38:06 PM PDT 24 |
| Peak memory | 647748 kb |
| Host | smart-5b08ffd9-bece-4c39-80ec-6a0fb23b557c |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 962274016 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.chip_sw_all_escalation_resets.962274016 |
| Directory | /workspace/62.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/67.chip_sw_all_escalation_resets.1856885643 |
| Short name | T360 |
| Test name | |
| Test status | |
| Simulation time | 5469126240 ps |
| CPU time | 576.73 seconds |
| Started | Jun 23 08:23:46 PM PDT 24 |
| Finished | Jun 23 08:33:23 PM PDT 24 |
| Peak memory | 643480 kb |
| Host | smart-b59cd670-127c-49c4-be40-a14dd0a8aeea |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 1856885643 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.chip_sw_all_escalation_resets.1856885643 |
| Directory | /workspace/67.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/69.chip_sw_all_escalation_resets.1154191131 |
| Short name | T738 |
| Test name | |
| Test status | |
| Simulation time | 4618616700 ps |
| CPU time | 450.56 seconds |
| Started | Jun 23 08:23:56 PM PDT 24 |
| Finished | Jun 23 08:31:26 PM PDT 24 |
| Peak memory | 647748 kb |
| Host | smart-f5796373-3887-4c56-87a2-8f0bc4186ce5 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 1154191131 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.chip_sw_all_escalation_resets.1154191131 |
| Directory | /workspace/69.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/71.chip_sw_alert_handler_lpg_sleep_mode_alerts.2118169032 |
| Short name | T740 |
| Test name | |
| Test status | |
| Simulation time | 4211289560 ps |
| CPU time | 440 seconds |
| Started | Jun 23 08:23:38 PM PDT 24 |
| Finished | Jun 23 08:30:58 PM PDT 24 |
| Peak memory | 642448 kb |
| Host | smart-33f8ee69-1886-4380-8904-ffa500ce6de9 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2118169032 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.chip_ sw_alert_handler_lpg_sleep_mode_alerts.2118169032 |
| Directory | /workspace/71.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/79.chip_sw_alert_handler_lpg_sleep_mode_alerts.828252162 |
| Short name | T821 |
| Test name | |
| Test status | |
| Simulation time | 4026138682 ps |
| CPU time | 388.47 seconds |
| Started | Jun 23 08:25:38 PM PDT 24 |
| Finished | Jun 23 08:32:07 PM PDT 24 |
| Peak memory | 642560 kb |
| Host | smart-b1446664-c108-4131-b7cd-e72d5e0f9211 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=828252162 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all _escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.chip_s w_alert_handler_lpg_sleep_mode_alerts.828252162 |
| Directory | /workspace/79.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/81.chip_sw_alert_handler_lpg_sleep_mode_alerts.1982594264 |
| Short name | T84 |
| Test name | |
| Test status | |
| Simulation time | 3682724152 ps |
| CPU time | 395.61 seconds |
| Started | Jun 23 08:25:21 PM PDT 24 |
| Finished | Jun 23 08:31:57 PM PDT 24 |
| Peak memory | 643012 kb |
| Host | smart-bf86f98d-6ced-424b-96eb-15d2d4227b20 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1982594264 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 81.chip_ sw_alert_handler_lpg_sleep_mode_alerts.1982594264 |
| Directory | /workspace/81.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/9.chip_sw_alert_handler_lpg_sleep_mode_alerts.3056980687 |
| Short name | T803 |
| Test name | |
| Test status | |
| Simulation time | 3434432460 ps |
| CPU time | 409.01 seconds |
| Started | Jun 23 08:19:08 PM PDT 24 |
| Finished | Jun 23 08:25:57 PM PDT 24 |
| Peak memory | 642548 kb |
| Host | smart-7210ec38-c1e1-4105-ad6b-68642f7469c9 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3056980687 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.chip_s w_alert_handler_lpg_sleep_mode_alerts.3056980687 |
| Directory | /workspace/9.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/9.chip_sw_all_escalation_resets.182295088 |
| Short name | T255 |
| Test name | |
| Test status | |
| Simulation time | 5037805160 ps |
| CPU time | 523.94 seconds |
| Started | Jun 23 08:18:14 PM PDT 24 |
| Finished | Jun 23 08:26:58 PM PDT 24 |
| Peak memory | 648236 kb |
| Host | smart-9dcbf7b8-3d64-42b9-afb2-427d4a8df7bf |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 182295088 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.chip_sw_all_escalation_resets.182295088 |
| Directory | /workspace/9.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/91.chip_sw_all_escalation_resets.4273377335 |
| Short name | T273 |
| Test name | |
| Test status | |
| Simulation time | 5054670440 ps |
| CPU time | 582.15 seconds |
| Started | Jun 23 08:25:41 PM PDT 24 |
| Finished | Jun 23 08:35:24 PM PDT 24 |
| Peak memory | 648052 kb |
| Host | smart-e273ab9b-2f23-471f-8e89-ceca28092949 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 4273377335 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 91.chip_sw_all_escalation_resets.4273377335 |
| Directory | /workspace/91.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/0.chip_sw_pwrmgr_lowpower_cancel.9405216 |
| Short name | T326 |
| Test name | |
| Test status | |
| Simulation time | 3733003208 ps |
| CPU time | 419.49 seconds |
| Started | Jun 23 07:55:00 PM PDT 24 |
| Finished | Jun 23 08:02:00 PM PDT 24 |
| Peak memory | 606904 kb |
| Host | smart-590fc24d-22a4-4a74-8d68-7e4e014719af |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_lowpower_cancel_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=9405216 -assert nopostproc +UVM_TE STNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo g /dev/null -cm_name 0.chip_sw_pwrmgr_lowpower_cancel.9405216 |
| Directory | /workspace/0.chip_sw_pwrmgr_lowpower_cancel/latest |
| Test location | /workspace/coverage/default/1.chip_sw_rstmgr_alert_info.869149777 |
| Short name | T316 |
| Test name | |
| Test status | |
| Simulation time | 13026484168 ps |
| CPU time | 1693.12 seconds |
| Started | Jun 23 08:00:55 PM PDT 24 |
| Finished | Jun 23 08:29:10 PM PDT 24 |
| Peak memory | 608860 kb |
| Host | smart-3d798083-e77a-4a71-99d1-30d8470d00a6 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=30_000_000 +en_scb_tl_err_chk=0 +sw_build_device=sim_dv +sw_images=rstmgr_alert_info_test:1:new_rules,test _rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb _random_seed=869149777 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_rstmgr_alert_info.869149777 |
| Directory | /workspace/1.chip_sw_rstmgr_alert_info/latest |
| Test location | /workspace/coverage/default/59.chip_sw_all_escalation_resets.2893475402 |
| Short name | T705 |
| Test name | |
| Test status | |
| Simulation time | 4890833620 ps |
| CPU time | 579.64 seconds |
| Started | Jun 23 08:22:52 PM PDT 24 |
| Finished | Jun 23 08:32:32 PM PDT 24 |
| Peak memory | 608376 kb |
| Host | smart-f4249da4-e2cd-4352-aa60-d5e8dbac623a |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 2893475402 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.chip_sw_all_escalation_resets.2893475402 |
| Directory | /workspace/59.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/0.chip_sw_keymgr_sideload_otbn.2592282618 |
| Short name | T220 |
| Test name | |
| Test status | |
| Simulation time | 16457672452 ps |
| CPU time | 4803.56 seconds |
| Started | Jun 23 07:50:48 PM PDT 24 |
| Finished | Jun 23 09:10:52 PM PDT 24 |
| Peak memory | 608848 kb |
| Host | smart-b4352006-7aba-46fc-9880-c4648100ae96 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=20_000_000 +sw_build_device=sim_dv +sw_images=keymgr_sideload_otbn_test:1:new_rules,test_rom:0 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25922 82618 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_keymgr_sideload_otbn.2592282618 |
| Directory | /workspace/0.chip_sw_keymgr_sideload_otbn/latest |
| Test location | /workspace/coverage/default/0.chip_sw_pwrmgr_full_aon_reset.2336497577 |
| Short name | T1175 |
| Test name | |
| Test status | |
| Simulation time | 7904484738 ps |
| CPU time | 610.19 seconds |
| Started | Jun 23 07:50:19 PM PDT 24 |
| Finished | Jun 23 08:00:30 PM PDT 24 |
| Peak memory | 607156 kb |
| Host | smart-285ee667-b65a-411c-9970-c71a977d54a9 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=rstmgr_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2336497577 -assert nopostproc +UVM_TESTNAME=c hip_base_test +UVM_TEST_SEQ=chip_sw_full_aon_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_ log /dev/null -cm_name 0.chip_sw_pwrmgr_full_aon_reset.2336497577 |
| Directory | /workspace/0.chip_sw_pwrmgr_full_aon_reset/latest |
| Test location | /workspace/coverage/default/0.chip_sw_sysrst_ctrl_ec_rst_l.947665012 |
| Short name | T37 |
| Test name | |
| Test status | |
| Simulation time | 20415660587 ps |
| CPU time | 3417.71 seconds |
| Started | Jun 23 07:50:21 PM PDT 24 |
| Finished | Jun 23 08:47:20 PM PDT 24 |
| Peak memory | 608480 kb |
| Host | smart-060cf74f-85fe-4485-86fc-640a670547f6 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=sysrst_ctrl_ec_rst_l_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=947665012 -assert nopostproc +UVM_TE STNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_ec_rst_l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de fault.vdb -cm_log /dev/null -cm_name 0.chip_sw_sysrst_ctrl_ec_rst_l.947665012 |
| Directory | /workspace/0.chip_sw_sysrst_ctrl_ec_rst_l/latest |
| Test location | /workspace/coverage/default/2.chip_sw_otp_ctrl_vendor_test_csr_access.1187381211 |
| Short name | T159 |
| Test name | |
| Test status | |
| Simulation time | 2493458804 ps |
| CPU time | 167.06 seconds |
| Started | Jun 23 08:08:24 PM PDT 24 |
| Finished | Jun 23 08:11:11 PM PDT 24 |
| Peak memory | 615084 kb |
| Host | smart-79062d86-d59c-4736-8dda-9ea02861a35a |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=otp_ctrl_vendor_test_csr_access_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1187381211 -assert nopost proc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_otp_ctrl_vendor_test_csr_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_otp_ctrl_vendor_test_csr_access.1187381211 |
| Directory | /workspace/2.chip_sw_otp_ctrl_vendor_test_csr_access/latest |
| Test location | /workspace/coverage/default/0.chip_sw_power_idle_load.2531642068 |
| Short name | T148 |
| Test name | |
| Test status | |
| Simulation time | 4929828192 ps |
| CPU time | 639.61 seconds |
| Started | Jun 23 07:55:19 PM PDT 24 |
| Finished | Jun 23 08:06:00 PM PDT 24 |
| Peak memory | 607348 kb |
| Host | smart-4903c43f-38d7-4182-be63-a3fba78827d7 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=chip_power_idle_load:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2531642068 -assert nopostproc +UVM_TESTNA ME=chip_base_test +UVM_TEST_SEQ=chip_sw_power_idle_load_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_power_idle_load.2531642068 |
| Directory | /workspace/0.chip_sw_power_idle_load/latest |
| Test location | /workspace/coverage/cover_reg_top/10.chip_tl_errors.1322193177 |
| Short name | T703 |
| Test name | |
| Test status | |
| Simulation time | 3149784636 ps |
| CPU time | 136.04 seconds |
| Started | Jun 23 07:22:57 PM PDT 24 |
| Finished | Jun 23 07:25:13 PM PDT 24 |
| Peak memory | 602544 kb |
| Host | smart-5a465e95-b816-4429-bb9a-d3d666d7aaa6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1322193177 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.chip_tl_errors.1322193177 |
| Directory | /workspace/10.chip_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/11.chip_tl_errors.3805894573 |
| Short name | T564 |
| Test name | |
| Test status | |
| Simulation time | 4548054579 ps |
| CPU time | 362.01 seconds |
| Started | Jun 23 07:23:19 PM PDT 24 |
| Finished | Jun 23 07:29:22 PM PDT 24 |
| Peak memory | 603464 kb |
| Host | smart-3cb4612a-8598-4446-9d60-af8084c9bb2c |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3805894573 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.chip_tl_errors.3805894573 |
| Directory | /workspace/11.chip_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/20.xbar_access_same_device_slow_rsp.2482511525 |
| Short name | T591 |
| Test name | |
| Test status | |
| Simulation time | 136457586732 ps |
| CPU time | 2667.93 seconds |
| Started | Jun 23 07:26:31 PM PDT 24 |
| Finished | Jun 23 08:11:00 PM PDT 24 |
| Peak memory | 574188 kb |
| Host | smart-2b8b8a6c-68be-4749-a944-adac2810ef97 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2482511525 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.xbar_access_same_ device_slow_rsp.2482511525 |
| Directory | /workspace/20.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/default/2.chip_sw_pwrmgr_lowpower_cancel.4191567260 |
| Short name | T327 |
| Test name | |
| Test status | |
| Simulation time | 3834291070 ps |
| CPU time | 423.51 seconds |
| Started | Jun 23 08:13:45 PM PDT 24 |
| Finished | Jun 23 08:20:49 PM PDT 24 |
| Peak memory | 606860 kb |
| Host | smart-7594fc69-3c4f-4139-8eae-436144470ac2 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_lowpower_cancel_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4191567260 -assert nopostproc +UVM _TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm _log /dev/null -cm_name 2.chip_sw_pwrmgr_lowpower_cancel.4191567260 |
| Directory | /workspace/2.chip_sw_pwrmgr_lowpower_cancel/latest |
| Test location | /workspace/coverage/default/2.chip_sw_rstmgr_alert_info.758302498 |
| Short name | T315 |
| Test name | |
| Test status | |
| Simulation time | 9828667838 ps |
| CPU time | 1711 seconds |
| Started | Jun 23 08:10:36 PM PDT 24 |
| Finished | Jun 23 08:39:08 PM PDT 24 |
| Peak memory | 608544 kb |
| Host | smart-970df37b-f03f-448f-8065-cd43f8d02e08 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=30_000_000 +en_scb_tl_err_chk=0 +sw_build_device=sim_dv +sw_images=rstmgr_alert_info_test:1:new_rules,test _rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb _random_seed=758302498 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_rstmgr_alert_info.758302498 |
| Directory | /workspace/2.chip_sw_rstmgr_alert_info/latest |
| Test location | /workspace/coverage/default/0.chip_sw_adc_ctrl_sleep_debug_cable_wakeup.44697278 |
| Short name | T1108 |
| Test name | |
| Test status | |
| Simulation time | 19118432028 ps |
| CPU time | 603.97 seconds |
| Started | Jun 23 07:49:53 PM PDT 24 |
| Finished | Jun 23 07:59:58 PM PDT 24 |
| Peak memory | 615132 kb |
| Host | smart-33119617-37fb-4926-b431-7e52a82dea30 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=adc_ctrl_sleep_debug_cable_wakeup_test:1:new_rules,test_rom: 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand om_seed=44697278 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_adc_ctrl_sleep_debug_cable_wakeup_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_adc_ctrl_sleep_debug_cable_wakeup.44697278 |
| Directory | /workspace/0.chip_sw_adc_ctrl_sleep_debug_cable_wakeup/latest |
| Test location | /workspace/coverage/default/0.chip_sw_edn_entropy_reqs.2080854730 |
| Short name | T424 |
| Test name | |
| Test status | |
| Simulation time | 6248238624 ps |
| CPU time | 1162.39 seconds |
| Started | Jun 23 07:53:14 PM PDT 24 |
| Finished | Jun 23 08:12:37 PM PDT 24 |
| Peak memory | 608812 kb |
| Host | smart-1fe2b0d5-e124-4a8a-94c4-1d25ff7f1b73 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=15000000 +rng_srate_value_min=15 +rng_srate_value_max=30 +sw_build_device=sim_dv +sw_images=entropy_src_ed n_reqs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2080854730 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_edn_entropy_reqs.2080854730 |
| Directory | /workspace/0.chip_sw_edn_entropy_reqs/latest |
| Test location | /workspace/coverage/default/0.chip_sw_i2c_host_tx_rx_idx1.2732593787 |
| Short name | T382 |
| Test name | |
| Test status | |
| Simulation time | 5747309574 ps |
| CPU time | 1052.33 seconds |
| Started | Jun 23 07:49:09 PM PDT 24 |
| Finished | Jun 23 08:06:42 PM PDT 24 |
| Peak memory | 607260 kb |
| Host | smart-96388a58-a03c-42d9-bb8b-7b6e21b37715 |
| User | root |
| Command | /workspace/default/simv +i2c_idx=1 +sw_build_device=sim_dv +sw_images=i2c_host_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2732593787 -assert nopostproc + UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_i2c_host_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de fault.vdb -cm_log /dev/null -cm_name 0.chip_sw_i2c_host_tx_rx_idx1.2732593787 |
| Directory | /workspace/0.chip_sw_i2c_host_tx_rx_idx1/latest |
| Test location | /workspace/coverage/default/0.chip_sw_alert_handler_lpg_clkoff.548251223 |
| Short name | T422 |
| Test name | |
| Test status | |
| Simulation time | 6349505902 ps |
| CPU time | 1306.43 seconds |
| Started | Jun 23 07:51:07 PM PDT 24 |
| Finished | Jun 23 08:12:54 PM PDT 24 |
| Peak memory | 607964 kb |
| Host | smart-fd1d9a90-bb87-4207-a83b-355c0cd1bd6b |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +sw_build_device=sim_dv +sw_images=alert_handler_lpg_clkoff_test:1:new_rules,test_r om:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r andom_seed=548251223 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_alert_handler_lpg_clkoff_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_alert_handler_lpg_clkoff.548251223 |
| Directory | /workspace/0.chip_sw_alert_handler_lpg_clkoff/latest |
| Test location | /workspace/coverage/default/0.chip_sw_flash_init_reduced_freq.32134886 |
| Short name | T1149 |
| Test name | |
| Test status | |
| Simulation time | 17732152121 ps |
| CPU time | 2010.6 seconds |
| Started | Jun 23 07:53:37 PM PDT 24 |
| Finished | Jun 23 08:27:10 PM PDT 24 |
| Peak memory | 610292 kb |
| Host | smart-badb72cc-4e35-4fe5-84c0-7ec9694ec3c7 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=25_000_000 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=flash_init_test:0:test_in_rom:new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=32134886 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_flash_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_flash_init_reduced_freq.32134886 |
| Directory | /workspace/0.chip_sw_flash_init_reduced_freq/latest |
| Test location | /workspace/coverage/default/0.chip_sw_pwrmgr_main_power_glitch_reset.2987731281 |
| Short name | T1233 |
| Test name | |
| Test status | |
| Simulation time | 3948578792 ps |
| CPU time | 389.82 seconds |
| Started | Jun 23 07:52:28 PM PDT 24 |
| Finished | Jun 23 07:58:58 PM PDT 24 |
| Peak memory | 613844 kb |
| Host | smart-1ac4f768-8b7f-497e-8b3c-c4524515a97c |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=pwrmgr_main_power_glitch_test:1:new_rules,test_rom:0 +cd c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se ed=2987731281 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_main_power_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_main_power_glitch_reset.2987731281 |
| Directory | /workspace/0.chip_sw_pwrmgr_main_power_glitch_reset/latest |
| Test location | /workspace/coverage/default/1.chip_sw_keymgr_sideload_aes.4224430941 |
| Short name | T224 |
| Test name | |
| Test status | |
| Simulation time | 6799733352 ps |
| CPU time | 1042.03 seconds |
| Started | Jun 23 08:01:03 PM PDT 24 |
| Finished | Jun 23 08:18:26 PM PDT 24 |
| Peak memory | 609132 kb |
| Host | smart-148ceab9-9f8c-4a29-a2f6-4a0c8865b6e6 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=20_000_000 +sw_build_device=sim_dv +sw_images=keymgr_sideload_aes_test:1:new_rules,test_rom:0 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=422443 0941 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_keymgr_sideload_aes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_keymgr_sideload_aes.4224430941 |
| Directory | /workspace/1.chip_sw_keymgr_sideload_aes/latest |
| Test location | /workspace/coverage/cover_reg_top/10.xbar_stress_all.2717254391 |
| Short name | T460 |
| Test name | |
| Test status | |
| Simulation time | 8485809293 ps |
| CPU time | 335.59 seconds |
| Started | Jun 23 07:23:16 PM PDT 24 |
| Finished | Jun 23 07:28:52 PM PDT 24 |
| Peak memory | 574312 kb |
| Host | smart-b8951179-c0ea-4f58-8368-a17f2a602ad7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2717254391 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.xbar_stress_all.2717254391 |
| Directory | /workspace/10.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/16.chip_tl_errors.2346883041 |
| Short name | T697 |
| Test name | |
| Test status | |
| Simulation time | 2945375404 ps |
| CPU time | 94.49 seconds |
| Started | Jun 23 07:25:11 PM PDT 24 |
| Finished | Jun 23 07:26:46 PM PDT 24 |
| Peak memory | 603484 kb |
| Host | smart-cce3e7ed-3830-40cf-9b9e-bdf913c48ab5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2346883041 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.chip_tl_errors.2346883041 |
| Directory | /workspace/16.chip_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/4.xbar_stress_all_with_error.4206348342 |
| Short name | T623 |
| Test name | |
| Test status | |
| Simulation time | 4440566296 ps |
| CPU time | 338.38 seconds |
| Started | Jun 23 07:21:24 PM PDT 24 |
| Finished | Jun 23 07:27:03 PM PDT 24 |
| Peak memory | 574364 kb |
| Host | smart-2ddf697a-e530-4373-b501-3e331d1130d7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4206348342 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.xbar_stress_all_with_error.4206348342 |
| Directory | /workspace/4.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/81.xbar_stress_all_with_error.616256761 |
| Short name | T707 |
| Test name | |
| Test status | |
| Simulation time | 15675232701 ps |
| CPU time | 603.03 seconds |
| Started | Jun 23 07:38:30 PM PDT 24 |
| Finished | Jun 23 07:48:34 PM PDT 24 |
| Peak memory | 574384 kb |
| Host | smart-efda489e-f295-4fed-93cb-8732cbb738b2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=616256761 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 81.xbar_stress_all_with_error.616256761 |
| Directory | /workspace/81.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/95.xbar_stress_all_with_error.4140877733 |
| Short name | T77 |
| Test name | |
| Test status | |
| Simulation time | 1369960181 ps |
| CPU time | 94.46 seconds |
| Started | Jun 23 07:40:52 PM PDT 24 |
| Finished | Jun 23 07:42:27 PM PDT 24 |
| Peak memory | 574196 kb |
| Host | smart-d172b4b9-32eb-43d8-bfc1-24b857665665 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4140877733 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 95.xbar_stress_all_with_error.4140877733 |
| Directory | /workspace/95.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/default/0.chip_sw_rv_core_ibex_nmi_irq.4023117561 |
| Short name | T245 |
| Test name | |
| Test status | |
| Simulation time | 4749335764 ps |
| CPU time | 957.82 seconds |
| Started | Jun 23 07:51:51 PM PDT 24 |
| Finished | Jun 23 08:07:50 PM PDT 24 |
| Peak memory | 606888 kb |
| Host | smart-2bb71674-dac8-4967-9727-deb4a94b7dd6 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=10_000_000 +sw_build_device=sim_dv +sw_images=rv_core_ibex_nmi_irq_test:1:new_rules,test_rom:0 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40231 17561 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_rv_core_ibex_nmi_irq.4023117561 |
| Directory | /workspace/0.chip_sw_rv_core_ibex_nmi_irq/latest |
| Test location | /workspace/coverage/default/2.chip_sw_i2c_device_tx_rx.2758562248 |
| Short name | T324 |
| Test name | |
| Test status | |
| Simulation time | 3253217704 ps |
| CPU time | 487.71 seconds |
| Started | Jun 23 08:06:06 PM PDT 24 |
| Finished | Jun 23 08:14:15 PM PDT 24 |
| Peak memory | 608096 kb |
| Host | smart-a3be08d0-d7e7-49a9-a59d-e185ef3826da |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=i2c_device_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2758562248 -assert nopostproc +UVM_TESTN AME=chip_base_test +UVM_TEST_SEQ=chip_sw_i2c_device_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v db -cm_log /dev/null -cm_name 2.chip_sw_i2c_device_tx_rx.2758562248 |
| Directory | /workspace/2.chip_sw_i2c_device_tx_rx/latest |
| Test location | /workspace/coverage/pad_ctrl_test_mode/0.chip_padctrl_attributes.692698897 |
| Short name | T185 |
| Test name | |
| Test status | |
| Simulation time | 5011361976 ps |
| CPU time | 295.47 seconds |
| Started | Jun 23 08:19:31 PM PDT 24 |
| Finished | Jun 23 08:24:27 PM PDT 24 |
| Peak memory | 641772 kb |
| Host | smart-aa5de064-b0b0-40d8-b291-cd00d2ee6ffd |
| User | root |
| Command | /workspace/pad_ctrl_test_mode/simv +use_otp_image=OtpTypeLcStProd +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=692698897 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TES T_SEQ=chip_padctrl_attributes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/pad_ctrl_test_mode.vdb -cm_log /dev/n ull -cm_name 0.chip_padctrl_attributes.692698897 |
| Directory | /workspace/0.chip_padctrl_attributes/latest |
| Test location | /workspace/coverage/cover_reg_top/0.chip_rv_dm_lc_disabled.1416636196 |
| Short name | T2718 |
| Test name | |
| Test status | |
| Simulation time | 14463547514 ps |
| CPU time | 855.45 seconds |
| Started | Jun 23 07:20:55 PM PDT 24 |
| Finished | Jun 23 07:35:11 PM PDT 24 |
| Peak memory | 588896 kb |
| Host | smart-d1d94dae-cf73-4bc6-92c2-befed419f3ac |
| User | root |
| Command | /workspace/cover_reg_top/simv +en_scb=0 +en_scb_tl_err_chk=0 +use_jtag_dmi=1 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1416636196 -assert nopostproc +UVM_TESTNAME=chip_base_t est +UVM_TEST_SEQ=chip_rv_dm_lc_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.chip_rv_dm_lc_disabled.1416636196 |
| Directory | /workspace/0.chip_rv_dm_lc_disabled/latest |
| Test location | /workspace/coverage/cover_reg_top/1.chip_csr_hw_reset.2574878175 |
| Short name | T128 |
| Test name | |
| Test status | |
| Simulation time | 4814490130 ps |
| CPU time | 279.59 seconds |
| Started | Jun 23 07:21:12 PM PDT 24 |
| Finished | Jun 23 07:25:51 PM PDT 24 |
| Peak memory | 662512 kb |
| Host | smart-ceceec96-edee-4303-a014-c6c84801c5e8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2574878175 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.chip_csr_hw_r eset.2574878175 |
| Directory | /workspace/1.chip_csr_hw_reset/latest |
| Test location | /workspace/coverage/default/0.chip_sw_csrng_edn_concurrency_reduced_freq.3609068799 |
| Short name | T107 |
| Test name | |
| Test status | |
| Simulation time | 26153387251 ps |
| CPU time | 5168.19 seconds |
| Started | Jun 23 07:54:10 PM PDT 24 |
| Finished | Jun 23 09:20:19 PM PDT 24 |
| Peak memory | 607096 kb |
| Host | smart-21661946-6f4f-4078-ac55-5282b6d24fa0 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=360_000_000 +rng_srate_value_min=15 +rng_srate_value_max=20 +cal_sys_clk_70mhz=1 +en_jitter=1 +accelerate_ cold_power_up_time=3 +accelerate_regulators_power_up_time=2 +sw_build_device=sim_dv +sw_images=csrng_edn_concurrency_test:1:new_rules,test_rom:0 + cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_ seed=3609068799 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_csrng_edn_concurrency_reduced_freq.3609068799 |
| Directory | /workspace/0.chip_sw_csrng_edn_concurrency_reduced_freq/latest |
| Test location | /workspace/coverage/default/0.chip_sw_edn_boot_mode.1802039309 |
| Short name | T686 |
| Test name | |
| Test status | |
| Simulation time | 2988688400 ps |
| CPU time | 431.85 seconds |
| Started | Jun 23 07:51:26 PM PDT 24 |
| Finished | Jun 23 07:58:39 PM PDT 24 |
| Peak memory | 607144 kb |
| Host | smart-4adafd55-c5af-473b-af73-e791d3a6b171 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +rng_srate_value=5 +accelerate_cold_power_up_time=3 +accelerate_regulators_power_up_time=2 +sw_ build_device=sim_dv +sw_images=edn_boot_mode:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1802039309 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ =chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_edn_ boot_mode.1802039309 |
| Directory | /workspace/0.chip_sw_edn_boot_mode/latest |
| Test location | /workspace/coverage/default/0.chip_sw_rv_core_ibex_lockstep_glitch.2083607268 |
| Short name | T385 |
| Test name | |
| Test status | |
| Simulation time | 2681350600 ps |
| CPU time | 293.64 seconds |
| Started | Jun 23 07:54:56 PM PDT 24 |
| Finished | Jun 23 07:59:50 PM PDT 24 |
| Peak memory | 636500 kb |
| Host | smart-9ae72ac7-f538-4dff-8db0-448de8ebb514 |
| User | root |
| Command | /workspace/default/simv +disable_assert_final_checks +sw_build_device=sim_dv +sw_images=aes_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2083607268 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rv_core_ibex_lockstep_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_rv_core_ibex_lockstep_glitch.2083607268 |
| Directory | /workspace/0.chip_sw_rv_core_ibex_lockstep_glitch/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_bad_b_good_dev.903335604 |
| Short name | T1287 |
| Test name | |
| Test status | |
| Simulation time | 24718608404 ps |
| CPU time | 5730.93 seconds |
| Started | Jun 23 07:57:32 PM PDT 24 |
| Finished | Jun 23 09:33:04 PM PDT 24 |
| Peak memory | 607084 kb |
| Host | smart-cec1bebf-5827-4a38-9624-cb90aaf8fed7 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_corrupted:1: ot_flash_binary:signed:fake_ecdsa_prod_key_0,empty_test_slot_b_fake_ecdsa_prod_key_0:2:ot_flash_binary,otp_img_boot_policy_valid_dev:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=903335604 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_boot_policy_valid_a_bad_b_good_dev.903335604 |
| Directory | /workspace/0.rom_e2e_boot_policy_valid_a_bad_b_good_dev/latest |
| Test location | /workspace/coverage/cover_reg_top/0.chip_csr_aliasing.1039649334 |
| Short name | T717 |
| Test name | |
| Test status | |
| Simulation time | 56041238111 ps |
| CPU time | 9649.8 seconds |
| Started | Jun 23 07:20:54 PM PDT 24 |
| Finished | Jun 23 10:01:45 PM PDT 24 |
| Peak memory | 633184 kb |
| Host | smart-3e6df8e7-b79b-45c1-972d-21a2eebbf16c |
| User | root |
| Command | /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +csr_aliasing +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1039649334 -assert nopostproc +UVM_TESTNAME=chip_ base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/ null -cm_name 0.chip_csr_aliasing.1039649334 |
| Directory | /workspace/0.chip_csr_aliasing/latest |
| Test location | /workspace/coverage/cover_reg_top/0.chip_csr_bit_bash.2152251802 |
| Short name | T2069 |
| Test name | |
| Test status | |
| Simulation time | 6872618627 ps |
| CPU time | 637.21 seconds |
| Started | Jun 23 07:20:53 PM PDT 24 |
| Finished | Jun 23 07:31:31 PM PDT 24 |
| Peak memory | 589040 kb |
| Host | smart-9bddab13-36d9-4f48-abcf-944f01e9fe85 |
| User | root |
| Command | /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +num_test_csrs=200 +csr_bit_bash +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2152251802 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to p.vdb -cm_log /dev/null -cm_name 0.chip_csr_bit_bash.2152251802 |
| Directory | /workspace/0.chip_csr_bit_bash/latest |
| Test location | /workspace/coverage/cover_reg_top/0.chip_csr_hw_reset.1385507565 |
| Short name | T137 |
| Test name | |
| Test status | |
| Simulation time | 4582710858 ps |
| CPU time | 240.24 seconds |
| Started | Jun 23 07:21:02 PM PDT 24 |
| Finished | Jun 23 07:25:02 PM PDT 24 |
| Peak memory | 662932 kb |
| Host | smart-4ffb4d24-785e-4eb4-a551-7924a5a60618 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1385507565 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.chip_csr_hw_r eset.1385507565 |
| Directory | /workspace/0.chip_csr_hw_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/0.chip_csr_rw.1460617591 |
| Short name | T716 |
| Test name | |
| Test status | |
| Simulation time | 4319081270 ps |
| CPU time | 375.8 seconds |
| Started | Jun 23 07:21:15 PM PDT 24 |
| Finished | Jun 23 07:27:31 PM PDT 24 |
| Peak memory | 594648 kb |
| Host | smart-033ff40c-639b-4287-a8c3-d245fcccc598 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1460617591 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.chip_csr_rw.1460617591 |
| Directory | /workspace/0.chip_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/0.chip_prim_tl_access.2518323207 |
| Short name | T2117 |
| Test name | |
| Test status | |
| Simulation time | 13954556828 ps |
| CPU time | 534.52 seconds |
| Started | Jun 23 07:21:00 PM PDT 24 |
| Finished | Jun 23 07:29:55 PM PDT 24 |
| Peak memory | 589992 kb |
| Host | smart-a65cc2f3-3819-42a7-b2d6-a6423785fb4d |
| User | root |
| Command | /workspace/cover_reg_top/simv +en_scb=0 +en_scb_tl_err_chk=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2518323207 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SE Q=chip_prim_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.chip_prim_tl_access.2518323207 |
| Directory | /workspace/0.chip_prim_tl_access/latest |
| Test location | /workspace/coverage/cover_reg_top/0.chip_same_csr_outstanding.3629938333 |
| Short name | T2440 |
| Test name | |
| Test status | |
| Simulation time | 32243613546 ps |
| CPU time | 4248.73 seconds |
| Started | Jun 23 07:20:58 PM PDT 24 |
| Finished | Jun 23 08:31:48 PM PDT 24 |
| Peak memory | 591196 kb |
| Host | smart-787eddcc-eef0-4854-a4d3-4635e658bc0a |
| User | root |
| Command | /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +run_same_csr_outstanding +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3629938333 -assert nopostproc +UVM_TE STNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb - cm_log /dev/null -cm_name 0.chip_same_csr_outstanding.3629938333 |
| Directory | /workspace/0.chip_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/0.chip_tl_errors.2261584454 |
| Short name | T673 |
| Test name | |
| Test status | |
| Simulation time | 3291377556 ps |
| CPU time | 215 seconds |
| Started | Jun 23 07:20:52 PM PDT 24 |
| Finished | Jun 23 07:24:28 PM PDT 24 |
| Peak memory | 596456 kb |
| Host | smart-e49cbb33-3e18-4912-9ab8-965a1b295ab6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2261584454 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.chip_tl_errors.2261584454 |
| Directory | /workspace/0.chip_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/0.xbar_access_same_device.2586809240 |
| Short name | T2037 |
| Test name | |
| Test status | |
| Simulation time | 452276993 ps |
| CPU time | 30.39 seconds |
| Started | Jun 23 07:20:56 PM PDT 24 |
| Finished | Jun 23 07:21:27 PM PDT 24 |
| Peak memory | 574076 kb |
| Host | smart-f6dc2630-c09c-4057-9c1e-1ac81e11bb7a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2586809240 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.xbar_access_same_device. 2586809240 |
| Directory | /workspace/0.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/0.xbar_access_same_device_slow_rsp.1839069345 |
| Short name | T2525 |
| Test name | |
| Test status | |
| Simulation time | 20404980325 ps |
| CPU time | 344.03 seconds |
| Started | Jun 23 07:20:56 PM PDT 24 |
| Finished | Jun 23 07:26:41 PM PDT 24 |
| Peak memory | 574224 kb |
| Host | smart-26bc0c59-51fc-4c4a-9dc6-5a85df4cdfb0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1839069345 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.xbar_access_same_d evice_slow_rsp.1839069345 |
| Directory | /workspace/0.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/0.xbar_error_and_unmapped_addr.1726534297 |
| Short name | T1781 |
| Test name | |
| Test status | |
| Simulation time | 728577477 ps |
| CPU time | 29.86 seconds |
| Started | Jun 23 07:21:00 PM PDT 24 |
| Finished | Jun 23 07:21:30 PM PDT 24 |
| Peak memory | 573704 kb |
| Host | smart-eba59e37-bf76-4f83-b04c-068aa86b92c9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1726534297 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.xbar_error_and_unmapped_addr .1726534297 |
| Directory | /workspace/0.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/0.xbar_error_random.2285060430 |
| Short name | T2106 |
| Test name | |
| Test status | |
| Simulation time | 743114681 ps |
| CPU time | 26.58 seconds |
| Started | Jun 23 07:21:04 PM PDT 24 |
| Finished | Jun 23 07:21:31 PM PDT 24 |
| Peak memory | 573736 kb |
| Host | smart-258a9bf5-febe-4a48-a20d-82e56f59f280 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2285060430 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.xbar_error_random.2285060430 |
| Directory | /workspace/0.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/0.xbar_random.3746708208 |
| Short name | T2396 |
| Test name | |
| Test status | |
| Simulation time | 1466687492 ps |
| CPU time | 48.3 seconds |
| Started | Jun 23 07:20:56 PM PDT 24 |
| Finished | Jun 23 07:21:45 PM PDT 24 |
| Peak memory | 573392 kb |
| Host | smart-9d234858-c072-43a6-b5cd-691852736841 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3746708208 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.xbar_random.3746708208 |
| Directory | /workspace/0.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/0.xbar_random_large_delays.410347294 |
| Short name | T669 |
| Test name | |
| Test status | |
| Simulation time | 54335890394 ps |
| CPU time | 616.12 seconds |
| Started | Jun 23 07:20:54 PM PDT 24 |
| Finished | Jun 23 07:31:11 PM PDT 24 |
| Peak memory | 574204 kb |
| Host | smart-4addcdc2-7a41-4b36-b1dd-544b9960133e |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=410347294 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.xbar_random_large_delays.410347294 |
| Directory | /workspace/0.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/0.xbar_random_slow_rsp.1136347558 |
| Short name | T1846 |
| Test name | |
| Test status | |
| Simulation time | 27267255183 ps |
| CPU time | 457.72 seconds |
| Started | Jun 23 07:20:56 PM PDT 24 |
| Finished | Jun 23 07:28:34 PM PDT 24 |
| Peak memory | 573512 kb |
| Host | smart-3d4caea6-cb3a-4b11-b979-7cbf33365cb2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1136347558 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.xbar_random_slow_rsp.1136347558 |
| Directory | /workspace/0.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/0.xbar_random_zero_delays.327836775 |
| Short name | T1678 |
| Test name | |
| Test status | |
| Simulation time | 246971918 ps |
| CPU time | 23.53 seconds |
| Started | Jun 23 07:20:54 PM PDT 24 |
| Finished | Jun 23 07:21:18 PM PDT 24 |
| Peak memory | 574072 kb |
| Host | smart-7c3292ee-7ae3-4630-98c5-e544a04dcfc6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=327836775 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.xbar_random_zero_delay s.327836775 |
| Directory | /workspace/0.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/0.xbar_same_source.2797221223 |
| Short name | T2309 |
| Test name | |
| Test status | |
| Simulation time | 530127194 ps |
| CPU time | 16.97 seconds |
| Started | Jun 23 07:20:57 PM PDT 24 |
| Finished | Jun 23 07:21:14 PM PDT 24 |
| Peak memory | 574092 kb |
| Host | smart-f93587c0-87bf-4657-9964-86ec69bcb6d6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2797221223 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.xbar_same_source.2797221223 |
| Directory | /workspace/0.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/0.xbar_smoke.3028448448 |
| Short name | T1732 |
| Test name | |
| Test status | |
| Simulation time | 169484310 ps |
| CPU time | 8.44 seconds |
| Started | Jun 23 07:20:55 PM PDT 24 |
| Finished | Jun 23 07:21:04 PM PDT 24 |
| Peak memory | 565128 kb |
| Host | smart-35dd2672-6a56-48c1-8faa-e498541bbe09 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3028448448 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.xbar_smoke.3028448448 |
| Directory | /workspace/0.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/0.xbar_smoke_large_delays.1887857195 |
| Short name | T2794 |
| Test name | |
| Test status | |
| Simulation time | 8460225847 ps |
| CPU time | 86.54 seconds |
| Started | Jun 23 07:20:56 PM PDT 24 |
| Finished | Jun 23 07:22:24 PM PDT 24 |
| Peak memory | 565260 kb |
| Host | smart-318ff3ae-3893-42a3-b5c5-e45f3d51f08e |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1887857195 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.xbar_smoke_large_delays.1887857195 |
| Directory | /workspace/0.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/0.xbar_smoke_slow_rsp.2869216109 |
| Short name | T2544 |
| Test name | |
| Test status | |
| Simulation time | 5753396206 ps |
| CPU time | 98.83 seconds |
| Started | Jun 23 07:20:57 PM PDT 24 |
| Finished | Jun 23 07:22:36 PM PDT 24 |
| Peak memory | 565900 kb |
| Host | smart-400f7649-7172-4386-a16c-b19c0b5f18d9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2869216109 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.xbar_smoke_slow_rsp.2869216109 |
| Directory | /workspace/0.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/0.xbar_smoke_zero_delays.3905948783 |
| Short name | T1402 |
| Test name | |
| Test status | |
| Simulation time | 41280986 ps |
| CPU time | 6 seconds |
| Started | Jun 23 07:20:58 PM PDT 24 |
| Finished | Jun 23 07:21:05 PM PDT 24 |
| Peak memory | 565444 kb |
| Host | smart-2437e5df-d53f-47b5-b47f-a903ee39e95a |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3905948783 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.xbar_smoke_zero_delays .3905948783 |
| Directory | /workspace/0.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/0.xbar_stress_all.3436852985 |
| Short name | T2880 |
| Test name | |
| Test status | |
| Simulation time | 1979001497 ps |
| CPU time | 157.46 seconds |
| Started | Jun 23 07:21:00 PM PDT 24 |
| Finished | Jun 23 07:23:38 PM PDT 24 |
| Peak memory | 574244 kb |
| Host | smart-5b501690-5e20-4f55-9442-c2948de99130 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3436852985 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.xbar_stress_all.3436852985 |
| Directory | /workspace/0.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/0.xbar_stress_all_with_error.430935898 |
| Short name | T2571 |
| Test name | |
| Test status | |
| Simulation time | 11362685693 ps |
| CPU time | 373.22 seconds |
| Started | Jun 23 07:21:01 PM PDT 24 |
| Finished | Jun 23 07:27:14 PM PDT 24 |
| Peak memory | 574372 kb |
| Host | smart-a98676c1-3172-4d48-9e8b-a0bdc3cf481b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=430935898 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.xbar_stress_all_with_error.430935898 |
| Directory | /workspace/0.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/0.xbar_stress_all_with_rand_reset.1157557708 |
| Short name | T519 |
| Test name | |
| Test status | |
| Simulation time | 2287820956 ps |
| CPU time | 350.47 seconds |
| Started | Jun 23 07:21:00 PM PDT 24 |
| Finished | Jun 23 07:26:50 PM PDT 24 |
| Peak memory | 574280 kb |
| Host | smart-b721d0cf-5340-4aae-9f1b-9850889989a4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1157557708 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.xbar_stress_all_ with_rand_reset.1157557708 |
| Directory | /workspace/0.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/0.xbar_stress_all_with_reset_error.2135420234 |
| Short name | T869 |
| Test name | |
| Test status | |
| Simulation time | 24168465557 ps |
| CPU time | 1059.42 seconds |
| Started | Jun 23 07:21:00 PM PDT 24 |
| Finished | Jun 23 07:38:40 PM PDT 24 |
| Peak memory | 582284 kb |
| Host | smart-f9d11366-5895-4a62-b864-9652b14db269 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2135420234 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.xbar_stress_all _with_reset_error.2135420234 |
| Directory | /workspace/0.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/0.xbar_unmapped_addr.3718109193 |
| Short name | T1978 |
| Test name | |
| Test status | |
| Simulation time | 39540422 ps |
| CPU time | 7.54 seconds |
| Started | Jun 23 07:21:01 PM PDT 24 |
| Finished | Jun 23 07:21:09 PM PDT 24 |
| Peak memory | 565272 kb |
| Host | smart-3e42328f-c7f4-4f51-95da-0520156aebff |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3718109193 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.xbar_unmapped_addr.3718109193 |
| Directory | /workspace/0.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/1.chip_csr_aliasing.342507250 |
| Short name | T1664 |
| Test name | |
| Test status | |
| Simulation time | 56501650441 ps |
| CPU time | 9746.15 seconds |
| Started | Jun 23 07:21:05 PM PDT 24 |
| Finished | Jun 23 10:03:32 PM PDT 24 |
| Peak memory | 635068 kb |
| Host | smart-2acdaef1-05a1-436c-a88f-350b4871f244 |
| User | root |
| Command | /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +csr_aliasing +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=342507250 -assert nopostproc +UVM_TESTNAME=chip_b ase_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/n ull -cm_name 1.chip_csr_aliasing.342507250 |
| Directory | /workspace/1.chip_csr_aliasing/latest |
| Test location | /workspace/coverage/cover_reg_top/1.chip_csr_bit_bash.2475875204 |
| Short name | T2855 |
| Test name | |
| Test status | |
| Simulation time | 5623341676 ps |
| CPU time | 449.58 seconds |
| Started | Jun 23 07:21:15 PM PDT 24 |
| Finished | Jun 23 07:28:45 PM PDT 24 |
| Peak memory | 589624 kb |
| Host | smart-4e23bc75-2ef7-4395-a723-77d4d718ee56 |
| User | root |
| Command | /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +num_test_csrs=200 +csr_bit_bash +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2475875204 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to p.vdb -cm_log /dev/null -cm_name 1.chip_csr_bit_bash.2475875204 |
| Directory | /workspace/1.chip_csr_bit_bash/latest |
| Test location | /workspace/coverage/cover_reg_top/1.chip_csr_rw.2692320385 |
| Short name | T2765 |
| Test name | |
| Test status | |
| Simulation time | 5307532473 ps |
| CPU time | 527.63 seconds |
| Started | Jun 23 07:21:19 PM PDT 24 |
| Finished | Jun 23 07:30:07 PM PDT 24 |
| Peak memory | 597160 kb |
| Host | smart-7b8fea2f-6732-4252-a677-55b14762ba83 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2692320385 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.chip_csr_rw.2692320385 |
| Directory | /workspace/1.chip_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/1.chip_prim_tl_access.336891857 |
| Short name | T1632 |
| Test name | |
| Test status | |
| Simulation time | 6211554880 ps |
| CPU time | 236.39 seconds |
| Started | Jun 23 07:21:04 PM PDT 24 |
| Finished | Jun 23 07:25:01 PM PDT 24 |
| Peak memory | 589016 kb |
| Host | smart-a700ed38-5a03-43e7-8388-c888b8052dea |
| User | root |
| Command | /workspace/cover_reg_top/simv +en_scb=0 +en_scb_tl_err_chk=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=336891857 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ =chip_prim_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1 .chip_prim_tl_access.336891857 |
| Directory | /workspace/1.chip_prim_tl_access/latest |
| Test location | /workspace/coverage/cover_reg_top/1.chip_rv_dm_lc_disabled.4266499573 |
| Short name | T1502 |
| Test name | |
| Test status | |
| Simulation time | 8282559601 ps |
| CPU time | 341.54 seconds |
| Started | Jun 23 07:21:16 PM PDT 24 |
| Finished | Jun 23 07:26:58 PM PDT 24 |
| Peak memory | 588896 kb |
| Host | smart-5a912d8d-1f22-4289-b38f-6b07eadaaa34 |
| User | root |
| Command | /workspace/cover_reg_top/simv +en_scb=0 +en_scb_tl_err_chk=0 +use_jtag_dmi=1 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4266499573 -assert nopostproc +UVM_TESTNAME=chip_base_t est +UVM_TEST_SEQ=chip_rv_dm_lc_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.chip_rv_dm_lc_disabled.4266499573 |
| Directory | /workspace/1.chip_rv_dm_lc_disabled/latest |
| Test location | /workspace/coverage/cover_reg_top/1.chip_same_csr_outstanding.3457442643 |
| Short name | T419 |
| Test name | |
| Test status | |
| Simulation time | 29456272842 ps |
| CPU time | 3803.61 seconds |
| Started | Jun 23 07:21:16 PM PDT 24 |
| Finished | Jun 23 08:24:40 PM PDT 24 |
| Peak memory | 591572 kb |
| Host | smart-601941cb-ea3b-4dcb-be96-7b3cf453bfa5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +run_same_csr_outstanding +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3457442643 -assert nopostproc +UVM_TE STNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb - cm_log /dev/null -cm_name 1.chip_same_csr_outstanding.3457442643 |
| Directory | /workspace/1.chip_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/1.chip_tl_errors.3942277563 |
| Short name | T2836 |
| Test name | |
| Test status | |
| Simulation time | 3286628992 ps |
| CPU time | 156.13 seconds |
| Started | Jun 23 07:21:07 PM PDT 24 |
| Finished | Jun 23 07:23:44 PM PDT 24 |
| Peak memory | 603520 kb |
| Host | smart-9b3143f4-b902-452a-b5f9-4b400cab46e9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3942277563 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.chip_tl_errors.3942277563 |
| Directory | /workspace/1.chip_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/1.xbar_access_same_device.53461001 |
| Short name | T2882 |
| Test name | |
| Test status | |
| Simulation time | 2666984270 ps |
| CPU time | 114.22 seconds |
| Started | Jun 23 07:21:07 PM PDT 24 |
| Finished | Jun 23 07:23:01 PM PDT 24 |
| Peak memory | 574208 kb |
| Host | smart-c4430c0e-086c-4c2d-b85d-0dfcae56f49f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53461001 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.xbar_access_same_device.53461001 |
| Directory | /workspace/1.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/1.xbar_access_same_device_slow_rsp.1114223284 |
| Short name | T2051 |
| Test name | |
| Test status | |
| Simulation time | 86931050365 ps |
| CPU time | 1467.85 seconds |
| Started | Jun 23 07:21:14 PM PDT 24 |
| Finished | Jun 23 07:45:42 PM PDT 24 |
| Peak memory | 574228 kb |
| Host | smart-5f8bf320-c69e-4148-93dc-ba86c35700b3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1114223284 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.xbar_access_same_d evice_slow_rsp.1114223284 |
| Directory | /workspace/1.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/1.xbar_error_and_unmapped_addr.3493074880 |
| Short name | T1448 |
| Test name | |
| Test status | |
| Simulation time | 315202804 ps |
| CPU time | 34.87 seconds |
| Started | Jun 23 07:21:06 PM PDT 24 |
| Finished | Jun 23 07:21:41 PM PDT 24 |
| Peak memory | 573376 kb |
| Host | smart-9fabaa0c-c61f-486c-af8d-179a927a69cb |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3493074880 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.xbar_error_and_unmapped_addr .3493074880 |
| Directory | /workspace/1.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/1.xbar_error_random.2677623350 |
| Short name | T2306 |
| Test name | |
| Test status | |
| Simulation time | 1382579995 ps |
| CPU time | 43.89 seconds |
| Started | Jun 23 07:21:08 PM PDT 24 |
| Finished | Jun 23 07:21:52 PM PDT 24 |
| Peak memory | 573692 kb |
| Host | smart-71a8ed94-4989-4c5a-8a37-aedf0a67a6b4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2677623350 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.xbar_error_random.2677623350 |
| Directory | /workspace/1.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/1.xbar_random.3691746128 |
| Short name | T604 |
| Test name | |
| Test status | |
| Simulation time | 2039740875 ps |
| CPU time | 70.7 seconds |
| Started | Jun 23 07:21:02 PM PDT 24 |
| Finished | Jun 23 07:22:13 PM PDT 24 |
| Peak memory | 574160 kb |
| Host | smart-5509a7ba-9955-4fa0-81ed-e48eed8299cd |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3691746128 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.xbar_random.3691746128 |
| Directory | /workspace/1.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/1.xbar_random_large_delays.2720715287 |
| Short name | T1871 |
| Test name | |
| Test status | |
| Simulation time | 72996041124 ps |
| CPU time | 781.17 seconds |
| Started | Jun 23 07:21:05 PM PDT 24 |
| Finished | Jun 23 07:34:07 PM PDT 24 |
| Peak memory | 574144 kb |
| Host | smart-5c647c88-c614-4791-b9b5-4b716b86fbeb |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2720715287 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.xbar_random_large_delays.2720715287 |
| Directory | /workspace/1.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/1.xbar_random_slow_rsp.3643948202 |
| Short name | T1818 |
| Test name | |
| Test status | |
| Simulation time | 26179113701 ps |
| CPU time | 419.08 seconds |
| Started | Jun 23 07:21:14 PM PDT 24 |
| Finished | Jun 23 07:28:13 PM PDT 24 |
| Peak memory | 574152 kb |
| Host | smart-934362c3-4ab3-4682-8fce-8134607b389f |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3643948202 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.xbar_random_slow_rsp.3643948202 |
| Directory | /workspace/1.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/1.xbar_random_zero_delays.3736786907 |
| Short name | T655 |
| Test name | |
| Test status | |
| Simulation time | 306577682 ps |
| CPU time | 30.74 seconds |
| Started | Jun 23 07:21:11 PM PDT 24 |
| Finished | Jun 23 07:21:42 PM PDT 24 |
| Peak memory | 574072 kb |
| Host | smart-fb0409c9-fee8-4356-acba-c72ea4723ba4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3736786907 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.xbar_random_zero_dela ys.3736786907 |
| Directory | /workspace/1.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/1.xbar_same_source.97203531 |
| Short name | T2828 |
| Test name | |
| Test status | |
| Simulation time | 195295322 ps |
| CPU time | 17.76 seconds |
| Started | Jun 23 07:21:04 PM PDT 24 |
| Finished | Jun 23 07:21:22 PM PDT 24 |
| Peak memory | 574064 kb |
| Host | smart-c2e9a19f-4341-48d2-bb1c-112dedbfe71b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97203531 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.xbar_same_source.97203531 |
| Directory | /workspace/1.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/1.xbar_smoke.3915763826 |
| Short name | T1959 |
| Test name | |
| Test status | |
| Simulation time | 37813376 ps |
| CPU time | 6.07 seconds |
| Started | Jun 23 07:21:11 PM PDT 24 |
| Finished | Jun 23 07:21:18 PM PDT 24 |
| Peak memory | 565528 kb |
| Host | smart-dd819fe1-3ff9-4fa4-9613-7a12594f812e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3915763826 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.xbar_smoke.3915763826 |
| Directory | /workspace/1.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/1.xbar_smoke_large_delays.744696130 |
| Short name | T614 |
| Test name | |
| Test status | |
| Simulation time | 7732840964 ps |
| CPU time | 75.67 seconds |
| Started | Jun 23 07:21:15 PM PDT 24 |
| Finished | Jun 23 07:22:31 PM PDT 24 |
| Peak memory | 565932 kb |
| Host | smart-14df7093-e4a7-4574-9cbb-78fd10454f31 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=744696130 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.xbar_smoke_large_delays.744696130 |
| Directory | /workspace/1.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/1.xbar_smoke_slow_rsp.2542175515 |
| Short name | T1439 |
| Test name | |
| Test status | |
| Simulation time | 5255018206 ps |
| CPU time | 82.61 seconds |
| Started | Jun 23 07:21:14 PM PDT 24 |
| Finished | Jun 23 07:22:37 PM PDT 24 |
| Peak memory | 565904 kb |
| Host | smart-46b26bc0-75a4-4575-b9ef-50265fa1cfed |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2542175515 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.xbar_smoke_slow_rsp.2542175515 |
| Directory | /workspace/1.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/1.xbar_smoke_zero_delays.2690601917 |
| Short name | T2553 |
| Test name | |
| Test status | |
| Simulation time | 45531513 ps |
| CPU time | 6.1 seconds |
| Started | Jun 23 07:21:11 PM PDT 24 |
| Finished | Jun 23 07:21:17 PM PDT 24 |
| Peak memory | 573320 kb |
| Host | smart-e1b4214d-7c50-42f7-a22e-9eb45b82363f |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2690601917 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.xbar_smoke_zero_delays .2690601917 |
| Directory | /workspace/1.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/1.xbar_stress_all.2646560641 |
| Short name | T2705 |
| Test name | |
| Test status | |
| Simulation time | 1524610364 ps |
| CPU time | 120.09 seconds |
| Started | Jun 23 07:21:12 PM PDT 24 |
| Finished | Jun 23 07:23:12 PM PDT 24 |
| Peak memory | 574240 kb |
| Host | smart-0b7dd9ba-03c4-4b98-9273-4e39887b579c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2646560641 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.xbar_stress_all.2646560641 |
| Directory | /workspace/1.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/1.xbar_stress_all_with_error.226045366 |
| Short name | T1802 |
| Test name | |
| Test status | |
| Simulation time | 434292676 ps |
| CPU time | 32.23 seconds |
| Started | Jun 23 07:21:09 PM PDT 24 |
| Finished | Jun 23 07:21:42 PM PDT 24 |
| Peak memory | 573704 kb |
| Host | smart-82c061e6-de76-480f-aec0-f018f1093598 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=226045366 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.xbar_stress_all_with_error.226045366 |
| Directory | /workspace/1.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/1.xbar_stress_all_with_rand_reset.194219802 |
| Short name | T2854 |
| Test name | |
| Test status | |
| Simulation time | 232090644 ps |
| CPU time | 136.87 seconds |
| Started | Jun 23 07:21:07 PM PDT 24 |
| Finished | Jun 23 07:23:24 PM PDT 24 |
| Peak memory | 574192 kb |
| Host | smart-382c325c-67c0-4698-bc3f-bff499f1005c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=194219802 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_res et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.xbar_stress_all_w ith_rand_reset.194219802 |
| Directory | /workspace/1.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/1.xbar_unmapped_addr.3185922044 |
| Short name | T1788 |
| Test name | |
| Test status | |
| Simulation time | 134852304 ps |
| CPU time | 16.84 seconds |
| Started | Jun 23 07:21:03 PM PDT 24 |
| Finished | Jun 23 07:21:20 PM PDT 24 |
| Peak memory | 574124 kb |
| Host | smart-bf0f5477-8993-4489-a757-d43cf9b65f8b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3185922044 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.xbar_unmapped_addr.3185922044 |
| Directory | /workspace/1.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/10.chip_csr_rw.2651038271 |
| Short name | T700 |
| Test name | |
| Test status | |
| Simulation time | 5297489146 ps |
| CPU time | 556.7 seconds |
| Started | Jun 23 07:23:21 PM PDT 24 |
| Finished | Jun 23 07:32:39 PM PDT 24 |
| Peak memory | 596880 kb |
| Host | smart-35283fdb-67b2-4780-acea-031c4435cb9d |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2651038271 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.chip_csr_rw.2651038271 |
| Directory | /workspace/10.chip_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/10.chip_same_csr_outstanding.1034986502 |
| Short name | T387 |
| Test name | |
| Test status | |
| Simulation time | 16746720417 ps |
| CPU time | 1788.34 seconds |
| Started | Jun 23 07:22:59 PM PDT 24 |
| Finished | Jun 23 07:52:48 PM PDT 24 |
| Peak memory | 591148 kb |
| Host | smart-56d20452-2dd5-4a99-a20f-98bd5ee3f794 |
| User | root |
| Command | /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +run_same_csr_outstanding +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1034986502 -assert nopostproc +UVM_TE STNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb - cm_log /dev/null -cm_name 10.chip_same_csr_outstanding.1034986502 |
| Directory | /workspace/10.chip_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/10.xbar_access_same_device.349464483 |
| Short name | T1652 |
| Test name | |
| Test status | |
| Simulation time | 853228274 ps |
| CPU time | 38.27 seconds |
| Started | Jun 23 07:23:01 PM PDT 24 |
| Finished | Jun 23 07:23:39 PM PDT 24 |
| Peak memory | 574084 kb |
| Host | smart-7b2e7487-c386-4b34-8176-e89ebb7b5dd3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=349464483 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.xbar_access_same_device. 349464483 |
| Directory | /workspace/10.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/10.xbar_access_same_device_slow_rsp.1409618041 |
| Short name | T2771 |
| Test name | |
| Test status | |
| Simulation time | 141602958570 ps |
| CPU time | 2710.15 seconds |
| Started | Jun 23 07:23:06 PM PDT 24 |
| Finished | Jun 23 08:08:17 PM PDT 24 |
| Peak memory | 574228 kb |
| Host | smart-878e389e-eb47-4843-a97b-4c28d57143ef |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1409618041 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.xbar_access_same_ device_slow_rsp.1409618041 |
| Directory | /workspace/10.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/10.xbar_error_and_unmapped_addr.2545936554 |
| Short name | T2332 |
| Test name | |
| Test status | |
| Simulation time | 636890211 ps |
| CPU time | 23.51 seconds |
| Started | Jun 23 07:23:11 PM PDT 24 |
| Finished | Jun 23 07:23:35 PM PDT 24 |
| Peak memory | 573724 kb |
| Host | smart-3c77a766-bbfe-407f-bed3-e072ea1ac244 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2545936554 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.xbar_error_and_unmapped_add r.2545936554 |
| Directory | /workspace/10.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/10.xbar_error_random.4151134311 |
| Short name | T2869 |
| Test name | |
| Test status | |
| Simulation time | 1642548370 ps |
| CPU time | 52.88 seconds |
| Started | Jun 23 07:23:11 PM PDT 24 |
| Finished | Jun 23 07:24:04 PM PDT 24 |
| Peak memory | 573744 kb |
| Host | smart-ca3a62ce-f869-479c-9524-59b82df1aa05 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4151134311 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.xbar_error_random.4151134311 |
| Directory | /workspace/10.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/10.xbar_random.2138996803 |
| Short name | T1442 |
| Test name | |
| Test status | |
| Simulation time | 121564212 ps |
| CPU time | 8.06 seconds |
| Started | Jun 23 07:22:58 PM PDT 24 |
| Finished | Jun 23 07:23:06 PM PDT 24 |
| Peak memory | 565868 kb |
| Host | smart-5d6d9225-0b4a-4978-a76f-bafe3d3f6d56 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2138996803 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.xbar_random.2138996803 |
| Directory | /workspace/10.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/10.xbar_random_large_delays.1432313681 |
| Short name | T535 |
| Test name | |
| Test status | |
| Simulation time | 38019138258 ps |
| CPU time | 375.73 seconds |
| Started | Jun 23 07:23:01 PM PDT 24 |
| Finished | Jun 23 07:29:17 PM PDT 24 |
| Peak memory | 573436 kb |
| Host | smart-119fddc3-5983-4c15-9304-4755a9de3f9e |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1432313681 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.xbar_random_large_delays.1432313681 |
| Directory | /workspace/10.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/10.xbar_random_slow_rsp.3562288653 |
| Short name | T1722 |
| Test name | |
| Test status | |
| Simulation time | 12328407155 ps |
| CPU time | 217.66 seconds |
| Started | Jun 23 07:23:01 PM PDT 24 |
| Finished | Jun 23 07:26:39 PM PDT 24 |
| Peak memory | 573524 kb |
| Host | smart-965b74d8-55e0-40e4-bfbe-2143d2316ab2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3562288653 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.xbar_random_slow_rsp.3562288653 |
| Directory | /workspace/10.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/10.xbar_random_zero_delays.832159056 |
| Short name | T2236 |
| Test name | |
| Test status | |
| Simulation time | 454335768 ps |
| CPU time | 34.49 seconds |
| Started | Jun 23 07:23:01 PM PDT 24 |
| Finished | Jun 23 07:23:36 PM PDT 24 |
| Peak memory | 574064 kb |
| Host | smart-0b32d4d2-f81f-4958-b417-a3c002518466 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=832159056 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.xbar_random_zero_dela ys.832159056 |
| Directory | /workspace/10.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/10.xbar_same_source.1522088581 |
| Short name | T2404 |
| Test name | |
| Test status | |
| Simulation time | 2055941230 ps |
| CPU time | 62.34 seconds |
| Started | Jun 23 07:23:10 PM PDT 24 |
| Finished | Jun 23 07:24:13 PM PDT 24 |
| Peak memory | 574040 kb |
| Host | smart-24db7766-4cac-4bf4-a3bb-f4f8e24e4a38 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1522088581 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.xbar_same_source.1522088581 |
| Directory | /workspace/10.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/10.xbar_smoke.2670224969 |
| Short name | T1365 |
| Test name | |
| Test status | |
| Simulation time | 234291344 ps |
| CPU time | 10.52 seconds |
| Started | Jun 23 07:22:56 PM PDT 24 |
| Finished | Jun 23 07:23:07 PM PDT 24 |
| Peak memory | 565192 kb |
| Host | smart-44bf18a1-a7f2-4f68-b53d-fd55c15d1f9c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2670224969 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.xbar_smoke.2670224969 |
| Directory | /workspace/10.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/10.xbar_smoke_large_delays.2129733334 |
| Short name | T2602 |
| Test name | |
| Test status | |
| Simulation time | 8921290298 ps |
| CPU time | 88.74 seconds |
| Started | Jun 23 07:22:57 PM PDT 24 |
| Finished | Jun 23 07:24:26 PM PDT 24 |
| Peak memory | 565916 kb |
| Host | smart-a09e070a-af6a-407f-8910-89ddda7c6a33 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2129733334 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.xbar_smoke_large_delays.2129733334 |
| Directory | /workspace/10.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/10.xbar_smoke_slow_rsp.990034819 |
| Short name | T2222 |
| Test name | |
| Test status | |
| Simulation time | 4985118941 ps |
| CPU time | 86.66 seconds |
| Started | Jun 23 07:22:58 PM PDT 24 |
| Finished | Jun 23 07:24:25 PM PDT 24 |
| Peak memory | 565936 kb |
| Host | smart-6484cb0e-dc95-485b-8fe1-6d857909b14b |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=990034819 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.xbar_smoke_slow_rsp.990034819 |
| Directory | /workspace/10.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/10.xbar_smoke_zero_delays.2122295549 |
| Short name | T2165 |
| Test name | |
| Test status | |
| Simulation time | 42821473 ps |
| CPU time | 6.01 seconds |
| Started | Jun 23 07:22:56 PM PDT 24 |
| Finished | Jun 23 07:23:02 PM PDT 24 |
| Peak memory | 573292 kb |
| Host | smart-87f988db-f1a9-4f89-bea2-ec5a17c781d8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2122295549 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.xbar_smoke_zero_delay s.2122295549 |
| Directory | /workspace/10.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/10.xbar_stress_all_with_error.478014482 |
| Short name | T1539 |
| Test name | |
| Test status | |
| Simulation time | 5167798157 ps |
| CPU time | 177.69 seconds |
| Started | Jun 23 07:23:18 PM PDT 24 |
| Finished | Jun 23 07:26:16 PM PDT 24 |
| Peak memory | 574348 kb |
| Host | smart-219281f2-9018-48ee-a4e7-ee7a25cbf52b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=478014482 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.xbar_stress_all_with_error.478014482 |
| Directory | /workspace/10.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/10.xbar_stress_all_with_rand_reset.1155884973 |
| Short name | T2313 |
| Test name | |
| Test status | |
| Simulation time | 184854925 ps |
| CPU time | 50.41 seconds |
| Started | Jun 23 07:23:22 PM PDT 24 |
| Finished | Jun 23 07:24:12 PM PDT 24 |
| Peak memory | 576420 kb |
| Host | smart-be9daf20-556f-454c-beb4-1fae49cf1984 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1155884973 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.xbar_stress_all _with_rand_reset.1155884973 |
| Directory | /workspace/10.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/10.xbar_stress_all_with_reset_error.2856226016 |
| Short name | T2581 |
| Test name | |
| Test status | |
| Simulation time | 6867059189 ps |
| CPU time | 499.89 seconds |
| Started | Jun 23 07:23:18 PM PDT 24 |
| Finished | Jun 23 07:31:38 PM PDT 24 |
| Peak memory | 576436 kb |
| Host | smart-a9c9295f-32bb-49c6-a8ad-cb587a09c27e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2856226016 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.xbar_stress_al l_with_reset_error.2856226016 |
| Directory | /workspace/10.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/10.xbar_unmapped_addr.3593185326 |
| Short name | T2459 |
| Test name | |
| Test status | |
| Simulation time | 251249166 ps |
| CPU time | 30.73 seconds |
| Started | Jun 23 07:23:11 PM PDT 24 |
| Finished | Jun 23 07:23:42 PM PDT 24 |
| Peak memory | 574148 kb |
| Host | smart-0ebbf450-b661-4aae-96e7-7a3877d8a055 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3593185326 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.xbar_unmapped_addr.3593185326 |
| Directory | /workspace/10.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/11.chip_csr_rw.2055487580 |
| Short name | T701 |
| Test name | |
| Test status | |
| Simulation time | 6756459300 ps |
| CPU time | 550.71 seconds |
| Started | Jun 23 07:23:41 PM PDT 24 |
| Finished | Jun 23 07:32:52 PM PDT 24 |
| Peak memory | 595524 kb |
| Host | smart-ca2a8b4b-8647-4017-87c2-11214cb13f81 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2055487580 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.chip_csr_rw.2055487580 |
| Directory | /workspace/11.chip_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/11.xbar_access_same_device.196672368 |
| Short name | T2825 |
| Test name | |
| Test status | |
| Simulation time | 2201694866 ps |
| CPU time | 80.99 seconds |
| Started | Jun 23 07:23:40 PM PDT 24 |
| Finished | Jun 23 07:25:01 PM PDT 24 |
| Peak memory | 574136 kb |
| Host | smart-f4b033e4-95df-4a36-9f90-d7486abb4015 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=196672368 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.xbar_access_same_device. 196672368 |
| Directory | /workspace/11.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/11.xbar_access_same_device_slow_rsp.1968855580 |
| Short name | T2838 |
| Test name | |
| Test status | |
| Simulation time | 78925831385 ps |
| CPU time | 1313.91 seconds |
| Started | Jun 23 07:23:28 PM PDT 24 |
| Finished | Jun 23 07:45:23 PM PDT 24 |
| Peak memory | 573528 kb |
| Host | smart-0d0cd0c1-0f6b-4254-9941-97522b460082 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1968855580 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.xbar_access_same_ device_slow_rsp.1968855580 |
| Directory | /workspace/11.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/11.xbar_error_and_unmapped_addr.2336714708 |
| Short name | T1700 |
| Test name | |
| Test status | |
| Simulation time | 315131064 ps |
| CPU time | 32.42 seconds |
| Started | Jun 23 07:23:41 PM PDT 24 |
| Finished | Jun 23 07:24:14 PM PDT 24 |
| Peak memory | 573744 kb |
| Host | smart-7fa4e1c7-378a-4fc9-a614-38dc4ccf0e60 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2336714708 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.xbar_error_and_unmapped_add r.2336714708 |
| Directory | /workspace/11.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/11.xbar_error_random.2744012291 |
| Short name | T1677 |
| Test name | |
| Test status | |
| Simulation time | 72270908 ps |
| CPU time | 9.36 seconds |
| Started | Jun 23 07:23:34 PM PDT 24 |
| Finished | Jun 23 07:23:44 PM PDT 24 |
| Peak memory | 573720 kb |
| Host | smart-999a2cff-a736-481e-8ed3-a0c8a11dc0fb |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2744012291 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.xbar_error_random.2744012291 |
| Directory | /workspace/11.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/11.xbar_random.1759857818 |
| Short name | T553 |
| Test name | |
| Test status | |
| Simulation time | 1049234810 ps |
| CPU time | 34.75 seconds |
| Started | Jun 23 07:24:31 PM PDT 24 |
| Finished | Jun 23 07:25:07 PM PDT 24 |
| Peak memory | 573440 kb |
| Host | smart-afe07e50-0105-4801-9d2b-05e4f4a4d6b2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1759857818 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.xbar_random.1759857818 |
| Directory | /workspace/11.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/11.xbar_random_large_delays.3694513462 |
| Short name | T543 |
| Test name | |
| Test status | |
| Simulation time | 78710614409 ps |
| CPU time | 786.55 seconds |
| Started | Jun 23 07:23:40 PM PDT 24 |
| Finished | Jun 23 07:36:47 PM PDT 24 |
| Peak memory | 574200 kb |
| Host | smart-a82140ec-7841-4cec-99b7-27c0b7956445 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3694513462 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.xbar_random_large_delays.3694513462 |
| Directory | /workspace/11.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/11.xbar_random_slow_rsp.2544377603 |
| Short name | T1883 |
| Test name | |
| Test status | |
| Simulation time | 11194920730 ps |
| CPU time | 188.93 seconds |
| Started | Jun 23 07:23:40 PM PDT 24 |
| Finished | Jun 23 07:26:50 PM PDT 24 |
| Peak memory | 574172 kb |
| Host | smart-8a4f0338-300e-4aaf-ab5f-a162c713b9c8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2544377603 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.xbar_random_slow_rsp.2544377603 |
| Directory | /workspace/11.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/11.xbar_random_zero_delays.2842221421 |
| Short name | T2425 |
| Test name | |
| Test status | |
| Simulation time | 385473108 ps |
| CPU time | 34.97 seconds |
| Started | Jun 23 07:23:32 PM PDT 24 |
| Finished | Jun 23 07:24:08 PM PDT 24 |
| Peak memory | 574108 kb |
| Host | smart-7854b6b6-912d-4b3f-b3c1-6409345e4f29 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2842221421 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.xbar_random_zero_del ays.2842221421 |
| Directory | /workspace/11.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/11.xbar_same_source.4216425995 |
| Short name | T2756 |
| Test name | |
| Test status | |
| Simulation time | 1763010910 ps |
| CPU time | 54.87 seconds |
| Started | Jun 23 07:23:38 PM PDT 24 |
| Finished | Jun 23 07:24:33 PM PDT 24 |
| Peak memory | 574092 kb |
| Host | smart-e56993bf-21e0-447a-b3fc-20935cded5d8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4216425995 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.xbar_same_source.4216425995 |
| Directory | /workspace/11.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/11.xbar_smoke.631436750 |
| Short name | T2563 |
| Test name | |
| Test status | |
| Simulation time | 189077500 ps |
| CPU time | 9.23 seconds |
| Started | Jun 23 07:23:19 PM PDT 24 |
| Finished | Jun 23 07:23:28 PM PDT 24 |
| Peak memory | 565516 kb |
| Host | smart-43de1e7c-1a01-47cc-b49a-ab5eb95a8ec1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=631436750 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.xbar_smoke.631436750 |
| Directory | /workspace/11.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/11.xbar_smoke_large_delays.4192953725 |
| Short name | T1373 |
| Test name | |
| Test status | |
| Simulation time | 8674879954 ps |
| CPU time | 89.81 seconds |
| Started | Jun 23 07:23:27 PM PDT 24 |
| Finished | Jun 23 07:24:57 PM PDT 24 |
| Peak memory | 565252 kb |
| Host | smart-e0a413e8-5528-455e-8d2e-98205d6cf171 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4192953725 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.xbar_smoke_large_delays.4192953725 |
| Directory | /workspace/11.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/11.xbar_smoke_slow_rsp.2525145569 |
| Short name | T2334 |
| Test name | |
| Test status | |
| Simulation time | 6268677091 ps |
| CPU time | 105.56 seconds |
| Started | Jun 23 07:23:23 PM PDT 24 |
| Finished | Jun 23 07:25:09 PM PDT 24 |
| Peak memory | 565236 kb |
| Host | smart-93e5cd34-0240-4689-bf23-7e8da961d2a9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2525145569 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.xbar_smoke_slow_rsp.2525145569 |
| Directory | /workspace/11.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/11.xbar_smoke_zero_delays.768348382 |
| Short name | T2288 |
| Test name | |
| Test status | |
| Simulation time | 51253511 ps |
| CPU time | 6.39 seconds |
| Started | Jun 23 07:23:26 PM PDT 24 |
| Finished | Jun 23 07:23:33 PM PDT 24 |
| Peak memory | 573380 kb |
| Host | smart-10996f2b-5f86-402a-aa76-a34c4c95f7c9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=768348382 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.xbar_smoke_zero_delays .768348382 |
| Directory | /workspace/11.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/11.xbar_stress_all.61791020 |
| Short name | T1985 |
| Test name | |
| Test status | |
| Simulation time | 12826501100 ps |
| CPU time | 554.46 seconds |
| Started | Jun 23 07:23:36 PM PDT 24 |
| Finished | Jun 23 07:32:51 PM PDT 24 |
| Peak memory | 574272 kb |
| Host | smart-1c5824e3-d547-4445-ab19-4c178483c824 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61791020 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.xbar_stress_all.61791020 |
| Directory | /workspace/11.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/11.xbar_stress_all_with_rand_reset.2852303156 |
| Short name | T1719 |
| Test name | |
| Test status | |
| Simulation time | 4495298773 ps |
| CPU time | 286.21 seconds |
| Started | Jun 23 07:23:33 PM PDT 24 |
| Finished | Jun 23 07:28:20 PM PDT 24 |
| Peak memory | 577348 kb |
| Host | smart-ab10d75e-056e-4f6e-b8c3-0ad9982c4013 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2852303156 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.xbar_stress_all _with_rand_reset.2852303156 |
| Directory | /workspace/11.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/11.xbar_unmapped_addr.2140283337 |
| Short name | T1983 |
| Test name | |
| Test status | |
| Simulation time | 95358166 ps |
| CPU time | 15.98 seconds |
| Started | Jun 23 07:23:33 PM PDT 24 |
| Finished | Jun 23 07:23:49 PM PDT 24 |
| Peak memory | 573412 kb |
| Host | smart-fbceba4f-f1de-4a26-98e9-038245e91a9e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2140283337 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.xbar_unmapped_addr.2140283337 |
| Directory | /workspace/11.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/12.chip_csr_rw.4165729074 |
| Short name | T2739 |
| Test name | |
| Test status | |
| Simulation time | 4044462536 ps |
| CPU time | 346.07 seconds |
| Started | Jun 23 07:23:54 PM PDT 24 |
| Finished | Jun 23 07:29:40 PM PDT 24 |
| Peak memory | 596824 kb |
| Host | smart-4c25a790-180d-490c-a05e-910140e33d1f |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4165729074 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.chip_csr_rw.4165729074 |
| Directory | /workspace/12.chip_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/12.chip_same_csr_outstanding.2208918613 |
| Short name | T1955 |
| Test name | |
| Test status | |
| Simulation time | 29547325818 ps |
| CPU time | 3476.72 seconds |
| Started | Jun 23 07:23:40 PM PDT 24 |
| Finished | Jun 23 08:21:38 PM PDT 24 |
| Peak memory | 591160 kb |
| Host | smart-0ad89428-6af9-4ca2-b0f4-42676e478f31 |
| User | root |
| Command | /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +run_same_csr_outstanding +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2208918613 -assert nopostproc +UVM_TE STNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb - cm_log /dev/null -cm_name 12.chip_same_csr_outstanding.2208918613 |
| Directory | /workspace/12.chip_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/12.chip_tl_errors.2110368687 |
| Short name | T675 |
| Test name | |
| Test status | |
| Simulation time | 4260739187 ps |
| CPU time | 446.75 seconds |
| Started | Jun 23 07:23:40 PM PDT 24 |
| Finished | Jun 23 07:31:08 PM PDT 24 |
| Peak memory | 603472 kb |
| Host | smart-4357b9dd-650f-41aa-a411-01bd94c081e4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2110368687 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.chip_tl_errors.2110368687 |
| Directory | /workspace/12.chip_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/12.xbar_access_same_device.2261086318 |
| Short name | T1608 |
| Test name | |
| Test status | |
| Simulation time | 1872267078 ps |
| CPU time | 88.92 seconds |
| Started | Jun 23 07:23:43 PM PDT 24 |
| Finished | Jun 23 07:25:13 PM PDT 24 |
| Peak memory | 574116 kb |
| Host | smart-e47da9fc-cf0c-429c-b711-05ffb5c03a6a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2261086318 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.xbar_access_same_device .2261086318 |
| Directory | /workspace/12.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/12.xbar_access_same_device_slow_rsp.618388594 |
| Short name | T2763 |
| Test name | |
| Test status | |
| Simulation time | 44610297316 ps |
| CPU time | 809.6 seconds |
| Started | Jun 23 07:23:43 PM PDT 24 |
| Finished | Jun 23 07:37:13 PM PDT 24 |
| Peak memory | 574224 kb |
| Host | smart-e528366d-a3f7-4cbc-a19e-ea2149e94ff4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=618388594 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.xbar_access_same_d evice_slow_rsp.618388594 |
| Directory | /workspace/12.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/12.xbar_error_and_unmapped_addr.1216235770 |
| Short name | T2501 |
| Test name | |
| Test status | |
| Simulation time | 305035504 ps |
| CPU time | 30.32 seconds |
| Started | Jun 23 07:23:55 PM PDT 24 |
| Finished | Jun 23 07:24:26 PM PDT 24 |
| Peak memory | 573264 kb |
| Host | smart-cff791a6-deb3-4e61-becf-2d887751c282 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1216235770 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.xbar_error_and_unmapped_add r.1216235770 |
| Directory | /workspace/12.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/12.xbar_error_random.650020722 |
| Short name | T1536 |
| Test name | |
| Test status | |
| Simulation time | 591254001 ps |
| CPU time | 47.4 seconds |
| Started | Jun 23 07:23:50 PM PDT 24 |
| Finished | Jun 23 07:24:38 PM PDT 24 |
| Peak memory | 573708 kb |
| Host | smart-42bdba58-c1e5-4983-acd6-228c66b0dfdf |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=650020722 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.xbar_error_random.650020722 |
| Directory | /workspace/12.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/12.xbar_random.3552318341 |
| Short name | T2460 |
| Test name | |
| Test status | |
| Simulation time | 207359802 ps |
| CPU time | 11.06 seconds |
| Started | Jun 23 07:23:47 PM PDT 24 |
| Finished | Jun 23 07:23:58 PM PDT 24 |
| Peak memory | 565192 kb |
| Host | smart-6c41709e-68ab-4b48-af76-c883a66c8b3a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3552318341 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.xbar_random.3552318341 |
| Directory | /workspace/12.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/12.xbar_random_large_delays.4156919773 |
| Short name | T2365 |
| Test name | |
| Test status | |
| Simulation time | 83911990076 ps |
| CPU time | 859.07 seconds |
| Started | Jun 23 07:23:44 PM PDT 24 |
| Finished | Jun 23 07:38:03 PM PDT 24 |
| Peak memory | 574204 kb |
| Host | smart-8acc5538-732d-4732-acd3-38cf8fcabdd8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4156919773 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.xbar_random_large_delays.4156919773 |
| Directory | /workspace/12.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/12.xbar_random_slow_rsp.3030944352 |
| Short name | T2547 |
| Test name | |
| Test status | |
| Simulation time | 30710643327 ps |
| CPU time | 528.98 seconds |
| Started | Jun 23 07:23:45 PM PDT 24 |
| Finished | Jun 23 07:32:34 PM PDT 24 |
| Peak memory | 574192 kb |
| Host | smart-58d85210-042d-4e8c-9510-eaef97c5f2d3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3030944352 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.xbar_random_slow_rsp.3030944352 |
| Directory | /workspace/12.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/12.xbar_random_zero_delays.2892000463 |
| Short name | T2590 |
| Test name | |
| Test status | |
| Simulation time | 616192557 ps |
| CPU time | 46.41 seconds |
| Started | Jun 23 07:23:45 PM PDT 24 |
| Finished | Jun 23 07:24:32 PM PDT 24 |
| Peak memory | 573696 kb |
| Host | smart-5cd9c062-7142-40fa-9965-35413053da5a |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2892000463 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.xbar_random_zero_del ays.2892000463 |
| Directory | /workspace/12.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/12.xbar_same_source.516183039 |
| Short name | T665 |
| Test name | |
| Test status | |
| Simulation time | 1245250145 ps |
| CPU time | 39.33 seconds |
| Started | Jun 23 07:23:47 PM PDT 24 |
| Finished | Jun 23 07:24:26 PM PDT 24 |
| Peak memory | 573352 kb |
| Host | smart-fe0cf909-d6c3-4374-8d3d-b0158c7f4c12 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=516183039 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.xbar_same_source.516183039 |
| Directory | /workspace/12.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/12.xbar_smoke.3600875230 |
| Short name | T1492 |
| Test name | |
| Test status | |
| Simulation time | 58690291 ps |
| CPU time | 6.91 seconds |
| Started | Jun 23 07:23:41 PM PDT 24 |
| Finished | Jun 23 07:23:48 PM PDT 24 |
| Peak memory | 574000 kb |
| Host | smart-637de824-0f94-4853-8d64-d4ca310c72bf |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3600875230 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.xbar_smoke.3600875230 |
| Directory | /workspace/12.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/12.xbar_smoke_large_delays.1182158350 |
| Short name | T1478 |
| Test name | |
| Test status | |
| Simulation time | 9456447112 ps |
| CPU time | 96.19 seconds |
| Started | Jun 23 07:23:42 PM PDT 24 |
| Finished | Jun 23 07:25:19 PM PDT 24 |
| Peak memory | 565920 kb |
| Host | smart-d273a591-834e-41c8-ba21-16cc8d860453 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1182158350 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.xbar_smoke_large_delays.1182158350 |
| Directory | /workspace/12.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/12.xbar_smoke_slow_rsp.4229595156 |
| Short name | T1405 |
| Test name | |
| Test status | |
| Simulation time | 5584690640 ps |
| CPU time | 92.05 seconds |
| Started | Jun 23 07:23:43 PM PDT 24 |
| Finished | Jun 23 07:25:15 PM PDT 24 |
| Peak memory | 565208 kb |
| Host | smart-776451ae-5096-4aed-8a50-e20cd66fee59 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4229595156 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.xbar_smoke_slow_rsp.4229595156 |
| Directory | /workspace/12.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/12.xbar_smoke_zero_delays.298401980 |
| Short name | T2038 |
| Test name | |
| Test status | |
| Simulation time | 46713948 ps |
| CPU time | 6.62 seconds |
| Started | Jun 23 07:23:46 PM PDT 24 |
| Finished | Jun 23 07:23:53 PM PDT 24 |
| Peak memory | 565156 kb |
| Host | smart-1959b069-3465-42a4-8f94-46b02a25e761 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=298401980 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.xbar_smoke_zero_delays .298401980 |
| Directory | /workspace/12.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/12.xbar_stress_all.2629461172 |
| Short name | T2055 |
| Test name | |
| Test status | |
| Simulation time | 13928621446 ps |
| CPU time | 586.68 seconds |
| Started | Jun 23 07:23:57 PM PDT 24 |
| Finished | Jun 23 07:33:44 PM PDT 24 |
| Peak memory | 574308 kb |
| Host | smart-1b9d6d94-4418-488e-a719-352b93028c3d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2629461172 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.xbar_stress_all.2629461172 |
| Directory | /workspace/12.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/12.xbar_stress_all_with_error.691631495 |
| Short name | T2126 |
| Test name | |
| Test status | |
| Simulation time | 941838542 ps |
| CPU time | 73.23 seconds |
| Started | Jun 23 07:23:57 PM PDT 24 |
| Finished | Jun 23 07:25:10 PM PDT 24 |
| Peak memory | 574124 kb |
| Host | smart-9f53d646-17af-4088-8c94-db88185ebdd1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=691631495 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.xbar_stress_all_with_error.691631495 |
| Directory | /workspace/12.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/12.xbar_stress_all_with_rand_reset.83685738 |
| Short name | T2632 |
| Test name | |
| Test status | |
| Simulation time | 79550620 ps |
| CPU time | 31.3 seconds |
| Started | Jun 23 07:23:54 PM PDT 24 |
| Finished | Jun 23 07:24:26 PM PDT 24 |
| Peak memory | 576276 kb |
| Host | smart-5e92214d-ae19-4725-a85a-d4536f70be40 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83685738 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_rese t_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.xbar_stress_all_w ith_rand_reset.83685738 |
| Directory | /workspace/12.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/12.xbar_stress_all_with_reset_error.1418477114 |
| Short name | T2526 |
| Test name | |
| Test status | |
| Simulation time | 1127098907 ps |
| CPU time | 112.82 seconds |
| Started | Jun 23 07:23:55 PM PDT 24 |
| Finished | Jun 23 07:25:48 PM PDT 24 |
| Peak memory | 574296 kb |
| Host | smart-ea7842ba-d0a7-4c01-93e2-0c1a65d41143 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1418477114 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.xbar_stress_al l_with_reset_error.1418477114 |
| Directory | /workspace/12.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/12.xbar_unmapped_addr.2696989891 |
| Short name | T1898 |
| Test name | |
| Test status | |
| Simulation time | 270589727 ps |
| CPU time | 35.49 seconds |
| Started | Jun 23 07:23:50 PM PDT 24 |
| Finished | Jun 23 07:24:26 PM PDT 24 |
| Peak memory | 574132 kb |
| Host | smart-9b668c98-3b37-45e8-bcc2-1b33df056a75 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2696989891 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.xbar_unmapped_addr.2696989891 |
| Directory | /workspace/12.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/13.chip_csr_rw.2909838985 |
| Short name | T1937 |
| Test name | |
| Test status | |
| Simulation time | 4566444473 ps |
| CPU time | 290.21 seconds |
| Started | Jun 23 07:24:33 PM PDT 24 |
| Finished | Jun 23 07:29:24 PM PDT 24 |
| Peak memory | 596444 kb |
| Host | smart-d9aa7394-2666-4601-897a-4c74b97237bb |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2909838985 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.chip_csr_rw.2909838985 |
| Directory | /workspace/13.chip_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/13.chip_same_csr_outstanding.3196499633 |
| Short name | T378 |
| Test name | |
| Test status | |
| Simulation time | 27811120296 ps |
| CPU time | 4182.44 seconds |
| Started | Jun 23 07:23:59 PM PDT 24 |
| Finished | Jun 23 08:33:42 PM PDT 24 |
| Peak memory | 590820 kb |
| Host | smart-f2391dd9-10b6-4ebf-8f81-a74ac0709a56 |
| User | root |
| Command | /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +run_same_csr_outstanding +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3196499633 -assert nopostproc +UVM_TE STNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb - cm_log /dev/null -cm_name 13.chip_same_csr_outstanding.3196499633 |
| Directory | /workspace/13.chip_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/13.xbar_access_same_device.1728347391 |
| Short name | T1869 |
| Test name | |
| Test status | |
| Simulation time | 2786946771 ps |
| CPU time | 110.84 seconds |
| Started | Jun 23 07:24:12 PM PDT 24 |
| Finished | Jun 23 07:26:03 PM PDT 24 |
| Peak memory | 574132 kb |
| Host | smart-0aaa0955-c3f1-43bd-a5d0-f37713fa7322 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1728347391 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.xbar_access_same_device .1728347391 |
| Directory | /workspace/13.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/13.xbar_access_same_device_slow_rsp.2337151510 |
| Short name | T1614 |
| Test name | |
| Test status | |
| Simulation time | 139997921577 ps |
| CPU time | 2546.31 seconds |
| Started | Jun 23 07:24:09 PM PDT 24 |
| Finished | Jun 23 08:06:36 PM PDT 24 |
| Peak memory | 574272 kb |
| Host | smart-048c3956-9e64-476f-b716-b920e4dc3270 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2337151510 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.xbar_access_same_ device_slow_rsp.2337151510 |
| Directory | /workspace/13.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/13.xbar_error_and_unmapped_addr.482083633 |
| Short name | T1775 |
| Test name | |
| Test status | |
| Simulation time | 38395788 ps |
| CPU time | 6.71 seconds |
| Started | Jun 23 07:24:17 PM PDT 24 |
| Finished | Jun 23 07:24:24 PM PDT 24 |
| Peak memory | 565536 kb |
| Host | smart-4d05b0fe-a61c-4a49-b194-509dbfe3f0f7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=482083633 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.xbar_error_and_unmapped_addr .482083633 |
| Directory | /workspace/13.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/13.xbar_error_random.234658892 |
| Short name | T1655 |
| Test name | |
| Test status | |
| Simulation time | 1901349694 ps |
| CPU time | 71.03 seconds |
| Started | Jun 23 07:24:10 PM PDT 24 |
| Finished | Jun 23 07:25:22 PM PDT 24 |
| Peak memory | 573344 kb |
| Host | smart-8a5753b5-454d-49e1-a164-97de3748dac7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=234658892 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.xbar_error_random.234658892 |
| Directory | /workspace/13.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/13.xbar_random.2246041492 |
| Short name | T1649 |
| Test name | |
| Test status | |
| Simulation time | 494356303 ps |
| CPU time | 41.61 seconds |
| Started | Jun 23 07:24:05 PM PDT 24 |
| Finished | Jun 23 07:24:47 PM PDT 24 |
| Peak memory | 574112 kb |
| Host | smart-f57e20e1-4b23-42b7-bda2-652e6ac84857 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2246041492 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.xbar_random.2246041492 |
| Directory | /workspace/13.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/13.xbar_random_large_delays.3826178197 |
| Short name | T1834 |
| Test name | |
| Test status | |
| Simulation time | 117152251061 ps |
| CPU time | 1271.23 seconds |
| Started | Jun 23 07:24:05 PM PDT 24 |
| Finished | Jun 23 07:45:17 PM PDT 24 |
| Peak memory | 574200 kb |
| Host | smart-44e3cc02-1917-402b-a482-229a6d4cbc8a |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3826178197 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.xbar_random_large_delays.3826178197 |
| Directory | /workspace/13.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/13.xbar_random_slow_rsp.113781943 |
| Short name | T2290 |
| Test name | |
| Test status | |
| Simulation time | 41058958913 ps |
| CPU time | 671.83 seconds |
| Started | Jun 23 07:24:09 PM PDT 24 |
| Finished | Jun 23 07:35:22 PM PDT 24 |
| Peak memory | 573528 kb |
| Host | smart-86a70624-cd63-4430-bf12-8eb9bdcbb82f |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=113781943 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.xbar_random_slow_rsp.113781943 |
| Directory | /workspace/13.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/13.xbar_random_zero_delays.2468659864 |
| Short name | T641 |
| Test name | |
| Test status | |
| Simulation time | 301609377 ps |
| CPU time | 26.71 seconds |
| Started | Jun 23 07:24:05 PM PDT 24 |
| Finished | Jun 23 07:24:32 PM PDT 24 |
| Peak memory | 573976 kb |
| Host | smart-9efc6bab-fa0e-485c-be53-ee1190be5824 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2468659864 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.xbar_random_zero_del ays.2468659864 |
| Directory | /workspace/13.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/13.xbar_same_source.1508414021 |
| Short name | T1820 |
| Test name | |
| Test status | |
| Simulation time | 2089032123 ps |
| CPU time | 60.62 seconds |
| Started | Jun 23 07:24:11 PM PDT 24 |
| Finished | Jun 23 07:25:11 PM PDT 24 |
| Peak memory | 573376 kb |
| Host | smart-1132ae86-6372-4ea1-9e07-a4e864e6fb2d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1508414021 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.xbar_same_source.1508414021 |
| Directory | /workspace/13.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/13.xbar_smoke.637332741 |
| Short name | T2447 |
| Test name | |
| Test status | |
| Simulation time | 45796135 ps |
| CPU time | 6.64 seconds |
| Started | Jun 23 07:24:04 PM PDT 24 |
| Finished | Jun 23 07:24:11 PM PDT 24 |
| Peak memory | 565152 kb |
| Host | smart-063c086f-4656-4440-b58c-eeada6c4503d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=637332741 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.xbar_smoke.637332741 |
| Directory | /workspace/13.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/13.xbar_smoke_large_delays.157125291 |
| Short name | T1704 |
| Test name | |
| Test status | |
| Simulation time | 6919503161 ps |
| CPU time | 68.47 seconds |
| Started | Jun 23 07:24:04 PM PDT 24 |
| Finished | Jun 23 07:25:13 PM PDT 24 |
| Peak memory | 565220 kb |
| Host | smart-cbf5d921-a0d7-43a5-a37c-3fff9e37c050 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=157125291 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.xbar_smoke_large_delays.157125291 |
| Directory | /workspace/13.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/13.xbar_smoke_slow_rsp.4067307150 |
| Short name | T1745 |
| Test name | |
| Test status | |
| Simulation time | 4723584261 ps |
| CPU time | 77.67 seconds |
| Started | Jun 23 07:24:08 PM PDT 24 |
| Finished | Jun 23 07:25:26 PM PDT 24 |
| Peak memory | 565924 kb |
| Host | smart-627b1281-5f70-4b7f-baa9-5d56452f8bfd |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4067307150 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.xbar_smoke_slow_rsp.4067307150 |
| Directory | /workspace/13.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/13.xbar_smoke_zero_delays.1520946410 |
| Short name | T2831 |
| Test name | |
| Test status | |
| Simulation time | 52068430 ps |
| CPU time | 6.46 seconds |
| Started | Jun 23 07:24:08 PM PDT 24 |
| Finished | Jun 23 07:24:15 PM PDT 24 |
| Peak memory | 565480 kb |
| Host | smart-19303a95-d191-4c37-9e63-43564b30a2fb |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1520946410 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.xbar_smoke_zero_delay s.1520946410 |
| Directory | /workspace/13.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/13.xbar_stress_all.3418023331 |
| Short name | T500 |
| Test name | |
| Test status | |
| Simulation time | 4429636543 ps |
| CPU time | 167.62 seconds |
| Started | Jun 23 07:24:17 PM PDT 24 |
| Finished | Jun 23 07:27:05 PM PDT 24 |
| Peak memory | 574092 kb |
| Host | smart-e4f9b9be-2e74-4cf2-afe4-caf3b223405e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3418023331 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.xbar_stress_all.3418023331 |
| Directory | /workspace/13.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/13.xbar_stress_all_with_error.4247221459 |
| Short name | T2548 |
| Test name | |
| Test status | |
| Simulation time | 11232139933 ps |
| CPU time | 354.25 seconds |
| Started | Jun 23 07:24:21 PM PDT 24 |
| Finished | Jun 23 07:30:16 PM PDT 24 |
| Peak memory | 574336 kb |
| Host | smart-2c4c18e4-90ae-49c1-ad96-f76967d526a2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4247221459 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.xbar_stress_all_with_error.4247221459 |
| Directory | /workspace/13.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/13.xbar_stress_all_with_rand_reset.1416734112 |
| Short name | T889 |
| Test name | |
| Test status | |
| Simulation time | 166383135 ps |
| CPU time | 139.38 seconds |
| Started | Jun 23 07:24:19 PM PDT 24 |
| Finished | Jun 23 07:26:38 PM PDT 24 |
| Peak memory | 576224 kb |
| Host | smart-8eb01cb0-8c5a-4c73-ac46-b18a4c313919 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1416734112 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.xbar_stress_all _with_rand_reset.1416734112 |
| Directory | /workspace/13.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/13.xbar_stress_all_with_reset_error.1192748041 |
| Short name | T2655 |
| Test name | |
| Test status | |
| Simulation time | 1798790741 ps |
| CPU time | 113.5 seconds |
| Started | Jun 23 07:24:22 PM PDT 24 |
| Finished | Jun 23 07:26:15 PM PDT 24 |
| Peak memory | 574208 kb |
| Host | smart-628a78d6-f773-4177-af61-43dff89e306e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1192748041 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.xbar_stress_al l_with_reset_error.1192748041 |
| Directory | /workspace/13.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/13.xbar_unmapped_addr.1275644410 |
| Short name | T1769 |
| Test name | |
| Test status | |
| Simulation time | 225989016 ps |
| CPU time | 28.18 seconds |
| Started | Jun 23 07:24:14 PM PDT 24 |
| Finished | Jun 23 07:24:43 PM PDT 24 |
| Peak memory | 574096 kb |
| Host | smart-dd2284b4-3ade-43bd-8b08-816aef7beaf0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1275644410 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.xbar_unmapped_addr.1275644410 |
| Directory | /workspace/13.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/14.chip_csr_rw.2120642140 |
| Short name | T2796 |
| Test name | |
| Test status | |
| Simulation time | 4918954617 ps |
| CPU time | 549.26 seconds |
| Started | Jun 23 07:24:39 PM PDT 24 |
| Finished | Jun 23 07:33:49 PM PDT 24 |
| Peak memory | 595768 kb |
| Host | smart-d11d5581-14a2-45ed-8808-e3777341b0c8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2120642140 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.chip_csr_rw.2120642140 |
| Directory | /workspace/14.chip_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/14.chip_same_csr_outstanding.3471392091 |
| Short name | T392 |
| Test name | |
| Test status | |
| Simulation time | 31741572682 ps |
| CPU time | 4077.82 seconds |
| Started | Jun 23 07:24:32 PM PDT 24 |
| Finished | Jun 23 08:32:32 PM PDT 24 |
| Peak memory | 591096 kb |
| Host | smart-b38575d2-267e-4b06-98c2-0e2796eef267 |
| User | root |
| Command | /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +run_same_csr_outstanding +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3471392091 -assert nopostproc +UVM_TE STNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb - cm_log /dev/null -cm_name 14.chip_same_csr_outstanding.3471392091 |
| Directory | /workspace/14.chip_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/14.chip_tl_errors.2276010115 |
| Short name | T723 |
| Test name | |
| Test status | |
| Simulation time | 3840136769 ps |
| CPU time | 285.42 seconds |
| Started | Jun 23 07:24:34 PM PDT 24 |
| Finished | Jun 23 07:29:20 PM PDT 24 |
| Peak memory | 598684 kb |
| Host | smart-741d86e2-d37f-4c1d-8cb7-824b5fb82373 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2276010115 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.chip_tl_errors.2276010115 |
| Directory | /workspace/14.chip_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/14.xbar_access_same_device.2154892383 |
| Short name | T2803 |
| Test name | |
| Test status | |
| Simulation time | 937513626 ps |
| CPU time | 75.61 seconds |
| Started | Jun 23 07:24:41 PM PDT 24 |
| Finished | Jun 23 07:25:57 PM PDT 24 |
| Peak memory | 574100 kb |
| Host | smart-0d39bdd8-c13c-4f36-b411-1ce770946b85 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2154892383 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.xbar_access_same_device .2154892383 |
| Directory | /workspace/14.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/14.xbar_access_same_device_slow_rsp.3700363009 |
| Short name | T2787 |
| Test name | |
| Test status | |
| Simulation time | 45305867253 ps |
| CPU time | 744.59 seconds |
| Started | Jun 23 07:24:39 PM PDT 24 |
| Finished | Jun 23 07:37:04 PM PDT 24 |
| Peak memory | 574216 kb |
| Host | smart-c51b0c0d-7e01-4501-a9b4-5288a932293d |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3700363009 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.xbar_access_same_ device_slow_rsp.3700363009 |
| Directory | /workspace/14.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/14.xbar_error_and_unmapped_addr.2796089383 |
| Short name | T2486 |
| Test name | |
| Test status | |
| Simulation time | 835313678 ps |
| CPU time | 28.62 seconds |
| Started | Jun 23 07:24:44 PM PDT 24 |
| Finished | Jun 23 07:25:13 PM PDT 24 |
| Peak memory | 573676 kb |
| Host | smart-d952f6ff-2598-4039-9a9e-a4662a7260b2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2796089383 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.xbar_error_and_unmapped_add r.2796089383 |
| Directory | /workspace/14.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/14.xbar_error_random.2493500679 |
| Short name | T1482 |
| Test name | |
| Test status | |
| Simulation time | 696175194 ps |
| CPU time | 26.45 seconds |
| Started | Jun 23 07:24:39 PM PDT 24 |
| Finished | Jun 23 07:25:06 PM PDT 24 |
| Peak memory | 573296 kb |
| Host | smart-ce9e3dfc-4106-481f-9ca7-bb76917d9083 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2493500679 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.xbar_error_random.2493500679 |
| Directory | /workspace/14.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/14.xbar_random.526048031 |
| Short name | T1393 |
| Test name | |
| Test status | |
| Simulation time | 519424601 ps |
| CPU time | 19.49 seconds |
| Started | Jun 23 07:24:40 PM PDT 24 |
| Finished | Jun 23 07:25:00 PM PDT 24 |
| Peak memory | 573416 kb |
| Host | smart-54b1841d-8d47-484c-8b66-89143cf33578 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=526048031 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.xbar_random.526048031 |
| Directory | /workspace/14.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/14.xbar_random_large_delays.79760193 |
| Short name | T1953 |
| Test name | |
| Test status | |
| Simulation time | 58587988900 ps |
| CPU time | 635.46 seconds |
| Started | Jun 23 07:24:38 PM PDT 24 |
| Finished | Jun 23 07:35:15 PM PDT 24 |
| Peak memory | 574212 kb |
| Host | smart-455bc7fa-e72f-4744-8c33-bb2907dd1197 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79760193 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.xbar_random_large_delays.79760193 |
| Directory | /workspace/14.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/14.xbar_random_slow_rsp.1411517027 |
| Short name | T491 |
| Test name | |
| Test status | |
| Simulation time | 33226869682 ps |
| CPU time | 596.1 seconds |
| Started | Jun 23 07:24:41 PM PDT 24 |
| Finished | Jun 23 07:34:38 PM PDT 24 |
| Peak memory | 574184 kb |
| Host | smart-0fe9feb4-540a-4760-9b6b-6b52f2d03e91 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1411517027 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.xbar_random_slow_rsp.1411517027 |
| Directory | /workspace/14.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/14.xbar_random_zero_delays.1468221926 |
| Short name | T1842 |
| Test name | |
| Test status | |
| Simulation time | 433008937 ps |
| CPU time | 43.45 seconds |
| Started | Jun 23 07:24:54 PM PDT 24 |
| Finished | Jun 23 07:25:38 PM PDT 24 |
| Peak memory | 574124 kb |
| Host | smart-233bc5c2-1bd1-430d-9a17-afbd9abcb746 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1468221926 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.xbar_random_zero_del ays.1468221926 |
| Directory | /workspace/14.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/14.xbar_same_source.817669265 |
| Short name | T2641 |
| Test name | |
| Test status | |
| Simulation time | 192368571 ps |
| CPU time | 8.46 seconds |
| Started | Jun 23 07:24:38 PM PDT 24 |
| Finished | Jun 23 07:24:47 PM PDT 24 |
| Peak memory | 565776 kb |
| Host | smart-ad50f936-7d17-4932-bd75-423bc2935f47 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=817669265 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.xbar_same_source.817669265 |
| Directory | /workspace/14.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/14.xbar_smoke.15075279 |
| Short name | T2454 |
| Test name | |
| Test status | |
| Simulation time | 53042252 ps |
| CPU time | 6.37 seconds |
| Started | Jun 23 07:24:34 PM PDT 24 |
| Finished | Jun 23 07:24:41 PM PDT 24 |
| Peak memory | 565468 kb |
| Host | smart-2842fcf3-be30-48dc-bf1c-759a86b9c49a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15075279 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.xbar_smoke.15075279 |
| Directory | /workspace/14.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/14.xbar_smoke_large_delays.115540962 |
| Short name | T1420 |
| Test name | |
| Test status | |
| Simulation time | 10884903501 ps |
| CPU time | 115.71 seconds |
| Started | Jun 23 07:24:39 PM PDT 24 |
| Finished | Jun 23 07:26:35 PM PDT 24 |
| Peak memory | 565184 kb |
| Host | smart-4b4f2ac9-a642-40aa-9359-e686d038e8bd |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=115540962 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.xbar_smoke_large_delays.115540962 |
| Directory | /workspace/14.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/14.xbar_smoke_slow_rsp.1096947090 |
| Short name | T2684 |
| Test name | |
| Test status | |
| Simulation time | 5604634198 ps |
| CPU time | 99.73 seconds |
| Started | Jun 23 07:24:39 PM PDT 24 |
| Finished | Jun 23 07:26:20 PM PDT 24 |
| Peak memory | 565552 kb |
| Host | smart-3e784cba-a2cd-4b7d-b116-5b2d75466188 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1096947090 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.xbar_smoke_slow_rsp.1096947090 |
| Directory | /workspace/14.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/14.xbar_smoke_zero_delays.3295915075 |
| Short name | T2194 |
| Test name | |
| Test status | |
| Simulation time | 37563712 ps |
| CPU time | 5.83 seconds |
| Started | Jun 23 07:24:41 PM PDT 24 |
| Finished | Jun 23 07:24:47 PM PDT 24 |
| Peak memory | 565116 kb |
| Host | smart-a67d84ed-a7b2-46bc-a0f3-8ea01b7197ea |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3295915075 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.xbar_smoke_zero_delay s.3295915075 |
| Directory | /workspace/14.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/14.xbar_stress_all.1733263481 |
| Short name | T493 |
| Test name | |
| Test status | |
| Simulation time | 15487502700 ps |
| CPU time | 522.63 seconds |
| Started | Jun 23 07:24:38 PM PDT 24 |
| Finished | Jun 23 07:33:21 PM PDT 24 |
| Peak memory | 574320 kb |
| Host | smart-f5ab3932-43cd-48b3-a716-3c1a144600cc |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1733263481 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.xbar_stress_all.1733263481 |
| Directory | /workspace/14.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/14.xbar_stress_all_with_error.1280177469 |
| Short name | T1796 |
| Test name | |
| Test status | |
| Simulation time | 8624212105 ps |
| CPU time | 353.88 seconds |
| Started | Jun 23 07:24:41 PM PDT 24 |
| Finished | Jun 23 07:30:35 PM PDT 24 |
| Peak memory | 573548 kb |
| Host | smart-4b5a72af-6353-4f90-8470-6da320f68301 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1280177469 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.xbar_stress_all_with_error.1280177469 |
| Directory | /workspace/14.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/14.xbar_stress_all_with_rand_reset.1225471858 |
| Short name | T2176 |
| Test name | |
| Test status | |
| Simulation time | 341399766 ps |
| CPU time | 169.98 seconds |
| Started | Jun 23 07:24:42 PM PDT 24 |
| Finished | Jun 23 07:27:32 PM PDT 24 |
| Peak memory | 575232 kb |
| Host | smart-bbd88b05-067b-4898-8892-d794ec6524e0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1225471858 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.xbar_stress_all _with_rand_reset.1225471858 |
| Directory | /workspace/14.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/14.xbar_stress_all_with_reset_error.3266450943 |
| Short name | T2721 |
| Test name | |
| Test status | |
| Simulation time | 183296588 ps |
| CPU time | 30.83 seconds |
| Started | Jun 23 07:24:39 PM PDT 24 |
| Finished | Jun 23 07:25:10 PM PDT 24 |
| Peak memory | 575788 kb |
| Host | smart-82459621-a295-40a2-a7ac-b80c5b714e9c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3266450943 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.xbar_stress_al l_with_reset_error.3266450943 |
| Directory | /workspace/14.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/14.xbar_unmapped_addr.3521439308 |
| Short name | T1641 |
| Test name | |
| Test status | |
| Simulation time | 1476463680 ps |
| CPU time | 60.2 seconds |
| Started | Jun 23 07:24:38 PM PDT 24 |
| Finished | Jun 23 07:25:39 PM PDT 24 |
| Peak memory | 574112 kb |
| Host | smart-62946827-6d07-4179-91b8-59c4313db2ed |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3521439308 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.xbar_unmapped_addr.3521439308 |
| Directory | /workspace/14.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/15.chip_csr_rw.2275217757 |
| Short name | T393 |
| Test name | |
| Test status | |
| Simulation time | 4975538920 ps |
| CPU time | 429.11 seconds |
| Started | Jun 23 07:25:08 PM PDT 24 |
| Finished | Jun 23 07:32:18 PM PDT 24 |
| Peak memory | 595292 kb |
| Host | smart-dd93149c-3e85-4fda-8148-5cddd115edd8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2275217757 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.chip_csr_rw.2275217757 |
| Directory | /workspace/15.chip_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/15.chip_same_csr_outstanding.4046022885 |
| Short name | T143 |
| Test name | |
| Test status | |
| Simulation time | 29015381538 ps |
| CPU time | 3134.57 seconds |
| Started | Jun 23 07:24:49 PM PDT 24 |
| Finished | Jun 23 08:17:04 PM PDT 24 |
| Peak memory | 591012 kb |
| Host | smart-00f9bbb4-eda4-440e-9749-141de54fb803 |
| User | root |
| Command | /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +run_same_csr_outstanding +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4046022885 -assert nopostproc +UVM_TE STNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb - cm_log /dev/null -cm_name 15.chip_same_csr_outstanding.4046022885 |
| Directory | /workspace/15.chip_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/15.chip_tl_errors.1879828633 |
| Short name | T2688 |
| Test name | |
| Test status | |
| Simulation time | 2098909630 ps |
| CPU time | 77.91 seconds |
| Started | Jun 23 07:24:43 PM PDT 24 |
| Finished | Jun 23 07:26:01 PM PDT 24 |
| Peak memory | 603428 kb |
| Host | smart-406c0345-5fc4-4c53-9fcf-5a4eedfe52e9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1879828633 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.chip_tl_errors.1879828633 |
| Directory | /workspace/15.chip_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/15.xbar_access_same_device.2574101021 |
| Short name | T1976 |
| Test name | |
| Test status | |
| Simulation time | 3908520673 ps |
| CPU time | 159.5 seconds |
| Started | Jun 23 07:25:00 PM PDT 24 |
| Finished | Jun 23 07:27:40 PM PDT 24 |
| Peak memory | 573468 kb |
| Host | smart-d2a73ae7-2d8d-4ba1-b6d0-36eacb570589 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2574101021 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.xbar_access_same_device .2574101021 |
| Directory | /workspace/15.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/15.xbar_access_same_device_slow_rsp.2256672951 |
| Short name | T2649 |
| Test name | |
| Test status | |
| Simulation time | 29838196589 ps |
| CPU time | 550.95 seconds |
| Started | Jun 23 07:25:00 PM PDT 24 |
| Finished | Jun 23 07:34:11 PM PDT 24 |
| Peak memory | 574204 kb |
| Host | smart-c37c6061-27ec-4fb9-842f-0d0fb92c7d14 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2256672951 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.xbar_access_same_ device_slow_rsp.2256672951 |
| Directory | /workspace/15.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/15.xbar_error_and_unmapped_addr.3945930191 |
| Short name | T2137 |
| Test name | |
| Test status | |
| Simulation time | 543117648 ps |
| CPU time | 26.01 seconds |
| Started | Jun 23 07:25:06 PM PDT 24 |
| Finished | Jun 23 07:25:32 PM PDT 24 |
| Peak memory | 573736 kb |
| Host | smart-9f03c61e-13d2-4b99-848b-d0f704239e1d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3945930191 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.xbar_error_and_unmapped_add r.3945930191 |
| Directory | /workspace/15.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/15.xbar_error_random.2753951738 |
| Short name | T2171 |
| Test name | |
| Test status | |
| Simulation time | 551204449 ps |
| CPU time | 43.24 seconds |
| Started | Jun 23 07:25:09 PM PDT 24 |
| Finished | Jun 23 07:25:52 PM PDT 24 |
| Peak memory | 573736 kb |
| Host | smart-0d0976ff-b0d1-4769-9cbf-cd5736262758 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2753951738 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.xbar_error_random.2753951738 |
| Directory | /workspace/15.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/15.xbar_random.1905571679 |
| Short name | T2798 |
| Test name | |
| Test status | |
| Simulation time | 1152002005 ps |
| CPU time | 42.09 seconds |
| Started | Jun 23 07:25:03 PM PDT 24 |
| Finished | Jun 23 07:25:45 PM PDT 24 |
| Peak memory | 573448 kb |
| Host | smart-50d20e4f-0c0f-4b5f-9318-3ba5c3f598cf |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1905571679 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.xbar_random.1905571679 |
| Directory | /workspace/15.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/15.xbar_random_large_delays.3573365008 |
| Short name | T685 |
| Test name | |
| Test status | |
| Simulation time | 43641660987 ps |
| CPU time | 450.45 seconds |
| Started | Jun 23 07:25:00 PM PDT 24 |
| Finished | Jun 23 07:32:31 PM PDT 24 |
| Peak memory | 574176 kb |
| Host | smart-6c776a5c-b967-436d-b662-2cdc5887b18b |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3573365008 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.xbar_random_large_delays.3573365008 |
| Directory | /workspace/15.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/15.xbar_random_slow_rsp.4184432083 |
| Short name | T2232 |
| Test name | |
| Test status | |
| Simulation time | 65282238061 ps |
| CPU time | 1032.1 seconds |
| Started | Jun 23 07:25:01 PM PDT 24 |
| Finished | Jun 23 07:42:14 PM PDT 24 |
| Peak memory | 574220 kb |
| Host | smart-6937e36b-3cff-4a40-88ca-fec9f2cb927e |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4184432083 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.xbar_random_slow_rsp.4184432083 |
| Directory | /workspace/15.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/15.xbar_random_zero_delays.2305586816 |
| Short name | T2177 |
| Test name | |
| Test status | |
| Simulation time | 397948874 ps |
| CPU time | 33.03 seconds |
| Started | Jun 23 07:25:01 PM PDT 24 |
| Finished | Jun 23 07:25:35 PM PDT 24 |
| Peak memory | 573928 kb |
| Host | smart-ef45ca8c-6f3b-448d-95a8-fa861f363b9e |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2305586816 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.xbar_random_zero_del ays.2305586816 |
| Directory | /workspace/15.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/15.xbar_same_source.3506032619 |
| Short name | T2074 |
| Test name | |
| Test status | |
| Simulation time | 1879156069 ps |
| CPU time | 59.05 seconds |
| Started | Jun 23 07:24:59 PM PDT 24 |
| Finished | Jun 23 07:25:58 PM PDT 24 |
| Peak memory | 573392 kb |
| Host | smart-99a6ceb2-237c-443d-a0f3-48830aee81b8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3506032619 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.xbar_same_source.3506032619 |
| Directory | /workspace/15.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/15.xbar_smoke.4134291017 |
| Short name | T1969 |
| Test name | |
| Test status | |
| Simulation time | 182766033 ps |
| CPU time | 7.54 seconds |
| Started | Jun 23 07:24:48 PM PDT 24 |
| Finished | Jun 23 07:24:56 PM PDT 24 |
| Peak memory | 573812 kb |
| Host | smart-403b0063-fd94-4787-9f3c-5a30ed236536 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4134291017 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.xbar_smoke.4134291017 |
| Directory | /workspace/15.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/15.xbar_smoke_large_delays.911732966 |
| Short name | T1768 |
| Test name | |
| Test status | |
| Simulation time | 9155889392 ps |
| CPU time | 93.41 seconds |
| Started | Jun 23 07:24:43 PM PDT 24 |
| Finished | Jun 23 07:26:17 PM PDT 24 |
| Peak memory | 565940 kb |
| Host | smart-6aa4c3a9-d435-4a4e-83ea-cdfc7d4f765a |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=911732966 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.xbar_smoke_large_delays.911732966 |
| Directory | /workspace/15.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/15.xbar_smoke_slow_rsp.620377119 |
| Short name | T1601 |
| Test name | |
| Test status | |
| Simulation time | 6033355133 ps |
| CPU time | 109.21 seconds |
| Started | Jun 23 07:24:44 PM PDT 24 |
| Finished | Jun 23 07:26:33 PM PDT 24 |
| Peak memory | 565556 kb |
| Host | smart-136367f7-a5c3-47ad-8ee8-f1f80a36fb23 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=620377119 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.xbar_smoke_slow_rsp.620377119 |
| Directory | /workspace/15.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/15.xbar_smoke_zero_delays.2195279333 |
| Short name | T1624 |
| Test name | |
| Test status | |
| Simulation time | 52996275 ps |
| CPU time | 5.93 seconds |
| Started | Jun 23 07:24:48 PM PDT 24 |
| Finished | Jun 23 07:24:55 PM PDT 24 |
| Peak memory | 573164 kb |
| Host | smart-61ccfff0-24c4-4625-9466-f1b068083a37 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2195279333 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.xbar_smoke_zero_delay s.2195279333 |
| Directory | /workspace/15.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/15.xbar_stress_all.3567478912 |
| Short name | T2385 |
| Test name | |
| Test status | |
| Simulation time | 4040628317 ps |
| CPU time | 347.09 seconds |
| Started | Jun 23 07:25:09 PM PDT 24 |
| Finished | Jun 23 07:30:57 PM PDT 24 |
| Peak memory | 574312 kb |
| Host | smart-b2955997-888a-4a50-9a4f-19eaa44c0d65 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3567478912 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.xbar_stress_all.3567478912 |
| Directory | /workspace/15.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/15.xbar_stress_all_with_error.261728270 |
| Short name | T2090 |
| Test name | |
| Test status | |
| Simulation time | 1664895103 ps |
| CPU time | 140.55 seconds |
| Started | Jun 23 07:25:08 PM PDT 24 |
| Finished | Jun 23 07:27:29 PM PDT 24 |
| Peak memory | 574300 kb |
| Host | smart-e33ea1aa-9c0e-4de8-960c-a2a8a894f9cb |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=261728270 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.xbar_stress_all_with_error.261728270 |
| Directory | /workspace/15.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/15.xbar_stress_all_with_rand_reset.288833327 |
| Short name | T2741 |
| Test name | |
| Test status | |
| Simulation time | 131663345 ps |
| CPU time | 46.3 seconds |
| Started | Jun 23 07:25:09 PM PDT 24 |
| Finished | Jun 23 07:25:55 PM PDT 24 |
| Peak memory | 576296 kb |
| Host | smart-b90d7691-f04f-4052-892a-f94456d42f6e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=288833327 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_res et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.xbar_stress_all_ with_rand_reset.288833327 |
| Directory | /workspace/15.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/15.xbar_stress_all_with_reset_error.3540024256 |
| Short name | T2255 |
| Test name | |
| Test status | |
| Simulation time | 8142692015 ps |
| CPU time | 419.42 seconds |
| Started | Jun 23 07:25:09 PM PDT 24 |
| Finished | Jun 23 07:32:09 PM PDT 24 |
| Peak memory | 574384 kb |
| Host | smart-744ef9c8-0b0e-4610-afea-8c00753cf0a7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3540024256 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.xbar_stress_al l_with_reset_error.3540024256 |
| Directory | /workspace/15.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/15.xbar_unmapped_addr.1265839100 |
| Short name | T2011 |
| Test name | |
| Test status | |
| Simulation time | 1193882534 ps |
| CPU time | 49.71 seconds |
| Started | Jun 23 07:25:10 PM PDT 24 |
| Finished | Jun 23 07:26:00 PM PDT 24 |
| Peak memory | 574168 kb |
| Host | smart-e53612f3-d200-47e1-8ed9-4f3fc1312f1a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1265839100 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.xbar_unmapped_addr.1265839100 |
| Directory | /workspace/15.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/16.chip_csr_rw.806169612 |
| Short name | T1977 |
| Test name | |
| Test status | |
| Simulation time | 3750045790 ps |
| CPU time | 322.14 seconds |
| Started | Jun 23 07:25:19 PM PDT 24 |
| Finished | Jun 23 07:30:42 PM PDT 24 |
| Peak memory | 595228 kb |
| Host | smart-9bb551af-5ce7-487f-b765-a01551350434 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=806169612 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.chip_csr_rw.806169612 |
| Directory | /workspace/16.chip_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/16.chip_same_csr_outstanding.733405330 |
| Short name | T418 |
| Test name | |
| Test status | |
| Simulation time | 15187211226 ps |
| CPU time | 2503.48 seconds |
| Started | Jun 23 07:25:07 PM PDT 24 |
| Finished | Jun 23 08:06:51 PM PDT 24 |
| Peak memory | 590692 kb |
| Host | smart-d37a7039-c14a-4bb2-88be-d46344507e14 |
| User | root |
| Command | /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +run_same_csr_outstanding +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=733405330 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c m_log /dev/null -cm_name 16.chip_same_csr_outstanding.733405330 |
| Directory | /workspace/16.chip_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/16.xbar_access_same_device.2014580667 |
| Short name | T2694 |
| Test name | |
| Test status | |
| Simulation time | 2027376533 ps |
| CPU time | 88.63 seconds |
| Started | Jun 23 07:25:13 PM PDT 24 |
| Finished | Jun 23 07:26:42 PM PDT 24 |
| Peak memory | 574084 kb |
| Host | smart-c4fb1cfd-0521-4c4b-9bd3-3093af87ac9c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2014580667 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.xbar_access_same_device .2014580667 |
| Directory | /workspace/16.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/16.xbar_access_same_device_slow_rsp.777831333 |
| Short name | T2127 |
| Test name | |
| Test status | |
| Simulation time | 80096059852 ps |
| CPU time | 1398.37 seconds |
| Started | Jun 23 07:25:15 PM PDT 24 |
| Finished | Jun 23 07:48:34 PM PDT 24 |
| Peak memory | 574156 kb |
| Host | smart-4c0d2b4e-8c55-4077-ba42-0ee726a409f1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=777831333 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.xbar_access_same_d evice_slow_rsp.777831333 |
| Directory | /workspace/16.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/16.xbar_error_and_unmapped_addr.1007752058 |
| Short name | T1409 |
| Test name | |
| Test status | |
| Simulation time | 830711774 ps |
| CPU time | 34.08 seconds |
| Started | Jun 23 07:25:12 PM PDT 24 |
| Finished | Jun 23 07:25:47 PM PDT 24 |
| Peak memory | 573764 kb |
| Host | smart-ee80f1a2-83a0-455a-a039-c6221b9a722d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1007752058 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.xbar_error_and_unmapped_add r.1007752058 |
| Directory | /workspace/16.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/16.xbar_error_random.1909953733 |
| Short name | T1995 |
| Test name | |
| Test status | |
| Simulation time | 2102629389 ps |
| CPU time | 69.14 seconds |
| Started | Jun 23 07:25:14 PM PDT 24 |
| Finished | Jun 23 07:26:23 PM PDT 24 |
| Peak memory | 573732 kb |
| Host | smart-ec3ff079-4495-4cb1-9888-9de89b6ba5e6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1909953733 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.xbar_error_random.1909953733 |
| Directory | /workspace/16.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/16.xbar_random.1832155070 |
| Short name | T2824 |
| Test name | |
| Test status | |
| Simulation time | 243527172 ps |
| CPU time | 25.17 seconds |
| Started | Jun 23 07:25:09 PM PDT 24 |
| Finished | Jun 23 07:25:34 PM PDT 24 |
| Peak memory | 574100 kb |
| Host | smart-36077341-f775-490a-815b-ff07b149f337 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1832155070 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.xbar_random.1832155070 |
| Directory | /workspace/16.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/16.xbar_random_large_delays.341495368 |
| Short name | T538 |
| Test name | |
| Test status | |
| Simulation time | 40478355077 ps |
| CPU time | 438.06 seconds |
| Started | Jun 23 07:25:09 PM PDT 24 |
| Finished | Jun 23 07:32:27 PM PDT 24 |
| Peak memory | 574156 kb |
| Host | smart-a392b747-cd27-44ec-aa65-b78b45485c76 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=341495368 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.xbar_random_large_delays.341495368 |
| Directory | /workspace/16.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/16.xbar_random_slow_rsp.2121708163 |
| Short name | T1509 |
| Test name | |
| Test status | |
| Simulation time | 26143160980 ps |
| CPU time | 457.16 seconds |
| Started | Jun 23 07:25:08 PM PDT 24 |
| Finished | Jun 23 07:32:46 PM PDT 24 |
| Peak memory | 573496 kb |
| Host | smart-7006aa25-5df0-4e4a-bd1f-d6b73c51e558 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2121708163 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.xbar_random_slow_rsp.2121708163 |
| Directory | /workspace/16.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/16.xbar_random_zero_delays.1384394763 |
| Short name | T2726 |
| Test name | |
| Test status | |
| Simulation time | 364347837 ps |
| CPU time | 33.14 seconds |
| Started | Jun 23 07:25:10 PM PDT 24 |
| Finished | Jun 23 07:25:43 PM PDT 24 |
| Peak memory | 573408 kb |
| Host | smart-d0b69f4c-424b-447f-86eb-04027399784d |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1384394763 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.xbar_random_zero_del ays.1384394763 |
| Directory | /workspace/16.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/16.xbar_same_source.2810648682 |
| Short name | T485 |
| Test name | |
| Test status | |
| Simulation time | 237084310 ps |
| CPU time | 21.53 seconds |
| Started | Jun 23 07:25:12 PM PDT 24 |
| Finished | Jun 23 07:25:34 PM PDT 24 |
| Peak memory | 573460 kb |
| Host | smart-3904cc80-2b3a-4d12-bb30-41a26a418e88 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2810648682 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.xbar_same_source.2810648682 |
| Directory | /workspace/16.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/16.xbar_smoke.1917738383 |
| Short name | T1488 |
| Test name | |
| Test status | |
| Simulation time | 50657175 ps |
| CPU time | 6.58 seconds |
| Started | Jun 23 07:25:10 PM PDT 24 |
| Finished | Jun 23 07:25:17 PM PDT 24 |
| Peak memory | 565844 kb |
| Host | smart-f618b0ef-e3d3-4b1b-98cd-547be3c985b5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1917738383 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.xbar_smoke.1917738383 |
| Directory | /workspace/16.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/16.xbar_smoke_large_delays.1526898715 |
| Short name | T1529 |
| Test name | |
| Test status | |
| Simulation time | 7776971337 ps |
| CPU time | 85.43 seconds |
| Started | Jun 23 07:25:11 PM PDT 24 |
| Finished | Jun 23 07:26:37 PM PDT 24 |
| Peak memory | 565532 kb |
| Host | smart-70771629-f536-4543-b6ba-c2d6bbb36b15 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1526898715 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.xbar_smoke_large_delays.1526898715 |
| Directory | /workspace/16.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/16.xbar_smoke_slow_rsp.4244259011 |
| Short name | T2405 |
| Test name | |
| Test status | |
| Simulation time | 2893499380 ps |
| CPU time | 47.63 seconds |
| Started | Jun 23 07:25:07 PM PDT 24 |
| Finished | Jun 23 07:25:55 PM PDT 24 |
| Peak memory | 565268 kb |
| Host | smart-af9946f7-a477-4c02-b13d-8a007f6c64a7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4244259011 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.xbar_smoke_slow_rsp.4244259011 |
| Directory | /workspace/16.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/16.xbar_smoke_zero_delays.3846281582 |
| Short name | T2773 |
| Test name | |
| Test status | |
| Simulation time | 49787123 ps |
| CPU time | 6.57 seconds |
| Started | Jun 23 07:25:09 PM PDT 24 |
| Finished | Jun 23 07:25:16 PM PDT 24 |
| Peak memory | 565496 kb |
| Host | smart-22645c9d-0fa0-42d1-acd1-7078913b9f4d |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3846281582 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.xbar_smoke_zero_delay s.3846281582 |
| Directory | /workspace/16.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/16.xbar_stress_all.3041334806 |
| Short name | T1986 |
| Test name | |
| Test status | |
| Simulation time | 664177230 ps |
| CPU time | 58.68 seconds |
| Started | Jun 23 07:25:12 PM PDT 24 |
| Finished | Jun 23 07:26:11 PM PDT 24 |
| Peak memory | 574180 kb |
| Host | smart-01d3b2c4-2267-4b6e-9f5a-18776d9c5ca9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3041334806 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.xbar_stress_all.3041334806 |
| Directory | /workspace/16.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/16.xbar_stress_all_with_error.3196107887 |
| Short name | T2383 |
| Test name | |
| Test status | |
| Simulation time | 2417018947 ps |
| CPU time | 162.87 seconds |
| Started | Jun 23 07:25:14 PM PDT 24 |
| Finished | Jun 23 07:27:57 PM PDT 24 |
| Peak memory | 574224 kb |
| Host | smart-dcf9eca8-1bc1-4cb3-90fe-00a596b99ca6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3196107887 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.xbar_stress_all_with_error.3196107887 |
| Directory | /workspace/16.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/16.xbar_stress_all_with_rand_reset.27700038 |
| Short name | T2392 |
| Test name | |
| Test status | |
| Simulation time | 1044664173 ps |
| CPU time | 283.12 seconds |
| Started | Jun 23 07:25:14 PM PDT 24 |
| Finished | Jun 23 07:29:57 PM PDT 24 |
| Peak memory | 574188 kb |
| Host | smart-047e9d0a-4cbf-4f05-acb3-0faa2949ab76 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27700038 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_rese t_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.xbar_stress_all_w ith_rand_reset.27700038 |
| Directory | /workspace/16.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/16.xbar_stress_all_with_reset_error.3026785432 |
| Short name | T2226 |
| Test name | |
| Test status | |
| Simulation time | 122986836 ps |
| CPU time | 48.52 seconds |
| Started | Jun 23 07:25:12 PM PDT 24 |
| Finished | Jun 23 07:26:01 PM PDT 24 |
| Peak memory | 576292 kb |
| Host | smart-1571dd8c-d31e-457c-9fb0-8480a1e81252 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3026785432 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.xbar_stress_al l_with_reset_error.3026785432 |
| Directory | /workspace/16.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/16.xbar_unmapped_addr.846394530 |
| Short name | T656 |
| Test name | |
| Test status | |
| Simulation time | 704869140 ps |
| CPU time | 29.07 seconds |
| Started | Jun 23 07:25:13 PM PDT 24 |
| Finished | Jun 23 07:25:43 PM PDT 24 |
| Peak memory | 573984 kb |
| Host | smart-ac43b6a2-c172-4df8-8747-9c212ff7b656 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=846394530 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.xbar_unmapped_addr.846394530 |
| Directory | /workspace/16.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/17.chip_csr_rw.3500289032 |
| Short name | T2022 |
| Test name | |
| Test status | |
| Simulation time | 5174042532 ps |
| CPU time | 564.63 seconds |
| Started | Jun 23 07:25:27 PM PDT 24 |
| Finished | Jun 23 07:34:52 PM PDT 24 |
| Peak memory | 595532 kb |
| Host | smart-915fe003-8922-4ea0-ad81-f9df5671e4d2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3500289032 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.chip_csr_rw.3500289032 |
| Directory | /workspace/17.chip_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/17.chip_same_csr_outstanding.2787803543 |
| Short name | T1849 |
| Test name | |
| Test status | |
| Simulation time | 29369911398 ps |
| CPU time | 3816.34 seconds |
| Started | Jun 23 07:25:18 PM PDT 24 |
| Finished | Jun 23 08:28:55 PM PDT 24 |
| Peak memory | 591100 kb |
| Host | smart-35894c9f-a6f7-4de7-a7bc-36abe066a36e |
| User | root |
| Command | /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +run_same_csr_outstanding +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2787803543 -assert nopostproc +UVM_TE STNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb - cm_log /dev/null -cm_name 17.chip_same_csr_outstanding.2787803543 |
| Directory | /workspace/17.chip_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/17.chip_tl_errors.2995089049 |
| Short name | T534 |
| Test name | |
| Test status | |
| Simulation time | 4409738210 ps |
| CPU time | 332.12 seconds |
| Started | Jun 23 07:25:16 PM PDT 24 |
| Finished | Jun 23 07:30:48 PM PDT 24 |
| Peak memory | 603544 kb |
| Host | smart-0432c575-8be8-4ab0-82d7-d612ce314530 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2995089049 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.chip_tl_errors.2995089049 |
| Directory | /workspace/17.chip_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/17.xbar_access_same_device.986135381 |
| Short name | T1968 |
| Test name | |
| Test status | |
| Simulation time | 985894782 ps |
| CPU time | 45.88 seconds |
| Started | Jun 23 07:25:26 PM PDT 24 |
| Finished | Jun 23 07:26:12 PM PDT 24 |
| Peak memory | 573868 kb |
| Host | smart-c69d1396-86fc-4745-ae23-9be0cc06f915 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=986135381 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.xbar_access_same_device. 986135381 |
| Directory | /workspace/17.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/17.xbar_access_same_device_slow_rsp.1895201556 |
| Short name | T1541 |
| Test name | |
| Test status | |
| Simulation time | 58276371053 ps |
| CPU time | 1024.26 seconds |
| Started | Jun 23 07:25:33 PM PDT 24 |
| Finished | Jun 23 07:42:38 PM PDT 24 |
| Peak memory | 573464 kb |
| Host | smart-c6d7aa65-29e6-462e-b1b1-0dc463583500 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1895201556 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.xbar_access_same_ device_slow_rsp.1895201556 |
| Directory | /workspace/17.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/17.xbar_error_and_unmapped_addr.1603252342 |
| Short name | T1395 |
| Test name | |
| Test status | |
| Simulation time | 852187436 ps |
| CPU time | 33.38 seconds |
| Started | Jun 23 07:25:32 PM PDT 24 |
| Finished | Jun 23 07:26:06 PM PDT 24 |
| Peak memory | 573388 kb |
| Host | smart-f8fb7208-e090-4d2e-8f6d-16ee06237a5d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1603252342 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.xbar_error_and_unmapped_add r.1603252342 |
| Directory | /workspace/17.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/17.xbar_error_random.1534310807 |
| Short name | T1997 |
| Test name | |
| Test status | |
| Simulation time | 135308375 ps |
| CPU time | 13.35 seconds |
| Started | Jun 23 07:25:33 PM PDT 24 |
| Finished | Jun 23 07:25:47 PM PDT 24 |
| Peak memory | 573716 kb |
| Host | smart-9347a72d-119c-4f41-81bb-a0be73335cdb |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1534310807 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.xbar_error_random.1534310807 |
| Directory | /workspace/17.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/17.xbar_random.1329260296 |
| Short name | T2597 |
| Test name | |
| Test status | |
| Simulation time | 414885610 ps |
| CPU time | 37.75 seconds |
| Started | Jun 23 07:25:28 PM PDT 24 |
| Finished | Jun 23 07:26:06 PM PDT 24 |
| Peak memory | 574140 kb |
| Host | smart-2a1912c6-19ac-477e-81e1-41f02266a1f8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1329260296 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.xbar_random.1329260296 |
| Directory | /workspace/17.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/17.xbar_random_large_delays.4190507393 |
| Short name | T558 |
| Test name | |
| Test status | |
| Simulation time | 79842320010 ps |
| CPU time | 817.85 seconds |
| Started | Jun 23 07:25:28 PM PDT 24 |
| Finished | Jun 23 07:39:07 PM PDT 24 |
| Peak memory | 574232 kb |
| Host | smart-26c4b268-5b99-42df-8698-ad39f1e2ca64 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4190507393 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.xbar_random_large_delays.4190507393 |
| Directory | /workspace/17.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/17.xbar_random_slow_rsp.3594130062 |
| Short name | T617 |
| Test name | |
| Test status | |
| Simulation time | 51772594355 ps |
| CPU time | 788.09 seconds |
| Started | Jun 23 07:25:30 PM PDT 24 |
| Finished | Jun 23 07:38:38 PM PDT 24 |
| Peak memory | 573500 kb |
| Host | smart-9946a022-6241-4d88-8734-0ed87c901026 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3594130062 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.xbar_random_slow_rsp.3594130062 |
| Directory | /workspace/17.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/17.xbar_random_zero_delays.1545309644 |
| Short name | T2088 |
| Test name | |
| Test status | |
| Simulation time | 487522115 ps |
| CPU time | 45.87 seconds |
| Started | Jun 23 07:25:22 PM PDT 24 |
| Finished | Jun 23 07:26:08 PM PDT 24 |
| Peak memory | 573420 kb |
| Host | smart-1faf2571-715f-4e2c-92a4-8717f50552ac |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1545309644 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.xbar_random_zero_del ays.1545309644 |
| Directory | /workspace/17.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/17.xbar_same_source.225364904 |
| Short name | T578 |
| Test name | |
| Test status | |
| Simulation time | 1382684338 ps |
| CPU time | 44.06 seconds |
| Started | Jun 23 07:25:28 PM PDT 24 |
| Finished | Jun 23 07:26:13 PM PDT 24 |
| Peak memory | 574100 kb |
| Host | smart-fef95a56-c80d-4273-99ad-78d0bcf56eb3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=225364904 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.xbar_same_source.225364904 |
| Directory | /workspace/17.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/17.xbar_smoke.3240762445 |
| Short name | T662 |
| Test name | |
| Test status | |
| Simulation time | 49205076 ps |
| CPU time | 7.22 seconds |
| Started | Jun 23 07:25:23 PM PDT 24 |
| Finished | Jun 23 07:25:31 PM PDT 24 |
| Peak memory | 565464 kb |
| Host | smart-2c586d78-b8d2-436e-96c1-a45e71de85ee |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3240762445 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.xbar_smoke.3240762445 |
| Directory | /workspace/17.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/17.xbar_smoke_large_delays.2601487184 |
| Short name | T2783 |
| Test name | |
| Test status | |
| Simulation time | 9365585466 ps |
| CPU time | 100.89 seconds |
| Started | Jun 23 07:25:24 PM PDT 24 |
| Finished | Jun 23 07:27:05 PM PDT 24 |
| Peak memory | 565548 kb |
| Host | smart-6053842b-cbc0-4c42-a727-650ec6d70e15 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2601487184 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.xbar_smoke_large_delays.2601487184 |
| Directory | /workspace/17.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/17.xbar_smoke_slow_rsp.2296016444 |
| Short name | T1992 |
| Test name | |
| Test status | |
| Simulation time | 5044195918 ps |
| CPU time | 83.02 seconds |
| Started | Jun 23 07:25:26 PM PDT 24 |
| Finished | Jun 23 07:26:49 PM PDT 24 |
| Peak memory | 565644 kb |
| Host | smart-de6304c3-9799-4f62-9383-5f6248224da2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2296016444 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.xbar_smoke_slow_rsp.2296016444 |
| Directory | /workspace/17.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/17.xbar_smoke_zero_delays.3657763322 |
| Short name | T2075 |
| Test name | |
| Test status | |
| Simulation time | 45874775 ps |
| CPU time | 6.64 seconds |
| Started | Jun 23 07:25:25 PM PDT 24 |
| Finished | Jun 23 07:25:33 PM PDT 24 |
| Peak memory | 565288 kb |
| Host | smart-915e261c-2169-4268-a4c2-72f7faeca5c8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3657763322 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.xbar_smoke_zero_delay s.3657763322 |
| Directory | /workspace/17.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/17.xbar_stress_all_with_error.1498347849 |
| Short name | T1889 |
| Test name | |
| Test status | |
| Simulation time | 3414718322 ps |
| CPU time | 127.39 seconds |
| Started | Jun 23 07:25:33 PM PDT 24 |
| Finished | Jun 23 07:27:41 PM PDT 24 |
| Peak memory | 573468 kb |
| Host | smart-6776ea5b-e1e5-427d-85c0-7f03b58f139a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1498347849 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.xbar_stress_all_with_error.1498347849 |
| Directory | /workspace/17.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/17.xbar_stress_all_with_rand_reset.82158189 |
| Short name | T2268 |
| Test name | |
| Test status | |
| Simulation time | 4759074741 ps |
| CPU time | 693.91 seconds |
| Started | Jun 23 07:25:33 PM PDT 24 |
| Finished | Jun 23 07:37:08 PM PDT 24 |
| Peak memory | 576344 kb |
| Host | smart-4623242d-3a68-4a13-b8d5-11da21031692 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82158189 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_rese t_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.xbar_stress_all_w ith_rand_reset.82158189 |
| Directory | /workspace/17.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/17.xbar_stress_all_with_reset_error.4094066071 |
| Short name | T1749 |
| Test name | |
| Test status | |
| Simulation time | 479248288 ps |
| CPU time | 141.84 seconds |
| Started | Jun 23 07:25:30 PM PDT 24 |
| Finished | Jun 23 07:27:52 PM PDT 24 |
| Peak memory | 574272 kb |
| Host | smart-195c8fcc-19b7-4df9-af73-51dd26b57fe9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4094066071 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.xbar_stress_al l_with_reset_error.4094066071 |
| Directory | /workspace/17.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/17.xbar_unmapped_addr.623285463 |
| Short name | T562 |
| Test name | |
| Test status | |
| Simulation time | 317170292 ps |
| CPU time | 44.08 seconds |
| Started | Jun 23 07:25:26 PM PDT 24 |
| Finished | Jun 23 07:26:10 PM PDT 24 |
| Peak memory | 573456 kb |
| Host | smart-c2bfb351-4118-4b1b-afa3-c66ffafd51ec |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=623285463 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.xbar_unmapped_addr.623285463 |
| Directory | /workspace/17.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/18.chip_csr_rw.2834612839 |
| Short name | T389 |
| Test name | |
| Test status | |
| Simulation time | 4228154300 ps |
| CPU time | 295.57 seconds |
| Started | Jun 23 07:25:55 PM PDT 24 |
| Finished | Jun 23 07:30:51 PM PDT 24 |
| Peak memory | 595948 kb |
| Host | smart-136f5ca7-e1e0-4a42-b934-b811d09efa0b |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2834612839 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.chip_csr_rw.2834612839 |
| Directory | /workspace/18.chip_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/18.chip_same_csr_outstanding.395556028 |
| Short name | T377 |
| Test name | |
| Test status | |
| Simulation time | 27183414792 ps |
| CPU time | 4131.49 seconds |
| Started | Jun 23 07:25:32 PM PDT 24 |
| Finished | Jun 23 08:34:25 PM PDT 24 |
| Peak memory | 591180 kb |
| Host | smart-9a258dff-baef-4484-b977-5e1accd757d4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +run_same_csr_outstanding +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=395556028 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c m_log /dev/null -cm_name 18.chip_same_csr_outstanding.395556028 |
| Directory | /workspace/18.chip_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/18.chip_tl_errors.1917095357 |
| Short name | T719 |
| Test name | |
| Test status | |
| Simulation time | 3829057456 ps |
| CPU time | 204.71 seconds |
| Started | Jun 23 07:25:32 PM PDT 24 |
| Finished | Jun 23 07:28:57 PM PDT 24 |
| Peak memory | 597400 kb |
| Host | smart-618fce18-6be6-4e4d-9243-7056acd9ede4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1917095357 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.chip_tl_errors.1917095357 |
| Directory | /workspace/18.chip_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/18.xbar_access_same_device.4169417244 |
| Short name | T2527 |
| Test name | |
| Test status | |
| Simulation time | 252876328 ps |
| CPU time | 20.61 seconds |
| Started | Jun 23 07:25:49 PM PDT 24 |
| Finished | Jun 23 07:26:10 PM PDT 24 |
| Peak memory | 574096 kb |
| Host | smart-abe21666-0983-4b27-a926-c634a6588d48 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4169417244 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.xbar_access_same_device .4169417244 |
| Directory | /workspace/18.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/18.xbar_access_same_device_slow_rsp.46538734 |
| Short name | T706 |
| Test name | |
| Test status | |
| Simulation time | 69524763130 ps |
| CPU time | 1150.46 seconds |
| Started | Jun 23 07:25:51 PM PDT 24 |
| Finished | Jun 23 07:45:02 PM PDT 24 |
| Peak memory | 574196 kb |
| Host | smart-22abea4a-3ffe-4ec8-9518-19e38e5e675c |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46538734 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.xbar_access_same_de vice_slow_rsp.46538734 |
| Directory | /workspace/18.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/18.xbar_error_and_unmapped_addr.3621659424 |
| Short name | T2406 |
| Test name | |
| Test status | |
| Simulation time | 136689114 ps |
| CPU time | 17.96 seconds |
| Started | Jun 23 07:25:54 PM PDT 24 |
| Finished | Jun 23 07:26:12 PM PDT 24 |
| Peak memory | 573352 kb |
| Host | smart-d4a607b9-18dd-483f-9429-c485b8d5e15f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3621659424 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.xbar_error_and_unmapped_add r.3621659424 |
| Directory | /workspace/18.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/18.xbar_error_random.3492785679 |
| Short name | T1919 |
| Test name | |
| Test status | |
| Simulation time | 2347283984 ps |
| CPU time | 83.94 seconds |
| Started | Jun 23 07:25:51 PM PDT 24 |
| Finished | Jun 23 07:27:16 PM PDT 24 |
| Peak memory | 573376 kb |
| Host | smart-215fd22f-6d85-4e9a-bc6e-f341cf866111 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3492785679 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.xbar_error_random.3492785679 |
| Directory | /workspace/18.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/18.xbar_random.1400354141 |
| Short name | T2592 |
| Test name | |
| Test status | |
| Simulation time | 344636992 ps |
| CPU time | 34.35 seconds |
| Started | Jun 23 07:25:50 PM PDT 24 |
| Finished | Jun 23 07:26:25 PM PDT 24 |
| Peak memory | 574084 kb |
| Host | smart-0c418fa4-bb53-475e-a678-00bbfed15d73 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1400354141 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.xbar_random.1400354141 |
| Directory | /workspace/18.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/18.xbar_random_large_delays.2441683250 |
| Short name | T2814 |
| Test name | |
| Test status | |
| Simulation time | 7557427820 ps |
| CPU time | 83.82 seconds |
| Started | Jun 23 07:25:50 PM PDT 24 |
| Finished | Jun 23 07:27:14 PM PDT 24 |
| Peak memory | 565948 kb |
| Host | smart-dc01954b-3cd2-4bc4-a878-fc28bbca4053 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2441683250 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.xbar_random_large_delays.2441683250 |
| Directory | /workspace/18.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/18.xbar_random_slow_rsp.1535867314 |
| Short name | T2618 |
| Test name | |
| Test status | |
| Simulation time | 3921029492 ps |
| CPU time | 69.63 seconds |
| Started | Jun 23 07:25:50 PM PDT 24 |
| Finished | Jun 23 07:26:59 PM PDT 24 |
| Peak memory | 565256 kb |
| Host | smart-c8b440e5-59d3-4373-affc-870ae23e9442 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1535867314 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.xbar_random_slow_rsp.1535867314 |
| Directory | /workspace/18.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/18.xbar_random_zero_delays.2334177405 |
| Short name | T518 |
| Test name | |
| Test status | |
| Simulation time | 581936542 ps |
| CPU time | 49.29 seconds |
| Started | Jun 23 07:25:50 PM PDT 24 |
| Finished | Jun 23 07:26:40 PM PDT 24 |
| Peak memory | 573708 kb |
| Host | smart-ac6f07b0-405a-4e17-9a89-09b8cf8cf3bd |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2334177405 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.xbar_random_zero_del ays.2334177405 |
| Directory | /workspace/18.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/18.xbar_same_source.1482968601 |
| Short name | T2379 |
| Test name | |
| Test status | |
| Simulation time | 1839350563 ps |
| CPU time | 49.47 seconds |
| Started | Jun 23 07:25:50 PM PDT 24 |
| Finished | Jun 23 07:26:40 PM PDT 24 |
| Peak memory | 574044 kb |
| Host | smart-6c20f8d4-0439-40c7-80ce-b78e3207dd0f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1482968601 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.xbar_same_source.1482968601 |
| Directory | /workspace/18.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/18.xbar_smoke.2004540689 |
| Short name | T2254 |
| Test name | |
| Test status | |
| Simulation time | 46519258 ps |
| CPU time | 6.8 seconds |
| Started | Jun 23 07:25:33 PM PDT 24 |
| Finished | Jun 23 07:25:41 PM PDT 24 |
| Peak memory | 565196 kb |
| Host | smart-5a62559d-069f-4467-80bb-0d1ee642e090 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2004540689 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.xbar_smoke.2004540689 |
| Directory | /workspace/18.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/18.xbar_smoke_large_delays.1941841810 |
| Short name | T2779 |
| Test name | |
| Test status | |
| Simulation time | 9057895330 ps |
| CPU time | 99.21 seconds |
| Started | Jun 23 07:25:46 PM PDT 24 |
| Finished | Jun 23 07:27:26 PM PDT 24 |
| Peak memory | 565252 kb |
| Host | smart-2c0b5155-42d1-4e80-b98d-a315891c01ef |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1941841810 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.xbar_smoke_large_delays.1941841810 |
| Directory | /workspace/18.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/18.xbar_smoke_slow_rsp.3501268811 |
| Short name | T2551 |
| Test name | |
| Test status | |
| Simulation time | 3430995675 ps |
| CPU time | 58.87 seconds |
| Started | Jun 23 07:25:44 PM PDT 24 |
| Finished | Jun 23 07:26:43 PM PDT 24 |
| Peak memory | 565524 kb |
| Host | smart-0d39f12f-e089-4f13-b76c-e6bae3ce8ace |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3501268811 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.xbar_smoke_slow_rsp.3501268811 |
| Directory | /workspace/18.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/18.xbar_smoke_zero_delays.2983343512 |
| Short name | T1414 |
| Test name | |
| Test status | |
| Simulation time | 49637464 ps |
| CPU time | 6.66 seconds |
| Started | Jun 23 07:25:33 PM PDT 24 |
| Finished | Jun 23 07:25:40 PM PDT 24 |
| Peak memory | 565536 kb |
| Host | smart-c818c9b6-b85e-4755-aa8f-3b80e3b33f6f |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2983343512 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.xbar_smoke_zero_delay s.2983343512 |
| Directory | /workspace/18.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/18.xbar_stress_all.1121922166 |
| Short name | T2427 |
| Test name | |
| Test status | |
| Simulation time | 10868297760 ps |
| CPU time | 423.58 seconds |
| Started | Jun 23 07:25:55 PM PDT 24 |
| Finished | Jun 23 07:32:59 PM PDT 24 |
| Peak memory | 574252 kb |
| Host | smart-e94a7b0a-dffd-4bc0-b54a-82f153da3da7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1121922166 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.xbar_stress_all.1121922166 |
| Directory | /workspace/18.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/18.xbar_stress_all_with_error.3644282453 |
| Short name | T574 |
| Test name | |
| Test status | |
| Simulation time | 17478280224 ps |
| CPU time | 640.08 seconds |
| Started | Jun 23 07:25:57 PM PDT 24 |
| Finished | Jun 23 07:36:37 PM PDT 24 |
| Peak memory | 574376 kb |
| Host | smart-a4ffc37b-2a15-44c1-acb6-ad7e6c0c3318 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3644282453 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.xbar_stress_all_with_error.3644282453 |
| Directory | /workspace/18.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/18.xbar_stress_all_with_rand_reset.4104527926 |
| Short name | T2822 |
| Test name | |
| Test status | |
| Simulation time | 1992568386 ps |
| CPU time | 439.69 seconds |
| Started | Jun 23 07:25:54 PM PDT 24 |
| Finished | Jun 23 07:33:15 PM PDT 24 |
| Peak memory | 574228 kb |
| Host | smart-eac57efb-cd02-4491-a17d-5c7ee93b8264 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4104527926 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.xbar_stress_all _with_rand_reset.4104527926 |
| Directory | /workspace/18.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/18.xbar_stress_all_with_reset_error.2972158323 |
| Short name | T2360 |
| Test name | |
| Test status | |
| Simulation time | 7037926147 ps |
| CPU time | 357.34 seconds |
| Started | Jun 23 07:25:57 PM PDT 24 |
| Finished | Jun 23 07:31:55 PM PDT 24 |
| Peak memory | 577384 kb |
| Host | smart-0b787100-d018-456a-bcfe-84be737d59b3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2972158323 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.xbar_stress_al l_with_reset_error.2972158323 |
| Directory | /workspace/18.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/18.xbar_unmapped_addr.3182217331 |
| Short name | T1620 |
| Test name | |
| Test status | |
| Simulation time | 328817430 ps |
| CPU time | 18.62 seconds |
| Started | Jun 23 07:25:51 PM PDT 24 |
| Finished | Jun 23 07:26:10 PM PDT 24 |
| Peak memory | 574152 kb |
| Host | smart-ea81540a-7200-49ef-aa41-232a3fb8d3fa |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3182217331 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.xbar_unmapped_addr.3182217331 |
| Directory | /workspace/18.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/19.chip_csr_rw.776007912 |
| Short name | T1581 |
| Test name | |
| Test status | |
| Simulation time | 5312619323 ps |
| CPU time | 518.56 seconds |
| Started | Jun 23 07:26:23 PM PDT 24 |
| Finished | Jun 23 07:35:01 PM PDT 24 |
| Peak memory | 596456 kb |
| Host | smart-be4efbf9-bfea-4360-967c-55df745d1deb |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=776007912 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.chip_csr_rw.776007912 |
| Directory | /workspace/19.chip_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/19.chip_same_csr_outstanding.3915910372 |
| Short name | T390 |
| Test name | |
| Test status | |
| Simulation time | 16858360784 ps |
| CPU time | 2639.58 seconds |
| Started | Jun 23 07:26:00 PM PDT 24 |
| Finished | Jun 23 08:10:00 PM PDT 24 |
| Peak memory | 591228 kb |
| Host | smart-2a3d98e9-eafb-4372-b918-9da384883d9b |
| User | root |
| Command | /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +run_same_csr_outstanding +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3915910372 -assert nopostproc +UVM_TE STNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb - cm_log /dev/null -cm_name 19.chip_same_csr_outstanding.3915910372 |
| Directory | /workspace/19.chip_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/19.xbar_access_same_device.876022239 |
| Short name | T2191 |
| Test name | |
| Test status | |
| Simulation time | 1717927477 ps |
| CPU time | 63.61 seconds |
| Started | Jun 23 07:26:21 PM PDT 24 |
| Finished | Jun 23 07:27:25 PM PDT 24 |
| Peak memory | 573452 kb |
| Host | smart-1d322860-0976-4e13-a79c-8f99a67e7638 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=876022239 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.xbar_access_same_device. 876022239 |
| Directory | /workspace/19.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/19.xbar_access_same_device_slow_rsp.4143647398 |
| Short name | T853 |
| Test name | |
| Test status | |
| Simulation time | 81784539351 ps |
| CPU time | 1490.28 seconds |
| Started | Jun 23 07:26:21 PM PDT 24 |
| Finished | Jun 23 07:51:12 PM PDT 24 |
| Peak memory | 574384 kb |
| Host | smart-a98cec81-9a49-403b-9476-c7c3187b3914 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4143647398 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.xbar_access_same_ device_slow_rsp.4143647398 |
| Directory | /workspace/19.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/19.xbar_error_and_unmapped_addr.2508187961 |
| Short name | T2481 |
| Test name | |
| Test status | |
| Simulation time | 1437234066 ps |
| CPU time | 49.25 seconds |
| Started | Jun 23 07:26:26 PM PDT 24 |
| Finished | Jun 23 07:27:16 PM PDT 24 |
| Peak memory | 573728 kb |
| Host | smart-e965bbfe-ac20-426a-abcb-aaa23d442ebc |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2508187961 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.xbar_error_and_unmapped_add r.2508187961 |
| Directory | /workspace/19.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/19.xbar_error_random.1439011495 |
| Short name | T1437 |
| Test name | |
| Test status | |
| Simulation time | 2255953684 ps |
| CPU time | 70.75 seconds |
| Started | Jun 23 07:26:19 PM PDT 24 |
| Finished | Jun 23 07:27:30 PM PDT 24 |
| Peak memory | 573776 kb |
| Host | smart-2e0af782-a23e-433f-89e2-9b48c615a97e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1439011495 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.xbar_error_random.1439011495 |
| Directory | /workspace/19.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/19.xbar_random.2914248213 |
| Short name | T1743 |
| Test name | |
| Test status | |
| Simulation time | 67091811 ps |
| CPU time | 9.56 seconds |
| Started | Jun 23 07:26:06 PM PDT 24 |
| Finished | Jun 23 07:26:15 PM PDT 24 |
| Peak memory | 574104 kb |
| Host | smart-2e5ce462-0737-496a-8688-361d32bfc481 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2914248213 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.xbar_random.2914248213 |
| Directory | /workspace/19.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/19.xbar_random_large_delays.2250289294 |
| Short name | T2530 |
| Test name | |
| Test status | |
| Simulation time | 33897947768 ps |
| CPU time | 358.79 seconds |
| Started | Jun 23 07:26:07 PM PDT 24 |
| Finished | Jun 23 07:32:06 PM PDT 24 |
| Peak memory | 574212 kb |
| Host | smart-cd8606c7-d5cd-4e96-af1d-72b8b634be01 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2250289294 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.xbar_random_large_delays.2250289294 |
| Directory | /workspace/19.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/19.xbar_random_slow_rsp.3101458832 |
| Short name | T2371 |
| Test name | |
| Test status | |
| Simulation time | 35300776236 ps |
| CPU time | 572.27 seconds |
| Started | Jun 23 07:26:19 PM PDT 24 |
| Finished | Jun 23 07:35:52 PM PDT 24 |
| Peak memory | 574168 kb |
| Host | smart-b5fcfc58-7982-44a2-8aaf-0257a14f2ad3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3101458832 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.xbar_random_slow_rsp.3101458832 |
| Directory | /workspace/19.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/19.xbar_random_zero_delays.1428070946 |
| Short name | T557 |
| Test name | |
| Test status | |
| Simulation time | 634925158 ps |
| CPU time | 53.63 seconds |
| Started | Jun 23 07:26:05 PM PDT 24 |
| Finished | Jun 23 07:26:58 PM PDT 24 |
| Peak memory | 574072 kb |
| Host | smart-2295eceb-008b-4740-a684-2303ccab66ff |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1428070946 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.xbar_random_zero_del ays.1428070946 |
| Directory | /workspace/19.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/19.xbar_same_source.1069968378 |
| Short name | T1847 |
| Test name | |
| Test status | |
| Simulation time | 1823767857 ps |
| CPU time | 52.09 seconds |
| Started | Jun 23 07:26:20 PM PDT 24 |
| Finished | Jun 23 07:27:13 PM PDT 24 |
| Peak memory | 573968 kb |
| Host | smart-674578fb-a1ba-4a2f-80c3-733d063772db |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1069968378 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.xbar_same_source.1069968378 |
| Directory | /workspace/19.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/19.xbar_smoke.2690417248 |
| Short name | T1432 |
| Test name | |
| Test status | |
| Simulation time | 174700804 ps |
| CPU time | 8.23 seconds |
| Started | Jun 23 07:26:02 PM PDT 24 |
| Finished | Jun 23 07:26:10 PM PDT 24 |
| Peak memory | 565180 kb |
| Host | smart-92bddbaa-5fcd-4173-a97d-85a840c39e83 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2690417248 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.xbar_smoke.2690417248 |
| Directory | /workspace/19.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/19.xbar_smoke_large_delays.193501232 |
| Short name | T1452 |
| Test name | |
| Test status | |
| Simulation time | 9181044599 ps |
| CPU time | 98.5 seconds |
| Started | Jun 23 07:26:01 PM PDT 24 |
| Finished | Jun 23 07:27:40 PM PDT 24 |
| Peak memory | 565912 kb |
| Host | smart-c2ea3e20-dbcc-4406-a795-a74fc9f3dac9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=193501232 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.xbar_smoke_large_delays.193501232 |
| Directory | /workspace/19.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/19.xbar_smoke_slow_rsp.2146099216 |
| Short name | T2050 |
| Test name | |
| Test status | |
| Simulation time | 5718419815 ps |
| CPU time | 91.78 seconds |
| Started | Jun 23 07:26:05 PM PDT 24 |
| Finished | Jun 23 07:27:37 PM PDT 24 |
| Peak memory | 565532 kb |
| Host | smart-d28de0c1-4873-4f32-8a1c-8aaf63b185dd |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2146099216 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.xbar_smoke_slow_rsp.2146099216 |
| Directory | /workspace/19.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/19.xbar_smoke_zero_delays.788927166 |
| Short name | T2026 |
| Test name | |
| Test status | |
| Simulation time | 38416808 ps |
| CPU time | 6 seconds |
| Started | Jun 23 07:26:01 PM PDT 24 |
| Finished | Jun 23 07:26:07 PM PDT 24 |
| Peak memory | 565132 kb |
| Host | smart-9d3dfb38-680c-4b08-ae99-f2fe7cf03b15 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=788927166 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.xbar_smoke_zero_delays .788927166 |
| Directory | /workspace/19.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/19.xbar_stress_all.2852240452 |
| Short name | T2464 |
| Test name | |
| Test status | |
| Simulation time | 4408264183 ps |
| CPU time | 419.95 seconds |
| Started | Jun 23 07:26:23 PM PDT 24 |
| Finished | Jun 23 07:33:24 PM PDT 24 |
| Peak memory | 574280 kb |
| Host | smart-c58019a7-d58a-4512-a543-9146789665f5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2852240452 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.xbar_stress_all.2852240452 |
| Directory | /workspace/19.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/19.xbar_stress_all_with_error.2655549313 |
| Short name | T1612 |
| Test name | |
| Test status | |
| Simulation time | 6868318881 ps |
| CPU time | 249.16 seconds |
| Started | Jun 23 07:26:27 PM PDT 24 |
| Finished | Jun 23 07:30:37 PM PDT 24 |
| Peak memory | 574280 kb |
| Host | smart-fc05a7cc-4e0e-4653-9937-87103ca34cf5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2655549313 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.xbar_stress_all_with_error.2655549313 |
| Directory | /workspace/19.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/19.xbar_stress_all_with_reset_error.2121616218 |
| Short name | T2136 |
| Test name | |
| Test status | |
| Simulation time | 15122825411 ps |
| CPU time | 708.23 seconds |
| Started | Jun 23 07:26:24 PM PDT 24 |
| Finished | Jun 23 07:38:13 PM PDT 24 |
| Peak memory | 576556 kb |
| Host | smart-30f21e4f-d635-47c0-8b78-8d816983f6f9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2121616218 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.xbar_stress_al l_with_reset_error.2121616218 |
| Directory | /workspace/19.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/19.xbar_unmapped_addr.3288486463 |
| Short name | T680 |
| Test name | |
| Test status | |
| Simulation time | 196649731 ps |
| CPU time | 21.73 seconds |
| Started | Jun 23 07:26:19 PM PDT 24 |
| Finished | Jun 23 07:26:41 PM PDT 24 |
| Peak memory | 573492 kb |
| Host | smart-fe7b8f00-4913-4e62-9614-18d1900bb55a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3288486463 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.xbar_unmapped_addr.3288486463 |
| Directory | /workspace/19.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/2.chip_csr_aliasing.1696427160 |
| Short name | T379 |
| Test name | |
| Test status | |
| Simulation time | 35780311374 ps |
| CPU time | 6599.32 seconds |
| Started | Jun 23 07:21:08 PM PDT 24 |
| Finished | Jun 23 09:11:09 PM PDT 24 |
| Peak memory | 592124 kb |
| Host | smart-18de7096-afa2-4327-8c65-7e1b041d839e |
| User | root |
| Command | /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +csr_aliasing +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1696427160 -assert nopostproc +UVM_TESTNAME=chip_ base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/ null -cm_name 2.chip_csr_aliasing.1696427160 |
| Directory | /workspace/2.chip_csr_aliasing/latest |
| Test location | /workspace/coverage/cover_reg_top/2.chip_csr_bit_bash.2811923310 |
| Short name | T1867 |
| Test name | |
| Test status | |
| Simulation time | 5409335677 ps |
| CPU time | 442.22 seconds |
| Started | Jun 23 07:21:14 PM PDT 24 |
| Finished | Jun 23 07:28:37 PM PDT 24 |
| Peak memory | 589780 kb |
| Host | smart-b41b43da-82d0-4179-827e-04b22ac8a37f |
| User | root |
| Command | /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +num_test_csrs=200 +csr_bit_bash +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2811923310 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to p.vdb -cm_log /dev/null -cm_name 2.chip_csr_bit_bash.2811923310 |
| Directory | /workspace/2.chip_csr_bit_bash/latest |
| Test location | /workspace/coverage/cover_reg_top/2.chip_csr_rw.2006900596 |
| Short name | T2298 |
| Test name | |
| Test status | |
| Simulation time | 5663323050 ps |
| CPU time | 667.09 seconds |
| Started | Jun 23 07:21:13 PM PDT 24 |
| Finished | Jun 23 07:32:21 PM PDT 24 |
| Peak memory | 595528 kb |
| Host | smart-0a374eb3-66f6-49b1-90d1-b2a65b2ed0e5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2006900596 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.chip_csr_rw.2006900596 |
| Directory | /workspace/2.chip_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/2.chip_prim_tl_access.4156392103 |
| Short name | T2498 |
| Test name | |
| Test status | |
| Simulation time | 14080034695 ps |
| CPU time | 541.73 seconds |
| Started | Jun 23 07:21:09 PM PDT 24 |
| Finished | Jun 23 07:30:11 PM PDT 24 |
| Peak memory | 587744 kb |
| Host | smart-bc36686d-f0e3-46f1-a34b-858db1179138 |
| User | root |
| Command | /workspace/cover_reg_top/simv +en_scb=0 +en_scb_tl_err_chk=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4156392103 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SE Q=chip_prim_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.chip_prim_tl_access.4156392103 |
| Directory | /workspace/2.chip_prim_tl_access/latest |
| Test location | /workspace/coverage/cover_reg_top/2.chip_rv_dm_lc_disabled.986771897 |
| Short name | T1576 |
| Test name | |
| Test status | |
| Simulation time | 12275390803 ps |
| CPU time | 663.51 seconds |
| Started | Jun 23 07:21:09 PM PDT 24 |
| Finished | Jun 23 07:32:13 PM PDT 24 |
| Peak memory | 588592 kb |
| Host | smart-5e4abe20-df6e-4d5d-ae64-505c1c5a6745 |
| User | root |
| Command | /workspace/cover_reg_top/simv +en_scb=0 +en_scb_tl_err_chk=0 +use_jtag_dmi=1 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=986771897 -assert nopostproc +UVM_TESTNAME=chip_base_te st +UVM_TEST_SEQ=chip_rv_dm_lc_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log / dev/null -cm_name 2.chip_rv_dm_lc_disabled.986771897 |
| Directory | /workspace/2.chip_rv_dm_lc_disabled/latest |
| Test location | /workspace/coverage/cover_reg_top/2.chip_tl_errors.780006897 |
| Short name | T720 |
| Test name | |
| Test status | |
| Simulation time | 3518244096 ps |
| CPU time | 143.25 seconds |
| Started | Jun 23 07:21:13 PM PDT 24 |
| Finished | Jun 23 07:23:37 PM PDT 24 |
| Peak memory | 596388 kb |
| Host | smart-3a39dcd7-5610-4fc6-82db-39da37eb86ce |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=780006897 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.chip_tl_errors.780006897 |
| Directory | /workspace/2.chip_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/2.xbar_access_same_device.3883022934 |
| Short name | T1725 |
| Test name | |
| Test status | |
| Simulation time | 586868700 ps |
| CPU time | 30.46 seconds |
| Started | Jun 23 07:21:18 PM PDT 24 |
| Finished | Jun 23 07:21:49 PM PDT 24 |
| Peak memory | 573416 kb |
| Host | smart-2f5ebec6-4de4-4b64-bb98-648d5d80dcc3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3883022934 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.xbar_access_same_device. 3883022934 |
| Directory | /workspace/2.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/2.xbar_access_same_device_slow_rsp.939218107 |
| Short name | T880 |
| Test name | |
| Test status | |
| Simulation time | 71162699135 ps |
| CPU time | 1297.45 seconds |
| Started | Jun 23 07:21:14 PM PDT 24 |
| Finished | Jun 23 07:42:52 PM PDT 24 |
| Peak memory | 574332 kb |
| Host | smart-7a19a7bf-b85b-4de4-93ef-b799dc814516 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=939218107 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.xbar_access_same_de vice_slow_rsp.939218107 |
| Directory | /workspace/2.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/2.xbar_error_and_unmapped_addr.1139557244 |
| Short name | T1372 |
| Test name | |
| Test status | |
| Simulation time | 36839110 ps |
| CPU time | 6.84 seconds |
| Started | Jun 23 07:21:19 PM PDT 24 |
| Finished | Jun 23 07:21:27 PM PDT 24 |
| Peak memory | 565668 kb |
| Host | smart-2a854f4c-4a20-4177-83cf-3484a9ea4589 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1139557244 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.xbar_error_and_unmapped_addr .1139557244 |
| Directory | /workspace/2.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/2.xbar_error_random.1123578345 |
| Short name | T2364 |
| Test name | |
| Test status | |
| Simulation time | 42155091 ps |
| CPU time | 6.26 seconds |
| Started | Jun 23 07:21:19 PM PDT 24 |
| Finished | Jun 23 07:21:26 PM PDT 24 |
| Peak memory | 565084 kb |
| Host | smart-c6e03180-76a3-43b3-ac0b-25cf60d6ba76 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1123578345 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.xbar_error_random.1123578345 |
| Directory | /workspace/2.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/2.xbar_random.2566390026 |
| Short name | T1487 |
| Test name | |
| Test status | |
| Simulation time | 288540565 ps |
| CPU time | 28.14 seconds |
| Started | Jun 23 07:21:11 PM PDT 24 |
| Finished | Jun 23 07:21:39 PM PDT 24 |
| Peak memory | 574096 kb |
| Host | smart-36cf55c8-995c-4a5b-b9c5-c6dfdb6dd978 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2566390026 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.xbar_random.2566390026 |
| Directory | /workspace/2.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/2.xbar_random_large_delays.2026666436 |
| Short name | T1908 |
| Test name | |
| Test status | |
| Simulation time | 105042594239 ps |
| CPU time | 1181.96 seconds |
| Started | Jun 23 07:21:09 PM PDT 24 |
| Finished | Jun 23 07:40:52 PM PDT 24 |
| Peak memory | 574164 kb |
| Host | smart-308c986e-b839-4b1d-8e73-8b0cfc8b4f17 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2026666436 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.xbar_random_large_delays.2026666436 |
| Directory | /workspace/2.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/2.xbar_random_slow_rsp.2330698823 |
| Short name | T2278 |
| Test name | |
| Test status | |
| Simulation time | 24666127309 ps |
| CPU time | 415.41 seconds |
| Started | Jun 23 07:21:11 PM PDT 24 |
| Finished | Jun 23 07:28:07 PM PDT 24 |
| Peak memory | 574160 kb |
| Host | smart-e4c154cc-ff2f-4dd2-9e39-8eeafc1b84c2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2330698823 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.xbar_random_slow_rsp.2330698823 |
| Directory | /workspace/2.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/2.xbar_random_zero_delays.3777530176 |
| Short name | T2040 |
| Test name | |
| Test status | |
| Simulation time | 581784844 ps |
| CPU time | 45.01 seconds |
| Started | Jun 23 07:21:10 PM PDT 24 |
| Finished | Jun 23 07:21:55 PM PDT 24 |
| Peak memory | 574080 kb |
| Host | smart-a348c4f7-a196-4121-a7af-85997e90c549 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3777530176 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.xbar_random_zero_dela ys.3777530176 |
| Directory | /workspace/2.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/2.xbar_same_source.3426387603 |
| Short name | T2491 |
| Test name | |
| Test status | |
| Simulation time | 1461942357 ps |
| CPU time | 41.73 seconds |
| Started | Jun 23 07:21:17 PM PDT 24 |
| Finished | Jun 23 07:21:59 PM PDT 24 |
| Peak memory | 574056 kb |
| Host | smart-68215363-c650-45d7-9726-fe56d140b3e0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3426387603 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.xbar_same_source.3426387603 |
| Directory | /workspace/2.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/2.xbar_smoke.2727175572 |
| Short name | T2651 |
| Test name | |
| Test status | |
| Simulation time | 160580342 ps |
| CPU time | 7.64 seconds |
| Started | Jun 23 07:21:10 PM PDT 24 |
| Finished | Jun 23 07:21:18 PM PDT 24 |
| Peak memory | 565100 kb |
| Host | smart-f1f8976f-e425-43b8-8668-8c7ab68596b5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2727175572 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.xbar_smoke.2727175572 |
| Directory | /workspace/2.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/2.xbar_smoke_large_delays.1497301049 |
| Short name | T1794 |
| Test name | |
| Test status | |
| Simulation time | 7474706284 ps |
| CPU time | 82.79 seconds |
| Started | Jun 23 07:21:07 PM PDT 24 |
| Finished | Jun 23 07:22:30 PM PDT 24 |
| Peak memory | 573456 kb |
| Host | smart-85209e12-4e29-4189-80af-ff2a10232ffe |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1497301049 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.xbar_smoke_large_delays.1497301049 |
| Directory | /workspace/2.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/2.xbar_smoke_slow_rsp.2814087546 |
| Short name | T1580 |
| Test name | |
| Test status | |
| Simulation time | 6603147869 ps |
| CPU time | 114.68 seconds |
| Started | Jun 23 07:21:09 PM PDT 24 |
| Finished | Jun 23 07:23:04 PM PDT 24 |
| Peak memory | 565500 kb |
| Host | smart-a2704f93-01f9-4a10-84b1-18b78c6b9f38 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2814087546 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.xbar_smoke_slow_rsp.2814087546 |
| Directory | /workspace/2.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/2.xbar_smoke_zero_delays.2147388607 |
| Short name | T2728 |
| Test name | |
| Test status | |
| Simulation time | 41296932 ps |
| CPU time | 6.04 seconds |
| Started | Jun 23 07:21:19 PM PDT 24 |
| Finished | Jun 23 07:21:26 PM PDT 24 |
| Peak memory | 565652 kb |
| Host | smart-8e995e21-b157-4edf-8177-1a9940c21cc4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2147388607 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.xbar_smoke_zero_delays .2147388607 |
| Directory | /workspace/2.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/2.xbar_stress_all.3972403226 |
| Short name | T2843 |
| Test name | |
| Test status | |
| Simulation time | 2930575769 ps |
| CPU time | 221.21 seconds |
| Started | Jun 23 07:21:17 PM PDT 24 |
| Finished | Jun 23 07:24:58 PM PDT 24 |
| Peak memory | 574284 kb |
| Host | smart-1f292329-041b-4591-a423-dead78dbdeaf |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3972403226 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.xbar_stress_all.3972403226 |
| Directory | /workspace/2.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/2.xbar_stress_all_with_error.3977030053 |
| Short name | T2043 |
| Test name | |
| Test status | |
| Simulation time | 7069192955 ps |
| CPU time | 259.97 seconds |
| Started | Jun 23 07:21:13 PM PDT 24 |
| Finished | Jun 23 07:25:33 PM PDT 24 |
| Peak memory | 574364 kb |
| Host | smart-6a74e46a-63c3-46e4-9556-2e69725748c2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3977030053 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.xbar_stress_all_with_error.3977030053 |
| Directory | /workspace/2.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/2.xbar_stress_all_with_reset_error.2389265817 |
| Short name | T2319 |
| Test name | |
| Test status | |
| Simulation time | 3405680957 ps |
| CPU time | 396.51 seconds |
| Started | Jun 23 07:21:19 PM PDT 24 |
| Finished | Jun 23 07:27:56 PM PDT 24 |
| Peak memory | 574368 kb |
| Host | smart-380d795a-a06b-46c7-9c47-d40e8127315b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2389265817 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.xbar_stress_all _with_reset_error.2389265817 |
| Directory | /workspace/2.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/2.xbar_unmapped_addr.2061905001 |
| Short name | T1408 |
| Test name | |
| Test status | |
| Simulation time | 74112385 ps |
| CPU time | 6.14 seconds |
| Started | Jun 23 07:21:16 PM PDT 24 |
| Finished | Jun 23 07:21:23 PM PDT 24 |
| Peak memory | 565168 kb |
| Host | smart-fb58d871-68ea-48f0-8570-1d76e579f1b5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2061905001 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.xbar_unmapped_addr.2061905001 |
| Directory | /workspace/2.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/20.chip_tl_errors.1152278361 |
| Short name | T2759 |
| Test name | |
| Test status | |
| Simulation time | 4258504090 ps |
| CPU time | 330.31 seconds |
| Started | Jun 23 07:26:24 PM PDT 24 |
| Finished | Jun 23 07:31:56 PM PDT 24 |
| Peak memory | 603516 kb |
| Host | smart-ce2f40ee-f374-406f-bb95-0c0750aabad0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1152278361 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.chip_tl_errors.1152278361 |
| Directory | /workspace/20.chip_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/20.xbar_access_same_device.140831239 |
| Short name | T1592 |
| Test name | |
| Test status | |
| Simulation time | 489549293 ps |
| CPU time | 41.47 seconds |
| Started | Jun 23 07:26:24 PM PDT 24 |
| Finished | Jun 23 07:27:06 PM PDT 24 |
| Peak memory | 574028 kb |
| Host | smart-e4cb34dc-2fa7-41c6-914c-52735c209b14 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=140831239 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.xbar_access_same_device. 140831239 |
| Directory | /workspace/20.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/20.xbar_error_and_unmapped_addr.1933976643 |
| Short name | T1435 |
| Test name | |
| Test status | |
| Simulation time | 716876996 ps |
| CPU time | 29.6 seconds |
| Started | Jun 23 07:26:33 PM PDT 24 |
| Finished | Jun 23 07:27:03 PM PDT 24 |
| Peak memory | 573684 kb |
| Host | smart-bbd89d15-ba98-464c-bf55-a70ae5195887 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1933976643 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.xbar_error_and_unmapped_add r.1933976643 |
| Directory | /workspace/20.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/20.xbar_error_random.545239479 |
| Short name | T1389 |
| Test name | |
| Test status | |
| Simulation time | 323064093 ps |
| CPU time | 14.12 seconds |
| Started | Jun 23 07:26:26 PM PDT 24 |
| Finished | Jun 23 07:26:41 PM PDT 24 |
| Peak memory | 573648 kb |
| Host | smart-d1430c2e-8708-4ac3-8663-d4206ea2def0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=545239479 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.xbar_error_random.545239479 |
| Directory | /workspace/20.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/20.xbar_random.610679938 |
| Short name | T1676 |
| Test name | |
| Test status | |
| Simulation time | 2321750258 ps |
| CPU time | 69.91 seconds |
| Started | Jun 23 07:26:22 PM PDT 24 |
| Finished | Jun 23 07:27:32 PM PDT 24 |
| Peak memory | 573352 kb |
| Host | smart-a95c5267-a0f2-4c23-9692-2aa225731b81 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=610679938 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.xbar_random.610679938 |
| Directory | /workspace/20.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/20.xbar_random_large_delays.399290980 |
| Short name | T616 |
| Test name | |
| Test status | |
| Simulation time | 83625064209 ps |
| CPU time | 813.54 seconds |
| Started | Jun 23 07:26:27 PM PDT 24 |
| Finished | Jun 23 07:40:01 PM PDT 24 |
| Peak memory | 574164 kb |
| Host | smart-c9ce011c-863b-40bd-8922-39d02928be4b |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=399290980 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.xbar_random_large_delays.399290980 |
| Directory | /workspace/20.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/20.xbar_random_slow_rsp.1952488170 |
| Short name | T2492 |
| Test name | |
| Test status | |
| Simulation time | 9161550625 ps |
| CPU time | 144.14 seconds |
| Started | Jun 23 07:26:27 PM PDT 24 |
| Finished | Jun 23 07:28:51 PM PDT 24 |
| Peak memory | 574192 kb |
| Host | smart-8ea51e5e-532e-4139-8f8e-7b38d163163e |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1952488170 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.xbar_random_slow_rsp.1952488170 |
| Directory | /workspace/20.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/20.xbar_random_zero_delays.1961953747 |
| Short name | T2401 |
| Test name | |
| Test status | |
| Simulation time | 325094209 ps |
| CPU time | 29.87 seconds |
| Started | Jun 23 07:26:23 PM PDT 24 |
| Finished | Jun 23 07:26:54 PM PDT 24 |
| Peak memory | 573440 kb |
| Host | smart-b09241a2-88f0-4634-ab75-d7e9217690a4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1961953747 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.xbar_random_zero_del ays.1961953747 |
| Directory | /workspace/20.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/20.xbar_same_source.3994461966 |
| Short name | T2390 |
| Test name | |
| Test status | |
| Simulation time | 404114412 ps |
| CPU time | 14.76 seconds |
| Started | Jun 23 07:26:31 PM PDT 24 |
| Finished | Jun 23 07:26:46 PM PDT 24 |
| Peak memory | 574032 kb |
| Host | smart-01a2fdcd-6cc8-4393-a377-c150c246ef90 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3994461966 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.xbar_same_source.3994461966 |
| Directory | /workspace/20.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/20.xbar_smoke.143585772 |
| Short name | T1662 |
| Test name | |
| Test status | |
| Simulation time | 209563225 ps |
| CPU time | 9.01 seconds |
| Started | Jun 23 07:26:23 PM PDT 24 |
| Finished | Jun 23 07:26:32 PM PDT 24 |
| Peak memory | 565420 kb |
| Host | smart-1f42f371-e1c4-4725-822e-bbec1193cac8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=143585772 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.xbar_smoke.143585772 |
| Directory | /workspace/20.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/20.xbar_smoke_large_delays.1905052144 |
| Short name | T2730 |
| Test name | |
| Test status | |
| Simulation time | 7377454413 ps |
| CPU time | 79.7 seconds |
| Started | Jun 23 07:26:24 PM PDT 24 |
| Finished | Jun 23 07:27:44 PM PDT 24 |
| Peak memory | 565532 kb |
| Host | smart-65ae6636-f81d-4dfa-94fc-4d197e5e6265 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1905052144 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.xbar_smoke_large_delays.1905052144 |
| Directory | /workspace/20.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/20.xbar_smoke_slow_rsp.3179316118 |
| Short name | T1626 |
| Test name | |
| Test status | |
| Simulation time | 4126639556 ps |
| CPU time | 73.54 seconds |
| Started | Jun 23 07:26:25 PM PDT 24 |
| Finished | Jun 23 07:27:39 PM PDT 24 |
| Peak memory | 565904 kb |
| Host | smart-bce8608a-1516-4841-bbab-c442ff9c4399 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3179316118 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.xbar_smoke_slow_rsp.3179316118 |
| Directory | /workspace/20.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/20.xbar_smoke_zero_delays.2180345776 |
| Short name | T2439 |
| Test name | |
| Test status | |
| Simulation time | 41261345 ps |
| CPU time | 6.07 seconds |
| Started | Jun 23 07:26:24 PM PDT 24 |
| Finished | Jun 23 07:26:31 PM PDT 24 |
| Peak memory | 565524 kb |
| Host | smart-2105f009-cff8-43fe-a48d-bf0a62c140ac |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2180345776 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.xbar_smoke_zero_delay s.2180345776 |
| Directory | /workspace/20.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/20.xbar_stress_all.850004196 |
| Short name | T492 |
| Test name | |
| Test status | |
| Simulation time | 10423675270 ps |
| CPU time | 386.04 seconds |
| Started | Jun 23 07:26:34 PM PDT 24 |
| Finished | Jun 23 07:33:01 PM PDT 24 |
| Peak memory | 574328 kb |
| Host | smart-a4a017a2-1bab-4261-9e5a-82e83a20c662 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=850004196 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.xbar_stress_all.850004196 |
| Directory | /workspace/20.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/20.xbar_stress_all_with_error.3597567956 |
| Short name | T2731 |
| Test name | |
| Test status | |
| Simulation time | 1755068476 ps |
| CPU time | 143.13 seconds |
| Started | Jun 23 07:26:34 PM PDT 24 |
| Finished | Jun 23 07:28:57 PM PDT 24 |
| Peak memory | 573488 kb |
| Host | smart-abbb5ec2-2282-4bfd-991b-d86bb30adb18 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3597567956 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.xbar_stress_all_with_error.3597567956 |
| Directory | /workspace/20.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/20.xbar_stress_all_with_rand_reset.4007414044 |
| Short name | T2234 |
| Test name | |
| Test status | |
| Simulation time | 345082418 ps |
| CPU time | 92.29 seconds |
| Started | Jun 23 07:26:33 PM PDT 24 |
| Finished | Jun 23 07:28:06 PM PDT 24 |
| Peak memory | 574252 kb |
| Host | smart-3e62fcfb-01c7-44d4-9fd8-eec12cb5c640 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4007414044 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.xbar_stress_all _with_rand_reset.4007414044 |
| Directory | /workspace/20.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/20.xbar_unmapped_addr.99120966 |
| Short name | T2816 |
| Test name | |
| Test status | |
| Simulation time | 261901211 ps |
| CPU time | 28.05 seconds |
| Started | Jun 23 07:26:29 PM PDT 24 |
| Finished | Jun 23 07:26:58 PM PDT 24 |
| Peak memory | 573480 kb |
| Host | smart-e8232571-02e7-4167-baf8-f22abe773d3d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99120966 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.xbar_unmapped_addr.99120966 |
| Directory | /workspace/20.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/21.xbar_access_same_device.1899670901 |
| Short name | T1579 |
| Test name | |
| Test status | |
| Simulation time | 661266095 ps |
| CPU time | 30.2 seconds |
| Started | Jun 23 07:26:39 PM PDT 24 |
| Finished | Jun 23 07:27:09 PM PDT 24 |
| Peak memory | 573408 kb |
| Host | smart-87fefedd-a28e-4586-aed6-1be322dd2085 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1899670901 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.xbar_access_same_device .1899670901 |
| Directory | /workspace/21.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/21.xbar_access_same_device_slow_rsp.2631080217 |
| Short name | T2213 |
| Test name | |
| Test status | |
| Simulation time | 73941371919 ps |
| CPU time | 1171.62 seconds |
| Started | Jun 23 07:26:39 PM PDT 24 |
| Finished | Jun 23 07:46:12 PM PDT 24 |
| Peak memory | 574240 kb |
| Host | smart-f10259f4-1b13-4423-868a-1ac37b438dfe |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2631080217 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.xbar_access_same_ device_slow_rsp.2631080217 |
| Directory | /workspace/21.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/21.xbar_error_and_unmapped_addr.1170938311 |
| Short name | T1701 |
| Test name | |
| Test status | |
| Simulation time | 907935797 ps |
| CPU time | 39.76 seconds |
| Started | Jun 23 07:26:48 PM PDT 24 |
| Finished | Jun 23 07:27:28 PM PDT 24 |
| Peak memory | 573400 kb |
| Host | smart-c2980bb6-6fd2-4bef-91a3-b6e0793f91e2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1170938311 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.xbar_error_and_unmapped_add r.1170938311 |
| Directory | /workspace/21.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/21.xbar_error_random.2682821055 |
| Short name | T1798 |
| Test name | |
| Test status | |
| Simulation time | 1335109671 ps |
| CPU time | 51.32 seconds |
| Started | Jun 23 07:26:49 PM PDT 24 |
| Finished | Jun 23 07:27:41 PM PDT 24 |
| Peak memory | 573744 kb |
| Host | smart-615cc0a7-113e-4416-a624-a46e52e16435 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2682821055 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.xbar_error_random.2682821055 |
| Directory | /workspace/21.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/21.xbar_random.3978761545 |
| Short name | T2403 |
| Test name | |
| Test status | |
| Simulation time | 1439237076 ps |
| CPU time | 53.24 seconds |
| Started | Jun 23 07:26:39 PM PDT 24 |
| Finished | Jun 23 07:27:32 PM PDT 24 |
| Peak memory | 574088 kb |
| Host | smart-43fb7847-8b51-4e4c-98b1-890656019583 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3978761545 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.xbar_random.3978761545 |
| Directory | /workspace/21.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/21.xbar_random_large_delays.3044918036 |
| Short name | T2080 |
| Test name | |
| Test status | |
| Simulation time | 85276476942 ps |
| CPU time | 861.16 seconds |
| Started | Jun 23 07:26:39 PM PDT 24 |
| Finished | Jun 23 07:41:00 PM PDT 24 |
| Peak memory | 573532 kb |
| Host | smart-66eeb329-deb8-4d8b-9599-f37b1183ebba |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3044918036 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.xbar_random_large_delays.3044918036 |
| Directory | /workspace/21.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/21.xbar_random_slow_rsp.3638146425 |
| Short name | T1877 |
| Test name | |
| Test status | |
| Simulation time | 33782923284 ps |
| CPU time | 576.3 seconds |
| Started | Jun 23 07:26:40 PM PDT 24 |
| Finished | Jun 23 07:36:16 PM PDT 24 |
| Peak memory | 573480 kb |
| Host | smart-487f46f8-3f0a-402d-9562-fac39bbbcc7a |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3638146425 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.xbar_random_slow_rsp.3638146425 |
| Directory | /workspace/21.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/21.xbar_random_zero_delays.3889769269 |
| Short name | T1882 |
| Test name | |
| Test status | |
| Simulation time | 62360213 ps |
| CPU time | 8.78 seconds |
| Started | Jun 23 07:26:37 PM PDT 24 |
| Finished | Jun 23 07:26:46 PM PDT 24 |
| Peak memory | 573728 kb |
| Host | smart-a948e9c8-11e7-4dda-98b0-07708e822754 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3889769269 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.xbar_random_zero_del ays.3889769269 |
| Directory | /workspace/21.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/21.xbar_same_source.3654497356 |
| Short name | T496 |
| Test name | |
| Test status | |
| Simulation time | 2089681744 ps |
| CPU time | 61.13 seconds |
| Started | Jun 23 07:26:38 PM PDT 24 |
| Finished | Jun 23 07:27:40 PM PDT 24 |
| Peak memory | 573432 kb |
| Host | smart-2ebcb565-8bc1-4903-9756-884c7098e45e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3654497356 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.xbar_same_source.3654497356 |
| Directory | /workspace/21.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/21.xbar_smoke.3548210472 |
| Short name | T2573 |
| Test name | |
| Test status | |
| Simulation time | 229756112 ps |
| CPU time | 8.64 seconds |
| Started | Jun 23 07:26:34 PM PDT 24 |
| Finished | Jun 23 07:26:43 PM PDT 24 |
| Peak memory | 565460 kb |
| Host | smart-3b9f0211-0c30-45ab-982c-2cc108596c57 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3548210472 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.xbar_smoke.3548210472 |
| Directory | /workspace/21.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/21.xbar_smoke_large_delays.4000609871 |
| Short name | T2529 |
| Test name | |
| Test status | |
| Simulation time | 8455432504 ps |
| CPU time | 90.96 seconds |
| Started | Jun 23 07:26:35 PM PDT 24 |
| Finished | Jun 23 07:28:06 PM PDT 24 |
| Peak memory | 565916 kb |
| Host | smart-c99ffbdb-07f0-4d3a-bbe9-91b98e18446c |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4000609871 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.xbar_smoke_large_delays.4000609871 |
| Directory | /workspace/21.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/21.xbar_smoke_slow_rsp.2804797566 |
| Short name | T2470 |
| Test name | |
| Test status | |
| Simulation time | 4828463381 ps |
| CPU time | 82.2 seconds |
| Started | Jun 23 07:26:44 PM PDT 24 |
| Finished | Jun 23 07:28:06 PM PDT 24 |
| Peak memory | 565964 kb |
| Host | smart-9efb6642-e6fb-4486-8ccf-91fbe69aba62 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2804797566 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.xbar_smoke_slow_rsp.2804797566 |
| Directory | /workspace/21.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/21.xbar_smoke_zero_delays.985093421 |
| Short name | T2875 |
| Test name | |
| Test status | |
| Simulation time | 45900670 ps |
| CPU time | 5.58 seconds |
| Started | Jun 23 07:26:31 PM PDT 24 |
| Finished | Jun 23 07:26:37 PM PDT 24 |
| Peak memory | 565384 kb |
| Host | smart-ff80bb3d-62ef-4c5a-af32-141d2a3c18b2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=985093421 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.xbar_smoke_zero_delays .985093421 |
| Directory | /workspace/21.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/21.xbar_stress_all.556315413 |
| Short name | T434 |
| Test name | |
| Test status | |
| Simulation time | 4317523288 ps |
| CPU time | 356.37 seconds |
| Started | Jun 23 07:26:49 PM PDT 24 |
| Finished | Jun 23 07:32:46 PM PDT 24 |
| Peak memory | 574300 kb |
| Host | smart-4177a1bb-abec-4e1f-9255-ba1d2bd3b228 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=556315413 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.xbar_stress_all.556315413 |
| Directory | /workspace/21.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/21.xbar_stress_all_with_error.2136575270 |
| Short name | T1838 |
| Test name | |
| Test status | |
| Simulation time | 2227044412 ps |
| CPU time | 78.34 seconds |
| Started | Jun 23 07:26:48 PM PDT 24 |
| Finished | Jun 23 07:28:07 PM PDT 24 |
| Peak memory | 574232 kb |
| Host | smart-71402852-aec1-4a50-9de3-d9bf1d54669e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2136575270 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.xbar_stress_all_with_error.2136575270 |
| Directory | /workspace/21.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/21.xbar_stress_all_with_rand_reset.38995989 |
| Short name | T1943 |
| Test name | |
| Test status | |
| Simulation time | 664846843 ps |
| CPU time | 276.85 seconds |
| Started | Jun 23 07:26:50 PM PDT 24 |
| Finished | Jun 23 07:31:27 PM PDT 24 |
| Peak memory | 576272 kb |
| Host | smart-e32e431d-c0c2-40ef-8477-e44e6d0e10f2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38995989 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_rese t_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.xbar_stress_all_w ith_rand_reset.38995989 |
| Directory | /workspace/21.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/21.xbar_stress_all_with_reset_error.3922865031 |
| Short name | T2562 |
| Test name | |
| Test status | |
| Simulation time | 18227554002 ps |
| CPU time | 795.87 seconds |
| Started | Jun 23 07:26:49 PM PDT 24 |
| Finished | Jun 23 07:40:05 PM PDT 24 |
| Peak memory | 577416 kb |
| Host | smart-a48fe51c-6296-44a2-864f-8bc79b6f288e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3922865031 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.xbar_stress_al l_with_reset_error.3922865031 |
| Directory | /workspace/21.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/21.xbar_unmapped_addr.619096356 |
| Short name | T2598 |
| Test name | |
| Test status | |
| Simulation time | 282678751 ps |
| CPU time | 35.58 seconds |
| Started | Jun 23 07:26:49 PM PDT 24 |
| Finished | Jun 23 07:27:25 PM PDT 24 |
| Peak memory | 574144 kb |
| Host | smart-7b1e0955-5676-4770-9127-5cc877535b33 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=619096356 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.xbar_unmapped_addr.619096356 |
| Directory | /workspace/21.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/22.xbar_access_same_device.4293646982 |
| Short name | T2399 |
| Test name | |
| Test status | |
| Simulation time | 2731622432 ps |
| CPU time | 126.97 seconds |
| Started | Jun 23 07:26:53 PM PDT 24 |
| Finished | Jun 23 07:29:00 PM PDT 24 |
| Peak memory | 573464 kb |
| Host | smart-1efa4cff-4b69-4cf3-8025-554342f2cedd |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4293646982 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.xbar_access_same_device .4293646982 |
| Directory | /workspace/22.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/22.xbar_error_and_unmapped_addr.1164433465 |
| Short name | T2172 |
| Test name | |
| Test status | |
| Simulation time | 1113057662 ps |
| CPU time | 47.82 seconds |
| Started | Jun 23 07:27:02 PM PDT 24 |
| Finished | Jun 23 07:27:50 PM PDT 24 |
| Peak memory | 573356 kb |
| Host | smart-4bf894a7-2436-423a-b718-968d428977bc |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1164433465 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.xbar_error_and_unmapped_add r.1164433465 |
| Directory | /workspace/22.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/22.xbar_error_random.3614890981 |
| Short name | T510 |
| Test name | |
| Test status | |
| Simulation time | 961246676 ps |
| CPU time | 38.66 seconds |
| Started | Jun 23 07:26:57 PM PDT 24 |
| Finished | Jun 23 07:27:36 PM PDT 24 |
| Peak memory | 573712 kb |
| Host | smart-4b0adb8e-5c77-45c2-aed8-5f8acc7b5b69 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3614890981 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.xbar_error_random.3614890981 |
| Directory | /workspace/22.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/22.xbar_random.332466980 |
| Short name | T603 |
| Test name | |
| Test status | |
| Simulation time | 390057860 ps |
| CPU time | 18.59 seconds |
| Started | Jun 23 07:26:53 PM PDT 24 |
| Finished | Jun 23 07:27:12 PM PDT 24 |
| Peak memory | 574052 kb |
| Host | smart-cd2eaa33-02f2-4753-be93-30968e7915d6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=332466980 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.xbar_random.332466980 |
| Directory | /workspace/22.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/22.xbar_random_large_delays.4176448193 |
| Short name | T640 |
| Test name | |
| Test status | |
| Simulation time | 57098043394 ps |
| CPU time | 661.35 seconds |
| Started | Jun 23 07:26:53 PM PDT 24 |
| Finished | Jun 23 07:37:54 PM PDT 24 |
| Peak memory | 574204 kb |
| Host | smart-f2b43de1-24d8-4839-b2e8-2fb8af07fc2b |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4176448193 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.xbar_random_large_delays.4176448193 |
| Directory | /workspace/22.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/22.xbar_random_slow_rsp.2326774869 |
| Short name | T2591 |
| Test name | |
| Test status | |
| Simulation time | 17845574430 ps |
| CPU time | 309.6 seconds |
| Started | Jun 23 07:26:55 PM PDT 24 |
| Finished | Jun 23 07:32:05 PM PDT 24 |
| Peak memory | 574160 kb |
| Host | smart-8fa4725a-bfa7-4650-b09b-62180a4192d6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2326774869 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.xbar_random_slow_rsp.2326774869 |
| Directory | /workspace/22.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/22.xbar_random_zero_delays.4082310342 |
| Short name | T1944 |
| Test name | |
| Test status | |
| Simulation time | 396542238 ps |
| CPU time | 30.6 seconds |
| Started | Jun 23 07:26:53 PM PDT 24 |
| Finished | Jun 23 07:27:24 PM PDT 24 |
| Peak memory | 573952 kb |
| Host | smart-00de74a5-350f-4c08-a82a-63e1e0153f03 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4082310342 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.xbar_random_zero_del ays.4082310342 |
| Directory | /workspace/22.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/22.xbar_same_source.643984388 |
| Short name | T2100 |
| Test name | |
| Test status | |
| Simulation time | 1652553194 ps |
| CPU time | 53.87 seconds |
| Started | Jun 23 07:26:51 PM PDT 24 |
| Finished | Jun 23 07:27:45 PM PDT 24 |
| Peak memory | 574028 kb |
| Host | smart-ebb64ae3-8c59-48a2-8b59-9ff89175f7aa |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=643984388 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.xbar_same_source.643984388 |
| Directory | /workspace/22.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/22.xbar_smoke.3208359886 |
| Short name | T1547 |
| Test name | |
| Test status | |
| Simulation time | 50834331 ps |
| CPU time | 6.6 seconds |
| Started | Jun 23 07:26:54 PM PDT 24 |
| Finished | Jun 23 07:27:01 PM PDT 24 |
| Peak memory | 565864 kb |
| Host | smart-045ac111-142b-419d-8741-93a89020faa7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3208359886 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.xbar_smoke.3208359886 |
| Directory | /workspace/22.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/22.xbar_smoke_large_delays.1682728531 |
| Short name | T644 |
| Test name | |
| Test status | |
| Simulation time | 7624229833 ps |
| CPU time | 77.31 seconds |
| Started | Jun 23 07:26:52 PM PDT 24 |
| Finished | Jun 23 07:28:09 PM PDT 24 |
| Peak memory | 565908 kb |
| Host | smart-117e2143-3e22-4ddc-88f5-1cf6ac6d35a7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1682728531 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.xbar_smoke_large_delays.1682728531 |
| Directory | /workspace/22.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/22.xbar_smoke_slow_rsp.2709984272 |
| Short name | T1637 |
| Test name | |
| Test status | |
| Simulation time | 5799988388 ps |
| CPU time | 95.66 seconds |
| Started | Jun 23 07:26:58 PM PDT 24 |
| Finished | Jun 23 07:28:34 PM PDT 24 |
| Peak memory | 565576 kb |
| Host | smart-6361285f-50df-4879-94c6-0ca11fd1c4b3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2709984272 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.xbar_smoke_slow_rsp.2709984272 |
| Directory | /workspace/22.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/22.xbar_smoke_zero_delays.1945911396 |
| Short name | T1379 |
| Test name | |
| Test status | |
| Simulation time | 54676451 ps |
| CPU time | 6.65 seconds |
| Started | Jun 23 07:26:54 PM PDT 24 |
| Finished | Jun 23 07:27:01 PM PDT 24 |
| Peak memory | 573336 kb |
| Host | smart-7988b2e5-a2d5-4d7c-8092-57f3ae6823c4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1945911396 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.xbar_smoke_zero_delay s.1945911396 |
| Directory | /workspace/22.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/22.xbar_stress_all.2664039046 |
| Short name | T528 |
| Test name | |
| Test status | |
| Simulation time | 2295460049 ps |
| CPU time | 183.84 seconds |
| Started | Jun 23 07:26:57 PM PDT 24 |
| Finished | Jun 23 07:30:02 PM PDT 24 |
| Peak memory | 574272 kb |
| Host | smart-b7f3b207-cd31-45c7-8ac2-903ea76a4545 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2664039046 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.xbar_stress_all.2664039046 |
| Directory | /workspace/22.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/22.xbar_stress_all_with_error.1401153906 |
| Short name | T2233 |
| Test name | |
| Test status | |
| Simulation time | 3099242873 ps |
| CPU time | 238.32 seconds |
| Started | Jun 23 07:27:02 PM PDT 24 |
| Finished | Jun 23 07:31:00 PM PDT 24 |
| Peak memory | 574364 kb |
| Host | smart-bb57095f-6904-49e5-896b-50de1bb471dd |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1401153906 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.xbar_stress_all_with_error.1401153906 |
| Directory | /workspace/22.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/22.xbar_stress_all_with_rand_reset.4293435974 |
| Short name | T2212 |
| Test name | |
| Test status | |
| Simulation time | 122967037 ps |
| CPU time | 47.32 seconds |
| Started | Jun 23 07:27:01 PM PDT 24 |
| Finished | Jun 23 07:27:49 PM PDT 24 |
| Peak memory | 574264 kb |
| Host | smart-e068e36c-8638-4fbc-bc76-a1706796bb1f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4293435974 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.xbar_stress_all _with_rand_reset.4293435974 |
| Directory | /workspace/22.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/22.xbar_stress_all_with_reset_error.4051994570 |
| Short name | T2456 |
| Test name | |
| Test status | |
| Simulation time | 3622098666 ps |
| CPU time | 408.34 seconds |
| Started | Jun 23 07:26:57 PM PDT 24 |
| Finished | Jun 23 07:33:46 PM PDT 24 |
| Peak memory | 575352 kb |
| Host | smart-e042cb31-9f5b-40c0-82ac-3723ddd7af20 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4051994570 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.xbar_stress_al l_with_reset_error.4051994570 |
| Directory | /workspace/22.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/22.xbar_unmapped_addr.3020313683 |
| Short name | T1423 |
| Test name | |
| Test status | |
| Simulation time | 138689317 ps |
| CPU time | 9 seconds |
| Started | Jun 23 07:27:01 PM PDT 24 |
| Finished | Jun 23 07:27:11 PM PDT 24 |
| Peak memory | 565920 kb |
| Host | smart-7a866b4d-1b5e-4d1c-b857-93202f6b3f53 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3020313683 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.xbar_unmapped_addr.3020313683 |
| Directory | /workspace/22.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/23.chip_tl_errors.1470476537 |
| Short name | T2693 |
| Test name | |
| Test status | |
| Simulation time | 3389267496 ps |
| CPU time | 232.61 seconds |
| Started | Jun 23 07:27:25 PM PDT 24 |
| Finished | Jun 23 07:31:18 PM PDT 24 |
| Peak memory | 597424 kb |
| Host | smart-d6260ef0-4208-4fb2-936f-9e80322a9607 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1470476537 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.chip_tl_errors.1470476537 |
| Directory | /workspace/23.chip_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/23.xbar_access_same_device.3009001559 |
| Short name | T2471 |
| Test name | |
| Test status | |
| Simulation time | 1941403437 ps |
| CPU time | 73.53 seconds |
| Started | Jun 23 07:27:30 PM PDT 24 |
| Finished | Jun 23 07:28:44 PM PDT 24 |
| Peak memory | 574128 kb |
| Host | smart-a9be4da0-4d71-481f-9798-5412b7ea1d99 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3009001559 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.xbar_access_same_device .3009001559 |
| Directory | /workspace/23.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/23.xbar_access_same_device_slow_rsp.2846544041 |
| Short name | T1921 |
| Test name | |
| Test status | |
| Simulation time | 109033342163 ps |
| CPU time | 1965.36 seconds |
| Started | Jun 23 07:27:32 PM PDT 24 |
| Finished | Jun 23 08:00:18 PM PDT 24 |
| Peak memory | 574236 kb |
| Host | smart-9b8c6738-c7a8-4b13-8c3e-c759c40c6fb7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2846544041 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.xbar_access_same_ device_slow_rsp.2846544041 |
| Directory | /workspace/23.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/23.xbar_error_and_unmapped_addr.3983389435 |
| Short name | T2377 |
| Test name | |
| Test status | |
| Simulation time | 346418166 ps |
| CPU time | 17.43 seconds |
| Started | Jun 23 07:27:30 PM PDT 24 |
| Finished | Jun 23 07:27:48 PM PDT 24 |
| Peak memory | 573660 kb |
| Host | smart-7f4ee3e7-e530-4c5e-b075-bbc5229df8a9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3983389435 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.xbar_error_and_unmapped_add r.3983389435 |
| Directory | /workspace/23.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/23.xbar_error_random.1145369476 |
| Short name | T2823 |
| Test name | |
| Test status | |
| Simulation time | 303194661 ps |
| CPU time | 22.48 seconds |
| Started | Jun 23 07:27:34 PM PDT 24 |
| Finished | Jun 23 07:27:57 PM PDT 24 |
| Peak memory | 573720 kb |
| Host | smart-0321c14e-c320-423e-866f-42c919b80f16 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1145369476 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.xbar_error_random.1145369476 |
| Directory | /workspace/23.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/23.xbar_random.2498762604 |
| Short name | T2575 |
| Test name | |
| Test status | |
| Simulation time | 2004387261 ps |
| CPU time | 62.53 seconds |
| Started | Jun 23 07:27:26 PM PDT 24 |
| Finished | Jun 23 07:28:28 PM PDT 24 |
| Peak memory | 574068 kb |
| Host | smart-ae7c5837-e99c-4596-8723-79bd3dbf871c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2498762604 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.xbar_random.2498762604 |
| Directory | /workspace/23.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/23.xbar_random_large_delays.481745618 |
| Short name | T1940 |
| Test name | |
| Test status | |
| Simulation time | 82709796129 ps |
| CPU time | 826.11 seconds |
| Started | Jun 23 07:27:26 PM PDT 24 |
| Finished | Jun 23 07:41:13 PM PDT 24 |
| Peak memory | 574076 kb |
| Host | smart-6f19fcdc-f1a7-4d98-8407-2e0822860a44 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=481745618 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.xbar_random_large_delays.481745618 |
| Directory | /workspace/23.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/23.xbar_random_slow_rsp.1622347375 |
| Short name | T2333 |
| Test name | |
| Test status | |
| Simulation time | 31847163457 ps |
| CPU time | 525.4 seconds |
| Started | Jun 23 07:27:31 PM PDT 24 |
| Finished | Jun 23 07:36:17 PM PDT 24 |
| Peak memory | 573476 kb |
| Host | smart-491aab8c-be6c-4028-b449-88a7ad164702 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1622347375 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.xbar_random_slow_rsp.1622347375 |
| Directory | /workspace/23.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/23.xbar_random_zero_delays.3816021724 |
| Short name | T666 |
| Test name | |
| Test status | |
| Simulation time | 573574493 ps |
| CPU time | 47.44 seconds |
| Started | Jun 23 07:27:25 PM PDT 24 |
| Finished | Jun 23 07:28:13 PM PDT 24 |
| Peak memory | 573456 kb |
| Host | smart-c1e31a19-ccb8-4666-a1c3-84042a58e731 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3816021724 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.xbar_random_zero_del ays.3816021724 |
| Directory | /workspace/23.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/23.xbar_same_source.354935880 |
| Short name | T2263 |
| Test name | |
| Test status | |
| Simulation time | 1934691609 ps |
| CPU time | 53.43 seconds |
| Started | Jun 23 07:27:35 PM PDT 24 |
| Finished | Jun 23 07:28:29 PM PDT 24 |
| Peak memory | 573376 kb |
| Host | smart-3cc9697c-bcbb-4595-9c18-59723c5218ea |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=354935880 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.xbar_same_source.354935880 |
| Directory | /workspace/23.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/23.xbar_smoke.3871240707 |
| Short name | T2013 |
| Test name | |
| Test status | |
| Simulation time | 38031936 ps |
| CPU time | 6.42 seconds |
| Started | Jun 23 07:27:27 PM PDT 24 |
| Finished | Jun 23 07:27:34 PM PDT 24 |
| Peak memory | 565764 kb |
| Host | smart-a82cb1d2-50da-4a2b-8a64-b91df9f412e5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3871240707 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.xbar_smoke.3871240707 |
| Directory | /workspace/23.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/23.xbar_smoke_large_delays.982707024 |
| Short name | T2478 |
| Test name | |
| Test status | |
| Simulation time | 7770609974 ps |
| CPU time | 78.55 seconds |
| Started | Jun 23 07:27:25 PM PDT 24 |
| Finished | Jun 23 07:28:44 PM PDT 24 |
| Peak memory | 565876 kb |
| Host | smart-68b768c2-ddfb-43e2-8191-e0df58cd6f96 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=982707024 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.xbar_smoke_large_delays.982707024 |
| Directory | /workspace/23.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/23.xbar_smoke_slow_rsp.4028176133 |
| Short name | T2256 |
| Test name | |
| Test status | |
| Simulation time | 5065178911 ps |
| CPU time | 83.26 seconds |
| Started | Jun 23 07:27:26 PM PDT 24 |
| Finished | Jun 23 07:28:49 PM PDT 24 |
| Peak memory | 565252 kb |
| Host | smart-c15737db-8979-48ef-a9ea-6927dc028c1b |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4028176133 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.xbar_smoke_slow_rsp.4028176133 |
| Directory | /workspace/23.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/23.xbar_smoke_zero_delays.4231139305 |
| Short name | T1694 |
| Test name | |
| Test status | |
| Simulation time | 51818039 ps |
| CPU time | 6.34 seconds |
| Started | Jun 23 07:27:26 PM PDT 24 |
| Finished | Jun 23 07:27:33 PM PDT 24 |
| Peak memory | 565620 kb |
| Host | smart-a83912c1-1eec-4e22-8e3b-b7581e56510d |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4231139305 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.xbar_smoke_zero_delay s.4231139305 |
| Directory | /workspace/23.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/23.xbar_stress_all.2368037804 |
| Short name | T549 |
| Test name | |
| Test status | |
| Simulation time | 2341937705 ps |
| CPU time | 87.38 seconds |
| Started | Jun 23 07:27:34 PM PDT 24 |
| Finished | Jun 23 07:29:02 PM PDT 24 |
| Peak memory | 574292 kb |
| Host | smart-9b235bcc-38a5-44b9-b4b5-5a989b202fc6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2368037804 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.xbar_stress_all.2368037804 |
| Directory | /workspace/23.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/23.xbar_stress_all_with_error.3180833992 |
| Short name | T2778 |
| Test name | |
| Test status | |
| Simulation time | 1574842714 ps |
| CPU time | 120.98 seconds |
| Started | Jun 23 07:27:34 PM PDT 24 |
| Finished | Jun 23 07:29:36 PM PDT 24 |
| Peak memory | 573724 kb |
| Host | smart-e4dd5ce5-c3e3-421e-8bd5-733cde3f957a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3180833992 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.xbar_stress_all_with_error.3180833992 |
| Directory | /workspace/23.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/23.xbar_stress_all_with_rand_reset.2533829772 |
| Short name | T2853 |
| Test name | |
| Test status | |
| Simulation time | 1989249379 ps |
| CPU time | 360.34 seconds |
| Started | Jun 23 07:27:31 PM PDT 24 |
| Finished | Jun 23 07:33:32 PM PDT 24 |
| Peak memory | 574220 kb |
| Host | smart-91bd8342-6bbb-4d17-a3c7-4f694f367ff3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2533829772 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.xbar_stress_all _with_rand_reset.2533829772 |
| Directory | /workspace/23.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/23.xbar_stress_all_with_reset_error.4251380827 |
| Short name | T2719 |
| Test name | |
| Test status | |
| Simulation time | 95179231 ps |
| CPU time | 12.94 seconds |
| Started | Jun 23 07:27:34 PM PDT 24 |
| Finished | Jun 23 07:27:47 PM PDT 24 |
| Peak memory | 574188 kb |
| Host | smart-3076d5ed-d675-49a0-b697-4f9b2f8e73e9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4251380827 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.xbar_stress_al l_with_reset_error.4251380827 |
| Directory | /workspace/23.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/23.xbar_unmapped_addr.131487711 |
| Short name | T1659 |
| Test name | |
| Test status | |
| Simulation time | 536996252 ps |
| CPU time | 24 seconds |
| Started | Jun 23 07:27:32 PM PDT 24 |
| Finished | Jun 23 07:27:57 PM PDT 24 |
| Peak memory | 574048 kb |
| Host | smart-6f034609-1ed2-4712-a4cd-f10d95c50ea6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=131487711 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.xbar_unmapped_addr.131487711 |
| Directory | /workspace/23.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/24.chip_tl_errors.1972043111 |
| Short name | T540 |
| Test name | |
| Test status | |
| Simulation time | 3794008979 ps |
| CPU time | 223.81 seconds |
| Started | Jun 23 07:27:33 PM PDT 24 |
| Finished | Jun 23 07:31:17 PM PDT 24 |
| Peak memory | 597428 kb |
| Host | smart-065ccb6a-911e-4bf1-8e58-83182953eb51 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1972043111 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.chip_tl_errors.1972043111 |
| Directory | /workspace/24.chip_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/24.xbar_access_same_device.1954204496 |
| Short name | T2795 |
| Test name | |
| Test status | |
| Simulation time | 565146058 ps |
| CPU time | 37.88 seconds |
| Started | Jun 23 07:27:32 PM PDT 24 |
| Finished | Jun 23 07:28:11 PM PDT 24 |
| Peak memory | 574112 kb |
| Host | smart-26b7ed73-43fe-4485-b7a1-47925e55c8cf |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1954204496 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.xbar_access_same_device .1954204496 |
| Directory | /workspace/24.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/24.xbar_access_same_device_slow_rsp.3622982133 |
| Short name | T2277 |
| Test name | |
| Test status | |
| Simulation time | 28990708989 ps |
| CPU time | 522.31 seconds |
| Started | Jun 23 07:27:34 PM PDT 24 |
| Finished | Jun 23 07:36:17 PM PDT 24 |
| Peak memory | 573576 kb |
| Host | smart-0dcfcc9e-baf9-4c6d-9762-62e8ece7737f |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3622982133 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.xbar_access_same_ device_slow_rsp.3622982133 |
| Directory | /workspace/24.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/24.xbar_error_and_unmapped_addr.1127937161 |
| Short name | T1449 |
| Test name | |
| Test status | |
| Simulation time | 298164967 ps |
| CPU time | 13.6 seconds |
| Started | Jun 23 07:27:33 PM PDT 24 |
| Finished | Jun 23 07:27:47 PM PDT 24 |
| Peak memory | 573352 kb |
| Host | smart-d0c8649a-d5ca-4eb0-a7d9-12a8cb46f855 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1127937161 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.xbar_error_and_unmapped_add r.1127937161 |
| Directory | /workspace/24.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/24.xbar_error_random.1794314233 |
| Short name | T1445 |
| Test name | |
| Test status | |
| Simulation time | 1696478365 ps |
| CPU time | 63.95 seconds |
| Started | Jun 23 07:27:30 PM PDT 24 |
| Finished | Jun 23 07:28:34 PM PDT 24 |
| Peak memory | 573292 kb |
| Host | smart-64f8043a-0365-4e88-aa82-9dc87cad7fe5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1794314233 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.xbar_error_random.1794314233 |
| Directory | /workspace/24.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/24.xbar_random.3578881112 |
| Short name | T1888 |
| Test name | |
| Test status | |
| Simulation time | 2434736508 ps |
| CPU time | 85.2 seconds |
| Started | Jun 23 07:27:30 PM PDT 24 |
| Finished | Jun 23 07:28:56 PM PDT 24 |
| Peak memory | 573516 kb |
| Host | smart-f6efdcdd-862f-4361-8f35-e92dc3921002 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3578881112 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.xbar_random.3578881112 |
| Directory | /workspace/24.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/24.xbar_random_large_delays.2082650224 |
| Short name | T2881 |
| Test name | |
| Test status | |
| Simulation time | 26404030059 ps |
| CPU time | 269.33 seconds |
| Started | Jun 23 07:27:31 PM PDT 24 |
| Finished | Jun 23 07:32:01 PM PDT 24 |
| Peak memory | 574232 kb |
| Host | smart-186b5264-0bd1-4285-9d58-1c746133847e |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2082650224 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.xbar_random_large_delays.2082650224 |
| Directory | /workspace/24.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/24.xbar_random_slow_rsp.12497688 |
| Short name | T2388 |
| Test name | |
| Test status | |
| Simulation time | 51183063948 ps |
| CPU time | 894.79 seconds |
| Started | Jun 23 07:27:34 PM PDT 24 |
| Finished | Jun 23 07:42:30 PM PDT 24 |
| Peak memory | 574160 kb |
| Host | smart-2abff52c-9f46-4d22-afd6-f03d16e8c9dc |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12497688 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.xbar_random_slow_rsp.12497688 |
| Directory | /workspace/24.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/24.xbar_random_zero_delays.2278648767 |
| Short name | T1525 |
| Test name | |
| Test status | |
| Simulation time | 35924183 ps |
| CPU time | 6.24 seconds |
| Started | Jun 23 07:27:33 PM PDT 24 |
| Finished | Jun 23 07:27:39 PM PDT 24 |
| Peak memory | 565384 kb |
| Host | smart-d0183737-c062-46f1-ab64-c9be5554ba46 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2278648767 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.xbar_random_zero_del ays.2278648767 |
| Directory | /workspace/24.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/24.xbar_same_source.1094056133 |
| Short name | T1671 |
| Test name | |
| Test status | |
| Simulation time | 94552871 ps |
| CPU time | 9.29 seconds |
| Started | Jun 23 07:27:31 PM PDT 24 |
| Finished | Jun 23 07:27:41 PM PDT 24 |
| Peak memory | 573404 kb |
| Host | smart-393ec35d-956e-4cdc-a238-4f03f0d8e540 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1094056133 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.xbar_same_source.1094056133 |
| Directory | /workspace/24.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/24.xbar_smoke.2261460612 |
| Short name | T2541 |
| Test name | |
| Test status | |
| Simulation time | 253097379 ps |
| CPU time | 9.77 seconds |
| Started | Jun 23 07:27:34 PM PDT 24 |
| Finished | Jun 23 07:27:45 PM PDT 24 |
| Peak memory | 565140 kb |
| Host | smart-373d51c5-5d22-4947-aaec-c2ca39c410a4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2261460612 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.xbar_smoke.2261460612 |
| Directory | /workspace/24.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/24.xbar_smoke_large_delays.3773838580 |
| Short name | T563 |
| Test name | |
| Test status | |
| Simulation time | 6602324097 ps |
| CPU time | 69.7 seconds |
| Started | Jun 23 07:27:31 PM PDT 24 |
| Finished | Jun 23 07:28:41 PM PDT 24 |
| Peak memory | 565244 kb |
| Host | smart-ccd4e820-fbf8-44c3-9fba-5837ca815269 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3773838580 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.xbar_smoke_large_delays.3773838580 |
| Directory | /workspace/24.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/24.xbar_smoke_slow_rsp.1383825175 |
| Short name | T458 |
| Test name | |
| Test status | |
| Simulation time | 5981422023 ps |
| CPU time | 101.41 seconds |
| Started | Jun 23 07:27:34 PM PDT 24 |
| Finished | Jun 23 07:29:16 PM PDT 24 |
| Peak memory | 565936 kb |
| Host | smart-70185d96-8b4b-4f0c-868b-106c6424a0b6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1383825175 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.xbar_smoke_slow_rsp.1383825175 |
| Directory | /workspace/24.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/24.xbar_smoke_zero_delays.897767980 |
| Short name | T2204 |
| Test name | |
| Test status | |
| Simulation time | 56072978 ps |
| CPU time | 6.64 seconds |
| Started | Jun 23 07:27:33 PM PDT 24 |
| Finished | Jun 23 07:27:41 PM PDT 24 |
| Peak memory | 565164 kb |
| Host | smart-3007bf94-bc58-455f-bdad-39a445452508 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=897767980 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.xbar_smoke_zero_delays .897767980 |
| Directory | /workspace/24.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/24.xbar_stress_all.170532745 |
| Short name | T2802 |
| Test name | |
| Test status | |
| Simulation time | 15187379045 ps |
| CPU time | 627.72 seconds |
| Started | Jun 23 07:27:32 PM PDT 24 |
| Finished | Jun 23 07:38:01 PM PDT 24 |
| Peak memory | 574308 kb |
| Host | smart-4d845bb5-ad3a-413c-b960-b890eacb8703 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=170532745 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.xbar_stress_all.170532745 |
| Directory | /workspace/24.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/24.xbar_stress_all_with_error.2123753086 |
| Short name | T2324 |
| Test name | |
| Test status | |
| Simulation time | 2795005969 ps |
| CPU time | 195.58 seconds |
| Started | Jun 23 07:27:34 PM PDT 24 |
| Finished | Jun 23 07:30:51 PM PDT 24 |
| Peak memory | 574372 kb |
| Host | smart-aeee95c8-949c-4ec2-8613-6529db5ea840 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2123753086 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.xbar_stress_all_with_error.2123753086 |
| Directory | /workspace/24.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/24.xbar_stress_all_with_reset_error.2126704752 |
| Short name | T1825 |
| Test name | |
| Test status | |
| Simulation time | 15922172 ps |
| CPU time | 18.56 seconds |
| Started | Jun 23 07:27:35 PM PDT 24 |
| Finished | Jun 23 07:27:54 PM PDT 24 |
| Peak memory | 565916 kb |
| Host | smart-1c4007ef-6464-4a26-afe8-dfb6c2b19123 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2126704752 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.xbar_stress_al l_with_reset_error.2126704752 |
| Directory | /workspace/24.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/24.xbar_unmapped_addr.1518759207 |
| Short name | T2467 |
| Test name | |
| Test status | |
| Simulation time | 1057135541 ps |
| CPU time | 43.31 seconds |
| Started | Jun 23 07:27:33 PM PDT 24 |
| Finished | Jun 23 07:28:17 PM PDT 24 |
| Peak memory | 574140 kb |
| Host | smart-8958f63e-8396-4e77-8231-68518b1291bf |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1518759207 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.xbar_unmapped_addr.1518759207 |
| Directory | /workspace/24.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/25.chip_tl_errors.4078413530 |
| Short name | T698 |
| Test name | |
| Test status | |
| Simulation time | 3153285978 ps |
| CPU time | 182.5 seconds |
| Started | Jun 23 07:27:35 PM PDT 24 |
| Finished | Jun 23 07:30:38 PM PDT 24 |
| Peak memory | 602608 kb |
| Host | smart-f3e8ecd7-1ae1-454b-bbec-6f1e4e271332 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4078413530 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.chip_tl_errors.4078413530 |
| Directory | /workspace/25.chip_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/25.xbar_access_same_device.365922224 |
| Short name | T2203 |
| Test name | |
| Test status | |
| Simulation time | 3517742131 ps |
| CPU time | 141.14 seconds |
| Started | Jun 23 07:27:38 PM PDT 24 |
| Finished | Jun 23 07:30:00 PM PDT 24 |
| Peak memory | 574196 kb |
| Host | smart-1c00d756-04da-42e7-ab9d-675ac667befd |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=365922224 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.xbar_access_same_device. 365922224 |
| Directory | /workspace/25.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/25.xbar_access_same_device_slow_rsp.98933557 |
| Short name | T2878 |
| Test name | |
| Test status | |
| Simulation time | 20726385593 ps |
| CPU time | 369.77 seconds |
| Started | Jun 23 07:27:46 PM PDT 24 |
| Finished | Jun 23 07:33:56 PM PDT 24 |
| Peak memory | 574312 kb |
| Host | smart-61cf0301-097c-49ca-8d17-805685bc5b04 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98933557 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.xbar_access_same_de vice_slow_rsp.98933557 |
| Directory | /workspace/25.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/25.xbar_error_and_unmapped_addr.2798478823 |
| Short name | T1375 |
| Test name | |
| Test status | |
| Simulation time | 1387368198 ps |
| CPU time | 58.15 seconds |
| Started | Jun 23 07:27:39 PM PDT 24 |
| Finished | Jun 23 07:28:38 PM PDT 24 |
| Peak memory | 573736 kb |
| Host | smart-58334bed-9cd4-4edc-bf29-558fb5bd3254 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2798478823 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.xbar_error_and_unmapped_add r.2798478823 |
| Directory | /workspace/25.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/25.xbar_error_random.2684785691 |
| Short name | T2270 |
| Test name | |
| Test status | |
| Simulation time | 267767091 ps |
| CPU time | 25.2 seconds |
| Started | Jun 23 07:27:46 PM PDT 24 |
| Finished | Jun 23 07:28:11 PM PDT 24 |
| Peak memory | 573484 kb |
| Host | smart-be0db4c2-dde1-4cf0-be6d-419f86726fd3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2684785691 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.xbar_error_random.2684785691 |
| Directory | /workspace/25.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/25.xbar_random.3563882432 |
| Short name | T2025 |
| Test name | |
| Test status | |
| Simulation time | 542886644 ps |
| CPU time | 45.22 seconds |
| Started | Jun 23 07:27:37 PM PDT 24 |
| Finished | Jun 23 07:28:22 PM PDT 24 |
| Peak memory | 574076 kb |
| Host | smart-5921d90d-6653-4ec0-baa7-b9dad1c29200 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3563882432 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.xbar_random.3563882432 |
| Directory | /workspace/25.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/25.xbar_random_large_delays.1935525793 |
| Short name | T627 |
| Test name | |
| Test status | |
| Simulation time | 19742271682 ps |
| CPU time | 216.29 seconds |
| Started | Jun 23 07:27:37 PM PDT 24 |
| Finished | Jun 23 07:31:14 PM PDT 24 |
| Peak memory | 574192 kb |
| Host | smart-74e08eef-98b4-4c81-8cd8-96e1ff939b3d |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1935525793 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.xbar_random_large_delays.1935525793 |
| Directory | /workspace/25.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/25.xbar_random_slow_rsp.4141089553 |
| Short name | T2164 |
| Test name | |
| Test status | |
| Simulation time | 40242514122 ps |
| CPU time | 743.89 seconds |
| Started | Jun 23 07:27:46 PM PDT 24 |
| Finished | Jun 23 07:40:10 PM PDT 24 |
| Peak memory | 574336 kb |
| Host | smart-36a63962-4c46-4186-888e-be252a41b8f9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4141089553 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.xbar_random_slow_rsp.4141089553 |
| Directory | /workspace/25.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/25.xbar_random_zero_delays.3991318343 |
| Short name | T1879 |
| Test name | |
| Test status | |
| Simulation time | 530033794 ps |
| CPU time | 39.13 seconds |
| Started | Jun 23 07:27:37 PM PDT 24 |
| Finished | Jun 23 07:28:16 PM PDT 24 |
| Peak memory | 573256 kb |
| Host | smart-00978b7e-b951-463d-a3c2-d75c28f4ebe3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3991318343 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.xbar_random_zero_del ays.3991318343 |
| Directory | /workspace/25.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/25.xbar_same_source.914861591 |
| Short name | T2681 |
| Test name | |
| Test status | |
| Simulation time | 1601916730 ps |
| CPU time | 45.36 seconds |
| Started | Jun 23 07:27:38 PM PDT 24 |
| Finished | Jun 23 07:28:24 PM PDT 24 |
| Peak memory | 573348 kb |
| Host | smart-6f29d75e-a5b5-48ea-ac1b-de9bae608d50 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=914861591 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.xbar_same_source.914861591 |
| Directory | /workspace/25.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/25.xbar_smoke.1558878603 |
| Short name | T2005 |
| Test name | |
| Test status | |
| Simulation time | 46351275 ps |
| CPU time | 6 seconds |
| Started | Jun 23 07:27:38 PM PDT 24 |
| Finished | Jun 23 07:27:44 PM PDT 24 |
| Peak memory | 565552 kb |
| Host | smart-eb01d2a6-7e3b-47c3-9cf3-bda6d21796a2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1558878603 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.xbar_smoke.1558878603 |
| Directory | /workspace/25.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/25.xbar_smoke_large_delays.3975701507 |
| Short name | T2557 |
| Test name | |
| Test status | |
| Simulation time | 6998531235 ps |
| CPU time | 72.32 seconds |
| Started | Jun 23 07:27:35 PM PDT 24 |
| Finished | Jun 23 07:28:48 PM PDT 24 |
| Peak memory | 565912 kb |
| Host | smart-ba866dec-1b37-4954-953b-0dfd49bba64b |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3975701507 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.xbar_smoke_large_delays.3975701507 |
| Directory | /workspace/25.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/25.xbar_smoke_slow_rsp.1729985275 |
| Short name | T1600 |
| Test name | |
| Test status | |
| Simulation time | 4110741236 ps |
| CPU time | 67.27 seconds |
| Started | Jun 23 07:27:34 PM PDT 24 |
| Finished | Jun 23 07:28:42 PM PDT 24 |
| Peak memory | 565496 kb |
| Host | smart-bf5b9b13-4db1-4bc9-98d6-a7b842dacd87 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1729985275 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.xbar_smoke_slow_rsp.1729985275 |
| Directory | /workspace/25.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/25.xbar_smoke_zero_delays.2282714975 |
| Short name | T1572 |
| Test name | |
| Test status | |
| Simulation time | 47381134 ps |
| CPU time | 6.23 seconds |
| Started | Jun 23 07:27:38 PM PDT 24 |
| Finished | Jun 23 07:27:44 PM PDT 24 |
| Peak memory | 573524 kb |
| Host | smart-ce822a89-1213-4977-a05e-c27ac8bc2858 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2282714975 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.xbar_smoke_zero_delay s.2282714975 |
| Directory | /workspace/25.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/25.xbar_stress_all.2846580191 |
| Short name | T559 |
| Test name | |
| Test status | |
| Simulation time | 17102646125 ps |
| CPU time | 649.84 seconds |
| Started | Jun 23 07:27:38 PM PDT 24 |
| Finished | Jun 23 07:38:29 PM PDT 24 |
| Peak memory | 574268 kb |
| Host | smart-5e3812a1-d0f1-4466-ab48-087ea7c6f4be |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2846580191 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.xbar_stress_all.2846580191 |
| Directory | /workspace/25.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/25.xbar_stress_all_with_error.1311223314 |
| Short name | T1418 |
| Test name | |
| Test status | |
| Simulation time | 2089417554 ps |
| CPU time | 68.97 seconds |
| Started | Jun 23 07:27:44 PM PDT 24 |
| Finished | Jun 23 07:28:53 PM PDT 24 |
| Peak memory | 574176 kb |
| Host | smart-1f0ccb3f-1d14-4575-85a6-9b21667e8000 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1311223314 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.xbar_stress_all_with_error.1311223314 |
| Directory | /workspace/25.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/25.xbar_stress_all_with_rand_reset.387538637 |
| Short name | T903 |
| Test name | |
| Test status | |
| Simulation time | 4556170415 ps |
| CPU time | 266.34 seconds |
| Started | Jun 23 07:27:42 PM PDT 24 |
| Finished | Jun 23 07:32:09 PM PDT 24 |
| Peak memory | 576348 kb |
| Host | smart-6040f555-23c0-45e9-9000-71d24e2c513f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=387538637 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_res et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.xbar_stress_all_ with_rand_reset.387538637 |
| Directory | /workspace/25.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/25.xbar_stress_all_with_reset_error.2779650992 |
| Short name | T2206 |
| Test name | |
| Test status | |
| Simulation time | 82814991 ps |
| CPU time | 15.15 seconds |
| Started | Jun 23 07:27:43 PM PDT 24 |
| Finished | Jun 23 07:27:59 PM PDT 24 |
| Peak memory | 565220 kb |
| Host | smart-645445af-5724-435c-802d-48dbe85b0f46 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2779650992 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.xbar_stress_al l_with_reset_error.2779650992 |
| Directory | /workspace/25.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/25.xbar_unmapped_addr.2036097338 |
| Short name | T1738 |
| Test name | |
| Test status | |
| Simulation time | 287084501 ps |
| CPU time | 15.55 seconds |
| Started | Jun 23 07:27:42 PM PDT 24 |
| Finished | Jun 23 07:27:58 PM PDT 24 |
| Peak memory | 574108 kb |
| Host | smart-1924086f-df79-4ec4-aabc-bcf0eaa56423 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2036097338 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.xbar_unmapped_addr.2036097338 |
| Directory | /workspace/25.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/26.chip_tl_errors.2331336226 |
| Short name | T722 |
| Test name | |
| Test status | |
| Simulation time | 4717907023 ps |
| CPU time | 481.95 seconds |
| Started | Jun 23 07:27:45 PM PDT 24 |
| Finished | Jun 23 07:35:47 PM PDT 24 |
| Peak memory | 603384 kb |
| Host | smart-3d1119aa-2ba8-48ee-9012-ede9cf59fd87 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2331336226 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.chip_tl_errors.2331336226 |
| Directory | /workspace/26.chip_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/26.xbar_access_same_device.603930671 |
| Short name | T1726 |
| Test name | |
| Test status | |
| Simulation time | 1330174528 ps |
| CPU time | 66.77 seconds |
| Started | Jun 23 07:28:04 PM PDT 24 |
| Finished | Jun 23 07:29:11 PM PDT 24 |
| Peak memory | 573812 kb |
| Host | smart-4487bd6a-dd52-4ddb-bcfd-c7064b3090b7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=603930671 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.xbar_access_same_device. 603930671 |
| Directory | /workspace/26.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/26.xbar_access_same_device_slow_rsp.833001206 |
| Short name | T856 |
| Test name | |
| Test status | |
| Simulation time | 56336018784 ps |
| CPU time | 979.37 seconds |
| Started | Jun 23 07:28:08 PM PDT 24 |
| Finished | Jun 23 07:44:28 PM PDT 24 |
| Peak memory | 574208 kb |
| Host | smart-f95b7b1d-9128-4c94-ba17-55c46c331fc0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=833001206 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.xbar_access_same_d evice_slow_rsp.833001206 |
| Directory | /workspace/26.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/26.xbar_error_and_unmapped_addr.3040844734 |
| Short name | T1770 |
| Test name | |
| Test status | |
| Simulation time | 752810687 ps |
| CPU time | 35.59 seconds |
| Started | Jun 23 07:28:12 PM PDT 24 |
| Finished | Jun 23 07:28:48 PM PDT 24 |
| Peak memory | 573720 kb |
| Host | smart-612d52bb-e531-4b0d-842d-b48a10c9080d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3040844734 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.xbar_error_and_unmapped_add r.3040844734 |
| Directory | /workspace/26.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/26.xbar_error_random.654662750 |
| Short name | T2197 |
| Test name | |
| Test status | |
| Simulation time | 615941424 ps |
| CPU time | 22.75 seconds |
| Started | Jun 23 07:28:14 PM PDT 24 |
| Finished | Jun 23 07:28:37 PM PDT 24 |
| Peak memory | 573696 kb |
| Host | smart-d03c44ef-b11f-4530-826f-695e5eaa0d1d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=654662750 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.xbar_error_random.654662750 |
| Directory | /workspace/26.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/26.xbar_random.1611431409 |
| Short name | T2079 |
| Test name | |
| Test status | |
| Simulation time | 54085295 ps |
| CPU time | 7.89 seconds |
| Started | Jun 23 07:28:06 PM PDT 24 |
| Finished | Jun 23 07:28:15 PM PDT 24 |
| Peak memory | 565892 kb |
| Host | smart-dbdecfb5-f116-4f44-b740-29cf63c46fd8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1611431409 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.xbar_random.1611431409 |
| Directory | /workspace/26.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/26.xbar_random_large_delays.3181870572 |
| Short name | T450 |
| Test name | |
| Test status | |
| Simulation time | 101031088439 ps |
| CPU time | 1016.46 seconds |
| Started | Jun 23 07:28:06 PM PDT 24 |
| Finished | Jun 23 07:45:03 PM PDT 24 |
| Peak memory | 574224 kb |
| Host | smart-93cafe05-abd5-4c35-9014-439dcb8689e6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3181870572 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.xbar_random_large_delays.3181870572 |
| Directory | /workspace/26.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/26.xbar_random_slow_rsp.3860615859 |
| Short name | T571 |
| Test name | |
| Test status | |
| Simulation time | 52650777086 ps |
| CPU time | 929.13 seconds |
| Started | Jun 23 07:28:06 PM PDT 24 |
| Finished | Jun 23 07:43:35 PM PDT 24 |
| Peak memory | 574116 kb |
| Host | smart-059ce8a3-6150-4279-a38b-4ece39f4668d |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3860615859 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.xbar_random_slow_rsp.3860615859 |
| Directory | /workspace/26.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/26.xbar_random_zero_delays.3580409883 |
| Short name | T454 |
| Test name | |
| Test status | |
| Simulation time | 428976725 ps |
| CPU time | 35.95 seconds |
| Started | Jun 23 07:28:05 PM PDT 24 |
| Finished | Jun 23 07:28:42 PM PDT 24 |
| Peak memory | 574076 kb |
| Host | smart-de89fc52-fa49-4d39-9098-f403162fff9b |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3580409883 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.xbar_random_zero_del ays.3580409883 |
| Directory | /workspace/26.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/26.xbar_same_source.1003727705 |
| Short name | T2081 |
| Test name | |
| Test status | |
| Simulation time | 1500237374 ps |
| CPU time | 46.01 seconds |
| Started | Jun 23 07:28:07 PM PDT 24 |
| Finished | Jun 23 07:28:53 PM PDT 24 |
| Peak memory | 574064 kb |
| Host | smart-66899371-593b-4637-9ed7-b67579b168e5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1003727705 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.xbar_same_source.1003727705 |
| Directory | /workspace/26.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/26.xbar_smoke.3918344021 |
| Short name | T1666 |
| Test name | |
| Test status | |
| Simulation time | 38748217 ps |
| CPU time | 5.85 seconds |
| Started | Jun 23 07:27:45 PM PDT 24 |
| Finished | Jun 23 07:27:51 PM PDT 24 |
| Peak memory | 573328 kb |
| Host | smart-eacc8adc-60bc-4cde-8489-a205c26dd2c6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3918344021 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.xbar_smoke.3918344021 |
| Directory | /workspace/26.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/26.xbar_smoke_large_delays.1103286344 |
| Short name | T2166 |
| Test name | |
| Test status | |
| Simulation time | 10592013107 ps |
| CPU time | 108.72 seconds |
| Started | Jun 23 07:28:08 PM PDT 24 |
| Finished | Jun 23 07:29:57 PM PDT 24 |
| Peak memory | 574144 kb |
| Host | smart-aa5ef31a-30be-428c-8b4d-2cc9b5712dec |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1103286344 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.xbar_smoke_large_delays.1103286344 |
| Directory | /workspace/26.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/26.xbar_smoke_slow_rsp.270702102 |
| Short name | T2209 |
| Test name | |
| Test status | |
| Simulation time | 4996675612 ps |
| CPU time | 88.79 seconds |
| Started | Jun 23 07:28:05 PM PDT 24 |
| Finished | Jun 23 07:29:34 PM PDT 24 |
| Peak memory | 565544 kb |
| Host | smart-2329e6ce-4a3e-4470-88bf-f2b5024ed74a |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=270702102 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.xbar_smoke_slow_rsp.270702102 |
| Directory | /workspace/26.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/26.xbar_smoke_zero_delays.3307860357 |
| Short name | T2443 |
| Test name | |
| Test status | |
| Simulation time | 53477736 ps |
| CPU time | 6.47 seconds |
| Started | Jun 23 07:27:44 PM PDT 24 |
| Finished | Jun 23 07:27:50 PM PDT 24 |
| Peak memory | 565460 kb |
| Host | smart-e94f4ec0-7825-4a37-950c-d22dfe51119e |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3307860357 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.xbar_smoke_zero_delay s.3307860357 |
| Directory | /workspace/26.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/26.xbar_stress_all.3268754127 |
| Short name | T1987 |
| Test name | |
| Test status | |
| Simulation time | 2051382707 ps |
| CPU time | 145.16 seconds |
| Started | Jun 23 07:28:11 PM PDT 24 |
| Finished | Jun 23 07:30:36 PM PDT 24 |
| Peak memory | 574192 kb |
| Host | smart-54968660-f073-4f34-8ca5-dcd91a76b3da |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3268754127 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.xbar_stress_all.3268754127 |
| Directory | /workspace/26.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/26.xbar_stress_all_with_error.2159248801 |
| Short name | T1565 |
| Test name | |
| Test status | |
| Simulation time | 5223248197 ps |
| CPU time | 206.71 seconds |
| Started | Jun 23 07:28:13 PM PDT 24 |
| Finished | Jun 23 07:31:40 PM PDT 24 |
| Peak memory | 574240 kb |
| Host | smart-4a155111-bb8d-4157-9356-2282e3fb9a38 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2159248801 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.xbar_stress_all_with_error.2159248801 |
| Directory | /workspace/26.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/26.xbar_stress_all_with_rand_reset.2753269111 |
| Short name | T2339 |
| Test name | |
| Test status | |
| Simulation time | 10549721160 ps |
| CPU time | 644.59 seconds |
| Started | Jun 23 07:28:11 PM PDT 24 |
| Finished | Jun 23 07:38:56 PM PDT 24 |
| Peak memory | 576356 kb |
| Host | smart-11ac0a8e-6536-4e96-9195-70d424fbbcd5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2753269111 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.xbar_stress_all _with_rand_reset.2753269111 |
| Directory | /workspace/26.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/26.xbar_stress_all_with_reset_error.262704381 |
| Short name | T2595 |
| Test name | |
| Test status | |
| Simulation time | 337198717 ps |
| CPU time | 113.91 seconds |
| Started | Jun 23 07:28:12 PM PDT 24 |
| Finished | Jun 23 07:30:07 PM PDT 24 |
| Peak memory | 577388 kb |
| Host | smart-8c4725f7-08ed-417d-adaa-34697c6d56a4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=262704381 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.xbar_stress_all _with_reset_error.262704381 |
| Directory | /workspace/26.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/26.xbar_unmapped_addr.2241325258 |
| Short name | T2304 |
| Test name | |
| Test status | |
| Simulation time | 957646049 ps |
| CPU time | 43.42 seconds |
| Started | Jun 23 07:28:10 PM PDT 24 |
| Finished | Jun 23 07:28:54 PM PDT 24 |
| Peak memory | 574152 kb |
| Host | smart-4a5fa071-fbc2-4946-85ba-09090765e7cf |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2241325258 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.xbar_unmapped_addr.2241325258 |
| Directory | /workspace/26.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/27.chip_tl_errors.3156217444 |
| Short name | T718 |
| Test name | |
| Test status | |
| Simulation time | 3130562690 ps |
| CPU time | 160.45 seconds |
| Started | Jun 23 07:29:16 PM PDT 24 |
| Finished | Jun 23 07:31:56 PM PDT 24 |
| Peak memory | 597472 kb |
| Host | smart-0fa14aac-4d8b-4857-bb1f-089341183b1e |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3156217444 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.chip_tl_errors.3156217444 |
| Directory | /workspace/27.chip_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/27.xbar_access_same_device.3665903349 |
| Short name | T523 |
| Test name | |
| Test status | |
| Simulation time | 866988184 ps |
| CPU time | 65.54 seconds |
| Started | Jun 23 07:28:18 PM PDT 24 |
| Finished | Jun 23 07:29:24 PM PDT 24 |
| Peak memory | 574104 kb |
| Host | smart-94e0e7d0-9c9d-46fe-afc2-9cf420ae76ed |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3665903349 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.xbar_access_same_device .3665903349 |
| Directory | /workspace/27.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/27.xbar_access_same_device_slow_rsp.3780823030 |
| Short name | T1744 |
| Test name | |
| Test status | |
| Simulation time | 58753953742 ps |
| CPU time | 1001.54 seconds |
| Started | Jun 23 07:28:12 PM PDT 24 |
| Finished | Jun 23 07:44:55 PM PDT 24 |
| Peak memory | 574208 kb |
| Host | smart-d89cc107-9f26-4424-a638-dc911ab26594 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3780823030 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.xbar_access_same_ device_slow_rsp.3780823030 |
| Directory | /workspace/27.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/27.xbar_error_and_unmapped_addr.868339708 |
| Short name | T1401 |
| Test name | |
| Test status | |
| Simulation time | 547961140 ps |
| CPU time | 27.35 seconds |
| Started | Jun 23 07:28:12 PM PDT 24 |
| Finished | Jun 23 07:28:39 PM PDT 24 |
| Peak memory | 573412 kb |
| Host | smart-315efaa3-951d-4b4b-ae18-6ceb2ecc87af |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=868339708 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.xbar_error_and_unmapped_addr .868339708 |
| Directory | /workspace/27.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/27.xbar_error_random.2033478029 |
| Short name | T2669 |
| Test name | |
| Test status | |
| Simulation time | 375553613 ps |
| CPU time | 35.83 seconds |
| Started | Jun 23 07:28:15 PM PDT 24 |
| Finished | Jun 23 07:28:51 PM PDT 24 |
| Peak memory | 573796 kb |
| Host | smart-a89efbf1-b6fc-4e1f-8b57-df5ba2c6bdfb |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2033478029 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.xbar_error_random.2033478029 |
| Directory | /workspace/27.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/27.xbar_random.2276456145 |
| Short name | T642 |
| Test name | |
| Test status | |
| Simulation time | 460899973 ps |
| CPU time | 44.78 seconds |
| Started | Jun 23 07:28:15 PM PDT 24 |
| Finished | Jun 23 07:29:00 PM PDT 24 |
| Peak memory | 574212 kb |
| Host | smart-53f767fd-be29-41cf-b05d-989cc34d8eab |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2276456145 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.xbar_random.2276456145 |
| Directory | /workspace/27.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/27.xbar_random_large_delays.643426495 |
| Short name | T663 |
| Test name | |
| Test status | |
| Simulation time | 84884970936 ps |
| CPU time | 820.98 seconds |
| Started | Jun 23 07:28:13 PM PDT 24 |
| Finished | Jun 23 07:41:54 PM PDT 24 |
| Peak memory | 574152 kb |
| Host | smart-05604080-b992-4f0a-a9cf-c67cb5fa57e3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=643426495 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.xbar_random_large_delays.643426495 |
| Directory | /workspace/27.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/27.xbar_random_slow_rsp.4251728210 |
| Short name | T1924 |
| Test name | |
| Test status | |
| Simulation time | 37354555359 ps |
| CPU time | 656.64 seconds |
| Started | Jun 23 07:28:10 PM PDT 24 |
| Finished | Jun 23 07:39:07 PM PDT 24 |
| Peak memory | 574176 kb |
| Host | smart-071297cc-6c29-43a0-b1bd-6ccbd9cd24a1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4251728210 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.xbar_random_slow_rsp.4251728210 |
| Directory | /workspace/27.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/27.xbar_random_zero_delays.724446905 |
| Short name | T1658 |
| Test name | |
| Test status | |
| Simulation time | 452871670 ps |
| CPU time | 38 seconds |
| Started | Jun 23 07:28:13 PM PDT 24 |
| Finished | Jun 23 07:28:51 PM PDT 24 |
| Peak memory | 573420 kb |
| Host | smart-beba4937-54b1-4a7e-9af0-20acc45f9939 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=724446905 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.xbar_random_zero_dela ys.724446905 |
| Directory | /workspace/27.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/27.xbar_same_source.1115813060 |
| Short name | T1558 |
| Test name | |
| Test status | |
| Simulation time | 1292604133 ps |
| CPU time | 35.13 seconds |
| Started | Jun 23 07:28:11 PM PDT 24 |
| Finished | Jun 23 07:28:46 PM PDT 24 |
| Peak memory | 573800 kb |
| Host | smart-9446d72e-fe61-45ee-9094-7dababfb82e1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1115813060 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.xbar_same_source.1115813060 |
| Directory | /workspace/27.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/27.xbar_smoke.2369528408 |
| Short name | T1548 |
| Test name | |
| Test status | |
| Simulation time | 40740646 ps |
| CPU time | 6.18 seconds |
| Started | Jun 23 07:28:18 PM PDT 24 |
| Finished | Jun 23 07:28:25 PM PDT 24 |
| Peak memory | 573348 kb |
| Host | smart-11d2d9d2-f692-4185-a55f-9b0154207e14 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2369528408 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.xbar_smoke.2369528408 |
| Directory | /workspace/27.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/27.xbar_smoke_large_delays.2682209281 |
| Short name | T1727 |
| Test name | |
| Test status | |
| Simulation time | 9695679053 ps |
| CPU time | 102.23 seconds |
| Started | Jun 23 07:28:12 PM PDT 24 |
| Finished | Jun 23 07:29:54 PM PDT 24 |
| Peak memory | 565192 kb |
| Host | smart-3d43708c-857e-44f6-b52f-a98e829fcfd9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2682209281 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.xbar_smoke_large_delays.2682209281 |
| Directory | /workspace/27.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/27.xbar_smoke_slow_rsp.183433671 |
| Short name | T2479 |
| Test name | |
| Test status | |
| Simulation time | 5991233790 ps |
| CPU time | 101.35 seconds |
| Started | Jun 23 07:28:13 PM PDT 24 |
| Finished | Jun 23 07:29:55 PM PDT 24 |
| Peak memory | 565948 kb |
| Host | smart-7942a5da-ffbe-41d4-ba58-4a2767cb3c70 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=183433671 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.xbar_smoke_slow_rsp.183433671 |
| Directory | /workspace/27.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/27.xbar_smoke_zero_delays.322924260 |
| Short name | T2160 |
| Test name | |
| Test status | |
| Simulation time | 41372272 ps |
| CPU time | 6.01 seconds |
| Started | Jun 23 07:28:12 PM PDT 24 |
| Finished | Jun 23 07:28:18 PM PDT 24 |
| Peak memory | 565500 kb |
| Host | smart-ed17753e-d669-4ff7-81cf-00682f365232 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=322924260 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.xbar_smoke_zero_delays .322924260 |
| Directory | /workspace/27.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/27.xbar_stress_all.3126178216 |
| Short name | T2613 |
| Test name | |
| Test status | |
| Simulation time | 12210734884 ps |
| CPU time | 507.73 seconds |
| Started | Jun 23 07:28:15 PM PDT 24 |
| Finished | Jun 23 07:36:43 PM PDT 24 |
| Peak memory | 574316 kb |
| Host | smart-197f6f88-03ac-448f-a9b1-39594c390698 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3126178216 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.xbar_stress_all.3126178216 |
| Directory | /workspace/27.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/27.xbar_stress_all_with_error.3209488593 |
| Short name | T1945 |
| Test name | |
| Test status | |
| Simulation time | 1247798830 ps |
| CPU time | 96.92 seconds |
| Started | Jun 23 07:28:12 PM PDT 24 |
| Finished | Jun 23 07:29:49 PM PDT 24 |
| Peak memory | 574208 kb |
| Host | smart-7c0e85b4-8e54-4029-910c-e47d0d4d6cea |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3209488593 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.xbar_stress_all_with_error.3209488593 |
| Directory | /workspace/27.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/27.xbar_stress_all_with_rand_reset.4103241637 |
| Short name | T897 |
| Test name | |
| Test status | |
| Simulation time | 270368873 ps |
| CPU time | 57.89 seconds |
| Started | Jun 23 07:28:15 PM PDT 24 |
| Finished | Jun 23 07:29:13 PM PDT 24 |
| Peak memory | 576300 kb |
| Host | smart-077dcd0d-bd63-420f-957b-dd88f2c8567c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4103241637 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.xbar_stress_all _with_rand_reset.4103241637 |
| Directory | /workspace/27.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/27.xbar_stress_all_with_reset_error.1351206298 |
| Short name | T1792 |
| Test name | |
| Test status | |
| Simulation time | 4657260572 ps |
| CPU time | 185.73 seconds |
| Started | Jun 23 07:28:14 PM PDT 24 |
| Finished | Jun 23 07:31:20 PM PDT 24 |
| Peak memory | 574360 kb |
| Host | smart-74aa69ef-3579-4dc2-8f2d-272a4ef6f878 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1351206298 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.xbar_stress_al l_with_reset_error.1351206298 |
| Directory | /workspace/27.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/27.xbar_unmapped_addr.448039439 |
| Short name | T2008 |
| Test name | |
| Test status | |
| Simulation time | 177864474 ps |
| CPU time | 23.22 seconds |
| Started | Jun 23 07:28:18 PM PDT 24 |
| Finished | Jun 23 07:28:42 PM PDT 24 |
| Peak memory | 574116 kb |
| Host | smart-48c9a3dc-6090-45f6-8829-61e3a193ce73 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=448039439 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.xbar_unmapped_addr.448039439 |
| Directory | /workspace/27.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/28.chip_tl_errors.1662861206 |
| Short name | T2676 |
| Test name | |
| Test status | |
| Simulation time | 3719903027 ps |
| CPU time | 250.54 seconds |
| Started | Jun 23 07:28:14 PM PDT 24 |
| Finished | Jun 23 07:32:25 PM PDT 24 |
| Peak memory | 603532 kb |
| Host | smart-ea9a4d24-8e22-4527-a5b6-c7b2fe75ecb3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1662861206 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.chip_tl_errors.1662861206 |
| Directory | /workspace/28.chip_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/28.xbar_access_same_device.1960085874 |
| Short name | T2738 |
| Test name | |
| Test status | |
| Simulation time | 1317564343 ps |
| CPU time | 65.15 seconds |
| Started | Jun 23 07:28:19 PM PDT 24 |
| Finished | Jun 23 07:29:24 PM PDT 24 |
| Peak memory | 574028 kb |
| Host | smart-8ae8de3e-5cd7-41ce-92e8-635619fa75a6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1960085874 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.xbar_access_same_device .1960085874 |
| Directory | /workspace/28.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/28.xbar_access_same_device_slow_rsp.4091823719 |
| Short name | T2609 |
| Test name | |
| Test status | |
| Simulation time | 64285924245 ps |
| CPU time | 1201.82 seconds |
| Started | Jun 23 07:28:22 PM PDT 24 |
| Finished | Jun 23 07:48:24 PM PDT 24 |
| Peak memory | 573616 kb |
| Host | smart-811189f8-4119-459b-8244-cfdccb302138 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4091823719 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.xbar_access_same_ device_slow_rsp.4091823719 |
| Directory | /workspace/28.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/28.xbar_error_and_unmapped_addr.791379714 |
| Short name | T1518 |
| Test name | |
| Test status | |
| Simulation time | 179782472 ps |
| CPU time | 21.02 seconds |
| Started | Jun 23 07:28:22 PM PDT 24 |
| Finished | Jun 23 07:28:43 PM PDT 24 |
| Peak memory | 573380 kb |
| Host | smart-628f96ae-3297-4236-baac-986d383698e2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=791379714 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.xbar_error_and_unmapped_addr .791379714 |
| Directory | /workspace/28.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/28.xbar_error_random.4233860385 |
| Short name | T1980 |
| Test name | |
| Test status | |
| Simulation time | 170583013 ps |
| CPU time | 15.94 seconds |
| Started | Jun 23 07:28:18 PM PDT 24 |
| Finished | Jun 23 07:28:35 PM PDT 24 |
| Peak memory | 573704 kb |
| Host | smart-a4f98dbd-0d11-444e-a731-f70eaafd38db |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4233860385 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.xbar_error_random.4233860385 |
| Directory | /workspace/28.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/28.xbar_random.3525967652 |
| Short name | T2301 |
| Test name | |
| Test status | |
| Simulation time | 195589030 ps |
| CPU time | 17.86 seconds |
| Started | Jun 23 07:28:20 PM PDT 24 |
| Finished | Jun 23 07:28:38 PM PDT 24 |
| Peak memory | 573296 kb |
| Host | smart-d8d1edc8-d202-4647-994b-edee8407ef06 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3525967652 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.xbar_random.3525967652 |
| Directory | /workspace/28.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/28.xbar_random_large_delays.2336898678 |
| Short name | T1907 |
| Test name | |
| Test status | |
| Simulation time | 52396120417 ps |
| CPU time | 536.55 seconds |
| Started | Jun 23 07:28:23 PM PDT 24 |
| Finished | Jun 23 07:37:20 PM PDT 24 |
| Peak memory | 573552 kb |
| Host | smart-f9c69de5-0d98-46e7-aa31-ff0614c24c64 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2336898678 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.xbar_random_large_delays.2336898678 |
| Directory | /workspace/28.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/28.xbar_random_slow_rsp.4132120016 |
| Short name | T2540 |
| Test name | |
| Test status | |
| Simulation time | 52998238425 ps |
| CPU time | 853.57 seconds |
| Started | Jun 23 07:28:23 PM PDT 24 |
| Finished | Jun 23 07:42:37 PM PDT 24 |
| Peak memory | 573524 kb |
| Host | smart-a83f6562-6984-4613-ada9-12ed072f9147 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4132120016 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.xbar_random_slow_rsp.4132120016 |
| Directory | /workspace/28.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/28.xbar_random_zero_delays.2914440615 |
| Short name | T1981 |
| Test name | |
| Test status | |
| Simulation time | 188832298 ps |
| CPU time | 16.86 seconds |
| Started | Jun 23 07:28:24 PM PDT 24 |
| Finished | Jun 23 07:28:41 PM PDT 24 |
| Peak memory | 573412 kb |
| Host | smart-983c40db-4ce4-4202-b280-2341a0d261b9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2914440615 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.xbar_random_zero_del ays.2914440615 |
| Directory | /workspace/28.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/28.xbar_same_source.3616707001 |
| Short name | T2518 |
| Test name | |
| Test status | |
| Simulation time | 135173297 ps |
| CPU time | 11.6 seconds |
| Started | Jun 23 07:28:23 PM PDT 24 |
| Finished | Jun 23 07:28:35 PM PDT 24 |
| Peak memory | 574088 kb |
| Host | smart-a422453b-0da7-458b-8ec1-f83212ce75ee |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3616707001 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.xbar_same_source.3616707001 |
| Directory | /workspace/28.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/28.xbar_smoke.1846681277 |
| Short name | T2848 |
| Test name | |
| Test status | |
| Simulation time | 225355812 ps |
| CPU time | 9.28 seconds |
| Started | Jun 23 07:28:10 PM PDT 24 |
| Finished | Jun 23 07:28:20 PM PDT 24 |
| Peak memory | 565476 kb |
| Host | smart-8c8305f6-0e62-4334-a653-d98f9839db18 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1846681277 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.xbar_smoke.1846681277 |
| Directory | /workspace/28.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/28.xbar_smoke_large_delays.2280738135 |
| Short name | T1816 |
| Test name | |
| Test status | |
| Simulation time | 6804162047 ps |
| CPU time | 71.98 seconds |
| Started | Jun 23 07:28:22 PM PDT 24 |
| Finished | Jun 23 07:29:34 PM PDT 24 |
| Peak memory | 565552 kb |
| Host | smart-b40cd8a3-067c-4ff1-81c9-e2c02b0db960 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2280738135 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.xbar_smoke_large_delays.2280738135 |
| Directory | /workspace/28.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/28.xbar_smoke_slow_rsp.3559821264 |
| Short name | T1809 |
| Test name | |
| Test status | |
| Simulation time | 5317778483 ps |
| CPU time | 93.22 seconds |
| Started | Jun 23 07:28:22 PM PDT 24 |
| Finished | Jun 23 07:29:55 PM PDT 24 |
| Peak memory | 565920 kb |
| Host | smart-23a41b3b-3c09-4df8-8f6a-048ea5be12da |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3559821264 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.xbar_smoke_slow_rsp.3559821264 |
| Directory | /workspace/28.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/28.xbar_smoke_zero_delays.3157056340 |
| Short name | T2785 |
| Test name | |
| Test status | |
| Simulation time | 45978136 ps |
| CPU time | 5.87 seconds |
| Started | Jun 23 07:28:14 PM PDT 24 |
| Finished | Jun 23 07:28:20 PM PDT 24 |
| Peak memory | 573212 kb |
| Host | smart-9aa11530-7af4-401b-b463-b8309c8853d9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3157056340 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.xbar_smoke_zero_delay s.3157056340 |
| Directory | /workspace/28.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/28.xbar_stress_all.2921866475 |
| Short name | T1654 |
| Test name | |
| Test status | |
| Simulation time | 8955203383 ps |
| CPU time | 320.94 seconds |
| Started | Jun 23 07:28:26 PM PDT 24 |
| Finished | Jun 23 07:33:47 PM PDT 24 |
| Peak memory | 574308 kb |
| Host | smart-a3f2bcef-6d60-4461-8a86-798706caccd0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2921866475 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.xbar_stress_all.2921866475 |
| Directory | /workspace/28.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/28.xbar_stress_all_with_error.2385662150 |
| Short name | T1406 |
| Test name | |
| Test status | |
| Simulation time | 13918575417 ps |
| CPU time | 494.05 seconds |
| Started | Jun 23 07:28:28 PM PDT 24 |
| Finished | Jun 23 07:36:42 PM PDT 24 |
| Peak memory | 574316 kb |
| Host | smart-583950cd-0830-439b-8a66-e81529ab4eb8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2385662150 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.xbar_stress_all_with_error.2385662150 |
| Directory | /workspace/28.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/28.xbar_stress_all_with_rand_reset.1680255673 |
| Short name | T451 |
| Test name | |
| Test status | |
| Simulation time | 2570360606 ps |
| CPU time | 356.23 seconds |
| Started | Jun 23 07:28:26 PM PDT 24 |
| Finished | Jun 23 07:34:23 PM PDT 24 |
| Peak memory | 577332 kb |
| Host | smart-bd8ba372-3d54-40a5-9ba0-a5835fe9b79c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1680255673 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.xbar_stress_all _with_rand_reset.1680255673 |
| Directory | /workspace/28.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/28.xbar_stress_all_with_reset_error.2333927349 |
| Short name | T1712 |
| Test name | |
| Test status | |
| Simulation time | 774506950 ps |
| CPU time | 173.61 seconds |
| Started | Jun 23 07:28:27 PM PDT 24 |
| Finished | Jun 23 07:31:21 PM PDT 24 |
| Peak memory | 574312 kb |
| Host | smart-673ac460-1b46-470b-aae8-0d7dd7576c1f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2333927349 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.xbar_stress_al l_with_reset_error.2333927349 |
| Directory | /workspace/28.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/28.xbar_unmapped_addr.1902705383 |
| Short name | T682 |
| Test name | |
| Test status | |
| Simulation time | 91528735 ps |
| CPU time | 14.89 seconds |
| Started | Jun 23 07:28:20 PM PDT 24 |
| Finished | Jun 23 07:28:35 PM PDT 24 |
| Peak memory | 574108 kb |
| Host | smart-16b67909-9a9b-4f79-b81f-7698087ebb85 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1902705383 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.xbar_unmapped_addr.1902705383 |
| Directory | /workspace/28.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/29.chip_tl_errors.310778244 |
| Short name | T2753 |
| Test name | |
| Test status | |
| Simulation time | 4354351879 ps |
| CPU time | 242.7 seconds |
| Started | Jun 23 07:28:26 PM PDT 24 |
| Finished | Jun 23 07:32:29 PM PDT 24 |
| Peak memory | 597356 kb |
| Host | smart-fb497c6d-13ae-4249-b727-5edb30e7324d |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=310778244 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.chip_tl_errors.310778244 |
| Directory | /workspace/29.chip_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/29.xbar_access_same_device.1465012914 |
| Short name | T2082 |
| Test name | |
| Test status | |
| Simulation time | 339365360 ps |
| CPU time | 23.65 seconds |
| Started | Jun 23 07:28:41 PM PDT 24 |
| Finished | Jun 23 07:29:05 PM PDT 24 |
| Peak memory | 574128 kb |
| Host | smart-00d96e52-b23e-4c18-8ce8-2564937a41bd |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1465012914 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.xbar_access_same_device .1465012914 |
| Directory | /workspace/29.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/29.xbar_access_same_device_slow_rsp.3901814622 |
| Short name | T852 |
| Test name | |
| Test status | |
| Simulation time | 75104537549 ps |
| CPU time | 1323.98 seconds |
| Started | Jun 23 07:28:46 PM PDT 24 |
| Finished | Jun 23 07:50:50 PM PDT 24 |
| Peak memory | 573592 kb |
| Host | smart-619ae13d-0eaa-4a23-9a6c-fc9685b96ddc |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3901814622 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.xbar_access_same_ device_slow_rsp.3901814622 |
| Directory | /workspace/29.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/29.xbar_error_and_unmapped_addr.2442839589 |
| Short name | T1638 |
| Test name | |
| Test status | |
| Simulation time | 555850233 ps |
| CPU time | 24.58 seconds |
| Started | Jun 23 07:28:39 PM PDT 24 |
| Finished | Jun 23 07:29:05 PM PDT 24 |
| Peak memory | 573736 kb |
| Host | smart-69791a1a-64d1-4e70-bfd5-405575c8ff08 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2442839589 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.xbar_error_and_unmapped_add r.2442839589 |
| Directory | /workspace/29.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/29.xbar_error_random.1342344211 |
| Short name | T1463 |
| Test name | |
| Test status | |
| Simulation time | 172711824 ps |
| CPU time | 9.61 seconds |
| Started | Jun 23 07:28:41 PM PDT 24 |
| Finished | Jun 23 07:28:51 PM PDT 24 |
| Peak memory | 573288 kb |
| Host | smart-aa1052c7-256d-4d61-af98-f6fb16133ecf |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1342344211 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.xbar_error_random.1342344211 |
| Directory | /workspace/29.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/29.xbar_random.2105068032 |
| Short name | T2250 |
| Test name | |
| Test status | |
| Simulation time | 2557530324 ps |
| CPU time | 96.93 seconds |
| Started | Jun 23 07:28:33 PM PDT 24 |
| Finished | Jun 23 07:30:11 PM PDT 24 |
| Peak memory | 574208 kb |
| Host | smart-141f6230-0483-4d7b-ba06-a863f80789e0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2105068032 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.xbar_random.2105068032 |
| Directory | /workspace/29.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/29.xbar_random_large_delays.768583520 |
| Short name | T2220 |
| Test name | |
| Test status | |
| Simulation time | 48291340765 ps |
| CPU time | 513.35 seconds |
| Started | Jun 23 07:28:39 PM PDT 24 |
| Finished | Jun 23 07:37:12 PM PDT 24 |
| Peak memory | 573500 kb |
| Host | smart-2659ea29-2d51-4435-807b-9a9db76ed96d |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=768583520 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.xbar_random_large_delays.768583520 |
| Directory | /workspace/29.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/29.xbar_random_slow_rsp.3646867789 |
| Short name | T1942 |
| Test name | |
| Test status | |
| Simulation time | 25215859428 ps |
| CPU time | 434.44 seconds |
| Started | Jun 23 07:28:40 PM PDT 24 |
| Finished | Jun 23 07:35:55 PM PDT 24 |
| Peak memory | 574152 kb |
| Host | smart-e035be4e-616b-4421-9380-32bc8c3c01e3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3646867789 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.xbar_random_slow_rsp.3646867789 |
| Directory | /workspace/29.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/29.xbar_random_zero_delays.2274240572 |
| Short name | T471 |
| Test name | |
| Test status | |
| Simulation time | 526869053 ps |
| CPU time | 45.09 seconds |
| Started | Jun 23 07:28:42 PM PDT 24 |
| Finished | Jun 23 07:29:27 PM PDT 24 |
| Peak memory | 573972 kb |
| Host | smart-692a6780-9b1c-42ec-aad5-443c95d15660 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2274240572 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.xbar_random_zero_del ays.2274240572 |
| Directory | /workspace/29.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/29.xbar_same_source.4267123680 |
| Short name | T650 |
| Test name | |
| Test status | |
| Simulation time | 1835501253 ps |
| CPU time | 54.47 seconds |
| Started | Jun 23 07:28:40 PM PDT 24 |
| Finished | Jun 23 07:29:35 PM PDT 24 |
| Peak memory | 574092 kb |
| Host | smart-5fd40166-bb7a-40ca-90eb-2cb2d4f64591 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4267123680 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.xbar_same_source.4267123680 |
| Directory | /workspace/29.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/29.xbar_smoke.4129145162 |
| Short name | T1905 |
| Test name | |
| Test status | |
| Simulation time | 209231486 ps |
| CPU time | 9.54 seconds |
| Started | Jun 23 07:28:35 PM PDT 24 |
| Finished | Jun 23 07:28:45 PM PDT 24 |
| Peak memory | 565764 kb |
| Host | smart-c1c87cd4-4a26-477b-971f-5a81f5338f73 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4129145162 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.xbar_smoke.4129145162 |
| Directory | /workspace/29.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/29.xbar_smoke_large_delays.865534031 |
| Short name | T1398 |
| Test name | |
| Test status | |
| Simulation time | 7057482792 ps |
| CPU time | 71.51 seconds |
| Started | Jun 23 07:28:37 PM PDT 24 |
| Finished | Jun 23 07:29:49 PM PDT 24 |
| Peak memory | 565940 kb |
| Host | smart-40da4b62-0d19-48aa-9250-2cbb6b4244b6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=865534031 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.xbar_smoke_large_delays.865534031 |
| Directory | /workspace/29.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/29.xbar_smoke_slow_rsp.3112398151 |
| Short name | T1530 |
| Test name | |
| Test status | |
| Simulation time | 6294152671 ps |
| CPU time | 101.45 seconds |
| Started | Jun 23 07:28:34 PM PDT 24 |
| Finished | Jun 23 07:30:16 PM PDT 24 |
| Peak memory | 565556 kb |
| Host | smart-5bdc10b5-7d8e-4bf4-9338-58b9d220dd99 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3112398151 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.xbar_smoke_slow_rsp.3112398151 |
| Directory | /workspace/29.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/29.xbar_smoke_zero_delays.3019702788 |
| Short name | T1636 |
| Test name | |
| Test status | |
| Simulation time | 47906681 ps |
| CPU time | 6.53 seconds |
| Started | Jun 23 07:28:35 PM PDT 24 |
| Finished | Jun 23 07:28:42 PM PDT 24 |
| Peak memory | 565472 kb |
| Host | smart-ab7a1c31-de7c-48ba-a032-558e59e6cac7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3019702788 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.xbar_smoke_zero_delay s.3019702788 |
| Directory | /workspace/29.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/29.xbar_stress_all.437589250 |
| Short name | T2211 |
| Test name | |
| Test status | |
| Simulation time | 5602915149 ps |
| CPU time | 217.37 seconds |
| Started | Jun 23 07:28:39 PM PDT 24 |
| Finished | Jun 23 07:32:17 PM PDT 24 |
| Peak memory | 574308 kb |
| Host | smart-88e56871-9df8-4edd-a434-f935699391a8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=437589250 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.xbar_stress_all.437589250 |
| Directory | /workspace/29.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/29.xbar_stress_all_with_error.1836598464 |
| Short name | T1589 |
| Test name | |
| Test status | |
| Simulation time | 17298063368 ps |
| CPU time | 548.41 seconds |
| Started | Jun 23 07:28:39 PM PDT 24 |
| Finished | Jun 23 07:37:48 PM PDT 24 |
| Peak memory | 574356 kb |
| Host | smart-07495c6c-0611-4a59-9d8e-f62dfc85a356 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1836598464 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.xbar_stress_all_with_error.1836598464 |
| Directory | /workspace/29.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/29.xbar_stress_all_with_reset_error.4135608294 |
| Short name | T2060 |
| Test name | |
| Test status | |
| Simulation time | 788604522 ps |
| CPU time | 169.01 seconds |
| Started | Jun 23 07:28:37 PM PDT 24 |
| Finished | Jun 23 07:31:27 PM PDT 24 |
| Peak memory | 576356 kb |
| Host | smart-6032db55-1f51-4817-bf54-88e7d6513851 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4135608294 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.xbar_stress_al l_with_reset_error.4135608294 |
| Directory | /workspace/29.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/29.xbar_unmapped_addr.3994694654 |
| Short name | T2654 |
| Test name | |
| Test status | |
| Simulation time | 904833772 ps |
| CPU time | 39.29 seconds |
| Started | Jun 23 07:28:46 PM PDT 24 |
| Finished | Jun 23 07:29:25 PM PDT 24 |
| Peak memory | 574140 kb |
| Host | smart-55b76b2b-fc14-4091-9f6c-2bdf6af9a45f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3994694654 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.xbar_unmapped_addr.3994694654 |
| Directory | /workspace/29.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/3.chip_csr_aliasing.1938153463 |
| Short name | T400 |
| Test name | |
| Test status | |
| Simulation time | 58538553164 ps |
| CPU time | 9229.23 seconds |
| Started | Jun 23 07:21:18 PM PDT 24 |
| Finished | Jun 23 09:55:08 PM PDT 24 |
| Peak memory | 647808 kb |
| Host | smart-63100938-271a-4735-9372-612f9371d333 |
| User | root |
| Command | /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +csr_aliasing +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1938153463 -assert nopostproc +UVM_TESTNAME=chip_ base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/ null -cm_name 3.chip_csr_aliasing.1938153463 |
| Directory | /workspace/3.chip_csr_aliasing/latest |
| Test location | /workspace/coverage/cover_reg_top/3.chip_csr_bit_bash.3512137624 |
| Short name | T2077 |
| Test name | |
| Test status | |
| Simulation time | 5752712586 ps |
| CPU time | 462.76 seconds |
| Started | Jun 23 07:21:15 PM PDT 24 |
| Finished | Jun 23 07:28:58 PM PDT 24 |
| Peak memory | 588704 kb |
| Host | smart-63d91fa8-064e-478b-8187-476c97676b81 |
| User | root |
| Command | /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +num_test_csrs=200 +csr_bit_bash +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3512137624 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to p.vdb -cm_log /dev/null -cm_name 3.chip_csr_bit_bash.3512137624 |
| Directory | /workspace/3.chip_csr_bit_bash/latest |
| Test location | /workspace/coverage/cover_reg_top/3.chip_csr_hw_reset.3195778801 |
| Short name | T129 |
| Test name | |
| Test status | |
| Simulation time | 6383792198 ps |
| CPU time | 436.63 seconds |
| Started | Jun 23 07:21:19 PM PDT 24 |
| Finished | Jun 23 07:28:36 PM PDT 24 |
| Peak memory | 659012 kb |
| Host | smart-f542ab77-0033-40ff-9bac-13baadba96fc |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3195778801 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.chip_csr_hw_r eset.3195778801 |
| Directory | /workspace/3.chip_csr_hw_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/3.chip_csr_rw.1517352705 |
| Short name | T1885 |
| Test name | |
| Test status | |
| Simulation time | 4583941388 ps |
| CPU time | 342.59 seconds |
| Started | Jun 23 07:21:21 PM PDT 24 |
| Finished | Jun 23 07:27:04 PM PDT 24 |
| Peak memory | 595304 kb |
| Host | smart-1aa44a2e-c1de-4054-a79f-656f7011710d |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1517352705 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.chip_csr_rw.1517352705 |
| Directory | /workspace/3.chip_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/3.chip_tl_errors.965284672 |
| Short name | T2865 |
| Test name | |
| Test status | |
| Simulation time | 5539731120 ps |
| CPU time | 483.2 seconds |
| Started | Jun 23 07:21:31 PM PDT 24 |
| Finished | Jun 23 07:29:35 PM PDT 24 |
| Peak memory | 597480 kb |
| Host | smart-64143f29-0421-4340-8340-7598a2d789f5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=965284672 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.chip_tl_errors.965284672 |
| Directory | /workspace/3.chip_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/3.xbar_access_same_device.2706956985 |
| Short name | T863 |
| Test name | |
| Test status | |
| Simulation time | 1750554849 ps |
| CPU time | 66.76 seconds |
| Started | Jun 23 07:21:59 PM PDT 24 |
| Finished | Jun 23 07:23:06 PM PDT 24 |
| Peak memory | 574100 kb |
| Host | smart-246a40d0-c112-4b9f-ad0c-e1b64f7752fa |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2706956985 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.xbar_access_same_device. 2706956985 |
| Directory | /workspace/3.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/3.xbar_error_and_unmapped_addr.3642412976 |
| Short name | T2067 |
| Test name | |
| Test status | |
| Simulation time | 641453738 ps |
| CPU time | 28.57 seconds |
| Started | Jun 23 07:21:30 PM PDT 24 |
| Finished | Jun 23 07:21:59 PM PDT 24 |
| Peak memory | 573652 kb |
| Host | smart-ade5501e-0c9e-45f6-8591-4b561ff9f996 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3642412976 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.xbar_error_and_unmapped_addr .3642412976 |
| Directory | /workspace/3.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/3.xbar_error_random.2958356673 |
| Short name | T1932 |
| Test name | |
| Test status | |
| Simulation time | 406979236 ps |
| CPU time | 34.92 seconds |
| Started | Jun 23 07:21:22 PM PDT 24 |
| Finished | Jun 23 07:21:57 PM PDT 24 |
| Peak memory | 573732 kb |
| Host | smart-1bffa42e-faf4-4968-8303-27ae1a4447ea |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2958356673 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.xbar_error_random.2958356673 |
| Directory | /workspace/3.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/3.xbar_random.1149115463 |
| Short name | T1828 |
| Test name | |
| Test status | |
| Simulation time | 598718950 ps |
| CPU time | 22.8 seconds |
| Started | Jun 23 07:21:25 PM PDT 24 |
| Finished | Jun 23 07:21:48 PM PDT 24 |
| Peak memory | 574076 kb |
| Host | smart-e3124ba7-efe0-4299-97ec-1701bb03b03a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1149115463 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.xbar_random.1149115463 |
| Directory | /workspace/3.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/3.xbar_random_large_delays.747737979 |
| Short name | T2244 |
| Test name | |
| Test status | |
| Simulation time | 71195736976 ps |
| CPU time | 703.02 seconds |
| Started | Jun 23 07:21:19 PM PDT 24 |
| Finished | Jun 23 07:33:02 PM PDT 24 |
| Peak memory | 574204 kb |
| Host | smart-25209ddc-42a5-4204-a9d5-c1ef75806213 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=747737979 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.xbar_random_large_delays.747737979 |
| Directory | /workspace/3.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/3.xbar_random_slow_rsp.1261330924 |
| Short name | T2009 |
| Test name | |
| Test status | |
| Simulation time | 66777603018 ps |
| CPU time | 995.74 seconds |
| Started | Jun 23 07:21:25 PM PDT 24 |
| Finished | Jun 23 07:38:01 PM PDT 24 |
| Peak memory | 573508 kb |
| Host | smart-49bd58fd-3938-4b84-be0c-30731568c030 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1261330924 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.xbar_random_slow_rsp.1261330924 |
| Directory | /workspace/3.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/3.xbar_random_zero_delays.2816406707 |
| Short name | T1596 |
| Test name | |
| Test status | |
| Simulation time | 259619468 ps |
| CPU time | 20.65 seconds |
| Started | Jun 23 07:21:31 PM PDT 24 |
| Finished | Jun 23 07:21:52 PM PDT 24 |
| Peak memory | 574064 kb |
| Host | smart-ed4d0fec-5a6b-4b3d-acc1-417d18b97a1a |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2816406707 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.xbar_random_zero_dela ys.2816406707 |
| Directory | /workspace/3.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/3.xbar_same_source.1160378020 |
| Short name | T1524 |
| Test name | |
| Test status | |
| Simulation time | 318787270 ps |
| CPU time | 25.49 seconds |
| Started | Jun 23 07:21:21 PM PDT 24 |
| Finished | Jun 23 07:21:47 PM PDT 24 |
| Peak memory | 573404 kb |
| Host | smart-8ea5f806-c2fe-4041-9280-4a36e1d04753 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1160378020 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.xbar_same_source.1160378020 |
| Directory | /workspace/3.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/3.xbar_smoke.816365928 |
| Short name | T2812 |
| Test name | |
| Test status | |
| Simulation time | 134171636 ps |
| CPU time | 7.32 seconds |
| Started | Jun 23 07:21:21 PM PDT 24 |
| Finished | Jun 23 07:21:29 PM PDT 24 |
| Peak memory | 565800 kb |
| Host | smart-678adb85-ea38-4f0d-b144-cccefced01f9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=816365928 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.xbar_smoke.816365928 |
| Directory | /workspace/3.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/3.xbar_smoke_large_delays.1941536579 |
| Short name | T1702 |
| Test name | |
| Test status | |
| Simulation time | 8261854689 ps |
| CPU time | 83.51 seconds |
| Started | Jun 23 07:21:21 PM PDT 24 |
| Finished | Jun 23 07:22:44 PM PDT 24 |
| Peak memory | 565920 kb |
| Host | smart-2fad7067-b031-49b7-9371-a9f192aed5eb |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1941536579 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.xbar_smoke_large_delays.1941536579 |
| Directory | /workspace/3.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/3.xbar_smoke_slow_rsp.1665373783 |
| Short name | T2338 |
| Test name | |
| Test status | |
| Simulation time | 5062580090 ps |
| CPU time | 88.67 seconds |
| Started | Jun 23 07:21:17 PM PDT 24 |
| Finished | Jun 23 07:22:46 PM PDT 24 |
| Peak memory | 565924 kb |
| Host | smart-22f2c840-855e-488a-bb70-6960c2b2ecbe |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1665373783 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.xbar_smoke_slow_rsp.1665373783 |
| Directory | /workspace/3.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/3.xbar_smoke_zero_delays.2259592337 |
| Short name | T2049 |
| Test name | |
| Test status | |
| Simulation time | 41435131 ps |
| CPU time | 6.29 seconds |
| Started | Jun 23 07:21:18 PM PDT 24 |
| Finished | Jun 23 07:21:25 PM PDT 24 |
| Peak memory | 565472 kb |
| Host | smart-27a3ce8c-d74c-4059-be57-8b9b9d1677c6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2259592337 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.xbar_smoke_zero_delays .2259592337 |
| Directory | /workspace/3.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/3.xbar_stress_all.3741881062 |
| Short name | T2614 |
| Test name | |
| Test status | |
| Simulation time | 223334251 ps |
| CPU time | 19.14 seconds |
| Started | Jun 23 07:21:16 PM PDT 24 |
| Finished | Jun 23 07:21:36 PM PDT 24 |
| Peak memory | 573448 kb |
| Host | smart-e061d829-028c-46fc-bf08-56be0fcc1013 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3741881062 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.xbar_stress_all.3741881062 |
| Directory | /workspace/3.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/3.xbar_stress_all_with_error.954662617 |
| Short name | T1400 |
| Test name | |
| Test status | |
| Simulation time | 10725848302 ps |
| CPU time | 374.77 seconds |
| Started | Jun 23 07:21:19 PM PDT 24 |
| Finished | Jun 23 07:27:34 PM PDT 24 |
| Peak memory | 574284 kb |
| Host | smart-21646ad2-d850-4f37-8f4d-a9079036a408 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=954662617 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.xbar_stress_all_with_error.954662617 |
| Directory | /workspace/3.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/3.xbar_stress_all_with_reset_error.1343252144 |
| Short name | T1716 |
| Test name | |
| Test status | |
| Simulation time | 300730357 ps |
| CPU time | 85.25 seconds |
| Started | Jun 23 07:21:20 PM PDT 24 |
| Finished | Jun 23 07:22:46 PM PDT 24 |
| Peak memory | 577352 kb |
| Host | smart-d016bfbd-7b36-4383-a088-bc69445d63b2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1343252144 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.xbar_stress_all _with_reset_error.1343252144 |
| Directory | /workspace/3.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/3.xbar_unmapped_addr.528183417 |
| Short name | T2849 |
| Test name | |
| Test status | |
| Simulation time | 1501638989 ps |
| CPU time | 62.24 seconds |
| Started | Jun 23 07:21:22 PM PDT 24 |
| Finished | Jun 23 07:22:25 PM PDT 24 |
| Peak memory | 574180 kb |
| Host | smart-249f063d-eb0a-40f3-8510-79ef503c6810 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=528183417 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.xbar_unmapped_addr.528183417 |
| Directory | /workspace/3.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/30.xbar_access_same_device.633157652 |
| Short name | T2267 |
| Test name | |
| Test status | |
| Simulation time | 234779517 ps |
| CPU time | 30.97 seconds |
| Started | Jun 23 07:28:45 PM PDT 24 |
| Finished | Jun 23 07:29:16 PM PDT 24 |
| Peak memory | 574008 kb |
| Host | smart-8f803596-c91a-4d41-8fa0-b5eb5327b032 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=633157652 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.xbar_access_same_device. 633157652 |
| Directory | /workspace/30.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/30.xbar_access_same_device_slow_rsp.3613505192 |
| Short name | T2700 |
| Test name | |
| Test status | |
| Simulation time | 134468394887 ps |
| CPU time | 2563.9 seconds |
| Started | Jun 23 07:28:47 PM PDT 24 |
| Finished | Jun 23 08:11:32 PM PDT 24 |
| Peak memory | 574288 kb |
| Host | smart-8a0c769a-a1c8-442b-874e-8c317152fcc1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3613505192 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.xbar_access_same_ device_slow_rsp.3613505192 |
| Directory | /workspace/30.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/30.xbar_error_and_unmapped_addr.1086409310 |
| Short name | T2727 |
| Test name | |
| Test status | |
| Simulation time | 245646192 ps |
| CPU time | 24.03 seconds |
| Started | Jun 23 07:28:55 PM PDT 24 |
| Finished | Jun 23 07:29:20 PM PDT 24 |
| Peak memory | 573752 kb |
| Host | smart-79f1497f-df36-4c8f-8791-209bf116a406 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1086409310 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.xbar_error_and_unmapped_add r.1086409310 |
| Directory | /workspace/30.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/30.xbar_error_random.1092922606 |
| Short name | T1543 |
| Test name | |
| Test status | |
| Simulation time | 492102449 ps |
| CPU time | 41.46 seconds |
| Started | Jun 23 07:28:45 PM PDT 24 |
| Finished | Jun 23 07:29:27 PM PDT 24 |
| Peak memory | 573364 kb |
| Host | smart-7e6cda22-ca08-4293-9e8e-3208d0bcc453 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1092922606 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.xbar_error_random.1092922606 |
| Directory | /workspace/30.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/30.xbar_random.2455001872 |
| Short name | T608 |
| Test name | |
| Test status | |
| Simulation time | 1336106333 ps |
| CPU time | 49.91 seconds |
| Started | Jun 23 07:28:43 PM PDT 24 |
| Finished | Jun 23 07:29:33 PM PDT 24 |
| Peak memory | 574088 kb |
| Host | smart-055e944f-6858-4306-8bfe-604f7d79a299 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2455001872 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.xbar_random.2455001872 |
| Directory | /workspace/30.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/30.xbar_random_large_delays.2492906764 |
| Short name | T483 |
| Test name | |
| Test status | |
| Simulation time | 105926410547 ps |
| CPU time | 1034.26 seconds |
| Started | Jun 23 07:28:43 PM PDT 24 |
| Finished | Jun 23 07:45:58 PM PDT 24 |
| Peak memory | 574228 kb |
| Host | smart-d5ff52e0-ee1b-47bf-b31b-074967ea7541 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2492906764 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.xbar_random_large_delays.2492906764 |
| Directory | /workspace/30.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/30.xbar_random_slow_rsp.1399039477 |
| Short name | T2281 |
| Test name | |
| Test status | |
| Simulation time | 68880493696 ps |
| CPU time | 1164.43 seconds |
| Started | Jun 23 07:28:47 PM PDT 24 |
| Finished | Jun 23 07:48:12 PM PDT 24 |
| Peak memory | 574216 kb |
| Host | smart-c63ab395-54dd-4338-9ecd-28953bae9fde |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1399039477 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.xbar_random_slow_rsp.1399039477 |
| Directory | /workspace/30.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/30.xbar_random_zero_delays.3906100448 |
| Short name | T2620 |
| Test name | |
| Test status | |
| Simulation time | 604982404 ps |
| CPU time | 48.15 seconds |
| Started | Jun 23 07:28:43 PM PDT 24 |
| Finished | Jun 23 07:29:32 PM PDT 24 |
| Peak memory | 574100 kb |
| Host | smart-e5ceac33-a2bf-4926-97ab-4b5e7a0c1c2a |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3906100448 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.xbar_random_zero_del ays.3906100448 |
| Directory | /workspace/30.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/30.xbar_same_source.358412562 |
| Short name | T2558 |
| Test name | |
| Test status | |
| Simulation time | 479715498 ps |
| CPU time | 35.39 seconds |
| Started | Jun 23 07:28:43 PM PDT 24 |
| Finished | Jun 23 07:29:18 PM PDT 24 |
| Peak memory | 573920 kb |
| Host | smart-3eddb421-2d74-413f-9fe4-785439596200 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=358412562 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.xbar_same_source.358412562 |
| Directory | /workspace/30.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/30.xbar_smoke.4263003473 |
| Short name | T2699 |
| Test name | |
| Test status | |
| Simulation time | 55444749 ps |
| CPU time | 6.94 seconds |
| Started | Jun 23 07:28:41 PM PDT 24 |
| Finished | Jun 23 07:28:48 PM PDT 24 |
| Peak memory | 565780 kb |
| Host | smart-c19498f1-70ff-4180-8fd0-0402ea9b2fa7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4263003473 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.xbar_smoke.4263003473 |
| Directory | /workspace/30.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/30.xbar_smoke_large_delays.1836436266 |
| Short name | T1746 |
| Test name | |
| Test status | |
| Simulation time | 8646295621 ps |
| CPU time | 88.36 seconds |
| Started | Jun 23 07:28:44 PM PDT 24 |
| Finished | Jun 23 07:30:13 PM PDT 24 |
| Peak memory | 565924 kb |
| Host | smart-91d13ade-7816-4f30-ad2e-13809eeffe35 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1836436266 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.xbar_smoke_large_delays.1836436266 |
| Directory | /workspace/30.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/30.xbar_smoke_slow_rsp.1613458502 |
| Short name | T1422 |
| Test name | |
| Test status | |
| Simulation time | 5952915095 ps |
| CPU time | 107.55 seconds |
| Started | Jun 23 07:28:43 PM PDT 24 |
| Finished | Jun 23 07:30:31 PM PDT 24 |
| Peak memory | 565240 kb |
| Host | smart-3c185f64-ab7f-4d9b-aa0d-9256db9ee5e2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1613458502 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.xbar_smoke_slow_rsp.1613458502 |
| Directory | /workspace/30.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/30.xbar_smoke_zero_delays.722866707 |
| Short name | T2596 |
| Test name | |
| Test status | |
| Simulation time | 54266701 ps |
| CPU time | 6.83 seconds |
| Started | Jun 23 07:28:40 PM PDT 24 |
| Finished | Jun 23 07:28:47 PM PDT 24 |
| Peak memory | 565500 kb |
| Host | smart-442c07f6-c98e-491e-aeb6-b31e4c32c085 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=722866707 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.xbar_smoke_zero_delays .722866707 |
| Directory | /workspace/30.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/30.xbar_stress_all.470805256 |
| Short name | T1861 |
| Test name | |
| Test status | |
| Simulation time | 3576550796 ps |
| CPU time | 283.76 seconds |
| Started | Jun 23 07:28:59 PM PDT 24 |
| Finished | Jun 23 07:33:43 PM PDT 24 |
| Peak memory | 574280 kb |
| Host | smart-6ddc5d32-fe4f-4ce2-afad-22eb588c0fb4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=470805256 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.xbar_stress_all.470805256 |
| Directory | /workspace/30.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/30.xbar_stress_all_with_error.1047563298 |
| Short name | T2249 |
| Test name | |
| Test status | |
| Simulation time | 2256452769 ps |
| CPU time | 215.73 seconds |
| Started | Jun 23 07:28:54 PM PDT 24 |
| Finished | Jun 23 07:32:30 PM PDT 24 |
| Peak memory | 574360 kb |
| Host | smart-8563b836-8862-463a-b033-90f72b83ab1f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1047563298 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.xbar_stress_all_with_error.1047563298 |
| Directory | /workspace/30.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/30.xbar_stress_all_with_reset_error.631601373 |
| Short name | T884 |
| Test name | |
| Test status | |
| Simulation time | 589184481 ps |
| CPU time | 195.75 seconds |
| Started | Jun 23 07:28:54 PM PDT 24 |
| Finished | Jun 23 07:32:10 PM PDT 24 |
| Peak memory | 576312 kb |
| Host | smart-7612c8f4-26ac-48ec-acab-dc7cfcde65b2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=631601373 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.xbar_stress_all _with_reset_error.631601373 |
| Directory | /workspace/30.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/30.xbar_unmapped_addr.3726334814 |
| Short name | T1833 |
| Test name | |
| Test status | |
| Simulation time | 1092176849 ps |
| CPU time | 42.59 seconds |
| Started | Jun 23 07:28:55 PM PDT 24 |
| Finished | Jun 23 07:29:38 PM PDT 24 |
| Peak memory | 574120 kb |
| Host | smart-6d67fe7d-4539-476e-ac26-d215a3b493f5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3726334814 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.xbar_unmapped_addr.3726334814 |
| Directory | /workspace/30.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/31.xbar_access_same_device.1997982386 |
| Short name | T848 |
| Test name | |
| Test status | |
| Simulation time | 508433163 ps |
| CPU time | 44.66 seconds |
| Started | Jun 23 07:29:00 PM PDT 24 |
| Finished | Jun 23 07:29:45 PM PDT 24 |
| Peak memory | 574068 kb |
| Host | smart-1ad3e8fb-52a4-4644-8058-75271ad38e07 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1997982386 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.xbar_access_same_device .1997982386 |
| Directory | /workspace/31.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/31.xbar_error_and_unmapped_addr.1600985016 |
| Short name | T1999 |
| Test name | |
| Test status | |
| Simulation time | 705331935 ps |
| CPU time | 32.43 seconds |
| Started | Jun 23 07:29:00 PM PDT 24 |
| Finished | Jun 23 07:29:33 PM PDT 24 |
| Peak memory | 573720 kb |
| Host | smart-ff1be982-923e-4c5d-a7ea-fd78826d6d5a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1600985016 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.xbar_error_and_unmapped_add r.1600985016 |
| Directory | /workspace/31.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/31.xbar_error_random.3680057147 |
| Short name | T2619 |
| Test name | |
| Test status | |
| Simulation time | 1180533663 ps |
| CPU time | 46.61 seconds |
| Started | Jun 23 07:29:00 PM PDT 24 |
| Finished | Jun 23 07:29:47 PM PDT 24 |
| Peak memory | 573332 kb |
| Host | smart-bcc3ce2e-6358-42cd-b8e1-b3557dd85018 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3680057147 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.xbar_error_random.3680057147 |
| Directory | /workspace/31.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/31.xbar_random.2741738029 |
| Short name | T2505 |
| Test name | |
| Test status | |
| Simulation time | 2174669742 ps |
| CPU time | 75.68 seconds |
| Started | Jun 23 07:29:01 PM PDT 24 |
| Finished | Jun 23 07:30:17 PM PDT 24 |
| Peak memory | 574288 kb |
| Host | smart-7fcf6595-cf7c-4280-bf9b-54c5e666ec11 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2741738029 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.xbar_random.2741738029 |
| Directory | /workspace/31.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/31.xbar_random_large_delays.330632301 |
| Short name | T1791 |
| Test name | |
| Test status | |
| Simulation time | 106014393098 ps |
| CPU time | 1085.56 seconds |
| Started | Jun 23 07:28:58 PM PDT 24 |
| Finished | Jun 23 07:47:04 PM PDT 24 |
| Peak memory | 574212 kb |
| Host | smart-b25e6a36-465a-4545-9bdf-b21292c62b3f |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=330632301 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.xbar_random_large_delays.330632301 |
| Directory | /workspace/31.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/31.xbar_random_slow_rsp.3226178640 |
| Short name | T2352 |
| Test name | |
| Test status | |
| Simulation time | 20002783715 ps |
| CPU time | 314.03 seconds |
| Started | Jun 23 07:29:01 PM PDT 24 |
| Finished | Jun 23 07:34:15 PM PDT 24 |
| Peak memory | 574184 kb |
| Host | smart-8a3ce27b-c321-411e-9abf-ac2c5a3cb5ea |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3226178640 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.xbar_random_slow_rsp.3226178640 |
| Directory | /workspace/31.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/31.xbar_random_zero_delays.3068670698 |
| Short name | T2864 |
| Test name | |
| Test status | |
| Simulation time | 474277732 ps |
| CPU time | 44.43 seconds |
| Started | Jun 23 07:28:59 PM PDT 24 |
| Finished | Jun 23 07:29:44 PM PDT 24 |
| Peak memory | 573440 kb |
| Host | smart-727ba6c4-9324-4678-9be1-a3fe11b68001 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3068670698 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.xbar_random_zero_del ays.3068670698 |
| Directory | /workspace/31.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/31.xbar_same_source.1600055000 |
| Short name | T1730 |
| Test name | |
| Test status | |
| Simulation time | 1307843401 ps |
| CPU time | 42.17 seconds |
| Started | Jun 23 07:28:59 PM PDT 24 |
| Finished | Jun 23 07:29:41 PM PDT 24 |
| Peak memory | 573312 kb |
| Host | smart-f5561904-2808-4b20-ac3a-aadf199d1551 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1600055000 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.xbar_same_source.1600055000 |
| Directory | /workspace/31.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/31.xbar_smoke.2193573191 |
| Short name | T2227 |
| Test name | |
| Test status | |
| Simulation time | 175957822 ps |
| CPU time | 7.74 seconds |
| Started | Jun 23 07:28:53 PM PDT 24 |
| Finished | Jun 23 07:29:02 PM PDT 24 |
| Peak memory | 565464 kb |
| Host | smart-e25563e7-b1d6-4982-b2a8-eddeb355d0a6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2193573191 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.xbar_smoke.2193573191 |
| Directory | /workspace/31.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/31.xbar_smoke_large_delays.1478574947 |
| Short name | T2538 |
| Test name | |
| Test status | |
| Simulation time | 7031339021 ps |
| CPU time | 77.57 seconds |
| Started | Jun 23 07:28:59 PM PDT 24 |
| Finished | Jun 23 07:30:17 PM PDT 24 |
| Peak memory | 565188 kb |
| Host | smart-c2770bdc-2f19-4dcb-b2e0-40c698a62102 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1478574947 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.xbar_smoke_large_delays.1478574947 |
| Directory | /workspace/31.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/31.xbar_smoke_slow_rsp.2921057267 |
| Short name | T1703 |
| Test name | |
| Test status | |
| Simulation time | 6281083438 ps |
| CPU time | 111.99 seconds |
| Started | Jun 23 07:29:02 PM PDT 24 |
| Finished | Jun 23 07:30:54 PM PDT 24 |
| Peak memory | 565944 kb |
| Host | smart-2ee276bf-058c-4de0-968d-82bd239c8ae6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2921057267 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.xbar_smoke_slow_rsp.2921057267 |
| Directory | /workspace/31.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/31.xbar_smoke_zero_delays.3620083934 |
| Short name | T2384 |
| Test name | |
| Test status | |
| Simulation time | 47190518 ps |
| CPU time | 6.35 seconds |
| Started | Jun 23 07:28:55 PM PDT 24 |
| Finished | Jun 23 07:29:02 PM PDT 24 |
| Peak memory | 565484 kb |
| Host | smart-b8ec536a-6376-48b9-97d5-48235d09a3ac |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3620083934 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.xbar_smoke_zero_delay s.3620083934 |
| Directory | /workspace/31.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/31.xbar_stress_all.1372663600 |
| Short name | T2682 |
| Test name | |
| Test status | |
| Simulation time | 2650617450 ps |
| CPU time | 227.62 seconds |
| Started | Jun 23 07:29:03 PM PDT 24 |
| Finished | Jun 23 07:32:50 PM PDT 24 |
| Peak memory | 574284 kb |
| Host | smart-b52af2bf-1a03-4622-b44a-def3368a34c5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1372663600 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.xbar_stress_all.1372663600 |
| Directory | /workspace/31.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/31.xbar_stress_all_with_error.150853242 |
| Short name | T2097 |
| Test name | |
| Test status | |
| Simulation time | 3582679756 ps |
| CPU time | 127.35 seconds |
| Started | Jun 23 07:29:16 PM PDT 24 |
| Finished | Jun 23 07:31:24 PM PDT 24 |
| Peak memory | 573576 kb |
| Host | smart-aeacae02-0600-4b74-ab26-c6c24f1c7558 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=150853242 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.xbar_stress_all_with_error.150853242 |
| Directory | /workspace/31.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/31.xbar_stress_all_with_rand_reset.245266010 |
| Short name | T2175 |
| Test name | |
| Test status | |
| Simulation time | 2022453167 ps |
| CPU time | 319.36 seconds |
| Started | Jun 23 07:29:05 PM PDT 24 |
| Finished | Jun 23 07:34:24 PM PDT 24 |
| Peak memory | 574180 kb |
| Host | smart-79241ff2-59bf-4ace-9de5-5d1b8de0ca40 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=245266010 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_res et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.xbar_stress_all_ with_rand_reset.245266010 |
| Directory | /workspace/31.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/31.xbar_stress_all_with_reset_error.2583520406 |
| Short name | T2035 |
| Test name | |
| Test status | |
| Simulation time | 40150309 ps |
| CPU time | 12.68 seconds |
| Started | Jun 23 07:29:15 PM PDT 24 |
| Finished | Jun 23 07:29:28 PM PDT 24 |
| Peak memory | 566012 kb |
| Host | smart-6fe53734-9a31-43da-a04a-7091eea2f675 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2583520406 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.xbar_stress_al l_with_reset_error.2583520406 |
| Directory | /workspace/31.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/31.xbar_unmapped_addr.3228302750 |
| Short name | T1368 |
| Test name | |
| Test status | |
| Simulation time | 86769143 ps |
| CPU time | 12.74 seconds |
| Started | Jun 23 07:29:02 PM PDT 24 |
| Finished | Jun 23 07:29:15 PM PDT 24 |
| Peak memory | 573420 kb |
| Host | smart-3245823f-2016-4c16-bd8e-51a4996fbff9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3228302750 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.xbar_unmapped_addr.3228302750 |
| Directory | /workspace/31.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/32.xbar_access_same_device.802340323 |
| Short name | T2555 |
| Test name | |
| Test status | |
| Simulation time | 2164505207 ps |
| CPU time | 88.93 seconds |
| Started | Jun 23 07:29:17 PM PDT 24 |
| Finished | Jun 23 07:30:46 PM PDT 24 |
| Peak memory | 574196 kb |
| Host | smart-fc4793d9-88bf-4886-baf1-f3ab00e7b779 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=802340323 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.xbar_access_same_device. 802340323 |
| Directory | /workspace/32.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/32.xbar_access_same_device_slow_rsp.2525024392 |
| Short name | T2344 |
| Test name | |
| Test status | |
| Simulation time | 18356281280 ps |
| CPU time | 320.49 seconds |
| Started | Jun 23 07:29:16 PM PDT 24 |
| Finished | Jun 23 07:34:36 PM PDT 24 |
| Peak memory | 574228 kb |
| Host | smart-db2af118-7252-433d-a8d3-520eb716f24a |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2525024392 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.xbar_access_same_ device_slow_rsp.2525024392 |
| Directory | /workspace/32.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/32.xbar_error_and_unmapped_addr.1862435264 |
| Short name | T2663 |
| Test name | |
| Test status | |
| Simulation time | 261264851 ps |
| CPU time | 13.57 seconds |
| Started | Jun 23 07:29:24 PM PDT 24 |
| Finished | Jun 23 07:29:38 PM PDT 24 |
| Peak memory | 573652 kb |
| Host | smart-3e3e919b-1d93-4236-91d6-b1107879302c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1862435264 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.xbar_error_and_unmapped_add r.1862435264 |
| Directory | /workspace/32.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/32.xbar_error_random.1390442207 |
| Short name | T1717 |
| Test name | |
| Test status | |
| Simulation time | 280179204 ps |
| CPU time | 26.54 seconds |
| Started | Jun 23 07:29:20 PM PDT 24 |
| Finished | Jun 23 07:29:47 PM PDT 24 |
| Peak memory | 573688 kb |
| Host | smart-f5cd986b-1f6e-4a03-a4e1-78f9d5761381 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1390442207 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.xbar_error_random.1390442207 |
| Directory | /workspace/32.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/32.xbar_random.2879287848 |
| Short name | T2830 |
| Test name | |
| Test status | |
| Simulation time | 2306002462 ps |
| CPU time | 86.22 seconds |
| Started | Jun 23 07:29:17 PM PDT 24 |
| Finished | Jun 23 07:30:43 PM PDT 24 |
| Peak memory | 574164 kb |
| Host | smart-a8c8921d-285c-4d97-857a-0143f82e0754 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2879287848 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.xbar_random.2879287848 |
| Directory | /workspace/32.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/32.xbar_random_large_delays.883159785 |
| Short name | T2703 |
| Test name | |
| Test status | |
| Simulation time | 52230244332 ps |
| CPU time | 543.73 seconds |
| Started | Jun 23 07:29:17 PM PDT 24 |
| Finished | Jun 23 07:38:21 PM PDT 24 |
| Peak memory | 574176 kb |
| Host | smart-592d7e22-8f7d-41d0-bec2-5bdec8b22c43 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=883159785 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.xbar_random_large_delays.883159785 |
| Directory | /workspace/32.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/32.xbar_random_slow_rsp.3057746214 |
| Short name | T1555 |
| Test name | |
| Test status | |
| Simulation time | 61724619473 ps |
| CPU time | 1099.27 seconds |
| Started | Jun 23 07:29:18 PM PDT 24 |
| Finished | Jun 23 07:47:39 PM PDT 24 |
| Peak memory | 573600 kb |
| Host | smart-cdd3288f-d262-409f-8f87-926c07aecce3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3057746214 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.xbar_random_slow_rsp.3057746214 |
| Directory | /workspace/32.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/32.xbar_random_zero_delays.1252876259 |
| Short name | T1533 |
| Test name | |
| Test status | |
| Simulation time | 244903466 ps |
| CPU time | 26.48 seconds |
| Started | Jun 23 07:29:17 PM PDT 24 |
| Finished | Jun 23 07:29:44 PM PDT 24 |
| Peak memory | 573408 kb |
| Host | smart-3fa5b2fa-f22b-4ddc-9950-6119aa9a9f4e |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1252876259 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.xbar_random_zero_del ays.1252876259 |
| Directory | /workspace/32.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/32.xbar_same_source.2505837527 |
| Short name | T426 |
| Test name | |
| Test status | |
| Simulation time | 1137611142 ps |
| CPU time | 34.44 seconds |
| Started | Jun 23 07:29:16 PM PDT 24 |
| Finished | Jun 23 07:29:51 PM PDT 24 |
| Peak memory | 574016 kb |
| Host | smart-a1c22d27-b6ed-4853-9446-eb62c517c271 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2505837527 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.xbar_same_source.2505837527 |
| Directory | /workspace/32.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/32.xbar_smoke.3290560460 |
| Short name | T1568 |
| Test name | |
| Test status | |
| Simulation time | 227593466 ps |
| CPU time | 9.63 seconds |
| Started | Jun 23 07:29:17 PM PDT 24 |
| Finished | Jun 23 07:29:27 PM PDT 24 |
| Peak memory | 565744 kb |
| Host | smart-3b638a93-f132-4058-a772-a853addd0edd |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3290560460 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.xbar_smoke.3290560460 |
| Directory | /workspace/32.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/32.xbar_smoke_large_delays.2002706660 |
| Short name | T2576 |
| Test name | |
| Test status | |
| Simulation time | 10827902234 ps |
| CPU time | 106.92 seconds |
| Started | Jun 23 07:29:17 PM PDT 24 |
| Finished | Jun 23 07:31:04 PM PDT 24 |
| Peak memory | 565904 kb |
| Host | smart-e3733900-3769-4393-b455-7c4909ccf00e |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2002706660 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.xbar_smoke_large_delays.2002706660 |
| Directory | /workspace/32.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/32.xbar_smoke_slow_rsp.2100603015 |
| Short name | T2418 |
| Test name | |
| Test status | |
| Simulation time | 3700525553 ps |
| CPU time | 59.76 seconds |
| Started | Jun 23 07:29:15 PM PDT 24 |
| Finished | Jun 23 07:30:15 PM PDT 24 |
| Peak memory | 565900 kb |
| Host | smart-0eab153e-e8cf-4bb0-9df7-b248bb7d7096 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2100603015 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.xbar_smoke_slow_rsp.2100603015 |
| Directory | /workspace/32.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/32.xbar_smoke_zero_delays.1673989316 |
| Short name | T1621 |
| Test name | |
| Test status | |
| Simulation time | 43409299 ps |
| CPU time | 6.58 seconds |
| Started | Jun 23 07:29:14 PM PDT 24 |
| Finished | Jun 23 07:29:21 PM PDT 24 |
| Peak memory | 565176 kb |
| Host | smart-c3876fcb-2ac5-4de7-9e2d-86724fc74be1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1673989316 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.xbar_smoke_zero_delay s.1673989316 |
| Directory | /workspace/32.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/32.xbar_stress_all.3676545605 |
| Short name | T550 |
| Test name | |
| Test status | |
| Simulation time | 1119810820 ps |
| CPU time | 83.26 seconds |
| Started | Jun 23 07:29:21 PM PDT 24 |
| Finished | Jun 23 07:30:44 PM PDT 24 |
| Peak memory | 573652 kb |
| Host | smart-6994eac2-a4dd-494f-9db1-60c3c1f97557 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3676545605 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.xbar_stress_all.3676545605 |
| Directory | /workspace/32.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/32.xbar_stress_all_with_error.606535315 |
| Short name | T860 |
| Test name | |
| Test status | |
| Simulation time | 9314018849 ps |
| CPU time | 339.51 seconds |
| Started | Jun 23 07:29:19 PM PDT 24 |
| Finished | Jun 23 07:34:58 PM PDT 24 |
| Peak memory | 574380 kb |
| Host | smart-188c56af-6217-4303-873a-ceb0761ba2ff |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=606535315 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.xbar_stress_all_with_error.606535315 |
| Directory | /workspace/32.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/32.xbar_stress_all_with_rand_reset.554748102 |
| Short name | T1585 |
| Test name | |
| Test status | |
| Simulation time | 57398998 ps |
| CPU time | 20.56 seconds |
| Started | Jun 23 07:29:21 PM PDT 24 |
| Finished | Jun 23 07:29:42 PM PDT 24 |
| Peak memory | 574192 kb |
| Host | smart-68623aa2-60b5-4830-b4fd-f0b4f30aecad |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=554748102 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_res et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.xbar_stress_all_ with_rand_reset.554748102 |
| Directory | /workspace/32.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/32.xbar_stress_all_with_reset_error.4205900344 |
| Short name | T2489 |
| Test name | |
| Test status | |
| Simulation time | 102563837 ps |
| CPU time | 22.36 seconds |
| Started | Jun 23 07:29:22 PM PDT 24 |
| Finished | Jun 23 07:29:45 PM PDT 24 |
| Peak memory | 573824 kb |
| Host | smart-3674c10b-f51a-4fc5-9c4d-6d5842b866ff |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4205900344 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.xbar_stress_al l_with_reset_error.4205900344 |
| Directory | /workspace/32.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/32.xbar_unmapped_addr.2638277312 |
| Short name | T1642 |
| Test name | |
| Test status | |
| Simulation time | 678943683 ps |
| CPU time | 30.66 seconds |
| Started | Jun 23 07:29:21 PM PDT 24 |
| Finished | Jun 23 07:29:52 PM PDT 24 |
| Peak memory | 574088 kb |
| Host | smart-8600a908-0584-4cf0-aeb9-be7cf73524ea |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2638277312 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.xbar_unmapped_addr.2638277312 |
| Directory | /workspace/32.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/33.xbar_access_same_device.1278327710 |
| Short name | T2490 |
| Test name | |
| Test status | |
| Simulation time | 416906477 ps |
| CPU time | 19.99 seconds |
| Started | Jun 23 07:29:25 PM PDT 24 |
| Finished | Jun 23 07:29:46 PM PDT 24 |
| Peak memory | 573832 kb |
| Host | smart-4b94044f-51d7-4a23-8ee4-26c50df80fdc |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1278327710 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.xbar_access_same_device .1278327710 |
| Directory | /workspace/33.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/33.xbar_access_same_device_slow_rsp.2466453927 |
| Short name | T879 |
| Test name | |
| Test status | |
| Simulation time | 31912790358 ps |
| CPU time | 513.24 seconds |
| Started | Jun 23 07:29:24 PM PDT 24 |
| Finished | Jun 23 07:37:58 PM PDT 24 |
| Peak memory | 574224 kb |
| Host | smart-6eba1df4-72ef-4bcb-ba69-26a00cf6453d |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2466453927 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.xbar_access_same_ device_slow_rsp.2466453927 |
| Directory | /workspace/33.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/33.xbar_error_and_unmapped_addr.606399546 |
| Short name | T1817 |
| Test name | |
| Test status | |
| Simulation time | 236236362 ps |
| CPU time | 25.06 seconds |
| Started | Jun 23 07:29:30 PM PDT 24 |
| Finished | Jun 23 07:29:55 PM PDT 24 |
| Peak memory | 573348 kb |
| Host | smart-593ae0f2-9769-470f-a622-1474d54204fb |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=606399546 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.xbar_error_and_unmapped_addr .606399546 |
| Directory | /workspace/33.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/33.xbar_error_random.1781835151 |
| Short name | T1675 |
| Test name | |
| Test status | |
| Simulation time | 171917242 ps |
| CPU time | 14.58 seconds |
| Started | Jun 23 07:29:28 PM PDT 24 |
| Finished | Jun 23 07:29:43 PM PDT 24 |
| Peak memory | 573276 kb |
| Host | smart-216a4259-307c-4278-b917-540c8b46f578 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1781835151 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.xbar_error_random.1781835151 |
| Directory | /workspace/33.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/33.xbar_random.1482296546 |
| Short name | T1813 |
| Test name | |
| Test status | |
| Simulation time | 100782099 ps |
| CPU time | 7.05 seconds |
| Started | Jun 23 07:29:23 PM PDT 24 |
| Finished | Jun 23 07:29:30 PM PDT 24 |
| Peak memory | 565716 kb |
| Host | smart-26ad875a-3409-47ac-9dc3-c50619e7229e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1482296546 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.xbar_random.1482296546 |
| Directory | /workspace/33.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/33.xbar_random_large_delays.1885467333 |
| Short name | T467 |
| Test name | |
| Test status | |
| Simulation time | 73376671714 ps |
| CPU time | 760.96 seconds |
| Started | Jun 23 07:29:22 PM PDT 24 |
| Finished | Jun 23 07:42:04 PM PDT 24 |
| Peak memory | 574148 kb |
| Host | smart-10fa6e25-1dc8-416b-b0ec-e64405af0841 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1885467333 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.xbar_random_large_delays.1885467333 |
| Directory | /workspace/33.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/33.xbar_random_slow_rsp.4040520948 |
| Short name | T2453 |
| Test name | |
| Test status | |
| Simulation time | 45891563232 ps |
| CPU time | 749.52 seconds |
| Started | Jun 23 07:29:22 PM PDT 24 |
| Finished | Jun 23 07:41:51 PM PDT 24 |
| Peak memory | 573484 kb |
| Host | smart-56f209f8-61ed-402a-a8dc-ca0bd8051603 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4040520948 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.xbar_random_slow_rsp.4040520948 |
| Directory | /workspace/33.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/33.xbar_random_zero_delays.1958296737 |
| Short name | T572 |
| Test name | |
| Test status | |
| Simulation time | 487044329 ps |
| CPU time | 45.79 seconds |
| Started | Jun 23 07:29:21 PM PDT 24 |
| Finished | Jun 23 07:30:07 PM PDT 24 |
| Peak memory | 574060 kb |
| Host | smart-828349fd-2973-42ef-b933-e70400c81433 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1958296737 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.xbar_random_zero_del ays.1958296737 |
| Directory | /workspace/33.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/33.xbar_same_source.1984328736 |
| Short name | T658 |
| Test name | |
| Test status | |
| Simulation time | 419325608 ps |
| CPU time | 30.51 seconds |
| Started | Jun 23 07:29:26 PM PDT 24 |
| Finished | Jun 23 07:29:57 PM PDT 24 |
| Peak memory | 574112 kb |
| Host | smart-cf6ca4de-359a-4727-b33d-d5d0fe947326 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1984328736 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.xbar_same_source.1984328736 |
| Directory | /workspace/33.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/33.xbar_smoke.3536681310 |
| Short name | T1773 |
| Test name | |
| Test status | |
| Simulation time | 205583787 ps |
| CPU time | 9.45 seconds |
| Started | Jun 23 07:29:24 PM PDT 24 |
| Finished | Jun 23 07:29:33 PM PDT 24 |
| Peak memory | 565176 kb |
| Host | smart-5696c1ef-ef0d-446e-a274-0275e0e4536e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3536681310 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.xbar_smoke.3536681310 |
| Directory | /workspace/33.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/33.xbar_smoke_large_delays.842661234 |
| Short name | T1443 |
| Test name | |
| Test status | |
| Simulation time | 7702260963 ps |
| CPU time | 80.97 seconds |
| Started | Jun 23 07:29:22 PM PDT 24 |
| Finished | Jun 23 07:30:43 PM PDT 24 |
| Peak memory | 565944 kb |
| Host | smart-2b20630c-1a8f-4afd-9f28-8f7fbc3567d0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=842661234 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.xbar_smoke_large_delays.842661234 |
| Directory | /workspace/33.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/33.xbar_smoke_slow_rsp.694693925 |
| Short name | T2065 |
| Test name | |
| Test status | |
| Simulation time | 5645790873 ps |
| CPU time | 94.26 seconds |
| Started | Jun 23 07:29:21 PM PDT 24 |
| Finished | Jun 23 07:30:56 PM PDT 24 |
| Peak memory | 565924 kb |
| Host | smart-0abb4245-d88f-453a-9b75-583911469061 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=694693925 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.xbar_smoke_slow_rsp.694693925 |
| Directory | /workspace/33.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/33.xbar_smoke_zero_delays.2233042930 |
| Short name | T629 |
| Test name | |
| Test status | |
| Simulation time | 41514779 ps |
| CPU time | 5.98 seconds |
| Started | Jun 23 07:29:23 PM PDT 24 |
| Finished | Jun 23 07:29:29 PM PDT 24 |
| Peak memory | 565536 kb |
| Host | smart-62b9fe2a-2f39-4ffa-b645-7fdaa7d32fbd |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2233042930 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.xbar_smoke_zero_delay s.2233042930 |
| Directory | /workspace/33.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/33.xbar_stress_all.4038445431 |
| Short name | T2750 |
| Test name | |
| Test status | |
| Simulation time | 11500113749 ps |
| CPU time | 416.54 seconds |
| Started | Jun 23 07:29:32 PM PDT 24 |
| Finished | Jun 23 07:36:29 PM PDT 24 |
| Peak memory | 574232 kb |
| Host | smart-69342d1b-5a89-4398-bf64-976b08d41d94 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4038445431 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.xbar_stress_all.4038445431 |
| Directory | /workspace/33.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/33.xbar_stress_all_with_error.1444429787 |
| Short name | T855 |
| Test name | |
| Test status | |
| Simulation time | 3236630004 ps |
| CPU time | 123.85 seconds |
| Started | Jun 23 07:29:37 PM PDT 24 |
| Finished | Jun 23 07:31:41 PM PDT 24 |
| Peak memory | 574248 kb |
| Host | smart-1243935d-d5d7-43b5-a1e5-17fdbbe9eed8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1444429787 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.xbar_stress_all_with_error.1444429787 |
| Directory | /workspace/33.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/33.xbar_stress_all_with_reset_error.1444286368 |
| Short name | T1814 |
| Test name | |
| Test status | |
| Simulation time | 4033934633 ps |
| CPU time | 164.71 seconds |
| Started | Jun 23 07:29:37 PM PDT 24 |
| Finished | Jun 23 07:32:22 PM PDT 24 |
| Peak memory | 573864 kb |
| Host | smart-89b50d04-4cab-40f9-b328-96e3299c1e3f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1444286368 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.xbar_stress_al l_with_reset_error.1444286368 |
| Directory | /workspace/33.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/33.xbar_unmapped_addr.50579320 |
| Short name | T1807 |
| Test name | |
| Test status | |
| Simulation time | 1376164462 ps |
| CPU time | 58.72 seconds |
| Started | Jun 23 07:29:31 PM PDT 24 |
| Finished | Jun 23 07:30:30 PM PDT 24 |
| Peak memory | 573444 kb |
| Host | smart-2dbad8c6-a2fd-4baa-8afe-90792c8a9ece |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50579320 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.xbar_unmapped_addr.50579320 |
| Directory | /workspace/33.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/34.xbar_access_same_device.3701518660 |
| Short name | T1815 |
| Test name | |
| Test status | |
| Simulation time | 504090147 ps |
| CPU time | 23.45 seconds |
| Started | Jun 23 07:29:58 PM PDT 24 |
| Finished | Jun 23 07:30:22 PM PDT 24 |
| Peak memory | 574076 kb |
| Host | smart-a9fa9f39-195a-415f-88ef-b174c17e4da6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3701518660 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.xbar_access_same_device .3701518660 |
| Directory | /workspace/34.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/34.xbar_access_same_device_slow_rsp.2270237593 |
| Short name | T2311 |
| Test name | |
| Test status | |
| Simulation time | 96838894007 ps |
| CPU time | 1733.45 seconds |
| Started | Jun 23 07:29:56 PM PDT 24 |
| Finished | Jun 23 07:58:50 PM PDT 24 |
| Peak memory | 573440 kb |
| Host | smart-e2acb074-7792-4049-8291-1c1fa28932a2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2270237593 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.xbar_access_same_ device_slow_rsp.2270237593 |
| Directory | /workspace/34.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/34.xbar_error_and_unmapped_addr.392865054 |
| Short name | T2124 |
| Test name | |
| Test status | |
| Simulation time | 21877945 ps |
| CPU time | 5.45 seconds |
| Started | Jun 23 07:30:03 PM PDT 24 |
| Finished | Jun 23 07:30:08 PM PDT 24 |
| Peak memory | 565524 kb |
| Host | smart-478b83df-bab2-4283-96d4-12017df8ad02 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=392865054 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.xbar_error_and_unmapped_addr .392865054 |
| Directory | /workspace/34.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/34.xbar_error_random.313214589 |
| Short name | T1364 |
| Test name | |
| Test status | |
| Simulation time | 664820038 ps |
| CPU time | 54.37 seconds |
| Started | Jun 23 07:29:59 PM PDT 24 |
| Finished | Jun 23 07:30:53 PM PDT 24 |
| Peak memory | 573676 kb |
| Host | smart-682faeab-f880-4e8b-b47d-7df6a9a5a93f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=313214589 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.xbar_error_random.313214589 |
| Directory | /workspace/34.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/34.xbar_random.1670228239 |
| Short name | T2109 |
| Test name | |
| Test status | |
| Simulation time | 230415838 ps |
| CPU time | 20.91 seconds |
| Started | Jun 23 07:29:38 PM PDT 24 |
| Finished | Jun 23 07:29:59 PM PDT 24 |
| Peak memory | 574084 kb |
| Host | smart-96bc1216-5333-40e3-8fe3-6ef82d729874 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1670228239 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.xbar_random.1670228239 |
| Directory | /workspace/34.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/34.xbar_random_large_delays.2976590733 |
| Short name | T589 |
| Test name | |
| Test status | |
| Simulation time | 20323730132 ps |
| CPU time | 218.48 seconds |
| Started | Jun 23 07:29:57 PM PDT 24 |
| Finished | Jun 23 07:33:36 PM PDT 24 |
| Peak memory | 574216 kb |
| Host | smart-bb8cec4b-78a1-417f-adee-95e41193e28a |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2976590733 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.xbar_random_large_delays.2976590733 |
| Directory | /workspace/34.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/34.xbar_random_slow_rsp.4245019850 |
| Short name | T1929 |
| Test name | |
| Test status | |
| Simulation time | 14195267382 ps |
| CPU time | 241.99 seconds |
| Started | Jun 23 07:29:56 PM PDT 24 |
| Finished | Jun 23 07:33:59 PM PDT 24 |
| Peak memory | 574160 kb |
| Host | smart-889b3650-df66-43a4-a7ea-469db1912748 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4245019850 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.xbar_random_slow_rsp.4245019850 |
| Directory | /workspace/34.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/34.xbar_random_zero_delays.12762631 |
| Short name | T529 |
| Test name | |
| Test status | |
| Simulation time | 423689760 ps |
| CPU time | 41.78 seconds |
| Started | Jun 23 07:29:56 PM PDT 24 |
| Finished | Jun 23 07:30:38 PM PDT 24 |
| Peak memory | 573404 kb |
| Host | smart-b1ae5bcb-3b62-4a13-a227-d408ee6cb1af |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12762631 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.xbar_random_zero_delay s.12762631 |
| Directory | /workspace/34.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/34.xbar_same_source.215789039 |
| Short name | T2601 |
| Test name | |
| Test status | |
| Simulation time | 1215296149 ps |
| CPU time | 40.02 seconds |
| Started | Jun 23 07:29:58 PM PDT 24 |
| Finished | Jun 23 07:30:39 PM PDT 24 |
| Peak memory | 573680 kb |
| Host | smart-556c8131-b329-48b5-a308-383ec5977260 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=215789039 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.xbar_same_source.215789039 |
| Directory | /workspace/34.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/34.xbar_smoke.3425870679 |
| Short name | T1604 |
| Test name | |
| Test status | |
| Simulation time | 200230792 ps |
| CPU time | 9.11 seconds |
| Started | Jun 23 07:29:34 PM PDT 24 |
| Finished | Jun 23 07:29:43 PM PDT 24 |
| Peak memory | 565140 kb |
| Host | smart-59604b07-fa06-41f0-a926-581bf5c06b5b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3425870679 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.xbar_smoke.3425870679 |
| Directory | /workspace/34.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/34.xbar_smoke_large_delays.805383592 |
| Short name | T1566 |
| Test name | |
| Test status | |
| Simulation time | 7681056282 ps |
| CPU time | 77.75 seconds |
| Started | Jun 23 07:29:38 PM PDT 24 |
| Finished | Jun 23 07:30:56 PM PDT 24 |
| Peak memory | 565908 kb |
| Host | smart-c4b2a811-70fd-4424-b652-b94b1dd3be28 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=805383592 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.xbar_smoke_large_delays.805383592 |
| Directory | /workspace/34.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/34.xbar_smoke_slow_rsp.3942343236 |
| Short name | T2487 |
| Test name | |
| Test status | |
| Simulation time | 4425383242 ps |
| CPU time | 75.14 seconds |
| Started | Jun 23 07:29:37 PM PDT 24 |
| Finished | Jun 23 07:30:53 PM PDT 24 |
| Peak memory | 565952 kb |
| Host | smart-e0387ea9-3576-4d19-b876-4d0812ab88eb |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3942343236 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.xbar_smoke_slow_rsp.3942343236 |
| Directory | /workspace/34.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/34.xbar_smoke_zero_delays.2048156156 |
| Short name | T2436 |
| Test name | |
| Test status | |
| Simulation time | 52150706 ps |
| CPU time | 6.33 seconds |
| Started | Jun 23 07:29:36 PM PDT 24 |
| Finished | Jun 23 07:29:43 PM PDT 24 |
| Peak memory | 565576 kb |
| Host | smart-d9c65bab-ffe1-4ac9-a66c-2de784b91eb7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2048156156 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.xbar_smoke_zero_delay s.2048156156 |
| Directory | /workspace/34.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/34.xbar_stress_all.2495332578 |
| Short name | T2004 |
| Test name | |
| Test status | |
| Simulation time | 3056267449 ps |
| CPU time | 282.86 seconds |
| Started | Jun 23 07:30:07 PM PDT 24 |
| Finished | Jun 23 07:34:51 PM PDT 24 |
| Peak memory | 574256 kb |
| Host | smart-c53cfc86-01f4-45e5-8fe0-8f6f4258f38f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2495332578 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.xbar_stress_all.2495332578 |
| Directory | /workspace/34.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/34.xbar_stress_all_with_error.2062076964 |
| Short name | T1785 |
| Test name | |
| Test status | |
| Simulation time | 1235947763 ps |
| CPU time | 102.9 seconds |
| Started | Jun 23 07:30:05 PM PDT 24 |
| Finished | Jun 23 07:31:49 PM PDT 24 |
| Peak memory | 574180 kb |
| Host | smart-ba865745-8977-4a71-a208-7a58de9e38d6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2062076964 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.xbar_stress_all_with_error.2062076964 |
| Directory | /workspace/34.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/34.xbar_stress_all_with_rand_reset.2961898512 |
| Short name | T633 |
| Test name | |
| Test status | |
| Simulation time | 187687192 ps |
| CPU time | 64.47 seconds |
| Started | Jun 23 07:30:04 PM PDT 24 |
| Finished | Jun 23 07:31:08 PM PDT 24 |
| Peak memory | 576296 kb |
| Host | smart-cf357333-56a7-4875-8aac-531356f0c6ab |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2961898512 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.xbar_stress_all _with_rand_reset.2961898512 |
| Directory | /workspace/34.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/34.xbar_stress_all_with_reset_error.3759605439 |
| Short name | T1570 |
| Test name | |
| Test status | |
| Simulation time | 10695983 ps |
| CPU time | 8.57 seconds |
| Started | Jun 23 07:30:10 PM PDT 24 |
| Finished | Jun 23 07:30:19 PM PDT 24 |
| Peak memory | 565592 kb |
| Host | smart-1ff31ba0-7905-41ad-a37e-634e2723d568 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3759605439 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.xbar_stress_al l_with_reset_error.3759605439 |
| Directory | /workspace/34.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/34.xbar_unmapped_addr.3646007354 |
| Short name | T1835 |
| Test name | |
| Test status | |
| Simulation time | 142048580 ps |
| CPU time | 18.48 seconds |
| Started | Jun 23 07:29:57 PM PDT 24 |
| Finished | Jun 23 07:30:16 PM PDT 24 |
| Peak memory | 573372 kb |
| Host | smart-a549d1d7-d2c7-4ab9-987b-57184a73f4ed |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3646007354 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.xbar_unmapped_addr.3646007354 |
| Directory | /workspace/34.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/35.xbar_access_same_device.372585367 |
| Short name | T2224 |
| Test name | |
| Test status | |
| Simulation time | 3192945608 ps |
| CPU time | 128.08 seconds |
| Started | Jun 23 07:30:04 PM PDT 24 |
| Finished | Jun 23 07:32:13 PM PDT 24 |
| Peak memory | 574144 kb |
| Host | smart-114c2db5-ca43-4c84-b8b8-09a4f37c1cfd |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=372585367 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.xbar_access_same_device. 372585367 |
| Directory | /workspace/35.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/35.xbar_access_same_device_slow_rsp.3956238299 |
| Short name | T2325 |
| Test name | |
| Test status | |
| Simulation time | 77086078789 ps |
| CPU time | 1371.02 seconds |
| Started | Jun 23 07:30:10 PM PDT 24 |
| Finished | Jun 23 07:53:01 PM PDT 24 |
| Peak memory | 574192 kb |
| Host | smart-24c6434c-cb57-4488-84ba-f5fd1292132b |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3956238299 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.xbar_access_same_ device_slow_rsp.3956238299 |
| Directory | /workspace/35.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/35.xbar_error_and_unmapped_addr.1284382788 |
| Short name | T1515 |
| Test name | |
| Test status | |
| Simulation time | 290363553 ps |
| CPU time | 29.06 seconds |
| Started | Jun 23 07:30:06 PM PDT 24 |
| Finished | Jun 23 07:30:36 PM PDT 24 |
| Peak memory | 573744 kb |
| Host | smart-8acc6c6b-d953-4124-ab70-4d17142e42f4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1284382788 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.xbar_error_and_unmapped_add r.1284382788 |
| Directory | /workspace/35.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/35.xbar_error_random.3093570066 |
| Short name | T1934 |
| Test name | |
| Test status | |
| Simulation time | 2510783305 ps |
| CPU time | 98.42 seconds |
| Started | Jun 23 07:30:07 PM PDT 24 |
| Finished | Jun 23 07:31:46 PM PDT 24 |
| Peak memory | 573688 kb |
| Host | smart-f7b01efd-1616-45d8-81e0-fa121801d683 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3093570066 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.xbar_error_random.3093570066 |
| Directory | /workspace/35.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/35.xbar_random.4092575053 |
| Short name | T457 |
| Test name | |
| Test status | |
| Simulation time | 606825830 ps |
| CPU time | 50.6 seconds |
| Started | Jun 23 07:30:10 PM PDT 24 |
| Finished | Jun 23 07:31:00 PM PDT 24 |
| Peak memory | 574120 kb |
| Host | smart-a2ab10e1-57ce-41d8-b337-e971a13a13dd |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4092575053 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.xbar_random.4092575053 |
| Directory | /workspace/35.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/35.xbar_random_large_delays.1194015654 |
| Short name | T1779 |
| Test name | |
| Test status | |
| Simulation time | 79893774418 ps |
| CPU time | 893.88 seconds |
| Started | Jun 23 07:30:08 PM PDT 24 |
| Finished | Jun 23 07:45:03 PM PDT 24 |
| Peak memory | 574148 kb |
| Host | smart-c6660c41-a56f-465f-8f3d-6630ee78b7d6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1194015654 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.xbar_random_large_delays.1194015654 |
| Directory | /workspace/35.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/35.xbar_random_slow_rsp.4027322783 |
| Short name | T1756 |
| Test name | |
| Test status | |
| Simulation time | 26919745836 ps |
| CPU time | 430.29 seconds |
| Started | Jun 23 07:30:06 PM PDT 24 |
| Finished | Jun 23 07:37:17 PM PDT 24 |
| Peak memory | 574188 kb |
| Host | smart-b85b0e7d-6a35-4661-95c0-4a33dcc6c280 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4027322783 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.xbar_random_slow_rsp.4027322783 |
| Directory | /workspace/35.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/35.xbar_random_zero_delays.3751251337 |
| Short name | T1535 |
| Test name | |
| Test status | |
| Simulation time | 345338976 ps |
| CPU time | 27.75 seconds |
| Started | Jun 23 07:30:10 PM PDT 24 |
| Finished | Jun 23 07:30:38 PM PDT 24 |
| Peak memory | 574076 kb |
| Host | smart-2009fc5e-d537-4002-84ac-2d7a2ede766c |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3751251337 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.xbar_random_zero_del ays.3751251337 |
| Directory | /workspace/35.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/35.xbar_same_source.1235193845 |
| Short name | T1714 |
| Test name | |
| Test status | |
| Simulation time | 516232833 ps |
| CPU time | 36.61 seconds |
| Started | Jun 23 07:30:05 PM PDT 24 |
| Finished | Jun 23 07:30:42 PM PDT 24 |
| Peak memory | 574080 kb |
| Host | smart-258c0c36-5258-4915-9072-a856c5733de9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1235193845 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.xbar_same_source.1235193845 |
| Directory | /workspace/35.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/35.xbar_smoke.1762300082 |
| Short name | T2002 |
| Test name | |
| Test status | |
| Simulation time | 132804219 ps |
| CPU time | 7.3 seconds |
| Started | Jun 23 07:30:09 PM PDT 24 |
| Finished | Jun 23 07:30:17 PM PDT 24 |
| Peak memory | 565176 kb |
| Host | smart-343661bc-7fd8-44a3-8566-f18c7b86e4c9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1762300082 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.xbar_smoke.1762300082 |
| Directory | /workspace/35.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/35.xbar_smoke_large_delays.4233473663 |
| Short name | T2274 |
| Test name | |
| Test status | |
| Simulation time | 6635904589 ps |
| CPU time | 67.33 seconds |
| Started | Jun 23 07:30:03 PM PDT 24 |
| Finished | Jun 23 07:31:10 PM PDT 24 |
| Peak memory | 565520 kb |
| Host | smart-535ea001-2d9e-44bd-a81f-5e816c9187c3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4233473663 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.xbar_smoke_large_delays.4233473663 |
| Directory | /workspace/35.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/35.xbar_smoke_slow_rsp.198013971 |
| Short name | T576 |
| Test name | |
| Test status | |
| Simulation time | 5155954700 ps |
| CPU time | 78.4 seconds |
| Started | Jun 23 07:30:07 PM PDT 24 |
| Finished | Jun 23 07:31:26 PM PDT 24 |
| Peak memory | 565892 kb |
| Host | smart-1ac6d205-bf8f-4a19-90ce-d847ec721e9e |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=198013971 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.xbar_smoke_slow_rsp.198013971 |
| Directory | /workspace/35.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/35.xbar_smoke_zero_delays.1225751936 |
| Short name | T1462 |
| Test name | |
| Test status | |
| Simulation time | 38470629 ps |
| CPU time | 5.89 seconds |
| Started | Jun 23 07:30:07 PM PDT 24 |
| Finished | Jun 23 07:30:14 PM PDT 24 |
| Peak memory | 565468 kb |
| Host | smart-452f51fd-6a11-45d2-8012-c555a63df420 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1225751936 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.xbar_smoke_zero_delay s.1225751936 |
| Directory | /workspace/35.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/35.xbar_stress_all.2219265791 |
| Short name | T1951 |
| Test name | |
| Test status | |
| Simulation time | 5235190003 ps |
| CPU time | 198.08 seconds |
| Started | Jun 23 07:30:05 PM PDT 24 |
| Finished | Jun 23 07:33:24 PM PDT 24 |
| Peak memory | 574292 kb |
| Host | smart-b96109c6-ebd4-4efd-bce5-b9a958e90f84 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2219265791 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.xbar_stress_all.2219265791 |
| Directory | /workspace/35.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/35.xbar_stress_all_with_error.1067855084 |
| Short name | T2709 |
| Test name | |
| Test status | |
| Simulation time | 1459725795 ps |
| CPU time | 60.94 seconds |
| Started | Jun 23 07:30:03 PM PDT 24 |
| Finished | Jun 23 07:31:05 PM PDT 24 |
| Peak memory | 574144 kb |
| Host | smart-b70c9c71-0315-4773-a8d8-07633e7d057b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1067855084 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.xbar_stress_all_with_error.1067855084 |
| Directory | /workspace/35.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/35.xbar_stress_all_with_rand_reset.1622952323 |
| Short name | T1909 |
| Test name | |
| Test status | |
| Simulation time | 1605784918 ps |
| CPU time | 102.83 seconds |
| Started | Jun 23 07:30:05 PM PDT 24 |
| Finished | Jun 23 07:31:48 PM PDT 24 |
| Peak memory | 574216 kb |
| Host | smart-c3a12c8c-ea4b-454c-98c3-4614aa9e32a1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1622952323 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.xbar_stress_all _with_rand_reset.1622952323 |
| Directory | /workspace/35.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/35.xbar_stress_all_with_reset_error.210443084 |
| Short name | T2296 |
| Test name | |
| Test status | |
| Simulation time | 719487927 ps |
| CPU time | 207.79 seconds |
| Started | Jun 23 07:30:03 PM PDT 24 |
| Finished | Jun 23 07:33:31 PM PDT 24 |
| Peak memory | 574296 kb |
| Host | smart-7141aa54-4c54-484b-a09f-41048d91314e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=210443084 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.xbar_stress_all _with_reset_error.210443084 |
| Directory | /workspace/35.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/35.xbar_unmapped_addr.2031958122 |
| Short name | T2317 |
| Test name | |
| Test status | |
| Simulation time | 1185510984 ps |
| CPU time | 52.15 seconds |
| Started | Jun 23 07:30:07 PM PDT 24 |
| Finished | Jun 23 07:31:00 PM PDT 24 |
| Peak memory | 573500 kb |
| Host | smart-a3c60dac-e088-4162-9ab3-23d57dc32b91 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2031958122 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.xbar_unmapped_addr.2031958122 |
| Directory | /workspace/35.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/36.xbar_access_same_device.919298171 |
| Short name | T2642 |
| Test name | |
| Test status | |
| Simulation time | 1248260786 ps |
| CPU time | 48.44 seconds |
| Started | Jun 23 07:30:09 PM PDT 24 |
| Finished | Jun 23 07:30:58 PM PDT 24 |
| Peak memory | 573872 kb |
| Host | smart-fcdbd1e7-44ac-4e6f-878b-2f00cbfc0c18 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=919298171 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.xbar_access_same_device. 919298171 |
| Directory | /workspace/36.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/36.xbar_access_same_device_slow_rsp.3430175127 |
| Short name | T2347 |
| Test name | |
| Test status | |
| Simulation time | 101088647445 ps |
| CPU time | 1820.65 seconds |
| Started | Jun 23 07:30:07 PM PDT 24 |
| Finished | Jun 23 08:00:29 PM PDT 24 |
| Peak memory | 574228 kb |
| Host | smart-02a19a19-671f-4687-834b-74a67c780343 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3430175127 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.xbar_access_same_ device_slow_rsp.3430175127 |
| Directory | /workspace/36.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/36.xbar_error_and_unmapped_addr.3032404115 |
| Short name | T1707 |
| Test name | |
| Test status | |
| Simulation time | 796258034 ps |
| CPU time | 32.54 seconds |
| Started | Jun 23 07:30:07 PM PDT 24 |
| Finished | Jun 23 07:30:40 PM PDT 24 |
| Peak memory | 573732 kb |
| Host | smart-6bc69305-c421-464a-b9d7-7097b6322a60 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3032404115 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.xbar_error_and_unmapped_add r.3032404115 |
| Directory | /workspace/36.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/36.xbar_error_random.3212306218 |
| Short name | T1787 |
| Test name | |
| Test status | |
| Simulation time | 1376727423 ps |
| CPU time | 50.1 seconds |
| Started | Jun 23 07:30:05 PM PDT 24 |
| Finished | Jun 23 07:30:55 PM PDT 24 |
| Peak memory | 573360 kb |
| Host | smart-027bfb1c-e94f-4a78-8cbc-9a07ee822ad9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3212306218 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.xbar_error_random.3212306218 |
| Directory | /workspace/36.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/36.xbar_random.677820796 |
| Short name | T590 |
| Test name | |
| Test status | |
| Simulation time | 104543626 ps |
| CPU time | 11.69 seconds |
| Started | Jun 23 07:30:03 PM PDT 24 |
| Finished | Jun 23 07:30:15 PM PDT 24 |
| Peak memory | 574108 kb |
| Host | smart-f46b381b-e433-4586-a4d2-96f8a2929507 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=677820796 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.xbar_random.677820796 |
| Directory | /workspace/36.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/36.xbar_random_large_delays.2508865519 |
| Short name | T2107 |
| Test name | |
| Test status | |
| Simulation time | 22560407678 ps |
| CPU time | 229.39 seconds |
| Started | Jun 23 07:30:05 PM PDT 24 |
| Finished | Jun 23 07:33:54 PM PDT 24 |
| Peak memory | 574232 kb |
| Host | smart-d301c473-a77c-4ba8-8c5d-12fc84911034 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2508865519 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.xbar_random_large_delays.2508865519 |
| Directory | /workspace/36.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/36.xbar_random_slow_rsp.535424499 |
| Short name | T2341 |
| Test name | |
| Test status | |
| Simulation time | 4250429274 ps |
| CPU time | 67.64 seconds |
| Started | Jun 23 07:30:04 PM PDT 24 |
| Finished | Jun 23 07:31:12 PM PDT 24 |
| Peak memory | 565276 kb |
| Host | smart-a4323814-d4ea-465e-b2d9-06d794aca847 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=535424499 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.xbar_random_slow_rsp.535424499 |
| Directory | /workspace/36.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/36.xbar_random_zero_delays.2942854733 |
| Short name | T681 |
| Test name | |
| Test status | |
| Simulation time | 478800685 ps |
| CPU time | 47.57 seconds |
| Started | Jun 23 07:30:07 PM PDT 24 |
| Finished | Jun 23 07:30:55 PM PDT 24 |
| Peak memory | 574240 kb |
| Host | smart-c1b1d473-d38b-421f-9cf7-aa5a5f4408cd |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2942854733 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.xbar_random_zero_del ays.2942854733 |
| Directory | /workspace/36.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/36.xbar_same_source.979118442 |
| Short name | T2776 |
| Test name | |
| Test status | |
| Simulation time | 351605998 ps |
| CPU time | 29.74 seconds |
| Started | Jun 23 07:30:06 PM PDT 24 |
| Finished | Jun 23 07:30:36 PM PDT 24 |
| Peak memory | 573392 kb |
| Host | smart-02e54cee-378d-46c3-8f5b-9719833c68c3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=979118442 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.xbar_same_source.979118442 |
| Directory | /workspace/36.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/36.xbar_smoke.917910866 |
| Short name | T2432 |
| Test name | |
| Test status | |
| Simulation time | 50344986 ps |
| CPU time | 6.83 seconds |
| Started | Jun 23 07:30:09 PM PDT 24 |
| Finished | Jun 23 07:30:16 PM PDT 24 |
| Peak memory | 565560 kb |
| Host | smart-e0394a18-3789-4195-a4df-812c91846ee8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=917910866 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.xbar_smoke.917910866 |
| Directory | /workspace/36.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/36.xbar_smoke_large_delays.963709658 |
| Short name | T2092 |
| Test name | |
| Test status | |
| Simulation time | 6714238762 ps |
| CPU time | 72.5 seconds |
| Started | Jun 23 07:30:04 PM PDT 24 |
| Finished | Jun 23 07:31:17 PM PDT 24 |
| Peak memory | 565260 kb |
| Host | smart-30e90b95-8541-4b05-8b95-34c1e3bfbc7b |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=963709658 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.xbar_smoke_large_delays.963709658 |
| Directory | /workspace/36.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/36.xbar_smoke_slow_rsp.714132002 |
| Short name | T599 |
| Test name | |
| Test status | |
| Simulation time | 6032153925 ps |
| CPU time | 104.99 seconds |
| Started | Jun 23 07:30:04 PM PDT 24 |
| Finished | Jun 23 07:31:50 PM PDT 24 |
| Peak memory | 565932 kb |
| Host | smart-8666df92-5bef-46dc-9eff-532015fdd3ff |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=714132002 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.xbar_smoke_slow_rsp.714132002 |
| Directory | /workspace/36.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/36.xbar_smoke_zero_delays.3560787273 |
| Short name | T585 |
| Test name | |
| Test status | |
| Simulation time | 42529164 ps |
| CPU time | 6.27 seconds |
| Started | Jun 23 07:30:06 PM PDT 24 |
| Finished | Jun 23 07:30:13 PM PDT 24 |
| Peak memory | 565540 kb |
| Host | smart-e449d795-c897-4e7c-8d3e-899fb18217bf |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3560787273 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.xbar_smoke_zero_delay s.3560787273 |
| Directory | /workspace/36.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/36.xbar_stress_all.906476575 |
| Short name | T2442 |
| Test name | |
| Test status | |
| Simulation time | 1528863966 ps |
| CPU time | 132.55 seconds |
| Started | Jun 23 07:30:06 PM PDT 24 |
| Finished | Jun 23 07:32:19 PM PDT 24 |
| Peak memory | 574384 kb |
| Host | smart-1fdf0bab-d01c-4fac-9168-08c618dcd01b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=906476575 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.xbar_stress_all.906476575 |
| Directory | /workspace/36.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/36.xbar_stress_all_with_error.1693387461 |
| Short name | T1497 |
| Test name | |
| Test status | |
| Simulation time | 2872946940 ps |
| CPU time | 93.23 seconds |
| Started | Jun 23 07:30:06 PM PDT 24 |
| Finished | Jun 23 07:31:39 PM PDT 24 |
| Peak memory | 573508 kb |
| Host | smart-0200dfaf-e1f2-4951-8472-a9bc57d22c3e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1693387461 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.xbar_stress_all_with_error.1693387461 |
| Directory | /workspace/36.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/36.xbar_stress_all_with_rand_reset.2943205597 |
| Short name | T587 |
| Test name | |
| Test status | |
| Simulation time | 220971315 ps |
| CPU time | 152.94 seconds |
| Started | Jun 23 07:30:07 PM PDT 24 |
| Finished | Jun 23 07:32:41 PM PDT 24 |
| Peak memory | 577296 kb |
| Host | smart-ba13af16-5473-414c-b3f4-f2ab3058997d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2943205597 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.xbar_stress_all _with_rand_reset.2943205597 |
| Directory | /workspace/36.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/36.xbar_stress_all_with_reset_error.3651154735 |
| Short name | T732 |
| Test name | |
| Test status | |
| Simulation time | 13813899026 ps |
| CPU time | 648.77 seconds |
| Started | Jun 23 07:30:09 PM PDT 24 |
| Finished | Jun 23 07:40:58 PM PDT 24 |
| Peak memory | 576428 kb |
| Host | smart-3c65d974-6d67-4650-b973-34e987f0915e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3651154735 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.xbar_stress_al l_with_reset_error.3651154735 |
| Directory | /workspace/36.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/36.xbar_unmapped_addr.235607288 |
| Short name | T2182 |
| Test name | |
| Test status | |
| Simulation time | 1020597265 ps |
| CPU time | 39.97 seconds |
| Started | Jun 23 07:30:06 PM PDT 24 |
| Finished | Jun 23 07:30:47 PM PDT 24 |
| Peak memory | 573480 kb |
| Host | smart-80ae993c-9c0e-4ce7-a126-03c900818024 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=235607288 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.xbar_unmapped_addr.235607288 |
| Directory | /workspace/36.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/37.xbar_access_same_device.4080498239 |
| Short name | T2579 |
| Test name | |
| Test status | |
| Simulation time | 2709983754 ps |
| CPU time | 107.7 seconds |
| Started | Jun 23 07:30:33 PM PDT 24 |
| Finished | Jun 23 07:32:21 PM PDT 24 |
| Peak memory | 574136 kb |
| Host | smart-362e10af-0d60-49a5-b455-676d91027123 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4080498239 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.xbar_access_same_device .4080498239 |
| Directory | /workspace/37.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/37.xbar_access_same_device_slow_rsp.3633273439 |
| Short name | T2646 |
| Test name | |
| Test status | |
| Simulation time | 33860817978 ps |
| CPU time | 587.34 seconds |
| Started | Jun 23 07:30:35 PM PDT 24 |
| Finished | Jun 23 07:40:23 PM PDT 24 |
| Peak memory | 573452 kb |
| Host | smart-acddd3eb-705d-4e2d-b015-761d41360fc2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3633273439 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.xbar_access_same_ device_slow_rsp.3633273439 |
| Directory | /workspace/37.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/37.xbar_error_and_unmapped_addr.1665374438 |
| Short name | T2201 |
| Test name | |
| Test status | |
| Simulation time | 73264620 ps |
| CPU time | 6.52 seconds |
| Started | Jun 23 07:30:42 PM PDT 24 |
| Finished | Jun 23 07:30:49 PM PDT 24 |
| Peak memory | 565400 kb |
| Host | smart-3fc9f223-a499-482f-8edc-c24df204de50 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1665374438 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.xbar_error_and_unmapped_add r.1665374438 |
| Directory | /workspace/37.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/37.xbar_error_random.1301529772 |
| Short name | T2326 |
| Test name | |
| Test status | |
| Simulation time | 2180717736 ps |
| CPU time | 69.67 seconds |
| Started | Jun 23 07:30:41 PM PDT 24 |
| Finished | Jun 23 07:31:51 PM PDT 24 |
| Peak memory | 573788 kb |
| Host | smart-a774e4ce-59fd-474a-8ff1-9b04b201b1db |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1301529772 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.xbar_error_random.1301529772 |
| Directory | /workspace/37.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/37.xbar_random.1301188796 |
| Short name | T1729 |
| Test name | |
| Test status | |
| Simulation time | 1061694462 ps |
| CPU time | 39.37 seconds |
| Started | Jun 23 07:30:36 PM PDT 24 |
| Finished | Jun 23 07:31:16 PM PDT 24 |
| Peak memory | 573396 kb |
| Host | smart-0acd8f22-fbaa-48d1-9c58-72869bafbf00 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1301188796 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.xbar_random.1301188796 |
| Directory | /workspace/37.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/37.xbar_random_large_delays.1531750049 |
| Short name | T652 |
| Test name | |
| Test status | |
| Simulation time | 17451154339 ps |
| CPU time | 180.78 seconds |
| Started | Jun 23 07:30:32 PM PDT 24 |
| Finished | Jun 23 07:33:33 PM PDT 24 |
| Peak memory | 573524 kb |
| Host | smart-8d656adf-61e2-4c72-b078-1cd1bf373a9d |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1531750049 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.xbar_random_large_delays.1531750049 |
| Directory | /workspace/37.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/37.xbar_random_slow_rsp.211789636 |
| Short name | T1583 |
| Test name | |
| Test status | |
| Simulation time | 49360121013 ps |
| CPU time | 820.23 seconds |
| Started | Jun 23 07:30:35 PM PDT 24 |
| Finished | Jun 23 07:44:16 PM PDT 24 |
| Peak memory | 574160 kb |
| Host | smart-17846db6-ef36-44de-add0-b32c38c03630 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=211789636 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.xbar_random_slow_rsp.211789636 |
| Directory | /workspace/37.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/37.xbar_random_zero_delays.2835048600 |
| Short name | T569 |
| Test name | |
| Test status | |
| Simulation time | 390759083 ps |
| CPU time | 35.38 seconds |
| Started | Jun 23 07:30:33 PM PDT 24 |
| Finished | Jun 23 07:31:08 PM PDT 24 |
| Peak memory | 573364 kb |
| Host | smart-0cb50487-50f7-4533-89cd-2fe580e88fb1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2835048600 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.xbar_random_zero_del ays.2835048600 |
| Directory | /workspace/37.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/37.xbar_same_source.425519117 |
| Short name | T1670 |
| Test name | |
| Test status | |
| Simulation time | 2000327119 ps |
| CPU time | 58.55 seconds |
| Started | Jun 23 07:30:39 PM PDT 24 |
| Finished | Jun 23 07:31:38 PM PDT 24 |
| Peak memory | 573428 kb |
| Host | smart-dca1048d-d4cc-4313-b187-b37f398b119c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=425519117 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.xbar_same_source.425519117 |
| Directory | /workspace/37.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/37.xbar_smoke.565449473 |
| Short name | T1588 |
| Test name | |
| Test status | |
| Simulation time | 247319237 ps |
| CPU time | 9.89 seconds |
| Started | Jun 23 07:30:05 PM PDT 24 |
| Finished | Jun 23 07:30:16 PM PDT 24 |
| Peak memory | 565460 kb |
| Host | smart-bce5f1d7-ad0f-4a7b-b74b-910e13ae63db |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=565449473 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.xbar_smoke.565449473 |
| Directory | /workspace/37.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/37.xbar_smoke_large_delays.1376958002 |
| Short name | T1954 |
| Test name | |
| Test status | |
| Simulation time | 9775692301 ps |
| CPU time | 96.37 seconds |
| Started | Jun 23 07:30:07 PM PDT 24 |
| Finished | Jun 23 07:31:44 PM PDT 24 |
| Peak memory | 565180 kb |
| Host | smart-f5f9bdf6-05a2-498c-bc2b-8006f2e14bb2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1376958002 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.xbar_smoke_large_delays.1376958002 |
| Directory | /workspace/37.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/37.xbar_smoke_slow_rsp.4146579690 |
| Short name | T2375 |
| Test name | |
| Test status | |
| Simulation time | 5090397800 ps |
| CPU time | 86.06 seconds |
| Started | Jun 23 07:30:09 PM PDT 24 |
| Finished | Jun 23 07:31:36 PM PDT 24 |
| Peak memory | 565544 kb |
| Host | smart-7be818cc-3f93-4a34-b854-e2d11c25cad5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4146579690 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.xbar_smoke_slow_rsp.4146579690 |
| Directory | /workspace/37.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/37.xbar_smoke_zero_delays.321933293 |
| Short name | T610 |
| Test name | |
| Test status | |
| Simulation time | 58625698 ps |
| CPU time | 6.97 seconds |
| Started | Jun 23 07:30:09 PM PDT 24 |
| Finished | Jun 23 07:30:17 PM PDT 24 |
| Peak memory | 565184 kb |
| Host | smart-acbda023-29d3-4c4a-8ae7-8e5ae9585521 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=321933293 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.xbar_smoke_zero_delays .321933293 |
| Directory | /workspace/37.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/37.xbar_stress_all.256628590 |
| Short name | T479 |
| Test name | |
| Test status | |
| Simulation time | 6133693052 ps |
| CPU time | 199.27 seconds |
| Started | Jun 23 07:30:40 PM PDT 24 |
| Finished | Jun 23 07:34:01 PM PDT 24 |
| Peak memory | 573604 kb |
| Host | smart-d88cdd44-6f86-4d42-bcf4-ec9e05f90f0a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=256628590 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.xbar_stress_all.256628590 |
| Directory | /workspace/37.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/37.xbar_stress_all_with_error.4216845745 |
| Short name | T2673 |
| Test name | |
| Test status | |
| Simulation time | 13001658321 ps |
| CPU time | 436.01 seconds |
| Started | Jun 23 07:30:45 PM PDT 24 |
| Finished | Jun 23 07:38:02 PM PDT 24 |
| Peak memory | 574144 kb |
| Host | smart-a9873d7c-6f1f-464b-88ee-ab64e55ab746 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4216845745 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.xbar_stress_all_with_error.4216845745 |
| Directory | /workspace/37.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/37.xbar_stress_all_with_rand_reset.3059559601 |
| Short name | T2149 |
| Test name | |
| Test status | |
| Simulation time | 207809980 ps |
| CPU time | 78.9 seconds |
| Started | Jun 23 07:30:43 PM PDT 24 |
| Finished | Jun 23 07:32:02 PM PDT 24 |
| Peak memory | 574192 kb |
| Host | smart-0d48c7f9-d155-46da-902d-2490bfb13ec5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3059559601 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.xbar_stress_all _with_rand_reset.3059559601 |
| Directory | /workspace/37.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/37.xbar_stress_all_with_reset_error.4274348097 |
| Short name | T507 |
| Test name | |
| Test status | |
| Simulation time | 2982662058 ps |
| CPU time | 302.32 seconds |
| Started | Jun 23 07:30:39 PM PDT 24 |
| Finished | Jun 23 07:35:42 PM PDT 24 |
| Peak memory | 576412 kb |
| Host | smart-bf432e74-e29e-46de-84b1-e2508d9e9705 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4274348097 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.xbar_stress_al l_with_reset_error.4274348097 |
| Directory | /workspace/37.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/37.xbar_unmapped_addr.1887167704 |
| Short name | T2863 |
| Test name | |
| Test status | |
| Simulation time | 150981146 ps |
| CPU time | 8.57 seconds |
| Started | Jun 23 07:30:40 PM PDT 24 |
| Finished | Jun 23 07:30:49 PM PDT 24 |
| Peak memory | 565176 kb |
| Host | smart-0e40d153-fd76-464a-976b-b278a948ed5f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1887167704 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.xbar_unmapped_addr.1887167704 |
| Directory | /workspace/37.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/38.xbar_access_same_device.565709852 |
| Short name | T2697 |
| Test name | |
| Test status | |
| Simulation time | 98692221 ps |
| CPU time | 9.28 seconds |
| Started | Jun 23 07:30:44 PM PDT 24 |
| Finished | Jun 23 07:30:54 PM PDT 24 |
| Peak memory | 565456 kb |
| Host | smart-c1ea5b55-e975-4c8b-b3fc-89c845c1ec3e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=565709852 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.xbar_access_same_device. 565709852 |
| Directory | /workspace/38.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/38.xbar_access_same_device_slow_rsp.968031057 |
| Short name | T2103 |
| Test name | |
| Test status | |
| Simulation time | 89706626418 ps |
| CPU time | 1639.99 seconds |
| Started | Jun 23 07:30:42 PM PDT 24 |
| Finished | Jun 23 07:58:03 PM PDT 24 |
| Peak memory | 573552 kb |
| Host | smart-f8074bd6-de24-46cb-b35f-217cb0a865fe |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=968031057 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.xbar_access_same_d evice_slow_rsp.968031057 |
| Directory | /workspace/38.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/38.xbar_error_and_unmapped_addr.3200883080 |
| Short name | T2840 |
| Test name | |
| Test status | |
| Simulation time | 636565980 ps |
| CPU time | 25.52 seconds |
| Started | Jun 23 07:30:42 PM PDT 24 |
| Finished | Jun 23 07:31:09 PM PDT 24 |
| Peak memory | 573820 kb |
| Host | smart-ba454322-f7dd-4d26-9dc7-d9856da4fe47 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3200883080 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.xbar_error_and_unmapped_add r.3200883080 |
| Directory | /workspace/38.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/38.xbar_error_random.390514515 |
| Short name | T1811 |
| Test name | |
| Test status | |
| Simulation time | 136912189 ps |
| CPU time | 7.39 seconds |
| Started | Jun 23 07:30:47 PM PDT 24 |
| Finished | Jun 23 07:30:55 PM PDT 24 |
| Peak memory | 565528 kb |
| Host | smart-2007c086-ec9d-4754-bca4-a55c687e3b9c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=390514515 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.xbar_error_random.390514515 |
| Directory | /workspace/38.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/38.xbar_random.2259316765 |
| Short name | T2476 |
| Test name | |
| Test status | |
| Simulation time | 527956962 ps |
| CPU time | 23.59 seconds |
| Started | Jun 23 07:30:41 PM PDT 24 |
| Finished | Jun 23 07:31:06 PM PDT 24 |
| Peak memory | 574104 kb |
| Host | smart-317c2f40-4398-4b77-b7f9-5a411c3baa86 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2259316765 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.xbar_random.2259316765 |
| Directory | /workspace/38.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/38.xbar_random_large_delays.22814675 |
| Short name | T2751 |
| Test name | |
| Test status | |
| Simulation time | 83113904825 ps |
| CPU time | 879.16 seconds |
| Started | Jun 23 07:30:40 PM PDT 24 |
| Finished | Jun 23 07:45:21 PM PDT 24 |
| Peak memory | 574108 kb |
| Host | smart-7be6f38e-e0a3-481e-a210-fedf0f16a900 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22814675 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.xbar_random_large_delays.22814675 |
| Directory | /workspace/38.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/38.xbar_random_slow_rsp.953518994 |
| Short name | T501 |
| Test name | |
| Test status | |
| Simulation time | 48367956893 ps |
| CPU time | 825.84 seconds |
| Started | Jun 23 07:30:45 PM PDT 24 |
| Finished | Jun 23 07:44:32 PM PDT 24 |
| Peak memory | 574212 kb |
| Host | smart-b87ecb41-97a4-4f20-a343-91330b83780e |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=953518994 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.xbar_random_slow_rsp.953518994 |
| Directory | /workspace/38.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/38.xbar_random_zero_delays.940728063 |
| Short name | T1965 |
| Test name | |
| Test status | |
| Simulation time | 408732604 ps |
| CPU time | 31.97 seconds |
| Started | Jun 23 07:30:39 PM PDT 24 |
| Finished | Jun 23 07:31:12 PM PDT 24 |
| Peak memory | 573588 kb |
| Host | smart-ac1a5748-302d-4998-af81-097eafed0733 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=940728063 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.xbar_random_zero_dela ys.940728063 |
| Directory | /workspace/38.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/38.xbar_same_source.663504984 |
| Short name | T632 |
| Test name | |
| Test status | |
| Simulation time | 2256996618 ps |
| CPU time | 67.59 seconds |
| Started | Jun 23 07:30:41 PM PDT 24 |
| Finished | Jun 23 07:31:50 PM PDT 24 |
| Peak memory | 573412 kb |
| Host | smart-1f6e0128-5a29-4614-9623-c0c4abfa59f8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=663504984 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.xbar_same_source.663504984 |
| Directory | /workspace/38.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/38.xbar_smoke.409732346 |
| Short name | T1693 |
| Test name | |
| Test status | |
| Simulation time | 205246284 ps |
| CPU time | 8.41 seconds |
| Started | Jun 23 07:30:41 PM PDT 24 |
| Finished | Jun 23 07:30:51 PM PDT 24 |
| Peak memory | 565480 kb |
| Host | smart-611f1b2d-4ad7-44cc-a89f-926c24d87a40 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=409732346 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.xbar_smoke.409732346 |
| Directory | /workspace/38.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/38.xbar_smoke_large_delays.2512924740 |
| Short name | T2293 |
| Test name | |
| Test status | |
| Simulation time | 8529259252 ps |
| CPU time | 88.9 seconds |
| Started | Jun 23 07:30:44 PM PDT 24 |
| Finished | Jun 23 07:32:14 PM PDT 24 |
| Peak memory | 565248 kb |
| Host | smart-e2d013b6-b058-4473-91c6-a557328d57f3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2512924740 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.xbar_smoke_large_delays.2512924740 |
| Directory | /workspace/38.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/38.xbar_smoke_slow_rsp.640566128 |
| Short name | T2356 |
| Test name | |
| Test status | |
| Simulation time | 4989329046 ps |
| CPU time | 78.43 seconds |
| Started | Jun 23 07:30:39 PM PDT 24 |
| Finished | Jun 23 07:31:58 PM PDT 24 |
| Peak memory | 565920 kb |
| Host | smart-67f49ce7-b02d-4496-91d0-0ebf1d1f65fe |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=640566128 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.xbar_smoke_slow_rsp.640566128 |
| Directory | /workspace/38.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/38.xbar_smoke_zero_delays.1865781100 |
| Short name | T643 |
| Test name | |
| Test status | |
| Simulation time | 59196584 ps |
| CPU time | 7.19 seconds |
| Started | Jun 23 07:30:39 PM PDT 24 |
| Finished | Jun 23 07:30:46 PM PDT 24 |
| Peak memory | 565500 kb |
| Host | smart-7edc9a61-fb8c-47fc-9d04-e5b8a0248c40 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1865781100 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.xbar_smoke_zero_delay s.1865781100 |
| Directory | /workspace/38.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/38.xbar_stress_all.619059046 |
| Short name | T2261 |
| Test name | |
| Test status | |
| Simulation time | 1674576149 ps |
| CPU time | 125.21 seconds |
| Started | Jun 23 07:30:41 PM PDT 24 |
| Finished | Jun 23 07:32:47 PM PDT 24 |
| Peak memory | 573484 kb |
| Host | smart-33b45d60-8e95-468c-9ba7-892fa1f35417 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=619059046 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.xbar_stress_all.619059046 |
| Directory | /workspace/38.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/38.xbar_stress_all_with_error.235414121 |
| Short name | T1575 |
| Test name | |
| Test status | |
| Simulation time | 6055611949 ps |
| CPU time | 229.12 seconds |
| Started | Jun 23 07:30:39 PM PDT 24 |
| Finished | Jun 23 07:34:29 PM PDT 24 |
| Peak memory | 574348 kb |
| Host | smart-1ff8cfe4-d6f3-45eb-8ce8-36f594401d29 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=235414121 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.xbar_stress_all_with_error.235414121 |
| Directory | /workspace/38.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/38.xbar_stress_all_with_reset_error.2858680522 |
| Short name | T902 |
| Test name | |
| Test status | |
| Simulation time | 28705945 ps |
| CPU time | 17.82 seconds |
| Started | Jun 23 07:30:40 PM PDT 24 |
| Finished | Jun 23 07:30:59 PM PDT 24 |
| Peak memory | 565500 kb |
| Host | smart-8699b434-e029-4f07-9f42-d827a7e4bb56 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2858680522 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.xbar_stress_al l_with_reset_error.2858680522 |
| Directory | /workspace/38.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/38.xbar_unmapped_addr.1490161666 |
| Short name | T2115 |
| Test name | |
| Test status | |
| Simulation time | 1450466371 ps |
| CPU time | 51.43 seconds |
| Started | Jun 23 07:30:41 PM PDT 24 |
| Finished | Jun 23 07:31:34 PM PDT 24 |
| Peak memory | 574132 kb |
| Host | smart-cbab0053-b105-456b-b6a1-935b80fccd4f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1490161666 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.xbar_unmapped_addr.1490161666 |
| Directory | /workspace/38.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/39.xbar_access_same_device.1311530655 |
| Short name | T2536 |
| Test name | |
| Test status | |
| Simulation time | 1177576420 ps |
| CPU time | 50.61 seconds |
| Started | Jun 23 07:30:44 PM PDT 24 |
| Finished | Jun 23 07:31:36 PM PDT 24 |
| Peak memory | 573696 kb |
| Host | smart-722c608e-0dda-4886-bfd9-6be0ea1e8723 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1311530655 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.xbar_access_same_device .1311530655 |
| Directory | /workspace/39.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/39.xbar_access_same_device_slow_rsp.1675460451 |
| Short name | T2168 |
| Test name | |
| Test status | |
| Simulation time | 136179375070 ps |
| CPU time | 2481.25 seconds |
| Started | Jun 23 07:30:41 PM PDT 24 |
| Finished | Jun 23 08:12:04 PM PDT 24 |
| Peak memory | 574284 kb |
| Host | smart-09e2f2cb-74e8-4358-a3ca-0f7b09c94019 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1675460451 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.xbar_access_same_ device_slow_rsp.1675460451 |
| Directory | /workspace/39.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/39.xbar_error_and_unmapped_addr.977734082 |
| Short name | T1474 |
| Test name | |
| Test status | |
| Simulation time | 215857526 ps |
| CPU time | 12.22 seconds |
| Started | Jun 23 07:30:41 PM PDT 24 |
| Finished | Jun 23 07:30:54 PM PDT 24 |
| Peak memory | 573732 kb |
| Host | smart-3156fdf1-5f03-420a-9bdc-35786f295fe8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=977734082 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.xbar_error_and_unmapped_addr .977734082 |
| Directory | /workspace/39.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/39.xbar_error_random.1485886742 |
| Short name | T1830 |
| Test name | |
| Test status | |
| Simulation time | 148380722 ps |
| CPU time | 13.13 seconds |
| Started | Jun 23 07:30:40 PM PDT 24 |
| Finished | Jun 23 07:30:54 PM PDT 24 |
| Peak memory | 573740 kb |
| Host | smart-362f5259-5fc9-4960-a02a-588818486759 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1485886742 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.xbar_error_random.1485886742 |
| Directory | /workspace/39.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/39.xbar_random.4204351604 |
| Short name | T516 |
| Test name | |
| Test status | |
| Simulation time | 520927100 ps |
| CPU time | 40.92 seconds |
| Started | Jun 23 07:30:40 PM PDT 24 |
| Finished | Jun 23 07:31:21 PM PDT 24 |
| Peak memory | 574140 kb |
| Host | smart-6524058f-fdb1-497b-a86d-4f56b00e7839 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4204351604 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.xbar_random.4204351604 |
| Directory | /workspace/39.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/39.xbar_random_large_delays.2186494862 |
| Short name | T1584 |
| Test name | |
| Test status | |
| Simulation time | 55901784534 ps |
| CPU time | 571.98 seconds |
| Started | Jun 23 07:30:42 PM PDT 24 |
| Finished | Jun 23 07:40:15 PM PDT 24 |
| Peak memory | 574164 kb |
| Host | smart-8cd65939-ddf3-4ee3-93bc-7f37b1d9359b |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2186494862 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.xbar_random_large_delays.2186494862 |
| Directory | /workspace/39.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/39.xbar_random_slow_rsp.263323141 |
| Short name | T625 |
| Test name | |
| Test status | |
| Simulation time | 27298414849 ps |
| CPU time | 495.42 seconds |
| Started | Jun 23 07:30:38 PM PDT 24 |
| Finished | Jun 23 07:38:54 PM PDT 24 |
| Peak memory | 574152 kb |
| Host | smart-80e7fd32-4c5a-480d-b558-381e97c00aa0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=263323141 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.xbar_random_slow_rsp.263323141 |
| Directory | /workspace/39.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/39.xbar_random_zero_delays.3357886815 |
| Short name | T2758 |
| Test name | |
| Test status | |
| Simulation time | 91544388 ps |
| CPU time | 11.5 seconds |
| Started | Jun 23 07:30:45 PM PDT 24 |
| Finished | Jun 23 07:30:57 PM PDT 24 |
| Peak memory | 573936 kb |
| Host | smart-978414cf-b4f5-4690-a4af-0e43637b9d28 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3357886815 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.xbar_random_zero_del ays.3357886815 |
| Directory | /workspace/39.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/39.xbar_same_source.1304747113 |
| Short name | T1599 |
| Test name | |
| Test status | |
| Simulation time | 2403223910 ps |
| CPU time | 68.93 seconds |
| Started | Jun 23 07:30:41 PM PDT 24 |
| Finished | Jun 23 07:31:51 PM PDT 24 |
| Peak memory | 574156 kb |
| Host | smart-bdbd94a6-ed2e-4cac-8e9b-d558be951892 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1304747113 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.xbar_same_source.1304747113 |
| Directory | /workspace/39.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/39.xbar_smoke.1349295302 |
| Short name | T1720 |
| Test name | |
| Test status | |
| Simulation time | 187612281 ps |
| CPU time | 8.34 seconds |
| Started | Jun 23 07:30:41 PM PDT 24 |
| Finished | Jun 23 07:30:51 PM PDT 24 |
| Peak memory | 565792 kb |
| Host | smart-906e4522-f22c-420e-86e6-1fb45c44ab83 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1349295302 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.xbar_smoke.1349295302 |
| Directory | /workspace/39.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/39.xbar_smoke_large_delays.2977326901 |
| Short name | T1362 |
| Test name | |
| Test status | |
| Simulation time | 6326681760 ps |
| CPU time | 64.57 seconds |
| Started | Jun 23 07:30:39 PM PDT 24 |
| Finished | Jun 23 07:31:44 PM PDT 24 |
| Peak memory | 565572 kb |
| Host | smart-9da9ae66-45cd-4006-a8db-973331c3fa68 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2977326901 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.xbar_smoke_large_delays.2977326901 |
| Directory | /workspace/39.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/39.xbar_smoke_slow_rsp.1676765245 |
| Short name | T2574 |
| Test name | |
| Test status | |
| Simulation time | 3517471337 ps |
| CPU time | 56.91 seconds |
| Started | Jun 23 07:30:47 PM PDT 24 |
| Finished | Jun 23 07:31:44 PM PDT 24 |
| Peak memory | 565944 kb |
| Host | smart-4600ef91-ce68-4fa6-b32b-267aa86739b3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1676765245 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.xbar_smoke_slow_rsp.1676765245 |
| Directory | /workspace/39.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/39.xbar_smoke_zero_delays.3277984181 |
| Short name | T2052 |
| Test name | |
| Test status | |
| Simulation time | 52126939 ps |
| CPU time | 7.12 seconds |
| Started | Jun 23 07:30:42 PM PDT 24 |
| Finished | Jun 23 07:30:50 PM PDT 24 |
| Peak memory | 565560 kb |
| Host | smart-ed0717c0-ddf1-48e7-8092-272c19d5a958 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3277984181 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.xbar_smoke_zero_delay s.3277984181 |
| Directory | /workspace/39.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/39.xbar_stress_all.3246930096 |
| Short name | T2243 |
| Test name | |
| Test status | |
| Simulation time | 12343708844 ps |
| CPU time | 526.32 seconds |
| Started | Jun 23 07:30:40 PM PDT 24 |
| Finished | Jun 23 07:39:27 PM PDT 24 |
| Peak memory | 574328 kb |
| Host | smart-6b90da14-d514-49b3-ab19-f396850125d7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3246930096 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.xbar_stress_all.3246930096 |
| Directory | /workspace/39.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/39.xbar_stress_all_with_error.2208372145 |
| Short name | T2129 |
| Test name | |
| Test status | |
| Simulation time | 2390134568 ps |
| CPU time | 99.45 seconds |
| Started | Jun 23 07:30:39 PM PDT 24 |
| Finished | Jun 23 07:32:19 PM PDT 24 |
| Peak memory | 573452 kb |
| Host | smart-edb768e1-29ec-4ca6-9fcd-d91d68753e48 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2208372145 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.xbar_stress_all_with_error.2208372145 |
| Directory | /workspace/39.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/39.xbar_stress_all_with_rand_reset.1077407499 |
| Short name | T586 |
| Test name | |
| Test status | |
| Simulation time | 471168426 ps |
| CPU time | 228.76 seconds |
| Started | Jun 23 07:30:41 PM PDT 24 |
| Finished | Jun 23 07:34:30 PM PDT 24 |
| Peak memory | 576304 kb |
| Host | smart-13dc3b61-97a5-4873-a026-5976c7037028 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1077407499 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.xbar_stress_all _with_rand_reset.1077407499 |
| Directory | /workspace/39.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/39.xbar_stress_all_with_reset_error.698825978 |
| Short name | T900 |
| Test name | |
| Test status | |
| Simulation time | 1027158561 ps |
| CPU time | 92.04 seconds |
| Started | Jun 23 07:30:42 PM PDT 24 |
| Finished | Jun 23 07:32:15 PM PDT 24 |
| Peak memory | 576292 kb |
| Host | smart-ba99fc93-8dc3-4d66-af18-5da19f75c788 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=698825978 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.xbar_stress_all _with_reset_error.698825978 |
| Directory | /workspace/39.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/39.xbar_unmapped_addr.4150423906 |
| Short name | T2310 |
| Test name | |
| Test status | |
| Simulation time | 43876100 ps |
| CPU time | 8.31 seconds |
| Started | Jun 23 07:30:43 PM PDT 24 |
| Finished | Jun 23 07:30:52 PM PDT 24 |
| Peak memory | 565928 kb |
| Host | smart-995bcfec-1c3b-4908-88a1-5990940b2dad |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4150423906 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.xbar_unmapped_addr.4150423906 |
| Directory | /workspace/39.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/4.chip_csr_aliasing.2875387055 |
| Short name | T1878 |
| Test name | |
| Test status | |
| Simulation time | 54488314413 ps |
| CPU time | 10049.4 seconds |
| Started | Jun 23 07:21:23 PM PDT 24 |
| Finished | Jun 23 10:08:54 PM PDT 24 |
| Peak memory | 634372 kb |
| Host | smart-2daffafa-55cf-4e96-b9e1-fa515a423d2b |
| User | root |
| Command | /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +csr_aliasing +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2875387055 -assert nopostproc +UVM_TESTNAME=chip_ base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/ null -cm_name 4.chip_csr_aliasing.2875387055 |
| Directory | /workspace/4.chip_csr_aliasing/latest |
| Test location | /workspace/coverage/cover_reg_top/4.chip_csr_bit_bash.594185385 |
| Short name | T388 |
| Test name | |
| Test status | |
| Simulation time | 11719592750 ps |
| CPU time | 1300.78 seconds |
| Started | Jun 23 07:21:20 PM PDT 24 |
| Finished | Jun 23 07:43:01 PM PDT 24 |
| Peak memory | 589136 kb |
| Host | smart-f3802035-7703-4bf0-979b-15ece6d9278e |
| User | root |
| Command | /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +num_test_csrs=200 +csr_bit_bash +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=594185385 -assert nopostproc + UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top .vdb -cm_log /dev/null -cm_name 4.chip_csr_bit_bash.594185385 |
| Directory | /workspace/4.chip_csr_bit_bash/latest |
| Test location | /workspace/coverage/cover_reg_top/4.chip_same_csr_outstanding.4045747984 |
| Short name | T432 |
| Test name | |
| Test status | |
| Simulation time | 15794466424 ps |
| CPU time | 1956.62 seconds |
| Started | Jun 23 07:21:23 PM PDT 24 |
| Finished | Jun 23 07:54:00 PM PDT 24 |
| Peak memory | 591184 kb |
| Host | smart-55525c03-f87c-4cca-86c2-aab8cd252fe5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +run_same_csr_outstanding +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4045747984 -assert nopostproc +UVM_TE STNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb - cm_log /dev/null -cm_name 4.chip_same_csr_outstanding.4045747984 |
| Directory | /workspace/4.chip_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/4.xbar_access_same_device.2957000541 |
| Short name | T2400 |
| Test name | |
| Test status | |
| Simulation time | 115643615 ps |
| CPU time | 11.54 seconds |
| Started | Jun 23 07:21:26 PM PDT 24 |
| Finished | Jun 23 07:21:38 PM PDT 24 |
| Peak memory | 574020 kb |
| Host | smart-d00418f4-4fd1-41f8-b7b4-1e3ab8462f90 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2957000541 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.xbar_access_same_device. 2957000541 |
| Directory | /workspace/4.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/4.xbar_access_same_device_slow_rsp.885309850 |
| Short name | T532 |
| Test name | |
| Test status | |
| Simulation time | 43424181236 ps |
| CPU time | 758.54 seconds |
| Started | Jun 23 07:21:28 PM PDT 24 |
| Finished | Jun 23 07:34:07 PM PDT 24 |
| Peak memory | 574228 kb |
| Host | smart-67abd043-b425-44e6-a165-d613b32fd7d4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=885309850 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.xbar_access_same_de vice_slow_rsp.885309850 |
| Directory | /workspace/4.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/4.xbar_error_and_unmapped_addr.1722884291 |
| Short name | T1410 |
| Test name | |
| Test status | |
| Simulation time | 645735908 ps |
| CPU time | 28.5 seconds |
| Started | Jun 23 07:21:22 PM PDT 24 |
| Finished | Jun 23 07:21:51 PM PDT 24 |
| Peak memory | 573688 kb |
| Host | smart-700a2c4e-c737-471f-a21d-2324b3bef059 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1722884291 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.xbar_error_and_unmapped_addr .1722884291 |
| Directory | /workspace/4.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/4.xbar_error_random.2357804768 |
| Short name | T2130 |
| Test name | |
| Test status | |
| Simulation time | 875955079 ps |
| CPU time | 32.74 seconds |
| Started | Jun 23 07:21:23 PM PDT 24 |
| Finished | Jun 23 07:21:56 PM PDT 24 |
| Peak memory | 573360 kb |
| Host | smart-ca3fa11d-df63-453b-b720-5608db2ddfce |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2357804768 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.xbar_error_random.2357804768 |
| Directory | /workspace/4.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/4.xbar_random.2676541220 |
| Short name | T2044 |
| Test name | |
| Test status | |
| Simulation time | 1288374581 ps |
| CPU time | 51.71 seconds |
| Started | Jun 23 07:21:24 PM PDT 24 |
| Finished | Jun 23 07:22:16 PM PDT 24 |
| Peak memory | 574068 kb |
| Host | smart-8c4aeb71-f6da-4039-88c1-b6528a5931f0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2676541220 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.xbar_random.2676541220 |
| Directory | /workspace/4.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/4.xbar_random_large_delays.1012760465 |
| Short name | T2754 |
| Test name | |
| Test status | |
| Simulation time | 15945600144 ps |
| CPU time | 178.35 seconds |
| Started | Jun 23 07:21:23 PM PDT 24 |
| Finished | Jun 23 07:24:22 PM PDT 24 |
| Peak memory | 573464 kb |
| Host | smart-c41f75a0-759d-4cf7-bba3-de71da307365 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1012760465 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.xbar_random_large_delays.1012760465 |
| Directory | /workspace/4.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/4.xbar_random_slow_rsp.2976768443 |
| Short name | T1836 |
| Test name | |
| Test status | |
| Simulation time | 61857392680 ps |
| CPU time | 1049.15 seconds |
| Started | Jun 23 07:21:24 PM PDT 24 |
| Finished | Jun 23 07:38:53 PM PDT 24 |
| Peak memory | 574156 kb |
| Host | smart-94ed48d7-8eac-4530-92b6-42619c0bcf10 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2976768443 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.xbar_random_slow_rsp.2976768443 |
| Directory | /workspace/4.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/4.xbar_random_zero_delays.1930568748 |
| Short name | T1808 |
| Test name | |
| Test status | |
| Simulation time | 256178717 ps |
| CPU time | 23.48 seconds |
| Started | Jun 23 07:21:24 PM PDT 24 |
| Finished | Jun 23 07:21:48 PM PDT 24 |
| Peak memory | 574096 kb |
| Host | smart-b65a83af-2186-4c9f-93f2-20daaac54148 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1930568748 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.xbar_random_zero_dela ys.1930568748 |
| Directory | /workspace/4.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/4.xbar_same_source.409988958 |
| Short name | T2143 |
| Test name | |
| Test status | |
| Simulation time | 317346936 ps |
| CPU time | 22.86 seconds |
| Started | Jun 23 07:21:22 PM PDT 24 |
| Finished | Jun 23 07:21:45 PM PDT 24 |
| Peak memory | 573744 kb |
| Host | smart-23163998-2ddc-4b74-b34b-5f73c7579805 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=409988958 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.xbar_same_source.409988958 |
| Directory | /workspace/4.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/4.xbar_smoke.2256647047 |
| Short name | T1845 |
| Test name | |
| Test status | |
| Simulation time | 57401719 ps |
| CPU time | 6.69 seconds |
| Started | Jun 23 07:21:23 PM PDT 24 |
| Finished | Jun 23 07:21:30 PM PDT 24 |
| Peak memory | 565480 kb |
| Host | smart-48876692-87d5-4c13-ac77-d3f2c115761d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2256647047 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.xbar_smoke.2256647047 |
| Directory | /workspace/4.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/4.xbar_smoke_large_delays.1892998233 |
| Short name | T1385 |
| Test name | |
| Test status | |
| Simulation time | 10507615399 ps |
| CPU time | 115.75 seconds |
| Started | Jun 23 07:21:27 PM PDT 24 |
| Finished | Jun 23 07:23:23 PM PDT 24 |
| Peak memory | 565936 kb |
| Host | smart-2f3acf34-76c5-46c2-8fd6-45aee94de25c |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1892998233 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.xbar_smoke_large_delays.1892998233 |
| Directory | /workspace/4.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/4.xbar_smoke_slow_rsp.278374727 |
| Short name | T1669 |
| Test name | |
| Test status | |
| Simulation time | 5206966585 ps |
| CPU time | 83.24 seconds |
| Started | Jun 23 07:21:22 PM PDT 24 |
| Finished | Jun 23 07:22:46 PM PDT 24 |
| Peak memory | 565924 kb |
| Host | smart-932dfa9d-14f6-437a-97cf-53ae811e3c61 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=278374727 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.xbar_smoke_slow_rsp.278374727 |
| Directory | /workspace/4.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/4.xbar_smoke_zero_delays.2921067212 |
| Short name | T2662 |
| Test name | |
| Test status | |
| Simulation time | 38492714 ps |
| CPU time | 5.56 seconds |
| Started | Jun 23 07:21:26 PM PDT 24 |
| Finished | Jun 23 07:21:32 PM PDT 24 |
| Peak memory | 565476 kb |
| Host | smart-728ce427-87c1-455c-bc69-3969bee2898f |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2921067212 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.xbar_smoke_zero_delays .2921067212 |
| Directory | /workspace/4.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/4.xbar_stress_all.2228311568 |
| Short name | T2362 |
| Test name | |
| Test status | |
| Simulation time | 3775961156 ps |
| CPU time | 268.54 seconds |
| Started | Jun 23 07:21:33 PM PDT 24 |
| Finished | Jun 23 07:26:02 PM PDT 24 |
| Peak memory | 573556 kb |
| Host | smart-f402d27a-fdb5-4e5c-865b-7986d9151d41 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2228311568 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.xbar_stress_all.2228311568 |
| Directory | /workspace/4.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/4.xbar_stress_all_with_rand_reset.2147991244 |
| Short name | T876 |
| Test name | |
| Test status | |
| Simulation time | 410813191 ps |
| CPU time | 152.53 seconds |
| Started | Jun 23 07:21:26 PM PDT 24 |
| Finished | Jun 23 07:23:59 PM PDT 24 |
| Peak memory | 576272 kb |
| Host | smart-02583655-fafa-4672-afe6-6b2028128056 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2147991244 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.xbar_stress_all_ with_rand_reset.2147991244 |
| Directory | /workspace/4.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/4.xbar_stress_all_with_reset_error.2197431377 |
| Short name | T861 |
| Test name | |
| Test status | |
| Simulation time | 828347678 ps |
| CPU time | 223.79 seconds |
| Started | Jun 23 07:21:23 PM PDT 24 |
| Finished | Jun 23 07:25:07 PM PDT 24 |
| Peak memory | 574260 kb |
| Host | smart-36d7317b-ba04-4ce5-b189-c57c1e7cebb3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2197431377 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.xbar_stress_all _with_reset_error.2197431377 |
| Directory | /workspace/4.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/4.xbar_unmapped_addr.2280918063 |
| Short name | T2391 |
| Test name | |
| Test status | |
| Simulation time | 24325696 ps |
| CPU time | 5.19 seconds |
| Started | Jun 23 07:21:24 PM PDT 24 |
| Finished | Jun 23 07:21:30 PM PDT 24 |
| Peak memory | 565884 kb |
| Host | smart-cc036e16-7f03-432c-89dd-a6fea1840bec |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2280918063 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.xbar_unmapped_addr.2280918063 |
| Directory | /workspace/4.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/40.xbar_access_same_device.3822755935 |
| Short name | T1531 |
| Test name | |
| Test status | |
| Simulation time | 245471245 ps |
| CPU time | 12.15 seconds |
| Started | Jun 23 07:30:43 PM PDT 24 |
| Finished | Jun 23 07:30:55 PM PDT 24 |
| Peak memory | 565488 kb |
| Host | smart-1217cae0-654b-4a9e-b3f9-12dd3a4b46d4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3822755935 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.xbar_access_same_device .3822755935 |
| Directory | /workspace/40.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/40.xbar_access_same_device_slow_rsp.226531667 |
| Short name | T2248 |
| Test name | |
| Test status | |
| Simulation time | 10374804603 ps |
| CPU time | 174.28 seconds |
| Started | Jun 23 07:30:45 PM PDT 24 |
| Finished | Jun 23 07:33:40 PM PDT 24 |
| Peak memory | 565956 kb |
| Host | smart-8ba14fb5-26d6-4ed2-8ba1-6e40f13baebe |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=226531667 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.xbar_access_same_d evice_slow_rsp.226531667 |
| Directory | /workspace/40.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/40.xbar_error_and_unmapped_addr.3173605239 |
| Short name | T2485 |
| Test name | |
| Test status | |
| Simulation time | 1283561522 ps |
| CPU time | 54.77 seconds |
| Started | Jun 23 07:30:53 PM PDT 24 |
| Finished | Jun 23 07:31:48 PM PDT 24 |
| Peak memory | 573336 kb |
| Host | smart-dfb4f9a8-cc41-4c1e-9264-532200e2d902 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3173605239 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.xbar_error_and_unmapped_add r.3173605239 |
| Directory | /workspace/40.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/40.xbar_error_random.3818410623 |
| Short name | T2661 |
| Test name | |
| Test status | |
| Simulation time | 257662037 ps |
| CPU time | 20.01 seconds |
| Started | Jun 23 07:30:54 PM PDT 24 |
| Finished | Jun 23 07:31:14 PM PDT 24 |
| Peak memory | 573716 kb |
| Host | smart-19a74854-9253-477a-9904-a1979f0b7353 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3818410623 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.xbar_error_random.3818410623 |
| Directory | /workspace/40.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/40.xbar_random.2768352960 |
| Short name | T2047 |
| Test name | |
| Test status | |
| Simulation time | 1107395706 ps |
| CPU time | 38.78 seconds |
| Started | Jun 23 07:30:44 PM PDT 24 |
| Finished | Jun 23 07:31:23 PM PDT 24 |
| Peak memory | 573440 kb |
| Host | smart-c50a96c4-f727-4c40-9dad-eb146fb36428 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2768352960 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.xbar_random.2768352960 |
| Directory | /workspace/40.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/40.xbar_random_large_delays.4187483258 |
| Short name | T2510 |
| Test name | |
| Test status | |
| Simulation time | 65845186313 ps |
| CPU time | 707.42 seconds |
| Started | Jun 23 07:30:47 PM PDT 24 |
| Finished | Jun 23 07:42:35 PM PDT 24 |
| Peak memory | 573576 kb |
| Host | smart-895b3fd3-ed18-430f-9837-d6c28d0c361f |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4187483258 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.xbar_random_large_delays.4187483258 |
| Directory | /workspace/40.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/40.xbar_random_slow_rsp.2111510369 |
| Short name | T2821 |
| Test name | |
| Test status | |
| Simulation time | 36851732662 ps |
| CPU time | 563.82 seconds |
| Started | Jun 23 07:30:48 PM PDT 24 |
| Finished | Jun 23 07:40:12 PM PDT 24 |
| Peak memory | 574212 kb |
| Host | smart-a76e4acf-64e1-47d5-8451-9abd35ff29cf |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2111510369 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.xbar_random_slow_rsp.2111510369 |
| Directory | /workspace/40.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/40.xbar_random_zero_delays.2181889038 |
| Short name | T2761 |
| Test name | |
| Test status | |
| Simulation time | 98216992 ps |
| CPU time | 11.31 seconds |
| Started | Jun 23 07:30:44 PM PDT 24 |
| Finished | Jun 23 07:30:55 PM PDT 24 |
| Peak memory | 573964 kb |
| Host | smart-0b7ff8fd-9114-4228-a4b1-1dac83c84cfe |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2181889038 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.xbar_random_zero_del ays.2181889038 |
| Directory | /workspace/40.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/40.xbar_same_source.1006130162 |
| Short name | T1709 |
| Test name | |
| Test status | |
| Simulation time | 175427430 ps |
| CPU time | 15.14 seconds |
| Started | Jun 23 07:30:55 PM PDT 24 |
| Finished | Jun 23 07:31:11 PM PDT 24 |
| Peak memory | 573360 kb |
| Host | smart-5e43cd31-03f9-4331-a60e-8ab1ce2fc439 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1006130162 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.xbar_same_source.1006130162 |
| Directory | /workspace/40.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/40.xbar_smoke.79382518 |
| Short name | T1748 |
| Test name | |
| Test status | |
| Simulation time | 219579142 ps |
| CPU time | 10.15 seconds |
| Started | Jun 23 07:30:45 PM PDT 24 |
| Finished | Jun 23 07:30:56 PM PDT 24 |
| Peak memory | 565532 kb |
| Host | smart-ea8c9516-b074-4ae2-9032-43c859cdf6f2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79382518 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.xbar_smoke.79382518 |
| Directory | /workspace/40.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/40.xbar_smoke_large_delays.396333567 |
| Short name | T2028 |
| Test name | |
| Test status | |
| Simulation time | 7473401200 ps |
| CPU time | 82.5 seconds |
| Started | Jun 23 07:30:43 PM PDT 24 |
| Finished | Jun 23 07:32:06 PM PDT 24 |
| Peak memory | 565220 kb |
| Host | smart-f240f460-aa9c-4c42-83de-a85022883460 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=396333567 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.xbar_smoke_large_delays.396333567 |
| Directory | /workspace/40.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/40.xbar_smoke_slow_rsp.3543277922 |
| Short name | T1618 |
| Test name | |
| Test status | |
| Simulation time | 5503029535 ps |
| CPU time | 90.89 seconds |
| Started | Jun 23 07:30:47 PM PDT 24 |
| Finished | Jun 23 07:32:18 PM PDT 24 |
| Peak memory | 565140 kb |
| Host | smart-d23d9b64-488a-433a-8192-d30dfae107a9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3543277922 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.xbar_smoke_slow_rsp.3543277922 |
| Directory | /workspace/40.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/40.xbar_smoke_zero_delays.1473659839 |
| Short name | T1480 |
| Test name | |
| Test status | |
| Simulation time | 57773015 ps |
| CPU time | 7.51 seconds |
| Started | Jun 23 07:30:44 PM PDT 24 |
| Finished | Jun 23 07:30:52 PM PDT 24 |
| Peak memory | 565472 kb |
| Host | smart-973ba011-376c-4538-b2b0-b900bd62aa67 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1473659839 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.xbar_smoke_zero_delay s.1473659839 |
| Directory | /workspace/40.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/40.xbar_stress_all.2220040010 |
| Short name | T441 |
| Test name | |
| Test status | |
| Simulation time | 8626749563 ps |
| CPU time | 358.04 seconds |
| Started | Jun 23 07:30:53 PM PDT 24 |
| Finished | Jun 23 07:36:51 PM PDT 24 |
| Peak memory | 574312 kb |
| Host | smart-30826b40-6644-469e-80fb-6383ca7837ae |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2220040010 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.xbar_stress_all.2220040010 |
| Directory | /workspace/40.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/40.xbar_stress_all_with_error.945230700 |
| Short name | T2085 |
| Test name | |
| Test status | |
| Simulation time | 1001498567 ps |
| CPU time | 95.85 seconds |
| Started | Jun 23 07:30:52 PM PDT 24 |
| Finished | Jun 23 07:32:28 PM PDT 24 |
| Peak memory | 573548 kb |
| Host | smart-ee4aa055-d877-4932-998f-76a346a8d977 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=945230700 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.xbar_stress_all_with_error.945230700 |
| Directory | /workspace/40.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/40.xbar_stress_all_with_rand_reset.3252220006 |
| Short name | T2608 |
| Test name | |
| Test status | |
| Simulation time | 757003791 ps |
| CPU time | 300.83 seconds |
| Started | Jun 23 07:30:55 PM PDT 24 |
| Finished | Jun 23 07:35:56 PM PDT 24 |
| Peak memory | 576300 kb |
| Host | smart-9b15256b-5eb2-4903-ace0-cdb0b8958bc7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3252220006 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.xbar_stress_all _with_rand_reset.3252220006 |
| Directory | /workspace/40.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/40.xbar_stress_all_with_reset_error.3675542752 |
| Short name | T2712 |
| Test name | |
| Test status | |
| Simulation time | 84181289 ps |
| CPU time | 30.17 seconds |
| Started | Jun 23 07:31:08 PM PDT 24 |
| Finished | Jun 23 07:31:38 PM PDT 24 |
| Peak memory | 575800 kb |
| Host | smart-a76c47c0-3dcf-4da6-b818-8d04c1390b8c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3675542752 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.xbar_stress_al l_with_reset_error.3675542752 |
| Directory | /workspace/40.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/40.xbar_unmapped_addr.3343776088 |
| Short name | T2122 |
| Test name | |
| Test status | |
| Simulation time | 151013277 ps |
| CPU time | 9.73 seconds |
| Started | Jun 23 07:30:55 PM PDT 24 |
| Finished | Jun 23 07:31:05 PM PDT 24 |
| Peak memory | 565964 kb |
| Host | smart-2628b71f-9918-4d68-b126-a2ee913d10a1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3343776088 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.xbar_unmapped_addr.3343776088 |
| Directory | /workspace/40.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/41.xbar_access_same_device.3794942113 |
| Short name | T526 |
| Test name | |
| Test status | |
| Simulation time | 870151255 ps |
| CPU time | 84.66 seconds |
| Started | Jun 23 07:30:59 PM PDT 24 |
| Finished | Jun 23 07:32:24 PM PDT 24 |
| Peak memory | 574128 kb |
| Host | smart-0f61269c-0dc0-4a26-b842-d33e224db202 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3794942113 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.xbar_access_same_device .3794942113 |
| Directory | /workspace/41.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/41.xbar_access_same_device_slow_rsp.144137769 |
| Short name | T2729 |
| Test name | |
| Test status | |
| Simulation time | 8381586875 ps |
| CPU time | 130.21 seconds |
| Started | Jun 23 07:30:58 PM PDT 24 |
| Finished | Jun 23 07:33:09 PM PDT 24 |
| Peak memory | 565812 kb |
| Host | smart-68da11d0-3aba-425f-bd29-2ef8a022fc12 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=144137769 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.xbar_access_same_d evice_slow_rsp.144137769 |
| Directory | /workspace/41.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/41.xbar_error_and_unmapped_addr.1408839647 |
| Short name | T1415 |
| Test name | |
| Test status | |
| Simulation time | 440569451 ps |
| CPU time | 19.24 seconds |
| Started | Jun 23 07:30:59 PM PDT 24 |
| Finished | Jun 23 07:31:18 PM PDT 24 |
| Peak memory | 573684 kb |
| Host | smart-4b427f92-24f1-4414-8c8f-4573159881c9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1408839647 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.xbar_error_and_unmapped_add r.1408839647 |
| Directory | /workspace/41.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/41.xbar_error_random.1022031009 |
| Short name | T2638 |
| Test name | |
| Test status | |
| Simulation time | 197203645 ps |
| CPU time | 16.67 seconds |
| Started | Jun 23 07:30:59 PM PDT 24 |
| Finished | Jun 23 07:31:17 PM PDT 24 |
| Peak memory | 573400 kb |
| Host | smart-78ed97d2-4de9-48c8-b869-5ad59b9780ce |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1022031009 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.xbar_error_random.1022031009 |
| Directory | /workspace/41.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/41.xbar_random.1241399735 |
| Short name | T2208 |
| Test name | |
| Test status | |
| Simulation time | 552286267 ps |
| CPU time | 20.75 seconds |
| Started | Jun 23 07:30:59 PM PDT 24 |
| Finished | Jun 23 07:31:20 PM PDT 24 |
| Peak memory | 574104 kb |
| Host | smart-584471e5-c2c4-4920-9fba-bc86013552a3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1241399735 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.xbar_random.1241399735 |
| Directory | /workspace/41.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/41.xbar_random_large_delays.1139560645 |
| Short name | T1550 |
| Test name | |
| Test status | |
| Simulation time | 10896259654 ps |
| CPU time | 110.27 seconds |
| Started | Jun 23 07:30:59 PM PDT 24 |
| Finished | Jun 23 07:32:49 PM PDT 24 |
| Peak memory | 574204 kb |
| Host | smart-21ae65e9-cd3a-4027-bac3-b73c9ccd530b |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1139560645 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.xbar_random_large_delays.1139560645 |
| Directory | /workspace/41.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/41.xbar_random_slow_rsp.4010136440 |
| Short name | T2879 |
| Test name | |
| Test status | |
| Simulation time | 30153352715 ps |
| CPU time | 482.71 seconds |
| Started | Jun 23 07:31:06 PM PDT 24 |
| Finished | Jun 23 07:39:09 PM PDT 24 |
| Peak memory | 574088 kb |
| Host | smart-9a416fd1-5ad3-4e52-9157-849db6db61c0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4010136440 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.xbar_random_slow_rsp.4010136440 |
| Directory | /workspace/41.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/41.xbar_random_zero_delays.2439214197 |
| Short name | T2710 |
| Test name | |
| Test status | |
| Simulation time | 251269151 ps |
| CPU time | 25.68 seconds |
| Started | Jun 23 07:30:59 PM PDT 24 |
| Finished | Jun 23 07:31:25 PM PDT 24 |
| Peak memory | 574096 kb |
| Host | smart-40c3aa83-f994-4827-998f-9a6c4433fa06 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2439214197 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.xbar_random_zero_del ays.2439214197 |
| Directory | /workspace/41.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/41.xbar_same_source.3217248395 |
| Short name | T448 |
| Test name | |
| Test status | |
| Simulation time | 2400780223 ps |
| CPU time | 70.86 seconds |
| Started | Jun 23 07:31:00 PM PDT 24 |
| Finished | Jun 23 07:32:11 PM PDT 24 |
| Peak memory | 574144 kb |
| Host | smart-e3c19104-2dae-4c48-aff5-f3fd5f47b864 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3217248395 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.xbar_same_source.3217248395 |
| Directory | /workspace/41.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/41.xbar_smoke.1355780866 |
| Short name | T1782 |
| Test name | |
| Test status | |
| Simulation time | 217992954 ps |
| CPU time | 9.65 seconds |
| Started | Jun 23 07:31:01 PM PDT 24 |
| Finished | Jun 23 07:31:11 PM PDT 24 |
| Peak memory | 565060 kb |
| Host | smart-351dc2f5-e2ef-46d0-ac66-f7c4fb40b570 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1355780866 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.xbar_smoke.1355780866 |
| Directory | /workspace/41.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/41.xbar_smoke_large_delays.571252355 |
| Short name | T645 |
| Test name | |
| Test status | |
| Simulation time | 9068613093 ps |
| CPU time | 97.56 seconds |
| Started | Jun 23 07:31:03 PM PDT 24 |
| Finished | Jun 23 07:32:41 PM PDT 24 |
| Peak memory | 565552 kb |
| Host | smart-51e6293b-d0e8-4fca-b202-e5e6cc432e13 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=571252355 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.xbar_smoke_large_delays.571252355 |
| Directory | /workspace/41.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/41.xbar_smoke_slow_rsp.1367640130 |
| Short name | T1560 |
| Test name | |
| Test status | |
| Simulation time | 5293696226 ps |
| CPU time | 93.62 seconds |
| Started | Jun 23 07:31:02 PM PDT 24 |
| Finished | Jun 23 07:32:35 PM PDT 24 |
| Peak memory | 565944 kb |
| Host | smart-a591b38b-e51a-4291-b589-be16da571e12 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1367640130 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.xbar_smoke_slow_rsp.1367640130 |
| Directory | /workspace/41.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/41.xbar_smoke_zero_delays.198363229 |
| Short name | T2162 |
| Test name | |
| Test status | |
| Simulation time | 37642355 ps |
| CPU time | 5.78 seconds |
| Started | Jun 23 07:31:06 PM PDT 24 |
| Finished | Jun 23 07:31:12 PM PDT 24 |
| Peak memory | 565080 kb |
| Host | smart-76bc64e1-71f7-4302-bc82-67055cba4502 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=198363229 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.xbar_smoke_zero_delays .198363229 |
| Directory | /workspace/41.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/41.xbar_stress_all.1547013910 |
| Short name | T588 |
| Test name | |
| Test status | |
| Simulation time | 1621316101 ps |
| CPU time | 127.33 seconds |
| Started | Jun 23 07:31:05 PM PDT 24 |
| Finished | Jun 23 07:33:13 PM PDT 24 |
| Peak memory | 574088 kb |
| Host | smart-778ae6f5-278b-47b0-8ad6-b13522d80497 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1547013910 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.xbar_stress_all.1547013910 |
| Directory | /workspace/41.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/41.xbar_stress_all_with_error.3490877879 |
| Short name | T1736 |
| Test name | |
| Test status | |
| Simulation time | 5134962053 ps |
| CPU time | 149.23 seconds |
| Started | Jun 23 07:31:04 PM PDT 24 |
| Finished | Jun 23 07:33:34 PM PDT 24 |
| Peak memory | 574288 kb |
| Host | smart-9c9e80eb-ab34-4347-9834-4d0f42b186fe |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3490877879 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.xbar_stress_all_with_error.3490877879 |
| Directory | /workspace/41.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/41.xbar_stress_all_with_rand_reset.292391122 |
| Short name | T890 |
| Test name | |
| Test status | |
| Simulation time | 226204283 ps |
| CPU time | 85.07 seconds |
| Started | Jun 23 07:31:00 PM PDT 24 |
| Finished | Jun 23 07:32:25 PM PDT 24 |
| Peak memory | 576268 kb |
| Host | smart-b3792ef7-8187-45db-a7d0-d3938825eb11 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=292391122 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_res et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.xbar_stress_all_ with_rand_reset.292391122 |
| Directory | /workspace/41.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/41.xbar_stress_all_with_reset_error.2018331707 |
| Short name | T1498 |
| Test name | |
| Test status | |
| Simulation time | 445621131 ps |
| CPU time | 128.11 seconds |
| Started | Jun 23 07:31:04 PM PDT 24 |
| Finished | Jun 23 07:33:12 PM PDT 24 |
| Peak memory | 576332 kb |
| Host | smart-9a56c47a-de5b-4326-9aed-30c075353682 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2018331707 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.xbar_stress_al l_with_reset_error.2018331707 |
| Directory | /workspace/41.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/41.xbar_unmapped_addr.3324735504 |
| Short name | T2480 |
| Test name | |
| Test status | |
| Simulation time | 230200867 ps |
| CPU time | 27.92 seconds |
| Started | Jun 23 07:30:59 PM PDT 24 |
| Finished | Jun 23 07:31:27 PM PDT 24 |
| Peak memory | 574104 kb |
| Host | smart-4bd5649e-df1e-4fa6-be36-0168430fd70b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3324735504 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.xbar_unmapped_addr.3324735504 |
| Directory | /workspace/41.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/42.xbar_access_same_device.601069002 |
| Short name | T1784 |
| Test name | |
| Test status | |
| Simulation time | 862874733 ps |
| CPU time | 74.13 seconds |
| Started | Jun 23 07:31:42 PM PDT 24 |
| Finished | Jun 23 07:32:56 PM PDT 24 |
| Peak memory | 574128 kb |
| Host | smart-9f1358ed-0a24-4285-9da5-219a04b61886 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=601069002 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.xbar_access_same_device. 601069002 |
| Directory | /workspace/42.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/42.xbar_access_same_device_slow_rsp.824267024 |
| Short name | T850 |
| Test name | |
| Test status | |
| Simulation time | 62464230265 ps |
| CPU time | 1111.74 seconds |
| Started | Jun 23 07:31:41 PM PDT 24 |
| Finished | Jun 23 07:50:14 PM PDT 24 |
| Peak memory | 574252 kb |
| Host | smart-c53b8ec7-568a-4676-ab93-56b697041746 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=824267024 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.xbar_access_same_d evice_slow_rsp.824267024 |
| Directory | /workspace/42.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/42.xbar_error_and_unmapped_addr.2341632592 |
| Short name | T2174 |
| Test name | |
| Test status | |
| Simulation time | 115519513 ps |
| CPU time | 13.85 seconds |
| Started | Jun 23 07:31:44 PM PDT 24 |
| Finished | Jun 23 07:31:58 PM PDT 24 |
| Peak memory | 573344 kb |
| Host | smart-c276681d-af96-43f1-9270-46ce110bfed2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2341632592 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.xbar_error_and_unmapped_add r.2341632592 |
| Directory | /workspace/42.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/42.xbar_error_random.2572669015 |
| Short name | T1562 |
| Test name | |
| Test status | |
| Simulation time | 1224137606 ps |
| CPU time | 40.69 seconds |
| Started | Jun 23 07:31:48 PM PDT 24 |
| Finished | Jun 23 07:32:29 PM PDT 24 |
| Peak memory | 573712 kb |
| Host | smart-158ee690-7d4c-4aa6-9b18-02096326d1f8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2572669015 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.xbar_error_random.2572669015 |
| Directory | /workspace/42.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/42.xbar_random.2854831856 |
| Short name | T1643 |
| Test name | |
| Test status | |
| Simulation time | 2143706119 ps |
| CPU time | 77.06 seconds |
| Started | Jun 23 07:31:39 PM PDT 24 |
| Finished | Jun 23 07:32:57 PM PDT 24 |
| Peak memory | 574132 kb |
| Host | smart-ae344438-2223-4cb7-ac78-e47d3b1e37bc |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2854831856 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.xbar_random.2854831856 |
| Directory | /workspace/42.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/42.xbar_random_large_delays.3275073612 |
| Short name | T660 |
| Test name | |
| Test status | |
| Simulation time | 51828478631 ps |
| CPU time | 549.54 seconds |
| Started | Jun 23 07:31:37 PM PDT 24 |
| Finished | Jun 23 07:40:47 PM PDT 24 |
| Peak memory | 574204 kb |
| Host | smart-3826e4de-2cba-4102-bdc9-9f11195b94f8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3275073612 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.xbar_random_large_delays.3275073612 |
| Directory | /workspace/42.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/42.xbar_random_slow_rsp.16418459 |
| Short name | T1628 |
| Test name | |
| Test status | |
| Simulation time | 47437150023 ps |
| CPU time | 876.58 seconds |
| Started | Jun 23 07:31:38 PM PDT 24 |
| Finished | Jun 23 07:46:15 PM PDT 24 |
| Peak memory | 574156 kb |
| Host | smart-1a891310-d405-4d11-8b59-56d7758f5917 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16418459 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.xbar_random_slow_rsp.16418459 |
| Directory | /workspace/42.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/42.xbar_random_zero_delays.1198493554 |
| Short name | T2397 |
| Test name | |
| Test status | |
| Simulation time | 201158033 ps |
| CPU time | 17.63 seconds |
| Started | Jun 23 07:31:37 PM PDT 24 |
| Finished | Jun 23 07:31:54 PM PDT 24 |
| Peak memory | 573376 kb |
| Host | smart-10f751dc-114e-4057-a09f-c43e783e26df |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1198493554 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.xbar_random_zero_del ays.1198493554 |
| Directory | /workspace/42.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/42.xbar_same_source.115935690 |
| Short name | T1661 |
| Test name | |
| Test status | |
| Simulation time | 2369514205 ps |
| CPU time | 73.84 seconds |
| Started | Jun 23 07:31:46 PM PDT 24 |
| Finished | Jun 23 07:33:00 PM PDT 24 |
| Peak memory | 574120 kb |
| Host | smart-401ecae4-881e-4301-8273-fbd1fa58bb2a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=115935690 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.xbar_same_source.115935690 |
| Directory | /workspace/42.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/42.xbar_smoke.2510026519 |
| Short name | T2169 |
| Test name | |
| Test status | |
| Simulation time | 226060981 ps |
| CPU time | 9.92 seconds |
| Started | Jun 23 07:31:38 PM PDT 24 |
| Finished | Jun 23 07:31:48 PM PDT 24 |
| Peak memory | 565728 kb |
| Host | smart-6d6be09a-9df5-4b9a-8f98-370699fd7a2b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2510026519 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.xbar_smoke.2510026519 |
| Directory | /workspace/42.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/42.xbar_smoke_large_delays.4209888162 |
| Short name | T1441 |
| Test name | |
| Test status | |
| Simulation time | 5728341452 ps |
| CPU time | 61.79 seconds |
| Started | Jun 23 07:31:37 PM PDT 24 |
| Finished | Jun 23 07:32:39 PM PDT 24 |
| Peak memory | 565548 kb |
| Host | smart-d675db64-6643-441d-a3b1-dbe657264a9f |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4209888162 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.xbar_smoke_large_delays.4209888162 |
| Directory | /workspace/42.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/42.xbar_smoke_slow_rsp.3111498073 |
| Short name | T2635 |
| Test name | |
| Test status | |
| Simulation time | 5806413608 ps |
| CPU time | 95.87 seconds |
| Started | Jun 23 07:31:38 PM PDT 24 |
| Finished | Jun 23 07:33:14 PM PDT 24 |
| Peak memory | 565936 kb |
| Host | smart-e0881105-c38e-4b16-a56d-8fc6629b84e9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3111498073 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.xbar_smoke_slow_rsp.3111498073 |
| Directory | /workspace/42.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/42.xbar_smoke_zero_delays.2837882843 |
| Short name | T2713 |
| Test name | |
| Test status | |
| Simulation time | 51844239 ps |
| CPU time | 6.64 seconds |
| Started | Jun 23 07:31:37 PM PDT 24 |
| Finished | Jun 23 07:31:44 PM PDT 24 |
| Peak memory | 565516 kb |
| Host | smart-e060bd8f-ddf1-4188-b720-ca1262cef6bf |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2837882843 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.xbar_smoke_zero_delay s.2837882843 |
| Directory | /workspace/42.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/42.xbar_stress_all.406083487 |
| Short name | T2568 |
| Test name | |
| Test status | |
| Simulation time | 12039134827 ps |
| CPU time | 432.69 seconds |
| Started | Jun 23 07:31:44 PM PDT 24 |
| Finished | Jun 23 07:38:57 PM PDT 24 |
| Peak memory | 574228 kb |
| Host | smart-01923524-6903-4dad-91df-4d5a4da91069 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=406083487 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.xbar_stress_all.406083487 |
| Directory | /workspace/42.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/42.xbar_stress_all_with_error.3267385883 |
| Short name | T2231 |
| Test name | |
| Test status | |
| Simulation time | 3720076824 ps |
| CPU time | 122.08 seconds |
| Started | Jun 23 07:31:43 PM PDT 24 |
| Finished | Jun 23 07:33:45 PM PDT 24 |
| Peak memory | 573472 kb |
| Host | smart-8a15f661-0fb8-4f5f-863f-a9f824bd8a11 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3267385883 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.xbar_stress_all_with_error.3267385883 |
| Directory | /workspace/42.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/42.xbar_stress_all_with_rand_reset.136822069 |
| Short name | T478 |
| Test name | |
| Test status | |
| Simulation time | 5304386443 ps |
| CPU time | 308.45 seconds |
| Started | Jun 23 07:31:42 PM PDT 24 |
| Finished | Jun 23 07:36:51 PM PDT 24 |
| Peak memory | 577384 kb |
| Host | smart-7e8dcc82-4c88-452c-9356-6f145a8b1037 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=136822069 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_res et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.xbar_stress_all_ with_rand_reset.136822069 |
| Directory | /workspace/42.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/42.xbar_stress_all_with_reset_error.981565402 |
| Short name | T2402 |
| Test name | |
| Test status | |
| Simulation time | 2644101955 ps |
| CPU time | 309.72 seconds |
| Started | Jun 23 07:31:49 PM PDT 24 |
| Finished | Jun 23 07:36:59 PM PDT 24 |
| Peak memory | 574368 kb |
| Host | smart-1a0d04c5-5e2a-437a-9473-b1c548b62f0c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=981565402 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.xbar_stress_all _with_reset_error.981565402 |
| Directory | /workspace/42.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/42.xbar_unmapped_addr.3446023271 |
| Short name | T1425 |
| Test name | |
| Test status | |
| Simulation time | 101596846 ps |
| CPU time | 14.4 seconds |
| Started | Jun 23 07:31:43 PM PDT 24 |
| Finished | Jun 23 07:31:58 PM PDT 24 |
| Peak memory | 574100 kb |
| Host | smart-f13ef4ff-8006-4e13-a67d-ef7067452f5d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3446023271 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.xbar_unmapped_addr.3446023271 |
| Directory | /workspace/42.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/43.xbar_access_same_device.4034793305 |
| Short name | T1609 |
| Test name | |
| Test status | |
| Simulation time | 1426651296 ps |
| CPU time | 60.36 seconds |
| Started | Jun 23 07:31:43 PM PDT 24 |
| Finished | Jun 23 07:32:44 PM PDT 24 |
| Peak memory | 574084 kb |
| Host | smart-c2f4297f-57ca-4a4a-aae0-2199b5f77a8f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4034793305 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.xbar_access_same_device .4034793305 |
| Directory | /workspace/43.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/43.xbar_access_same_device_slow_rsp.1692178517 |
| Short name | T2512 |
| Test name | |
| Test status | |
| Simulation time | 15787600699 ps |
| CPU time | 278.63 seconds |
| Started | Jun 23 07:31:45 PM PDT 24 |
| Finished | Jun 23 07:36:24 PM PDT 24 |
| Peak memory | 574212 kb |
| Host | smart-9d3e64e4-56b2-44b6-a38f-df7899db97bd |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1692178517 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.xbar_access_same_ device_slow_rsp.1692178517 |
| Directory | /workspace/43.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/43.xbar_error_and_unmapped_addr.918714195 |
| Short name | T1392 |
| Test name | |
| Test status | |
| Simulation time | 819697455 ps |
| CPU time | 37.45 seconds |
| Started | Jun 23 07:31:41 PM PDT 24 |
| Finished | Jun 23 07:32:19 PM PDT 24 |
| Peak memory | 573664 kb |
| Host | smart-048950ee-279b-4409-b602-02eca4b6d7b0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=918714195 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.xbar_error_and_unmapped_addr .918714195 |
| Directory | /workspace/43.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/43.xbar_error_random.4136206809 |
| Short name | T1750 |
| Test name | |
| Test status | |
| Simulation time | 1243397928 ps |
| CPU time | 39.61 seconds |
| Started | Jun 23 07:31:43 PM PDT 24 |
| Finished | Jun 23 07:32:23 PM PDT 24 |
| Peak memory | 573712 kb |
| Host | smart-cf6d2d92-535b-498f-9f9b-45552ea0dfb3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4136206809 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.xbar_error_random.4136206809 |
| Directory | /workspace/43.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/43.xbar_random.3049539623 |
| Short name | T2629 |
| Test name | |
| Test status | |
| Simulation time | 297339556 ps |
| CPU time | 24.8 seconds |
| Started | Jun 23 07:31:45 PM PDT 24 |
| Finished | Jun 23 07:32:10 PM PDT 24 |
| Peak memory | 573440 kb |
| Host | smart-cb20d07d-d89b-40cb-b3ac-751919a2168d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3049539623 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.xbar_random.3049539623 |
| Directory | /workspace/43.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/43.xbar_random_large_delays.4234384270 |
| Short name | T624 |
| Test name | |
| Test status | |
| Simulation time | 56070811853 ps |
| CPU time | 602.2 seconds |
| Started | Jun 23 07:31:45 PM PDT 24 |
| Finished | Jun 23 07:41:48 PM PDT 24 |
| Peak memory | 573448 kb |
| Host | smart-42261908-80e4-41b2-a2a7-d71ab1e79bf9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4234384270 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.xbar_random_large_delays.4234384270 |
| Directory | /workspace/43.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/43.xbar_random_slow_rsp.1991844259 |
| Short name | T2735 |
| Test name | |
| Test status | |
| Simulation time | 36509774698 ps |
| CPU time | 634.03 seconds |
| Started | Jun 23 07:31:45 PM PDT 24 |
| Finished | Jun 23 07:42:20 PM PDT 24 |
| Peak memory | 574164 kb |
| Host | smart-7a2a1633-6fa2-4a56-bfc4-14c712c451fe |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1991844259 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.xbar_random_slow_rsp.1991844259 |
| Directory | /workspace/43.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/43.xbar_random_zero_delays.4021973035 |
| Short name | T2021 |
| Test name | |
| Test status | |
| Simulation time | 273837490 ps |
| CPU time | 27.31 seconds |
| Started | Jun 23 07:31:43 PM PDT 24 |
| Finished | Jun 23 07:32:11 PM PDT 24 |
| Peak memory | 573712 kb |
| Host | smart-198523c8-7591-42ad-bb73-ba37f52f23c5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4021973035 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.xbar_random_zero_del ays.4021973035 |
| Directory | /workspace/43.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/43.xbar_same_source.1960152494 |
| Short name | T1464 |
| Test name | |
| Test status | |
| Simulation time | 2161352295 ps |
| CPU time | 61.15 seconds |
| Started | Jun 23 07:31:43 PM PDT 24 |
| Finished | Jun 23 07:32:45 PM PDT 24 |
| Peak memory | 574148 kb |
| Host | smart-9c336c25-dbcd-4899-bd1c-c88db7646a71 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1960152494 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.xbar_same_source.1960152494 |
| Directory | /workspace/43.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/43.xbar_smoke.2123573749 |
| Short name | T1489 |
| Test name | |
| Test status | |
| Simulation time | 41007943 ps |
| CPU time | 6.1 seconds |
| Started | Jun 23 07:31:42 PM PDT 24 |
| Finished | Jun 23 07:31:49 PM PDT 24 |
| Peak memory | 565512 kb |
| Host | smart-4b257208-9d60-492f-897c-757ed46edff3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2123573749 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.xbar_smoke.2123573749 |
| Directory | /workspace/43.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/43.xbar_smoke_large_delays.2888646813 |
| Short name | T2604 |
| Test name | |
| Test status | |
| Simulation time | 8241755265 ps |
| CPU time | 82.66 seconds |
| Started | Jun 23 07:31:45 PM PDT 24 |
| Finished | Jun 23 07:33:07 PM PDT 24 |
| Peak memory | 565548 kb |
| Host | smart-dc152178-6e0a-4333-b6bf-cb82922d3344 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2888646813 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.xbar_smoke_large_delays.2888646813 |
| Directory | /workspace/43.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/43.xbar_smoke_slow_rsp.1967387424 |
| Short name | T2291 |
| Test name | |
| Test status | |
| Simulation time | 4642530414 ps |
| CPU time | 79.85 seconds |
| Started | Jun 23 07:31:45 PM PDT 24 |
| Finished | Jun 23 07:33:05 PM PDT 24 |
| Peak memory | 565300 kb |
| Host | smart-77589efd-ef74-4235-9987-635172b28fa3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1967387424 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.xbar_smoke_slow_rsp.1967387424 |
| Directory | /workspace/43.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/43.xbar_smoke_zero_delays.338428356 |
| Short name | T1427 |
| Test name | |
| Test status | |
| Simulation time | 39485670 ps |
| CPU time | 6.05 seconds |
| Started | Jun 23 07:31:48 PM PDT 24 |
| Finished | Jun 23 07:31:54 PM PDT 24 |
| Peak memory | 565548 kb |
| Host | smart-5c33a38f-cc81-48ee-9a3e-fd5ebfd74ef0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=338428356 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.xbar_smoke_zero_delays .338428356 |
| Directory | /workspace/43.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/43.xbar_stress_all.3424747194 |
| Short name | T464 |
| Test name | |
| Test status | |
| Simulation time | 7590624774 ps |
| CPU time | 301.27 seconds |
| Started | Jun 23 07:31:43 PM PDT 24 |
| Finished | Jun 23 07:36:44 PM PDT 24 |
| Peak memory | 574264 kb |
| Host | smart-d8e2b2c2-66e2-4012-bbd1-73e745f0b924 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3424747194 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.xbar_stress_all.3424747194 |
| Directory | /workspace/43.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/43.xbar_stress_all_with_error.3230633328 |
| Short name | T2537 |
| Test name | |
| Test status | |
| Simulation time | 7040542971 ps |
| CPU time | 539.23 seconds |
| Started | Jun 23 07:31:43 PM PDT 24 |
| Finished | Jun 23 07:40:42 PM PDT 24 |
| Peak memory | 574376 kb |
| Host | smart-d42d0794-0bbe-4ab7-8210-bd4bf763df07 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3230633328 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.xbar_stress_all_with_error.3230633328 |
| Directory | /workspace/43.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/43.xbar_stress_all_with_rand_reset.3403109195 |
| Short name | T545 |
| Test name | |
| Test status | |
| Simulation time | 4238637499 ps |
| CPU time | 426.33 seconds |
| Started | Jun 23 07:31:45 PM PDT 24 |
| Finished | Jun 23 07:38:52 PM PDT 24 |
| Peak memory | 574260 kb |
| Host | smart-924ba6c2-e3a2-4ae8-be06-4313006f9ae2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3403109195 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.xbar_stress_all _with_rand_reset.3403109195 |
| Directory | /workspace/43.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/43.xbar_stress_all_with_reset_error.1711559020 |
| Short name | T2437 |
| Test name | |
| Test status | |
| Simulation time | 7253681795 ps |
| CPU time | 293.42 seconds |
| Started | Jun 23 07:31:43 PM PDT 24 |
| Finished | Jun 23 07:36:37 PM PDT 24 |
| Peak memory | 574312 kb |
| Host | smart-190bfaeb-bcbc-422b-b22f-9a8058d65f73 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1711559020 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.xbar_stress_al l_with_reset_error.1711559020 |
| Directory | /workspace/43.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/43.xbar_unmapped_addr.2238335458 |
| Short name | T1718 |
| Test name | |
| Test status | |
| Simulation time | 78224345 ps |
| CPU time | 10.92 seconds |
| Started | Jun 23 07:31:44 PM PDT 24 |
| Finished | Jun 23 07:31:56 PM PDT 24 |
| Peak memory | 573420 kb |
| Host | smart-438f5660-4499-43ef-89f1-05ec43e3a4f1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2238335458 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.xbar_unmapped_addr.2238335458 |
| Directory | /workspace/43.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/44.xbar_access_same_device.3757488258 |
| Short name | T1421 |
| Test name | |
| Test status | |
| Simulation time | 103716441 ps |
| CPU time | 9.42 seconds |
| Started | Jun 23 07:31:43 PM PDT 24 |
| Finished | Jun 23 07:31:53 PM PDT 24 |
| Peak memory | 565476 kb |
| Host | smart-416ff6f6-e76a-439e-8602-a3d42e636d17 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3757488258 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.xbar_access_same_device .3757488258 |
| Directory | /workspace/44.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/44.xbar_access_same_device_slow_rsp.688657240 |
| Short name | T1933 |
| Test name | |
| Test status | |
| Simulation time | 2556140016 ps |
| CPU time | 44.34 seconds |
| Started | Jun 23 07:31:45 PM PDT 24 |
| Finished | Jun 23 07:32:30 PM PDT 24 |
| Peak memory | 565936 kb |
| Host | smart-b1f87ba1-58ed-45d4-b89c-d628d2409d28 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=688657240 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.xbar_access_same_d evice_slow_rsp.688657240 |
| Directory | /workspace/44.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/44.xbar_error_and_unmapped_addr.1574595964 |
| Short name | T1366 |
| Test name | |
| Test status | |
| Simulation time | 56085386 ps |
| CPU time | 8.34 seconds |
| Started | Jun 23 07:31:48 PM PDT 24 |
| Finished | Jun 23 07:31:57 PM PDT 24 |
| Peak memory | 573732 kb |
| Host | smart-27f3133f-9d98-49c0-9ae0-777ecbcdbf64 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1574595964 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.xbar_error_and_unmapped_add r.1574595964 |
| Directory | /workspace/44.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/44.xbar_error_random.4087420751 |
| Short name | T2000 |
| Test name | |
| Test status | |
| Simulation time | 2202854320 ps |
| CPU time | 68.85 seconds |
| Started | Jun 23 07:31:42 PM PDT 24 |
| Finished | Jun 23 07:32:51 PM PDT 24 |
| Peak memory | 573360 kb |
| Host | smart-fb72b41d-9abc-45a7-8c39-ad15be71fdaa |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4087420751 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.xbar_error_random.4087420751 |
| Directory | /workspace/44.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/44.xbar_random.1113884569 |
| Short name | T1697 |
| Test name | |
| Test status | |
| Simulation time | 961277326 ps |
| CPU time | 32.56 seconds |
| Started | Jun 23 07:31:48 PM PDT 24 |
| Finished | Jun 23 07:32:21 PM PDT 24 |
| Peak memory | 574236 kb |
| Host | smart-b1bc3720-8bba-4fb7-8632-9f3c61a5bf90 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1113884569 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.xbar_random.1113884569 |
| Directory | /workspace/44.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/44.xbar_random_large_delays.2665309965 |
| Short name | T1685 |
| Test name | |
| Test status | |
| Simulation time | 22999362905 ps |
| CPU time | 239 seconds |
| Started | Jun 23 07:31:49 PM PDT 24 |
| Finished | Jun 23 07:35:48 PM PDT 24 |
| Peak memory | 574208 kb |
| Host | smart-6059291d-d1ea-466c-b7a1-3016a53c4d18 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2665309965 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.xbar_random_large_delays.2665309965 |
| Directory | /workspace/44.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/44.xbar_random_slow_rsp.3883863247 |
| Short name | T2386 |
| Test name | |
| Test status | |
| Simulation time | 31276741482 ps |
| CPU time | 556.08 seconds |
| Started | Jun 23 07:31:46 PM PDT 24 |
| Finished | Jun 23 07:41:03 PM PDT 24 |
| Peak memory | 573676 kb |
| Host | smart-851de80e-9ae6-4f9c-aa31-57b643f5ada0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3883863247 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.xbar_random_slow_rsp.3883863247 |
| Directory | /workspace/44.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/44.xbar_random_zero_delays.1120148358 |
| Short name | T1805 |
| Test name | |
| Test status | |
| Simulation time | 232733718 ps |
| CPU time | 23.67 seconds |
| Started | Jun 23 07:31:46 PM PDT 24 |
| Finished | Jun 23 07:32:10 PM PDT 24 |
| Peak memory | 573424 kb |
| Host | smart-5264a5ce-7773-4927-802e-8725dccc036e |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1120148358 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.xbar_random_zero_del ays.1120148358 |
| Directory | /workspace/44.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/44.xbar_same_source.2279730270 |
| Short name | T597 |
| Test name | |
| Test status | |
| Simulation time | 235185385 ps |
| CPU time | 18.28 seconds |
| Started | Jun 23 07:31:44 PM PDT 24 |
| Finished | Jun 23 07:32:02 PM PDT 24 |
| Peak memory | 574088 kb |
| Host | smart-41a1ccda-27d4-4a34-a7a6-3711ed5fd39f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2279730270 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.xbar_same_source.2279730270 |
| Directory | /workspace/44.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/44.xbar_smoke.2297514863 |
| Short name | T1894 |
| Test name | |
| Test status | |
| Simulation time | 232676019 ps |
| CPU time | 10.34 seconds |
| Started | Jun 23 07:31:46 PM PDT 24 |
| Finished | Jun 23 07:31:56 PM PDT 24 |
| Peak memory | 565860 kb |
| Host | smart-c302b010-eee6-4fe2-a509-2c790f0e32a2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2297514863 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.xbar_smoke.2297514863 |
| Directory | /workspace/44.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/44.xbar_smoke_large_delays.2208195097 |
| Short name | T2539 |
| Test name | |
| Test status | |
| Simulation time | 6796732959 ps |
| CPU time | 76.63 seconds |
| Started | Jun 23 07:31:45 PM PDT 24 |
| Finished | Jun 23 07:33:03 PM PDT 24 |
| Peak memory | 565180 kb |
| Host | smart-ccb10b51-fab9-4457-9b63-9a5e804a849d |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2208195097 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.xbar_smoke_large_delays.2208195097 |
| Directory | /workspace/44.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/44.xbar_smoke_slow_rsp.761928406 |
| Short name | T1454 |
| Test name | |
| Test status | |
| Simulation time | 6148424070 ps |
| CPU time | 99.96 seconds |
| Started | Jun 23 07:31:48 PM PDT 24 |
| Finished | Jun 23 07:33:28 PM PDT 24 |
| Peak memory | 565548 kb |
| Host | smart-5dc98f57-d3d9-4856-9b8c-2ebc5abfb150 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=761928406 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.xbar_smoke_slow_rsp.761928406 |
| Directory | /workspace/44.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/44.xbar_smoke_zero_delays.709044503 |
| Short name | T1553 |
| Test name | |
| Test status | |
| Simulation time | 56280683 ps |
| CPU time | 6.75 seconds |
| Started | Jun 23 07:31:46 PM PDT 24 |
| Finished | Jun 23 07:31:53 PM PDT 24 |
| Peak memory | 565532 kb |
| Host | smart-13a5f204-6350-4898-bf67-9caad7342b6a |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=709044503 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.xbar_smoke_zero_delays .709044503 |
| Directory | /workspace/44.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/44.xbar_stress_all.2317647476 |
| Short name | T494 |
| Test name | |
| Test status | |
| Simulation time | 1657731730 ps |
| CPU time | 145.05 seconds |
| Started | Jun 23 07:31:47 PM PDT 24 |
| Finished | Jun 23 07:34:12 PM PDT 24 |
| Peak memory | 573940 kb |
| Host | smart-d9cb3c25-a14e-4983-9d45-9506e00ca27a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2317647476 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.xbar_stress_all.2317647476 |
| Directory | /workspace/44.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/44.xbar_stress_all_with_error.50740398 |
| Short name | T2428 |
| Test name | |
| Test status | |
| Simulation time | 10063155817 ps |
| CPU time | 304.03 seconds |
| Started | Jun 23 07:31:50 PM PDT 24 |
| Finished | Jun 23 07:36:54 PM PDT 24 |
| Peak memory | 573584 kb |
| Host | smart-3da4dae4-8f9c-4959-8779-b23ec9560ac7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50740398 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.xbar_stress_all_with_error.50740398 |
| Directory | /workspace/44.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/44.xbar_stress_all_with_rand_reset.1585045515 |
| Short name | T2063 |
| Test name | |
| Test status | |
| Simulation time | 2132626178 ps |
| CPU time | 347.79 seconds |
| Started | Jun 23 07:31:47 PM PDT 24 |
| Finished | Jun 23 07:37:36 PM PDT 24 |
| Peak memory | 574272 kb |
| Host | smart-5a9ff37f-b619-446b-bfca-33c2396de5c8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1585045515 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.xbar_stress_all _with_rand_reset.1585045515 |
| Directory | /workspace/44.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/44.xbar_stress_all_with_reset_error.3505964871 |
| Short name | T1895 |
| Test name | |
| Test status | |
| Simulation time | 5891607557 ps |
| CPU time | 411.02 seconds |
| Started | Jun 23 07:31:46 PM PDT 24 |
| Finished | Jun 23 07:38:38 PM PDT 24 |
| Peak memory | 576420 kb |
| Host | smart-0a38bc38-e27b-4e58-ab0e-17931f88ff97 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3505964871 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.xbar_stress_al l_with_reset_error.3505964871 |
| Directory | /workspace/44.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/44.xbar_unmapped_addr.3263633735 |
| Short name | T2768 |
| Test name | |
| Test status | |
| Simulation time | 240348933 ps |
| CPU time | 29.86 seconds |
| Started | Jun 23 07:31:44 PM PDT 24 |
| Finished | Jun 23 07:32:14 PM PDT 24 |
| Peak memory | 573436 kb |
| Host | smart-d1acbade-2097-4c4d-bebb-3d71d45c2f46 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3263633735 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.xbar_unmapped_addr.3263633735 |
| Directory | /workspace/44.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/45.xbar_access_same_device.3064991893 |
| Short name | T1667 |
| Test name | |
| Test status | |
| Simulation time | 52687092 ps |
| CPU time | 7.44 seconds |
| Started | Jun 23 07:31:53 PM PDT 24 |
| Finished | Jun 23 07:32:01 PM PDT 24 |
| Peak memory | 565136 kb |
| Host | smart-2ad36ab2-452c-43ed-8306-5734921f7320 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3064991893 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.xbar_access_same_device .3064991893 |
| Directory | /workspace/45.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/45.xbar_access_same_device_slow_rsp.4117299407 |
| Short name | T654 |
| Test name | |
| Test status | |
| Simulation time | 151687245089 ps |
| CPU time | 2980.96 seconds |
| Started | Jun 23 07:31:53 PM PDT 24 |
| Finished | Jun 23 08:21:35 PM PDT 24 |
| Peak memory | 574220 kb |
| Host | smart-0473971c-bbba-4c0d-a22c-d593835d7b52 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4117299407 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.xbar_access_same_ device_slow_rsp.4117299407 |
| Directory | /workspace/45.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/45.xbar_error_and_unmapped_addr.2515590889 |
| Short name | T1706 |
| Test name | |
| Test status | |
| Simulation time | 799794953 ps |
| CPU time | 30.68 seconds |
| Started | Jun 23 07:32:28 PM PDT 24 |
| Finished | Jun 23 07:33:00 PM PDT 24 |
| Peak memory | 573680 kb |
| Host | smart-8ed3ba95-e1f4-424b-8cb2-e644fb91b33d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2515590889 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.xbar_error_and_unmapped_add r.2515590889 |
| Directory | /workspace/45.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/45.xbar_error_random.575569369 |
| Short name | T1479 |
| Test name | |
| Test status | |
| Simulation time | 271205719 ps |
| CPU time | 10.93 seconds |
| Started | Jun 23 07:31:55 PM PDT 24 |
| Finished | Jun 23 07:32:07 PM PDT 24 |
| Peak memory | 573724 kb |
| Host | smart-a0f3ddb0-3918-4bd8-9003-2ee3b6d08865 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=575569369 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.xbar_error_random.575569369 |
| Directory | /workspace/45.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/45.xbar_random.472704871 |
| Short name | T2292 |
| Test name | |
| Test status | |
| Simulation time | 2046301022 ps |
| CPU time | 67.55 seconds |
| Started | Jun 23 07:31:58 PM PDT 24 |
| Finished | Jun 23 07:33:06 PM PDT 24 |
| Peak memory | 574056 kb |
| Host | smart-49de1f24-00fc-493f-8e32-24292dd5406e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=472704871 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.xbar_random.472704871 |
| Directory | /workspace/45.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/45.xbar_random_large_delays.853813669 |
| Short name | T2691 |
| Test name | |
| Test status | |
| Simulation time | 3158696387 ps |
| CPU time | 35.35 seconds |
| Started | Jun 23 07:31:55 PM PDT 24 |
| Finished | Jun 23 07:32:31 PM PDT 24 |
| Peak memory | 565956 kb |
| Host | smart-250e5b1e-c678-43be-935f-15185f5c2345 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=853813669 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.xbar_random_large_delays.853813669 |
| Directory | /workspace/45.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/45.xbar_random_slow_rsp.3635560631 |
| Short name | T2061 |
| Test name | |
| Test status | |
| Simulation time | 26500996214 ps |
| CPU time | 448.5 seconds |
| Started | Jun 23 07:31:54 PM PDT 24 |
| Finished | Jun 23 07:39:23 PM PDT 24 |
| Peak memory | 574168 kb |
| Host | smart-4105bec0-267c-41f5-8011-f9c0e2441d9b |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3635560631 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.xbar_random_slow_rsp.3635560631 |
| Directory | /workspace/45.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/45.xbar_random_zero_delays.1799678562 |
| Short name | T2183 |
| Test name | |
| Test status | |
| Simulation time | 68831847 ps |
| CPU time | 8.16 seconds |
| Started | Jun 23 07:31:52 PM PDT 24 |
| Finished | Jun 23 07:32:01 PM PDT 24 |
| Peak memory | 574068 kb |
| Host | smart-830ff76f-6059-41ef-8226-7d458b82cc3d |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1799678562 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.xbar_random_zero_del ays.1799678562 |
| Directory | /workspace/45.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/45.xbar_same_source.4183737901 |
| Short name | T2677 |
| Test name | |
| Test status | |
| Simulation time | 1527660288 ps |
| CPU time | 42.79 seconds |
| Started | Jun 23 07:31:52 PM PDT 24 |
| Finished | Jun 23 07:32:35 PM PDT 24 |
| Peak memory | 573676 kb |
| Host | smart-204b26f7-9e9d-44dd-9c99-f5b958087d8a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4183737901 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.xbar_same_source.4183737901 |
| Directory | /workspace/45.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/45.xbar_smoke.194367666 |
| Short name | T2094 |
| Test name | |
| Test status | |
| Simulation time | 183363863 ps |
| CPU time | 8.52 seconds |
| Started | Jun 23 07:31:56 PM PDT 24 |
| Finished | Jun 23 07:32:05 PM PDT 24 |
| Peak memory | 565520 kb |
| Host | smart-14ec5f79-5f8c-4c1f-ad5f-1a0c05b64a98 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=194367666 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.xbar_smoke.194367666 |
| Directory | /workspace/45.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/45.xbar_smoke_large_delays.2288432763 |
| Short name | T1991 |
| Test name | |
| Test status | |
| Simulation time | 6629261068 ps |
| CPU time | 69.55 seconds |
| Started | Jun 23 07:31:54 PM PDT 24 |
| Finished | Jun 23 07:33:04 PM PDT 24 |
| Peak memory | 565252 kb |
| Host | smart-965144e1-f2b3-4b80-98d9-b36b649c9fe5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2288432763 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.xbar_smoke_large_delays.2288432763 |
| Directory | /workspace/45.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/45.xbar_smoke_slow_rsp.2052924694 |
| Short name | T1455 |
| Test name | |
| Test status | |
| Simulation time | 5585314775 ps |
| CPU time | 90.24 seconds |
| Started | Jun 23 07:31:54 PM PDT 24 |
| Finished | Jun 23 07:33:25 PM PDT 24 |
| Peak memory | 565540 kb |
| Host | smart-6d2781b0-416c-421a-8f8f-ea25b14f36b6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2052924694 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.xbar_smoke_slow_rsp.2052924694 |
| Directory | /workspace/45.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/45.xbar_smoke_zero_delays.2969325543 |
| Short name | T2623 |
| Test name | |
| Test status | |
| Simulation time | 41455844 ps |
| CPU time | 6.05 seconds |
| Started | Jun 23 07:31:51 PM PDT 24 |
| Finished | Jun 23 07:31:58 PM PDT 24 |
| Peak memory | 565484 kb |
| Host | smart-ac785d64-a9f2-4d80-a253-716e25ee0eb6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2969325543 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.xbar_smoke_zero_delay s.2969325543 |
| Directory | /workspace/45.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/45.xbar_stress_all.2576407049 |
| Short name | T582 |
| Test name | |
| Test status | |
| Simulation time | 3471954342 ps |
| CPU time | 121.74 seconds |
| Started | Jun 23 07:32:28 PM PDT 24 |
| Finished | Jun 23 07:34:31 PM PDT 24 |
| Peak memory | 574244 kb |
| Host | smart-bc29c3d0-a676-4edb-bc86-8c6c3e18b286 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2576407049 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.xbar_stress_all.2576407049 |
| Directory | /workspace/45.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/45.xbar_stress_all_with_error.1201540237 |
| Short name | T2214 |
| Test name | |
| Test status | |
| Simulation time | 11289061246 ps |
| CPU time | 451.31 seconds |
| Started | Jun 23 07:32:26 PM PDT 24 |
| Finished | Jun 23 07:39:57 PM PDT 24 |
| Peak memory | 574296 kb |
| Host | smart-28ce71f1-ebb7-4ccd-8ac4-7aecce51417f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1201540237 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.xbar_stress_all_with_error.1201540237 |
| Directory | /workspace/45.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/45.xbar_stress_all_with_rand_reset.1447264437 |
| Short name | T888 |
| Test name | |
| Test status | |
| Simulation time | 835349626 ps |
| CPU time | 280.26 seconds |
| Started | Jun 23 07:32:30 PM PDT 24 |
| Finished | Jun 23 07:37:11 PM PDT 24 |
| Peak memory | 574148 kb |
| Host | smart-49851920-85f0-4d7a-804b-4557b7d9c01b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1447264437 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.xbar_stress_all _with_rand_reset.1447264437 |
| Directory | /workspace/45.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/45.xbar_stress_all_with_reset_error.3555660501 |
| Short name | T2827 |
| Test name | |
| Test status | |
| Simulation time | 2272869132 ps |
| CPU time | 287.37 seconds |
| Started | Jun 23 07:32:28 PM PDT 24 |
| Finished | Jun 23 07:37:16 PM PDT 24 |
| Peak memory | 574376 kb |
| Host | smart-7154545b-fb4e-4fc5-9ff4-a3c0b13610f2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3555660501 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.xbar_stress_al l_with_reset_error.3555660501 |
| Directory | /workspace/45.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/45.xbar_unmapped_addr.3700826118 |
| Short name | T1765 |
| Test name | |
| Test status | |
| Simulation time | 218705280 ps |
| CPU time | 28.26 seconds |
| Started | Jun 23 07:32:27 PM PDT 24 |
| Finished | Jun 23 07:32:57 PM PDT 24 |
| Peak memory | 574152 kb |
| Host | smart-a26e433c-a650-41ba-b410-2dcfc21d1683 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3700826118 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.xbar_unmapped_addr.3700826118 |
| Directory | /workspace/45.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/46.xbar_access_same_device.1005076063 |
| Short name | T2229 |
| Test name | |
| Test status | |
| Simulation time | 2254580495 ps |
| CPU time | 84.62 seconds |
| Started | Jun 23 07:32:27 PM PDT 24 |
| Finished | Jun 23 07:33:52 PM PDT 24 |
| Peak memory | 574132 kb |
| Host | smart-276e1350-06a0-46de-b676-2530ca121b1e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1005076063 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.xbar_access_same_device .1005076063 |
| Directory | /workspace/46.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/46.xbar_access_same_device_slow_rsp.1394073189 |
| Short name | T1663 |
| Test name | |
| Test status | |
| Simulation time | 51002787933 ps |
| CPU time | 789.69 seconds |
| Started | Jun 23 07:32:39 PM PDT 24 |
| Finished | Jun 23 07:45:50 PM PDT 24 |
| Peak memory | 573508 kb |
| Host | smart-7ff133f1-6b67-4ea6-adc8-716b3566e8ea |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1394073189 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.xbar_access_same_ device_slow_rsp.1394073189 |
| Directory | /workspace/46.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/46.xbar_error_and_unmapped_addr.1191821727 |
| Short name | T1577 |
| Test name | |
| Test status | |
| Simulation time | 256407252 ps |
| CPU time | 28.77 seconds |
| Started | Jun 23 07:32:41 PM PDT 24 |
| Finished | Jun 23 07:33:10 PM PDT 24 |
| Peak memory | 573324 kb |
| Host | smart-a01a29ea-9163-474c-a431-5e2cbd66424a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1191821727 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.xbar_error_and_unmapped_add r.1191821727 |
| Directory | /workspace/46.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/46.xbar_error_random.590289782 |
| Short name | T2484 |
| Test name | |
| Test status | |
| Simulation time | 2066699274 ps |
| CPU time | 72.36 seconds |
| Started | Jun 23 07:32:39 PM PDT 24 |
| Finished | Jun 23 07:33:51 PM PDT 24 |
| Peak memory | 573340 kb |
| Host | smart-514f15c2-14f8-4f29-8794-8d4da16a613a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=590289782 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.xbar_error_random.590289782 |
| Directory | /workspace/46.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/46.xbar_random.1724001868 |
| Short name | T1424 |
| Test name | |
| Test status | |
| Simulation time | 1175753835 ps |
| CPU time | 43.82 seconds |
| Started | Jun 23 07:32:29 PM PDT 24 |
| Finished | Jun 23 07:33:13 PM PDT 24 |
| Peak memory | 574092 kb |
| Host | smart-9bb8af79-dda3-460a-920f-542c72090a98 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1724001868 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.xbar_random.1724001868 |
| Directory | /workspace/46.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/46.xbar_random_large_delays.1682856538 |
| Short name | T593 |
| Test name | |
| Test status | |
| Simulation time | 41752799199 ps |
| CPU time | 436.31 seconds |
| Started | Jun 23 07:32:27 PM PDT 24 |
| Finished | Jun 23 07:39:44 PM PDT 24 |
| Peak memory | 574128 kb |
| Host | smart-5cc1f45b-7522-4f15-aead-f30869f3d661 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1682856538 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.xbar_random_large_delays.1682856538 |
| Directory | /workspace/46.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/46.xbar_random_slow_rsp.2845164813 |
| Short name | T2031 |
| Test name | |
| Test status | |
| Simulation time | 41052528193 ps |
| CPU time | 699.95 seconds |
| Started | Jun 23 07:32:28 PM PDT 24 |
| Finished | Jun 23 07:44:08 PM PDT 24 |
| Peak memory | 574184 kb |
| Host | smart-5b7b72c3-c3c2-4b0c-81d1-fa016ab3a2d5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2845164813 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.xbar_random_slow_rsp.2845164813 |
| Directory | /workspace/46.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/46.xbar_random_zero_delays.3975963402 |
| Short name | T2772 |
| Test name | |
| Test status | |
| Simulation time | 80099363 ps |
| CPU time | 10.3 seconds |
| Started | Jun 23 07:32:28 PM PDT 24 |
| Finished | Jun 23 07:32:39 PM PDT 24 |
| Peak memory | 573408 kb |
| Host | smart-24d498c2-b2c3-4344-9576-38d313d9b552 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3975963402 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.xbar_random_zero_del ays.3975963402 |
| Directory | /workspace/46.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/46.xbar_same_source.2466157753 |
| Short name | T1495 |
| Test name | |
| Test status | |
| Simulation time | 370787669 ps |
| CPU time | 13.2 seconds |
| Started | Jun 23 07:32:37 PM PDT 24 |
| Finished | Jun 23 07:32:50 PM PDT 24 |
| Peak memory | 573352 kb |
| Host | smart-a3e68b50-4279-4c15-9c94-6b6370053de9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2466157753 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.xbar_same_source.2466157753 |
| Directory | /workspace/46.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/46.xbar_smoke.2723497171 |
| Short name | T1623 |
| Test name | |
| Test status | |
| Simulation time | 45673036 ps |
| CPU time | 6.2 seconds |
| Started | Jun 23 07:32:28 PM PDT 24 |
| Finished | Jun 23 07:32:35 PM PDT 24 |
| Peak memory | 565740 kb |
| Host | smart-f7c8fbb6-1501-46df-a8f0-c5fc4f78515a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2723497171 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.xbar_smoke.2723497171 |
| Directory | /workspace/46.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/46.xbar_smoke_large_delays.1613164505 |
| Short name | T1459 |
| Test name | |
| Test status | |
| Simulation time | 9135142205 ps |
| CPU time | 95.3 seconds |
| Started | Jun 23 07:32:26 PM PDT 24 |
| Finished | Jun 23 07:34:02 PM PDT 24 |
| Peak memory | 565252 kb |
| Host | smart-35c6ca80-3202-45f6-a2a4-1c1d7311536d |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1613164505 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.xbar_smoke_large_delays.1613164505 |
| Directory | /workspace/46.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/46.xbar_smoke_slow_rsp.204921399 |
| Short name | T2552 |
| Test name | |
| Test status | |
| Simulation time | 4999167277 ps |
| CPU time | 79.29 seconds |
| Started | Jun 23 07:32:27 PM PDT 24 |
| Finished | Jun 23 07:33:47 PM PDT 24 |
| Peak memory | 565912 kb |
| Host | smart-52386572-084a-4df9-a546-3e645f938aca |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=204921399 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.xbar_smoke_slow_rsp.204921399 |
| Directory | /workspace/46.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/46.xbar_smoke_zero_delays.700889304 |
| Short name | T1931 |
| Test name | |
| Test status | |
| Simulation time | 42401224 ps |
| CPU time | 6.16 seconds |
| Started | Jun 23 07:32:26 PM PDT 24 |
| Finished | Jun 23 07:32:33 PM PDT 24 |
| Peak memory | 573380 kb |
| Host | smart-140de925-5c7e-4765-b16f-fa74a959e171 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=700889304 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.xbar_smoke_zero_delays .700889304 |
| Directory | /workspace/46.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/46.xbar_stress_all.3278217689 |
| Short name | T2408 |
| Test name | |
| Test status | |
| Simulation time | 1992511580 ps |
| CPU time | 132.28 seconds |
| Started | Jun 23 07:32:39 PM PDT 24 |
| Finished | Jun 23 07:34:51 PM PDT 24 |
| Peak memory | 574272 kb |
| Host | smart-6285de5d-ec18-4d22-838a-3b439b9ab746 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3278217689 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.xbar_stress_all.3278217689 |
| Directory | /workspace/46.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/46.xbar_stress_all_with_error.2310381800 |
| Short name | T2766 |
| Test name | |
| Test status | |
| Simulation time | 2402268386 ps |
| CPU time | 152.89 seconds |
| Started | Jun 23 07:32:38 PM PDT 24 |
| Finished | Jun 23 07:35:12 PM PDT 24 |
| Peak memory | 574312 kb |
| Host | smart-93ec3be4-2cfe-455e-9d06-08b8ab73b243 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2310381800 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.xbar_stress_all_with_error.2310381800 |
| Directory | /workspace/46.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/46.xbar_stress_all_with_rand_reset.1662306357 |
| Short name | T2151 |
| Test name | |
| Test status | |
| Simulation time | 536693277 ps |
| CPU time | 164.79 seconds |
| Started | Jun 23 07:32:40 PM PDT 24 |
| Finished | Jun 23 07:35:25 PM PDT 24 |
| Peak memory | 574216 kb |
| Host | smart-92d2e47a-1034-4cdc-a3fd-29809f2f6be9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1662306357 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.xbar_stress_all _with_rand_reset.1662306357 |
| Directory | /workspace/46.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/46.xbar_stress_all_with_reset_error.3177817876 |
| Short name | T2610 |
| Test name | |
| Test status | |
| Simulation time | 7786955013 ps |
| CPU time | 432.54 seconds |
| Started | Jun 23 07:32:35 PM PDT 24 |
| Finished | Jun 23 07:39:48 PM PDT 24 |
| Peak memory | 576412 kb |
| Host | smart-88ba6b53-8824-4a1e-b149-7532401e083e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3177817876 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.xbar_stress_al l_with_reset_error.3177817876 |
| Directory | /workspace/46.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/46.xbar_unmapped_addr.3791491720 |
| Short name | T1764 |
| Test name | |
| Test status | |
| Simulation time | 205632673 ps |
| CPU time | 11.61 seconds |
| Started | Jun 23 07:32:39 PM PDT 24 |
| Finished | Jun 23 07:32:52 PM PDT 24 |
| Peak memory | 574100 kb |
| Host | smart-599f73ec-08b6-4e53-b858-e244bb12e672 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3791491720 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.xbar_unmapped_addr.3791491720 |
| Directory | /workspace/46.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/47.xbar_access_same_device_slow_rsp.3711260462 |
| Short name | T1864 |
| Test name | |
| Test status | |
| Simulation time | 79017492165 ps |
| CPU time | 1413.34 seconds |
| Started | Jun 23 07:32:35 PM PDT 24 |
| Finished | Jun 23 07:56:09 PM PDT 24 |
| Peak memory | 574232 kb |
| Host | smart-c44e0fe0-2812-420d-b65a-565edae507e0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3711260462 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.xbar_access_same_ device_slow_rsp.3711260462 |
| Directory | /workspace/47.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/47.xbar_error_and_unmapped_addr.2933001367 |
| Short name | T2606 |
| Test name | |
| Test status | |
| Simulation time | 644546251 ps |
| CPU time | 23.73 seconds |
| Started | Jun 23 07:32:38 PM PDT 24 |
| Finished | Jun 23 07:33:02 PM PDT 24 |
| Peak memory | 573672 kb |
| Host | smart-5a2708e4-5390-4067-bce9-15b70c6c504a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2933001367 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.xbar_error_and_unmapped_add r.2933001367 |
| Directory | /workspace/47.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/47.xbar_error_random.3661301238 |
| Short name | T2032 |
| Test name | |
| Test status | |
| Simulation time | 1272762900 ps |
| CPU time | 43.97 seconds |
| Started | Jun 23 07:32:41 PM PDT 24 |
| Finished | Jun 23 07:33:25 PM PDT 24 |
| Peak memory | 573728 kb |
| Host | smart-3f33c394-8b95-46c5-a96c-5b86ed64c1b9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3661301238 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.xbar_error_random.3661301238 |
| Directory | /workspace/47.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/47.xbar_random.4249863397 |
| Short name | T1428 |
| Test name | |
| Test status | |
| Simulation time | 111021466 ps |
| CPU time | 7.19 seconds |
| Started | Jun 23 07:32:37 PM PDT 24 |
| Finished | Jun 23 07:32:44 PM PDT 24 |
| Peak memory | 565844 kb |
| Host | smart-4050c4f0-7b8c-49c2-a4d4-9e4d01c4f1e6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4249863397 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.xbar_random.4249863397 |
| Directory | /workspace/47.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/47.xbar_random_large_delays.3071388234 |
| Short name | T592 |
| Test name | |
| Test status | |
| Simulation time | 57098860571 ps |
| CPU time | 583.28 seconds |
| Started | Jun 23 07:32:42 PM PDT 24 |
| Finished | Jun 23 07:42:26 PM PDT 24 |
| Peak memory | 573528 kb |
| Host | smart-339b6a6b-1199-45d5-94dd-f99e4ca39e4f |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3071388234 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.xbar_random_large_delays.3071388234 |
| Directory | /workspace/47.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/47.xbar_random_slow_rsp.1478686520 |
| Short name | T2228 |
| Test name | |
| Test status | |
| Simulation time | 61312893906 ps |
| CPU time | 1168.86 seconds |
| Started | Jun 23 07:32:34 PM PDT 24 |
| Finished | Jun 23 07:52:04 PM PDT 24 |
| Peak memory | 573432 kb |
| Host | smart-694a056b-676c-4c18-889c-baad69dfa357 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1478686520 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.xbar_random_slow_rsp.1478686520 |
| Directory | /workspace/47.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/47.xbar_random_zero_delays.3141124637 |
| Short name | T2549 |
| Test name | |
| Test status | |
| Simulation time | 66639399 ps |
| CPU time | 8.63 seconds |
| Started | Jun 23 07:32:39 PM PDT 24 |
| Finished | Jun 23 07:32:49 PM PDT 24 |
| Peak memory | 574004 kb |
| Host | smart-86790c5f-6694-4a62-99ed-f51702c2595e |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3141124637 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.xbar_random_zero_del ays.3141124637 |
| Directory | /workspace/47.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/47.xbar_same_source.303281252 |
| Short name | T514 |
| Test name | |
| Test status | |
| Simulation time | 80227538 ps |
| CPU time | 8.45 seconds |
| Started | Jun 23 07:32:35 PM PDT 24 |
| Finished | Jun 23 07:32:43 PM PDT 24 |
| Peak memory | 573944 kb |
| Host | smart-eba38fe2-159d-405b-b721-ea5d286bf6e8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=303281252 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.xbar_same_source.303281252 |
| Directory | /workspace/47.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/47.xbar_smoke.2446917482 |
| Short name | T2499 |
| Test name | |
| Test status | |
| Simulation time | 187066596 ps |
| CPU time | 8.57 seconds |
| Started | Jun 23 07:32:35 PM PDT 24 |
| Finished | Jun 23 07:32:44 PM PDT 24 |
| Peak memory | 573464 kb |
| Host | smart-d32fde32-ad30-4939-ac67-1ff10d45ffa8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2446917482 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.xbar_smoke.2446917482 |
| Directory | /workspace/47.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/47.xbar_smoke_large_delays.144091892 |
| Short name | T560 |
| Test name | |
| Test status | |
| Simulation time | 8447591316 ps |
| CPU time | 85.16 seconds |
| Started | Jun 23 07:32:42 PM PDT 24 |
| Finished | Jun 23 07:34:07 PM PDT 24 |
| Peak memory | 565904 kb |
| Host | smart-51974740-2d5d-454a-9da3-3f9f01113a00 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=144091892 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.xbar_smoke_large_delays.144091892 |
| Directory | /workspace/47.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/47.xbar_smoke_slow_rsp.4226729234 |
| Short name | T1646 |
| Test name | |
| Test status | |
| Simulation time | 6384978432 ps |
| CPU time | 107.85 seconds |
| Started | Jun 23 07:32:39 PM PDT 24 |
| Finished | Jun 23 07:34:28 PM PDT 24 |
| Peak memory | 565520 kb |
| Host | smart-d07565df-aa88-4385-9157-6f704dc6eb22 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4226729234 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.xbar_smoke_slow_rsp.4226729234 |
| Directory | /workspace/47.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/47.xbar_smoke_zero_delays.2566557924 |
| Short name | T1594 |
| Test name | |
| Test status | |
| Simulation time | 53175699 ps |
| CPU time | 7.04 seconds |
| Started | Jun 23 07:32:41 PM PDT 24 |
| Finished | Jun 23 07:32:49 PM PDT 24 |
| Peak memory | 573732 kb |
| Host | smart-97453372-3ce8-45e8-bbb2-7e0b00830127 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2566557924 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.xbar_smoke_zero_delay s.2566557924 |
| Directory | /workspace/47.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/47.xbar_stress_all.1793156408 |
| Short name | T2704 |
| Test name | |
| Test status | |
| Simulation time | 2796141034 ps |
| CPU time | 193.52 seconds |
| Started | Jun 23 07:32:38 PM PDT 24 |
| Finished | Jun 23 07:35:52 PM PDT 24 |
| Peak memory | 574300 kb |
| Host | smart-13a4da4c-1aeb-4657-92d4-7094c3469f43 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1793156408 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.xbar_stress_all.1793156408 |
| Directory | /workspace/47.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/47.xbar_stress_all_with_error.2598470171 |
| Short name | T2387 |
| Test name | |
| Test status | |
| Simulation time | 3357527164 ps |
| CPU time | 262.48 seconds |
| Started | Jun 23 07:32:46 PM PDT 24 |
| Finished | Jun 23 07:37:08 PM PDT 24 |
| Peak memory | 574328 kb |
| Host | smart-b8b26c63-76fc-4327-9485-77c5de76433b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2598470171 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.xbar_stress_all_with_error.2598470171 |
| Directory | /workspace/47.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/47.xbar_stress_all_with_rand_reset.2847292753 |
| Short name | T1485 |
| Test name | |
| Test status | |
| Simulation time | 388815955 ps |
| CPU time | 211.29 seconds |
| Started | Jun 23 07:32:39 PM PDT 24 |
| Finished | Jun 23 07:36:11 PM PDT 24 |
| Peak memory | 576296 kb |
| Host | smart-3c69351b-dbc1-4be6-b80a-1149651e1c13 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2847292753 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.xbar_stress_all _with_rand_reset.2847292753 |
| Directory | /workspace/47.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/47.xbar_stress_all_with_reset_error.4275733659 |
| Short name | T2497 |
| Test name | |
| Test status | |
| Simulation time | 1839396989 ps |
| CPU time | 77.68 seconds |
| Started | Jun 23 07:32:40 PM PDT 24 |
| Finished | Jun 23 07:33:59 PM PDT 24 |
| Peak memory | 576004 kb |
| Host | smart-157653a2-0675-433c-af6f-f19985446086 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4275733659 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.xbar_stress_al l_with_reset_error.4275733659 |
| Directory | /workspace/47.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/47.xbar_unmapped_addr.3414349258 |
| Short name | T70 |
| Test name | |
| Test status | |
| Simulation time | 67598428 ps |
| CPU time | 5.96 seconds |
| Started | Jun 23 07:32:40 PM PDT 24 |
| Finished | Jun 23 07:32:46 PM PDT 24 |
| Peak memory | 565720 kb |
| Host | smart-1837c82c-48ed-47a1-9939-fd5be82ced6e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3414349258 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.xbar_unmapped_addr.3414349258 |
| Directory | /workspace/47.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/48.xbar_access_same_device.2060832556 |
| Short name | T885 |
| Test name | |
| Test status | |
| Simulation time | 209670576 ps |
| CPU time | 20.13 seconds |
| Started | Jun 23 07:32:43 PM PDT 24 |
| Finished | Jun 23 07:33:03 PM PDT 24 |
| Peak memory | 574088 kb |
| Host | smart-84e7a9c7-6a8c-4016-9d86-1cabfeb6d377 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2060832556 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.xbar_access_same_device .2060832556 |
| Directory | /workspace/48.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/48.xbar_access_same_device_slow_rsp.161645171 |
| Short name | T1683 |
| Test name | |
| Test status | |
| Simulation time | 93607888359 ps |
| CPU time | 1549.33 seconds |
| Started | Jun 23 07:32:39 PM PDT 24 |
| Finished | Jun 23 07:58:30 PM PDT 24 |
| Peak memory | 574260 kb |
| Host | smart-eeea0d4b-63f0-4a23-9653-b603fabbe605 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=161645171 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.xbar_access_same_d evice_slow_rsp.161645171 |
| Directory | /workspace/48.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/48.xbar_error_and_unmapped_addr.3775772788 |
| Short name | T2272 |
| Test name | |
| Test status | |
| Simulation time | 51902929 ps |
| CPU time | 8.54 seconds |
| Started | Jun 23 07:32:34 PM PDT 24 |
| Finished | Jun 23 07:32:43 PM PDT 24 |
| Peak memory | 573392 kb |
| Host | smart-7efa447c-df3c-43aa-b251-c75616a56ede |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3775772788 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.xbar_error_and_unmapped_add r.3775772788 |
| Directory | /workspace/48.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/48.xbar_error_random.3111376842 |
| Short name | T2112 |
| Test name | |
| Test status | |
| Simulation time | 1891535571 ps |
| CPU time | 65.87 seconds |
| Started | Jun 23 07:32:35 PM PDT 24 |
| Finished | Jun 23 07:33:41 PM PDT 24 |
| Peak memory | 573372 kb |
| Host | smart-85cf7c9c-cbd0-4c18-b17e-45b8b1c3d930 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3111376842 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.xbar_error_random.3111376842 |
| Directory | /workspace/48.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/48.xbar_random.1576903646 |
| Short name | T1554 |
| Test name | |
| Test status | |
| Simulation time | 1038950968 ps |
| CPU time | 37.09 seconds |
| Started | Jun 23 07:32:35 PM PDT 24 |
| Finished | Jun 23 07:33:13 PM PDT 24 |
| Peak memory | 573424 kb |
| Host | smart-66265ee4-5532-48e2-9864-f6bb95b0d6f3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1576903646 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.xbar_random.1576903646 |
| Directory | /workspace/48.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/48.xbar_random_large_delays.1752745921 |
| Short name | T2246 |
| Test name | |
| Test status | |
| Simulation time | 15864312009 ps |
| CPU time | 154.78 seconds |
| Started | Jun 23 07:32:37 PM PDT 24 |
| Finished | Jun 23 07:35:12 PM PDT 24 |
| Peak memory | 573428 kb |
| Host | smart-e176b42c-7422-42a0-958f-9b64871c1244 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1752745921 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.xbar_random_large_delays.1752745921 |
| Directory | /workspace/48.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/48.xbar_random_slow_rsp.2874948836 |
| Short name | T1591 |
| Test name | |
| Test status | |
| Simulation time | 3827170543 ps |
| CPU time | 63.37 seconds |
| Started | Jun 23 07:32:39 PM PDT 24 |
| Finished | Jun 23 07:33:43 PM PDT 24 |
| Peak memory | 565260 kb |
| Host | smart-02490942-8337-42e0-b202-584548846a5f |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2874948836 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.xbar_random_slow_rsp.2874948836 |
| Directory | /workspace/48.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/48.xbar_random_zero_delays.3192444365 |
| Short name | T1538 |
| Test name | |
| Test status | |
| Simulation time | 337267596 ps |
| CPU time | 30.08 seconds |
| Started | Jun 23 07:32:35 PM PDT 24 |
| Finished | Jun 23 07:33:06 PM PDT 24 |
| Peak memory | 573392 kb |
| Host | smart-85aaa2dd-9563-41ee-8c7c-7ebc44ca232d |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3192444365 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.xbar_random_zero_del ays.3192444365 |
| Directory | /workspace/48.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/48.xbar_same_source.2749788321 |
| Short name | T1982 |
| Test name | |
| Test status | |
| Simulation time | 2592165429 ps |
| CPU time | 73.27 seconds |
| Started | Jun 23 07:32:42 PM PDT 24 |
| Finished | Jun 23 07:33:55 PM PDT 24 |
| Peak memory | 573724 kb |
| Host | smart-58e44ac7-a1bf-45ce-88f7-e9b99aaab427 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2749788321 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.xbar_same_source.2749788321 |
| Directory | /workspace/48.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/48.xbar_smoke.1439973635 |
| Short name | T2285 |
| Test name | |
| Test status | |
| Simulation time | 178202286 ps |
| CPU time | 8.42 seconds |
| Started | Jun 23 07:32:42 PM PDT 24 |
| Finished | Jun 23 07:32:51 PM PDT 24 |
| Peak memory | 565720 kb |
| Host | smart-6e90f270-6714-48ab-83c9-a176a992f064 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1439973635 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.xbar_smoke.1439973635 |
| Directory | /workspace/48.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/48.xbar_smoke_large_delays.1984680759 |
| Short name | T2749 |
| Test name | |
| Test status | |
| Simulation time | 10060015889 ps |
| CPU time | 106.12 seconds |
| Started | Jun 23 07:32:35 PM PDT 24 |
| Finished | Jun 23 07:34:21 PM PDT 24 |
| Peak memory | 565944 kb |
| Host | smart-2c38c25c-cfd1-4139-af71-a3efb6cf89db |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1984680759 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.xbar_smoke_large_delays.1984680759 |
| Directory | /workspace/48.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/48.xbar_smoke_slow_rsp.3963419655 |
| Short name | T1952 |
| Test name | |
| Test status | |
| Simulation time | 4542913826 ps |
| CPU time | 76.97 seconds |
| Started | Jun 23 07:32:39 PM PDT 24 |
| Finished | Jun 23 07:33:56 PM PDT 24 |
| Peak memory | 565916 kb |
| Host | smart-3fb0d537-4999-4552-9771-894b0c1fca51 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3963419655 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.xbar_smoke_slow_rsp.3963419655 |
| Directory | /workspace/48.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/48.xbar_smoke_zero_delays.4019114866 |
| Short name | T2781 |
| Test name | |
| Test status | |
| Simulation time | 49734580 ps |
| CPU time | 6.47 seconds |
| Started | Jun 23 07:32:39 PM PDT 24 |
| Finished | Jun 23 07:32:46 PM PDT 24 |
| Peak memory | 565548 kb |
| Host | smart-62889713-c5dd-421c-ae62-62eff89742c2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4019114866 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.xbar_smoke_zero_delay s.4019114866 |
| Directory | /workspace/48.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/48.xbar_stress_all.2677373649 |
| Short name | T2020 |
| Test name | |
| Test status | |
| Simulation time | 9993091430 ps |
| CPU time | 370.58 seconds |
| Started | Jun 23 07:32:40 PM PDT 24 |
| Finished | Jun 23 07:38:51 PM PDT 24 |
| Peak memory | 574288 kb |
| Host | smart-ad97e27d-73ba-4a12-869d-1e4eaeede96a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2677373649 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.xbar_stress_all.2677373649 |
| Directory | /workspace/48.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/48.xbar_stress_all_with_error.3547358121 |
| Short name | T2089 |
| Test name | |
| Test status | |
| Simulation time | 987691067 ps |
| CPU time | 90.39 seconds |
| Started | Jun 23 07:32:39 PM PDT 24 |
| Finished | Jun 23 07:34:10 PM PDT 24 |
| Peak memory | 574224 kb |
| Host | smart-8d335dc1-bdd8-4bb5-9fc8-c6abb350de3d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3547358121 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.xbar_stress_all_with_error.3547358121 |
| Directory | /workspace/48.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/48.xbar_stress_all_with_rand_reset.3745899961 |
| Short name | T2468 |
| Test name | |
| Test status | |
| Simulation time | 351386407 ps |
| CPU time | 105.13 seconds |
| Started | Jun 23 07:32:39 PM PDT 24 |
| Finished | Jun 23 07:34:25 PM PDT 24 |
| Peak memory | 577284 kb |
| Host | smart-21127b16-11a0-4813-8f6d-1ade2ac4b321 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3745899961 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.xbar_stress_all _with_rand_reset.3745899961 |
| Directory | /workspace/48.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/48.xbar_stress_all_with_reset_error.1421375404 |
| Short name | T2131 |
| Test name | |
| Test status | |
| Simulation time | 21105214 ps |
| CPU time | 22.31 seconds |
| Started | Jun 23 07:32:40 PM PDT 24 |
| Finished | Jun 23 07:33:03 PM PDT 24 |
| Peak memory | 574552 kb |
| Host | smart-c65f40a0-d085-4256-94b9-f120dae3285c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1421375404 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.xbar_stress_al l_with_reset_error.1421375404 |
| Directory | /workspace/48.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/48.xbar_unmapped_addr.3959338894 |
| Short name | T2087 |
| Test name | |
| Test status | |
| Simulation time | 1040911849 ps |
| CPU time | 41.56 seconds |
| Started | Jun 23 07:32:40 PM PDT 24 |
| Finished | Jun 23 07:33:23 PM PDT 24 |
| Peak memory | 574160 kb |
| Host | smart-0e1d4777-349b-4e93-a51c-917e1f9bd70d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3959338894 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.xbar_unmapped_addr.3959338894 |
| Directory | /workspace/48.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/49.xbar_access_same_device.3968048851 |
| Short name | T1633 |
| Test name | |
| Test status | |
| Simulation time | 2581561094 ps |
| CPU time | 105.54 seconds |
| Started | Jun 23 07:32:47 PM PDT 24 |
| Finished | Jun 23 07:34:33 PM PDT 24 |
| Peak memory | 573464 kb |
| Host | smart-d1fab8df-32e4-40ef-8ba7-2bf8d24f1b04 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3968048851 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.xbar_access_same_device .3968048851 |
| Directory | /workspace/49.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/49.xbar_access_same_device_slow_rsp.2272041216 |
| Short name | T871 |
| Test name | |
| Test status | |
| Simulation time | 84246142401 ps |
| CPU time | 1545.15 seconds |
| Started | Jun 23 07:32:41 PM PDT 24 |
| Finished | Jun 23 07:58:27 PM PDT 24 |
| Peak memory | 574220 kb |
| Host | smart-643635f3-1f69-4820-a4ac-fb3b273296f7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2272041216 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.xbar_access_same_ device_slow_rsp.2272041216 |
| Directory | /workspace/49.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/49.xbar_error_and_unmapped_addr.2834882996 |
| Short name | T1484 |
| Test name | |
| Test status | |
| Simulation time | 361845155 ps |
| CPU time | 14.98 seconds |
| Started | Jun 23 07:32:36 PM PDT 24 |
| Finished | Jun 23 07:32:51 PM PDT 24 |
| Peak memory | 573664 kb |
| Host | smart-5b8336fa-1e7d-4c5f-9623-d0f943d4b385 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2834882996 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.xbar_error_and_unmapped_add r.2834882996 |
| Directory | /workspace/49.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/49.xbar_error_random.813601442 |
| Short name | T2580 |
| Test name | |
| Test status | |
| Simulation time | 258754544 ps |
| CPU time | 18.92 seconds |
| Started | Jun 23 07:32:40 PM PDT 24 |
| Finished | Jun 23 07:33:00 PM PDT 24 |
| Peak memory | 573364 kb |
| Host | smart-c2d3126a-a50b-432d-ab06-0a9ac51fa98b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=813601442 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.xbar_error_random.813601442 |
| Directory | /workspace/49.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/49.xbar_random.615292830 |
| Short name | T2767 |
| Test name | |
| Test status | |
| Simulation time | 560221631 ps |
| CPU time | 52.81 seconds |
| Started | Jun 23 07:32:34 PM PDT 24 |
| Finished | Jun 23 07:33:28 PM PDT 24 |
| Peak memory | 574256 kb |
| Host | smart-59cc6a90-00a0-407b-935f-552f4a61d773 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=615292830 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.xbar_random.615292830 |
| Directory | /workspace/49.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/49.xbar_random_large_delays.1669093906 |
| Short name | T1466 |
| Test name | |
| Test status | |
| Simulation time | 97351692646 ps |
| CPU time | 1036.16 seconds |
| Started | Jun 23 07:32:42 PM PDT 24 |
| Finished | Jun 23 07:49:58 PM PDT 24 |
| Peak memory | 574200 kb |
| Host | smart-c4662fa0-67a9-4414-a1a0-6f316160ed8e |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1669093906 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.xbar_random_large_delays.1669093906 |
| Directory | /workspace/49.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/49.xbar_random_slow_rsp.2554192148 |
| Short name | T615 |
| Test name | |
| Test status | |
| Simulation time | 26061694847 ps |
| CPU time | 457.12 seconds |
| Started | Jun 23 07:32:40 PM PDT 24 |
| Finished | Jun 23 07:40:18 PM PDT 24 |
| Peak memory | 574156 kb |
| Host | smart-95b0439c-7c85-49fa-a056-400370de3913 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2554192148 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.xbar_random_slow_rsp.2554192148 |
| Directory | /workspace/49.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/49.xbar_random_zero_delays.2036965678 |
| Short name | T2811 |
| Test name | |
| Test status | |
| Simulation time | 257927338 ps |
| CPU time | 21.93 seconds |
| Started | Jun 23 07:32:39 PM PDT 24 |
| Finished | Jun 23 07:33:02 PM PDT 24 |
| Peak memory | 574084 kb |
| Host | smart-efe507e1-580a-4b70-88e2-96c8238a8747 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2036965678 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.xbar_random_zero_del ays.2036965678 |
| Directory | /workspace/49.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/49.xbar_same_source.3850037200 |
| Short name | T626 |
| Test name | |
| Test status | |
| Simulation time | 2638523916 ps |
| CPU time | 80.81 seconds |
| Started | Jun 23 07:32:46 PM PDT 24 |
| Finished | Jun 23 07:34:07 PM PDT 24 |
| Peak memory | 574148 kb |
| Host | smart-2bc9b5b5-8dd2-4049-bb6d-57c116752e8b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3850037200 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.xbar_same_source.3850037200 |
| Directory | /workspace/49.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/49.xbar_smoke.1490768741 |
| Short name | T2376 |
| Test name | |
| Test status | |
| Simulation time | 45765557 ps |
| CPU time | 6.21 seconds |
| Started | Jun 23 07:32:45 PM PDT 24 |
| Finished | Jun 23 07:32:51 PM PDT 24 |
| Peak memory | 565848 kb |
| Host | smart-b6651623-560c-48a8-91e9-4f45f3d1880c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1490768741 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.xbar_smoke.1490768741 |
| Directory | /workspace/49.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/49.xbar_smoke_large_delays.933017246 |
| Short name | T1695 |
| Test name | |
| Test status | |
| Simulation time | 9068989962 ps |
| CPU time | 98.51 seconds |
| Started | Jun 23 07:32:37 PM PDT 24 |
| Finished | Jun 23 07:34:16 PM PDT 24 |
| Peak memory | 565248 kb |
| Host | smart-115f604a-225f-4ec5-afd1-e91ed07bea47 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=933017246 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.xbar_smoke_large_delays.933017246 |
| Directory | /workspace/49.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/49.xbar_smoke_slow_rsp.730010876 |
| Short name | T595 |
| Test name | |
| Test status | |
| Simulation time | 4491458405 ps |
| CPU time | 75.97 seconds |
| Started | Jun 23 07:32:38 PM PDT 24 |
| Finished | Jun 23 07:33:54 PM PDT 24 |
| Peak memory | 565276 kb |
| Host | smart-cccbac5b-e95c-4875-b5be-3ac7f54f0309 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=730010876 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.xbar_smoke_slow_rsp.730010876 |
| Directory | /workspace/49.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/49.xbar_smoke_zero_delays.756558188 |
| Short name | T1786 |
| Test name | |
| Test status | |
| Simulation time | 50006524 ps |
| CPU time | 6.5 seconds |
| Started | Jun 23 07:32:45 PM PDT 24 |
| Finished | Jun 23 07:32:52 PM PDT 24 |
| Peak memory | 565520 kb |
| Host | smart-d5ec9b10-c3f2-4fad-a78a-caabc59faeec |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=756558188 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.xbar_smoke_zero_delays .756558188 |
| Directory | /workspace/49.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/49.xbar_stress_all.548007290 |
| Short name | T2145 |
| Test name | |
| Test status | |
| Simulation time | 12582649751 ps |
| CPU time | 467.81 seconds |
| Started | Jun 23 07:32:40 PM PDT 24 |
| Finished | Jun 23 07:40:29 PM PDT 24 |
| Peak memory | 574284 kb |
| Host | smart-d95ea76a-bb3c-4738-96dd-86e6176195aa |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=548007290 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.xbar_stress_all.548007290 |
| Directory | /workspace/49.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/49.xbar_stress_all_with_error.1862902495 |
| Short name | T1902 |
| Test name | |
| Test status | |
| Simulation time | 9635463917 ps |
| CPU time | 314.9 seconds |
| Started | Jun 23 07:32:51 PM PDT 24 |
| Finished | Jun 23 07:38:06 PM PDT 24 |
| Peak memory | 574316 kb |
| Host | smart-b50a3fe0-2ac0-434e-97cc-758ef13d3ef1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1862902495 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.xbar_stress_all_with_error.1862902495 |
| Directory | /workspace/49.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/49.xbar_stress_all_with_rand_reset.2676257852 |
| Short name | T2048 |
| Test name | |
| Test status | |
| Simulation time | 523703602 ps |
| CPU time | 253.05 seconds |
| Started | Jun 23 07:32:41 PM PDT 24 |
| Finished | Jun 23 07:36:55 PM PDT 24 |
| Peak memory | 574252 kb |
| Host | smart-55d57af1-5339-4bcd-a2d0-1386f2feee6a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2676257852 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.xbar_stress_all _with_rand_reset.2676257852 |
| Directory | /workspace/49.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/49.xbar_stress_all_with_reset_error.966663249 |
| Short name | T894 |
| Test name | |
| Test status | |
| Simulation time | 300764664 ps |
| CPU time | 95.63 seconds |
| Started | Jun 23 07:32:48 PM PDT 24 |
| Finished | Jun 23 07:34:24 PM PDT 24 |
| Peak memory | 576360 kb |
| Host | smart-86c1e843-cdc7-4284-a7b1-029d92b6854b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=966663249 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.xbar_stress_all _with_reset_error.966663249 |
| Directory | /workspace/49.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/49.xbar_unmapped_addr.3243249885 |
| Short name | T2533 |
| Test name | |
| Test status | |
| Simulation time | 218635801 ps |
| CPU time | 26.71 seconds |
| Started | Jun 23 07:32:46 PM PDT 24 |
| Finished | Jun 23 07:33:13 PM PDT 24 |
| Peak memory | 574128 kb |
| Host | smart-54876b4c-105c-4289-82ad-a77d508c8b7f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3243249885 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.xbar_unmapped_addr.3243249885 |
| Directory | /workspace/49.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/5.chip_csr_rw.2668776655 |
| Short name | T1886 |
| Test name | |
| Test status | |
| Simulation time | 5829469200 ps |
| CPU time | 578.46 seconds |
| Started | Jun 23 07:21:33 PM PDT 24 |
| Finished | Jun 23 07:31:12 PM PDT 24 |
| Peak memory | 596808 kb |
| Host | smart-19490e3a-5383-49fb-af94-9a0850b3d1a2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2668776655 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.chip_csr_rw.2668776655 |
| Directory | /workspace/5.chip_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/5.chip_same_csr_outstanding.2098799153 |
| Short name | T2513 |
| Test name | |
| Test status | |
| Simulation time | 29581772567 ps |
| CPU time | 4043.89 seconds |
| Started | Jun 23 07:21:31 PM PDT 24 |
| Finished | Jun 23 08:28:56 PM PDT 24 |
| Peak memory | 591204 kb |
| Host | smart-683e293e-288e-48c0-9fbc-f1533c31061b |
| User | root |
| Command | /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +run_same_csr_outstanding +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2098799153 -assert nopostproc +UVM_TE STNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb - cm_log /dev/null -cm_name 5.chip_same_csr_outstanding.2098799153 |
| Directory | /workspace/5.chip_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/5.chip_tl_errors.1076557038 |
| Short name | T511 |
| Test name | |
| Test status | |
| Simulation time | 3987513992 ps |
| CPU time | 251.79 seconds |
| Started | Jun 23 07:21:28 PM PDT 24 |
| Finished | Jun 23 07:25:41 PM PDT 24 |
| Peak memory | 596392 kb |
| Host | smart-646a0ddb-f504-4d61-a204-b65d27407e36 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1076557038 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.chip_tl_errors.1076557038 |
| Directory | /workspace/5.chip_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/5.xbar_access_same_device.1897750668 |
| Short name | T1522 |
| Test name | |
| Test status | |
| Simulation time | 440317520 ps |
| CPU time | 38.31 seconds |
| Started | Jun 23 07:21:28 PM PDT 24 |
| Finished | Jun 23 07:22:07 PM PDT 24 |
| Peak memory | 574152 kb |
| Host | smart-657ff483-2cf4-467c-b597-6c1e07755173 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1897750668 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.xbar_access_same_device. 1897750668 |
| Directory | /workspace/5.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/5.xbar_access_same_device_slow_rsp.3003837343 |
| Short name | T1772 |
| Test name | |
| Test status | |
| Simulation time | 135121976166 ps |
| CPU time | 2395.03 seconds |
| Started | Jun 23 07:21:28 PM PDT 24 |
| Finished | Jun 23 08:01:24 PM PDT 24 |
| Peak memory | 574296 kb |
| Host | smart-246abc0d-fa8c-4bcc-a656-356b05986719 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3003837343 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.xbar_access_same_d evice_slow_rsp.3003837343 |
| Directory | /workspace/5.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/5.xbar_error_and_unmapped_addr.1299131228 |
| Short name | T1841 |
| Test name | |
| Test status | |
| Simulation time | 1337651520 ps |
| CPU time | 53.43 seconds |
| Started | Jun 23 07:21:35 PM PDT 24 |
| Finished | Jun 23 07:22:28 PM PDT 24 |
| Peak memory | 574184 kb |
| Host | smart-97ea6ca8-2152-42be-8bf6-ccb1a6477750 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1299131228 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.xbar_error_and_unmapped_addr .1299131228 |
| Directory | /workspace/5.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/5.xbar_error_random.1160530570 |
| Short name | T2086 |
| Test name | |
| Test status | |
| Simulation time | 34768974 ps |
| CPU time | 5.7 seconds |
| Started | Jun 23 07:21:36 PM PDT 24 |
| Finished | Jun 23 07:21:42 PM PDT 24 |
| Peak memory | 565348 kb |
| Host | smart-9341cac5-9e37-46b9-b922-63af4b2b4be2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1160530570 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.xbar_error_random.1160530570 |
| Directory | /workspace/5.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/5.xbar_random.2082675405 |
| Short name | T1672 |
| Test name | |
| Test status | |
| Simulation time | 292310992 ps |
| CPU time | 12.86 seconds |
| Started | Jun 23 07:21:31 PM PDT 24 |
| Finished | Jun 23 07:21:44 PM PDT 24 |
| Peak memory | 574080 kb |
| Host | smart-4fdd8d54-5fd4-4885-ae97-52a44890375a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2082675405 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.xbar_random.2082675405 |
| Directory | /workspace/5.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/5.xbar_random_large_delays.1842816810 |
| Short name | T1690 |
| Test name | |
| Test status | |
| Simulation time | 37907775067 ps |
| CPU time | 395.99 seconds |
| Started | Jun 23 07:21:31 PM PDT 24 |
| Finished | Jun 23 07:28:07 PM PDT 24 |
| Peak memory | 574216 kb |
| Host | smart-49e28cf7-4743-458e-aaf4-37c6ad118843 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1842816810 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.xbar_random_large_delays.1842816810 |
| Directory | /workspace/5.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/5.xbar_random_slow_rsp.3543618691 |
| Short name | T561 |
| Test name | |
| Test status | |
| Simulation time | 54569977065 ps |
| CPU time | 915.49 seconds |
| Started | Jun 23 07:21:31 PM PDT 24 |
| Finished | Jun 23 07:36:47 PM PDT 24 |
| Peak memory | 574180 kb |
| Host | smart-13a32fcc-b386-4a9e-9704-1dad839f4bea |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3543618691 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.xbar_random_slow_rsp.3543618691 |
| Directory | /workspace/5.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/5.xbar_random_zero_delays.3793577733 |
| Short name | T620 |
| Test name | |
| Test status | |
| Simulation time | 142870935 ps |
| CPU time | 15.81 seconds |
| Started | Jun 23 07:21:36 PM PDT 24 |
| Finished | Jun 23 07:21:53 PM PDT 24 |
| Peak memory | 574096 kb |
| Host | smart-4a3ca82a-983a-45fa-9ee5-4d58860ebe15 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3793577733 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.xbar_random_zero_dela ys.3793577733 |
| Directory | /workspace/5.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/5.xbar_same_source.2578961992 |
| Short name | T2534 |
| Test name | |
| Test status | |
| Simulation time | 1306401386 ps |
| CPU time | 36.54 seconds |
| Started | Jun 23 07:21:36 PM PDT 24 |
| Finished | Jun 23 07:22:13 PM PDT 24 |
| Peak memory | 573304 kb |
| Host | smart-e52044f3-37e6-442c-b76d-2db95b15c187 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2578961992 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.xbar_same_source.2578961992 |
| Directory | /workspace/5.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/5.xbar_smoke.3519976556 |
| Short name | T1496 |
| Test name | |
| Test status | |
| Simulation time | 56094595 ps |
| CPU time | 6.73 seconds |
| Started | Jun 23 07:21:26 PM PDT 24 |
| Finished | Jun 23 07:21:33 PM PDT 24 |
| Peak memory | 565180 kb |
| Host | smart-5492432e-00fb-4c52-85bb-7e5d5d740fd0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3519976556 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.xbar_smoke.3519976556 |
| Directory | /workspace/5.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/5.xbar_smoke_large_delays.2801873604 |
| Short name | T1616 |
| Test name | |
| Test status | |
| Simulation time | 10472006875 ps |
| CPU time | 107.51 seconds |
| Started | Jun 23 07:21:35 PM PDT 24 |
| Finished | Jun 23 07:23:22 PM PDT 24 |
| Peak memory | 565352 kb |
| Host | smart-b8145b2b-2509-4383-a9e2-a6ec24a7147a |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2801873604 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.xbar_smoke_large_delays.2801873604 |
| Directory | /workspace/5.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/5.xbar_smoke_slow_rsp.2718767928 |
| Short name | T1486 |
| Test name | |
| Test status | |
| Simulation time | 3626976280 ps |
| CPU time | 61.64 seconds |
| Started | Jun 23 07:21:30 PM PDT 24 |
| Finished | Jun 23 07:22:32 PM PDT 24 |
| Peak memory | 565236 kb |
| Host | smart-c298e4bc-087e-45d1-b95d-647a92a21dad |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2718767928 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.xbar_smoke_slow_rsp.2718767928 |
| Directory | /workspace/5.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/5.xbar_smoke_zero_delays.42795024 |
| Short name | T1972 |
| Test name | |
| Test status | |
| Simulation time | 55414675 ps |
| CPU time | 7.16 seconds |
| Started | Jun 23 07:21:29 PM PDT 24 |
| Finished | Jun 23 07:21:36 PM PDT 24 |
| Peak memory | 565484 kb |
| Host | smart-4d66dad6-a254-457e-a78b-619e99239b84 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42795024 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.xbar_smoke_zero_delays.42795024 |
| Directory | /workspace/5.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/5.xbar_stress_all.1702478159 |
| Short name | T2235 |
| Test name | |
| Test status | |
| Simulation time | 6439224367 ps |
| CPU time | 240.81 seconds |
| Started | Jun 23 07:21:30 PM PDT 24 |
| Finished | Jun 23 07:25:31 PM PDT 24 |
| Peak memory | 574300 kb |
| Host | smart-cca0c0c8-32d2-4429-a2ab-a69769c507fa |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1702478159 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.xbar_stress_all.1702478159 |
| Directory | /workspace/5.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/5.xbar_stress_all_with_error.1970556643 |
| Short name | T2128 |
| Test name | |
| Test status | |
| Simulation time | 1895408138 ps |
| CPU time | 170.47 seconds |
| Started | Jun 23 07:21:33 PM PDT 24 |
| Finished | Jun 23 07:24:24 PM PDT 24 |
| Peak memory | 574284 kb |
| Host | smart-d9fd4ce3-f937-4c3d-925a-2cf9c3b1cdef |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1970556643 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.xbar_stress_all_with_error.1970556643 |
| Directory | /workspace/5.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/5.xbar_stress_all_with_rand_reset.3414293734 |
| Short name | T672 |
| Test name | |
| Test status | |
| Simulation time | 97401281 ps |
| CPU time | 27.59 seconds |
| Started | Jun 23 07:21:28 PM PDT 24 |
| Finished | Jun 23 07:21:55 PM PDT 24 |
| Peak memory | 574248 kb |
| Host | smart-de266c35-710a-4dcb-89e8-7ba5b49d7a15 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3414293734 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.xbar_stress_all_ with_rand_reset.3414293734 |
| Directory | /workspace/5.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/5.xbar_stress_all_with_reset_error.2566331760 |
| Short name | T896 |
| Test name | |
| Test status | |
| Simulation time | 582534514 ps |
| CPU time | 258.16 seconds |
| Started | Jun 23 07:21:35 PM PDT 24 |
| Finished | Jun 23 07:25:54 PM PDT 24 |
| Peak memory | 574308 kb |
| Host | smart-f33294d4-23ac-4ce6-9915-fb4922f50df1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2566331760 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.xbar_stress_all _with_reset_error.2566331760 |
| Directory | /workspace/5.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/5.xbar_unmapped_addr.870700040 |
| Short name | T462 |
| Test name | |
| Test status | |
| Simulation time | 214567117 ps |
| CPU time | 28.03 seconds |
| Started | Jun 23 07:21:28 PM PDT 24 |
| Finished | Jun 23 07:21:56 PM PDT 24 |
| Peak memory | 574144 kb |
| Host | smart-2e3b1d9f-eb62-40ba-977b-249fad5763ce |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=870700040 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.xbar_unmapped_addr.870700040 |
| Directory | /workspace/5.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/50.xbar_access_same_device.3817696321 |
| Short name | T1481 |
| Test name | |
| Test status | |
| Simulation time | 1993505866 ps |
| CPU time | 73.19 seconds |
| Started | Jun 23 07:32:55 PM PDT 24 |
| Finished | Jun 23 07:34:08 PM PDT 24 |
| Peak memory | 574088 kb |
| Host | smart-107d30fb-844d-4b2c-a8ac-811068f01a8a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3817696321 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 50.xbar_access_same_device .3817696321 |
| Directory | /workspace/50.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/50.xbar_access_same_device_slow_rsp.2012085465 |
| Short name | T1800 |
| Test name | |
| Test status | |
| Simulation time | 96611950599 ps |
| CPU time | 1768.77 seconds |
| Started | Jun 23 07:32:57 PM PDT 24 |
| Finished | Jun 23 08:02:26 PM PDT 24 |
| Peak memory | 573960 kb |
| Host | smart-cf60eb80-e083-49ea-be3a-473152770301 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2012085465 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 50.xbar_access_same_ device_slow_rsp.2012085465 |
| Directory | /workspace/50.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/50.xbar_error_and_unmapped_addr.4240276838 |
| Short name | T2605 |
| Test name | |
| Test status | |
| Simulation time | 1230221369 ps |
| CPU time | 51.82 seconds |
| Started | Jun 23 07:33:01 PM PDT 24 |
| Finished | Jun 23 07:33:53 PM PDT 24 |
| Peak memory | 573676 kb |
| Host | smart-8a5de807-a93c-4d1b-ad7b-413da488e0b4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4240276838 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 50.xbar_error_and_unmapped_add r.4240276838 |
| Directory | /workspace/50.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/50.xbar_error_random.3615204317 |
| Short name | T1440 |
| Test name | |
| Test status | |
| Simulation time | 615061094 ps |
| CPU time | 49.59 seconds |
| Started | Jun 23 07:32:55 PM PDT 24 |
| Finished | Jun 23 07:33:45 PM PDT 24 |
| Peak memory | 573756 kb |
| Host | smart-f451baf4-f23a-494e-a193-56fce3cd65d1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3615204317 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 50.xbar_error_random.3615204317 |
| Directory | /workspace/50.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/50.xbar_random.3386576762 |
| Short name | T2299 |
| Test name | |
| Test status | |
| Simulation time | 646424977 ps |
| CPU time | 58.8 seconds |
| Started | Jun 23 07:32:54 PM PDT 24 |
| Finished | Jun 23 07:33:53 PM PDT 24 |
| Peak memory | 574132 kb |
| Host | smart-98c1d1b0-6fd9-4e64-a351-b91631bda5cb |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3386576762 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 50.xbar_random.3386576762 |
| Directory | /workspace/50.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/50.xbar_random_large_delays.1152552302 |
| Short name | T1605 |
| Test name | |
| Test status | |
| Simulation time | 40642808724 ps |
| CPU time | 424.84 seconds |
| Started | Jun 23 07:32:55 PM PDT 24 |
| Finished | Jun 23 07:40:00 PM PDT 24 |
| Peak memory | 573520 kb |
| Host | smart-7040d879-4c47-4271-b01c-027a0d5ff0a6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1152552302 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 50.xbar_random_large_delays.1152552302 |
| Directory | /workspace/50.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/50.xbar_random_slow_rsp.303305986 |
| Short name | T2378 |
| Test name | |
| Test status | |
| Simulation time | 10795422563 ps |
| CPU time | 181 seconds |
| Started | Jun 23 07:32:53 PM PDT 24 |
| Finished | Jun 23 07:35:54 PM PDT 24 |
| Peak memory | 574140 kb |
| Host | smart-1ce48881-425b-449b-8ac6-147683eeba27 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=303305986 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 50.xbar_random_slow_rsp.303305986 |
| Directory | /workspace/50.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/50.xbar_random_zero_delays.843540131 |
| Short name | T2116 |
| Test name | |
| Test status | |
| Simulation time | 430067074 ps |
| CPU time | 35.52 seconds |
| Started | Jun 23 07:33:02 PM PDT 24 |
| Finished | Jun 23 07:33:37 PM PDT 24 |
| Peak memory | 574088 kb |
| Host | smart-65574a5a-a464-4d66-a879-ce2d5f4f1887 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=843540131 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 50.xbar_random_zero_dela ys.843540131 |
| Directory | /workspace/50.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/50.xbar_same_source.1138572757 |
| Short name | T525 |
| Test name | |
| Test status | |
| Simulation time | 1238127418 ps |
| CPU time | 37.52 seconds |
| Started | Jun 23 07:32:56 PM PDT 24 |
| Finished | Jun 23 07:33:34 PM PDT 24 |
| Peak memory | 573384 kb |
| Host | smart-7d6d6979-be61-44e2-871f-ad0eb7a3c803 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1138572757 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 50.xbar_same_source.1138572757 |
| Directory | /workspace/50.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/50.xbar_smoke.448242006 |
| Short name | T1962 |
| Test name | |
| Test status | |
| Simulation time | 204567666 ps |
| CPU time | 8.07 seconds |
| Started | Jun 23 07:32:48 PM PDT 24 |
| Finished | Jun 23 07:32:56 PM PDT 24 |
| Peak memory | 565480 kb |
| Host | smart-76bd4f0f-49fb-4551-a1a7-cb63e3157193 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=448242006 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 50.xbar_smoke.448242006 |
| Directory | /workspace/50.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/50.xbar_smoke_large_delays.782736854 |
| Short name | T2737 |
| Test name | |
| Test status | |
| Simulation time | 8205892158 ps |
| CPU time | 85.53 seconds |
| Started | Jun 23 07:32:51 PM PDT 24 |
| Finished | Jun 23 07:34:17 PM PDT 24 |
| Peak memory | 565892 kb |
| Host | smart-82e7f595-3932-4448-b283-c70dace5b173 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=782736854 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 50.xbar_smoke_large_delays.782736854 |
| Directory | /workspace/50.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/50.xbar_smoke_slow_rsp.3601309029 |
| Short name | T1715 |
| Test name | |
| Test status | |
| Simulation time | 4318644375 ps |
| CPU time | 70.19 seconds |
| Started | Jun 23 07:32:54 PM PDT 24 |
| Finished | Jun 23 07:34:04 PM PDT 24 |
| Peak memory | 565224 kb |
| Host | smart-f3b7ffbe-2249-4e27-b641-083532ac5afb |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3601309029 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 50.xbar_smoke_slow_rsp.3601309029 |
| Directory | /workspace/50.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/50.xbar_smoke_zero_delays.381886287 |
| Short name | T1793 |
| Test name | |
| Test status | |
| Simulation time | 47689962 ps |
| CPU time | 6.62 seconds |
| Started | Jun 23 07:32:50 PM PDT 24 |
| Finished | Jun 23 07:32:57 PM PDT 24 |
| Peak memory | 565372 kb |
| Host | smart-462fe343-2ee9-4d9c-bfb3-93606c4e3e43 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=381886287 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 50.xbar_smoke_zero_delays .381886287 |
| Directory | /workspace/50.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/50.xbar_stress_all.3114661897 |
| Short name | T2808 |
| Test name | |
| Test status | |
| Simulation time | 444417622 ps |
| CPU time | 41.94 seconds |
| Started | Jun 23 07:33:02 PM PDT 24 |
| Finished | Jun 23 07:33:44 PM PDT 24 |
| Peak memory | 574196 kb |
| Host | smart-13bf8a7f-347a-478f-b0c6-24e41a070d15 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3114661897 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 50.xbar_stress_all.3114661897 |
| Directory | /workspace/50.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/50.xbar_stress_all_with_error.3128467806 |
| Short name | T1946 |
| Test name | |
| Test status | |
| Simulation time | 5310077164 ps |
| CPU time | 178.51 seconds |
| Started | Jun 23 07:32:57 PM PDT 24 |
| Finished | Jun 23 07:35:55 PM PDT 24 |
| Peak memory | 573556 kb |
| Host | smart-73edd47f-7817-4b51-96c9-72c29dc7b0ef |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3128467806 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 50.xbar_stress_all_with_error.3128467806 |
| Directory | /workspace/50.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/50.xbar_stress_all_with_rand_reset.2934387427 |
| Short name | T901 |
| Test name | |
| Test status | |
| Simulation time | 472253707 ps |
| CPU time | 247.75 seconds |
| Started | Jun 23 07:32:58 PM PDT 24 |
| Finished | Jun 23 07:37:06 PM PDT 24 |
| Peak memory | 576268 kb |
| Host | smart-e74ac171-97a6-4b23-8158-76a1f9e749e3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2934387427 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 50.xbar_stress_all _with_rand_reset.2934387427 |
| Directory | /workspace/50.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/50.xbar_stress_all_with_reset_error.589599092 |
| Short name | T907 |
| Test name | |
| Test status | |
| Simulation time | 620522600 ps |
| CPU time | 191.22 seconds |
| Started | Jun 23 07:32:54 PM PDT 24 |
| Finished | Jun 23 07:36:06 PM PDT 24 |
| Peak memory | 575356 kb |
| Host | smart-e3f7a1da-5ffb-4d9e-a65e-f5eac05d8e92 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=589599092 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 50.xbar_stress_all _with_reset_error.589599092 |
| Directory | /workspace/50.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/50.xbar_unmapped_addr.1985900711 |
| Short name | T2242 |
| Test name | |
| Test status | |
| Simulation time | 227471127 ps |
| CPU time | 11.82 seconds |
| Started | Jun 23 07:32:55 PM PDT 24 |
| Finished | Jun 23 07:33:07 PM PDT 24 |
| Peak memory | 573468 kb |
| Host | smart-34ed5413-3d86-4af4-95d2-65c4a2dc1e83 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1985900711 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 50.xbar_unmapped_addr.1985900711 |
| Directory | /workspace/50.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/51.xbar_access_same_device.1795726038 |
| Short name | T2155 |
| Test name | |
| Test status | |
| Simulation time | 1562028315 ps |
| CPU time | 61.02 seconds |
| Started | Jun 23 07:33:08 PM PDT 24 |
| Finished | Jun 23 07:34:09 PM PDT 24 |
| Peak memory | 573428 kb |
| Host | smart-54ce4092-4a25-44aa-a5d4-8ecdfe01f3d9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1795726038 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 51.xbar_access_same_device .1795726038 |
| Directory | /workspace/51.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/51.xbar_access_same_device_slow_rsp.296857997 |
| Short name | T2108 |
| Test name | |
| Test status | |
| Simulation time | 69359579855 ps |
| CPU time | 1230.99 seconds |
| Started | Jun 23 07:32:59 PM PDT 24 |
| Finished | Jun 23 07:53:31 PM PDT 24 |
| Peak memory | 574216 kb |
| Host | smart-942c09e8-f509-4fc2-8b7f-9445f2c6d41a |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=296857997 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 51.xbar_access_same_d evice_slow_rsp.296857997 |
| Directory | /workspace/51.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/51.xbar_error_and_unmapped_addr.1385832801 |
| Short name | T2120 |
| Test name | |
| Test status | |
| Simulation time | 488852396 ps |
| CPU time | 20.48 seconds |
| Started | Jun 23 07:33:02 PM PDT 24 |
| Finished | Jun 23 07:33:23 PM PDT 24 |
| Peak memory | 573700 kb |
| Host | smart-a8b48b31-7440-46f4-91ed-2f97d80a3ff7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1385832801 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 51.xbar_error_and_unmapped_add r.1385832801 |
| Directory | /workspace/51.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/51.xbar_error_random.1988215080 |
| Short name | T1526 |
| Test name | |
| Test status | |
| Simulation time | 2339162660 ps |
| CPU time | 78.57 seconds |
| Started | Jun 23 07:33:07 PM PDT 24 |
| Finished | Jun 23 07:34:26 PM PDT 24 |
| Peak memory | 573412 kb |
| Host | smart-398372b0-99be-4045-9dd2-6155f2b49dab |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1988215080 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 51.xbar_error_random.1988215080 |
| Directory | /workspace/51.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/51.xbar_random.3874706689 |
| Short name | T651 |
| Test name | |
| Test status | |
| Simulation time | 1426480341 ps |
| CPU time | 54.28 seconds |
| Started | Jun 23 07:32:58 PM PDT 24 |
| Finished | Jun 23 07:33:52 PM PDT 24 |
| Peak memory | 574072 kb |
| Host | smart-53c38401-5bf2-44b7-84bc-0c2cbed5e43f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3874706689 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 51.xbar_random.3874706689 |
| Directory | /workspace/51.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/51.xbar_random_large_delays.1541239852 |
| Short name | T2475 |
| Test name | |
| Test status | |
| Simulation time | 90106089997 ps |
| CPU time | 929.2 seconds |
| Started | Jun 23 07:33:08 PM PDT 24 |
| Finished | Jun 23 07:48:38 PM PDT 24 |
| Peak memory | 574216 kb |
| Host | smart-e906005d-1f76-40ff-afbb-122a5fa0ab4c |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1541239852 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 51.xbar_random_large_delays.1541239852 |
| Directory | /workspace/51.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/51.xbar_random_slow_rsp.491437115 |
| Short name | T1776 |
| Test name | |
| Test status | |
| Simulation time | 9856568297 ps |
| CPU time | 162.93 seconds |
| Started | Jun 23 07:32:59 PM PDT 24 |
| Finished | Jun 23 07:35:42 PM PDT 24 |
| Peak memory | 574152 kb |
| Host | smart-00c4574a-1011-49c4-990f-776fb9052ae6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=491437115 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 51.xbar_random_slow_rsp.491437115 |
| Directory | /workspace/51.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/51.xbar_random_zero_delays.3138291239 |
| Short name | T2323 |
| Test name | |
| Test status | |
| Simulation time | 547427182 ps |
| CPU time | 45.47 seconds |
| Started | Jun 23 07:33:00 PM PDT 24 |
| Finished | Jun 23 07:33:46 PM PDT 24 |
| Peak memory | 573424 kb |
| Host | smart-39f3b05f-06e9-4d93-9ac3-9ac0e5459c08 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3138291239 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 51.xbar_random_zero_del ays.3138291239 |
| Directory | /workspace/51.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/51.xbar_same_source.3037574959 |
| Short name | T1569 |
| Test name | |
| Test status | |
| Simulation time | 1725531744 ps |
| CPU time | 51.61 seconds |
| Started | Jun 23 07:33:00 PM PDT 24 |
| Finished | Jun 23 07:33:52 PM PDT 24 |
| Peak memory | 574096 kb |
| Host | smart-3d250dc0-d8f7-44cf-808c-758be31c9641 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3037574959 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 51.xbar_same_source.3037574959 |
| Directory | /workspace/51.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/51.xbar_smoke.3462436115 |
| Short name | T2844 |
| Test name | |
| Test status | |
| Simulation time | 227038965 ps |
| CPU time | 10.07 seconds |
| Started | Jun 23 07:32:56 PM PDT 24 |
| Finished | Jun 23 07:33:07 PM PDT 24 |
| Peak memory | 565852 kb |
| Host | smart-4c1fca9b-6cf0-4f23-ab76-6e18c81ec0fa |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3462436115 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 51.xbar_smoke.3462436115 |
| Directory | /workspace/51.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/51.xbar_smoke_large_delays.4085589863 |
| Short name | T2429 |
| Test name | |
| Test status | |
| Simulation time | 7251093403 ps |
| CPU time | 71.31 seconds |
| Started | Jun 23 07:32:57 PM PDT 24 |
| Finished | Jun 23 07:34:09 PM PDT 24 |
| Peak memory | 564880 kb |
| Host | smart-9a187ece-374e-461b-80c8-84251503e745 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4085589863 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 51.xbar_smoke_large_delays.4085589863 |
| Directory | /workspace/51.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/51.xbar_smoke_slow_rsp.229440668 |
| Short name | T2666 |
| Test name | |
| Test status | |
| Simulation time | 5467984301 ps |
| CPU time | 88.62 seconds |
| Started | Jun 23 07:32:56 PM PDT 24 |
| Finished | Jun 23 07:34:25 PM PDT 24 |
| Peak memory | 565940 kb |
| Host | smart-2063a196-7b62-4174-99c6-45b99226c442 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=229440668 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 51.xbar_smoke_slow_rsp.229440668 |
| Directory | /workspace/51.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/51.xbar_smoke_zero_delays.1646753965 |
| Short name | T2001 |
| Test name | |
| Test status | |
| Simulation time | 49307547 ps |
| CPU time | 6.92 seconds |
| Started | Jun 23 07:33:01 PM PDT 24 |
| Finished | Jun 23 07:33:08 PM PDT 24 |
| Peak memory | 565548 kb |
| Host | smart-c97df876-2bb7-4fd0-89bd-3d6840a1171e |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1646753965 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 51.xbar_smoke_zero_delay s.1646753965 |
| Directory | /workspace/51.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/51.xbar_stress_all.1726536296 |
| Short name | T583 |
| Test name | |
| Test status | |
| Simulation time | 13905134511 ps |
| CPU time | 462.22 seconds |
| Started | Jun 23 07:33:06 PM PDT 24 |
| Finished | Jun 23 07:40:48 PM PDT 24 |
| Peak memory | 574300 kb |
| Host | smart-29cc1aa1-d796-461c-9c38-34b2a25a41a4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1726536296 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 51.xbar_stress_all.1726536296 |
| Directory | /workspace/51.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/51.xbar_stress_all_with_error.3232283945 |
| Short name | T2565 |
| Test name | |
| Test status | |
| Simulation time | 195077454 ps |
| CPU time | 8.32 seconds |
| Started | Jun 23 07:33:03 PM PDT 24 |
| Finished | Jun 23 07:33:12 PM PDT 24 |
| Peak memory | 565436 kb |
| Host | smart-bf240ca6-19a3-421b-b3eb-a7190ebefb2d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3232283945 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 51.xbar_stress_all_with_error.3232283945 |
| Directory | /workspace/51.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/51.xbar_stress_all_with_rand_reset.2014463645 |
| Short name | T2426 |
| Test name | |
| Test status | |
| Simulation time | 259740908 ps |
| CPU time | 171.46 seconds |
| Started | Jun 23 07:33:02 PM PDT 24 |
| Finished | Jun 23 07:35:54 PM PDT 24 |
| Peak memory | 574252 kb |
| Host | smart-f5f38ded-83e1-4abb-a3f5-974aebf0b2b6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2014463645 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 51.xbar_stress_all _with_rand_reset.2014463645 |
| Directory | /workspace/51.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/51.xbar_stress_all_with_reset_error.2834332723 |
| Short name | T2788 |
| Test name | |
| Test status | |
| Simulation time | 122098430 ps |
| CPU time | 111.61 seconds |
| Started | Jun 23 07:33:07 PM PDT 24 |
| Finished | Jun 23 07:34:58 PM PDT 24 |
| Peak memory | 574316 kb |
| Host | smart-dc79eacb-cae0-4746-81b4-30e1e2ae217e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2834332723 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 51.xbar_stress_al l_with_reset_error.2834332723 |
| Directory | /workspace/51.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/51.xbar_unmapped_addr.1729290780 |
| Short name | T2784 |
| Test name | |
| Test status | |
| Simulation time | 828869871 ps |
| CPU time | 36.1 seconds |
| Started | Jun 23 07:33:08 PM PDT 24 |
| Finished | Jun 23 07:33:44 PM PDT 24 |
| Peak memory | 574144 kb |
| Host | smart-76e3e192-f859-4bb5-83e0-7561f907ab66 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1729290780 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 51.xbar_unmapped_addr.1729290780 |
| Directory | /workspace/51.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/52.xbar_access_same_device.908499669 |
| Short name | T1516 |
| Test name | |
| Test status | |
| Simulation time | 1321946998 ps |
| CPU time | 62.66 seconds |
| Started | Jun 23 07:33:07 PM PDT 24 |
| Finished | Jun 23 07:34:10 PM PDT 24 |
| Peak memory | 573456 kb |
| Host | smart-3775eff1-5dc7-4a57-99de-0793c7ced06c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=908499669 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 52.xbar_access_same_device. 908499669 |
| Directory | /workspace/52.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/52.xbar_access_same_device_slow_rsp.2590315271 |
| Short name | T2260 |
| Test name | |
| Test status | |
| Simulation time | 120957455511 ps |
| CPU time | 2066.88 seconds |
| Started | Jun 23 07:33:06 PM PDT 24 |
| Finished | Jun 23 08:07:34 PM PDT 24 |
| Peak memory | 574200 kb |
| Host | smart-6dc450ad-7b9e-4868-9d53-80b1810749b9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2590315271 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 52.xbar_access_same_ device_slow_rsp.2590315271 |
| Directory | /workspace/52.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/52.xbar_error_and_unmapped_addr.1539138011 |
| Short name | T1417 |
| Test name | |
| Test status | |
| Simulation time | 1205294902 ps |
| CPU time | 45.28 seconds |
| Started | Jun 23 07:33:19 PM PDT 24 |
| Finished | Jun 23 07:34:05 PM PDT 24 |
| Peak memory | 573748 kb |
| Host | smart-aa5b4a3d-8862-40d6-9c8c-8b402e900186 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1539138011 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 52.xbar_error_and_unmapped_add r.1539138011 |
| Directory | /workspace/52.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/52.xbar_error_random.1439538644 |
| Short name | T649 |
| Test name | |
| Test status | |
| Simulation time | 1614158631 ps |
| CPU time | 60.14 seconds |
| Started | Jun 23 07:33:17 PM PDT 24 |
| Finished | Jun 23 07:34:17 PM PDT 24 |
| Peak memory | 573360 kb |
| Host | smart-84085cb5-61fb-46bf-9b98-de53dc5e95cb |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1439538644 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 52.xbar_error_random.1439538644 |
| Directory | /workspace/52.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/52.xbar_random.356989543 |
| Short name | T2010 |
| Test name | |
| Test status | |
| Simulation time | 505874644 ps |
| CPU time | 39.42 seconds |
| Started | Jun 23 07:33:05 PM PDT 24 |
| Finished | Jun 23 07:33:45 PM PDT 24 |
| Peak memory | 574120 kb |
| Host | smart-2279a354-02ed-4507-b340-ceea3601f570 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=356989543 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 52.xbar_random.356989543 |
| Directory | /workspace/52.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/52.xbar_random_large_delays.1436637775 |
| Short name | T477 |
| Test name | |
| Test status | |
| Simulation time | 79990793341 ps |
| CPU time | 840.85 seconds |
| Started | Jun 23 07:33:05 PM PDT 24 |
| Finished | Jun 23 07:47:06 PM PDT 24 |
| Peak memory | 574176 kb |
| Host | smart-7eca0556-c1ac-462d-bacf-6b4c59231a25 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1436637775 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 52.xbar_random_large_delays.1436637775 |
| Directory | /workspace/52.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/52.xbar_random_slow_rsp.1933785048 |
| Short name | T573 |
| Test name | |
| Test status | |
| Simulation time | 64873779199 ps |
| CPU time | 1176.19 seconds |
| Started | Jun 23 07:33:08 PM PDT 24 |
| Finished | Jun 23 07:52:45 PM PDT 24 |
| Peak memory | 574200 kb |
| Host | smart-12463ae6-5308-4a03-8498-931464a4dbfb |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1933785048 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 52.xbar_random_slow_rsp.1933785048 |
| Directory | /workspace/52.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/52.xbar_random_zero_delays.3043680578 |
| Short name | T2389 |
| Test name | |
| Test status | |
| Simulation time | 35879708 ps |
| CPU time | 6.08 seconds |
| Started | Jun 23 07:33:09 PM PDT 24 |
| Finished | Jun 23 07:33:15 PM PDT 24 |
| Peak memory | 565688 kb |
| Host | smart-22fb48ca-8df1-4288-a14f-83d4ccf07e44 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3043680578 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 52.xbar_random_zero_del ays.3043680578 |
| Directory | /workspace/52.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/52.xbar_same_source.2868758049 |
| Short name | T2188 |
| Test name | |
| Test status | |
| Simulation time | 2385586833 ps |
| CPU time | 66.22 seconds |
| Started | Jun 23 07:33:07 PM PDT 24 |
| Finished | Jun 23 07:34:14 PM PDT 24 |
| Peak memory | 573792 kb |
| Host | smart-4f9e9fa6-9e48-4568-b8d8-f3c26115ed35 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2868758049 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 52.xbar_same_source.2868758049 |
| Directory | /workspace/52.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/52.xbar_smoke.1454278733 |
| Short name | T1513 |
| Test name | |
| Test status | |
| Simulation time | 215571751 ps |
| CPU time | 9.58 seconds |
| Started | Jun 23 07:33:02 PM PDT 24 |
| Finished | Jun 23 07:33:12 PM PDT 24 |
| Peak memory | 565472 kb |
| Host | smart-6f70348e-3392-46bb-a1fe-bb41c04d28a7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1454278733 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 52.xbar_smoke.1454278733 |
| Directory | /workspace/52.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/52.xbar_smoke_large_delays.995705102 |
| Short name | T2745 |
| Test name | |
| Test status | |
| Simulation time | 7879457944 ps |
| CPU time | 80 seconds |
| Started | Jun 23 07:33:02 PM PDT 24 |
| Finished | Jun 23 07:34:22 PM PDT 24 |
| Peak memory | 565508 kb |
| Host | smart-df3c0cb1-7b41-40b6-b164-037e2bc84184 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=995705102 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 52.xbar_smoke_large_delays.995705102 |
| Directory | /workspace/52.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/52.xbar_smoke_slow_rsp.1813670887 |
| Short name | T1721 |
| Test name | |
| Test status | |
| Simulation time | 6556280229 ps |
| CPU time | 106.26 seconds |
| Started | Jun 23 07:33:08 PM PDT 24 |
| Finished | Jun 23 07:34:55 PM PDT 24 |
| Peak memory | 565260 kb |
| Host | smart-d3d294be-a177-4e3a-a909-d202ff204cc5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1813670887 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 52.xbar_smoke_slow_rsp.1813670887 |
| Directory | /workspace/52.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/52.xbar_smoke_zero_delays.3869171211 |
| Short name | T2714 |
| Test name | |
| Test status | |
| Simulation time | 40904137 ps |
| CPU time | 5.84 seconds |
| Started | Jun 23 07:33:02 PM PDT 24 |
| Finished | Jun 23 07:33:08 PM PDT 24 |
| Peak memory | 565460 kb |
| Host | smart-80057312-6b37-40a3-b82a-baf8c78aceb5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3869171211 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 52.xbar_smoke_zero_delay s.3869171211 |
| Directory | /workspace/52.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/52.xbar_stress_all.830381492 |
| Short name | T2668 |
| Test name | |
| Test status | |
| Simulation time | 6342172932 ps |
| CPU time | 250.09 seconds |
| Started | Jun 23 07:33:16 PM PDT 24 |
| Finished | Jun 23 07:37:27 PM PDT 24 |
| Peak memory | 573632 kb |
| Host | smart-85cf912c-d879-40e5-a122-06dcbdbd7134 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=830381492 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 52.xbar_stress_all.830381492 |
| Directory | /workspace/52.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/52.xbar_stress_all_with_error.390642542 |
| Short name | T2139 |
| Test name | |
| Test status | |
| Simulation time | 1737813738 ps |
| CPU time | 52.79 seconds |
| Started | Jun 23 07:33:18 PM PDT 24 |
| Finished | Jun 23 07:34:12 PM PDT 24 |
| Peak memory | 573388 kb |
| Host | smart-86ed4a86-4d4a-4415-a0ae-bedc915a4c59 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=390642542 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 52.xbar_stress_all_with_error.390642542 |
| Directory | /workspace/52.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/52.xbar_stress_all_with_rand_reset.345437083 |
| Short name | T2515 |
| Test name | |
| Test status | |
| Simulation time | 9463601890 ps |
| CPU time | 463.07 seconds |
| Started | Jun 23 07:33:18 PM PDT 24 |
| Finished | Jun 23 07:41:01 PM PDT 24 |
| Peak memory | 575268 kb |
| Host | smart-b9ed16da-db08-4459-8485-cc873d478ffa |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=345437083 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_res et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 52.xbar_stress_all_ with_rand_reset.345437083 |
| Directory | /workspace/52.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/52.xbar_stress_all_with_reset_error.4047954062 |
| Short name | T2748 |
| Test name | |
| Test status | |
| Simulation time | 142350926 ps |
| CPU time | 32.44 seconds |
| Started | Jun 23 07:33:19 PM PDT 24 |
| Finished | Jun 23 07:33:52 PM PDT 24 |
| Peak memory | 574248 kb |
| Host | smart-d4767317-2c86-4a6a-a4b9-472cb7a9a275 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4047954062 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 52.xbar_stress_al l_with_reset_error.4047954062 |
| Directory | /workspace/52.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/52.xbar_unmapped_addr.2954032263 |
| Short name | T2273 |
| Test name | |
| Test status | |
| Simulation time | 240418823 ps |
| CPU time | 26.4 seconds |
| Started | Jun 23 07:33:19 PM PDT 24 |
| Finished | Jun 23 07:33:46 PM PDT 24 |
| Peak memory | 574144 kb |
| Host | smart-718f8cdd-9acc-4f34-9603-7689e2711072 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2954032263 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 52.xbar_unmapped_addr.2954032263 |
| Directory | /workspace/52.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/53.xbar_access_same_device.3257143532 |
| Short name | T2801 |
| Test name | |
| Test status | |
| Simulation time | 1814388450 ps |
| CPU time | 75.29 seconds |
| Started | Jun 23 07:33:19 PM PDT 24 |
| Finished | Jun 23 07:34:34 PM PDT 24 |
| Peak memory | 574124 kb |
| Host | smart-a3852da3-ab48-44ce-bfc4-9ef1c66fad74 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3257143532 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 53.xbar_access_same_device .3257143532 |
| Directory | /workspace/53.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/53.xbar_access_same_device_slow_rsp.2489158416 |
| Short name | T1990 |
| Test name | |
| Test status | |
| Simulation time | 53021474206 ps |
| CPU time | 940.82 seconds |
| Started | Jun 23 07:33:44 PM PDT 24 |
| Finished | Jun 23 07:49:25 PM PDT 24 |
| Peak memory | 574192 kb |
| Host | smart-33a674ab-eebd-47e6-bbb0-99f23306dd7c |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2489158416 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 53.xbar_access_same_ device_slow_rsp.2489158416 |
| Directory | /workspace/53.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/53.xbar_error_and_unmapped_addr.4271337882 |
| Short name | T2702 |
| Test name | |
| Test status | |
| Simulation time | 957516848 ps |
| CPU time | 35.11 seconds |
| Started | Jun 23 07:33:46 PM PDT 24 |
| Finished | Jun 23 07:34:21 PM PDT 24 |
| Peak memory | 573744 kb |
| Host | smart-8b8e5f95-0302-4579-bbf1-ab658d75022a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4271337882 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 53.xbar_error_and_unmapped_add r.4271337882 |
| Directory | /workspace/53.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/53.xbar_error_random.393403007 |
| Short name | T2416 |
| Test name | |
| Test status | |
| Simulation time | 403269309 ps |
| CPU time | 14.91 seconds |
| Started | Jun 23 07:34:48 PM PDT 24 |
| Finished | Jun 23 07:35:03 PM PDT 24 |
| Peak memory | 573348 kb |
| Host | smart-57caf0dd-ab24-4dfb-add0-a6c56312e79f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=393403007 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 53.xbar_error_random.393403007 |
| Directory | /workspace/53.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/53.xbar_random.568398216 |
| Short name | T1778 |
| Test name | |
| Test status | |
| Simulation time | 1241752087 ps |
| CPU time | 43.12 seconds |
| Started | Jun 23 07:33:20 PM PDT 24 |
| Finished | Jun 23 07:34:03 PM PDT 24 |
| Peak memory | 574096 kb |
| Host | smart-d0172191-302f-4569-bb3d-ea9aa3476a84 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=568398216 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 53.xbar_random.568398216 |
| Directory | /workspace/53.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/53.xbar_random_large_delays.3421048292 |
| Short name | T2813 |
| Test name | |
| Test status | |
| Simulation time | 21990337847 ps |
| CPU time | 239.67 seconds |
| Started | Jun 23 07:33:19 PM PDT 24 |
| Finished | Jun 23 07:37:19 PM PDT 24 |
| Peak memory | 574196 kb |
| Host | smart-de09c4fe-b01a-493e-ad60-15e5d7800f09 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3421048292 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 53.xbar_random_large_delays.3421048292 |
| Directory | /workspace/53.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/53.xbar_random_slow_rsp.2365292152 |
| Short name | T657 |
| Test name | |
| Test status | |
| Simulation time | 56422229110 ps |
| CPU time | 945.27 seconds |
| Started | Jun 23 07:33:17 PM PDT 24 |
| Finished | Jun 23 07:49:03 PM PDT 24 |
| Peak memory | 574164 kb |
| Host | smart-1b68e1e1-a908-4983-ae22-e591e45f283d |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2365292152 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 53.xbar_random_slow_rsp.2365292152 |
| Directory | /workspace/53.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/53.xbar_random_zero_delays.3340052616 |
| Short name | T628 |
| Test name | |
| Test status | |
| Simulation time | 145554779 ps |
| CPU time | 14.73 seconds |
| Started | Jun 23 07:33:18 PM PDT 24 |
| Finished | Jun 23 07:33:33 PM PDT 24 |
| Peak memory | 573688 kb |
| Host | smart-40abb9fe-0ce4-4bfe-ae2c-604f453ee641 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3340052616 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 53.xbar_random_zero_del ays.3340052616 |
| Directory | /workspace/53.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/53.xbar_same_source.2751520364 |
| Short name | T2800 |
| Test name | |
| Test status | |
| Simulation time | 736334399 ps |
| CPU time | 22.55 seconds |
| Started | Jun 23 07:33:43 PM PDT 24 |
| Finished | Jun 23 07:34:06 PM PDT 24 |
| Peak memory | 574032 kb |
| Host | smart-d72d5fe0-a2dd-4ecd-a943-16ca0ca0bb07 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2751520364 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 53.xbar_same_source.2751520364 |
| Directory | /workspace/53.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/53.xbar_smoke.865467769 |
| Short name | T2419 |
| Test name | |
| Test status | |
| Simulation time | 243830675 ps |
| CPU time | 9.44 seconds |
| Started | Jun 23 07:33:19 PM PDT 24 |
| Finished | Jun 23 07:33:29 PM PDT 24 |
| Peak memory | 565176 kb |
| Host | smart-de0d855b-03e9-42e0-9300-825124e3e6fc |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=865467769 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 53.xbar_smoke.865467769 |
| Directory | /workspace/53.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/53.xbar_smoke_large_delays.3494400726 |
| Short name | T1467 |
| Test name | |
| Test status | |
| Simulation time | 9216133345 ps |
| CPU time | 90.44 seconds |
| Started | Jun 23 07:33:20 PM PDT 24 |
| Finished | Jun 23 07:34:51 PM PDT 24 |
| Peak memory | 573748 kb |
| Host | smart-0f952d0f-d8d1-4d7d-a31c-2e60599c71da |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3494400726 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 53.xbar_smoke_large_delays.3494400726 |
| Directory | /workspace/53.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/53.xbar_smoke_slow_rsp.4144680048 |
| Short name | T1650 |
| Test name | |
| Test status | |
| Simulation time | 3953547605 ps |
| CPU time | 70.62 seconds |
| Started | Jun 23 07:33:18 PM PDT 24 |
| Finished | Jun 23 07:34:29 PM PDT 24 |
| Peak memory | 565932 kb |
| Host | smart-916aa0ca-f25f-4333-bdb5-216a2cfe039b |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4144680048 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 53.xbar_smoke_slow_rsp.4144680048 |
| Directory | /workspace/53.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/53.xbar_smoke_zero_delays.3555498347 |
| Short name | T2195 |
| Test name | |
| Test status | |
| Simulation time | 41213280 ps |
| CPU time | 6.31 seconds |
| Started | Jun 23 07:33:18 PM PDT 24 |
| Finished | Jun 23 07:33:25 PM PDT 24 |
| Peak memory | 565184 kb |
| Host | smart-9a7dbb69-79db-4d87-b49b-208a27ceab8e |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3555498347 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 53.xbar_smoke_zero_delay s.3555498347 |
| Directory | /workspace/53.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/53.xbar_stress_all.1711338540 |
| Short name | T2847 |
| Test name | |
| Test status | |
| Simulation time | 1033208113 ps |
| CPU time | 88.63 seconds |
| Started | Jun 23 07:33:49 PM PDT 24 |
| Finished | Jun 23 07:35:18 PM PDT 24 |
| Peak memory | 573536 kb |
| Host | smart-d75bd7b2-b307-4860-ad67-599a9e4f23cd |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1711338540 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 53.xbar_stress_all.1711338540 |
| Directory | /workspace/53.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/53.xbar_stress_all_with_rand_reset.732852865 |
| Short name | T2207 |
| Test name | |
| Test status | |
| Simulation time | 4786853299 ps |
| CPU time | 599.31 seconds |
| Started | Jun 23 07:33:45 PM PDT 24 |
| Finished | Jun 23 07:43:44 PM PDT 24 |
| Peak memory | 574328 kb |
| Host | smart-3e64d861-1f29-47a0-83e3-1833b0e4fc2f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=732852865 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_res et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 53.xbar_stress_all_ with_rand_reset.732852865 |
| Directory | /workspace/53.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/53.xbar_stress_all_with_reset_error.1495010749 |
| Short name | T2603 |
| Test name | |
| Test status | |
| Simulation time | 408116743 ps |
| CPU time | 85.69 seconds |
| Started | Jun 23 07:33:57 PM PDT 24 |
| Finished | Jun 23 07:35:23 PM PDT 24 |
| Peak memory | 576296 kb |
| Host | smart-6edf9c08-9fe8-4c4c-8e49-bb5c219543f5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1495010749 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 53.xbar_stress_al l_with_reset_error.1495010749 |
| Directory | /workspace/53.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/53.xbar_unmapped_addr.1157775683 |
| Short name | T2870 |
| Test name | |
| Test status | |
| Simulation time | 783282806 ps |
| CPU time | 30.78 seconds |
| Started | Jun 23 07:33:47 PM PDT 24 |
| Finished | Jun 23 07:34:18 PM PDT 24 |
| Peak memory | 574128 kb |
| Host | smart-35fab0e7-e9da-4447-9c1e-ffc8f7a04254 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1157775683 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 53.xbar_unmapped_addr.1157775683 |
| Directory | /workspace/53.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/54.xbar_access_same_device.2667714572 |
| Short name | T2372 |
| Test name | |
| Test status | |
| Simulation time | 234401939 ps |
| CPU time | 11.28 seconds |
| Started | Jun 23 07:33:58 PM PDT 24 |
| Finished | Jun 23 07:34:10 PM PDT 24 |
| Peak memory | 565500 kb |
| Host | smart-5db6324a-e8e6-4602-8f31-89e0704156e4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2667714572 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 54.xbar_access_same_device .2667714572 |
| Directory | /workspace/54.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/54.xbar_access_same_device_slow_rsp.813435054 |
| Short name | T2652 |
| Test name | |
| Test status | |
| Simulation time | 21404049877 ps |
| CPU time | 377.76 seconds |
| Started | Jun 23 07:33:51 PM PDT 24 |
| Finished | Jun 23 07:40:09 PM PDT 24 |
| Peak memory | 574188 kb |
| Host | smart-40e48a40-2cd8-457a-95fc-4b4b441cd0a2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=813435054 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 54.xbar_access_same_d evice_slow_rsp.813435054 |
| Directory | /workspace/54.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/54.xbar_error_and_unmapped_addr.2105857206 |
| Short name | T1494 |
| Test name | |
| Test status | |
| Simulation time | 156160841 ps |
| CPU time | 8.9 seconds |
| Started | Jun 23 07:33:52 PM PDT 24 |
| Finished | Jun 23 07:34:01 PM PDT 24 |
| Peak memory | 573364 kb |
| Host | smart-d1396693-3894-4550-ac1b-33a3637b58d0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2105857206 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 54.xbar_error_and_unmapped_add r.2105857206 |
| Directory | /workspace/54.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/54.xbar_error_random.1508134436 |
| Short name | T2355 |
| Test name | |
| Test status | |
| Simulation time | 1978768218 ps |
| CPU time | 70.94 seconds |
| Started | Jun 23 07:33:49 PM PDT 24 |
| Finished | Jun 23 07:35:01 PM PDT 24 |
| Peak memory | 573340 kb |
| Host | smart-4566e359-e069-4827-a36a-153b26ecd2fe |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1508134436 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 54.xbar_error_random.1508134436 |
| Directory | /workspace/54.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/54.xbar_random.532049123 |
| Short name | T606 |
| Test name | |
| Test status | |
| Simulation time | 254839120 ps |
| CPU time | 22.66 seconds |
| Started | Jun 23 07:33:54 PM PDT 24 |
| Finished | Jun 23 07:34:17 PM PDT 24 |
| Peak memory | 574124 kb |
| Host | smart-90989ccd-c481-4dc6-8d55-2358ebaa25fc |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=532049123 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 54.xbar_random.532049123 |
| Directory | /workspace/54.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/54.xbar_random_large_delays.670803819 |
| Short name | T1979 |
| Test name | |
| Test status | |
| Simulation time | 72219748878 ps |
| CPU time | 750.41 seconds |
| Started | Jun 23 07:33:52 PM PDT 24 |
| Finished | Jun 23 07:46:23 PM PDT 24 |
| Peak memory | 574212 kb |
| Host | smart-0a52fadd-93f4-4262-b1e1-153ca33d4f74 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=670803819 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 54.xbar_random_large_delays.670803819 |
| Directory | /workspace/54.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/54.xbar_random_slow_rsp.2181887045 |
| Short name | T1684 |
| Test name | |
| Test status | |
| Simulation time | 4311443621 ps |
| CPU time | 70.19 seconds |
| Started | Jun 23 07:33:53 PM PDT 24 |
| Finished | Jun 23 07:35:03 PM PDT 24 |
| Peak memory | 565588 kb |
| Host | smart-6a9d88d0-461b-4fb4-a817-ce01947515d3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2181887045 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 54.xbar_random_slow_rsp.2181887045 |
| Directory | /workspace/54.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/54.xbar_random_zero_delays.1608824756 |
| Short name | T2170 |
| Test name | |
| Test status | |
| Simulation time | 595019025 ps |
| CPU time | 47.85 seconds |
| Started | Jun 23 07:33:52 PM PDT 24 |
| Finished | Jun 23 07:34:40 PM PDT 24 |
| Peak memory | 574104 kb |
| Host | smart-4b11c38e-11a4-4978-a631-359ad6b6df79 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1608824756 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 54.xbar_random_zero_del ays.1608824756 |
| Directory | /workspace/54.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/54.xbar_same_source.1230700946 |
| Short name | T1508 |
| Test name | |
| Test status | |
| Simulation time | 442236965 ps |
| CPU time | 15.22 seconds |
| Started | Jun 23 07:33:51 PM PDT 24 |
| Finished | Jun 23 07:34:07 PM PDT 24 |
| Peak memory | 573980 kb |
| Host | smart-a5698998-2eaf-444d-a9e7-5eb01e57be6c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1230700946 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 54.xbar_same_source.1230700946 |
| Directory | /workspace/54.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/54.xbar_smoke.1367122822 |
| Short name | T2412 |
| Test name | |
| Test status | |
| Simulation time | 50418524 ps |
| CPU time | 6.55 seconds |
| Started | Jun 23 07:33:57 PM PDT 24 |
| Finished | Jun 23 07:34:04 PM PDT 24 |
| Peak memory | 573992 kb |
| Host | smart-fbfb1d85-de0f-448d-a2c2-8c3e51320b3d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1367122822 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 54.xbar_smoke.1367122822 |
| Directory | /workspace/54.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/54.xbar_smoke_large_delays.157602637 |
| Short name | T1668 |
| Test name | |
| Test status | |
| Simulation time | 6774587801 ps |
| CPU time | 72.64 seconds |
| Started | Jun 23 07:33:56 PM PDT 24 |
| Finished | Jun 23 07:35:10 PM PDT 24 |
| Peak memory | 565536 kb |
| Host | smart-61f22cdf-0740-4824-afcb-5e1586f26ea0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=157602637 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 54.xbar_smoke_large_delays.157602637 |
| Directory | /workspace/54.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/54.xbar_smoke_slow_rsp.1816193396 |
| Short name | T639 |
| Test name | |
| Test status | |
| Simulation time | 4162292384 ps |
| CPU time | 67.23 seconds |
| Started | Jun 23 07:33:51 PM PDT 24 |
| Finished | Jun 23 07:34:59 PM PDT 24 |
| Peak memory | 565564 kb |
| Host | smart-14f32554-5463-4ef0-98ff-71bd3076e3e4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1816193396 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 54.xbar_smoke_slow_rsp.1816193396 |
| Directory | /workspace/54.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/54.xbar_smoke_zero_delays.3778471803 |
| Short name | T2245 |
| Test name | |
| Test status | |
| Simulation time | 45377802 ps |
| CPU time | 6.07 seconds |
| Started | Jun 23 07:33:54 PM PDT 24 |
| Finished | Jun 23 07:34:01 PM PDT 24 |
| Peak memory | 573656 kb |
| Host | smart-d452f1b6-d36b-4423-85dd-750dc08f110c |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3778471803 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 54.xbar_smoke_zero_delay s.3778471803 |
| Directory | /workspace/54.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/54.xbar_stress_all.2005446410 |
| Short name | T2657 |
| Test name | |
| Test status | |
| Simulation time | 6506081350 ps |
| CPU time | 209.95 seconds |
| Started | Jun 23 07:33:50 PM PDT 24 |
| Finished | Jun 23 07:37:21 PM PDT 24 |
| Peak memory | 574156 kb |
| Host | smart-59af8e19-63b9-4b07-a575-82327a2fb3d4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2005446410 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 54.xbar_stress_all.2005446410 |
| Directory | /workspace/54.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/54.xbar_stress_all_with_error.3376265452 |
| Short name | T2742 |
| Test name | |
| Test status | |
| Simulation time | 2751177925 ps |
| CPU time | 215.06 seconds |
| Started | Jun 23 07:33:50 PM PDT 24 |
| Finished | Jun 23 07:37:26 PM PDT 24 |
| Peak memory | 573564 kb |
| Host | smart-ef226c2b-1b9d-4cdd-bdfa-1dfbb70e4d8d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3376265452 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 54.xbar_stress_all_with_error.3376265452 |
| Directory | /workspace/54.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/54.xbar_stress_all_with_rand_reset.3115036939 |
| Short name | T2644 |
| Test name | |
| Test status | |
| Simulation time | 257530827 ps |
| CPU time | 109.96 seconds |
| Started | Jun 23 07:33:50 PM PDT 24 |
| Finished | Jun 23 07:35:40 PM PDT 24 |
| Peak memory | 576292 kb |
| Host | smart-7436659b-14eb-4091-957c-f3643f8dec22 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3115036939 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 54.xbar_stress_all _with_rand_reset.3115036939 |
| Directory | /workspace/54.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/54.xbar_stress_all_with_reset_error.4260026010 |
| Short name | T2125 |
| Test name | |
| Test status | |
| Simulation time | 1174221482 ps |
| CPU time | 260.23 seconds |
| Started | Jun 23 07:33:51 PM PDT 24 |
| Finished | Jun 23 07:38:12 PM PDT 24 |
| Peak memory | 574316 kb |
| Host | smart-676b327b-af31-41be-b5de-0a10a31a3357 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4260026010 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 54.xbar_stress_al l_with_reset_error.4260026010 |
| Directory | /workspace/54.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/54.xbar_unmapped_addr.1039737071 |
| Short name | T2835 |
| Test name | |
| Test status | |
| Simulation time | 884153161 ps |
| CPU time | 35.64 seconds |
| Started | Jun 23 07:33:59 PM PDT 24 |
| Finished | Jun 23 07:34:35 PM PDT 24 |
| Peak memory | 573324 kb |
| Host | smart-dae89afe-f38c-4a94-90ea-dcc1ee069485 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1039737071 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 54.xbar_unmapped_addr.1039737071 |
| Directory | /workspace/54.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/55.xbar_access_same_device.3194319382 |
| Short name | T2382 |
| Test name | |
| Test status | |
| Simulation time | 625981375 ps |
| CPU time | 53.29 seconds |
| Started | Jun 23 07:33:55 PM PDT 24 |
| Finished | Jun 23 07:34:48 PM PDT 24 |
| Peak memory | 574088 kb |
| Host | smart-bc1e2934-1b5b-47b8-89fe-bc8ae2ca775f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3194319382 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 55.xbar_access_same_device .3194319382 |
| Directory | /workspace/55.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/55.xbar_access_same_device_slow_rsp.3357315292 |
| Short name | T1610 |
| Test name | |
| Test status | |
| Simulation time | 20871226699 ps |
| CPU time | 380.06 seconds |
| Started | Jun 23 07:33:51 PM PDT 24 |
| Finished | Jun 23 07:40:12 PM PDT 24 |
| Peak memory | 574160 kb |
| Host | smart-7cde62b9-cb6e-445e-b7f8-969da4531e05 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3357315292 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 55.xbar_access_same_ device_slow_rsp.3357315292 |
| Directory | /workspace/55.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/55.xbar_error_and_unmapped_addr.986409187 |
| Short name | T1383 |
| Test name | |
| Test status | |
| Simulation time | 474239419 ps |
| CPU time | 20.42 seconds |
| Started | Jun 23 07:33:53 PM PDT 24 |
| Finished | Jun 23 07:34:13 PM PDT 24 |
| Peak memory | 573312 kb |
| Host | smart-257c0213-2ca1-48bd-bd7f-dd7a7f7886ac |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=986409187 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 55.xbar_error_and_unmapped_addr .986409187 |
| Directory | /workspace/55.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/55.xbar_error_random.53280177 |
| Short name | T1545 |
| Test name | |
| Test status | |
| Simulation time | 1978589608 ps |
| CPU time | 71.9 seconds |
| Started | Jun 23 07:33:57 PM PDT 24 |
| Finished | Jun 23 07:35:09 PM PDT 24 |
| Peak memory | 573464 kb |
| Host | smart-e7c62eaf-7ec0-454a-8f53-6282ecb7d441 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53280177 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 55.xbar_error_random.53280177 |
| Directory | /workspace/55.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/55.xbar_random.3107130302 |
| Short name | T1453 |
| Test name | |
| Test status | |
| Simulation time | 954771116 ps |
| CPU time | 39.22 seconds |
| Started | Jun 23 07:33:57 PM PDT 24 |
| Finished | Jun 23 07:34:36 PM PDT 24 |
| Peak memory | 574052 kb |
| Host | smart-9543bce6-4a7d-457c-bc26-1d160bb6f300 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3107130302 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 55.xbar_random.3107130302 |
| Directory | /workspace/55.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/55.xbar_random_large_delays.2496889746 |
| Short name | T2407 |
| Test name | |
| Test status | |
| Simulation time | 85072732348 ps |
| CPU time | 969.66 seconds |
| Started | Jun 23 07:33:59 PM PDT 24 |
| Finished | Jun 23 07:50:09 PM PDT 24 |
| Peak memory | 573348 kb |
| Host | smart-1905466c-1d39-4ed9-b686-4e226d31227d |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2496889746 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 55.xbar_random_large_delays.2496889746 |
| Directory | /workspace/55.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/55.xbar_random_slow_rsp.3142396739 |
| Short name | T661 |
| Test name | |
| Test status | |
| Simulation time | 40779337169 ps |
| CPU time | 710.72 seconds |
| Started | Jun 23 07:33:56 PM PDT 24 |
| Finished | Jun 23 07:45:47 PM PDT 24 |
| Peak memory | 574180 kb |
| Host | smart-3ee6295e-13d5-4964-8e98-10ba8b82a026 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3142396739 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 55.xbar_random_slow_rsp.3142396739 |
| Directory | /workspace/55.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/55.xbar_random_zero_delays.1871849458 |
| Short name | T1950 |
| Test name | |
| Test status | |
| Simulation time | 580560628 ps |
| CPU time | 54.5 seconds |
| Started | Jun 23 07:33:51 PM PDT 24 |
| Finished | Jun 23 07:34:45 PM PDT 24 |
| Peak memory | 574120 kb |
| Host | smart-caf64273-d7cf-4489-9445-a03a142167ff |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1871849458 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 55.xbar_random_zero_del ays.1871849458 |
| Directory | /workspace/55.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/55.xbar_same_source.2569392737 |
| Short name | T568 |
| Test name | |
| Test status | |
| Simulation time | 1457284713 ps |
| CPU time | 40.93 seconds |
| Started | Jun 23 07:33:50 PM PDT 24 |
| Finished | Jun 23 07:34:31 PM PDT 24 |
| Peak memory | 573348 kb |
| Host | smart-135c597e-baa2-49f2-b846-dd5c36af2e89 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2569392737 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 55.xbar_same_source.2569392737 |
| Directory | /workspace/55.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/55.xbar_smoke.1899004512 |
| Short name | T1870 |
| Test name | |
| Test status | |
| Simulation time | 50991186 ps |
| CPU time | 6.53 seconds |
| Started | Jun 23 07:33:53 PM PDT 24 |
| Finished | Jun 23 07:34:00 PM PDT 24 |
| Peak memory | 565484 kb |
| Host | smart-ea00cdda-2856-4748-9e8b-081419147e32 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1899004512 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 55.xbar_smoke.1899004512 |
| Directory | /workspace/55.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/55.xbar_smoke_large_delays.704363348 |
| Short name | T1653 |
| Test name | |
| Test status | |
| Simulation time | 8088738113 ps |
| CPU time | 83.52 seconds |
| Started | Jun 23 07:33:55 PM PDT 24 |
| Finished | Jun 23 07:35:19 PM PDT 24 |
| Peak memory | 565388 kb |
| Host | smart-0658f6a7-7184-4129-a46b-abefbc530e20 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=704363348 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 55.xbar_smoke_large_delays.704363348 |
| Directory | /workspace/55.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/55.xbar_smoke_slow_rsp.2510314118 |
| Short name | T1404 |
| Test name | |
| Test status | |
| Simulation time | 4225492566 ps |
| CPU time | 66.17 seconds |
| Started | Jun 23 07:33:49 PM PDT 24 |
| Finished | Jun 23 07:34:56 PM PDT 24 |
| Peak memory | 565612 kb |
| Host | smart-94ad9394-9d44-489f-a215-6a326bc6099b |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2510314118 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 55.xbar_smoke_slow_rsp.2510314118 |
| Directory | /workspace/55.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/55.xbar_smoke_zero_delays.75649702 |
| Short name | T2264 |
| Test name | |
| Test status | |
| Simulation time | 54243059 ps |
| CPU time | 6.26 seconds |
| Started | Jun 23 07:33:54 PM PDT 24 |
| Finished | Jun 23 07:34:01 PM PDT 24 |
| Peak memory | 565516 kb |
| Host | smart-8ae10c24-0e61-475a-9d01-481436b10750 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75649702 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 55.xbar_smoke_zero_delays.75649702 |
| Directory | /workspace/55.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/55.xbar_stress_all.617242341 |
| Short name | T2807 |
| Test name | |
| Test status | |
| Simulation time | 4329976292 ps |
| CPU time | 332.41 seconds |
| Started | Jun 23 07:33:57 PM PDT 24 |
| Finished | Jun 23 07:39:30 PM PDT 24 |
| Peak memory | 574404 kb |
| Host | smart-af075f2d-963a-4e6c-86fb-d91279a071af |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=617242341 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 55.xbar_stress_all.617242341 |
| Directory | /workspace/55.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/55.xbar_stress_all_with_error.2142270437 |
| Short name | T1971 |
| Test name | |
| Test status | |
| Simulation time | 10261240857 ps |
| CPU time | 321.05 seconds |
| Started | Jun 23 07:33:54 PM PDT 24 |
| Finished | Jun 23 07:39:16 PM PDT 24 |
| Peak memory | 573576 kb |
| Host | smart-8d972e23-ce39-48d5-a6ea-cdd789c53b3e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2142270437 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 55.xbar_stress_all_with_error.2142270437 |
| Directory | /workspace/55.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/55.xbar_stress_all_with_rand_reset.3721585231 |
| Short name | T2647 |
| Test name | |
| Test status | |
| Simulation time | 171844606 ps |
| CPU time | 72.57 seconds |
| Started | Jun 23 07:33:51 PM PDT 24 |
| Finished | Jun 23 07:35:04 PM PDT 24 |
| Peak memory | 574192 kb |
| Host | smart-57350d10-c170-40d1-9b9d-cac826c5abdf |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3721585231 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 55.xbar_stress_all _with_rand_reset.3721585231 |
| Directory | /workspace/55.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/55.xbar_stress_all_with_reset_error.682386771 |
| Short name | T1647 |
| Test name | |
| Test status | |
| Simulation time | 386822638 ps |
| CPU time | 76.83 seconds |
| Started | Jun 23 07:33:56 PM PDT 24 |
| Finished | Jun 23 07:35:13 PM PDT 24 |
| Peak memory | 575308 kb |
| Host | smart-a1001a55-d25b-45e5-9f66-6d75304b3efa |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=682386771 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 55.xbar_stress_all _with_reset_error.682386771 |
| Directory | /workspace/55.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/55.xbar_unmapped_addr.2300011153 |
| Short name | T2118 |
| Test name | |
| Test status | |
| Simulation time | 285282957 ps |
| CPU time | 31.84 seconds |
| Started | Jun 23 07:33:51 PM PDT 24 |
| Finished | Jun 23 07:34:23 PM PDT 24 |
| Peak memory | 574088 kb |
| Host | smart-7c3a508f-aed9-41f1-b9f2-f28946a6ad27 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2300011153 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 55.xbar_unmapped_addr.2300011153 |
| Directory | /workspace/55.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/56.xbar_access_same_device.574495842 |
| Short name | T883 |
| Test name | |
| Test status | |
| Simulation time | 3769266315 ps |
| CPU time | 150.26 seconds |
| Started | Jun 23 07:33:51 PM PDT 24 |
| Finished | Jun 23 07:36:22 PM PDT 24 |
| Peak memory | 574200 kb |
| Host | smart-53bfa3b9-b187-4a07-9617-8a84a5f195c8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=574495842 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 56.xbar_access_same_device. 574495842 |
| Directory | /workspace/56.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/56.xbar_access_same_device_slow_rsp.1849779113 |
| Short name | T1741 |
| Test name | |
| Test status | |
| Simulation time | 2703937121 ps |
| CPU time | 46.41 seconds |
| Started | Jun 23 07:33:54 PM PDT 24 |
| Finished | Jun 23 07:34:41 PM PDT 24 |
| Peak memory | 565952 kb |
| Host | smart-828efded-da1b-40d0-9a28-cb12f0d3df54 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1849779113 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 56.xbar_access_same_ device_slow_rsp.1849779113 |
| Directory | /workspace/56.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/56.xbar_error_and_unmapped_addr.1381977615 |
| Short name | T2294 |
| Test name | |
| Test status | |
| Simulation time | 151887340 ps |
| CPU time | 9.23 seconds |
| Started | Jun 23 07:33:51 PM PDT 24 |
| Finished | Jun 23 07:34:01 PM PDT 24 |
| Peak memory | 565160 kb |
| Host | smart-d5e12ec2-eaa4-4ecc-8d2f-6fe37755931b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1381977615 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 56.xbar_error_and_unmapped_add r.1381977615 |
| Directory | /workspace/56.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/56.xbar_error_random.2359120736 |
| Short name | T2102 |
| Test name | |
| Test status | |
| Simulation time | 127053186 ps |
| CPU time | 13.04 seconds |
| Started | Jun 23 07:33:56 PM PDT 24 |
| Finished | Jun 23 07:34:09 PM PDT 24 |
| Peak memory | 573720 kb |
| Host | smart-cfd45759-a36c-4716-a55e-e72478705932 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2359120736 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 56.xbar_error_random.2359120736 |
| Directory | /workspace/56.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/56.xbar_random.2848344752 |
| Short name | T2509 |
| Test name | |
| Test status | |
| Simulation time | 328972272 ps |
| CPU time | 14.57 seconds |
| Started | Jun 23 07:33:54 PM PDT 24 |
| Finished | Jun 23 07:34:09 PM PDT 24 |
| Peak memory | 574116 kb |
| Host | smart-01f994c0-c4fd-4fac-969e-f1d7b1636e74 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2848344752 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 56.xbar_random.2848344752 |
| Directory | /workspace/56.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/56.xbar_random_large_delays.3661951455 |
| Short name | T1635 |
| Test name | |
| Test status | |
| Simulation time | 57371487550 ps |
| CPU time | 550.53 seconds |
| Started | Jun 23 07:33:52 PM PDT 24 |
| Finished | Jun 23 07:43:03 PM PDT 24 |
| Peak memory | 574212 kb |
| Host | smart-170fd890-c123-4485-a180-b43ece4a3754 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3661951455 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 56.xbar_random_large_delays.3661951455 |
| Directory | /workspace/56.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/56.xbar_random_slow_rsp.1309926825 |
| Short name | T2346 |
| Test name | |
| Test status | |
| Simulation time | 15266214155 ps |
| CPU time | 264.73 seconds |
| Started | Jun 23 07:33:55 PM PDT 24 |
| Finished | Jun 23 07:38:20 PM PDT 24 |
| Peak memory | 573520 kb |
| Host | smart-dc9fd110-4e05-466f-80f0-ffca445010ca |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1309926825 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 56.xbar_random_slow_rsp.1309926825 |
| Directory | /workspace/56.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/56.xbar_random_zero_delays.3828554223 |
| Short name | T2315 |
| Test name | |
| Test status | |
| Simulation time | 233894416 ps |
| CPU time | 21.62 seconds |
| Started | Jun 23 07:33:49 PM PDT 24 |
| Finished | Jun 23 07:34:11 PM PDT 24 |
| Peak memory | 574112 kb |
| Host | smart-862872bc-c522-4e86-9297-01a2e0a8a657 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3828554223 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 56.xbar_random_zero_del ays.3828554223 |
| Directory | /workspace/56.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/56.xbar_same_source.2911699214 |
| Short name | T2493 |
| Test name | |
| Test status | |
| Simulation time | 125461588 ps |
| CPU time | 10.64 seconds |
| Started | Jun 23 07:33:56 PM PDT 24 |
| Finished | Jun 23 07:34:07 PM PDT 24 |
| Peak memory | 574224 kb |
| Host | smart-81a87389-d0a6-47b4-b222-ea23d2e50fa9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2911699214 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 56.xbar_same_source.2911699214 |
| Directory | /workspace/56.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/56.xbar_smoke.2690477409 |
| Short name | T1964 |
| Test name | |
| Test status | |
| Simulation time | 219013081 ps |
| CPU time | 8.98 seconds |
| Started | Jun 23 07:33:57 PM PDT 24 |
| Finished | Jun 23 07:34:06 PM PDT 24 |
| Peak memory | 565728 kb |
| Host | smart-a2bc8f77-8f64-48bd-8bac-02b58ce7f84f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2690477409 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 56.xbar_smoke.2690477409 |
| Directory | /workspace/56.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/56.xbar_smoke_large_delays.3938408885 |
| Short name | T2091 |
| Test name | |
| Test status | |
| Simulation time | 8277284146 ps |
| CPU time | 85.42 seconds |
| Started | Jun 23 07:33:57 PM PDT 24 |
| Finished | Jun 23 07:35:22 PM PDT 24 |
| Peak memory | 565552 kb |
| Host | smart-802bd74b-2e92-448b-9ef1-81379a640f69 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3938408885 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 56.xbar_smoke_large_delays.3938408885 |
| Directory | /workspace/56.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/56.xbar_smoke_slow_rsp.1609640760 |
| Short name | T2532 |
| Test name | |
| Test status | |
| Simulation time | 3131704494 ps |
| CPU time | 51.78 seconds |
| Started | Jun 23 07:33:57 PM PDT 24 |
| Finished | Jun 23 07:34:50 PM PDT 24 |
| Peak memory | 565688 kb |
| Host | smart-f9368754-07a5-4219-8f5d-292f21f6030f |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1609640760 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 56.xbar_smoke_slow_rsp.1609640760 |
| Directory | /workspace/56.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/56.xbar_smoke_zero_delays.287138477 |
| Short name | T1832 |
| Test name | |
| Test status | |
| Simulation time | 55484709 ps |
| CPU time | 6.69 seconds |
| Started | Jun 23 07:33:50 PM PDT 24 |
| Finished | Jun 23 07:33:57 PM PDT 24 |
| Peak memory | 565432 kb |
| Host | smart-6a1cc791-4da0-484d-8809-bd07cb60cd39 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=287138477 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 56.xbar_smoke_zero_delays .287138477 |
| Directory | /workspace/56.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/56.xbar_stress_all.1979901361 |
| Short name | T547 |
| Test name | |
| Test status | |
| Simulation time | 2781987693 ps |
| CPU time | 209.89 seconds |
| Started | Jun 23 07:33:58 PM PDT 24 |
| Finished | Jun 23 07:37:28 PM PDT 24 |
| Peak memory | 574376 kb |
| Host | smart-695387d3-26b4-43b7-b0ef-09dec3a06e86 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1979901361 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 56.xbar_stress_all.1979901361 |
| Directory | /workspace/56.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/56.xbar_stress_all_with_error.676259414 |
| Short name | T1799 |
| Test name | |
| Test status | |
| Simulation time | 2285770764 ps |
| CPU time | 187.89 seconds |
| Started | Jun 23 07:33:55 PM PDT 24 |
| Finished | Jun 23 07:37:03 PM PDT 24 |
| Peak memory | 574368 kb |
| Host | smart-7b7a2281-94cd-41c9-ad67-62addb725064 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=676259414 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 56.xbar_stress_all_with_error.676259414 |
| Directory | /workspace/56.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/56.xbar_stress_all_with_rand_reset.182992081 |
| Short name | T2846 |
| Test name | |
| Test status | |
| Simulation time | 4129121020 ps |
| CPU time | 480.96 seconds |
| Started | Jun 23 07:33:54 PM PDT 24 |
| Finished | Jun 23 07:41:55 PM PDT 24 |
| Peak memory | 574316 kb |
| Host | smart-f731efaa-10a1-41b1-a8f6-abaa2465ad85 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=182992081 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_res et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 56.xbar_stress_all_ with_rand_reset.182992081 |
| Directory | /workspace/56.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/56.xbar_stress_all_with_reset_error.1677595151 |
| Short name | T1795 |
| Test name | |
| Test status | |
| Simulation time | 258401241 ps |
| CPU time | 54.41 seconds |
| Started | Jun 23 07:33:54 PM PDT 24 |
| Finished | Jun 23 07:34:49 PM PDT 24 |
| Peak memory | 574296 kb |
| Host | smart-c5842657-080c-496b-962c-30a8911c050d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1677595151 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 56.xbar_stress_al l_with_reset_error.1677595151 |
| Directory | /workspace/56.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/56.xbar_unmapped_addr.2567346057 |
| Short name | T1473 |
| Test name | |
| Test status | |
| Simulation time | 83888835 ps |
| CPU time | 6.74 seconds |
| Started | Jun 23 07:33:53 PM PDT 24 |
| Finished | Jun 23 07:34:00 PM PDT 24 |
| Peak memory | 565248 kb |
| Host | smart-1bb95a50-591f-4e78-9264-710a6059136a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2567346057 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 56.xbar_unmapped_addr.2567346057 |
| Directory | /workspace/56.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/57.xbar_access_same_device.1891944573 |
| Short name | T1527 |
| Test name | |
| Test status | |
| Simulation time | 1105905784 ps |
| CPU time | 44.79 seconds |
| Started | Jun 23 07:34:08 PM PDT 24 |
| Finished | Jun 23 07:34:54 PM PDT 24 |
| Peak memory | 573400 kb |
| Host | smart-ebd5724d-0e52-46f6-9520-bcff954ca192 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1891944573 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 57.xbar_access_same_device .1891944573 |
| Directory | /workspace/57.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/57.xbar_access_same_device_slow_rsp.3145089111 |
| Short name | T864 |
| Test name | |
| Test status | |
| Simulation time | 50135443768 ps |
| CPU time | 956.99 seconds |
| Started | Jun 23 07:34:08 PM PDT 24 |
| Finished | Jun 23 07:50:05 PM PDT 24 |
| Peak memory | 574264 kb |
| Host | smart-6e9fe36a-2ad5-40a1-89d1-ac4b5e73a8de |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3145089111 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 57.xbar_access_same_ device_slow_rsp.3145089111 |
| Directory | /workspace/57.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/57.xbar_error_and_unmapped_addr.1044227549 |
| Short name | T2572 |
| Test name | |
| Test status | |
| Simulation time | 1468190585 ps |
| CPU time | 52.62 seconds |
| Started | Jun 23 07:34:16 PM PDT 24 |
| Finished | Jun 23 07:35:09 PM PDT 24 |
| Peak memory | 573332 kb |
| Host | smart-0aa5f998-f1c3-4f52-bfd2-4b0a4859facb |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1044227549 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 57.xbar_error_and_unmapped_add r.1044227549 |
| Directory | /workspace/57.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/57.xbar_error_random.749118401 |
| Short name | T2083 |
| Test name | |
| Test status | |
| Simulation time | 1114560343 ps |
| CPU time | 40.96 seconds |
| Started | Jun 23 07:34:08 PM PDT 24 |
| Finished | Jun 23 07:34:49 PM PDT 24 |
| Peak memory | 573284 kb |
| Host | smart-713ad245-6886-433c-afa3-609ab2927b4f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=749118401 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 57.xbar_error_random.749118401 |
| Directory | /workspace/57.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/57.xbar_random.2332707974 |
| Short name | T1819 |
| Test name | |
| Test status | |
| Simulation time | 1387095008 ps |
| CPU time | 52.34 seconds |
| Started | Jun 23 07:34:09 PM PDT 24 |
| Finished | Jun 23 07:35:01 PM PDT 24 |
| Peak memory | 574088 kb |
| Host | smart-9d67268f-bd05-43eb-a7e2-5782aab044a6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2332707974 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 57.xbar_random.2332707974 |
| Directory | /workspace/57.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/57.xbar_random_large_delays.1765409691 |
| Short name | T679 |
| Test name | |
| Test status | |
| Simulation time | 35051301471 ps |
| CPU time | 347.63 seconds |
| Started | Jun 23 07:34:07 PM PDT 24 |
| Finished | Jun 23 07:39:55 PM PDT 24 |
| Peak memory | 574200 kb |
| Host | smart-81da502c-f47e-455e-b6c1-933be30c28ae |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1765409691 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 57.xbar_random_large_delays.1765409691 |
| Directory | /workspace/57.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/57.xbar_random_slow_rsp.721974808 |
| Short name | T2678 |
| Test name | |
| Test status | |
| Simulation time | 29855200906 ps |
| CPU time | 488.76 seconds |
| Started | Jun 23 07:34:08 PM PDT 24 |
| Finished | Jun 23 07:42:17 PM PDT 24 |
| Peak memory | 574188 kb |
| Host | smart-6836d414-8fe5-4eaa-8fec-981f4354301b |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=721974808 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 57.xbar_random_slow_rsp.721974808 |
| Directory | /workspace/57.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/57.xbar_random_zero_delays.2612327803 |
| Short name | T2345 |
| Test name | |
| Test status | |
| Simulation time | 260499312 ps |
| CPU time | 22.64 seconds |
| Started | Jun 23 07:34:08 PM PDT 24 |
| Finished | Jun 23 07:34:31 PM PDT 24 |
| Peak memory | 573320 kb |
| Host | smart-8fb9d3cc-0a3d-490e-b145-e43211cb0bef |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2612327803 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 57.xbar_random_zero_del ays.2612327803 |
| Directory | /workspace/57.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/57.xbar_same_source.339067919 |
| Short name | T1904 |
| Test name | |
| Test status | |
| Simulation time | 1504832761 ps |
| CPU time | 46.51 seconds |
| Started | Jun 23 07:34:09 PM PDT 24 |
| Finished | Jun 23 07:34:56 PM PDT 24 |
| Peak memory | 573716 kb |
| Host | smart-bd9dce42-5c03-4645-854b-14369031eef9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=339067919 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 57.xbar_same_source.339067919 |
| Directory | /workspace/57.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/57.xbar_smoke.3892527251 |
| Short name | T1679 |
| Test name | |
| Test status | |
| Simulation time | 229718085 ps |
| CPU time | 10.14 seconds |
| Started | Jun 23 07:33:56 PM PDT 24 |
| Finished | Jun 23 07:34:07 PM PDT 24 |
| Peak memory | 565128 kb |
| Host | smart-3c15facf-cfe5-4ba8-af31-6b49688d2556 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3892527251 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 57.xbar_smoke.3892527251 |
| Directory | /workspace/57.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/57.xbar_smoke_large_delays.42144315 |
| Short name | T2723 |
| Test name | |
| Test status | |
| Simulation time | 10060353020 ps |
| CPU time | 104.34 seconds |
| Started | Jun 23 07:34:11 PM PDT 24 |
| Finished | Jun 23 07:35:55 PM PDT 24 |
| Peak memory | 565912 kb |
| Host | smart-b7a17233-d9d2-4966-81e0-40fef398c272 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42144315 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 57.xbar_smoke_large_delays.42144315 |
| Directory | /workspace/57.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/57.xbar_smoke_slow_rsp.3683732746 |
| Short name | T1561 |
| Test name | |
| Test status | |
| Simulation time | 3696821267 ps |
| CPU time | 61.48 seconds |
| Started | Jun 23 07:34:07 PM PDT 24 |
| Finished | Jun 23 07:35:09 PM PDT 24 |
| Peak memory | 565564 kb |
| Host | smart-edca0881-58ad-420f-b1d7-f0d13c9227c0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3683732746 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 57.xbar_smoke_slow_rsp.3683732746 |
| Directory | /workspace/57.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/57.xbar_smoke_zero_delays.1636942122 |
| Short name | T2135 |
| Test name | |
| Test status | |
| Simulation time | 42101332 ps |
| CPU time | 6.39 seconds |
| Started | Jun 23 07:33:56 PM PDT 24 |
| Finished | Jun 23 07:34:03 PM PDT 24 |
| Peak memory | 565472 kb |
| Host | smart-4acbb772-fcdf-4c34-a66a-c0e5fe5fe517 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1636942122 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 57.xbar_smoke_zero_delay s.1636942122 |
| Directory | /workspace/57.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/57.xbar_stress_all.744217422 |
| Short name | T2202 |
| Test name | |
| Test status | |
| Simulation time | 11539212058 ps |
| CPU time | 425.43 seconds |
| Started | Jun 23 07:34:15 PM PDT 24 |
| Finished | Jun 23 07:41:20 PM PDT 24 |
| Peak memory | 574184 kb |
| Host | smart-f0cc6ec0-9b92-4e4e-94ff-0605009204f0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=744217422 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 57.xbar_stress_all.744217422 |
| Directory | /workspace/57.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/57.xbar_stress_all_with_error.820039991 |
| Short name | T2358 |
| Test name | |
| Test status | |
| Simulation time | 3091207494 ps |
| CPU time | 210.95 seconds |
| Started | Jun 23 07:34:16 PM PDT 24 |
| Finished | Jun 23 07:37:47 PM PDT 24 |
| Peak memory | 573856 kb |
| Host | smart-29a39159-bd94-4eeb-af92-5546b8a1728c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=820039991 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 57.xbar_stress_all_with_error.820039991 |
| Directory | /workspace/57.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/57.xbar_stress_all_with_rand_reset.3528641922 |
| Short name | T2809 |
| Test name | |
| Test status | |
| Simulation time | 18472145314 ps |
| CPU time | 988.07 seconds |
| Started | Jun 23 07:34:13 PM PDT 24 |
| Finished | Jun 23 07:50:42 PM PDT 24 |
| Peak memory | 575312 kb |
| Host | smart-58246cd4-2a95-4fb0-a6b7-d7b3c54fb975 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3528641922 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 57.xbar_stress_all _with_rand_reset.3528641922 |
| Directory | /workspace/57.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/57.xbar_stress_all_with_reset_error.690270110 |
| Short name | T1615 |
| Test name | |
| Test status | |
| Simulation time | 393019134 ps |
| CPU time | 152.38 seconds |
| Started | Jun 23 07:34:12 PM PDT 24 |
| Finished | Jun 23 07:36:44 PM PDT 24 |
| Peak memory | 574336 kb |
| Host | smart-ba44e53d-66a6-49b5-a119-d2141ebe6c0a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=690270110 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 57.xbar_stress_all _with_reset_error.690270110 |
| Directory | /workspace/57.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/57.xbar_unmapped_addr.2536481742 |
| Short name | T2110 |
| Test name | |
| Test status | |
| Simulation time | 1047010683 ps |
| CPU time | 45.36 seconds |
| Started | Jun 23 07:34:14 PM PDT 24 |
| Finished | Jun 23 07:34:59 PM PDT 24 |
| Peak memory | 574096 kb |
| Host | smart-406657f3-bcc5-4dd8-b8f1-da4e17cb870f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2536481742 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 57.xbar_unmapped_addr.2536481742 |
| Directory | /workspace/57.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/58.xbar_access_same_device.509071338 |
| Short name | T2528 |
| Test name | |
| Test status | |
| Simulation time | 104201769 ps |
| CPU time | 7.88 seconds |
| Started | Jun 23 07:34:17 PM PDT 24 |
| Finished | Jun 23 07:34:25 PM PDT 24 |
| Peak memory | 565200 kb |
| Host | smart-06b9eb20-f85f-40cc-a2fb-4fb9c7584daa |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=509071338 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 58.xbar_access_same_device. 509071338 |
| Directory | /workspace/58.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/58.xbar_access_same_device_slow_rsp.665758770 |
| Short name | T2374 |
| Test name | |
| Test status | |
| Simulation time | 142756917037 ps |
| CPU time | 2600.82 seconds |
| Started | Jun 23 07:34:15 PM PDT 24 |
| Finished | Jun 23 08:17:36 PM PDT 24 |
| Peak memory | 574300 kb |
| Host | smart-fcf23bd4-f80b-4cdb-a386-99e62479a7bd |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=665758770 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 58.xbar_access_same_d evice_slow_rsp.665758770 |
| Directory | /workspace/58.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/58.xbar_error_and_unmapped_addr.3194864517 |
| Short name | T2019 |
| Test name | |
| Test status | |
| Simulation time | 362381307 ps |
| CPU time | 17.03 seconds |
| Started | Jun 23 07:34:10 PM PDT 24 |
| Finished | Jun 23 07:34:28 PM PDT 24 |
| Peak memory | 573616 kb |
| Host | smart-0c273cd6-fc7b-4fe0-ad9f-9ecaaeb1d77b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3194864517 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 58.xbar_error_and_unmapped_add r.3194864517 |
| Directory | /workspace/58.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/58.xbar_error_random.223581542 |
| Short name | T1737 |
| Test name | |
| Test status | |
| Simulation time | 997199770 ps |
| CPU time | 30.97 seconds |
| Started | Jun 23 07:34:18 PM PDT 24 |
| Finished | Jun 23 07:34:49 PM PDT 24 |
| Peak memory | 573728 kb |
| Host | smart-683ea9f0-e63e-4c53-af5f-9c2e0275c291 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=223581542 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 58.xbar_error_random.223581542 |
| Directory | /workspace/58.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/58.xbar_random.939985388 |
| Short name | T474 |
| Test name | |
| Test status | |
| Simulation time | 484644426 ps |
| CPU time | 40.47 seconds |
| Started | Jun 23 07:34:20 PM PDT 24 |
| Finished | Jun 23 07:35:01 PM PDT 24 |
| Peak memory | 573356 kb |
| Host | smart-21c17796-bd4c-41b5-b016-05bb894f4925 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=939985388 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 58.xbar_random.939985388 |
| Directory | /workspace/58.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/58.xbar_random_large_delays.338055740 |
| Short name | T2084 |
| Test name | |
| Test status | |
| Simulation time | 107396459198 ps |
| CPU time | 1191.52 seconds |
| Started | Jun 23 07:34:18 PM PDT 24 |
| Finished | Jun 23 07:54:10 PM PDT 24 |
| Peak memory | 574224 kb |
| Host | smart-9f64a437-3df4-47a9-9f67-c0caf48ef031 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=338055740 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 58.xbar_random_large_delays.338055740 |
| Directory | /workspace/58.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/58.xbar_random_slow_rsp.1804178233 |
| Short name | T555 |
| Test name | |
| Test status | |
| Simulation time | 58440717573 ps |
| CPU time | 942.07 seconds |
| Started | Jun 23 07:34:15 PM PDT 24 |
| Finished | Jun 23 07:49:58 PM PDT 24 |
| Peak memory | 574196 kb |
| Host | smart-bfcb7be3-b8e2-4cdc-b06e-94b7b3e6f0b6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1804178233 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 58.xbar_random_slow_rsp.1804178233 |
| Directory | /workspace/58.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/58.xbar_random_zero_delays.770593425 |
| Short name | T570 |
| Test name | |
| Test status | |
| Simulation time | 610439002 ps |
| CPU time | 53.35 seconds |
| Started | Jun 23 07:34:11 PM PDT 24 |
| Finished | Jun 23 07:35:05 PM PDT 24 |
| Peak memory | 574084 kb |
| Host | smart-a4515c11-1c9f-4ef2-9dd0-c4e7f46ba501 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=770593425 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 58.xbar_random_zero_dela ys.770593425 |
| Directory | /workspace/58.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/58.xbar_same_source.3183478704 |
| Short name | T602 |
| Test name | |
| Test status | |
| Simulation time | 498550600 ps |
| CPU time | 39.98 seconds |
| Started | Jun 23 07:34:19 PM PDT 24 |
| Finished | Jun 23 07:34:59 PM PDT 24 |
| Peak memory | 574048 kb |
| Host | smart-0e9b5036-ef91-4aef-abb0-81e86f1394c4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3183478704 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 58.xbar_same_source.3183478704 |
| Directory | /workspace/58.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/58.xbar_smoke.1487563823 |
| Short name | T1590 |
| Test name | |
| Test status | |
| Simulation time | 213299628 ps |
| CPU time | 9.38 seconds |
| Started | Jun 23 07:34:15 PM PDT 24 |
| Finished | Jun 23 07:34:25 PM PDT 24 |
| Peak memory | 565852 kb |
| Host | smart-c4e5e4b4-1152-4361-9937-03f3fbe594e5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1487563823 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 58.xbar_smoke.1487563823 |
| Directory | /workspace/58.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/58.xbar_smoke_large_delays.1463505681 |
| Short name | T1506 |
| Test name | |
| Test status | |
| Simulation time | 8435287684 ps |
| CPU time | 88.19 seconds |
| Started | Jun 23 07:34:13 PM PDT 24 |
| Finished | Jun 23 07:35:41 PM PDT 24 |
| Peak memory | 565908 kb |
| Host | smart-f4691d80-fb66-498d-9021-afad12167de4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1463505681 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 58.xbar_smoke_large_delays.1463505681 |
| Directory | /workspace/58.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/58.xbar_smoke_slow_rsp.3210107409 |
| Short name | T2275 |
| Test name | |
| Test status | |
| Simulation time | 6856490170 ps |
| CPU time | 116.2 seconds |
| Started | Jun 23 07:34:14 PM PDT 24 |
| Finished | Jun 23 07:36:10 PM PDT 24 |
| Peak memory | 565936 kb |
| Host | smart-235a64e7-f079-4a69-8c3e-50906e2c0284 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3210107409 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 58.xbar_smoke_slow_rsp.3210107409 |
| Directory | /workspace/58.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/58.xbar_smoke_zero_delays.1023423280 |
| Short name | T1407 |
| Test name | |
| Test status | |
| Simulation time | 39694505 ps |
| CPU time | 5.5 seconds |
| Started | Jun 23 07:34:18 PM PDT 24 |
| Finished | Jun 23 07:34:24 PM PDT 24 |
| Peak memory | 565172 kb |
| Host | smart-61e7dcf1-0fd1-4ee7-8cd3-781c3e3187b7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1023423280 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 58.xbar_smoke_zero_delay s.1023423280 |
| Directory | /workspace/58.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/58.xbar_stress_all.4195942344 |
| Short name | T2196 |
| Test name | |
| Test status | |
| Simulation time | 2905872643 ps |
| CPU time | 98.55 seconds |
| Started | Jun 23 07:34:20 PM PDT 24 |
| Finished | Jun 23 07:35:58 PM PDT 24 |
| Peak memory | 573996 kb |
| Host | smart-569a4324-8122-4557-9992-92f1bb3758e1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4195942344 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 58.xbar_stress_all.4195942344 |
| Directory | /workspace/58.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/58.xbar_stress_all_with_error.3445021390 |
| Short name | T1988 |
| Test name | |
| Test status | |
| Simulation time | 7336098313 ps |
| CPU time | 230.55 seconds |
| Started | Jun 23 07:34:15 PM PDT 24 |
| Finished | Jun 23 07:38:06 PM PDT 24 |
| Peak memory | 573560 kb |
| Host | smart-b342edc0-5406-4623-8efe-ae7703dc0ec9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3445021390 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 58.xbar_stress_all_with_error.3445021390 |
| Directory | /workspace/58.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/58.xbar_stress_all_with_rand_reset.2950948123 |
| Short name | T1731 |
| Test name | |
| Test status | |
| Simulation time | 46055064 ps |
| CPU time | 16.05 seconds |
| Started | Jun 23 07:34:13 PM PDT 24 |
| Finished | Jun 23 07:34:29 PM PDT 24 |
| Peak memory | 574200 kb |
| Host | smart-13a87a5b-9f6a-44bc-b7f2-7c89bcfe46f4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2950948123 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 58.xbar_stress_all _with_rand_reset.2950948123 |
| Directory | /workspace/58.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/58.xbar_stress_all_with_reset_error.1102641223 |
| Short name | T882 |
| Test name | |
| Test status | |
| Simulation time | 11475196927 ps |
| CPU time | 537.2 seconds |
| Started | Jun 23 07:35:18 PM PDT 24 |
| Finished | Jun 23 07:44:16 PM PDT 24 |
| Peak memory | 576412 kb |
| Host | smart-f9c451c6-bea7-45ae-bcaa-8fdfba4ca517 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1102641223 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 58.xbar_stress_al l_with_reset_error.1102641223 |
| Directory | /workspace/58.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/58.xbar_unmapped_addr.3165522840 |
| Short name | T2018 |
| Test name | |
| Test status | |
| Simulation time | 268766651 ps |
| CPU time | 36.22 seconds |
| Started | Jun 23 07:34:19 PM PDT 24 |
| Finished | Jun 23 07:34:56 PM PDT 24 |
| Peak memory | 574108 kb |
| Host | smart-30464e84-59af-4238-82d4-76a8a367fe02 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3165522840 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 58.xbar_unmapped_addr.3165522840 |
| Directory | /workspace/58.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/59.xbar_access_same_device.2939518286 |
| Short name | T2153 |
| Test name | |
| Test status | |
| Simulation time | 1728681789 ps |
| CPU time | 73.08 seconds |
| Started | Jun 23 07:34:20 PM PDT 24 |
| Finished | Jun 23 07:35:33 PM PDT 24 |
| Peak memory | 574092 kb |
| Host | smart-9e4e91c8-92b9-4d6c-904b-0985211137e4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2939518286 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 59.xbar_access_same_device .2939518286 |
| Directory | /workspace/59.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/59.xbar_access_same_device_slow_rsp.795391460 |
| Short name | T2850 |
| Test name | |
| Test status | |
| Simulation time | 122382734133 ps |
| CPU time | 2200.11 seconds |
| Started | Jun 23 07:34:20 PM PDT 24 |
| Finished | Jun 23 08:11:01 PM PDT 24 |
| Peak memory | 573432 kb |
| Host | smart-187f8e32-1ae0-4754-bee4-8ceffc27b554 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=795391460 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 59.xbar_access_same_d evice_slow_rsp.795391460 |
| Directory | /workspace/59.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/59.xbar_error_and_unmapped_addr.2027939052 |
| Short name | T2583 |
| Test name | |
| Test status | |
| Simulation time | 905885578 ps |
| CPU time | 34.52 seconds |
| Started | Jun 23 07:34:26 PM PDT 24 |
| Finished | Jun 23 07:35:01 PM PDT 24 |
| Peak memory | 573744 kb |
| Host | smart-4b7c6a45-a7ae-4d5c-893d-56648c19fddd |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2027939052 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 59.xbar_error_and_unmapped_add r.2027939052 |
| Directory | /workspace/59.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/59.xbar_error_random.2699271578 |
| Short name | T2683 |
| Test name | |
| Test status | |
| Simulation time | 2091698324 ps |
| CPU time | 78.54 seconds |
| Started | Jun 23 07:34:24 PM PDT 24 |
| Finished | Jun 23 07:35:43 PM PDT 24 |
| Peak memory | 573700 kb |
| Host | smart-99057a66-5dc6-4b95-b974-15f601dbb110 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2699271578 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 59.xbar_error_random.2699271578 |
| Directory | /workspace/59.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/59.xbar_random.3624082386 |
| Short name | T2769 |
| Test name | |
| Test status | |
| Simulation time | 1538704819 ps |
| CPU time | 55.45 seconds |
| Started | Jun 23 07:34:23 PM PDT 24 |
| Finished | Jun 23 07:35:19 PM PDT 24 |
| Peak memory | 574100 kb |
| Host | smart-f6c20193-dd99-4890-b81b-a1e34eba1cf5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3624082386 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 59.xbar_random.3624082386 |
| Directory | /workspace/59.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/59.xbar_random_large_delays.3036612014 |
| Short name | T2271 |
| Test name | |
| Test status | |
| Simulation time | 83407263788 ps |
| CPU time | 885.32 seconds |
| Started | Jun 23 07:34:21 PM PDT 24 |
| Finished | Jun 23 07:49:07 PM PDT 24 |
| Peak memory | 573456 kb |
| Host | smart-3212d65a-b19d-4d44-a865-65dd89ce59cb |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3036612014 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 59.xbar_random_large_delays.3036612014 |
| Directory | /workspace/59.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/59.xbar_random_slow_rsp.3402305861 |
| Short name | T2258 |
| Test name | |
| Test status | |
| Simulation time | 70560299383 ps |
| CPU time | 1229.13 seconds |
| Started | Jun 23 07:34:23 PM PDT 24 |
| Finished | Jun 23 07:54:53 PM PDT 24 |
| Peak memory | 573544 kb |
| Host | smart-2d701808-c501-4c91-9551-e5e4c3db4cbe |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3402305861 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 59.xbar_random_slow_rsp.3402305861 |
| Directory | /workspace/59.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/59.xbar_random_zero_delays.3133357194 |
| Short name | T2303 |
| Test name | |
| Test status | |
| Simulation time | 311515941 ps |
| CPU time | 28.92 seconds |
| Started | Jun 23 07:34:23 PM PDT 24 |
| Finished | Jun 23 07:34:52 PM PDT 24 |
| Peak memory | 574072 kb |
| Host | smart-27d12986-fcf3-4798-af32-899928b15249 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3133357194 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 59.xbar_random_zero_del ays.3133357194 |
| Directory | /workspace/59.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/59.xbar_same_source.3079616027 |
| Short name | T1698 |
| Test name | |
| Test status | |
| Simulation time | 1385342704 ps |
| CPU time | 42.92 seconds |
| Started | Jun 23 07:34:21 PM PDT 24 |
| Finished | Jun 23 07:35:04 PM PDT 24 |
| Peak memory | 573704 kb |
| Host | smart-86a847cb-235a-43e9-97b4-dde87561034d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3079616027 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 59.xbar_same_source.3079616027 |
| Directory | /workspace/59.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/59.xbar_smoke.3304377836 |
| Short name | T2495 |
| Test name | |
| Test status | |
| Simulation time | 205601485 ps |
| CPU time | 8.55 seconds |
| Started | Jun 23 07:34:20 PM PDT 24 |
| Finished | Jun 23 07:34:29 PM PDT 24 |
| Peak memory | 565452 kb |
| Host | smart-f4ad41d1-b4d8-46e9-98e4-62f56de0c3c0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3304377836 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 59.xbar_smoke.3304377836 |
| Directory | /workspace/59.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/59.xbar_smoke_large_delays.2405437323 |
| Short name | T2099 |
| Test name | |
| Test status | |
| Simulation time | 7542826306 ps |
| CPU time | 77.97 seconds |
| Started | Jun 23 07:34:20 PM PDT 24 |
| Finished | Jun 23 07:35:39 PM PDT 24 |
| Peak memory | 565476 kb |
| Host | smart-ac5e31b8-3ba3-415a-9d06-7d6bd12babfe |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2405437323 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 59.xbar_smoke_large_delays.2405437323 |
| Directory | /workspace/59.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/59.xbar_smoke_slow_rsp.338229548 |
| Short name | T2071 |
| Test name | |
| Test status | |
| Simulation time | 4886265279 ps |
| CPU time | 82.01 seconds |
| Started | Jun 23 07:34:15 PM PDT 24 |
| Finished | Jun 23 07:35:37 PM PDT 24 |
| Peak memory | 565928 kb |
| Host | smart-3587f777-a2da-4bc9-b1e0-a3cb464b67c7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=338229548 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 59.xbar_smoke_slow_rsp.338229548 |
| Directory | /workspace/59.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/59.xbar_smoke_zero_delays.1420446837 |
| Short name | T2724 |
| Test name | |
| Test status | |
| Simulation time | 40424203 ps |
| CPU time | 6.34 seconds |
| Started | Jun 23 07:34:16 PM PDT 24 |
| Finished | Jun 23 07:34:22 PM PDT 24 |
| Peak memory | 565624 kb |
| Host | smart-e16306de-9fd1-4b7f-9c6c-b6daae2ef175 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1420446837 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 59.xbar_smoke_zero_delay s.1420446837 |
| Directory | /workspace/59.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/59.xbar_stress_all.1395473135 |
| Short name | T2284 |
| Test name | |
| Test status | |
| Simulation time | 2784665450 ps |
| CPU time | 230.39 seconds |
| Started | Jun 23 07:34:27 PM PDT 24 |
| Finished | Jun 23 07:38:17 PM PDT 24 |
| Peak memory | 574316 kb |
| Host | smart-19a6dc99-c2f6-4226-b54c-0a9a181ecc51 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1395473135 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 59.xbar_stress_all.1395473135 |
| Directory | /workspace/59.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/59.xbar_stress_all_with_error.1283107774 |
| Short name | T1860 |
| Test name | |
| Test status | |
| Simulation time | 12447555342 ps |
| CPU time | 448.65 seconds |
| Started | Jun 23 07:34:26 PM PDT 24 |
| Finished | Jun 23 07:41:55 PM PDT 24 |
| Peak memory | 574452 kb |
| Host | smart-a677847e-1b91-43c2-ae0e-a453bf25af7e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1283107774 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 59.xbar_stress_all_with_error.1283107774 |
| Directory | /workspace/59.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/59.xbar_stress_all_with_rand_reset.1573435543 |
| Short name | T2450 |
| Test name | |
| Test status | |
| Simulation time | 4125849076 ps |
| CPU time | 524.38 seconds |
| Started | Jun 23 07:34:26 PM PDT 24 |
| Finished | Jun 23 07:43:10 PM PDT 24 |
| Peak memory | 574268 kb |
| Host | smart-406e720b-88eb-4dc6-b4d8-312ef98fc303 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1573435543 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 59.xbar_stress_all _with_rand_reset.1573435543 |
| Directory | /workspace/59.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/59.xbar_stress_all_with_reset_error.210197682 |
| Short name | T2417 |
| Test name | |
| Test status | |
| Simulation time | 2153056761 ps |
| CPU time | 155.35 seconds |
| Started | Jun 23 07:34:31 PM PDT 24 |
| Finished | Jun 23 07:37:06 PM PDT 24 |
| Peak memory | 576328 kb |
| Host | smart-0902eba5-9868-4a2b-94d7-d879f5986520 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=210197682 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 59.xbar_stress_all _with_reset_error.210197682 |
| Directory | /workspace/59.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/59.xbar_unmapped_addr.652791210 |
| Short name | T2331 |
| Test name | |
| Test status | |
| Simulation time | 275040175 ps |
| CPU time | 29.63 seconds |
| Started | Jun 23 07:34:25 PM PDT 24 |
| Finished | Jun 23 07:34:55 PM PDT 24 |
| Peak memory | 574128 kb |
| Host | smart-be95d2ab-5bcd-4adb-967a-4cf704d6d38b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=652791210 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 59.xbar_unmapped_addr.652791210 |
| Directory | /workspace/59.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/6.chip_csr_rw.2368937379 |
| Short name | T2237 |
| Test name | |
| Test status | |
| Simulation time | 5001778585 ps |
| CPU time | 297 seconds |
| Started | Jun 23 07:22:05 PM PDT 24 |
| Finished | Jun 23 07:27:02 PM PDT 24 |
| Peak memory | 594152 kb |
| Host | smart-9cdbb8fc-eef1-4d3d-bfa7-6862436f1caa |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2368937379 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.chip_csr_rw.2368937379 |
| Directory | /workspace/6.chip_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/6.chip_same_csr_outstanding.3816107842 |
| Short name | T2414 |
| Test name | |
| Test status | |
| Simulation time | 30672806443 ps |
| CPU time | 4008.3 seconds |
| Started | Jun 23 07:21:33 PM PDT 24 |
| Finished | Jun 23 08:28:22 PM PDT 24 |
| Peak memory | 590876 kb |
| Host | smart-ce7d51e6-7b2d-4b26-ad98-f7044d187c1e |
| User | root |
| Command | /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +run_same_csr_outstanding +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3816107842 -assert nopostproc +UVM_TE STNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb - cm_log /dev/null -cm_name 6.chip_same_csr_outstanding.3816107842 |
| Directory | /workspace/6.chip_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/6.chip_tl_errors.243098891 |
| Short name | T699 |
| Test name | |
| Test status | |
| Simulation time | 3743962224 ps |
| CPU time | 223.01 seconds |
| Started | Jun 23 07:21:35 PM PDT 24 |
| Finished | Jun 23 07:25:19 PM PDT 24 |
| Peak memory | 597472 kb |
| Host | smart-a9013046-2c73-4cde-977f-5f685f8d3051 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=243098891 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.chip_tl_errors.243098891 |
| Directory | /workspace/6.chip_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/6.xbar_access_same_device.985470759 |
| Short name | T2446 |
| Test name | |
| Test status | |
| Simulation time | 488622415 ps |
| CPU time | 37.85 seconds |
| Started | Jun 23 07:21:36 PM PDT 24 |
| Finished | Jun 23 07:22:14 PM PDT 24 |
| Peak memory | 574096 kb |
| Host | smart-b1d644a1-4e83-4083-9d18-f1971a17c284 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=985470759 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.xbar_access_same_device.985470759 |
| Directory | /workspace/6.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/6.xbar_access_same_device_slow_rsp.2648864731 |
| Short name | T2815 |
| Test name | |
| Test status | |
| Simulation time | 41872054827 ps |
| CPU time | 676.33 seconds |
| Started | Jun 23 07:21:41 PM PDT 24 |
| Finished | Jun 23 07:32:58 PM PDT 24 |
| Peak memory | 573464 kb |
| Host | smart-79571f66-f685-4efb-b634-ddd7a2b6e2c2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2648864731 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.xbar_access_same_d evice_slow_rsp.2648864731 |
| Directory | /workspace/6.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/6.xbar_error_and_unmapped_addr.3070179137 |
| Short name | T2852 |
| Test name | |
| Test status | |
| Simulation time | 813056226 ps |
| CPU time | 35.52 seconds |
| Started | Jun 23 07:21:51 PM PDT 24 |
| Finished | Jun 23 07:22:27 PM PDT 24 |
| Peak memory | 573392 kb |
| Host | smart-43ba8235-a0a4-48b1-b31d-faab68c1395e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3070179137 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.xbar_error_and_unmapped_addr .3070179137 |
| Directory | /workspace/6.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/6.xbar_error_random.3727036337 |
| Short name | T1376 |
| Test name | |
| Test status | |
| Simulation time | 1537830670 ps |
| CPU time | 53.36 seconds |
| Started | Jun 23 07:21:42 PM PDT 24 |
| Finished | Jun 23 07:22:35 PM PDT 24 |
| Peak memory | 573748 kb |
| Host | smart-060c2fc0-793a-414a-872a-6b46baf0bf71 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3727036337 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.xbar_error_random.3727036337 |
| Directory | /workspace/6.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/6.xbar_random.4232812782 |
| Short name | T2637 |
| Test name | |
| Test status | |
| Simulation time | 93664735 ps |
| CPU time | 10.87 seconds |
| Started | Jun 23 07:21:37 PM PDT 24 |
| Finished | Jun 23 07:21:48 PM PDT 24 |
| Peak memory | 574008 kb |
| Host | smart-abf338bd-e8a9-411e-b071-de8ce12a02b0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4232812782 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.xbar_random.4232812782 |
| Directory | /workspace/6.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/6.xbar_random_large_delays.3841705185 |
| Short name | T2154 |
| Test name | |
| Test status | |
| Simulation time | 24863310313 ps |
| CPU time | 269.63 seconds |
| Started | Jun 23 07:21:37 PM PDT 24 |
| Finished | Jun 23 07:26:07 PM PDT 24 |
| Peak memory | 574216 kb |
| Host | smart-c90b4e18-a9a8-48eb-86f5-37b39e231367 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3841705185 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.xbar_random_large_delays.3841705185 |
| Directory | /workspace/6.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/6.xbar_random_slow_rsp.4027484070 |
| Short name | T575 |
| Test name | |
| Test status | |
| Simulation time | 25536412886 ps |
| CPU time | 425.9 seconds |
| Started | Jun 23 07:21:38 PM PDT 24 |
| Finished | Jun 23 07:28:44 PM PDT 24 |
| Peak memory | 573480 kb |
| Host | smart-ae8cc4ed-7f33-4f12-bb94-7f0139d083b5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4027484070 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.xbar_random_slow_rsp.4027484070 |
| Directory | /workspace/6.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/6.xbar_random_zero_delays.4074164508 |
| Short name | T1826 |
| Test name | |
| Test status | |
| Simulation time | 183128904 ps |
| CPU time | 18.49 seconds |
| Started | Jun 23 07:21:37 PM PDT 24 |
| Finished | Jun 23 07:21:55 PM PDT 24 |
| Peak memory | 573964 kb |
| Host | smart-b6c3e48f-de3d-486c-a543-655c1fa56b4d |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4074164508 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.xbar_random_zero_dela ys.4074164508 |
| Directory | /workspace/6.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/6.xbar_same_source.749156716 |
| Short name | T1657 |
| Test name | |
| Test status | |
| Simulation time | 163344802 ps |
| CPU time | 7.52 seconds |
| Started | Jun 23 07:21:43 PM PDT 24 |
| Finished | Jun 23 07:21:51 PM PDT 24 |
| Peak memory | 565876 kb |
| Host | smart-5a2e1385-f391-4da7-9d3f-81a7cf158843 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=749156716 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.xbar_same_source.749156716 |
| Directory | /workspace/6.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/6.xbar_smoke.1186284946 |
| Short name | T2689 |
| Test name | |
| Test status | |
| Simulation time | 46421521 ps |
| CPU time | 6.43 seconds |
| Started | Jun 23 07:21:32 PM PDT 24 |
| Finished | Jun 23 07:21:38 PM PDT 24 |
| Peak memory | 565456 kb |
| Host | smart-c43c1d3b-52a8-4005-94f7-d8609ba0697e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1186284946 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.xbar_smoke.1186284946 |
| Directory | /workspace/6.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/6.xbar_smoke_large_delays.3275242351 |
| Short name | T1387 |
| Test name | |
| Test status | |
| Simulation time | 7396966960 ps |
| CPU time | 81.9 seconds |
| Started | Jun 23 07:21:32 PM PDT 24 |
| Finished | Jun 23 07:22:54 PM PDT 24 |
| Peak memory | 565204 kb |
| Host | smart-7e5f22a6-dedb-448c-b6c3-4dccbf485c98 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3275242351 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.xbar_smoke_large_delays.3275242351 |
| Directory | /workspace/6.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/6.xbar_smoke_slow_rsp.2261661188 |
| Short name | T1837 |
| Test name | |
| Test status | |
| Simulation time | 3763229093 ps |
| CPU time | 64.95 seconds |
| Started | Jun 23 07:21:32 PM PDT 24 |
| Finished | Jun 23 07:22:37 PM PDT 24 |
| Peak memory | 565912 kb |
| Host | smart-654fa046-2edd-4dc0-a2d9-d6a3cad23cf8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2261661188 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.xbar_smoke_slow_rsp.2261661188 |
| Directory | /workspace/6.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/6.xbar_smoke_zero_delays.2736140688 |
| Short name | T2173 |
| Test name | |
| Test status | |
| Simulation time | 44563543 ps |
| CPU time | 6.18 seconds |
| Started | Jun 23 07:21:31 PM PDT 24 |
| Finished | Jun 23 07:21:38 PM PDT 24 |
| Peak memory | 573380 kb |
| Host | smart-9d68b2a9-066d-46fc-b9c6-85e1fc5795c0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2736140688 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.xbar_smoke_zero_delays .2736140688 |
| Directory | /workspace/6.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/6.xbar_stress_all.1789061936 |
| Short name | T533 |
| Test name | |
| Test status | |
| Simulation time | 4669356047 ps |
| CPU time | 204.64 seconds |
| Started | Jun 23 07:21:49 PM PDT 24 |
| Finished | Jun 23 07:25:14 PM PDT 24 |
| Peak memory | 574284 kb |
| Host | smart-cfbc8366-118a-4814-87bc-5275c9580910 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1789061936 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.xbar_stress_all.1789061936 |
| Directory | /workspace/6.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/6.xbar_stress_all_with_error.3010696451 |
| Short name | T2302 |
| Test name | |
| Test status | |
| Simulation time | 2896778495 ps |
| CPU time | 205.25 seconds |
| Started | Jun 23 07:21:50 PM PDT 24 |
| Finished | Jun 23 07:25:16 PM PDT 24 |
| Peak memory | 574376 kb |
| Host | smart-4a9f2408-8045-4963-a870-c71fadd510ce |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3010696451 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.xbar_stress_all_with_error.3010696451 |
| Directory | /workspace/6.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/6.xbar_stress_all_with_rand_reset.993690452 |
| Short name | T2792 |
| Test name | |
| Test status | |
| Simulation time | 2606135606 ps |
| CPU time | 453.86 seconds |
| Started | Jun 23 07:21:49 PM PDT 24 |
| Finished | Jun 23 07:29:23 PM PDT 24 |
| Peak memory | 576324 kb |
| Host | smart-aa9c9283-e507-4f8f-97c5-c3f7a10f25e1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=993690452 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_res et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.xbar_stress_all_w ith_rand_reset.993690452 |
| Directory | /workspace/6.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/6.xbar_stress_all_with_reset_error.2619420627 |
| Short name | T2546 |
| Test name | |
| Test status | |
| Simulation time | 369619689 ps |
| CPU time | 141.88 seconds |
| Started | Jun 23 07:22:01 PM PDT 24 |
| Finished | Jun 23 07:24:23 PM PDT 24 |
| Peak memory | 574312 kb |
| Host | smart-4db200a9-c42f-4b28-bcbe-efee7aca2a80 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2619420627 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.xbar_stress_all _with_reset_error.2619420627 |
| Directory | /workspace/6.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/6.xbar_unmapped_addr.45910026 |
| Short name | T668 |
| Test name | |
| Test status | |
| Simulation time | 1125265822 ps |
| CPU time | 45.38 seconds |
| Started | Jun 23 07:21:47 PM PDT 24 |
| Finished | Jun 23 07:22:33 PM PDT 24 |
| Peak memory | 573456 kb |
| Host | smart-c612388b-cf88-4a3f-a546-419b7fbd7d61 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45910026 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.xbar_unmapped_addr.45910026 |
| Directory | /workspace/6.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/60.xbar_access_same_device.3778461168 |
| Short name | T2265 |
| Test name | |
| Test status | |
| Simulation time | 2847262339 ps |
| CPU time | 105.11 seconds |
| Started | Jun 23 07:34:43 PM PDT 24 |
| Finished | Jun 23 07:36:29 PM PDT 24 |
| Peak memory | 573880 kb |
| Host | smart-c5372330-d645-4d89-aa95-6530f6e6133b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3778461168 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 60.xbar_access_same_device .3778461168 |
| Directory | /workspace/60.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/60.xbar_access_same_device_slow_rsp.1636122796 |
| Short name | T2318 |
| Test name | |
| Test status | |
| Simulation time | 113436463188 ps |
| CPU time | 2059.24 seconds |
| Started | Jun 23 07:34:43 PM PDT 24 |
| Finished | Jun 23 08:09:03 PM PDT 24 |
| Peak memory | 574000 kb |
| Host | smart-0fdfc23f-d464-4079-8c06-d1f43f3fc7f0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1636122796 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 60.xbar_access_same_ device_slow_rsp.1636122796 |
| Directory | /workspace/60.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/60.xbar_error_and_unmapped_addr.14657516 |
| Short name | T2462 |
| Test name | |
| Test status | |
| Simulation time | 91374028 ps |
| CPU time | 7.2 seconds |
| Started | Jun 23 07:34:42 PM PDT 24 |
| Finished | Jun 23 07:34:49 PM PDT 24 |
| Peak memory | 565496 kb |
| Host | smart-e11371c0-1a51-4606-9c30-36c352be5841 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14657516 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 60.xbar_error_and_unmapped_addr.14657516 |
| Directory | /workspace/60.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/60.xbar_error_random.1248360201 |
| Short name | T1483 |
| Test name | |
| Test status | |
| Simulation time | 694685142 ps |
| CPU time | 27.04 seconds |
| Started | Jun 23 07:34:40 PM PDT 24 |
| Finished | Jun 23 07:35:07 PM PDT 24 |
| Peak memory | 573744 kb |
| Host | smart-712bd3e6-0732-478d-811e-da204950225c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1248360201 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 60.xbar_error_random.1248360201 |
| Directory | /workspace/60.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/60.xbar_random.1772075135 |
| Short name | T1852 |
| Test name | |
| Test status | |
| Simulation time | 256740933 ps |
| CPU time | 12.04 seconds |
| Started | Jun 23 07:34:38 PM PDT 24 |
| Finished | Jun 23 07:34:50 PM PDT 24 |
| Peak memory | 574088 kb |
| Host | smart-0a452e95-3e9b-4e66-ae94-98684567980e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1772075135 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 60.xbar_random.1772075135 |
| Directory | /workspace/60.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/60.xbar_random_large_delays.3248058826 |
| Short name | T2455 |
| Test name | |
| Test status | |
| Simulation time | 12058191318 ps |
| CPU time | 114.01 seconds |
| Started | Jun 23 07:34:38 PM PDT 24 |
| Finished | Jun 23 07:36:33 PM PDT 24 |
| Peak memory | 574176 kb |
| Host | smart-8295108c-bef1-474e-8a85-746bc287a641 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3248058826 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 60.xbar_random_large_delays.3248058826 |
| Directory | /workspace/60.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/60.xbar_random_slow_rsp.337481983 |
| Short name | T2269 |
| Test name | |
| Test status | |
| Simulation time | 63008824878 ps |
| CPU time | 1103.17 seconds |
| Started | Jun 23 07:34:36 PM PDT 24 |
| Finished | Jun 23 07:53:00 PM PDT 24 |
| Peak memory | 573504 kb |
| Host | smart-a42ec5cf-9629-46a5-bd32-8eebdd374bef |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=337481983 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 60.xbar_random_slow_rsp.337481983 |
| Directory | /workspace/60.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/60.xbar_random_zero_delays.929964293 |
| Short name | T1456 |
| Test name | |
| Test status | |
| Simulation time | 518781389 ps |
| CPU time | 42.92 seconds |
| Started | Jun 23 07:34:36 PM PDT 24 |
| Finished | Jun 23 07:35:19 PM PDT 24 |
| Peak memory | 573564 kb |
| Host | smart-ba91c662-b23b-442e-afa9-a6ad57a8c5a3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=929964293 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 60.xbar_random_zero_dela ys.929964293 |
| Directory | /workspace/60.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/60.xbar_same_source.3778692309 |
| Short name | T1783 |
| Test name | |
| Test status | |
| Simulation time | 2069532596 ps |
| CPU time | 63.6 seconds |
| Started | Jun 23 07:34:43 PM PDT 24 |
| Finished | Jun 23 07:35:47 PM PDT 24 |
| Peak memory | 573428 kb |
| Host | smart-5a393330-d9d5-44fa-a131-c04ed56928f9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3778692309 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 60.xbar_same_source.3778692309 |
| Directory | /workspace/60.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/60.xbar_smoke.2839950292 |
| Short name | T2600 |
| Test name | |
| Test status | |
| Simulation time | 157111613 ps |
| CPU time | 7.7 seconds |
| Started | Jun 23 07:34:32 PM PDT 24 |
| Finished | Jun 23 07:34:40 PM PDT 24 |
| Peak memory | 565872 kb |
| Host | smart-07c6fde5-8198-4511-8178-dfcfe4373934 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2839950292 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 60.xbar_smoke.2839950292 |
| Directory | /workspace/60.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/60.xbar_smoke_large_delays.3573154735 |
| Short name | T2639 |
| Test name | |
| Test status | |
| Simulation time | 7835295304 ps |
| CPU time | 86.35 seconds |
| Started | Jun 23 07:34:29 PM PDT 24 |
| Finished | Jun 23 07:35:56 PM PDT 24 |
| Peak memory | 565520 kb |
| Host | smart-79ced2fb-015c-4df3-a8dd-b364e041478c |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3573154735 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 60.xbar_smoke_large_delays.3573154735 |
| Directory | /workspace/60.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/60.xbar_smoke_slow_rsp.2717048681 |
| Short name | T2634 |
| Test name | |
| Test status | |
| Simulation time | 5515500936 ps |
| CPU time | 97.97 seconds |
| Started | Jun 23 07:34:34 PM PDT 24 |
| Finished | Jun 23 07:36:12 PM PDT 24 |
| Peak memory | 565536 kb |
| Host | smart-c3bcf05b-3a89-43ed-a511-261d5b36693a |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2717048681 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 60.xbar_smoke_slow_rsp.2717048681 |
| Directory | /workspace/60.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/60.xbar_smoke_zero_delays.1818330540 |
| Short name | T1499 |
| Test name | |
| Test status | |
| Simulation time | 43833379 ps |
| CPU time | 5.85 seconds |
| Started | Jun 23 07:34:33 PM PDT 24 |
| Finished | Jun 23 07:34:40 PM PDT 24 |
| Peak memory | 573680 kb |
| Host | smart-e763bebb-31fe-418e-8c03-8cd85e66e674 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1818330540 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 60.xbar_smoke_zero_delay s.1818330540 |
| Directory | /workspace/60.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/60.xbar_stress_all.3686161260 |
| Short name | T634 |
| Test name | |
| Test status | |
| Simulation time | 15645589975 ps |
| CPU time | 537.83 seconds |
| Started | Jun 23 07:35:08 PM PDT 24 |
| Finished | Jun 23 07:44:06 PM PDT 24 |
| Peak memory | 574276 kb |
| Host | smart-2902273d-022e-4d11-9593-6556027001ad |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3686161260 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 60.xbar_stress_all.3686161260 |
| Directory | /workspace/60.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/60.xbar_stress_all_with_error.4156334277 |
| Short name | T2760 |
| Test name | |
| Test status | |
| Simulation time | 3192421419 ps |
| CPU time | 248.09 seconds |
| Started | Jun 23 07:35:10 PM PDT 24 |
| Finished | Jun 23 07:39:18 PM PDT 24 |
| Peak memory | 574452 kb |
| Host | smart-e289dafd-842c-41fe-9d29-91dd39cc08cd |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4156334277 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 60.xbar_stress_all_with_error.4156334277 |
| Directory | /workspace/60.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/60.xbar_stress_all_with_rand_reset.3655285536 |
| Short name | T1810 |
| Test name | |
| Test status | |
| Simulation time | 186324994 ps |
| CPU time | 75.4 seconds |
| Started | Jun 23 07:35:10 PM PDT 24 |
| Finished | Jun 23 07:36:26 PM PDT 24 |
| Peak memory | 576272 kb |
| Host | smart-66de3e7a-bf9e-411b-99ef-80a068add390 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3655285536 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 60.xbar_stress_all _with_rand_reset.3655285536 |
| Directory | /workspace/60.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/60.xbar_stress_all_with_reset_error.2454473396 |
| Short name | T1967 |
| Test name | |
| Test status | |
| Simulation time | 2972689400 ps |
| CPU time | 272.86 seconds |
| Started | Jun 23 07:35:09 PM PDT 24 |
| Finished | Jun 23 07:39:42 PM PDT 24 |
| Peak memory | 576392 kb |
| Host | smart-5f9e6e91-a5a9-4d01-9a31-d66ac449e197 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2454473396 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 60.xbar_stress_al l_with_reset_error.2454473396 |
| Directory | /workspace/60.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/60.xbar_unmapped_addr.2816155350 |
| Short name | T2046 |
| Test name | |
| Test status | |
| Simulation time | 222960904 ps |
| CPU time | 28.53 seconds |
| Started | Jun 23 07:34:39 PM PDT 24 |
| Finished | Jun 23 07:35:07 PM PDT 24 |
| Peak memory | 574120 kb |
| Host | smart-03022841-cb10-4aca-b914-116140a34282 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2816155350 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 60.xbar_unmapped_addr.2816155350 |
| Directory | /workspace/60.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/61.xbar_access_same_device.1106801490 |
| Short name | T881 |
| Test name | |
| Test status | |
| Simulation time | 1980958997 ps |
| CPU time | 72.99 seconds |
| Started | Jun 23 07:35:17 PM PDT 24 |
| Finished | Jun 23 07:36:31 PM PDT 24 |
| Peak memory | 573952 kb |
| Host | smart-df8fc546-5b9e-45b7-b531-f36d277f1382 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1106801490 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 61.xbar_access_same_device .1106801490 |
| Directory | /workspace/61.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/61.xbar_access_same_device_slow_rsp.1358055128 |
| Short name | T2354 |
| Test name | |
| Test status | |
| Simulation time | 46162562942 ps |
| CPU time | 839.68 seconds |
| Started | Jun 23 07:35:14 PM PDT 24 |
| Finished | Jun 23 07:49:14 PM PDT 24 |
| Peak memory | 574224 kb |
| Host | smart-ba720c6d-fc39-4c50-8390-4bb527a1ed00 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1358055128 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 61.xbar_access_same_ device_slow_rsp.1358055128 |
| Directory | /workspace/61.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/61.xbar_error_and_unmapped_addr.524177450 |
| Short name | T1622 |
| Test name | |
| Test status | |
| Simulation time | 1053688369 ps |
| CPU time | 47.1 seconds |
| Started | Jun 23 07:35:13 PM PDT 24 |
| Finished | Jun 23 07:36:01 PM PDT 24 |
| Peak memory | 573748 kb |
| Host | smart-c9db3e78-a1a3-4a1c-a6a5-46d497b8693f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=524177450 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 61.xbar_error_and_unmapped_addr .524177450 |
| Directory | /workspace/61.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/61.xbar_error_random.4207057321 |
| Short name | T1476 |
| Test name | |
| Test status | |
| Simulation time | 1582535854 ps |
| CPU time | 52.62 seconds |
| Started | Jun 23 07:35:14 PM PDT 24 |
| Finished | Jun 23 07:36:07 PM PDT 24 |
| Peak memory | 573732 kb |
| Host | smart-7522f397-bdb0-4363-942a-c28396845460 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4207057321 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 61.xbar_error_random.4207057321 |
| Directory | /workspace/61.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/61.xbar_random.619816933 |
| Short name | T2469 |
| Test name | |
| Test status | |
| Simulation time | 1974399552 ps |
| CPU time | 71.99 seconds |
| Started | Jun 23 07:35:10 PM PDT 24 |
| Finished | Jun 23 07:36:22 PM PDT 24 |
| Peak memory | 574120 kb |
| Host | smart-8ab0d913-4e48-47c7-9046-2f2a33c044cf |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=619816933 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 61.xbar_random.619816933 |
| Directory | /workspace/61.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/61.xbar_random_large_delays.818979900 |
| Short name | T2441 |
| Test name | |
| Test status | |
| Simulation time | 82302505698 ps |
| CPU time | 912.03 seconds |
| Started | Jun 23 07:35:11 PM PDT 24 |
| Finished | Jun 23 07:50:24 PM PDT 24 |
| Peak memory | 574224 kb |
| Host | smart-3758e0ca-5fa1-445e-a6d5-041686ac8402 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=818979900 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 61.xbar_random_large_delays.818979900 |
| Directory | /workspace/61.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/61.xbar_random_slow_rsp.1532148686 |
| Short name | T1699 |
| Test name | |
| Test status | |
| Simulation time | 10614621288 ps |
| CPU time | 187.88 seconds |
| Started | Jun 23 07:35:09 PM PDT 24 |
| Finished | Jun 23 07:38:17 PM PDT 24 |
| Peak memory | 574112 kb |
| Host | smart-f8b1c478-01dc-4f1c-a959-666d7003ec66 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1532148686 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 61.xbar_random_slow_rsp.1532148686 |
| Directory | /workspace/61.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/61.xbar_random_zero_delays.3352211503 |
| Short name | T648 |
| Test name | |
| Test status | |
| Simulation time | 161971694 ps |
| CPU time | 15.97 seconds |
| Started | Jun 23 07:35:11 PM PDT 24 |
| Finished | Jun 23 07:35:27 PM PDT 24 |
| Peak memory | 573708 kb |
| Host | smart-7d900f05-fefa-4bd4-9892-a11236aebf7a |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3352211503 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 61.xbar_random_zero_del ays.3352211503 |
| Directory | /workspace/61.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/61.xbar_same_source.2665191433 |
| Short name | T1947 |
| Test name | |
| Test status | |
| Simulation time | 1969634260 ps |
| CPU time | 60.66 seconds |
| Started | Jun 23 07:35:14 PM PDT 24 |
| Finished | Jun 23 07:36:15 PM PDT 24 |
| Peak memory | 574108 kb |
| Host | smart-b700d28d-2687-4f29-ba7d-b94a202acae3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2665191433 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 61.xbar_same_source.2665191433 |
| Directory | /workspace/61.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/61.xbar_smoke.1874270314 |
| Short name | T2262 |
| Test name | |
| Test status | |
| Simulation time | 257894208 ps |
| CPU time | 10.06 seconds |
| Started | Jun 23 07:35:08 PM PDT 24 |
| Finished | Jun 23 07:35:18 PM PDT 24 |
| Peak memory | 565168 kb |
| Host | smart-c07c6513-7e6c-4828-bbf3-9b9956c6c633 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1874270314 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 61.xbar_smoke.1874270314 |
| Directory | /workspace/61.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/61.xbar_smoke_large_delays.851441978 |
| Short name | T1493 |
| Test name | |
| Test status | |
| Simulation time | 7292235203 ps |
| CPU time | 72.15 seconds |
| Started | Jun 23 07:35:08 PM PDT 24 |
| Finished | Jun 23 07:36:20 PM PDT 24 |
| Peak memory | 574124 kb |
| Host | smart-97bc23f5-f022-43b3-a16a-a661289d4445 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=851441978 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 61.xbar_smoke_large_delays.851441978 |
| Directory | /workspace/61.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/61.xbar_smoke_slow_rsp.1333419824 |
| Short name | T2833 |
| Test name | |
| Test status | |
| Simulation time | 4455147876 ps |
| CPU time | 77.13 seconds |
| Started | Jun 23 07:35:10 PM PDT 24 |
| Finished | Jun 23 07:36:27 PM PDT 24 |
| Peak memory | 565920 kb |
| Host | smart-47ac46c7-135c-4a64-b274-a6faceb8ad66 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1333419824 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 61.xbar_smoke_slow_rsp.1333419824 |
| Directory | /workspace/61.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/61.xbar_smoke_zero_delays.1999947065 |
| Short name | T2698 |
| Test name | |
| Test status | |
| Simulation time | 42779113 ps |
| CPU time | 6.05 seconds |
| Started | Jun 23 07:35:09 PM PDT 24 |
| Finished | Jun 23 07:35:16 PM PDT 24 |
| Peak memory | 565496 kb |
| Host | smart-d19e1777-e20b-4c15-a8c0-0e6837840239 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1999947065 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 61.xbar_smoke_zero_delay s.1999947065 |
| Directory | /workspace/61.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/61.xbar_stress_all.3131693669 |
| Short name | T1692 |
| Test name | |
| Test status | |
| Simulation time | 3279428879 ps |
| CPU time | 253.8 seconds |
| Started | Jun 23 07:35:13 PM PDT 24 |
| Finished | Jun 23 07:39:27 PM PDT 24 |
| Peak memory | 574020 kb |
| Host | smart-eee9e9ad-cdd3-4e03-ba79-457b1a2a053d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3131693669 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 61.xbar_stress_all.3131693669 |
| Directory | /workspace/61.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/61.xbar_stress_all_with_error.3806024355 |
| Short name | T2805 |
| Test name | |
| Test status | |
| Simulation time | 6233558657 ps |
| CPU time | 212.51 seconds |
| Started | Jun 23 07:35:27 PM PDT 24 |
| Finished | Jun 23 07:39:00 PM PDT 24 |
| Peak memory | 574372 kb |
| Host | smart-dcd7e839-d8c1-40b1-a0fa-ad7aa6dafefc |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3806024355 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 61.xbar_stress_all_with_error.3806024355 |
| Directory | /workspace/61.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/61.xbar_stress_all_with_rand_reset.1283470293 |
| Short name | T2607 |
| Test name | |
| Test status | |
| Simulation time | 2959909935 ps |
| CPU time | 259.18 seconds |
| Started | Jun 23 07:35:19 PM PDT 24 |
| Finished | Jun 23 07:39:39 PM PDT 24 |
| Peak memory | 574312 kb |
| Host | smart-62a7fab8-1899-4f37-9329-da229cd347ee |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1283470293 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 61.xbar_stress_all _with_rand_reset.1283470293 |
| Directory | /workspace/61.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/61.xbar_stress_all_with_reset_error.1525791346 |
| Short name | T905 |
| Test name | |
| Test status | |
| Simulation time | 856634643 ps |
| CPU time | 257.62 seconds |
| Started | Jun 23 07:35:15 PM PDT 24 |
| Finished | Jun 23 07:39:33 PM PDT 24 |
| Peak memory | 576364 kb |
| Host | smart-adfc20b5-d337-4704-85c6-e96da41bd45a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1525791346 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 61.xbar_stress_al l_with_reset_error.1525791346 |
| Directory | /workspace/61.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/61.xbar_unmapped_addr.2173324389 |
| Short name | T2096 |
| Test name | |
| Test status | |
| Simulation time | 978171794 ps |
| CPU time | 44.47 seconds |
| Started | Jun 23 07:35:13 PM PDT 24 |
| Finished | Jun 23 07:35:58 PM PDT 24 |
| Peak memory | 573420 kb |
| Host | smart-7fc17290-f02d-4c28-8af2-20645f356750 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2173324389 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 61.xbar_unmapped_addr.2173324389 |
| Directory | /workspace/61.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/62.xbar_access_same_device.4102643943 |
| Short name | T2133 |
| Test name | |
| Test status | |
| Simulation time | 753860350 ps |
| CPU time | 46.87 seconds |
| Started | Jun 23 07:35:13 PM PDT 24 |
| Finished | Jun 23 07:36:00 PM PDT 24 |
| Peak memory | 573448 kb |
| Host | smart-e181e612-00dc-4550-8efd-e77e6beef7d2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4102643943 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 62.xbar_access_same_device .4102643943 |
| Directory | /workspace/62.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/62.xbar_error_and_unmapped_addr.3805898477 |
| Short name | T1639 |
| Test name | |
| Test status | |
| Simulation time | 115663609 ps |
| CPU time | 14.56 seconds |
| Started | Jun 23 07:35:14 PM PDT 24 |
| Finished | Jun 23 07:35:29 PM PDT 24 |
| Peak memory | 573724 kb |
| Host | smart-f37255cd-d423-4824-abf0-5ae53309a7ec |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3805898477 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 62.xbar_error_and_unmapped_add r.3805898477 |
| Directory | /workspace/62.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/62.xbar_error_random.1527158305 |
| Short name | T1460 |
| Test name | |
| Test status | |
| Simulation time | 65755327 ps |
| CPU time | 8.48 seconds |
| Started | Jun 23 07:35:22 PM PDT 24 |
| Finished | Jun 23 07:35:30 PM PDT 24 |
| Peak memory | 573704 kb |
| Host | smart-ecfae85d-68df-4a05-8609-0973042a279d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1527158305 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 62.xbar_error_random.1527158305 |
| Directory | /workspace/62.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/62.xbar_random.1040474542 |
| Short name | T2062 |
| Test name | |
| Test status | |
| Simulation time | 430234157 ps |
| CPU time | 18.55 seconds |
| Started | Jun 23 07:35:14 PM PDT 24 |
| Finished | Jun 23 07:35:33 PM PDT 24 |
| Peak memory | 573380 kb |
| Host | smart-b83a21ae-49d0-405c-8d1b-ff87c7ef11df |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1040474542 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 62.xbar_random.1040474542 |
| Directory | /workspace/62.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/62.xbar_random_large_delays.2145974830 |
| Short name | T2554 |
| Test name | |
| Test status | |
| Simulation time | 93239896938 ps |
| CPU time | 973.56 seconds |
| Started | Jun 23 07:35:14 PM PDT 24 |
| Finished | Jun 23 07:51:27 PM PDT 24 |
| Peak memory | 574216 kb |
| Host | smart-c6971029-1d4a-4437-af2b-fbec4646fca7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2145974830 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 62.xbar_random_large_delays.2145974830 |
| Directory | /workspace/62.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/62.xbar_random_slow_rsp.856438687 |
| Short name | T2616 |
| Test name | |
| Test status | |
| Simulation time | 5577576526 ps |
| CPU time | 97.52 seconds |
| Started | Jun 23 07:35:13 PM PDT 24 |
| Finished | Jun 23 07:36:51 PM PDT 24 |
| Peak memory | 565984 kb |
| Host | smart-8bae15c9-d3fe-44d7-8f61-cc64c5cab0b9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=856438687 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 62.xbar_random_slow_rsp.856438687 |
| Directory | /workspace/62.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/62.xbar_random_zero_delays.2380333842 |
| Short name | T481 |
| Test name | |
| Test status | |
| Simulation time | 385986747 ps |
| CPU time | 35.92 seconds |
| Started | Jun 23 07:35:14 PM PDT 24 |
| Finished | Jun 23 07:35:50 PM PDT 24 |
| Peak memory | 573432 kb |
| Host | smart-f8f72e43-9983-4123-a809-fbff08a41889 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2380333842 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 62.xbar_random_zero_del ays.2380333842 |
| Directory | /workspace/62.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/62.xbar_same_source.1717831920 |
| Short name | T2466 |
| Test name | |
| Test status | |
| Simulation time | 164861036 ps |
| CPU time | 14.36 seconds |
| Started | Jun 23 07:35:12 PM PDT 24 |
| Finished | Jun 23 07:35:27 PM PDT 24 |
| Peak memory | 574104 kb |
| Host | smart-ac63129c-71f7-4b27-8077-f6eb897f8cb3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1717831920 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 62.xbar_same_source.1717831920 |
| Directory | /workspace/62.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/62.xbar_smoke.1499215558 |
| Short name | T1960 |
| Test name | |
| Test status | |
| Simulation time | 146357552 ps |
| CPU time | 7.81 seconds |
| Started | Jun 23 07:35:17 PM PDT 24 |
| Finished | Jun 23 07:35:25 PM PDT 24 |
| Peak memory | 565144 kb |
| Host | smart-c538b0e1-848c-4115-bb3a-727d57ec7d28 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1499215558 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 62.xbar_smoke.1499215558 |
| Directory | /workspace/62.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/62.xbar_smoke_large_delays.210419170 |
| Short name | T2786 |
| Test name | |
| Test status | |
| Simulation time | 8865432301 ps |
| CPU time | 98.48 seconds |
| Started | Jun 23 07:35:18 PM PDT 24 |
| Finished | Jun 23 07:36:57 PM PDT 24 |
| Peak memory | 573736 kb |
| Host | smart-d0c784ca-5133-4c5c-ba14-a11d29cd69e6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=210419170 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 62.xbar_smoke_large_delays.210419170 |
| Directory | /workspace/62.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/62.xbar_smoke_slow_rsp.1622595520 |
| Short name | T2337 |
| Test name | |
| Test status | |
| Simulation time | 5109893552 ps |
| CPU time | 90.79 seconds |
| Started | Jun 23 07:35:20 PM PDT 24 |
| Finished | Jun 23 07:36:51 PM PDT 24 |
| Peak memory | 565280 kb |
| Host | smart-12ad3b4c-154e-4645-b940-dce7a3b9a911 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1622595520 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 62.xbar_smoke_slow_rsp.1622595520 |
| Directory | /workspace/62.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/62.xbar_smoke_zero_delays.2723867386 |
| Short name | T2240 |
| Test name | |
| Test status | |
| Simulation time | 53311389 ps |
| CPU time | 6.28 seconds |
| Started | Jun 23 07:35:17 PM PDT 24 |
| Finished | Jun 23 07:35:24 PM PDT 24 |
| Peak memory | 565416 kb |
| Host | smart-f59b1c30-fd8b-4599-8d2b-d36ee093a28f |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2723867386 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 62.xbar_smoke_zero_delay s.2723867386 |
| Directory | /workspace/62.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/62.xbar_stress_all.4037962142 |
| Short name | T2152 |
| Test name | |
| Test status | |
| Simulation time | 10650641007 ps |
| CPU time | 380.88 seconds |
| Started | Jun 23 07:35:13 PM PDT 24 |
| Finished | Jun 23 07:41:35 PM PDT 24 |
| Peak memory | 574208 kb |
| Host | smart-251e88c2-e96b-4fd2-b285-5aced92005b3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4037962142 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 62.xbar_stress_all.4037962142 |
| Directory | /workspace/62.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/62.xbar_stress_all_with_error.544837413 |
| Short name | T1665 |
| Test name | |
| Test status | |
| Simulation time | 2748563483 ps |
| CPU time | 214.05 seconds |
| Started | Jun 23 07:35:15 PM PDT 24 |
| Finished | Jun 23 07:38:49 PM PDT 24 |
| Peak memory | 574384 kb |
| Host | smart-4838939a-7211-491b-a484-162b40b25156 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=544837413 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 62.xbar_stress_all_with_error.544837413 |
| Directory | /workspace/62.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/62.xbar_stress_all_with_rand_reset.935393549 |
| Short name | T2307 |
| Test name | |
| Test status | |
| Simulation time | 16576466916 ps |
| CPU time | 837.19 seconds |
| Started | Jun 23 07:35:12 PM PDT 24 |
| Finished | Jun 23 07:49:10 PM PDT 24 |
| Peak memory | 576292 kb |
| Host | smart-66a6ea5f-1ce1-4a50-8c6e-b694afcde2e3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=935393549 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_res et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 62.xbar_stress_all_ with_rand_reset.935393549 |
| Directory | /workspace/62.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/62.xbar_stress_all_with_reset_error.3043295621 |
| Short name | T1523 |
| Test name | |
| Test status | |
| Simulation time | 575418712 ps |
| CPU time | 136.75 seconds |
| Started | Jun 23 07:35:18 PM PDT 24 |
| Finished | Jun 23 07:37:35 PM PDT 24 |
| Peak memory | 574308 kb |
| Host | smart-d0821491-43cd-47cf-8d1a-d0d34618781b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3043295621 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 62.xbar_stress_al l_with_reset_error.3043295621 |
| Directory | /workspace/62.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/62.xbar_unmapped_addr.2241029741 |
| Short name | T2430 |
| Test name | |
| Test status | |
| Simulation time | 1065217032 ps |
| CPU time | 45.53 seconds |
| Started | Jun 23 07:35:24 PM PDT 24 |
| Finished | Jun 23 07:36:09 PM PDT 24 |
| Peak memory | 573496 kb |
| Host | smart-531ac7d5-39ad-4ffc-a54f-175f256b6faa |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2241029741 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 62.xbar_unmapped_addr.2241029741 |
| Directory | /workspace/62.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/63.xbar_access_same_device.3503171798 |
| Short name | T2239 |
| Test name | |
| Test status | |
| Simulation time | 323239414 ps |
| CPU time | 16.01 seconds |
| Started | Jun 23 07:35:14 PM PDT 24 |
| Finished | Jun 23 07:35:30 PM PDT 24 |
| Peak memory | 574072 kb |
| Host | smart-7e33a3da-b8f7-4853-9616-c8b35abe0ced |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3503171798 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 63.xbar_access_same_device .3503171798 |
| Directory | /workspace/63.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/63.xbar_access_same_device_slow_rsp.540165757 |
| Short name | T2034 |
| Test name | |
| Test status | |
| Simulation time | 125966356648 ps |
| CPU time | 2226.37 seconds |
| Started | Jun 23 07:35:23 PM PDT 24 |
| Finished | Jun 23 08:12:30 PM PDT 24 |
| Peak memory | 574220 kb |
| Host | smart-88b07349-8580-4152-8590-cf7e3b3602ae |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=540165757 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 63.xbar_access_same_d evice_slow_rsp.540165757 |
| Directory | /workspace/63.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/63.xbar_error_and_unmapped_addr.3714778397 |
| Short name | T1682 |
| Test name | |
| Test status | |
| Simulation time | 423390315 ps |
| CPU time | 17.85 seconds |
| Started | Jun 23 07:35:17 PM PDT 24 |
| Finished | Jun 23 07:35:35 PM PDT 24 |
| Peak memory | 573688 kb |
| Host | smart-16128830-aaa9-482a-bd01-db00d9753e8a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3714778397 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 63.xbar_error_and_unmapped_add r.3714778397 |
| Directory | /workspace/63.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/63.xbar_error_random.3806463230 |
| Short name | T1537 |
| Test name | |
| Test status | |
| Simulation time | 2448848922 ps |
| CPU time | 83.44 seconds |
| Started | Jun 23 07:35:19 PM PDT 24 |
| Finished | Jun 23 07:36:43 PM PDT 24 |
| Peak memory | 573776 kb |
| Host | smart-5939f052-0f1f-4ad3-84de-61c6839cc435 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3806463230 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 63.xbar_error_random.3806463230 |
| Directory | /workspace/63.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/63.xbar_random.2038133499 |
| Short name | T2569 |
| Test name | |
| Test status | |
| Simulation time | 2172732506 ps |
| CPU time | 75.72 seconds |
| Started | Jun 23 07:35:20 PM PDT 24 |
| Finished | Jun 23 07:36:36 PM PDT 24 |
| Peak memory | 574156 kb |
| Host | smart-30d06feb-5e09-466a-af05-3c155a584d40 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2038133499 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 63.xbar_random.2038133499 |
| Directory | /workspace/63.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/63.xbar_random_large_delays.3367560422 |
| Short name | T524 |
| Test name | |
| Test status | |
| Simulation time | 56271771920 ps |
| CPU time | 575.12 seconds |
| Started | Jun 23 07:35:18 PM PDT 24 |
| Finished | Jun 23 07:44:54 PM PDT 24 |
| Peak memory | 573504 kb |
| Host | smart-277f7f5a-ed0d-4c17-ad9d-1182f3a49974 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3367560422 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 63.xbar_random_large_delays.3367560422 |
| Directory | /workspace/63.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/63.xbar_random_slow_rsp.805620127 |
| Short name | T453 |
| Test name | |
| Test status | |
| Simulation time | 11034223904 ps |
| CPU time | 177.01 seconds |
| Started | Jun 23 07:35:15 PM PDT 24 |
| Finished | Jun 23 07:38:12 PM PDT 24 |
| Peak memory | 573468 kb |
| Host | smart-c3c83658-6748-42dd-9d24-70c5110f025b |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=805620127 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 63.xbar_random_slow_rsp.805620127 |
| Directory | /workspace/63.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/63.xbar_random_zero_delays.3225502396 |
| Short name | T2141 |
| Test name | |
| Test status | |
| Simulation time | 38299529 ps |
| CPU time | 6.33 seconds |
| Started | Jun 23 07:35:17 PM PDT 24 |
| Finished | Jun 23 07:35:23 PM PDT 24 |
| Peak memory | 565668 kb |
| Host | smart-e2032f2b-dc96-4de8-9aba-cb152f92e128 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3225502396 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 63.xbar_random_zero_del ays.3225502396 |
| Directory | /workspace/63.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/63.xbar_same_source.3361578597 |
| Short name | T1771 |
| Test name | |
| Test status | |
| Simulation time | 229921626 ps |
| CPU time | 10.43 seconds |
| Started | Jun 23 07:35:17 PM PDT 24 |
| Finished | Jun 23 07:35:28 PM PDT 24 |
| Peak memory | 565876 kb |
| Host | smart-af1759d4-f0a8-408a-affd-4e4318e57f69 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3361578597 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 63.xbar_same_source.3361578597 |
| Directory | /workspace/63.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/63.xbar_smoke.2755725123 |
| Short name | T2818 |
| Test name | |
| Test status | |
| Simulation time | 189668186 ps |
| CPU time | 8.36 seconds |
| Started | Jun 23 07:35:16 PM PDT 24 |
| Finished | Jun 23 07:35:25 PM PDT 24 |
| Peak memory | 565888 kb |
| Host | smart-358a528a-0a21-48c8-9573-c1490ef862a0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2755725123 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 63.xbar_smoke.2755725123 |
| Directory | /workspace/63.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/63.xbar_smoke_large_delays.3970897590 |
| Short name | T1450 |
| Test name | |
| Test status | |
| Simulation time | 6580425659 ps |
| CPU time | 65.59 seconds |
| Started | Jun 23 07:35:16 PM PDT 24 |
| Finished | Jun 23 07:36:21 PM PDT 24 |
| Peak memory | 565220 kb |
| Host | smart-f2d22d49-e31b-449b-93e5-4d8f0a806b82 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3970897590 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 63.xbar_smoke_large_delays.3970897590 |
| Directory | /workspace/63.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/63.xbar_smoke_slow_rsp.3763810002 |
| Short name | T1723 |
| Test name | |
| Test status | |
| Simulation time | 5170745092 ps |
| CPU time | 86.36 seconds |
| Started | Jun 23 07:35:17 PM PDT 24 |
| Finished | Jun 23 07:36:44 PM PDT 24 |
| Peak memory | 565916 kb |
| Host | smart-3b1cd0a8-f762-4597-8651-69cdfc78c938 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3763810002 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 63.xbar_smoke_slow_rsp.3763810002 |
| Directory | /workspace/63.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/63.xbar_smoke_zero_delays.2340011235 |
| Short name | T2535 |
| Test name | |
| Test status | |
| Simulation time | 38757528 ps |
| CPU time | 5.38 seconds |
| Started | Jun 23 07:35:18 PM PDT 24 |
| Finished | Jun 23 07:35:24 PM PDT 24 |
| Peak memory | 565164 kb |
| Host | smart-5056810b-9781-447f-ad6e-ba63d7c9ee19 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2340011235 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 63.xbar_smoke_zero_delay s.2340011235 |
| Directory | /workspace/63.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/63.xbar_stress_all.2310327330 |
| Short name | T470 |
| Test name | |
| Test status | |
| Simulation time | 2430261884 ps |
| CPU time | 218.64 seconds |
| Started | Jun 23 07:35:18 PM PDT 24 |
| Finished | Jun 23 07:38:57 PM PDT 24 |
| Peak memory | 574264 kb |
| Host | smart-56f0b9e9-7441-4ad5-b284-f9df0ea326e7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2310327330 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 63.xbar_stress_all.2310327330 |
| Directory | /workspace/63.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/63.xbar_stress_all_with_error.693549023 |
| Short name | T2708 |
| Test name | |
| Test status | |
| Simulation time | 10812052801 ps |
| CPU time | 479.05 seconds |
| Started | Jun 23 07:35:19 PM PDT 24 |
| Finished | Jun 23 07:43:19 PM PDT 24 |
| Peak memory | 573696 kb |
| Host | smart-65e6a2d8-c0f1-4262-b731-55b839dbd920 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=693549023 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 63.xbar_stress_all_with_error.693549023 |
| Directory | /workspace/63.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/63.xbar_stress_all_with_rand_reset.186779424 |
| Short name | T2095 |
| Test name | |
| Test status | |
| Simulation time | 12484047552 ps |
| CPU time | 625.19 seconds |
| Started | Jun 23 07:35:19 PM PDT 24 |
| Finished | Jun 23 07:45:44 PM PDT 24 |
| Peak memory | 574316 kb |
| Host | smart-d52e6238-f0f5-4849-918d-018b616a011a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=186779424 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_res et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 63.xbar_stress_all_ with_rand_reset.186779424 |
| Directory | /workspace/63.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/63.xbar_unmapped_addr.3509362362 |
| Short name | T584 |
| Test name | |
| Test status | |
| Simulation time | 187366614 ps |
| CPU time | 23.8 seconds |
| Started | Jun 23 07:35:19 PM PDT 24 |
| Finished | Jun 23 07:35:43 PM PDT 24 |
| Peak memory | 573496 kb |
| Host | smart-fe726e2e-fd7f-45d9-9fac-591f744be758 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3509362362 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 63.xbar_unmapped_addr.3509362362 |
| Directory | /workspace/63.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/64.xbar_access_same_device.3436003096 |
| Short name | T2660 |
| Test name | |
| Test status | |
| Simulation time | 93855821 ps |
| CPU time | 7.29 seconds |
| Started | Jun 23 07:35:21 PM PDT 24 |
| Finished | Jun 23 07:35:29 PM PDT 24 |
| Peak memory | 565856 kb |
| Host | smart-0df401ad-8c52-48c5-a35e-f1128836fb2e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3436003096 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 64.xbar_access_same_device .3436003096 |
| Directory | /workspace/64.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/64.xbar_error_and_unmapped_addr.4091190622 |
| Short name | T1434 |
| Test name | |
| Test status | |
| Simulation time | 57931591 ps |
| CPU time | 8.63 seconds |
| Started | Jun 23 07:35:19 PM PDT 24 |
| Finished | Jun 23 07:35:28 PM PDT 24 |
| Peak memory | 573644 kb |
| Host | smart-96756f79-4d83-4557-a012-c864081eac66 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4091190622 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 64.xbar_error_and_unmapped_add r.4091190622 |
| Directory | /workspace/64.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/64.xbar_error_random.1903101275 |
| Short name | T1381 |
| Test name | |
| Test status | |
| Simulation time | 1981758774 ps |
| CPU time | 68.52 seconds |
| Started | Jun 23 07:35:20 PM PDT 24 |
| Finished | Jun 23 07:36:28 PM PDT 24 |
| Peak memory | 573740 kb |
| Host | smart-50ce9929-4a81-4dda-b6c1-06dfaf50ab8b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1903101275 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 64.xbar_error_random.1903101275 |
| Directory | /workspace/64.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/64.xbar_random.4159483243 |
| Short name | T1855 |
| Test name | |
| Test status | |
| Simulation time | 455311149 ps |
| CPU time | 15.67 seconds |
| Started | Jun 23 07:35:18 PM PDT 24 |
| Finished | Jun 23 07:35:34 PM PDT 24 |
| Peak memory | 574076 kb |
| Host | smart-ab3cc5c8-4b12-4a43-8a47-7abead4b6c36 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4159483243 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 64.xbar_random.4159483243 |
| Directory | /workspace/64.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/64.xbar_random_large_delays.2137384444 |
| Short name | T2320 |
| Test name | |
| Test status | |
| Simulation time | 17970465399 ps |
| CPU time | 196.38 seconds |
| Started | Jun 23 07:35:15 PM PDT 24 |
| Finished | Jun 23 07:38:31 PM PDT 24 |
| Peak memory | 573520 kb |
| Host | smart-69932a56-bc64-43d8-9adc-28bfbd718140 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2137384444 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 64.xbar_random_large_delays.2137384444 |
| Directory | /workspace/64.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/64.xbar_random_slow_rsp.2501049887 |
| Short name | T2185 |
| Test name | |
| Test status | |
| Simulation time | 7598208352 ps |
| CPU time | 127.11 seconds |
| Started | Jun 23 07:35:17 PM PDT 24 |
| Finished | Jun 23 07:37:24 PM PDT 24 |
| Peak memory | 573640 kb |
| Host | smart-d080d921-e57f-4c39-8402-cb31ba62610d |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2501049887 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 64.xbar_random_slow_rsp.2501049887 |
| Directory | /workspace/64.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/64.xbar_random_zero_delays.2719191505 |
| Short name | T530 |
| Test name | |
| Test status | |
| Simulation time | 457314168 ps |
| CPU time | 43.25 seconds |
| Started | Jun 23 07:35:16 PM PDT 24 |
| Finished | Jun 23 07:35:59 PM PDT 24 |
| Peak memory | 574072 kb |
| Host | smart-3c6dac8b-f03d-464b-b93b-e6478b89fb79 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2719191505 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 64.xbar_random_zero_del ays.2719191505 |
| Directory | /workspace/64.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/64.xbar_same_source.2885746537 |
| Short name | T2205 |
| Test name | |
| Test status | |
| Simulation time | 1057991465 ps |
| CPU time | 28.49 seconds |
| Started | Jun 23 07:35:14 PM PDT 24 |
| Finished | Jun 23 07:35:43 PM PDT 24 |
| Peak memory | 574088 kb |
| Host | smart-6ec646f9-b35f-4c64-b056-9921070f8209 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2885746537 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 64.xbar_same_source.2885746537 |
| Directory | /workspace/64.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/64.xbar_smoke.1030381819 |
| Short name | T1843 |
| Test name | |
| Test status | |
| Simulation time | 48923547 ps |
| CPU time | 6.7 seconds |
| Started | Jun 23 07:35:17 PM PDT 24 |
| Finished | Jun 23 07:35:24 PM PDT 24 |
| Peak memory | 565748 kb |
| Host | smart-0cff8caa-ea9a-4b3e-817f-dd5a7fec1993 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1030381819 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 64.xbar_smoke.1030381819 |
| Directory | /workspace/64.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/64.xbar_smoke_large_delays.3896487858 |
| Short name | T2134 |
| Test name | |
| Test status | |
| Simulation time | 6764870394 ps |
| CPU time | 69.31 seconds |
| Started | Jun 23 07:35:17 PM PDT 24 |
| Finished | Jun 23 07:36:26 PM PDT 24 |
| Peak memory | 565928 kb |
| Host | smart-e69284b4-6d88-4e9f-842b-4cf77d05a960 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3896487858 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 64.xbar_smoke_large_delays.3896487858 |
| Directory | /workspace/64.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/64.xbar_smoke_slow_rsp.378659957 |
| Short name | T2238 |
| Test name | |
| Test status | |
| Simulation time | 4472871023 ps |
| CPU time | 76.14 seconds |
| Started | Jun 23 07:35:16 PM PDT 24 |
| Finished | Jun 23 07:36:33 PM PDT 24 |
| Peak memory | 565928 kb |
| Host | smart-7b4d6ad5-34f8-4b82-9763-ff619ea00e85 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=378659957 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 64.xbar_smoke_slow_rsp.378659957 |
| Directory | /workspace/64.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/64.xbar_smoke_zero_delays.1212647653 |
| Short name | T1854 |
| Test name | |
| Test status | |
| Simulation time | 43885424 ps |
| CPU time | 6.06 seconds |
| Started | Jun 23 07:35:24 PM PDT 24 |
| Finished | Jun 23 07:35:30 PM PDT 24 |
| Peak memory | 565184 kb |
| Host | smart-99090d7d-345c-4d1d-84c6-c2afa0bf5dd6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1212647653 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 64.xbar_smoke_zero_delay s.1212647653 |
| Directory | /workspace/64.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/64.xbar_stress_all.2112631006 |
| Short name | T1760 |
| Test name | |
| Test status | |
| Simulation time | 3372740577 ps |
| CPU time | 119.09 seconds |
| Started | Jun 23 07:35:22 PM PDT 24 |
| Finished | Jun 23 07:37:21 PM PDT 24 |
| Peak memory | 574244 kb |
| Host | smart-9b8aaaeb-830c-4281-8c78-8465b3ef18da |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2112631006 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 64.xbar_stress_all.2112631006 |
| Directory | /workspace/64.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/64.xbar_stress_all_with_error.1210073621 |
| Short name | T1634 |
| Test name | |
| Test status | |
| Simulation time | 14356460695 ps |
| CPU time | 541.25 seconds |
| Started | Jun 23 07:35:26 PM PDT 24 |
| Finished | Jun 23 07:44:28 PM PDT 24 |
| Peak memory | 574352 kb |
| Host | smart-b3b8b93f-d0c3-4888-9fed-a51a2a3f9f6e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1210073621 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 64.xbar_stress_all_with_error.1210073621 |
| Directory | /workspace/64.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/64.xbar_stress_all_with_rand_reset.232200195 |
| Short name | T548 |
| Test name | |
| Test status | |
| Simulation time | 7708266319 ps |
| CPU time | 808.18 seconds |
| Started | Jun 23 07:35:26 PM PDT 24 |
| Finished | Jun 23 07:48:54 PM PDT 24 |
| Peak memory | 576364 kb |
| Host | smart-38125e89-8bc6-4c79-a964-e2795a450eed |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=232200195 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_res et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 64.xbar_stress_all_ with_rand_reset.232200195 |
| Directory | /workspace/64.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/64.xbar_stress_all_with_reset_error.3082181926 |
| Short name | T892 |
| Test name | |
| Test status | |
| Simulation time | 197999910 ps |
| CPU time | 73.75 seconds |
| Started | Jun 23 07:35:24 PM PDT 24 |
| Finished | Jun 23 07:36:38 PM PDT 24 |
| Peak memory | 576344 kb |
| Host | smart-68d2ed1e-c6fc-4e29-aa94-fde91732dd6f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3082181926 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 64.xbar_stress_al l_with_reset_error.3082181926 |
| Directory | /workspace/64.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/64.xbar_unmapped_addr.993073358 |
| Short name | T1763 |
| Test name | |
| Test status | |
| Simulation time | 196129918 ps |
| CPU time | 22.33 seconds |
| Started | Jun 23 07:35:26 PM PDT 24 |
| Finished | Jun 23 07:35:48 PM PDT 24 |
| Peak memory | 573444 kb |
| Host | smart-a90513bd-dc6e-4b70-80cc-aa7eeebc603e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=993073358 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 64.xbar_unmapped_addr.993073358 |
| Directory | /workspace/64.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/65.xbar_access_same_device.1603284409 |
| Short name | T2282 |
| Test name | |
| Test status | |
| Simulation time | 1912226081 ps |
| CPU time | 79.11 seconds |
| Started | Jun 23 07:35:23 PM PDT 24 |
| Finished | Jun 23 07:36:42 PM PDT 24 |
| Peak memory | 574060 kb |
| Host | smart-ca9e2367-5ee0-4e35-928f-84da397e3725 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1603284409 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 65.xbar_access_same_device .1603284409 |
| Directory | /workspace/65.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/65.xbar_access_same_device_slow_rsp.2325920664 |
| Short name | T1851 |
| Test name | |
| Test status | |
| Simulation time | 149248802439 ps |
| CPU time | 2707.53 seconds |
| Started | Jun 23 07:35:23 PM PDT 24 |
| Finished | Jun 23 08:20:31 PM PDT 24 |
| Peak memory | 574224 kb |
| Host | smart-4214ccdb-8606-4281-b537-ae4790934f1a |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2325920664 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 65.xbar_access_same_ device_slow_rsp.2325920664 |
| Directory | /workspace/65.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/65.xbar_error_and_unmapped_addr.2965883236 |
| Short name | T2316 |
| Test name | |
| Test status | |
| Simulation time | 1001114617 ps |
| CPU time | 34.74 seconds |
| Started | Jun 23 07:35:22 PM PDT 24 |
| Finished | Jun 23 07:35:57 PM PDT 24 |
| Peak memory | 573388 kb |
| Host | smart-616cf3b3-5c73-4acd-bdd0-aa2c6abc72c3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2965883236 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 65.xbar_error_and_unmapped_add r.2965883236 |
| Directory | /workspace/65.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/65.xbar_error_random.798290618 |
| Short name | T1511 |
| Test name | |
| Test status | |
| Simulation time | 467871583 ps |
| CPU time | 38.43 seconds |
| Started | Jun 23 07:35:22 PM PDT 24 |
| Finished | Jun 23 07:36:01 PM PDT 24 |
| Peak memory | 573732 kb |
| Host | smart-c736719c-0c46-4b09-807a-8a46e8c8c68e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=798290618 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 65.xbar_error_random.798290618 |
| Directory | /workspace/65.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/65.xbar_random.1572848671 |
| Short name | T2680 |
| Test name | |
| Test status | |
| Simulation time | 364580210 ps |
| CPU time | 16.26 seconds |
| Started | Jun 23 07:35:18 PM PDT 24 |
| Finished | Jun 23 07:35:35 PM PDT 24 |
| Peak memory | 574056 kb |
| Host | smart-56f02f42-51e1-46e6-83d6-f8cc512c6d7f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1572848671 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 65.xbar_random.1572848671 |
| Directory | /workspace/65.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/65.xbar_random_large_delays.4166601884 |
| Short name | T2559 |
| Test name | |
| Test status | |
| Simulation time | 63227399232 ps |
| CPU time | 630.69 seconds |
| Started | Jun 23 07:35:20 PM PDT 24 |
| Finished | Jun 23 07:45:51 PM PDT 24 |
| Peak memory | 574184 kb |
| Host | smart-0ce7ce33-485d-4aab-8d75-99ce9e4f0473 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4166601884 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 65.xbar_random_large_delays.4166601884 |
| Directory | /workspace/65.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/65.xbar_random_slow_rsp.2879692207 |
| Short name | T2780 |
| Test name | |
| Test status | |
| Simulation time | 35440516069 ps |
| CPU time | 578.6 seconds |
| Started | Jun 23 07:35:25 PM PDT 24 |
| Finished | Jun 23 07:45:04 PM PDT 24 |
| Peak memory | 573524 kb |
| Host | smart-f89c1878-5563-4ccb-9a48-16221de8c749 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2879692207 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 65.xbar_random_slow_rsp.2879692207 |
| Directory | /workspace/65.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/65.xbar_random_zero_delays.2538753721 |
| Short name | T2736 |
| Test name | |
| Test status | |
| Simulation time | 355465510 ps |
| CPU time | 27.68 seconds |
| Started | Jun 23 07:35:20 PM PDT 24 |
| Finished | Jun 23 07:35:48 PM PDT 24 |
| Peak memory | 573424 kb |
| Host | smart-c2029ef1-9832-4227-a7ba-819d7b88930d |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2538753721 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 65.xbar_random_zero_del ays.2538753721 |
| Directory | /workspace/65.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/65.xbar_same_source.1120437393 |
| Short name | T630 |
| Test name | |
| Test status | |
| Simulation time | 811599893 ps |
| CPU time | 23.71 seconds |
| Started | Jun 23 07:35:24 PM PDT 24 |
| Finished | Jun 23 07:35:48 PM PDT 24 |
| Peak memory | 574100 kb |
| Host | smart-023de33e-09ad-450d-a14b-49c35d58b8fd |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1120437393 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 65.xbar_same_source.1120437393 |
| Directory | /workspace/65.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/65.xbar_smoke.2613308541 |
| Short name | T1471 |
| Test name | |
| Test status | |
| Simulation time | 192532792 ps |
| CPU time | 8.79 seconds |
| Started | Jun 23 07:35:20 PM PDT 24 |
| Finished | Jun 23 07:35:29 PM PDT 24 |
| Peak memory | 565476 kb |
| Host | smart-670c7d6f-5ede-4e06-888a-0628ffaa1b96 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2613308541 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 65.xbar_smoke.2613308541 |
| Directory | /workspace/65.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/65.xbar_smoke_large_delays.3638832494 |
| Short name | T2810 |
| Test name | |
| Test status | |
| Simulation time | 9906828490 ps |
| CPU time | 101.12 seconds |
| Started | Jun 23 07:35:24 PM PDT 24 |
| Finished | Jun 23 07:37:05 PM PDT 24 |
| Peak memory | 565920 kb |
| Host | smart-336a1b9e-e584-40a9-b181-c7981b7e7a43 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3638832494 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 65.xbar_smoke_large_delays.3638832494 |
| Directory | /workspace/65.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/65.xbar_smoke_slow_rsp.3352361686 |
| Short name | T2014 |
| Test name | |
| Test status | |
| Simulation time | 6418978853 ps |
| CPU time | 100.56 seconds |
| Started | Jun 23 07:35:27 PM PDT 24 |
| Finished | Jun 23 07:37:07 PM PDT 24 |
| Peak memory | 573420 kb |
| Host | smart-660701d2-1ea4-4923-9b4a-bbac152f5217 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3352361686 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 65.xbar_smoke_slow_rsp.3352361686 |
| Directory | /workspace/65.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/65.xbar_smoke_zero_delays.2133457506 |
| Short name | T1686 |
| Test name | |
| Test status | |
| Simulation time | 52158403 ps |
| CPU time | 6.24 seconds |
| Started | Jun 23 07:35:25 PM PDT 24 |
| Finished | Jun 23 07:35:32 PM PDT 24 |
| Peak memory | 565532 kb |
| Host | smart-fbc012b6-3f7a-443d-83ee-8a7812583c1b |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2133457506 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 65.xbar_smoke_zero_delay s.2133457506 |
| Directory | /workspace/65.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/65.xbar_stress_all.3135422626 |
| Short name | T2449 |
| Test name | |
| Test status | |
| Simulation time | 16902499001 ps |
| CPU time | 567.28 seconds |
| Started | Jun 23 07:35:34 PM PDT 24 |
| Finished | Jun 23 07:45:02 PM PDT 24 |
| Peak memory | 574308 kb |
| Host | smart-e693fcb6-5301-4919-8a88-4bcfed5fe601 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3135422626 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 65.xbar_stress_all.3135422626 |
| Directory | /workspace/65.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/65.xbar_stress_all_with_error.1287406159 |
| Short name | T878 |
| Test name | |
| Test status | |
| Simulation time | 15660869853 ps |
| CPU time | 574.58 seconds |
| Started | Jun 23 07:35:26 PM PDT 24 |
| Finished | Jun 23 07:45:01 PM PDT 24 |
| Peak memory | 574296 kb |
| Host | smart-6b718523-2464-4c70-b864-775dabbda515 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1287406159 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 65.xbar_stress_all_with_error.1287406159 |
| Directory | /workspace/65.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/65.xbar_stress_all_with_rand_reset.820832420 |
| Short name | T2359 |
| Test name | |
| Test status | |
| Simulation time | 5864993125 ps |
| CPU time | 289.35 seconds |
| Started | Jun 23 07:35:26 PM PDT 24 |
| Finished | Jun 23 07:40:16 PM PDT 24 |
| Peak memory | 576332 kb |
| Host | smart-f8bdf3ca-98b2-45d7-af79-b40c0cbb03ae |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=820832420 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_res et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 65.xbar_stress_all_ with_rand_reset.820832420 |
| Directory | /workspace/65.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/65.xbar_stress_all_with_reset_error.1227625813 |
| Short name | T2132 |
| Test name | |
| Test status | |
| Simulation time | 19842098556 ps |
| CPU time | 943.43 seconds |
| Started | Jun 23 07:35:34 PM PDT 24 |
| Finished | Jun 23 07:51:18 PM PDT 24 |
| Peak memory | 576912 kb |
| Host | smart-ceeec81b-a423-458e-bf2b-688f055d3592 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1227625813 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 65.xbar_stress_al l_with_reset_error.1227625813 |
| Directory | /workspace/65.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/65.xbar_unmapped_addr.1651272191 |
| Short name | T2221 |
| Test name | |
| Test status | |
| Simulation time | 231153488 ps |
| CPU time | 30.09 seconds |
| Started | Jun 23 07:35:29 PM PDT 24 |
| Finished | Jun 23 07:35:59 PM PDT 24 |
| Peak memory | 574120 kb |
| Host | smart-75780949-850c-44f7-875f-8812d7fc29c6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1651272191 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 65.xbar_unmapped_addr.1651272191 |
| Directory | /workspace/65.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/66.xbar_access_same_device.614109404 |
| Short name | T509 |
| Test name | |
| Test status | |
| Simulation time | 3308314125 ps |
| CPU time | 130.01 seconds |
| Started | Jun 23 07:35:41 PM PDT 24 |
| Finished | Jun 23 07:37:52 PM PDT 24 |
| Peak memory | 574108 kb |
| Host | smart-74d07235-fa7a-422b-b096-e423f2804efa |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=614109404 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 66.xbar_access_same_device. 614109404 |
| Directory | /workspace/66.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/66.xbar_access_same_device_slow_rsp.889048490 |
| Short name | T2423 |
| Test name | |
| Test status | |
| Simulation time | 111203512037 ps |
| CPU time | 2037.81 seconds |
| Started | Jun 23 07:35:41 PM PDT 24 |
| Finished | Jun 23 08:09:39 PM PDT 24 |
| Peak memory | 574296 kb |
| Host | smart-02ac10ec-0954-4c6e-aee1-0d6a24047c02 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=889048490 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 66.xbar_access_same_d evice_slow_rsp.889048490 |
| Directory | /workspace/66.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/66.xbar_error_and_unmapped_addr.1056600306 |
| Short name | T1890 |
| Test name | |
| Test status | |
| Simulation time | 1173897300 ps |
| CPU time | 47.14 seconds |
| Started | Jun 23 07:35:43 PM PDT 24 |
| Finished | Jun 23 07:36:30 PM PDT 24 |
| Peak memory | 573736 kb |
| Host | smart-455dec11-92e3-485d-bad7-086ea1e66d88 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1056600306 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 66.xbar_error_and_unmapped_add r.1056600306 |
| Directory | /workspace/66.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/66.xbar_error_random.1394104230 |
| Short name | T1367 |
| Test name | |
| Test status | |
| Simulation time | 296780321 ps |
| CPU time | 27.17 seconds |
| Started | Jun 23 07:35:42 PM PDT 24 |
| Finished | Jun 23 07:36:10 PM PDT 24 |
| Peak memory | 573728 kb |
| Host | smart-03a8699f-dd92-4872-9675-52874c4dbb2c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1394104230 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 66.xbar_error_random.1394104230 |
| Directory | /workspace/66.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/66.xbar_random.251988215 |
| Short name | T2409 |
| Test name | |
| Test status | |
| Simulation time | 350525825 ps |
| CPU time | 27.16 seconds |
| Started | Jun 23 07:35:27 PM PDT 24 |
| Finished | Jun 23 07:35:55 PM PDT 24 |
| Peak memory | 574112 kb |
| Host | smart-6f8b1a5d-695b-4af8-8bdd-f559df1e03f6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=251988215 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 66.xbar_random.251988215 |
| Directory | /workspace/66.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/66.xbar_random_large_delays.2181339225 |
| Short name | T1915 |
| Test name | |
| Test status | |
| Simulation time | 103091012307 ps |
| CPU time | 1188.41 seconds |
| Started | Jun 23 07:35:42 PM PDT 24 |
| Finished | Jun 23 07:55:30 PM PDT 24 |
| Peak memory | 574248 kb |
| Host | smart-2e9d9e5b-6789-4732-ad5d-468f395ef068 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2181339225 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 66.xbar_random_large_delays.2181339225 |
| Directory | /workspace/66.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/66.xbar_random_slow_rsp.4215159963 |
| Short name | T1941 |
| Test name | |
| Test status | |
| Simulation time | 25733174756 ps |
| CPU time | 430.55 seconds |
| Started | Jun 23 07:35:40 PM PDT 24 |
| Finished | Jun 23 07:42:51 PM PDT 24 |
| Peak memory | 574200 kb |
| Host | smart-0dc143ad-95dc-4f3c-a754-9383a152f3a9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4215159963 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 66.xbar_random_slow_rsp.4215159963 |
| Directory | /workspace/66.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/66.xbar_random_zero_delays.509374983 |
| Short name | T2357 |
| Test name | |
| Test status | |
| Simulation time | 121645514 ps |
| CPU time | 12.74 seconds |
| Started | Jun 23 07:35:25 PM PDT 24 |
| Finished | Jun 23 07:35:38 PM PDT 24 |
| Peak memory | 573420 kb |
| Host | smart-82c3bbbd-be3c-4bf2-9f74-765fb0a39f8e |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=509374983 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 66.xbar_random_zero_dela ys.509374983 |
| Directory | /workspace/66.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/66.xbar_same_source.1383533223 |
| Short name | T487 |
| Test name | |
| Test status | |
| Simulation time | 916787735 ps |
| CPU time | 25.45 seconds |
| Started | Jun 23 07:35:41 PM PDT 24 |
| Finished | Jun 23 07:36:07 PM PDT 24 |
| Peak memory | 573368 kb |
| Host | smart-3f0d03b4-2b08-4345-80af-d54e47f65b46 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1383533223 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 66.xbar_same_source.1383533223 |
| Directory | /workspace/66.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/66.xbar_smoke.355474179 |
| Short name | T1451 |
| Test name | |
| Test status | |
| Simulation time | 48892453 ps |
| CPU time | 6.53 seconds |
| Started | Jun 23 07:35:45 PM PDT 24 |
| Finished | Jun 23 07:35:51 PM PDT 24 |
| Peak memory | 565496 kb |
| Host | smart-6333cfcb-a6c8-49ef-8228-6f3a9e466ffd |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=355474179 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 66.xbar_smoke.355474179 |
| Directory | /workspace/66.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/66.xbar_smoke_large_delays.2370312552 |
| Short name | T1411 |
| Test name | |
| Test status | |
| Simulation time | 7769432763 ps |
| CPU time | 88.65 seconds |
| Started | Jun 23 07:35:29 PM PDT 24 |
| Finished | Jun 23 07:36:58 PM PDT 24 |
| Peak memory | 565268 kb |
| Host | smart-7ddafeed-f7f3-44ef-96a0-fb1d60fa192e |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2370312552 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 66.xbar_smoke_large_delays.2370312552 |
| Directory | /workspace/66.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/66.xbar_smoke_slow_rsp.4090981633 |
| Short name | T2054 |
| Test name | |
| Test status | |
| Simulation time | 5325232295 ps |
| CPU time | 84.09 seconds |
| Started | Jun 23 07:35:34 PM PDT 24 |
| Finished | Jun 23 07:36:59 PM PDT 24 |
| Peak memory | 565552 kb |
| Host | smart-848e6d60-3ee8-4ef2-8aa9-8c7d65f75d53 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4090981633 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 66.xbar_smoke_slow_rsp.4090981633 |
| Directory | /workspace/66.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/66.xbar_smoke_zero_delays.466996883 |
| Short name | T1640 |
| Test name | |
| Test status | |
| Simulation time | 44197259 ps |
| CPU time | 5.92 seconds |
| Started | Jun 23 07:35:34 PM PDT 24 |
| Finished | Jun 23 07:35:40 PM PDT 24 |
| Peak memory | 565468 kb |
| Host | smart-e1cb6fa0-0ed9-4b73-b8c8-6a590783d138 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=466996883 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 66.xbar_smoke_zero_delays .466996883 |
| Directory | /workspace/66.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/66.xbar_stress_all.1082654870 |
| Short name | T613 |
| Test name | |
| Test status | |
| Simulation time | 2669808608 ps |
| CPU time | 205.34 seconds |
| Started | Jun 23 07:35:44 PM PDT 24 |
| Finished | Jun 23 07:39:10 PM PDT 24 |
| Peak memory | 574300 kb |
| Host | smart-c7f6fefe-26dc-4afa-9836-e51153597c42 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1082654870 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 66.xbar_stress_all.1082654870 |
| Directory | /workspace/66.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/66.xbar_stress_all_with_error.65481960 |
| Short name | T2496 |
| Test name | |
| Test status | |
| Simulation time | 4940358856 ps |
| CPU time | 334.49 seconds |
| Started | Jun 23 07:35:46 PM PDT 24 |
| Finished | Jun 23 07:41:21 PM PDT 24 |
| Peak memory | 574368 kb |
| Host | smart-c9af9a9e-1e37-4c33-9ae8-dc34fe6321f5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65481960 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 66.xbar_stress_all_with_error.65481960 |
| Directory | /workspace/66.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/66.xbar_stress_all_with_rand_reset.4269851343 |
| Short name | T2524 |
| Test name | |
| Test status | |
| Simulation time | 7914453 ps |
| CPU time | 13.52 seconds |
| Started | Jun 23 07:35:45 PM PDT 24 |
| Finished | Jun 23 07:35:59 PM PDT 24 |
| Peak memory | 565176 kb |
| Host | smart-638d81f6-6288-4ccd-b1d8-7949421884bf |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4269851343 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 66.xbar_stress_all _with_rand_reset.4269851343 |
| Directory | /workspace/66.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/66.xbar_stress_all_with_reset_error.538397833 |
| Short name | T1742 |
| Test name | |
| Test status | |
| Simulation time | 745462377 ps |
| CPU time | 242.54 seconds |
| Started | Jun 23 07:35:45 PM PDT 24 |
| Finished | Jun 23 07:39:48 PM PDT 24 |
| Peak memory | 574312 kb |
| Host | smart-25828122-e1b7-4833-8378-8840e5441d0d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=538397833 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 66.xbar_stress_all _with_reset_error.538397833 |
| Directory | /workspace/66.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/66.xbar_unmapped_addr.879937934 |
| Short name | T2692 |
| Test name | |
| Test status | |
| Simulation time | 280863402 ps |
| CPU time | 32.62 seconds |
| Started | Jun 23 07:35:42 PM PDT 24 |
| Finished | Jun 23 07:36:15 PM PDT 24 |
| Peak memory | 574116 kb |
| Host | smart-3ace4daa-6a0a-4304-b30e-64844308317a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=879937934 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 66.xbar_unmapped_addr.879937934 |
| Directory | /workspace/66.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/67.xbar_access_same_device.1249667296 |
| Short name | T1512 |
| Test name | |
| Test status | |
| Simulation time | 584444121 ps |
| CPU time | 45.68 seconds |
| Started | Jun 23 07:35:45 PM PDT 24 |
| Finished | Jun 23 07:36:31 PM PDT 24 |
| Peak memory | 574132 kb |
| Host | smart-8e55d094-a9ef-4455-b8e9-b7c2a2ff86b1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1249667296 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 67.xbar_access_same_device .1249667296 |
| Directory | /workspace/67.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/67.xbar_access_same_device_slow_rsp.2215434305 |
| Short name | T1935 |
| Test name | |
| Test status | |
| Simulation time | 89635140623 ps |
| CPU time | 1650.06 seconds |
| Started | Jun 23 07:35:48 PM PDT 24 |
| Finished | Jun 23 08:03:19 PM PDT 24 |
| Peak memory | 574244 kb |
| Host | smart-3fda417b-e91f-4a26-8d51-64d47c8a7275 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2215434305 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 67.xbar_access_same_ device_slow_rsp.2215434305 |
| Directory | /workspace/67.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/67.xbar_error_and_unmapped_addr.1219377027 |
| Short name | T1446 |
| Test name | |
| Test status | |
| Simulation time | 86530731 ps |
| CPU time | 12.1 seconds |
| Started | Jun 23 07:35:53 PM PDT 24 |
| Finished | Jun 23 07:36:06 PM PDT 24 |
| Peak memory | 573320 kb |
| Host | smart-f8de90e6-5987-4f10-8902-ff0d48be32f0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1219377027 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 67.xbar_error_and_unmapped_add r.1219377027 |
| Directory | /workspace/67.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/67.xbar_error_random.2619477732 |
| Short name | T1829 |
| Test name | |
| Test status | |
| Simulation time | 121615449 ps |
| CPU time | 12.41 seconds |
| Started | Jun 23 07:35:52 PM PDT 24 |
| Finished | Jun 23 07:36:05 PM PDT 24 |
| Peak memory | 573724 kb |
| Host | smart-6be71b3f-0b02-4241-8416-6a4acd518ead |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2619477732 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 67.xbar_error_random.2619477732 |
| Directory | /workspace/67.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/67.xbar_random.3505501983 |
| Short name | T1766 |
| Test name | |
| Test status | |
| Simulation time | 2597150180 ps |
| CPU time | 93.55 seconds |
| Started | Jun 23 07:35:49 PM PDT 24 |
| Finished | Jun 23 07:37:22 PM PDT 24 |
| Peak memory | 574204 kb |
| Host | smart-ced35b27-642b-4c1e-a07f-f47c7fcc408e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3505501983 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 67.xbar_random.3505501983 |
| Directory | /workspace/67.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/67.xbar_random_large_delays.1383614074 |
| Short name | T2070 |
| Test name | |
| Test status | |
| Simulation time | 67316731543 ps |
| CPU time | 692.62 seconds |
| Started | Jun 23 07:35:47 PM PDT 24 |
| Finished | Jun 23 07:47:20 PM PDT 24 |
| Peak memory | 574212 kb |
| Host | smart-b93085a6-c270-4913-835d-4e09c82c3e22 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1383614074 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 67.xbar_random_large_delays.1383614074 |
| Directory | /workspace/67.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/67.xbar_random_slow_rsp.3827563738 |
| Short name | T1630 |
| Test name | |
| Test status | |
| Simulation time | 23678922818 ps |
| CPU time | 428.17 seconds |
| Started | Jun 23 07:35:46 PM PDT 24 |
| Finished | Jun 23 07:42:54 PM PDT 24 |
| Peak memory | 573488 kb |
| Host | smart-37fd1526-2197-42fa-af76-7dac11aa58e7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3827563738 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 67.xbar_random_slow_rsp.3827563738 |
| Directory | /workspace/67.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/67.xbar_random_zero_delays.1299020390 |
| Short name | T2829 |
| Test name | |
| Test status | |
| Simulation time | 165827333 ps |
| CPU time | 16.22 seconds |
| Started | Jun 23 07:35:46 PM PDT 24 |
| Finished | Jun 23 07:36:03 PM PDT 24 |
| Peak memory | 574052 kb |
| Host | smart-4a87f23e-a558-4ab3-9f12-dae8086ccc5f |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1299020390 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 67.xbar_random_zero_del ays.1299020390 |
| Directory | /workspace/67.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/67.xbar_same_source.3098261748 |
| Short name | T2627 |
| Test name | |
| Test status | |
| Simulation time | 119442102 ps |
| CPU time | 10.19 seconds |
| Started | Jun 23 07:35:47 PM PDT 24 |
| Finished | Jun 23 07:35:58 PM PDT 24 |
| Peak memory | 574096 kb |
| Host | smart-f330c457-5b9b-4daa-8666-f3915cc2d729 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3098261748 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 67.xbar_same_source.3098261748 |
| Directory | /workspace/67.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/67.xbar_smoke.535445093 |
| Short name | T1578 |
| Test name | |
| Test status | |
| Simulation time | 183594929 ps |
| CPU time | 8.56 seconds |
| Started | Jun 23 07:35:46 PM PDT 24 |
| Finished | Jun 23 07:35:55 PM PDT 24 |
| Peak memory | 565476 kb |
| Host | smart-b972150a-ed37-4183-99fa-5d95566cb481 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=535445093 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 67.xbar_smoke.535445093 |
| Directory | /workspace/67.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/67.xbar_smoke_large_delays.7768009 |
| Short name | T664 |
| Test name | |
| Test status | |
| Simulation time | 7530940024 ps |
| CPU time | 80.13 seconds |
| Started | Jun 23 07:35:45 PM PDT 24 |
| Finished | Jun 23 07:37:06 PM PDT 24 |
| Peak memory | 565916 kb |
| Host | smart-d79d00d8-fedc-425b-848b-8385a148a88a |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=7768009 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 67.xbar_smoke_large_delays.7768009 |
| Directory | /workspace/67.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/67.xbar_smoke_slow_rsp.2385644061 |
| Short name | T2342 |
| Test name | |
| Test status | |
| Simulation time | 3477287707 ps |
| CPU time | 60.88 seconds |
| Started | Jun 23 07:35:46 PM PDT 24 |
| Finished | Jun 23 07:36:47 PM PDT 24 |
| Peak memory | 565236 kb |
| Host | smart-0c4a07d4-ef84-40a6-840e-335dda62ab4c |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2385644061 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 67.xbar_smoke_slow_rsp.2385644061 |
| Directory | /workspace/67.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/67.xbar_smoke_zero_delays.2132788241 |
| Short name | T2566 |
| Test name | |
| Test status | |
| Simulation time | 46414398 ps |
| CPU time | 6.36 seconds |
| Started | Jun 23 07:35:47 PM PDT 24 |
| Finished | Jun 23 07:35:54 PM PDT 24 |
| Peak memory | 565156 kb |
| Host | smart-5400809c-ba1a-42bd-a015-5bc252ea8614 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2132788241 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 67.xbar_smoke_zero_delay s.2132788241 |
| Directory | /workspace/67.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/67.xbar_stress_all.3302664619 |
| Short name | T435 |
| Test name | |
| Test status | |
| Simulation time | 2403581012 ps |
| CPU time | 202.22 seconds |
| Started | Jun 23 07:35:51 PM PDT 24 |
| Finished | Jun 23 07:39:14 PM PDT 24 |
| Peak memory | 574276 kb |
| Host | smart-947b321c-4247-4a48-ad56-42fc1ff7f924 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3302664619 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 67.xbar_stress_all.3302664619 |
| Directory | /workspace/67.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/67.xbar_stress_all_with_error.1310578077 |
| Short name | T870 |
| Test name | |
| Test status | |
| Simulation time | 16012521601 ps |
| CPU time | 617.88 seconds |
| Started | Jun 23 07:35:54 PM PDT 24 |
| Finished | Jun 23 07:46:13 PM PDT 24 |
| Peak memory | 574376 kb |
| Host | smart-8bae152b-f6b0-4ff4-b345-75cd283085bb |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1310578077 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 67.xbar_stress_all_with_error.1310578077 |
| Directory | /workspace/67.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/67.xbar_stress_all_with_rand_reset.817185467 |
| Short name | T2474 |
| Test name | |
| Test status | |
| Simulation time | 497353424 ps |
| CPU time | 160.93 seconds |
| Started | Jun 23 07:35:50 PM PDT 24 |
| Finished | Jun 23 07:38:31 PM PDT 24 |
| Peak memory | 575256 kb |
| Host | smart-b6f400bc-dd01-412d-8645-ecd488cd2e34 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=817185467 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_res et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 67.xbar_stress_all_ with_rand_reset.817185467 |
| Directory | /workspace/67.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/67.xbar_stress_all_with_reset_error.2379303623 |
| Short name | T2163 |
| Test name | |
| Test status | |
| Simulation time | 8867162568 ps |
| CPU time | 624.16 seconds |
| Started | Jun 23 07:35:51 PM PDT 24 |
| Finished | Jun 23 07:46:15 PM PDT 24 |
| Peak memory | 577412 kb |
| Host | smart-79b2d66e-c82b-4390-95d5-1fc84104ba8d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2379303623 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 67.xbar_stress_al l_with_reset_error.2379303623 |
| Directory | /workspace/67.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/67.xbar_unmapped_addr.3903703198 |
| Short name | T1394 |
| Test name | |
| Test status | |
| Simulation time | 813397876 ps |
| CPU time | 31.91 seconds |
| Started | Jun 23 07:35:50 PM PDT 24 |
| Finished | Jun 23 07:36:23 PM PDT 24 |
| Peak memory | 574128 kb |
| Host | smart-3b95c27a-1113-4373-b135-fa100340466a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3903703198 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 67.xbar_unmapped_addr.3903703198 |
| Directory | /workspace/67.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/68.xbar_access_same_device.1565858785 |
| Short name | T1386 |
| Test name | |
| Test status | |
| Simulation time | 340218903 ps |
| CPU time | 18.18 seconds |
| Started | Jun 23 07:35:55 PM PDT 24 |
| Finished | Jun 23 07:36:14 PM PDT 24 |
| Peak memory | 573772 kb |
| Host | smart-71fc18d1-ee38-462e-88fa-7df63a16618b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1565858785 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 68.xbar_access_same_device .1565858785 |
| Directory | /workspace/68.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/68.xbar_access_same_device_slow_rsp.3380797160 |
| Short name | T858 |
| Test name | |
| Test status | |
| Simulation time | 40837329959 ps |
| CPU time | 720.68 seconds |
| Started | Jun 23 07:35:57 PM PDT 24 |
| Finished | Jun 23 07:47:58 PM PDT 24 |
| Peak memory | 573448 kb |
| Host | smart-6728abda-08b2-40a7-9280-28780bdb8016 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3380797160 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 68.xbar_access_same_ device_slow_rsp.3380797160 |
| Directory | /workspace/68.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/68.xbar_error_and_unmapped_addr.2179642418 |
| Short name | T2420 |
| Test name | |
| Test status | |
| Simulation time | 1121295067 ps |
| CPU time | 46.14 seconds |
| Started | Jun 23 07:35:56 PM PDT 24 |
| Finished | Jun 23 07:36:42 PM PDT 24 |
| Peak memory | 573392 kb |
| Host | smart-bacc5325-2f24-49d6-bab5-380b82ae0661 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2179642418 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 68.xbar_error_and_unmapped_add r.2179642418 |
| Directory | /workspace/68.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/68.xbar_error_random.212589876 |
| Short name | T2859 |
| Test name | |
| Test status | |
| Simulation time | 1260976834 ps |
| CPU time | 45.63 seconds |
| Started | Jun 23 07:35:57 PM PDT 24 |
| Finished | Jun 23 07:36:43 PM PDT 24 |
| Peak memory | 573372 kb |
| Host | smart-45794695-d472-49af-bf6d-7956a0b8bfd3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=212589876 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 68.xbar_error_random.212589876 |
| Directory | /workspace/68.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/68.xbar_random.4261661580 |
| Short name | T2506 |
| Test name | |
| Test status | |
| Simulation time | 485624654 ps |
| CPU time | 42.54 seconds |
| Started | Jun 23 07:35:54 PM PDT 24 |
| Finished | Jun 23 07:36:37 PM PDT 24 |
| Peak memory | 574120 kb |
| Host | smart-e5279a1e-d3b2-42ce-8179-7eba0cb84f3b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4261661580 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 68.xbar_random.4261661580 |
| Directory | /workspace/68.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/68.xbar_random_large_delays.2755541488 |
| Short name | T1470 |
| Test name | |
| Test status | |
| Simulation time | 97624398431 ps |
| CPU time | 939.6 seconds |
| Started | Jun 23 07:35:54 PM PDT 24 |
| Finished | Jun 23 07:51:34 PM PDT 24 |
| Peak memory | 574232 kb |
| Host | smart-f0056eab-129a-4a22-9c66-080002e52ca2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2755541488 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 68.xbar_random_large_delays.2755541488 |
| Directory | /workspace/68.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/68.xbar_random_slow_rsp.2101291026 |
| Short name | T1900 |
| Test name | |
| Test status | |
| Simulation time | 63825334117 ps |
| CPU time | 1152.62 seconds |
| Started | Jun 23 07:35:54 PM PDT 24 |
| Finished | Jun 23 07:55:08 PM PDT 24 |
| Peak memory | 573480 kb |
| Host | smart-1effaa87-3994-407f-9d35-fb2d4187b740 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2101291026 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 68.xbar_random_slow_rsp.2101291026 |
| Directory | /workspace/68.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/68.xbar_random_zero_delays.879687246 |
| Short name | T2520 |
| Test name | |
| Test status | |
| Simulation time | 357241163 ps |
| CPU time | 32.42 seconds |
| Started | Jun 23 07:35:53 PM PDT 24 |
| Finished | Jun 23 07:36:26 PM PDT 24 |
| Peak memory | 573356 kb |
| Host | smart-392a231d-6023-466d-833a-91562030db37 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=879687246 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 68.xbar_random_zero_dela ys.879687246 |
| Directory | /workspace/68.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/68.xbar_same_source.2011451732 |
| Short name | T2458 |
| Test name | |
| Test status | |
| Simulation time | 2327789855 ps |
| CPU time | 70.87 seconds |
| Started | Jun 23 07:35:57 PM PDT 24 |
| Finished | Jun 23 07:37:08 PM PDT 24 |
| Peak memory | 573576 kb |
| Host | smart-52303fcc-99c5-4f5e-a0f4-81f890e7389a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2011451732 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 68.xbar_same_source.2011451732 |
| Directory | /workspace/68.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/68.xbar_smoke.2347124354 |
| Short name | T513 |
| Test name | |
| Test status | |
| Simulation time | 215811514 ps |
| CPU time | 8.81 seconds |
| Started | Jun 23 07:35:51 PM PDT 24 |
| Finished | Jun 23 07:36:00 PM PDT 24 |
| Peak memory | 565444 kb |
| Host | smart-b0d99ca0-2c13-425b-87e1-d4753a4e9e45 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2347124354 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 68.xbar_smoke.2347124354 |
| Directory | /workspace/68.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/68.xbar_smoke_large_delays.4294843660 |
| Short name | T1688 |
| Test name | |
| Test status | |
| Simulation time | 9816516456 ps |
| CPU time | 102.97 seconds |
| Started | Jun 23 07:35:53 PM PDT 24 |
| Finished | Jun 23 07:37:37 PM PDT 24 |
| Peak memory | 565920 kb |
| Host | smart-fedf1349-b136-4671-9d8d-fc1478c58dc2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4294843660 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 68.xbar_smoke_large_delays.4294843660 |
| Directory | /workspace/68.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/68.xbar_smoke_slow_rsp.1368831203 |
| Short name | T2577 |
| Test name | |
| Test status | |
| Simulation time | 5474369168 ps |
| CPU time | 94.52 seconds |
| Started | Jun 23 07:35:50 PM PDT 24 |
| Finished | Jun 23 07:37:25 PM PDT 24 |
| Peak memory | 573736 kb |
| Host | smart-326e5dfd-34e4-440e-9b12-c5396cc93fde |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1368831203 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 68.xbar_smoke_slow_rsp.1368831203 |
| Directory | /workspace/68.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/68.xbar_smoke_zero_delays.3615102000 |
| Short name | T2599 |
| Test name | |
| Test status | |
| Simulation time | 55675336 ps |
| CPU time | 7.03 seconds |
| Started | Jun 23 07:35:53 PM PDT 24 |
| Finished | Jun 23 07:36:01 PM PDT 24 |
| Peak memory | 565180 kb |
| Host | smart-622b20f7-c565-4605-8ea0-925fb6072077 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3615102000 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 68.xbar_smoke_zero_delay s.3615102000 |
| Directory | /workspace/68.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/68.xbar_stress_all.3090730271 |
| Short name | T442 |
| Test name | |
| Test status | |
| Simulation time | 13184221970 ps |
| CPU time | 465.15 seconds |
| Started | Jun 23 07:35:56 PM PDT 24 |
| Finished | Jun 23 07:43:42 PM PDT 24 |
| Peak memory | 574272 kb |
| Host | smart-459dd900-0d94-4750-bc2b-2b3cac4b5c28 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3090730271 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 68.xbar_stress_all.3090730271 |
| Directory | /workspace/68.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/68.xbar_stress_all_with_error.2506987127 |
| Short name | T2098 |
| Test name | |
| Test status | |
| Simulation time | 6099156331 ps |
| CPU time | 201.74 seconds |
| Started | Jun 23 07:36:00 PM PDT 24 |
| Finished | Jun 23 07:39:22 PM PDT 24 |
| Peak memory | 574284 kb |
| Host | smart-184b97b6-0fc9-46f2-9cf7-f1e1570773ae |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2506987127 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 68.xbar_stress_all_with_error.2506987127 |
| Directory | /workspace/68.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/68.xbar_stress_all_with_rand_reset.3723774240 |
| Short name | T498 |
| Test name | |
| Test status | |
| Simulation time | 3004086117 ps |
| CPU time | 491.92 seconds |
| Started | Jun 23 07:36:00 PM PDT 24 |
| Finished | Jun 23 07:44:13 PM PDT 24 |
| Peak memory | 574320 kb |
| Host | smart-3fba6d68-7e05-476f-8e6f-d64ed40b5d87 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3723774240 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 68.xbar_stress_all _with_rand_reset.3723774240 |
| Directory | /workspace/68.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/68.xbar_stress_all_with_reset_error.3773122042 |
| Short name | T1998 |
| Test name | |
| Test status | |
| Simulation time | 96188402 ps |
| CPU time | 31.61 seconds |
| Started | Jun 23 07:35:56 PM PDT 24 |
| Finished | Jun 23 07:36:27 PM PDT 24 |
| Peak memory | 574620 kb |
| Host | smart-e66dae31-693a-4d3e-b75d-e991f0d5c9ac |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3773122042 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 68.xbar_stress_al l_with_reset_error.3773122042 |
| Directory | /workspace/68.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/68.xbar_unmapped_addr.2585546439 |
| Short name | T1519 |
| Test name | |
| Test status | |
| Simulation time | 86213847 ps |
| CPU time | 7.01 seconds |
| Started | Jun 23 07:35:54 PM PDT 24 |
| Finished | Jun 23 07:36:01 PM PDT 24 |
| Peak memory | 565820 kb |
| Host | smart-8b91c925-00e6-4f3b-b282-2bb7a2d5d93f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2585546439 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 68.xbar_unmapped_addr.2585546439 |
| Directory | /workspace/68.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/69.xbar_access_same_device.4255520152 |
| Short name | T1874 |
| Test name | |
| Test status | |
| Simulation time | 4070499211 ps |
| CPU time | 147.88 seconds |
| Started | Jun 23 07:36:01 PM PDT 24 |
| Finished | Jun 23 07:38:29 PM PDT 24 |
| Peak memory | 573480 kb |
| Host | smart-73fef236-ed48-4b87-b117-190ad1758ccf |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4255520152 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 69.xbar_access_same_device .4255520152 |
| Directory | /workspace/69.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/69.xbar_access_same_device_slow_rsp.2028802924 |
| Short name | T2241 |
| Test name | |
| Test status | |
| Simulation time | 14689318913 ps |
| CPU time | 238.78 seconds |
| Started | Jun 23 07:36:16 PM PDT 24 |
| Finished | Jun 23 07:40:15 PM PDT 24 |
| Peak memory | 573508 kb |
| Host | smart-ac98b66f-179e-41e3-a917-00f9c08d4519 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2028802924 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 69.xbar_access_same_ device_slow_rsp.2028802924 |
| Directory | /workspace/69.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/69.xbar_error_and_unmapped_addr.1878216112 |
| Short name | T2503 |
| Test name | |
| Test status | |
| Simulation time | 666972986 ps |
| CPU time | 24.63 seconds |
| Started | Jun 23 07:36:13 PM PDT 24 |
| Finished | Jun 23 07:36:38 PM PDT 24 |
| Peak memory | 573328 kb |
| Host | smart-39d6b0fb-ea32-47a8-aeab-a39d3ac98598 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1878216112 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 69.xbar_error_and_unmapped_add r.1878216112 |
| Directory | /workspace/69.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/69.xbar_error_random.1724349738 |
| Short name | T2105 |
| Test name | |
| Test status | |
| Simulation time | 41642033 ps |
| CPU time | 6.5 seconds |
| Started | Jun 23 07:36:13 PM PDT 24 |
| Finished | Jun 23 07:36:19 PM PDT 24 |
| Peak memory | 573616 kb |
| Host | smart-6e8995cb-a1d4-427e-b7e5-0660f0187b01 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1724349738 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 69.xbar_error_random.1724349738 |
| Directory | /workspace/69.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/69.xbar_random.2615554271 |
| Short name | T579 |
| Test name | |
| Test status | |
| Simulation time | 171815495 ps |
| CPU time | 17.59 seconds |
| Started | Jun 23 07:36:04 PM PDT 24 |
| Finished | Jun 23 07:36:22 PM PDT 24 |
| Peak memory | 574120 kb |
| Host | smart-47eff360-8fe7-4225-ac5d-176e46a2ceee |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2615554271 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 69.xbar_random.2615554271 |
| Directory | /workspace/69.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/69.xbar_random_large_delays.3057252043 |
| Short name | T1734 |
| Test name | |
| Test status | |
| Simulation time | 99374056123 ps |
| CPU time | 1091.7 seconds |
| Started | Jun 23 07:36:01 PM PDT 24 |
| Finished | Jun 23 07:54:13 PM PDT 24 |
| Peak memory | 574224 kb |
| Host | smart-86f08387-5ad0-45b5-8ada-60a78cafa857 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3057252043 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 69.xbar_random_large_delays.3057252043 |
| Directory | /workspace/69.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/69.xbar_random_slow_rsp.3470643236 |
| Short name | T2138 |
| Test name | |
| Test status | |
| Simulation time | 22807979092 ps |
| CPU time | 403.95 seconds |
| Started | Jun 23 07:36:00 PM PDT 24 |
| Finished | Jun 23 07:42:44 PM PDT 24 |
| Peak memory | 574172 kb |
| Host | smart-94378ed9-a27d-4982-93a5-8769a2e19ebb |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3470643236 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 69.xbar_random_slow_rsp.3470643236 |
| Directory | /workspace/69.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/69.xbar_random_zero_delays.2798163522 |
| Short name | T1740 |
| Test name | |
| Test status | |
| Simulation time | 625345961 ps |
| CPU time | 50.05 seconds |
| Started | Jun 23 07:36:01 PM PDT 24 |
| Finished | Jun 23 07:36:51 PM PDT 24 |
| Peak memory | 574104 kb |
| Host | smart-925e7889-575f-4b4c-a900-aa4e9ed3b0bc |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2798163522 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 69.xbar_random_zero_del ays.2798163522 |
| Directory | /workspace/69.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/69.xbar_same_source.3949495262 |
| Short name | T2373 |
| Test name | |
| Test status | |
| Simulation time | 1320126740 ps |
| CPU time | 38.49 seconds |
| Started | Jun 23 07:36:13 PM PDT 24 |
| Finished | Jun 23 07:36:52 PM PDT 24 |
| Peak memory | 574044 kb |
| Host | smart-059d69a2-aa4c-4c07-a458-d5f84fd027ff |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3949495262 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 69.xbar_same_source.3949495262 |
| Directory | /workspace/69.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/69.xbar_smoke.483816942 |
| Short name | T2725 |
| Test name | |
| Test status | |
| Simulation time | 178684748 ps |
| CPU time | 7.66 seconds |
| Started | Jun 23 07:36:01 PM PDT 24 |
| Finished | Jun 23 07:36:09 PM PDT 24 |
| Peak memory | 565460 kb |
| Host | smart-dde5e0fe-80bf-4184-aa74-5a65ea0b04c4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=483816942 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 69.xbar_smoke.483816942 |
| Directory | /workspace/69.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/69.xbar_smoke_large_delays.3798973777 |
| Short name | T1963 |
| Test name | |
| Test status | |
| Simulation time | 5159143937 ps |
| CPU time | 52.88 seconds |
| Started | Jun 23 07:35:59 PM PDT 24 |
| Finished | Jun 23 07:36:52 PM PDT 24 |
| Peak memory | 565916 kb |
| Host | smart-ac3b7ef0-738c-46c7-9eff-2f8750940049 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3798973777 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 69.xbar_smoke_large_delays.3798973777 |
| Directory | /workspace/69.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/69.xbar_smoke_slow_rsp.417862569 |
| Short name | T1551 |
| Test name | |
| Test status | |
| Simulation time | 5626380945 ps |
| CPU time | 94.46 seconds |
| Started | Jun 23 07:36:04 PM PDT 24 |
| Finished | Jun 23 07:37:39 PM PDT 24 |
| Peak memory | 574128 kb |
| Host | smart-fb87d47a-02e9-46b5-a59d-14bd664f719c |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=417862569 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 69.xbar_smoke_slow_rsp.417862569 |
| Directory | /workspace/69.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/69.xbar_smoke_zero_delays.1940084963 |
| Short name | T1491 |
| Test name | |
| Test status | |
| Simulation time | 45121905 ps |
| CPU time | 6.74 seconds |
| Started | Jun 23 07:35:58 PM PDT 24 |
| Finished | Jun 23 07:36:05 PM PDT 24 |
| Peak memory | 565532 kb |
| Host | smart-955dfe58-c7f2-4465-b29a-c2e84d194cc9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1940084963 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 69.xbar_smoke_zero_delay s.1940084963 |
| Directory | /workspace/69.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/69.xbar_stress_all.2658584349 |
| Short name | T684 |
| Test name | |
| Test status | |
| Simulation time | 1082143641 ps |
| CPU time | 96.3 seconds |
| Started | Jun 23 07:36:13 PM PDT 24 |
| Finished | Jun 23 07:37:50 PM PDT 24 |
| Peak memory | 574256 kb |
| Host | smart-02c90879-41c5-43ae-8974-d0f50952777f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2658584349 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 69.xbar_stress_all.2658584349 |
| Directory | /workspace/69.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/69.xbar_stress_all_with_error.1465068627 |
| Short name | T1469 |
| Test name | |
| Test status | |
| Simulation time | 1440316444 ps |
| CPU time | 100.32 seconds |
| Started | Jun 23 07:36:14 PM PDT 24 |
| Finished | Jun 23 07:37:55 PM PDT 24 |
| Peak memory | 574292 kb |
| Host | smart-d79999ff-9742-4bda-8871-b90954ca7219 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1465068627 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 69.xbar_stress_all_with_error.1465068627 |
| Directory | /workspace/69.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/69.xbar_stress_all_with_reset_error.3476841878 |
| Short name | T2473 |
| Test name | |
| Test status | |
| Simulation time | 12754860 ps |
| CPU time | 6.54 seconds |
| Started | Jun 23 07:36:12 PM PDT 24 |
| Finished | Jun 23 07:36:19 PM PDT 24 |
| Peak memory | 574080 kb |
| Host | smart-bb135f81-ec61-4a42-99d8-9440616f9686 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3476841878 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 69.xbar_stress_al l_with_reset_error.3476841878 |
| Directory | /workspace/69.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/69.xbar_unmapped_addr.2996736956 |
| Short name | T546 |
| Test name | |
| Test status | |
| Simulation time | 1492921329 ps |
| CPU time | 67.66 seconds |
| Started | Jun 23 07:36:13 PM PDT 24 |
| Finished | Jun 23 07:37:22 PM PDT 24 |
| Peak memory | 574128 kb |
| Host | smart-3b8cbb38-0f66-431e-9c2e-1ec3b09d1437 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2996736956 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 69.xbar_unmapped_addr.2996736956 |
| Directory | /workspace/69.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/7.chip_csr_rw.3716615492 |
| Short name | T2762 |
| Test name | |
| Test status | |
| Simulation time | 4539974625 ps |
| CPU time | 334.63 seconds |
| Started | Jun 23 07:22:28 PM PDT 24 |
| Finished | Jun 23 07:28:03 PM PDT 24 |
| Peak memory | 595516 kb |
| Host | smart-8ad242fd-a9f6-432e-a368-6e6c1ef04c16 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3716615492 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.chip_csr_rw.3716615492 |
| Directory | /workspace/7.chip_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/7.chip_same_csr_outstanding.747298349 |
| Short name | T420 |
| Test name | |
| Test status | |
| Simulation time | 16615860758 ps |
| CPU time | 2280.56 seconds |
| Started | Jun 23 07:22:06 PM PDT 24 |
| Finished | Jun 23 08:00:07 PM PDT 24 |
| Peak memory | 589788 kb |
| Host | smart-1f8b9ae5-3e00-4d80-a7f9-758e1d89dcdd |
| User | root |
| Command | /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +run_same_csr_outstanding +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=747298349 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c m_log /dev/null -cm_name 7.chip_same_csr_outstanding.747298349 |
| Directory | /workspace/7.chip_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/7.xbar_access_same_device.4230256588 |
| Short name | T750 |
| Test name | |
| Test status | |
| Simulation time | 153032520 ps |
| CPU time | 10.74 seconds |
| Started | Jun 23 07:22:20 PM PDT 24 |
| Finished | Jun 23 07:22:31 PM PDT 24 |
| Peak memory | 573768 kb |
| Host | smart-c44725e3-a8ad-471e-aaa0-b0fd93bb648d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4230256588 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.xbar_access_same_device. 4230256588 |
| Directory | /workspace/7.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/7.xbar_access_same_device_slow_rsp.3268186451 |
| Short name | T862 |
| Test name | |
| Test status | |
| Simulation time | 9356259463 ps |
| CPU time | 153.08 seconds |
| Started | Jun 23 07:22:17 PM PDT 24 |
| Finished | Jun 23 07:24:51 PM PDT 24 |
| Peak memory | 565968 kb |
| Host | smart-8f3e9a7e-0a2a-4b26-828b-e513ddcddb14 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3268186451 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.xbar_access_same_d evice_slow_rsp.3268186451 |
| Directory | /workspace/7.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/7.xbar_error_and_unmapped_addr.149551779 |
| Short name | T2685 |
| Test name | |
| Test status | |
| Simulation time | 281391009 ps |
| CPU time | 30.25 seconds |
| Started | Jun 23 07:22:23 PM PDT 24 |
| Finished | Jun 23 07:22:54 PM PDT 24 |
| Peak memory | 573384 kb |
| Host | smart-fd92587a-9470-412e-9fc3-3cffee5146da |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=149551779 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.xbar_error_and_unmapped_addr. 149551779 |
| Directory | /workspace/7.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/7.xbar_error_random.8897727 |
| Short name | T2873 |
| Test name | |
| Test status | |
| Simulation time | 1774353820 ps |
| CPU time | 65.2 seconds |
| Started | Jun 23 07:22:25 PM PDT 24 |
| Finished | Jun 23 07:23:31 PM PDT 24 |
| Peak memory | 573352 kb |
| Host | smart-52b3cc9f-ebd4-4ca6-96cd-6e8a0e59bcd7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=8897727 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.xbar_error_random.8897727 |
| Directory | /workspace/7.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/7.xbar_random.3226166330 |
| Short name | T646 |
| Test name | |
| Test status | |
| Simulation time | 659022570 ps |
| CPU time | 21.21 seconds |
| Started | Jun 23 07:22:20 PM PDT 24 |
| Finished | Jun 23 07:22:42 PM PDT 24 |
| Peak memory | 574104 kb |
| Host | smart-cf4589c3-3c00-4c55-918b-3952cb64a004 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3226166330 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.xbar_random.3226166330 |
| Directory | /workspace/7.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/7.xbar_random_large_delays.1788912914 |
| Short name | T2640 |
| Test name | |
| Test status | |
| Simulation time | 75096510426 ps |
| CPU time | 753.98 seconds |
| Started | Jun 23 07:22:18 PM PDT 24 |
| Finished | Jun 23 07:34:52 PM PDT 24 |
| Peak memory | 573528 kb |
| Host | smart-c9a50b4d-a873-4ddf-9170-a94494b19f57 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1788912914 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.xbar_random_large_delays.1788912914 |
| Directory | /workspace/7.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/7.xbar_random_slow_rsp.2383244542 |
| Short name | T2340 |
| Test name | |
| Test status | |
| Simulation time | 67884031367 ps |
| CPU time | 1210.75 seconds |
| Started | Jun 23 07:22:16 PM PDT 24 |
| Finished | Jun 23 07:42:27 PM PDT 24 |
| Peak memory | 574192 kb |
| Host | smart-25ee5b8d-7b64-4efb-b654-ab1bf3136ad7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2383244542 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.xbar_random_slow_rsp.2383244542 |
| Directory | /workspace/7.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/7.xbar_random_zero_delays.3236209002 |
| Short name | T2643 |
| Test name | |
| Test status | |
| Simulation time | 253263497 ps |
| CPU time | 27.12 seconds |
| Started | Jun 23 07:22:17 PM PDT 24 |
| Finished | Jun 23 07:22:45 PM PDT 24 |
| Peak memory | 574088 kb |
| Host | smart-5e50192f-03c5-4011-9170-2acf61367efb |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3236209002 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.xbar_random_zero_dela ys.3236209002 |
| Directory | /workspace/7.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/7.xbar_same_source.725890667 |
| Short name | T541 |
| Test name | |
| Test status | |
| Simulation time | 479832045 ps |
| CPU time | 38.01 seconds |
| Started | Jun 23 07:22:23 PM PDT 24 |
| Finished | Jun 23 07:23:01 PM PDT 24 |
| Peak memory | 573704 kb |
| Host | smart-ba5ac70d-7f9a-4d54-b4f5-4bc94adeb71d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=725890667 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.xbar_same_source.725890667 |
| Directory | /workspace/7.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/7.xbar_smoke.960118872 |
| Short name | T1689 |
| Test name | |
| Test status | |
| Simulation time | 203731717 ps |
| CPU time | 10.14 seconds |
| Started | Jun 23 07:22:04 PM PDT 24 |
| Finished | Jun 23 07:22:14 PM PDT 24 |
| Peak memory | 565144 kb |
| Host | smart-3cb8eedf-e5b6-4bd7-87f2-25b2861c23d5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=960118872 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.xbar_smoke.960118872 |
| Directory | /workspace/7.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/7.xbar_smoke_large_delays.3272871854 |
| Short name | T427 |
| Test name | |
| Test status | |
| Simulation time | 8746043385 ps |
| CPU time | 93.32 seconds |
| Started | Jun 23 07:22:08 PM PDT 24 |
| Finished | Jun 23 07:23:41 PM PDT 24 |
| Peak memory | 574072 kb |
| Host | smart-a9cb87ee-c700-4bf7-8a04-3828de9ae67a |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3272871854 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.xbar_smoke_large_delays.3272871854 |
| Directory | /workspace/7.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/7.xbar_smoke_slow_rsp.312862433 |
| Short name | T2687 |
| Test name | |
| Test status | |
| Simulation time | 5112032903 ps |
| CPU time | 81.51 seconds |
| Started | Jun 23 07:22:08 PM PDT 24 |
| Finished | Jun 23 07:23:29 PM PDT 24 |
| Peak memory | 565912 kb |
| Host | smart-4f82a3c3-131d-41a3-9be6-73031f14a3bc |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=312862433 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.xbar_smoke_slow_rsp.312862433 |
| Directory | /workspace/7.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/7.xbar_smoke_zero_delays.3527921559 |
| Short name | T1881 |
| Test name | |
| Test status | |
| Simulation time | 45616053 ps |
| CPU time | 6.15 seconds |
| Started | Jun 23 07:22:03 PM PDT 24 |
| Finished | Jun 23 07:22:10 PM PDT 24 |
| Peak memory | 565176 kb |
| Host | smart-84c6ca47-765b-49bf-b503-c4f2041b0275 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3527921559 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.xbar_smoke_zero_delays .3527921559 |
| Directory | /workspace/7.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/7.xbar_stress_all.2086571225 |
| Short name | T2444 |
| Test name | |
| Test status | |
| Simulation time | 7606232484 ps |
| CPU time | 281.71 seconds |
| Started | Jun 23 07:22:24 PM PDT 24 |
| Finished | Jun 23 07:27:07 PM PDT 24 |
| Peak memory | 574268 kb |
| Host | smart-e826f4fe-7b95-4edd-98b1-a22399c12a9d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2086571225 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.xbar_stress_all.2086571225 |
| Directory | /workspace/7.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/7.xbar_stress_all_with_error.499025225 |
| Short name | T2186 |
| Test name | |
| Test status | |
| Simulation time | 3068572933 ps |
| CPU time | 270.9 seconds |
| Started | Jun 23 07:22:22 PM PDT 24 |
| Finished | Jun 23 07:26:53 PM PDT 24 |
| Peak memory | 574372 kb |
| Host | smart-7075f744-17fd-4a27-a18e-c5e9e94e2d0d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=499025225 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.xbar_stress_all_with_error.499025225 |
| Directory | /workspace/7.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/7.xbar_stress_all_with_rand_reset.3911409618 |
| Short name | T2587 |
| Test name | |
| Test status | |
| Simulation time | 668877849 ps |
| CPU time | 197.42 seconds |
| Started | Jun 23 07:22:25 PM PDT 24 |
| Finished | Jun 23 07:25:43 PM PDT 24 |
| Peak memory | 576296 kb |
| Host | smart-d2ed60dd-19b3-4d4e-b1c5-af41daf2e831 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3911409618 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.xbar_stress_all_ with_rand_reset.3911409618 |
| Directory | /workspace/7.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/7.xbar_stress_all_with_reset_error.3598903623 |
| Short name | T2686 |
| Test name | |
| Test status | |
| Simulation time | 414482747 ps |
| CPU time | 139.32 seconds |
| Started | Jun 23 07:22:34 PM PDT 24 |
| Finished | Jun 23 07:24:54 PM PDT 24 |
| Peak memory | 574272 kb |
| Host | smart-f51b4895-8645-4f9d-bb12-c0e216f376fb |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3598903623 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.xbar_stress_all _with_reset_error.3598903623 |
| Directory | /workspace/7.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/7.xbar_unmapped_addr.3773527444 |
| Short name | T2508 |
| Test name | |
| Test status | |
| Simulation time | 1467087749 ps |
| CPU time | 59.95 seconds |
| Started | Jun 23 07:22:24 PM PDT 24 |
| Finished | Jun 23 07:23:25 PM PDT 24 |
| Peak memory | 574188 kb |
| Host | smart-e667c15d-cfe7-4405-b2ef-59fd3984e039 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3773527444 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.xbar_unmapped_addr.3773527444 |
| Directory | /workspace/7.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/70.xbar_access_same_device.2605374631 |
| Short name | T1790 |
| Test name | |
| Test status | |
| Simulation time | 1373504848 ps |
| CPU time | 49.71 seconds |
| Started | Jun 23 07:36:21 PM PDT 24 |
| Finished | Jun 23 07:37:12 PM PDT 24 |
| Peak memory | 573580 kb |
| Host | smart-9ddea3f6-09ae-472a-a0ff-257c66797640 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2605374631 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 70.xbar_access_same_device .2605374631 |
| Directory | /workspace/70.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/70.xbar_access_same_device_slow_rsp.1653605338 |
| Short name | T1862 |
| Test name | |
| Test status | |
| Simulation time | 63362330174 ps |
| CPU time | 1157.36 seconds |
| Started | Jun 23 07:36:18 PM PDT 24 |
| Finished | Jun 23 07:55:36 PM PDT 24 |
| Peak memory | 574188 kb |
| Host | smart-6a6b875e-e7fc-4a9a-a928-2d9d8fcc80da |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1653605338 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 70.xbar_access_same_ device_slow_rsp.1653605338 |
| Directory | /workspace/70.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/70.xbar_error_and_unmapped_addr.3900027440 |
| Short name | T2797 |
| Test name | |
| Test status | |
| Simulation time | 169055227 ps |
| CPU time | 19.38 seconds |
| Started | Jun 23 07:36:19 PM PDT 24 |
| Finished | Jun 23 07:36:38 PM PDT 24 |
| Peak memory | 573728 kb |
| Host | smart-be04b46b-fc2d-4782-8e1f-9cccb147a590 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3900027440 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 70.xbar_error_and_unmapped_add r.3900027440 |
| Directory | /workspace/70.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/70.xbar_error_random.1636475414 |
| Short name | T2167 |
| Test name | |
| Test status | |
| Simulation time | 317325643 ps |
| CPU time | 26.99 seconds |
| Started | Jun 23 07:36:18 PM PDT 24 |
| Finished | Jun 23 07:36:45 PM PDT 24 |
| Peak memory | 573728 kb |
| Host | smart-51475946-6ace-4747-8991-e21e8d59f8fe |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1636475414 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 70.xbar_error_random.1636475414 |
| Directory | /workspace/70.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/70.xbar_random.1522290515 |
| Short name | T1597 |
| Test name | |
| Test status | |
| Simulation time | 333562788 ps |
| CPU time | 29.65 seconds |
| Started | Jun 23 07:36:21 PM PDT 24 |
| Finished | Jun 23 07:36:52 PM PDT 24 |
| Peak memory | 573596 kb |
| Host | smart-4c6ae06d-9411-48d9-acef-9529e93f8e24 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1522290515 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 70.xbar_random.1522290515 |
| Directory | /workspace/70.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/70.xbar_random_large_delays.1635181177 |
| Short name | T594 |
| Test name | |
| Test status | |
| Simulation time | 47664521672 ps |
| CPU time | 496.55 seconds |
| Started | Jun 23 07:36:17 PM PDT 24 |
| Finished | Jun 23 07:44:34 PM PDT 24 |
| Peak memory | 574152 kb |
| Host | smart-39f9d9b4-547c-46d8-b7ae-aec3cc3d25d1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1635181177 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 70.xbar_random_large_delays.1635181177 |
| Directory | /workspace/70.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/70.xbar_random_slow_rsp.2519119538 |
| Short name | T465 |
| Test name | |
| Test status | |
| Simulation time | 7482922594 ps |
| CPU time | 133.09 seconds |
| Started | Jun 23 07:36:20 PM PDT 24 |
| Finished | Jun 23 07:38:33 PM PDT 24 |
| Peak memory | 574168 kb |
| Host | smart-8f6bdfcd-39cc-4d39-9ee5-4956bbd943ee |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2519119538 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 70.xbar_random_slow_rsp.2519119538 |
| Directory | /workspace/70.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/70.xbar_random_zero_delays.3647204024 |
| Short name | T2588 |
| Test name | |
| Test status | |
| Simulation time | 154636532 ps |
| CPU time | 16.83 seconds |
| Started | Jun 23 07:36:17 PM PDT 24 |
| Finished | Jun 23 07:36:34 PM PDT 24 |
| Peak memory | 574060 kb |
| Host | smart-a4c3b3e5-ac36-4c55-aaec-cb148d1c1a36 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3647204024 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 70.xbar_random_zero_del ays.3647204024 |
| Directory | /workspace/70.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/70.xbar_same_source.3099044333 |
| Short name | T1755 |
| Test name | |
| Test status | |
| Simulation time | 271731901 ps |
| CPU time | 22.03 seconds |
| Started | Jun 23 07:36:17 PM PDT 24 |
| Finished | Jun 23 07:36:39 PM PDT 24 |
| Peak memory | 573308 kb |
| Host | smart-001314c8-e3fe-402d-b2b0-4e253cd68998 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3099044333 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 70.xbar_same_source.3099044333 |
| Directory | /workspace/70.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/70.xbar_smoke.1494286203 |
| Short name | T1645 |
| Test name | |
| Test status | |
| Simulation time | 220992145 ps |
| CPU time | 8.86 seconds |
| Started | Jun 23 07:36:13 PM PDT 24 |
| Finished | Jun 23 07:36:23 PM PDT 24 |
| Peak memory | 565860 kb |
| Host | smart-ac6802ea-6292-4536-bcff-b7dab9950607 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1494286203 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 70.xbar_smoke.1494286203 |
| Directory | /workspace/70.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/70.xbar_smoke_large_delays.3695383375 |
| Short name | T1899 |
| Test name | |
| Test status | |
| Simulation time | 6604667140 ps |
| CPU time | 65.23 seconds |
| Started | Jun 23 07:36:16 PM PDT 24 |
| Finished | Jun 23 07:37:21 PM PDT 24 |
| Peak memory | 565932 kb |
| Host | smart-2516b0a6-c12f-42cf-8761-4e1b7a7a6b45 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3695383375 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 70.xbar_smoke_large_delays.3695383375 |
| Directory | /workspace/70.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/70.xbar_smoke_slow_rsp.815486748 |
| Short name | T2036 |
| Test name | |
| Test status | |
| Simulation time | 5862935470 ps |
| CPU time | 97.51 seconds |
| Started | Jun 23 07:36:16 PM PDT 24 |
| Finished | Jun 23 07:37:54 PM PDT 24 |
| Peak memory | 565916 kb |
| Host | smart-1d7a95d4-40bb-4048-a8af-885577adbb29 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=815486748 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 70.xbar_smoke_slow_rsp.815486748 |
| Directory | /workspace/70.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/70.xbar_smoke_zero_delays.2641924712 |
| Short name | T1918 |
| Test name | |
| Test status | |
| Simulation time | 46192657 ps |
| CPU time | 6.04 seconds |
| Started | Jun 23 07:36:17 PM PDT 24 |
| Finished | Jun 23 07:36:23 PM PDT 24 |
| Peak memory | 565112 kb |
| Host | smart-6eac433d-a486-41d1-b0a3-c0479b7e4e57 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2641924712 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 70.xbar_smoke_zero_delay s.2641924712 |
| Directory | /workspace/70.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/70.xbar_stress_all.1005416950 |
| Short name | T2033 |
| Test name | |
| Test status | |
| Simulation time | 9568983486 ps |
| CPU time | 331.29 seconds |
| Started | Jun 23 07:36:18 PM PDT 24 |
| Finished | Jun 23 07:41:49 PM PDT 24 |
| Peak memory | 574076 kb |
| Host | smart-b5da9c85-6efc-4a8f-b4e4-1861f9123855 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1005416950 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 70.xbar_stress_all.1005416950 |
| Directory | /workspace/70.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/70.xbar_stress_all_with_error.2703577113 |
| Short name | T2113 |
| Test name | |
| Test status | |
| Simulation time | 10360884136 ps |
| CPU time | 403.07 seconds |
| Started | Jun 23 07:36:24 PM PDT 24 |
| Finished | Jun 23 07:43:07 PM PDT 24 |
| Peak memory | 574392 kb |
| Host | smart-f056aa7a-f486-4c40-acae-3ad752ed5335 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2703577113 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 70.xbar_stress_all_with_error.2703577113 |
| Directory | /workspace/70.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/70.xbar_stress_all_with_rand_reset.2052162083 |
| Short name | T440 |
| Test name | |
| Test status | |
| Simulation time | 13699579911 ps |
| CPU time | 711.53 seconds |
| Started | Jun 23 07:36:20 PM PDT 24 |
| Finished | Jun 23 07:48:12 PM PDT 24 |
| Peak memory | 576348 kb |
| Host | smart-a23ed490-aa1f-46f1-8704-4d26d5b67556 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2052162083 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 70.xbar_stress_all _with_rand_reset.2052162083 |
| Directory | /workspace/70.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/70.xbar_stress_all_with_reset_error.2112335469 |
| Short name | T2422 |
| Test name | |
| Test status | |
| Simulation time | 14676986698 ps |
| CPU time | 738.29 seconds |
| Started | Jun 23 07:36:26 PM PDT 24 |
| Finished | Jun 23 07:48:44 PM PDT 24 |
| Peak memory | 576432 kb |
| Host | smart-70c7da67-c1ca-49bb-992d-81476ed7768a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2112335469 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 70.xbar_stress_al l_with_reset_error.2112335469 |
| Directory | /workspace/70.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/70.xbar_unmapped_addr.2892842917 |
| Short name | T1673 |
| Test name | |
| Test status | |
| Simulation time | 1128549568 ps |
| CPU time | 43.8 seconds |
| Started | Jun 23 07:36:18 PM PDT 24 |
| Finished | Jun 23 07:37:02 PM PDT 24 |
| Peak memory | 573452 kb |
| Host | smart-4b8e6802-400f-402a-89ea-50d2a25c7498 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2892842917 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 70.xbar_unmapped_addr.2892842917 |
| Directory | /workspace/70.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/71.xbar_access_same_device.3427212624 |
| Short name | T449 |
| Test name | |
| Test status | |
| Simulation time | 987035877 ps |
| CPU time | 82.96 seconds |
| Started | Jun 23 07:36:28 PM PDT 24 |
| Finished | Jun 23 07:37:51 PM PDT 24 |
| Peak memory | 573488 kb |
| Host | smart-61077e76-bd9e-4046-9b1e-1ae7b280decb |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3427212624 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 71.xbar_access_same_device .3427212624 |
| Directory | /workspace/71.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/71.xbar_access_same_device_slow_rsp.3045371342 |
| Short name | T1897 |
| Test name | |
| Test status | |
| Simulation time | 137042370156 ps |
| CPU time | 2315.81 seconds |
| Started | Jun 23 07:36:40 PM PDT 24 |
| Finished | Jun 23 08:15:16 PM PDT 24 |
| Peak memory | 574188 kb |
| Host | smart-6bb9b820-004d-4903-aff9-19760f4a6049 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3045371342 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 71.xbar_access_same_ device_slow_rsp.3045371342 |
| Directory | /workspace/71.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/71.xbar_error_and_unmapped_addr.1354539407 |
| Short name | T1761 |
| Test name | |
| Test status | |
| Simulation time | 798884657 ps |
| CPU time | 30.76 seconds |
| Started | Jun 23 07:36:29 PM PDT 24 |
| Finished | Jun 23 07:37:00 PM PDT 24 |
| Peak memory | 573544 kb |
| Host | smart-5ab6d4df-77f9-465c-8531-3f32fecdbbe0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1354539407 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 71.xbar_error_and_unmapped_add r.1354539407 |
| Directory | /workspace/71.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/71.xbar_error_random.633724850 |
| Short name | T1396 |
| Test name | |
| Test status | |
| Simulation time | 329804987 ps |
| CPU time | 27.32 seconds |
| Started | Jun 23 07:36:27 PM PDT 24 |
| Finished | Jun 23 07:36:54 PM PDT 24 |
| Peak memory | 573668 kb |
| Host | smart-f7c96b1f-c3ed-49c4-95a0-8c3d0e498887 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=633724850 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 71.xbar_error_random.633724850 |
| Directory | /workspace/71.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/71.xbar_random.3473034549 |
| Short name | T2866 |
| Test name | |
| Test status | |
| Simulation time | 1665720941 ps |
| CPU time | 58.24 seconds |
| Started | Jun 23 07:36:20 PM PDT 24 |
| Finished | Jun 23 07:37:19 PM PDT 24 |
| Peak memory | 574104 kb |
| Host | smart-59700a0d-ef6c-4929-9460-9da1e1e4a97a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3473034549 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 71.xbar_random.3473034549 |
| Directory | /workspace/71.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/71.xbar_random_large_delays.873100480 |
| Short name | T1627 |
| Test name | |
| Test status | |
| Simulation time | 68721552031 ps |
| CPU time | 726.41 seconds |
| Started | Jun 23 07:36:27 PM PDT 24 |
| Finished | Jun 23 07:48:34 PM PDT 24 |
| Peak memory | 573416 kb |
| Host | smart-0c9a5750-66b2-4197-bc1d-9d8df8bb1d0d |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=873100480 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 71.xbar_random_large_delays.873100480 |
| Directory | /workspace/71.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/71.xbar_random_slow_rsp.1594460498 |
| Short name | T1958 |
| Test name | |
| Test status | |
| Simulation time | 5109652569 ps |
| CPU time | 82.88 seconds |
| Started | Jun 23 07:36:27 PM PDT 24 |
| Finished | Jun 23 07:37:50 PM PDT 24 |
| Peak memory | 565944 kb |
| Host | smart-e8a1c63f-2915-421d-9370-265cc7120421 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1594460498 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 71.xbar_random_slow_rsp.1594460498 |
| Directory | /workspace/71.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/71.xbar_random_zero_delays.695309475 |
| Short name | T2161 |
| Test name | |
| Test status | |
| Simulation time | 434307149 ps |
| CPU time | 40.66 seconds |
| Started | Jun 23 07:36:23 PM PDT 24 |
| Finished | Jun 23 07:37:04 PM PDT 24 |
| Peak memory | 573392 kb |
| Host | smart-3e047203-66cb-47cd-b3e0-215d33a684e6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=695309475 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 71.xbar_random_zero_dela ys.695309475 |
| Directory | /workspace/71.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/71.xbar_same_source.2516055959 |
| Short name | T443 |
| Test name | |
| Test status | |
| Simulation time | 1314522115 ps |
| CPU time | 36.29 seconds |
| Started | Jun 23 07:36:26 PM PDT 24 |
| Finished | Jun 23 07:37:03 PM PDT 24 |
| Peak memory | 574100 kb |
| Host | smart-1059a6c6-ed91-4771-8374-418efad7b51f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2516055959 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 71.xbar_same_source.2516055959 |
| Directory | /workspace/71.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/71.xbar_smoke.4250386601 |
| Short name | T2314 |
| Test name | |
| Test status | |
| Simulation time | 215859026 ps |
| CPU time | 9.47 seconds |
| Started | Jun 23 07:36:21 PM PDT 24 |
| Finished | Jun 23 07:36:32 PM PDT 24 |
| Peak memory | 565504 kb |
| Host | smart-accf526e-49c0-4b6b-a37e-142c05296f17 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4250386601 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 71.xbar_smoke.4250386601 |
| Directory | /workspace/71.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/71.xbar_smoke_large_delays.2718000482 |
| Short name | T2119 |
| Test name | |
| Test status | |
| Simulation time | 8058238293 ps |
| CPU time | 81.89 seconds |
| Started | Jun 23 07:36:25 PM PDT 24 |
| Finished | Jun 23 07:37:47 PM PDT 24 |
| Peak memory | 565264 kb |
| Host | smart-d1ca77a5-b04d-4cde-a3ea-92200ebaf706 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2718000482 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 71.xbar_smoke_large_delays.2718000482 |
| Directory | /workspace/71.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/71.xbar_smoke_slow_rsp.2427761879 |
| Short name | T1390 |
| Test name | |
| Test status | |
| Simulation time | 5796804704 ps |
| CPU time | 93.85 seconds |
| Started | Jun 23 07:36:21 PM PDT 24 |
| Finished | Jun 23 07:37:56 PM PDT 24 |
| Peak memory | 565272 kb |
| Host | smart-6b8479ed-ef6b-418f-acff-ba3499ca5f2d |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2427761879 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 71.xbar_smoke_slow_rsp.2427761879 |
| Directory | /workspace/71.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/71.xbar_smoke_zero_delays.3552985404 |
| Short name | T1891 |
| Test name | |
| Test status | |
| Simulation time | 46216707 ps |
| CPU time | 6.57 seconds |
| Started | Jun 23 07:36:22 PM PDT 24 |
| Finished | Jun 23 07:36:29 PM PDT 24 |
| Peak memory | 573336 kb |
| Host | smart-1eca77c9-232f-458a-9120-548ba2a30535 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3552985404 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 71.xbar_smoke_zero_delay s.3552985404 |
| Directory | /workspace/71.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/71.xbar_stress_all.2465738723 |
| Short name | T2872 |
| Test name | |
| Test status | |
| Simulation time | 14365643930 ps |
| CPU time | 586.78 seconds |
| Started | Jun 23 07:36:28 PM PDT 24 |
| Finished | Jun 23 07:46:15 PM PDT 24 |
| Peak memory | 574200 kb |
| Host | smart-92dae7a3-728b-413f-be70-a5b6c2ae99c6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2465738723 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 71.xbar_stress_all.2465738723 |
| Directory | /workspace/71.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/71.xbar_stress_all_with_error.1681984768 |
| Short name | T1949 |
| Test name | |
| Test status | |
| Simulation time | 3981944893 ps |
| CPU time | 145.22 seconds |
| Started | Jun 23 07:36:25 PM PDT 24 |
| Finished | Jun 23 07:38:50 PM PDT 24 |
| Peak memory | 574252 kb |
| Host | smart-76046833-ad22-4117-8a6a-458fa4bd278d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1681984768 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 71.xbar_stress_all_with_error.1681984768 |
| Directory | /workspace/71.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/71.xbar_stress_all_with_rand_reset.2425952851 |
| Short name | T517 |
| Test name | |
| Test status | |
| Simulation time | 1376601570 ps |
| CPU time | 274.34 seconds |
| Started | Jun 23 07:36:25 PM PDT 24 |
| Finished | Jun 23 07:40:59 PM PDT 24 |
| Peak memory | 574352 kb |
| Host | smart-5b2281e5-5347-4183-b879-469eb16c5650 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2425952851 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 71.xbar_stress_all _with_rand_reset.2425952851 |
| Directory | /workspace/71.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/71.xbar_stress_all_with_reset_error.1577160252 |
| Short name | T2217 |
| Test name | |
| Test status | |
| Simulation time | 6550861832 ps |
| CPU time | 281.12 seconds |
| Started | Jun 23 07:36:31 PM PDT 24 |
| Finished | Jun 23 07:41:12 PM PDT 24 |
| Peak memory | 576380 kb |
| Host | smart-a53e412f-c42e-47c2-bc19-dece923b10bd |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1577160252 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 71.xbar_stress_al l_with_reset_error.1577160252 |
| Directory | /workspace/71.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/71.xbar_unmapped_addr.1898328396 |
| Short name | T2434 |
| Test name | |
| Test status | |
| Simulation time | 159408643 ps |
| CPU time | 20.39 seconds |
| Started | Jun 23 07:36:25 PM PDT 24 |
| Finished | Jun 23 07:36:46 PM PDT 24 |
| Peak memory | 573460 kb |
| Host | smart-2071255f-d24d-4504-9fcf-3201e456035f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1898328396 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 71.xbar_unmapped_addr.1898328396 |
| Directory | /workspace/71.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/72.xbar_access_same_device.2349242108 |
| Short name | T1520 |
| Test name | |
| Test status | |
| Simulation time | 484552516 ps |
| CPU time | 42.62 seconds |
| Started | Jun 23 07:36:46 PM PDT 24 |
| Finished | Jun 23 07:37:30 PM PDT 24 |
| Peak memory | 574128 kb |
| Host | smart-8c6917dd-fc95-4d26-88d5-794765760f49 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2349242108 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 72.xbar_access_same_device .2349242108 |
| Directory | /workspace/72.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/72.xbar_access_same_device_slow_rsp.4252409981 |
| Short name | T497 |
| Test name | |
| Test status | |
| Simulation time | 117590070984 ps |
| CPU time | 2223.42 seconds |
| Started | Jun 23 07:36:47 PM PDT 24 |
| Finished | Jun 23 08:13:51 PM PDT 24 |
| Peak memory | 573716 kb |
| Host | smart-101b81d8-2e8f-49c4-b7d8-e4498e1cbd2a |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4252409981 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 72.xbar_access_same_ device_slow_rsp.4252409981 |
| Directory | /workspace/72.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/72.xbar_error_and_unmapped_addr.1770114662 |
| Short name | T1884 |
| Test name | |
| Test status | |
| Simulation time | 185917336 ps |
| CPU time | 11.74 seconds |
| Started | Jun 23 07:36:51 PM PDT 24 |
| Finished | Jun 23 07:37:04 PM PDT 24 |
| Peak memory | 573324 kb |
| Host | smart-2386f380-6b56-41df-9a36-09713fcbdc49 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1770114662 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 72.xbar_error_and_unmapped_add r.1770114662 |
| Directory | /workspace/72.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/72.xbar_error_random.1648288512 |
| Short name | T1370 |
| Test name | |
| Test status | |
| Simulation time | 1986626012 ps |
| CPU time | 69.76 seconds |
| Started | Jun 23 07:36:47 PM PDT 24 |
| Finished | Jun 23 07:37:57 PM PDT 24 |
| Peak memory | 573736 kb |
| Host | smart-493488e7-48bd-454b-8e1a-907b41f9cc7d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1648288512 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 72.xbar_error_random.1648288512 |
| Directory | /workspace/72.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/72.xbar_random.1788592394 |
| Short name | T527 |
| Test name | |
| Test status | |
| Simulation time | 1355119469 ps |
| CPU time | 48.1 seconds |
| Started | Jun 23 07:36:29 PM PDT 24 |
| Finished | Jun 23 07:37:17 PM PDT 24 |
| Peak memory | 574056 kb |
| Host | smart-b158ab4e-fec2-4f7b-a0f0-dac138ac3014 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1788592394 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 72.xbar_random.1788592394 |
| Directory | /workspace/72.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/72.xbar_random_large_delays.3642417571 |
| Short name | T1564 |
| Test name | |
| Test status | |
| Simulation time | 34409520217 ps |
| CPU time | 360.03 seconds |
| Started | Jun 23 07:36:33 PM PDT 24 |
| Finished | Jun 23 07:42:33 PM PDT 24 |
| Peak memory | 574360 kb |
| Host | smart-681686a1-b8f0-4e0d-abe9-fedf833476c8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3642417571 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 72.xbar_random_large_delays.3642417571 |
| Directory | /workspace/72.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/72.xbar_random_slow_rsp.3591078765 |
| Short name | T2146 |
| Test name | |
| Test status | |
| Simulation time | 32796267659 ps |
| CPU time | 602.02 seconds |
| Started | Jun 23 07:36:32 PM PDT 24 |
| Finished | Jun 23 07:46:34 PM PDT 24 |
| Peak memory | 574188 kb |
| Host | smart-7b2909e4-46bc-45e9-a1cb-cfa1bb5ff0c9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3591078765 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 72.xbar_random_slow_rsp.3591078765 |
| Directory | /workspace/72.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/72.xbar_random_zero_delays.1538266163 |
| Short name | T1803 |
| Test name | |
| Test status | |
| Simulation time | 378775810 ps |
| CPU time | 29.98 seconds |
| Started | Jun 23 07:36:31 PM PDT 24 |
| Finished | Jun 23 07:37:01 PM PDT 24 |
| Peak memory | 574092 kb |
| Host | smart-4adff6c0-3596-4ee8-9a3e-83d9b6ca9ec8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1538266163 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 72.xbar_random_zero_del ays.1538266163 |
| Directory | /workspace/72.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/72.xbar_same_source.886420415 |
| Short name | T2057 |
| Test name | |
| Test status | |
| Simulation time | 1356913992 ps |
| CPU time | 41 seconds |
| Started | Jun 23 07:36:47 PM PDT 24 |
| Finished | Jun 23 07:37:29 PM PDT 24 |
| Peak memory | 573644 kb |
| Host | smart-c3da54b3-408f-444d-b04d-c9767a0eb664 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=886420415 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 72.xbar_same_source.886420415 |
| Directory | /workspace/72.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/72.xbar_smoke.1203680959 |
| Short name | T2381 |
| Test name | |
| Test status | |
| Simulation time | 206465139 ps |
| CPU time | 8.87 seconds |
| Started | Jun 23 07:36:29 PM PDT 24 |
| Finished | Jun 23 07:36:38 PM PDT 24 |
| Peak memory | 565496 kb |
| Host | smart-eeddcb44-a5ea-41a0-b38f-d60ce73ac5db |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1203680959 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 72.xbar_smoke.1203680959 |
| Directory | /workspace/72.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/72.xbar_smoke_large_delays.2074839352 |
| Short name | T619 |
| Test name | |
| Test status | |
| Simulation time | 8410697171 ps |
| CPU time | 90.14 seconds |
| Started | Jun 23 07:36:30 PM PDT 24 |
| Finished | Jun 23 07:38:00 PM PDT 24 |
| Peak memory | 565916 kb |
| Host | smart-92eda215-eac7-4ab4-8f68-c544d37b367b |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2074839352 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 72.xbar_smoke_large_delays.2074839352 |
| Directory | /workspace/72.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/72.xbar_smoke_slow_rsp.1327489927 |
| Short name | T2711 |
| Test name | |
| Test status | |
| Simulation time | 4374297324 ps |
| CPU time | 74.63 seconds |
| Started | Jun 23 07:36:32 PM PDT 24 |
| Finished | Jun 23 07:37:47 PM PDT 24 |
| Peak memory | 565928 kb |
| Host | smart-7fe2f67a-7c8a-4c4c-8508-767110e3f00b |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1327489927 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 72.xbar_smoke_slow_rsp.1327489927 |
| Directory | /workspace/72.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/72.xbar_smoke_zero_delays.1223447870 |
| Short name | T2178 |
| Test name | |
| Test status | |
| Simulation time | 56371899 ps |
| CPU time | 7.3 seconds |
| Started | Jun 23 07:36:32 PM PDT 24 |
| Finished | Jun 23 07:36:39 PM PDT 24 |
| Peak memory | 565480 kb |
| Host | smart-85a808f3-c16f-47fc-801a-ba8d04b9d690 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1223447870 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 72.xbar_smoke_zero_delay s.1223447870 |
| Directory | /workspace/72.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/72.xbar_stress_all.3413806770 |
| Short name | T1956 |
| Test name | |
| Test status | |
| Simulation time | 17562064848 ps |
| CPU time | 671.37 seconds |
| Started | Jun 23 07:36:50 PM PDT 24 |
| Finished | Jun 23 07:48:02 PM PDT 24 |
| Peak memory | 574284 kb |
| Host | smart-87b02a02-c0da-4758-8531-71a9bb70f392 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3413806770 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 72.xbar_stress_all.3413806770 |
| Directory | /workspace/72.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/72.xbar_stress_all_with_error.4027287754 |
| Short name | T2720 |
| Test name | |
| Test status | |
| Simulation time | 608873561 ps |
| CPU time | 47.17 seconds |
| Started | Jun 23 07:36:53 PM PDT 24 |
| Finished | Jun 23 07:37:40 PM PDT 24 |
| Peak memory | 573340 kb |
| Host | smart-5699ed69-8ced-4c67-b444-cefd79e6fa28 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4027287754 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 72.xbar_stress_all_with_error.4027287754 |
| Directory | /workspace/72.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/72.xbar_stress_all_with_rand_reset.3520685696 |
| Short name | T1844 |
| Test name | |
| Test status | |
| Simulation time | 723306990 ps |
| CPU time | 296.79 seconds |
| Started | Jun 23 07:36:52 PM PDT 24 |
| Finished | Jun 23 07:41:49 PM PDT 24 |
| Peak memory | 576292 kb |
| Host | smart-9e2b22b0-ccb9-4f24-91e7-06c106347b81 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3520685696 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 72.xbar_stress_all _with_rand_reset.3520685696 |
| Directory | /workspace/72.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/72.xbar_stress_all_with_reset_error.21840744 |
| Short name | T1542 |
| Test name | |
| Test status | |
| Simulation time | 7805322 ps |
| CPU time | 14.74 seconds |
| Started | Jun 23 07:36:53 PM PDT 24 |
| Finished | Jun 23 07:37:09 PM PDT 24 |
| Peak memory | 565448 kb |
| Host | smart-36b0bd01-00ca-4c37-b4a7-bf2b16cb371e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21840744 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_res et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 72.xbar_stress_all_ with_reset_error.21840744 |
| Directory | /workspace/72.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/72.xbar_unmapped_addr.1473368498 |
| Short name | T674 |
| Test name | |
| Test status | |
| Simulation time | 1291527629 ps |
| CPU time | 52.31 seconds |
| Started | Jun 23 07:36:46 PM PDT 24 |
| Finished | Jun 23 07:37:39 PM PDT 24 |
| Peak memory | 574028 kb |
| Host | smart-0c9a365d-657f-4e54-a344-6df918675199 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1473368498 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 72.xbar_unmapped_addr.1473368498 |
| Directory | /workspace/72.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/73.xbar_access_same_device.825176612 |
| Short name | T1461 |
| Test name | |
| Test status | |
| Simulation time | 1147107772 ps |
| CPU time | 40.28 seconds |
| Started | Jun 23 07:36:55 PM PDT 24 |
| Finished | Jun 23 07:37:35 PM PDT 24 |
| Peak memory | 574072 kb |
| Host | smart-d0cdfc1b-9487-4ece-9962-0b0c6af18115 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=825176612 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 73.xbar_access_same_device. 825176612 |
| Directory | /workspace/73.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/73.xbar_access_same_device_slow_rsp.117943231 |
| Short name | T2328 |
| Test name | |
| Test status | |
| Simulation time | 27156397967 ps |
| CPU time | 504.58 seconds |
| Started | Jun 23 07:36:51 PM PDT 24 |
| Finished | Jun 23 07:45:17 PM PDT 24 |
| Peak memory | 574168 kb |
| Host | smart-03b93a0c-52cf-4973-8344-af311f5cdbd5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=117943231 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 73.xbar_access_same_d evice_slow_rsp.117943231 |
| Directory | /workspace/73.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/73.xbar_error_and_unmapped_addr.1101238369 |
| Short name | T1465 |
| Test name | |
| Test status | |
| Simulation time | 152477436 ps |
| CPU time | 17.83 seconds |
| Started | Jun 23 07:36:54 PM PDT 24 |
| Finished | Jun 23 07:37:12 PM PDT 24 |
| Peak memory | 573748 kb |
| Host | smart-45c21a2a-0b07-44a7-947b-4ec22be3d574 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1101238369 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 73.xbar_error_and_unmapped_add r.1101238369 |
| Directory | /workspace/73.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/73.xbar_error_random.2683505362 |
| Short name | T1696 |
| Test name | |
| Test status | |
| Simulation time | 1966644229 ps |
| CPU time | 64.07 seconds |
| Started | Jun 23 07:36:51 PM PDT 24 |
| Finished | Jun 23 07:37:56 PM PDT 24 |
| Peak memory | 573356 kb |
| Host | smart-76f4606f-d0c8-4496-b894-374b066c7a5f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2683505362 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 73.xbar_error_random.2683505362 |
| Directory | /workspace/73.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/73.xbar_random.1619532455 |
| Short name | T611 |
| Test name | |
| Test status | |
| Simulation time | 129034118 ps |
| CPU time | 8.46 seconds |
| Started | Jun 23 07:36:52 PM PDT 24 |
| Finished | Jun 23 07:37:01 PM PDT 24 |
| Peak memory | 565756 kb |
| Host | smart-142ab224-ca66-49d9-91af-7b7b18211dc2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1619532455 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 73.xbar_random.1619532455 |
| Directory | /workspace/73.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/73.xbar_random_large_delays.2792291240 |
| Short name | T600 |
| Test name | |
| Test status | |
| Simulation time | 114650768010 ps |
| CPU time | 1215.18 seconds |
| Started | Jun 23 07:36:54 PM PDT 24 |
| Finished | Jun 23 07:57:09 PM PDT 24 |
| Peak memory | 573488 kb |
| Host | smart-c8e43c92-ff92-4508-992b-dadf7aecbf1c |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2792291240 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 73.xbar_random_large_delays.2792291240 |
| Directory | /workspace/73.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/73.xbar_random_slow_rsp.4207066580 |
| Short name | T2257 |
| Test name | |
| Test status | |
| Simulation time | 37900724118 ps |
| CPU time | 621.8 seconds |
| Started | Jun 23 07:36:51 PM PDT 24 |
| Finished | Jun 23 07:47:14 PM PDT 24 |
| Peak memory | 574224 kb |
| Host | smart-4d7d405b-5a5d-4bb8-b4e3-2570febff1ad |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4207066580 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 73.xbar_random_slow_rsp.4207066580 |
| Directory | /workspace/73.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/73.xbar_random_zero_delays.2169597047 |
| Short name | T1728 |
| Test name | |
| Test status | |
| Simulation time | 297814455 ps |
| CPU time | 29.56 seconds |
| Started | Jun 23 07:36:53 PM PDT 24 |
| Finished | Jun 23 07:37:23 PM PDT 24 |
| Peak memory | 574072 kb |
| Host | smart-4e3436a5-cf4a-444a-8fe5-6c754fbd0a7f |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2169597047 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 73.xbar_random_zero_del ays.2169597047 |
| Directory | /workspace/73.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/73.xbar_same_source.2185667030 |
| Short name | T2016 |
| Test name | |
| Test status | |
| Simulation time | 2866994721 ps |
| CPU time | 82.01 seconds |
| Started | Jun 23 07:36:53 PM PDT 24 |
| Finished | Jun 23 07:38:16 PM PDT 24 |
| Peak memory | 574168 kb |
| Host | smart-7648f76a-e71b-42bc-a4d9-edcd10fbf9f0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2185667030 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 73.xbar_same_source.2185667030 |
| Directory | /workspace/73.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/73.xbar_smoke.1887534687 |
| Short name | T1866 |
| Test name | |
| Test status | |
| Simulation time | 50009615 ps |
| CPU time | 7.06 seconds |
| Started | Jun 23 07:36:51 PM PDT 24 |
| Finished | Jun 23 07:36:59 PM PDT 24 |
| Peak memory | 565472 kb |
| Host | smart-cd26d46d-41f9-4eaf-bb6b-6b413f767ea3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1887534687 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 73.xbar_smoke.1887534687 |
| Directory | /workspace/73.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/73.xbar_smoke_large_delays.1830309985 |
| Short name | T2747 |
| Test name | |
| Test status | |
| Simulation time | 7164607203 ps |
| CPU time | 75.13 seconds |
| Started | Jun 23 07:36:51 PM PDT 24 |
| Finished | Jun 23 07:38:06 PM PDT 24 |
| Peak memory | 565252 kb |
| Host | smart-ed8d22e3-aaf9-45a0-974c-a39e9d0c14ce |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1830309985 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 73.xbar_smoke_large_delays.1830309985 |
| Directory | /workspace/73.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/73.xbar_smoke_slow_rsp.1439905991 |
| Short name | T2180 |
| Test name | |
| Test status | |
| Simulation time | 5733598814 ps |
| CPU time | 96.07 seconds |
| Started | Jun 23 07:36:51 PM PDT 24 |
| Finished | Jun 23 07:38:27 PM PDT 24 |
| Peak memory | 565232 kb |
| Host | smart-4c56ad35-9ac8-4b9d-9aca-3e0bda4eabc2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1439905991 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 73.xbar_smoke_slow_rsp.1439905991 |
| Directory | /workspace/73.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/73.xbar_smoke_zero_delays.3032334424 |
| Short name | T2556 |
| Test name | |
| Test status | |
| Simulation time | 38012140 ps |
| CPU time | 5.94 seconds |
| Started | Jun 23 07:36:54 PM PDT 24 |
| Finished | Jun 23 07:37:00 PM PDT 24 |
| Peak memory | 573736 kb |
| Host | smart-f9345ea0-830d-43bc-a31e-48b2299158e7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3032334424 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 73.xbar_smoke_zero_delay s.3032334424 |
| Directory | /workspace/73.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/73.xbar_stress_all.884678802 |
| Short name | T1528 |
| Test name | |
| Test status | |
| Simulation time | 5960589 ps |
| CPU time | 3.76 seconds |
| Started | Jun 23 07:36:50 PM PDT 24 |
| Finished | Jun 23 07:36:54 PM PDT 24 |
| Peak memory | 565288 kb |
| Host | smart-4b434bae-70bb-45e1-903e-877c377c209c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=884678802 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 73.xbar_stress_all.884678802 |
| Directory | /workspace/73.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/73.xbar_stress_all_with_error.3655863450 |
| Short name | T2073 |
| Test name | |
| Test status | |
| Simulation time | 2415138618 ps |
| CPU time | 83.11 seconds |
| Started | Jun 23 07:37:05 PM PDT 24 |
| Finished | Jun 23 07:38:28 PM PDT 24 |
| Peak memory | 574260 kb |
| Host | smart-b17ba442-597b-4c6f-ad75-fb6f6e81c50c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3655863450 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 73.xbar_stress_all_with_error.3655863450 |
| Directory | /workspace/73.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/73.xbar_stress_all_with_rand_reset.3647756307 |
| Short name | T1859 |
| Test name | |
| Test status | |
| Simulation time | 511318115 ps |
| CPU time | 161.41 seconds |
| Started | Jun 23 07:36:56 PM PDT 24 |
| Finished | Jun 23 07:39:37 PM PDT 24 |
| Peak memory | 574216 kb |
| Host | smart-e570285c-dbdb-4465-aa37-291c054ee179 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3647756307 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 73.xbar_stress_all _with_rand_reset.3647756307 |
| Directory | /workspace/73.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/73.xbar_stress_all_with_reset_error.1471533859 |
| Short name | T909 |
| Test name | |
| Test status | |
| Simulation time | 251400725 ps |
| CPU time | 76.89 seconds |
| Started | Jun 23 07:36:59 PM PDT 24 |
| Finished | Jun 23 07:38:17 PM PDT 24 |
| Peak memory | 576332 kb |
| Host | smart-893caa4a-b0ee-43f8-a5d2-83cd6f73f814 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1471533859 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 73.xbar_stress_al l_with_reset_error.1471533859 |
| Directory | /workspace/73.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/73.xbar_unmapped_addr.2340900392 |
| Short name | T1780 |
| Test name | |
| Test status | |
| Simulation time | 306362033 ps |
| CPU time | 15.52 seconds |
| Started | Jun 23 07:36:54 PM PDT 24 |
| Finished | Jun 23 07:37:10 PM PDT 24 |
| Peak memory | 574104 kb |
| Host | smart-729f42f2-5c68-4c3d-afed-4d23c0d129c2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2340900392 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 73.xbar_unmapped_addr.2340900392 |
| Directory | /workspace/73.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/74.xbar_access_same_device_slow_rsp.574852043 |
| Short name | T1875 |
| Test name | |
| Test status | |
| Simulation time | 50204668149 ps |
| CPU time | 964.99 seconds |
| Started | Jun 23 07:36:59 PM PDT 24 |
| Finished | Jun 23 07:53:05 PM PDT 24 |
| Peak memory | 573528 kb |
| Host | smart-1eba1786-4ec2-46d4-a7db-b88367d51c8f |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=574852043 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 74.xbar_access_same_d evice_slow_rsp.574852043 |
| Directory | /workspace/74.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/74.xbar_error_and_unmapped_addr.3519910459 |
| Short name | T1617 |
| Test name | |
| Test status | |
| Simulation time | 125658448 ps |
| CPU time | 15.07 seconds |
| Started | Jun 23 07:37:01 PM PDT 24 |
| Finished | Jun 23 07:37:16 PM PDT 24 |
| Peak memory | 573636 kb |
| Host | smart-a8e44555-3095-4af8-b1b9-3ac547606c9e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3519910459 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 74.xbar_error_and_unmapped_add r.3519910459 |
| Directory | /workspace/74.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/74.xbar_error_random.3788473813 |
| Short name | T2348 |
| Test name | |
| Test status | |
| Simulation time | 2160920458 ps |
| CPU time | 76.77 seconds |
| Started | Jun 23 07:37:07 PM PDT 24 |
| Finished | Jun 23 07:38:24 PM PDT 24 |
| Peak memory | 573796 kb |
| Host | smart-7dd1794f-c5eb-4b2e-a12a-705c5c1d71e5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3788473813 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 74.xbar_error_random.3788473813 |
| Directory | /workspace/74.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/74.xbar_random.2852348356 |
| Short name | T1587 |
| Test name | |
| Test status | |
| Simulation time | 280520648 ps |
| CPU time | 25.59 seconds |
| Started | Jun 23 07:36:53 PM PDT 24 |
| Finished | Jun 23 07:37:19 PM PDT 24 |
| Peak memory | 573440 kb |
| Host | smart-6ccb1ec0-6308-4377-9a48-5838894db88a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2852348356 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 74.xbar_random.2852348356 |
| Directory | /workspace/74.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/74.xbar_random_large_delays.2978040867 |
| Short name | T1751 |
| Test name | |
| Test status | |
| Simulation time | 6010500343 ps |
| CPU time | 63.04 seconds |
| Started | Jun 23 07:36:56 PM PDT 24 |
| Finished | Jun 23 07:37:59 PM PDT 24 |
| Peak memory | 565236 kb |
| Host | smart-59025118-ba87-4828-83a7-0e3818fb1ffc |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2978040867 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 74.xbar_random_large_delays.2978040867 |
| Directory | /workspace/74.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/74.xbar_random_slow_rsp.1416990782 |
| Short name | T2353 |
| Test name | |
| Test status | |
| Simulation time | 29368360873 ps |
| CPU time | 464.83 seconds |
| Started | Jun 23 07:37:00 PM PDT 24 |
| Finished | Jun 23 07:44:45 PM PDT 24 |
| Peak memory | 573512 kb |
| Host | smart-23e8e028-71ac-44b9-a914-85416caf77c6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1416990782 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 74.xbar_random_slow_rsp.1416990782 |
| Directory | /workspace/74.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/74.xbar_random_zero_delays.1213639474 |
| Short name | T2380 |
| Test name | |
| Test status | |
| Simulation time | 331983314 ps |
| CPU time | 30.65 seconds |
| Started | Jun 23 07:36:59 PM PDT 24 |
| Finished | Jun 23 07:37:30 PM PDT 24 |
| Peak memory | 574064 kb |
| Host | smart-51c1d36d-33b2-4d91-ab5b-6ce50c4c972f |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1213639474 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 74.xbar_random_zero_del ays.1213639474 |
| Directory | /workspace/74.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/74.xbar_same_source.2716078239 |
| Short name | T683 |
| Test name | |
| Test status | |
| Simulation time | 1116580707 ps |
| CPU time | 33.51 seconds |
| Started | Jun 23 07:37:06 PM PDT 24 |
| Finished | Jun 23 07:37:40 PM PDT 24 |
| Peak memory | 573416 kb |
| Host | smart-aea3f1a7-f0f3-47e6-a305-c4b38438f600 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2716078239 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 74.xbar_same_source.2716078239 |
| Directory | /workspace/74.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/74.xbar_smoke.3223682772 |
| Short name | T2871 |
| Test name | |
| Test status | |
| Simulation time | 39373764 ps |
| CPU time | 5.77 seconds |
| Started | Jun 23 07:36:56 PM PDT 24 |
| Finished | Jun 23 07:37:02 PM PDT 24 |
| Peak memory | 565176 kb |
| Host | smart-38288703-f22f-442e-831b-9e20353f22e0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3223682772 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 74.xbar_smoke.3223682772 |
| Directory | /workspace/74.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/74.xbar_smoke_large_delays.3187540326 |
| Short name | T1559 |
| Test name | |
| Test status | |
| Simulation time | 7458070175 ps |
| CPU time | 83.29 seconds |
| Started | Jun 23 07:36:56 PM PDT 24 |
| Finished | Jun 23 07:38:20 PM PDT 24 |
| Peak memory | 565536 kb |
| Host | smart-8ebaa551-c840-4461-aaf7-70dbf192cc6c |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3187540326 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 74.xbar_smoke_large_delays.3187540326 |
| Directory | /workspace/74.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/74.xbar_smoke_slow_rsp.1438640977 |
| Short name | T2837 |
| Test name | |
| Test status | |
| Simulation time | 4625825555 ps |
| CPU time | 78.17 seconds |
| Started | Jun 23 07:36:59 PM PDT 24 |
| Finished | Jun 23 07:38:17 PM PDT 24 |
| Peak memory | 565904 kb |
| Host | smart-a5e6087e-904b-468e-a643-6690340c6f6c |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1438640977 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 74.xbar_smoke_slow_rsp.1438640977 |
| Directory | /workspace/74.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/74.xbar_smoke_zero_delays.2634660300 |
| Short name | T1831 |
| Test name | |
| Test status | |
| Simulation time | 53946696 ps |
| CPU time | 6.93 seconds |
| Started | Jun 23 07:36:59 PM PDT 24 |
| Finished | Jun 23 07:37:06 PM PDT 24 |
| Peak memory | 565516 kb |
| Host | smart-d5dba12c-bee2-4c65-8d8c-3541b0a4a12e |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2634660300 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 74.xbar_smoke_zero_delay s.2634660300 |
| Directory | /workspace/74.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/74.xbar_stress_all.390992629 |
| Short name | T2451 |
| Test name | |
| Test status | |
| Simulation time | 1147579618 ps |
| CPU time | 44.49 seconds |
| Started | Jun 23 07:37:01 PM PDT 24 |
| Finished | Jun 23 07:37:46 PM PDT 24 |
| Peak memory | 574208 kb |
| Host | smart-3c0ac6fa-9871-4381-90fc-471fe144cd78 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=390992629 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 74.xbar_stress_all.390992629 |
| Directory | /workspace/74.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/74.xbar_stress_all_with_error.1483155723 |
| Short name | T2612 |
| Test name | |
| Test status | |
| Simulation time | 9969851156 ps |
| CPU time | 381.72 seconds |
| Started | Jun 23 07:36:58 PM PDT 24 |
| Finished | Jun 23 07:43:20 PM PDT 24 |
| Peak memory | 574348 kb |
| Host | smart-53f47305-28ba-437e-a371-33890d97add0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1483155723 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 74.xbar_stress_all_with_error.1483155723 |
| Directory | /workspace/74.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/74.xbar_stress_all_with_rand_reset.1874627370 |
| Short name | T468 |
| Test name | |
| Test status | |
| Simulation time | 11006013323 ps |
| CPU time | 554.72 seconds |
| Started | Jun 23 07:37:03 PM PDT 24 |
| Finished | Jun 23 07:46:18 PM PDT 24 |
| Peak memory | 576280 kb |
| Host | smart-2ef13cac-2e0f-4a47-95f9-c169174ad8c1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1874627370 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 74.xbar_stress_all _with_rand_reset.1874627370 |
| Directory | /workspace/74.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/74.xbar_stress_all_with_reset_error.947607547 |
| Short name | T1507 |
| Test name | |
| Test status | |
| Simulation time | 185210630 ps |
| CPU time | 29.41 seconds |
| Started | Jun 23 07:37:00 PM PDT 24 |
| Finished | Jun 23 07:37:30 PM PDT 24 |
| Peak memory | 574268 kb |
| Host | smart-35ee9e64-b220-4dc3-9b09-e89aae56318a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=947607547 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 74.xbar_stress_all _with_reset_error.947607547 |
| Directory | /workspace/74.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/74.xbar_unmapped_addr.1558304123 |
| Short name | T2363 |
| Test name | |
| Test status | |
| Simulation time | 385709407 ps |
| CPU time | 18.25 seconds |
| Started | Jun 23 07:37:03 PM PDT 24 |
| Finished | Jun 23 07:37:22 PM PDT 24 |
| Peak memory | 574092 kb |
| Host | smart-a6ca8e82-43e0-4f2b-a29a-15e530373490 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1558304123 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 74.xbar_unmapped_addr.1558304123 |
| Directory | /workspace/74.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/75.xbar_access_same_device.643918845 |
| Short name | T1911 |
| Test name | |
| Test status | |
| Simulation time | 650626935 ps |
| CPU time | 27.74 seconds |
| Started | Jun 23 07:37:04 PM PDT 24 |
| Finished | Jun 23 07:37:32 PM PDT 24 |
| Peak memory | 574116 kb |
| Host | smart-690fbb0b-8e8e-4a12-9aac-0becb593ba4a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=643918845 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 75.xbar_access_same_device. 643918845 |
| Directory | /workspace/75.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/75.xbar_access_same_device_slow_rsp.3263953657 |
| Short name | T1822 |
| Test name | |
| Test status | |
| Simulation time | 116814806523 ps |
| CPU time | 2119.65 seconds |
| Started | Jun 23 07:37:27 PM PDT 24 |
| Finished | Jun 23 08:12:47 PM PDT 24 |
| Peak memory | 573608 kb |
| Host | smart-a7ab0bd2-5e18-40fa-aef3-c1d1262df138 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3263953657 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 75.xbar_access_same_ device_slow_rsp.3263953657 |
| Directory | /workspace/75.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/75.xbar_error_and_unmapped_addr.1793670295 |
| Short name | T2431 |
| Test name | |
| Test status | |
| Simulation time | 159606128 ps |
| CPU time | 18 seconds |
| Started | Jun 23 07:37:28 PM PDT 24 |
| Finished | Jun 23 07:37:46 PM PDT 24 |
| Peak memory | 573664 kb |
| Host | smart-ca8a21a4-b4c5-4ad4-9c98-d11f4c66a7d3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1793670295 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 75.xbar_error_and_unmapped_add r.1793670295 |
| Directory | /workspace/75.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/75.xbar_error_random.1508623303 |
| Short name | T2041 |
| Test name | |
| Test status | |
| Simulation time | 425802653 ps |
| CPU time | 33.42 seconds |
| Started | Jun 23 07:37:30 PM PDT 24 |
| Finished | Jun 23 07:38:03 PM PDT 24 |
| Peak memory | 573332 kb |
| Host | smart-d907a7fa-23f0-472e-8015-d077c661e065 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1508623303 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 75.xbar_error_random.1508623303 |
| Directory | /workspace/75.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/75.xbar_random.857131048 |
| Short name | T2007 |
| Test name | |
| Test status | |
| Simulation time | 31054532 ps |
| CPU time | 5.88 seconds |
| Started | Jun 23 07:37:06 PM PDT 24 |
| Finished | Jun 23 07:37:13 PM PDT 24 |
| Peak memory | 565184 kb |
| Host | smart-22762dff-0655-430a-a344-ed9e0ce9f765 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=857131048 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 75.xbar_random.857131048 |
| Directory | /workspace/75.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/75.xbar_random_large_delays.1040756498 |
| Short name | T2093 |
| Test name | |
| Test status | |
| Simulation time | 60390756452 ps |
| CPU time | 704.01 seconds |
| Started | Jun 23 07:37:07 PM PDT 24 |
| Finished | Jun 23 07:48:51 PM PDT 24 |
| Peak memory | 574216 kb |
| Host | smart-f8990b85-17fa-4bb4-bf7d-a4488dab7fa3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1040756498 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 75.xbar_random_large_delays.1040756498 |
| Directory | /workspace/75.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/75.xbar_random_slow_rsp.3541923159 |
| Short name | T1873 |
| Test name | |
| Test status | |
| Simulation time | 6296183982 ps |
| CPU time | 99.97 seconds |
| Started | Jun 23 07:37:07 PM PDT 24 |
| Finished | Jun 23 07:38:47 PM PDT 24 |
| Peak memory | 573516 kb |
| Host | smart-11ba1f2d-efe0-42e5-9242-4bd628fd0803 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3541923159 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 75.xbar_random_slow_rsp.3541923159 |
| Directory | /workspace/75.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/75.xbar_random_zero_delays.3829365998 |
| Short name | T605 |
| Test name | |
| Test status | |
| Simulation time | 566845399 ps |
| CPU time | 46.96 seconds |
| Started | Jun 23 07:37:04 PM PDT 24 |
| Finished | Jun 23 07:37:51 PM PDT 24 |
| Peak memory | 574100 kb |
| Host | smart-c9872664-23bb-4da8-98be-cb5908f0dbdc |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3829365998 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 75.xbar_random_zero_del ays.3829365998 |
| Directory | /workspace/75.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/75.xbar_same_source.3635079755 |
| Short name | T2858 |
| Test name | |
| Test status | |
| Simulation time | 902892807 ps |
| CPU time | 29.65 seconds |
| Started | Jun 23 07:37:30 PM PDT 24 |
| Finished | Jun 23 07:38:00 PM PDT 24 |
| Peak memory | 573400 kb |
| Host | smart-ed38d57c-3d0f-44d1-94b8-8eebed3507ae |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3635079755 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 75.xbar_same_source.3635079755 |
| Directory | /workspace/75.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/75.xbar_smoke.4068659514 |
| Short name | T2650 |
| Test name | |
| Test status | |
| Simulation time | 255108497 ps |
| CPU time | 10.63 seconds |
| Started | Jun 23 07:37:06 PM PDT 24 |
| Finished | Jun 23 07:37:17 PM PDT 24 |
| Peak memory | 565192 kb |
| Host | smart-2d29c762-cbca-4937-a068-79362775d53e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4068659514 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 75.xbar_smoke.4068659514 |
| Directory | /workspace/75.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/75.xbar_smoke_large_delays.1751410070 |
| Short name | T1660 |
| Test name | |
| Test status | |
| Simulation time | 7752784328 ps |
| CPU time | 84.68 seconds |
| Started | Jun 23 07:37:00 PM PDT 24 |
| Finished | Jun 23 07:38:25 PM PDT 24 |
| Peak memory | 565556 kb |
| Host | smart-7d7d8319-de91-4409-99d3-70a9c96ee374 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1751410070 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 75.xbar_smoke_large_delays.1751410070 |
| Directory | /workspace/75.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/75.xbar_smoke_slow_rsp.405401795 |
| Short name | T2343 |
| Test name | |
| Test status | |
| Simulation time | 4953840371 ps |
| CPU time | 85.4 seconds |
| Started | Jun 23 07:37:05 PM PDT 24 |
| Finished | Jun 23 07:38:30 PM PDT 24 |
| Peak memory | 565280 kb |
| Host | smart-23e83ce3-5c05-462d-ac8c-6821176cc39d |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=405401795 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 75.xbar_smoke_slow_rsp.405401795 |
| Directory | /workspace/75.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/75.xbar_smoke_zero_delays.4209310725 |
| Short name | T2015 |
| Test name | |
| Test status | |
| Simulation time | 42096298 ps |
| CPU time | 6.01 seconds |
| Started | Jun 23 07:36:59 PM PDT 24 |
| Finished | Jun 23 07:37:05 PM PDT 24 |
| Peak memory | 565476 kb |
| Host | smart-7af74835-1a2e-4c45-8ad5-b3a7cd6e504c |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4209310725 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 75.xbar_smoke_zero_delay s.4209310725 |
| Directory | /workspace/75.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/75.xbar_stress_all.1278172092 |
| Short name | T1973 |
| Test name | |
| Test status | |
| Simulation time | 3076234042 ps |
| CPU time | 116.78 seconds |
| Started | Jun 23 07:37:33 PM PDT 24 |
| Finished | Jun 23 07:39:30 PM PDT 24 |
| Peak memory | 574272 kb |
| Host | smart-4febfe05-90d1-47cb-b58b-bda52cccfcaa |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1278172092 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 75.xbar_stress_all.1278172092 |
| Directory | /workspace/75.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/75.xbar_stress_all_with_error.284848513 |
| Short name | T2717 |
| Test name | |
| Test status | |
| Simulation time | 10036904179 ps |
| CPU time | 381.5 seconds |
| Started | Jun 23 07:37:34 PM PDT 24 |
| Finished | Jun 23 07:43:56 PM PDT 24 |
| Peak memory | 574380 kb |
| Host | smart-c02b6774-fc03-4e1f-bb45-39ccb4a8c24a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=284848513 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 75.xbar_stress_all_with_error.284848513 |
| Directory | /workspace/75.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/75.xbar_stress_all_with_rand_reset.2395153721 |
| Short name | T906 |
| Test name | |
| Test status | |
| Simulation time | 642482905 ps |
| CPU time | 207.94 seconds |
| Started | Jun 23 07:37:34 PM PDT 24 |
| Finished | Jun 23 07:41:03 PM PDT 24 |
| Peak memory | 576288 kb |
| Host | smart-219068d5-4167-45af-ba70-b280036720bc |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2395153721 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 75.xbar_stress_all _with_rand_reset.2395153721 |
| Directory | /workspace/75.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/75.xbar_stress_all_with_reset_error.3466088973 |
| Short name | T898 |
| Test name | |
| Test status | |
| Simulation time | 7767556135 ps |
| CPU time | 382.14 seconds |
| Started | Jun 23 07:37:39 PM PDT 24 |
| Finished | Jun 23 07:44:02 PM PDT 24 |
| Peak memory | 574376 kb |
| Host | smart-cace4067-6b7a-421e-bb2e-6a47dc350eb1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3466088973 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 75.xbar_stress_al l_with_reset_error.3466088973 |
| Directory | /workspace/75.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/75.xbar_unmapped_addr.416327291 |
| Short name | T2789 |
| Test name | |
| Test status | |
| Simulation time | 990970372 ps |
| CPU time | 41.75 seconds |
| Started | Jun 23 07:37:29 PM PDT 24 |
| Finished | Jun 23 07:38:11 PM PDT 24 |
| Peak memory | 574156 kb |
| Host | smart-41a37547-27c6-4552-8be0-3f31f4b96211 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=416327291 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 75.xbar_unmapped_addr.416327291 |
| Directory | /workspace/75.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/76.xbar_access_same_device.3053667242 |
| Short name | T522 |
| Test name | |
| Test status | |
| Simulation time | 1462196759 ps |
| CPU time | 108.83 seconds |
| Started | Jun 23 07:37:33 PM PDT 24 |
| Finished | Jun 23 07:39:23 PM PDT 24 |
| Peak memory | 574164 kb |
| Host | smart-fd3919c1-77d1-4a43-a10c-157429e66056 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3053667242 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 76.xbar_access_same_device .3053667242 |
| Directory | /workspace/76.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/76.xbar_error_and_unmapped_addr.2692067136 |
| Short name | T2150 |
| Test name | |
| Test status | |
| Simulation time | 467770519 ps |
| CPU time | 21.35 seconds |
| Started | Jun 23 07:37:39 PM PDT 24 |
| Finished | Jun 23 07:38:01 PM PDT 24 |
| Peak memory | 573648 kb |
| Host | smart-2f3e3c1e-fe5f-40f6-a052-c55947ebec8b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2692067136 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 76.xbar_error_and_unmapped_add r.2692067136 |
| Directory | /workspace/76.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/76.xbar_error_random.1667900953 |
| Short name | T2410 |
| Test name | |
| Test status | |
| Simulation time | 87823109 ps |
| CPU time | 6.85 seconds |
| Started | Jun 23 07:37:36 PM PDT 24 |
| Finished | Jun 23 07:37:43 PM PDT 24 |
| Peak memory | 565432 kb |
| Host | smart-a206bd38-67af-4906-9fb5-0c6e6527449a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1667900953 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 76.xbar_error_random.1667900953 |
| Directory | /workspace/76.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/76.xbar_random.2853861346 |
| Short name | T2626 |
| Test name | |
| Test status | |
| Simulation time | 2078378752 ps |
| CPU time | 75.18 seconds |
| Started | Jun 23 07:37:40 PM PDT 24 |
| Finished | Jun 23 07:38:55 PM PDT 24 |
| Peak memory | 574128 kb |
| Host | smart-b0971d61-b89a-471b-a1d4-b096e17e6704 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2853861346 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 76.xbar_random.2853861346 |
| Directory | /workspace/76.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/76.xbar_random_slow_rsp.3663156557 |
| Short name | T495 |
| Test name | |
| Test status | |
| Simulation time | 44452059100 ps |
| CPU time | 765.24 seconds |
| Started | Jun 23 07:37:39 PM PDT 24 |
| Finished | Jun 23 07:50:24 PM PDT 24 |
| Peak memory | 574212 kb |
| Host | smart-2a100525-c9b9-4f6b-96a1-1665cecacce4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3663156557 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 76.xbar_random_slow_rsp.3663156557 |
| Directory | /workspace/76.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/76.xbar_random_zero_delays.541350081 |
| Short name | T1644 |
| Test name | |
| Test status | |
| Simulation time | 560323458 ps |
| CPU time | 51.35 seconds |
| Started | Jun 23 07:37:34 PM PDT 24 |
| Finished | Jun 23 07:38:26 PM PDT 24 |
| Peak memory | 574096 kb |
| Host | smart-3251fe8f-dd23-4208-9b93-4d9d201b0fa3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=541350081 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 76.xbar_random_zero_dela ys.541350081 |
| Directory | /workspace/76.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/76.xbar_same_source.3511916971 |
| Short name | T459 |
| Test name | |
| Test status | |
| Simulation time | 2449259010 ps |
| CPU time | 74.85 seconds |
| Started | Jun 23 07:37:37 PM PDT 24 |
| Finished | Jun 23 07:38:52 PM PDT 24 |
| Peak memory | 574088 kb |
| Host | smart-32edccb4-083c-4efc-972a-6ef22c077d1f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3511916971 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 76.xbar_same_source.3511916971 |
| Directory | /workspace/76.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/76.xbar_smoke.2606667618 |
| Short name | T1824 |
| Test name | |
| Test status | |
| Simulation time | 44522827 ps |
| CPU time | 5.88 seconds |
| Started | Jun 23 07:37:34 PM PDT 24 |
| Finished | Jun 23 07:37:40 PM PDT 24 |
| Peak memory | 565796 kb |
| Host | smart-896721dd-6390-41ae-85b7-f90b2f4e79b1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2606667618 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 76.xbar_smoke.2606667618 |
| Directory | /workspace/76.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/76.xbar_smoke_large_delays.1602776443 |
| Short name | T2351 |
| Test name | |
| Test status | |
| Simulation time | 7792841168 ps |
| CPU time | 84.81 seconds |
| Started | Jun 23 07:37:37 PM PDT 24 |
| Finished | Jun 23 07:39:03 PM PDT 24 |
| Peak memory | 565920 kb |
| Host | smart-765a884a-fca2-4504-9ade-57190ef456e4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1602776443 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 76.xbar_smoke_large_delays.1602776443 |
| Directory | /workspace/76.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/76.xbar_smoke_slow_rsp.2484055956 |
| Short name | T1747 |
| Test name | |
| Test status | |
| Simulation time | 3288325512 ps |
| CPU time | 56.35 seconds |
| Started | Jun 23 07:37:34 PM PDT 24 |
| Finished | Jun 23 07:38:31 PM PDT 24 |
| Peak memory | 565196 kb |
| Host | smart-35ac2158-60ad-4319-9536-652903e2d6a5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2484055956 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 76.xbar_smoke_slow_rsp.2484055956 |
| Directory | /workspace/76.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/76.xbar_smoke_zero_delays.3372263686 |
| Short name | T2053 |
| Test name | |
| Test status | |
| Simulation time | 41429347 ps |
| CPU time | 5.74 seconds |
| Started | Jun 23 07:37:37 PM PDT 24 |
| Finished | Jun 23 07:37:43 PM PDT 24 |
| Peak memory | 565496 kb |
| Host | smart-7792ff24-a638-4968-810e-7ab3cee3d4d1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3372263686 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 76.xbar_smoke_zero_delay s.3372263686 |
| Directory | /workspace/76.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/76.xbar_stress_all.2712612319 |
| Short name | T565 |
| Test name | |
| Test status | |
| Simulation time | 1932281429 ps |
| CPU time | 187.18 seconds |
| Started | Jun 23 07:37:33 PM PDT 24 |
| Finished | Jun 23 07:40:41 PM PDT 24 |
| Peak memory | 574240 kb |
| Host | smart-3e09b385-d48c-43fc-843e-e909a0baa8e0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2712612319 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 76.xbar_stress_all.2712612319 |
| Directory | /workspace/76.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/76.xbar_stress_all_with_error.1440515591 |
| Short name | T2199 |
| Test name | |
| Test status | |
| Simulation time | 8596565446 ps |
| CPU time | 315.18 seconds |
| Started | Jun 23 07:37:34 PM PDT 24 |
| Finished | Jun 23 07:42:50 PM PDT 24 |
| Peak memory | 574336 kb |
| Host | smart-cfbaa8b1-0c4b-49b3-a71e-41544a3ecdff |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1440515591 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 76.xbar_stress_all_with_error.1440515591 |
| Directory | /workspace/76.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/76.xbar_stress_all_with_rand_reset.700073068 |
| Short name | T536 |
| Test name | |
| Test status | |
| Simulation time | 212936745 ps |
| CPU time | 93.86 seconds |
| Started | Jun 23 07:37:35 PM PDT 24 |
| Finished | Jun 23 07:39:09 PM PDT 24 |
| Peak memory | 576296 kb |
| Host | smart-b23d9217-c1e0-41f8-9a86-aba67b3f95fb |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=700073068 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_res et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 76.xbar_stress_all_ with_rand_reset.700073068 |
| Directory | /workspace/76.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/76.xbar_stress_all_with_reset_error.3768044509 |
| Short name | T1920 |
| Test name | |
| Test status | |
| Simulation time | 159168569 ps |
| CPU time | 72.82 seconds |
| Started | Jun 23 07:37:34 PM PDT 24 |
| Finished | Jun 23 07:38:48 PM PDT 24 |
| Peak memory | 574284 kb |
| Host | smart-40ebad28-6864-4d53-85c5-ea358aecfa18 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3768044509 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 76.xbar_stress_al l_with_reset_error.3768044509 |
| Directory | /workspace/76.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/76.xbar_unmapped_addr.84105942 |
| Short name | T2461 |
| Test name | |
| Test status | |
| Simulation time | 21533566 ps |
| CPU time | 5.43 seconds |
| Started | Jun 23 07:37:34 PM PDT 24 |
| Finished | Jun 23 07:37:40 PM PDT 24 |
| Peak memory | 565904 kb |
| Host | smart-10036858-10f6-4abd-9279-9d65f0e5cf66 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84105942 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 76.xbar_unmapped_addr.84105942 |
| Directory | /workspace/76.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/77.xbar_access_same_device.4091432503 |
| Short name | T2349 |
| Test name | |
| Test status | |
| Simulation time | 253590021 ps |
| CPU time | 21.65 seconds |
| Started | Jun 23 07:37:36 PM PDT 24 |
| Finished | Jun 23 07:37:58 PM PDT 24 |
| Peak memory | 573972 kb |
| Host | smart-a10b8ade-a540-4e40-afcc-77790055f7d6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4091432503 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 77.xbar_access_same_device .4091432503 |
| Directory | /workspace/77.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/77.xbar_access_same_device_slow_rsp.1414631277 |
| Short name | T865 |
| Test name | |
| Test status | |
| Simulation time | 67169052473 ps |
| CPU time | 1271.81 seconds |
| Started | Jun 23 07:37:34 PM PDT 24 |
| Finished | Jun 23 07:58:47 PM PDT 24 |
| Peak memory | 574220 kb |
| Host | smart-242e8e08-ede0-4044-90ee-64d0d320e470 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1414631277 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 77.xbar_access_same_ device_slow_rsp.1414631277 |
| Directory | /workspace/77.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/77.xbar_error_and_unmapped_addr.6220310 |
| Short name | T1416 |
| Test name | |
| Test status | |
| Simulation time | 685071272 ps |
| CPU time | 27.98 seconds |
| Started | Jun 23 07:38:36 PM PDT 24 |
| Finished | Jun 23 07:39:05 PM PDT 24 |
| Peak memory | 573372 kb |
| Host | smart-8b9ca20a-3ba6-4673-9657-26f8ac461501 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=6220310 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 77.xbar_error_and_unmapped_addr.6220310 |
| Directory | /workspace/77.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/77.xbar_error_random.4086350839 |
| Short name | T1363 |
| Test name | |
| Test status | |
| Simulation time | 63095866 ps |
| CPU time | 8.75 seconds |
| Started | Jun 23 07:37:33 PM PDT 24 |
| Finished | Jun 23 07:37:42 PM PDT 24 |
| Peak memory | 573672 kb |
| Host | smart-4232a2d1-29a3-4c29-b010-a9824d111e16 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4086350839 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 77.xbar_error_random.4086350839 |
| Directory | /workspace/77.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/77.xbar_random.3659507439 |
| Short name | T466 |
| Test name | |
| Test status | |
| Simulation time | 118276306 ps |
| CPU time | 14.36 seconds |
| Started | Jun 23 07:37:33 PM PDT 24 |
| Finished | Jun 23 07:37:48 PM PDT 24 |
| Peak memory | 574088 kb |
| Host | smart-42dcb305-61f6-46a7-bb76-31378c9f68ab |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3659507439 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 77.xbar_random.3659507439 |
| Directory | /workspace/77.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/77.xbar_random_large_delays.228865513 |
| Short name | T596 |
| Test name | |
| Test status | |
| Simulation time | 61582856134 ps |
| CPU time | 671.11 seconds |
| Started | Jun 23 07:37:34 PM PDT 24 |
| Finished | Jun 23 07:48:46 PM PDT 24 |
| Peak memory | 573504 kb |
| Host | smart-e53d896b-86d8-49d4-b68e-4e3274d83dcd |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=228865513 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 77.xbar_random_large_delays.228865513 |
| Directory | /workspace/77.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/77.xbar_random_slow_rsp.4858914 |
| Short name | T671 |
| Test name | |
| Test status | |
| Simulation time | 32027986956 ps |
| CPU time | 565.69 seconds |
| Started | Jun 23 07:37:37 PM PDT 24 |
| Finished | Jun 23 07:47:03 PM PDT 24 |
| Peak memory | 574176 kb |
| Host | smart-06549272-bcec-463b-b40b-d4776b13294f |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4858914 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 77.xbar_random_slow_rsp.4858914 |
| Directory | /workspace/77.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/77.xbar_random_zero_delays.2762550739 |
| Short name | T1916 |
| Test name | |
| Test status | |
| Simulation time | 514324678 ps |
| CPU time | 42.52 seconds |
| Started | Jun 23 07:37:36 PM PDT 24 |
| Finished | Jun 23 07:38:19 PM PDT 24 |
| Peak memory | 574076 kb |
| Host | smart-f5394b80-1c96-47a4-adaa-3f018edc8c97 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2762550739 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 77.xbar_random_zero_del ays.2762550739 |
| Directory | /workspace/77.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/77.xbar_same_source.3654960305 |
| Short name | T2733 |
| Test name | |
| Test status | |
| Simulation time | 494483465 ps |
| CPU time | 31.6 seconds |
| Started | Jun 23 07:37:36 PM PDT 24 |
| Finished | Jun 23 07:38:08 PM PDT 24 |
| Peak memory | 574064 kb |
| Host | smart-bc0fc946-b548-4e2a-b964-28aa595b51d6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3654960305 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 77.xbar_same_source.3654960305 |
| Directory | /workspace/77.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/77.xbar_smoke.1297568797 |
| Short name | T1758 |
| Test name | |
| Test status | |
| Simulation time | 202844396 ps |
| CPU time | 8.84 seconds |
| Started | Jun 23 07:37:37 PM PDT 24 |
| Finished | Jun 23 07:37:46 PM PDT 24 |
| Peak memory | 565140 kb |
| Host | smart-db448b12-50ab-4a85-8d3a-13a4d35b2dae |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1297568797 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 77.xbar_smoke.1297568797 |
| Directory | /workspace/77.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/77.xbar_smoke_large_delays.4165272204 |
| Short name | T1377 |
| Test name | |
| Test status | |
| Simulation time | 7931043787 ps |
| CPU time | 85.88 seconds |
| Started | Jun 23 07:37:34 PM PDT 24 |
| Finished | Jun 23 07:39:01 PM PDT 24 |
| Peak memory | 565524 kb |
| Host | smart-682bac30-e3a8-4f84-a71e-a80a756bc014 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4165272204 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 77.xbar_smoke_large_delays.4165272204 |
| Directory | /workspace/77.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/77.xbar_smoke_slow_rsp.2196746322 |
| Short name | T2287 |
| Test name | |
| Test status | |
| Simulation time | 5625199288 ps |
| CPU time | 99.31 seconds |
| Started | Jun 23 07:37:35 PM PDT 24 |
| Finished | Jun 23 07:39:15 PM PDT 24 |
| Peak memory | 565544 kb |
| Host | smart-4791ab42-4ec1-4f0e-bf60-964496805a6f |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2196746322 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 77.xbar_smoke_slow_rsp.2196746322 |
| Directory | /workspace/77.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/77.xbar_smoke_zero_delays.895239116 |
| Short name | T1774 |
| Test name | |
| Test status | |
| Simulation time | 44491038 ps |
| CPU time | 6.21 seconds |
| Started | Jun 23 07:37:37 PM PDT 24 |
| Finished | Jun 23 07:37:43 PM PDT 24 |
| Peak memory | 565488 kb |
| Host | smart-f0d9c563-93b1-4c9b-b56a-8c2faf58d573 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=895239116 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 77.xbar_smoke_zero_delays .895239116 |
| Directory | /workspace/77.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/77.xbar_stress_all.628764856 |
| Short name | T2667 |
| Test name | |
| Test status | |
| Simulation time | 7625022589 ps |
| CPU time | 271.41 seconds |
| Started | Jun 23 07:37:36 PM PDT 24 |
| Finished | Jun 23 07:42:08 PM PDT 24 |
| Peak memory | 574248 kb |
| Host | smart-04e11ac7-b1a6-478d-9182-43ed353a7251 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=628764856 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 77.xbar_stress_all.628764856 |
| Directory | /workspace/77.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/77.xbar_stress_all_with_error.4014368030 |
| Short name | T1457 |
| Test name | |
| Test status | |
| Simulation time | 782241585 ps |
| CPU time | 60.89 seconds |
| Started | Jun 23 07:37:41 PM PDT 24 |
| Finished | Jun 23 07:38:42 PM PDT 24 |
| Peak memory | 573492 kb |
| Host | smart-abfa9025-71ea-4e79-9178-6df9b5ed3f4b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4014368030 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 77.xbar_stress_all_with_error.4014368030 |
| Directory | /workspace/77.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/77.xbar_stress_all_with_rand_reset.2160422274 |
| Short name | T2867 |
| Test name | |
| Test status | |
| Simulation time | 5852366041 ps |
| CPU time | 480.46 seconds |
| Started | Jun 23 07:37:37 PM PDT 24 |
| Finished | Jun 23 07:45:38 PM PDT 24 |
| Peak memory | 576320 kb |
| Host | smart-1ad84be3-f8da-46f1-8a54-b5b6c07d656d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2160422274 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 77.xbar_stress_all _with_rand_reset.2160422274 |
| Directory | /workspace/77.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/77.xbar_unmapped_addr.3979113379 |
| Short name | T1613 |
| Test name | |
| Test status | |
| Simulation time | 169529059 ps |
| CPU time | 20.45 seconds |
| Started | Jun 23 07:37:38 PM PDT 24 |
| Finished | Jun 23 07:37:58 PM PDT 24 |
| Peak memory | 574144 kb |
| Host | smart-129f4a8d-f7df-41c0-b6cf-d9dbeaffe14d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3979113379 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 77.xbar_unmapped_addr.3979113379 |
| Directory | /workspace/77.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/78.xbar_access_same_device.1675810599 |
| Short name | T2024 |
| Test name | |
| Test status | |
| Simulation time | 2271539333 ps |
| CPU time | 98.21 seconds |
| Started | Jun 23 07:37:43 PM PDT 24 |
| Finished | Jun 23 07:39:22 PM PDT 24 |
| Peak memory | 573528 kb |
| Host | smart-034555d7-1610-40bb-8203-4377666a13fa |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1675810599 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 78.xbar_access_same_device .1675810599 |
| Directory | /workspace/78.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/78.xbar_access_same_device_slow_rsp.346656376 |
| Short name | T2457 |
| Test name | |
| Test status | |
| Simulation time | 112831572979 ps |
| CPU time | 2183.57 seconds |
| Started | Jun 23 07:37:44 PM PDT 24 |
| Finished | Jun 23 08:14:08 PM PDT 24 |
| Peak memory | 574280 kb |
| Host | smart-2f2863e2-d934-4312-99c5-254de487fd2f |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=346656376 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 78.xbar_access_same_d evice_slow_rsp.346656376 |
| Directory | /workspace/78.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/78.xbar_error_and_unmapped_addr.3859329201 |
| Short name | T2715 |
| Test name | |
| Test status | |
| Simulation time | 1184501917 ps |
| CPU time | 48.2 seconds |
| Started | Jun 23 07:37:49 PM PDT 24 |
| Finished | Jun 23 07:38:38 PM PDT 24 |
| Peak memory | 573800 kb |
| Host | smart-0d244329-4ed9-4408-9099-8aa50bd7eef3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3859329201 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 78.xbar_error_and_unmapped_add r.3859329201 |
| Directory | /workspace/78.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/78.xbar_error_random.3161016641 |
| Short name | T2582 |
| Test name | |
| Test status | |
| Simulation time | 57439844 ps |
| CPU time | 7.03 seconds |
| Started | Jun 23 07:37:49 PM PDT 24 |
| Finished | Jun 23 07:37:56 PM PDT 24 |
| Peak memory | 565532 kb |
| Host | smart-35682e57-046a-4c13-89df-5df156abccd4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3161016641 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 78.xbar_error_random.3161016641 |
| Directory | /workspace/78.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/78.xbar_random.2273738221 |
| Short name | T2862 |
| Test name | |
| Test status | |
| Simulation time | 502318730 ps |
| CPU time | 21.42 seconds |
| Started | Jun 23 07:37:38 PM PDT 24 |
| Finished | Jun 23 07:38:00 PM PDT 24 |
| Peak memory | 573432 kb |
| Host | smart-2c0889bd-52a9-4f4c-9e62-bb016cb79f7d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2273738221 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 78.xbar_random.2273738221 |
| Directory | /workspace/78.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/78.xbar_random_large_delays.3152281918 |
| Short name | T2790 |
| Test name | |
| Test status | |
| Simulation time | 19648183359 ps |
| CPU time | 201.18 seconds |
| Started | Jun 23 07:37:50 PM PDT 24 |
| Finished | Jun 23 07:41:11 PM PDT 24 |
| Peak memory | 574164 kb |
| Host | smart-a71dffca-759d-4fc6-8335-1d9c5ca4f0a5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3152281918 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 78.xbar_random_large_delays.3152281918 |
| Directory | /workspace/78.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/78.xbar_random_slow_rsp.2496916055 |
| Short name | T1856 |
| Test name | |
| Test status | |
| Simulation time | 56280600737 ps |
| CPU time | 1051.84 seconds |
| Started | Jun 23 07:37:47 PM PDT 24 |
| Finished | Jun 23 07:55:19 PM PDT 24 |
| Peak memory | 573528 kb |
| Host | smart-c1e81aa6-c175-4c39-bd65-d14097f964a5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2496916055 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 78.xbar_random_slow_rsp.2496916055 |
| Directory | /workspace/78.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/78.xbar_random_zero_delays.3826627151 |
| Short name | T1757 |
| Test name | |
| Test status | |
| Simulation time | 552138259 ps |
| CPU time | 49.96 seconds |
| Started | Jun 23 07:37:41 PM PDT 24 |
| Finished | Jun 23 07:38:31 PM PDT 24 |
| Peak memory | 574108 kb |
| Host | smart-1908ceb1-ab70-44a0-bb66-58be45567db6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3826627151 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 78.xbar_random_zero_del ays.3826627151 |
| Directory | /workspace/78.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/78.xbar_same_source.3526616530 |
| Short name | T1754 |
| Test name | |
| Test status | |
| Simulation time | 1732568036 ps |
| CPU time | 50.64 seconds |
| Started | Jun 23 07:37:47 PM PDT 24 |
| Finished | Jun 23 07:38:38 PM PDT 24 |
| Peak memory | 574104 kb |
| Host | smart-3d7e2486-f199-42e0-8e1c-a67198644593 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3526616530 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 78.xbar_same_source.3526616530 |
| Directory | /workspace/78.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/78.xbar_smoke.2291549738 |
| Short name | T1438 |
| Test name | |
| Test status | |
| Simulation time | 203832108 ps |
| CPU time | 8.54 seconds |
| Started | Jun 23 07:37:38 PM PDT 24 |
| Finished | Jun 23 07:37:46 PM PDT 24 |
| Peak memory | 565656 kb |
| Host | smart-32aa5ce6-ba49-4858-ba31-52bc06e5c52a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2291549738 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 78.xbar_smoke.2291549738 |
| Directory | /workspace/78.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/78.xbar_smoke_large_delays.2342533765 |
| Short name | T1593 |
| Test name | |
| Test status | |
| Simulation time | 8429992906 ps |
| CPU time | 84.12 seconds |
| Started | Jun 23 07:37:42 PM PDT 24 |
| Finished | Jun 23 07:39:06 PM PDT 24 |
| Peak memory | 573476 kb |
| Host | smart-940172c1-1e4e-4d60-a60d-651b6206432f |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2342533765 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 78.xbar_smoke_large_delays.2342533765 |
| Directory | /workspace/78.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/78.xbar_smoke_slow_rsp.2663605054 |
| Short name | T2531 |
| Test name | |
| Test status | |
| Simulation time | 6633890598 ps |
| CPU time | 110.51 seconds |
| Started | Jun 23 07:37:41 PM PDT 24 |
| Finished | Jun 23 07:39:32 PM PDT 24 |
| Peak memory | 565908 kb |
| Host | smart-81166517-bd05-4460-b244-a3cee3c55b30 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2663605054 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 78.xbar_smoke_slow_rsp.2663605054 |
| Directory | /workspace/78.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/78.xbar_smoke_zero_delays.3658061028 |
| Short name | T607 |
| Test name | |
| Test status | |
| Simulation time | 46836226 ps |
| CPU time | 6.3 seconds |
| Started | Jun 23 07:37:39 PM PDT 24 |
| Finished | Jun 23 07:37:46 PM PDT 24 |
| Peak memory | 565540 kb |
| Host | smart-eda511fb-83af-43ae-9eb2-66dc02cc64e9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3658061028 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 78.xbar_smoke_zero_delay s.3658061028 |
| Directory | /workspace/78.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/78.xbar_stress_all.4274255271 |
| Short name | T482 |
| Test name | |
| Test status | |
| Simulation time | 11444272239 ps |
| CPU time | 412.75 seconds |
| Started | Jun 23 07:37:44 PM PDT 24 |
| Finished | Jun 23 07:44:38 PM PDT 24 |
| Peak memory | 574308 kb |
| Host | smart-007cdcbd-2e39-4528-ab11-ecb2d4631f49 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4274255271 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 78.xbar_stress_all.4274255271 |
| Directory | /workspace/78.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/78.xbar_stress_all_with_error.1072012353 |
| Short name | T2289 |
| Test name | |
| Test status | |
| Simulation time | 3090381533 ps |
| CPU time | 103.63 seconds |
| Started | Jun 23 07:37:58 PM PDT 24 |
| Finished | Jun 23 07:39:42 PM PDT 24 |
| Peak memory | 574208 kb |
| Host | smart-51d9cc83-8978-4070-a4ed-c4e85662af28 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1072012353 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 78.xbar_stress_all_with_error.1072012353 |
| Directory | /workspace/78.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/78.xbar_stress_all_with_rand_reset.2120808248 |
| Short name | T566 |
| Test name | |
| Test status | |
| Simulation time | 252344453 ps |
| CPU time | 170.18 seconds |
| Started | Jun 23 07:37:43 PM PDT 24 |
| Finished | Jun 23 07:40:34 PM PDT 24 |
| Peak memory | 575236 kb |
| Host | smart-86854ae2-9f84-43c3-8231-94cbe84fd9f2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2120808248 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 78.xbar_stress_all _with_rand_reset.2120808248 |
| Directory | /workspace/78.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/78.xbar_stress_all_with_reset_error.1100918458 |
| Short name | T893 |
| Test name | |
| Test status | |
| Simulation time | 1033703451 ps |
| CPU time | 130.62 seconds |
| Started | Jun 23 07:37:48 PM PDT 24 |
| Finished | Jun 23 07:39:59 PM PDT 24 |
| Peak memory | 576356 kb |
| Host | smart-021b60ac-e5c2-48b5-aa7b-46e646ae149f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1100918458 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 78.xbar_stress_al l_with_reset_error.1100918458 |
| Directory | /workspace/78.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/78.xbar_unmapped_addr.3132321970 |
| Short name | T2322 |
| Test name | |
| Test status | |
| Simulation time | 182969462 ps |
| CPU time | 21.31 seconds |
| Started | Jun 23 07:37:46 PM PDT 24 |
| Finished | Jun 23 07:38:08 PM PDT 24 |
| Peak memory | 574152 kb |
| Host | smart-263cca8a-aec0-4b6e-abee-f6e0d34f4299 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3132321970 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 78.xbar_unmapped_addr.3132321970 |
| Directory | /workspace/78.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/79.xbar_access_same_device.1445842247 |
| Short name | T1629 |
| Test name | |
| Test status | |
| Simulation time | 1611980396 ps |
| CPU time | 78.54 seconds |
| Started | Jun 23 07:37:56 PM PDT 24 |
| Finished | Jun 23 07:39:15 PM PDT 24 |
| Peak memory | 574164 kb |
| Host | smart-c7c8cc9a-f8c0-4b2b-abfc-87023de5e93b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1445842247 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 79.xbar_access_same_device .1445842247 |
| Directory | /workspace/79.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/79.xbar_access_same_device_slow_rsp.2014177590 |
| Short name | T2517 |
| Test name | |
| Test status | |
| Simulation time | 89840608197 ps |
| CPU time | 1732.45 seconds |
| Started | Jun 23 07:37:58 PM PDT 24 |
| Finished | Jun 23 08:06:51 PM PDT 24 |
| Peak memory | 573660 kb |
| Host | smart-d24a683f-4732-4b2d-a8b9-d86376d25e2d |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2014177590 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 79.xbar_access_same_ device_slow_rsp.2014177590 |
| Directory | /workspace/79.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/79.xbar_error_and_unmapped_addr.1172449815 |
| Short name | T2564 |
| Test name | |
| Test status | |
| Simulation time | 1172436789 ps |
| CPU time | 47.33 seconds |
| Started | Jun 23 07:37:59 PM PDT 24 |
| Finished | Jun 23 07:38:46 PM PDT 24 |
| Peak memory | 573564 kb |
| Host | smart-94ab60d6-7dd8-4477-9499-0a384c925904 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1172449815 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 79.xbar_error_and_unmapped_add r.1172449815 |
| Directory | /workspace/79.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/79.xbar_error_random.987075689 |
| Short name | T2820 |
| Test name | |
| Test status | |
| Simulation time | 129255475 ps |
| CPU time | 12.68 seconds |
| Started | Jun 23 07:38:00 PM PDT 24 |
| Finished | Jun 23 07:38:13 PM PDT 24 |
| Peak memory | 573720 kb |
| Host | smart-7a6bf293-3fba-4a6d-90fd-6b5b17e49a47 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=987075689 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 79.xbar_error_random.987075689 |
| Directory | /workspace/79.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/79.xbar_random.3682160415 |
| Short name | T1447 |
| Test name | |
| Test status | |
| Simulation time | 326024599 ps |
| CPU time | 28.05 seconds |
| Started | Jun 23 07:37:49 PM PDT 24 |
| Finished | Jun 23 07:38:17 PM PDT 24 |
| Peak memory | 574096 kb |
| Host | smart-bda506b2-69c8-4076-b209-dccd10476912 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3682160415 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 79.xbar_random.3682160415 |
| Directory | /workspace/79.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/79.xbar_random_large_delays.727700495 |
| Short name | T1903 |
| Test name | |
| Test status | |
| Simulation time | 22791852803 ps |
| CPU time | 245.87 seconds |
| Started | Jun 23 07:37:47 PM PDT 24 |
| Finished | Jun 23 07:41:53 PM PDT 24 |
| Peak memory | 574172 kb |
| Host | smart-82e53b32-f1c6-444f-8d15-4266084879be |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=727700495 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 79.xbar_random_large_delays.727700495 |
| Directory | /workspace/79.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/79.xbar_random_slow_rsp.1642045401 |
| Short name | T638 |
| Test name | |
| Test status | |
| Simulation time | 20627307276 ps |
| CPU time | 371.97 seconds |
| Started | Jun 23 07:37:58 PM PDT 24 |
| Finished | Jun 23 07:44:10 PM PDT 24 |
| Peak memory | 573476 kb |
| Host | smart-23b3673f-a572-44cf-a554-dab3768fb84a |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1642045401 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 79.xbar_random_slow_rsp.1642045401 |
| Directory | /workspace/79.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/79.xbar_random_zero_delays.2900595601 |
| Short name | T2421 |
| Test name | |
| Test status | |
| Simulation time | 225531150 ps |
| CPU time | 21.82 seconds |
| Started | Jun 23 07:37:48 PM PDT 24 |
| Finished | Jun 23 07:38:10 PM PDT 24 |
| Peak memory | 574076 kb |
| Host | smart-69c9db61-6052-4052-b263-5eadd39ee801 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2900595601 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 79.xbar_random_zero_del ays.2900595601 |
| Directory | /workspace/79.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/79.xbar_same_source.3459491957 |
| Short name | T2219 |
| Test name | |
| Test status | |
| Simulation time | 184809924 ps |
| CPU time | 15.74 seconds |
| Started | Jun 23 07:38:00 PM PDT 24 |
| Finished | Jun 23 07:38:16 PM PDT 24 |
| Peak memory | 573968 kb |
| Host | smart-8c46cfc7-e65f-4ca1-b0d3-a7d1dc57176b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3459491957 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 79.xbar_same_source.3459491957 |
| Directory | /workspace/79.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/79.xbar_smoke.3474999890 |
| Short name | T1752 |
| Test name | |
| Test status | |
| Simulation time | 176828768 ps |
| CPU time | 7.69 seconds |
| Started | Jun 23 07:37:49 PM PDT 24 |
| Finished | Jun 23 07:37:57 PM PDT 24 |
| Peak memory | 565480 kb |
| Host | smart-734fa555-9746-415f-8794-ffb18c644d63 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3474999890 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 79.xbar_smoke.3474999890 |
| Directory | /workspace/79.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/79.xbar_smoke_large_delays.3197664369 |
| Short name | T1711 |
| Test name | |
| Test status | |
| Simulation time | 8020277731 ps |
| CPU time | 79.2 seconds |
| Started | Jun 23 07:37:58 PM PDT 24 |
| Finished | Jun 23 07:39:18 PM PDT 24 |
| Peak memory | 565540 kb |
| Host | smart-542a6501-4da7-4731-9f5c-2b11c309953e |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3197664369 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 79.xbar_smoke_large_delays.3197664369 |
| Directory | /workspace/79.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/79.xbar_smoke_slow_rsp.1740598115 |
| Short name | T1397 |
| Test name | |
| Test status | |
| Simulation time | 5331826114 ps |
| CPU time | 89.94 seconds |
| Started | Jun 23 07:37:47 PM PDT 24 |
| Finished | Jun 23 07:39:17 PM PDT 24 |
| Peak memory | 565844 kb |
| Host | smart-4d21e53f-dbb3-43c7-aab8-61465148097e |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1740598115 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 79.xbar_smoke_slow_rsp.1740598115 |
| Directory | /workspace/79.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/79.xbar_smoke_zero_delays.3047063777 |
| Short name | T1925 |
| Test name | |
| Test status | |
| Simulation time | 51561005 ps |
| CPU time | 6.45 seconds |
| Started | Jun 23 07:37:47 PM PDT 24 |
| Finished | Jun 23 07:37:54 PM PDT 24 |
| Peak memory | 573736 kb |
| Host | smart-c85e5616-4218-4865-a64c-8b2153ea6cae |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3047063777 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 79.xbar_smoke_zero_delay s.3047063777 |
| Directory | /workspace/79.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/79.xbar_stress_all.3352970324 |
| Short name | T2868 |
| Test name | |
| Test status | |
| Simulation time | 1383098511 ps |
| CPU time | 118.39 seconds |
| Started | Jun 23 07:38:00 PM PDT 24 |
| Finished | Jun 23 07:39:59 PM PDT 24 |
| Peak memory | 574236 kb |
| Host | smart-30b8fede-b362-4a4c-a969-3798fd929acb |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3352970324 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 79.xbar_stress_all.3352970324 |
| Directory | /workspace/79.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/79.xbar_stress_all_with_error.3987900955 |
| Short name | T847 |
| Test name | |
| Test status | |
| Simulation time | 9104258433 ps |
| CPU time | 283.01 seconds |
| Started | Jun 23 07:38:04 PM PDT 24 |
| Finished | Jun 23 07:42:48 PM PDT 24 |
| Peak memory | 574348 kb |
| Host | smart-99fa6eb1-5941-47c5-84fe-4215ffab9029 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3987900955 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 79.xbar_stress_all_with_error.3987900955 |
| Directory | /workspace/79.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/79.xbar_stress_all_with_rand_reset.2036784593 |
| Short name | T2519 |
| Test name | |
| Test status | |
| Simulation time | 642148895 ps |
| CPU time | 349.12 seconds |
| Started | Jun 23 07:38:11 PM PDT 24 |
| Finished | Jun 23 07:44:00 PM PDT 24 |
| Peak memory | 576304 kb |
| Host | smart-54502426-46b4-43f2-92cc-b7c3a93e18a7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2036784593 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 79.xbar_stress_all _with_rand_reset.2036784593 |
| Directory | /workspace/79.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/79.xbar_stress_all_with_reset_error.2208293371 |
| Short name | T2834 |
| Test name | |
| Test status | |
| Simulation time | 91270635 ps |
| CPU time | 36.29 seconds |
| Started | Jun 23 07:38:10 PM PDT 24 |
| Finished | Jun 23 07:38:46 PM PDT 24 |
| Peak memory | 575844 kb |
| Host | smart-a2748e91-8b42-455d-9a47-0071754517c5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2208293371 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 79.xbar_stress_al l_with_reset_error.2208293371 |
| Directory | /workspace/79.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/79.xbar_unmapped_addr.2364322018 |
| Short name | T2369 |
| Test name | |
| Test status | |
| Simulation time | 1303963746 ps |
| CPU time | 52.54 seconds |
| Started | Jun 23 07:37:59 PM PDT 24 |
| Finished | Jun 23 07:38:51 PM PDT 24 |
| Peak memory | 573396 kb |
| Host | smart-c5227553-2bfc-4c17-a861-be1bf897dcea |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2364322018 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 79.xbar_unmapped_addr.2364322018 |
| Directory | /workspace/79.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/8.chip_csr_rw.1166506618 |
| Short name | T1839 |
| Test name | |
| Test status | |
| Simulation time | 4936144860 ps |
| CPU time | 328.8 seconds |
| Started | Jun 23 07:22:38 PM PDT 24 |
| Finished | Jun 23 07:28:07 PM PDT 24 |
| Peak memory | 595140 kb |
| Host | smart-46831efc-27b1-431e-bfa6-ad1813509fa3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1166506618 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.chip_csr_rw.1166506618 |
| Directory | /workspace/8.chip_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/8.chip_same_csr_outstanding.1797281181 |
| Short name | T401 |
| Test name | |
| Test status | |
| Simulation time | 30947332603 ps |
| CPU time | 4922.03 seconds |
| Started | Jun 23 07:22:37 PM PDT 24 |
| Finished | Jun 23 08:44:40 PM PDT 24 |
| Peak memory | 591348 kb |
| Host | smart-5389550d-5df2-48b8-b5f8-9d06dc7e229e |
| User | root |
| Command | /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +run_same_csr_outstanding +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1797281181 -assert nopostproc +UVM_TE STNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb - cm_log /dev/null -cm_name 8.chip_same_csr_outstanding.1797281181 |
| Directory | /workspace/8.chip_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/8.chip_tl_errors.2661691825 |
| Short name | T2774 |
| Test name | |
| Test status | |
| Simulation time | 3378627379 ps |
| CPU time | 285.49 seconds |
| Started | Jun 23 07:22:27 PM PDT 24 |
| Finished | Jun 23 07:27:13 PM PDT 24 |
| Peak memory | 597760 kb |
| Host | smart-78c08455-208b-4cfd-9bce-553d38f4ae95 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2661691825 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.chip_tl_errors.2661691825 |
| Directory | /workspace/8.chip_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/8.xbar_access_same_device.3903116434 |
| Short name | T2411 |
| Test name | |
| Test status | |
| Simulation time | 3039998789 ps |
| CPU time | 111.33 seconds |
| Started | Jun 23 07:22:32 PM PDT 24 |
| Finished | Jun 23 07:24:24 PM PDT 24 |
| Peak memory | 574220 kb |
| Host | smart-13d13ff5-a8af-4bc2-9051-98fd9d606a81 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3903116434 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.xbar_access_same_device. 3903116434 |
| Directory | /workspace/8.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/8.xbar_access_same_device_slow_rsp.1244165312 |
| Short name | T1857 |
| Test name | |
| Test status | |
| Simulation time | 98037910998 ps |
| CPU time | 1739.08 seconds |
| Started | Jun 23 07:22:34 PM PDT 24 |
| Finished | Jun 23 07:51:33 PM PDT 24 |
| Peak memory | 574260 kb |
| Host | smart-2c49b1dd-f8f4-4ad4-8fa9-fdc1156752b2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1244165312 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.xbar_access_same_d evice_slow_rsp.1244165312 |
| Directory | /workspace/8.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/8.xbar_error_and_unmapped_addr.2499681856 |
| Short name | T2716 |
| Test name | |
| Test status | |
| Simulation time | 80486625 ps |
| CPU time | 11.73 seconds |
| Started | Jun 23 07:22:38 PM PDT 24 |
| Finished | Jun 23 07:22:51 PM PDT 24 |
| Peak memory | 573380 kb |
| Host | smart-f6de7e94-d3f3-40c4-86d8-e64942775ba6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2499681856 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.xbar_error_and_unmapped_addr .2499681856 |
| Directory | /workspace/8.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/8.xbar_error_random.631765067 |
| Short name | T2845 |
| Test name | |
| Test status | |
| Simulation time | 2398004435 ps |
| CPU time | 82.31 seconds |
| Started | Jun 23 07:22:34 PM PDT 24 |
| Finished | Jun 23 07:23:56 PM PDT 24 |
| Peak memory | 573372 kb |
| Host | smart-e57612f0-5b3e-4a73-84b3-6b3ed712cdb1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=631765067 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.xbar_error_random.631765067 |
| Directory | /workspace/8.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/8.xbar_random.667840036 |
| Short name | T515 |
| Test name | |
| Test status | |
| Simulation time | 948857228 ps |
| CPU time | 32.32 seconds |
| Started | Jun 23 07:22:32 PM PDT 24 |
| Finished | Jun 23 07:23:05 PM PDT 24 |
| Peak memory | 574080 kb |
| Host | smart-ed5c8cbf-206d-49d6-a654-063ee6156b0e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=667840036 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.xbar_random.667840036 |
| Directory | /workspace/8.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/8.xbar_random_large_delays.2770006978 |
| Short name | T676 |
| Test name | |
| Test status | |
| Simulation time | 11859265414 ps |
| CPU time | 124.64 seconds |
| Started | Jun 23 07:22:36 PM PDT 24 |
| Finished | Jun 23 07:24:41 PM PDT 24 |
| Peak memory | 574196 kb |
| Host | smart-1abf5864-808a-432b-be26-3359b214b571 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2770006978 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.xbar_random_large_delays.2770006978 |
| Directory | /workspace/8.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/8.xbar_random_slow_rsp.890646643 |
| Short name | T1762 |
| Test name | |
| Test status | |
| Simulation time | 42373223240 ps |
| CPU time | 682.84 seconds |
| Started | Jun 23 07:22:33 PM PDT 24 |
| Finished | Jun 23 07:33:57 PM PDT 24 |
| Peak memory | 574188 kb |
| Host | smart-b006e875-76b1-42dd-ace2-993b945e60a7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=890646643 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.xbar_random_slow_rsp.890646643 |
| Directory | /workspace/8.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/8.xbar_random_zero_delays.3184447174 |
| Short name | T1674 |
| Test name | |
| Test status | |
| Simulation time | 465252934 ps |
| CPU time | 40.36 seconds |
| Started | Jun 23 07:22:34 PM PDT 24 |
| Finished | Jun 23 07:23:15 PM PDT 24 |
| Peak memory | 573836 kb |
| Host | smart-f0d6fb89-5292-44d9-b4eb-7f9cf5dca40d |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3184447174 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.xbar_random_zero_dela ys.3184447174 |
| Directory | /workspace/8.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/8.xbar_same_source.1615131477 |
| Short name | T1413 |
| Test name | |
| Test status | |
| Simulation time | 264691280 ps |
| CPU time | 11.35 seconds |
| Started | Jun 23 07:22:33 PM PDT 24 |
| Finished | Jun 23 07:22:45 PM PDT 24 |
| Peak memory | 573664 kb |
| Host | smart-b96e950a-3c99-4d67-907f-3b49993489f4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1615131477 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.xbar_same_source.1615131477 |
| Directory | /workspace/8.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/8.xbar_smoke.181708176 |
| Short name | T1789 |
| Test name | |
| Test status | |
| Simulation time | 183203131 ps |
| CPU time | 8.57 seconds |
| Started | Jun 23 07:22:27 PM PDT 24 |
| Finished | Jun 23 07:22:36 PM PDT 24 |
| Peak memory | 565452 kb |
| Host | smart-49d5a377-4a8f-4c6b-983a-5a99111969bb |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=181708176 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.xbar_smoke.181708176 |
| Directory | /workspace/8.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/8.xbar_smoke_large_delays.4139478165 |
| Short name | T631 |
| Test name | |
| Test status | |
| Simulation time | 8322693864 ps |
| CPU time | 85.02 seconds |
| Started | Jun 23 07:22:34 PM PDT 24 |
| Finished | Jun 23 07:24:00 PM PDT 24 |
| Peak memory | 565560 kb |
| Host | smart-10d8761e-1cb5-473a-b1e4-5175b81584d8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4139478165 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.xbar_smoke_large_delays.4139478165 |
| Directory | /workspace/8.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/8.xbar_smoke_slow_rsp.1925609687 |
| Short name | T2006 |
| Test name | |
| Test status | |
| Simulation time | 4379714867 ps |
| CPU time | 74.72 seconds |
| Started | Jun 23 07:22:34 PM PDT 24 |
| Finished | Jun 23 07:23:49 PM PDT 24 |
| Peak memory | 565912 kb |
| Host | smart-5cbb3b26-0c8f-4b76-8f23-7f80e2a2fb5e |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1925609687 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.xbar_smoke_slow_rsp.1925609687 |
| Directory | /workspace/8.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/8.xbar_smoke_zero_delays.2413446312 |
| Short name | T2578 |
| Test name | |
| Test status | |
| Simulation time | 53608825 ps |
| CPU time | 6.18 seconds |
| Started | Jun 23 07:22:34 PM PDT 24 |
| Finished | Jun 23 07:22:41 PM PDT 24 |
| Peak memory | 565540 kb |
| Host | smart-7bc34de0-703d-4fbb-b4cd-aa90400b92b0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2413446312 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.xbar_smoke_zero_delays .2413446312 |
| Directory | /workspace/8.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/8.xbar_stress_all.4264665362 |
| Short name | T2477 |
| Test name | |
| Test status | |
| Simulation time | 4472159291 ps |
| CPU time | 161.33 seconds |
| Started | Jun 23 07:22:39 PM PDT 24 |
| Finished | Jun 23 07:25:21 PM PDT 24 |
| Peak memory | 574304 kb |
| Host | smart-1f2d94f0-f92c-493e-9a4e-c66c035865e4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4264665362 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.xbar_stress_all.4264665362 |
| Directory | /workspace/8.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/8.xbar_stress_all_with_error.3262639055 |
| Short name | T731 |
| Test name | |
| Test status | |
| Simulation time | 9323672187 ps |
| CPU time | 329.69 seconds |
| Started | Jun 23 07:22:37 PM PDT 24 |
| Finished | Jun 23 07:28:07 PM PDT 24 |
| Peak memory | 574364 kb |
| Host | smart-62a64116-38e8-4c0f-a8b4-d55bb06ebfdb |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3262639055 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.xbar_stress_all_with_error.3262639055 |
| Directory | /workspace/8.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/8.xbar_stress_all_with_rand_reset.2564985254 |
| Short name | T2636 |
| Test name | |
| Test status | |
| Simulation time | 6598659396 ps |
| CPU time | 680.32 seconds |
| Started | Jun 23 07:22:46 PM PDT 24 |
| Finished | Jun 23 07:34:07 PM PDT 24 |
| Peak memory | 574300 kb |
| Host | smart-0f2bc4fd-eef0-4eba-afe4-81005f5f8bba |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2564985254 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.xbar_stress_all_ with_rand_reset.2564985254 |
| Directory | /workspace/8.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/8.xbar_stress_all_with_reset_error.3711587269 |
| Short name | T1872 |
| Test name | |
| Test status | |
| Simulation time | 77629923 ps |
| CPU time | 13.4 seconds |
| Started | Jun 23 07:22:38 PM PDT 24 |
| Finished | Jun 23 07:22:52 PM PDT 24 |
| Peak memory | 566016 kb |
| Host | smart-858db625-cdfc-4343-8f63-374786b015d8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3711587269 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.xbar_stress_all _with_reset_error.3711587269 |
| Directory | /workspace/8.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/8.xbar_unmapped_addr.288510591 |
| Short name | T1863 |
| Test name | |
| Test status | |
| Simulation time | 271991122 ps |
| CPU time | 33.83 seconds |
| Started | Jun 23 07:22:39 PM PDT 24 |
| Finished | Jun 23 07:23:13 PM PDT 24 |
| Peak memory | 573428 kb |
| Host | smart-f52592ef-b8d9-42d9-87c2-60a38f580637 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=288510591 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.xbar_unmapped_addr.288510591 |
| Directory | /workspace/8.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/80.xbar_access_same_device.4097480418 |
| Short name | T2504 |
| Test name | |
| Test status | |
| Simulation time | 1275324129 ps |
| CPU time | 61.64 seconds |
| Started | Jun 23 07:38:03 PM PDT 24 |
| Finished | Jun 23 07:39:04 PM PDT 24 |
| Peak memory | 574076 kb |
| Host | smart-70d62437-5f55-4dfc-85ec-2c8eb3f0300d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4097480418 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 80.xbar_access_same_device .4097480418 |
| Directory | /workspace/80.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/80.xbar_access_same_device_slow_rsp.3197788719 |
| Short name | T1753 |
| Test name | |
| Test status | |
| Simulation time | 111795895412 ps |
| CPU time | 2103.56 seconds |
| Started | Jun 23 07:38:13 PM PDT 24 |
| Finished | Jun 23 08:13:18 PM PDT 24 |
| Peak memory | 574280 kb |
| Host | smart-365e4ead-36b6-40f2-abf1-d8a57781b84a |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3197788719 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 80.xbar_access_same_ device_slow_rsp.3197788719 |
| Directory | /workspace/80.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/80.xbar_error_and_unmapped_addr.3846574475 |
| Short name | T1939 |
| Test name | |
| Test status | |
| Simulation time | 572719923 ps |
| CPU time | 22.16 seconds |
| Started | Jun 23 07:38:03 PM PDT 24 |
| Finished | Jun 23 07:38:26 PM PDT 24 |
| Peak memory | 573732 kb |
| Host | smart-aa63ade3-23df-4dfa-b84b-daf2af225a17 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3846574475 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 80.xbar_error_and_unmapped_add r.3846574475 |
| Directory | /workspace/80.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/80.xbar_error_random.1939665517 |
| Short name | T1436 |
| Test name | |
| Test status | |
| Simulation time | 2060322223 ps |
| CPU time | 75.19 seconds |
| Started | Jun 23 07:38:25 PM PDT 24 |
| Finished | Jun 23 07:39:40 PM PDT 24 |
| Peak memory | 573340 kb |
| Host | smart-4b15081d-4898-4820-918d-c9d88a6283f7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1939665517 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 80.xbar_error_random.1939665517 |
| Directory | /workspace/80.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/80.xbar_random.467556592 |
| Short name | T2336 |
| Test name | |
| Test status | |
| Simulation time | 1329782753 ps |
| CPU time | 43.61 seconds |
| Started | Jun 23 07:38:02 PM PDT 24 |
| Finished | Jun 23 07:38:45 PM PDT 24 |
| Peak memory | 574120 kb |
| Host | smart-c09788d1-3137-4fb2-8658-79eb462d0b5b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=467556592 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 80.xbar_random.467556592 |
| Directory | /workspace/80.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/80.xbar_random_large_delays.2967030303 |
| Short name | T2148 |
| Test name | |
| Test status | |
| Simulation time | 86938493040 ps |
| CPU time | 1013.19 seconds |
| Started | Jun 23 07:38:08 PM PDT 24 |
| Finished | Jun 23 07:55:02 PM PDT 24 |
| Peak memory | 574192 kb |
| Host | smart-184dd7a5-a4e0-4ac8-abcb-f1b97e822973 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2967030303 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 80.xbar_random_large_delays.2967030303 |
| Directory | /workspace/80.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/80.xbar_random_slow_rsp.3085966860 |
| Short name | T2861 |
| Test name | |
| Test status | |
| Simulation time | 41213122317 ps |
| CPU time | 730.5 seconds |
| Started | Jun 23 07:38:05 PM PDT 24 |
| Finished | Jun 23 07:50:16 PM PDT 24 |
| Peak memory | 574188 kb |
| Host | smart-d5b1dfc6-8400-4e43-892c-c09bcbe03262 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3085966860 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 80.xbar_random_slow_rsp.3085966860 |
| Directory | /workspace/80.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/80.xbar_random_zero_delays.1838297330 |
| Short name | T2030 |
| Test name | |
| Test status | |
| Simulation time | 529309273 ps |
| CPU time | 46.58 seconds |
| Started | Jun 23 07:38:09 PM PDT 24 |
| Finished | Jun 23 07:38:56 PM PDT 24 |
| Peak memory | 574028 kb |
| Host | smart-ec8bed9a-fd35-4f60-9fe1-b0bb8d9a772d |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1838297330 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 80.xbar_random_zero_del ays.1838297330 |
| Directory | /workspace/80.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/80.xbar_same_source.467520077 |
| Short name | T2734 |
| Test name | |
| Test status | |
| Simulation time | 539522938 ps |
| CPU time | 17.83 seconds |
| Started | Jun 23 07:38:02 PM PDT 24 |
| Finished | Jun 23 07:38:20 PM PDT 24 |
| Peak memory | 574120 kb |
| Host | smart-d8f584a7-b97c-4097-8624-c4fc9efc7abe |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=467520077 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 80.xbar_same_source.467520077 |
| Directory | /workspace/80.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/80.xbar_smoke.1475232796 |
| Short name | T1371 |
| Test name | |
| Test status | |
| Simulation time | 193263001 ps |
| CPU time | 8.48 seconds |
| Started | Jun 23 07:38:03 PM PDT 24 |
| Finished | Jun 23 07:38:11 PM PDT 24 |
| Peak memory | 565176 kb |
| Host | smart-3a215dde-4148-4e7a-8417-39d94a9dd49e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1475232796 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 80.xbar_smoke.1475232796 |
| Directory | /workspace/80.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/80.xbar_smoke_large_delays.2819652615 |
| Short name | T1521 |
| Test name | |
| Test status | |
| Simulation time | 7411811731 ps |
| CPU time | 79.44 seconds |
| Started | Jun 23 07:38:11 PM PDT 24 |
| Finished | Jun 23 07:39:31 PM PDT 24 |
| Peak memory | 565204 kb |
| Host | smart-9ac5e9c0-290b-4b5d-86f6-2eef1dd0176b |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2819652615 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 80.xbar_smoke_large_delays.2819652615 |
| Directory | /workspace/80.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/80.xbar_smoke_slow_rsp.831124985 |
| Short name | T1865 |
| Test name | |
| Test status | |
| Simulation time | 3276195980 ps |
| CPU time | 54.82 seconds |
| Started | Jun 23 07:38:04 PM PDT 24 |
| Finished | Jun 23 07:38:59 PM PDT 24 |
| Peak memory | 565548 kb |
| Host | smart-cb968ced-830b-40dc-884b-048e32405302 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=831124985 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 80.xbar_smoke_slow_rsp.831124985 |
| Directory | /workspace/80.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/80.xbar_smoke_zero_delays.2367293253 |
| Short name | T2058 |
| Test name | |
| Test status | |
| Simulation time | 51724179 ps |
| CPU time | 6.87 seconds |
| Started | Jun 23 07:38:03 PM PDT 24 |
| Finished | Jun 23 07:38:10 PM PDT 24 |
| Peak memory | 565532 kb |
| Host | smart-cd9ddb0a-7329-47b3-8e04-f979e1109a63 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2367293253 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 80.xbar_smoke_zero_delay s.2367293253 |
| Directory | /workspace/80.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/80.xbar_stress_all.1585773507 |
| Short name | T2593 |
| Test name | |
| Test status | |
| Simulation time | 5223902478 ps |
| CPU time | 189.84 seconds |
| Started | Jun 23 07:38:02 PM PDT 24 |
| Finished | Jun 23 07:41:12 PM PDT 24 |
| Peak memory | 574252 kb |
| Host | smart-53e8132f-4717-4edc-b353-3e7b0b8e1fcd |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1585773507 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 80.xbar_stress_all.1585773507 |
| Directory | /workspace/80.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/80.xbar_stress_all_with_error.2890991089 |
| Short name | T622 |
| Test name | |
| Test status | |
| Simulation time | 7241231352 ps |
| CPU time | 251.6 seconds |
| Started | Jun 23 07:38:08 PM PDT 24 |
| Finished | Jun 23 07:42:20 PM PDT 24 |
| Peak memory | 574384 kb |
| Host | smart-2ca1aa48-e249-4e67-86e0-27ad62e88297 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2890991089 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 80.xbar_stress_all_with_error.2890991089 |
| Directory | /workspace/80.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/80.xbar_stress_all_with_rand_reset.2425937520 |
| Short name | T2819 |
| Test name | |
| Test status | |
| Simulation time | 3850253115 ps |
| CPU time | 207.01 seconds |
| Started | Jun 23 07:38:08 PM PDT 24 |
| Finished | Jun 23 07:41:36 PM PDT 24 |
| Peak memory | 575464 kb |
| Host | smart-177922be-7a43-4a39-a09f-f1b33cc68902 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2425937520 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 80.xbar_stress_all _with_rand_reset.2425937520 |
| Directory | /workspace/80.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/80.xbar_stress_all_with_reset_error.1027148433 |
| Short name | T2330 |
| Test name | |
| Test status | |
| Simulation time | 5668308418 ps |
| CPU time | 347.67 seconds |
| Started | Jun 23 07:38:25 PM PDT 24 |
| Finished | Jun 23 07:44:13 PM PDT 24 |
| Peak memory | 576412 kb |
| Host | smart-5f92e9ba-0426-42b3-9124-bccd2f3c6c0d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1027148433 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 80.xbar_stress_al l_with_reset_error.1027148433 |
| Directory | /workspace/80.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/80.xbar_unmapped_addr.1957361099 |
| Short name | T1510 |
| Test name | |
| Test status | |
| Simulation time | 1394557710 ps |
| CPU time | 59.9 seconds |
| Started | Jun 23 07:38:05 PM PDT 24 |
| Finished | Jun 23 07:39:05 PM PDT 24 |
| Peak memory | 573468 kb |
| Host | smart-868b4415-2cc1-4ef3-a884-0201053c7b1b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1957361099 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 80.xbar_unmapped_addr.1957361099 |
| Directory | /workspace/80.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/81.xbar_access_same_device.1963555534 |
| Short name | T2757 |
| Test name | |
| Test status | |
| Simulation time | 3096429307 ps |
| CPU time | 122.92 seconds |
| Started | Jun 23 07:38:10 PM PDT 24 |
| Finished | Jun 23 07:40:13 PM PDT 24 |
| Peak memory | 574216 kb |
| Host | smart-99539bcd-99dd-4dc7-9011-cc361527a3ba |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1963555534 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 81.xbar_access_same_device .1963555534 |
| Directory | /workspace/81.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/81.xbar_access_same_device_slow_rsp.1556215365 |
| Short name | T857 |
| Test name | |
| Test status | |
| Simulation time | 41465144980 ps |
| CPU time | 725.37 seconds |
| Started | Jun 23 07:38:25 PM PDT 24 |
| Finished | Jun 23 07:50:31 PM PDT 24 |
| Peak memory | 574188 kb |
| Host | smart-d94cb8b2-a913-4882-8167-61b889c42d85 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1556215365 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 81.xbar_access_same_ device_slow_rsp.1556215365 |
| Directory | /workspace/81.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/81.xbar_error_and_unmapped_addr.3258673704 |
| Short name | T2839 |
| Test name | |
| Test status | |
| Simulation time | 75487803 ps |
| CPU time | 10.49 seconds |
| Started | Jun 23 07:38:30 PM PDT 24 |
| Finished | Jun 23 07:38:41 PM PDT 24 |
| Peak memory | 573728 kb |
| Host | smart-7ef8adff-5514-4119-bc57-4ea0e34f82d5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3258673704 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 81.xbar_error_and_unmapped_add r.3258673704 |
| Directory | /workspace/81.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/81.xbar_error_random.2737261600 |
| Short name | T1892 |
| Test name | |
| Test status | |
| Simulation time | 523044298 ps |
| CPU time | 44.74 seconds |
| Started | Jun 23 07:38:08 PM PDT 24 |
| Finished | Jun 23 07:38:53 PM PDT 24 |
| Peak memory | 573360 kb |
| Host | smart-cd3ccf4a-19e0-4ae7-8c67-8615a1fec62b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2737261600 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 81.xbar_error_random.2737261600 |
| Directory | /workspace/81.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/81.xbar_random.2754243295 |
| Short name | T2121 |
| Test name | |
| Test status | |
| Simulation time | 2505460850 ps |
| CPU time | 95.16 seconds |
| Started | Jun 23 07:38:08 PM PDT 24 |
| Finished | Jun 23 07:39:43 PM PDT 24 |
| Peak memory | 574188 kb |
| Host | smart-2be56af6-bedd-4e8d-adf9-524122e48b0d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2754243295 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 81.xbar_random.2754243295 |
| Directory | /workspace/81.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/81.xbar_random_large_delays.4150011121 |
| Short name | T2223 |
| Test name | |
| Test status | |
| Simulation time | 33342379379 ps |
| CPU time | 355.9 seconds |
| Started | Jun 23 07:38:07 PM PDT 24 |
| Finished | Jun 23 07:44:03 PM PDT 24 |
| Peak memory | 574200 kb |
| Host | smart-373444f9-a299-4535-9b40-811588867feb |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4150011121 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 81.xbar_random_large_delays.4150011121 |
| Directory | /workspace/81.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/81.xbar_random_slow_rsp.2386523542 |
| Short name | T609 |
| Test name | |
| Test status | |
| Simulation time | 42880950788 ps |
| CPU time | 737.49 seconds |
| Started | Jun 23 07:38:24 PM PDT 24 |
| Finished | Jun 23 07:50:42 PM PDT 24 |
| Peak memory | 574156 kb |
| Host | smart-818caef9-7eac-45f8-a70b-8a64ab33fb17 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2386523542 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 81.xbar_random_slow_rsp.2386523542 |
| Directory | /workspace/81.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/81.xbar_random_zero_delays.3551778686 |
| Short name | T2594 |
| Test name | |
| Test status | |
| Simulation time | 523067872 ps |
| CPU time | 45.76 seconds |
| Started | Jun 23 07:38:12 PM PDT 24 |
| Finished | Jun 23 07:38:58 PM PDT 24 |
| Peak memory | 573668 kb |
| Host | smart-6f7ff6ec-34b9-42b9-b177-a8c8bae7b6e5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3551778686 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 81.xbar_random_zero_del ays.3551778686 |
| Directory | /workspace/81.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/81.xbar_same_source.1097654034 |
| Short name | T2104 |
| Test name | |
| Test status | |
| Simulation time | 2174885128 ps |
| CPU time | 56.25 seconds |
| Started | Jun 23 07:38:24 PM PDT 24 |
| Finished | Jun 23 07:39:21 PM PDT 24 |
| Peak memory | 574160 kb |
| Host | smart-d20996ed-70e9-4045-b16e-c199a0e9c7b2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1097654034 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 81.xbar_same_source.1097654034 |
| Directory | /workspace/81.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/81.xbar_smoke.862408683 |
| Short name | T1913 |
| Test name | |
| Test status | |
| Simulation time | 41061943 ps |
| CPU time | 5.88 seconds |
| Started | Jun 23 07:38:12 PM PDT 24 |
| Finished | Jun 23 07:38:18 PM PDT 24 |
| Peak memory | 565492 kb |
| Host | smart-fe63ee7a-a99e-464c-9265-69c2530da65f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=862408683 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 81.xbar_smoke.862408683 |
| Directory | /workspace/81.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/81.xbar_smoke_large_delays.1078582271 |
| Short name | T2286 |
| Test name | |
| Test status | |
| Simulation time | 8602728864 ps |
| CPU time | 83.84 seconds |
| Started | Jun 23 07:38:09 PM PDT 24 |
| Finished | Jun 23 07:39:33 PM PDT 24 |
| Peak memory | 565212 kb |
| Host | smart-31668db0-bba9-4112-854a-d4f46a850959 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1078582271 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 81.xbar_smoke_large_delays.1078582271 |
| Directory | /workspace/81.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/81.xbar_smoke_slow_rsp.1801331501 |
| Short name | T2327 |
| Test name | |
| Test status | |
| Simulation time | 4638836896 ps |
| CPU time | 73.08 seconds |
| Started | Jun 23 07:38:06 PM PDT 24 |
| Finished | Jun 23 07:39:19 PM PDT 24 |
| Peak memory | 565936 kb |
| Host | smart-ef7e0eaf-ecf1-446c-8da8-db8500685fd3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1801331501 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 81.xbar_smoke_slow_rsp.1801331501 |
| Directory | /workspace/81.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/81.xbar_smoke_zero_delays.1175318333 |
| Short name | T1858 |
| Test name | |
| Test status | |
| Simulation time | 56568317 ps |
| CPU time | 6.61 seconds |
| Started | Jun 23 07:38:09 PM PDT 24 |
| Finished | Jun 23 07:38:16 PM PDT 24 |
| Peak memory | 565540 kb |
| Host | smart-0e2668ee-29e9-477c-9d07-e25a13fff03d |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1175318333 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 81.xbar_smoke_zero_delay s.1175318333 |
| Directory | /workspace/81.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/81.xbar_stress_all.3153365346 |
| Short name | T598 |
| Test name | |
| Test status | |
| Simulation time | 2274215921 ps |
| CPU time | 194.23 seconds |
| Started | Jun 23 07:38:32 PM PDT 24 |
| Finished | Jun 23 07:41:46 PM PDT 24 |
| Peak memory | 574236 kb |
| Host | smart-93c77f2a-9167-48f0-bb1c-fe19704be808 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3153365346 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 81.xbar_stress_all.3153365346 |
| Directory | /workspace/81.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/81.xbar_stress_all_with_rand_reset.1199265531 |
| Short name | T2179 |
| Test name | |
| Test status | |
| Simulation time | 82457138 ps |
| CPU time | 24.51 seconds |
| Started | Jun 23 07:38:33 PM PDT 24 |
| Finished | Jun 23 07:38:57 PM PDT 24 |
| Peak memory | 565980 kb |
| Host | smart-9a6fb79c-270a-453f-90b5-74dad3280a48 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1199265531 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 81.xbar_stress_all _with_rand_reset.1199265531 |
| Directory | /workspace/81.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/81.xbar_stress_all_with_reset_error.3090775470 |
| Short name | T1876 |
| Test name | |
| Test status | |
| Simulation time | 2230535943 ps |
| CPU time | 94.88 seconds |
| Started | Jun 23 07:38:29 PM PDT 24 |
| Finished | Jun 23 07:40:04 PM PDT 24 |
| Peak memory | 576336 kb |
| Host | smart-0ffb7110-a6bf-4ecf-9a52-e828f6b9f2ce |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3090775470 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 81.xbar_stress_al l_with_reset_error.3090775470 |
| Directory | /workspace/81.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/81.xbar_unmapped_addr.1868058875 |
| Short name | T445 |
| Test name | |
| Test status | |
| Simulation time | 132838928 ps |
| CPU time | 9.52 seconds |
| Started | Jun 23 07:38:32 PM PDT 24 |
| Finished | Jun 23 07:38:42 PM PDT 24 |
| Peak memory | 566072 kb |
| Host | smart-298c49d1-b20e-4f1a-8f69-047378406426 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1868058875 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 81.xbar_unmapped_addr.1868058875 |
| Directory | /workspace/81.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/82.xbar_access_same_device.2080023265 |
| Short name | T874 |
| Test name | |
| Test status | |
| Simulation time | 1150707992 ps |
| CPU time | 45.1 seconds |
| Started | Jun 23 07:38:38 PM PDT 24 |
| Finished | Jun 23 07:39:23 PM PDT 24 |
| Peak memory | 574020 kb |
| Host | smart-54f1a7b8-a593-491f-8143-267952f14c5c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2080023265 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 82.xbar_access_same_device .2080023265 |
| Directory | /workspace/82.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/82.xbar_access_same_device_slow_rsp.1246025981 |
| Short name | T2615 |
| Test name | |
| Test status | |
| Simulation time | 64888325563 ps |
| CPU time | 1307.33 seconds |
| Started | Jun 23 07:38:36 PM PDT 24 |
| Finished | Jun 23 08:00:25 PM PDT 24 |
| Peak memory | 573536 kb |
| Host | smart-ff664f0d-0414-42d6-a824-a712656243f5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1246025981 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 82.xbar_access_same_ device_slow_rsp.1246025981 |
| Directory | /workspace/82.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/82.xbar_error_and_unmapped_addr.94798821 |
| Short name | T2624 |
| Test name | |
| Test status | |
| Simulation time | 245872950 ps |
| CPU time | 28.37 seconds |
| Started | Jun 23 07:38:35 PM PDT 24 |
| Finished | Jun 23 07:39:04 PM PDT 24 |
| Peak memory | 573728 kb |
| Host | smart-f37182fa-911d-4685-8fe1-7862936fd8c1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94798821 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 82.xbar_error_and_unmapped_addr.94798821 |
| Directory | /workspace/82.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/82.xbar_error_random.2821987995 |
| Short name | T2679 |
| Test name | |
| Test status | |
| Simulation time | 83938923 ps |
| CPU time | 9.64 seconds |
| Started | Jun 23 07:38:38 PM PDT 24 |
| Finished | Jun 23 07:38:48 PM PDT 24 |
| Peak memory | 573664 kb |
| Host | smart-d0f96b5d-c822-4ea8-8b2f-ee378343bad3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2821987995 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 82.xbar_error_random.2821987995 |
| Directory | /workspace/82.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/82.xbar_random.4228217174 |
| Short name | T554 |
| Test name | |
| Test status | |
| Simulation time | 2098866441 ps |
| CPU time | 71 seconds |
| Started | Jun 23 07:38:37 PM PDT 24 |
| Finished | Jun 23 07:39:49 PM PDT 24 |
| Peak memory | 574140 kb |
| Host | smart-06d82cf4-bcd8-4c43-ac5f-66ea7dcda63b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4228217174 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 82.xbar_random.4228217174 |
| Directory | /workspace/82.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/82.xbar_random_large_delays.4060326451 |
| Short name | T2511 |
| Test name | |
| Test status | |
| Simulation time | 49896580729 ps |
| CPU time | 608.61 seconds |
| Started | Jun 23 07:38:37 PM PDT 24 |
| Finished | Jun 23 07:48:46 PM PDT 24 |
| Peak memory | 573480 kb |
| Host | smart-6b3867cb-bb62-4c81-8a39-42647e1c66da |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4060326451 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 82.xbar_random_large_delays.4060326451 |
| Directory | /workspace/82.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/82.xbar_random_slow_rsp.2920042189 |
| Short name | T2184 |
| Test name | |
| Test status | |
| Simulation time | 63704506409 ps |
| CPU time | 1087.71 seconds |
| Started | Jun 23 07:38:35 PM PDT 24 |
| Finished | Jun 23 07:56:43 PM PDT 24 |
| Peak memory | 573496 kb |
| Host | smart-6a8571e3-74b2-41f4-b32f-77f5fbca9dc6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2920042189 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 82.xbar_random_slow_rsp.2920042189 |
| Directory | /workspace/82.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/82.xbar_random_zero_delays.1751643711 |
| Short name | T1806 |
| Test name | |
| Test status | |
| Simulation time | 226189459 ps |
| CPU time | 20.3 seconds |
| Started | Jun 23 07:38:37 PM PDT 24 |
| Finished | Jun 23 07:38:58 PM PDT 24 |
| Peak memory | 574068 kb |
| Host | smart-fb59695b-e0f2-4b60-9775-5a9b1a0b2ce6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1751643711 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 82.xbar_random_zero_del ays.1751643711 |
| Directory | /workspace/82.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/82.xbar_same_source.888000857 |
| Short name | T2860 |
| Test name | |
| Test status | |
| Simulation time | 447545362 ps |
| CPU time | 33.24 seconds |
| Started | Jun 23 07:38:57 PM PDT 24 |
| Finished | Jun 23 07:39:31 PM PDT 24 |
| Peak memory | 574072 kb |
| Host | smart-419d3d03-9f98-47be-9356-3ed1a7491fca |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=888000857 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 82.xbar_same_source.888000857 |
| Directory | /workspace/82.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/82.xbar_smoke.1377708719 |
| Short name | T1430 |
| Test name | |
| Test status | |
| Simulation time | 183261825 ps |
| CPU time | 9 seconds |
| Started | Jun 23 07:38:30 PM PDT 24 |
| Finished | Jun 23 07:38:39 PM PDT 24 |
| Peak memory | 565460 kb |
| Host | smart-37ae5c8d-215f-458a-a76d-73bdaf4080a5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1377708719 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 82.xbar_smoke.1377708719 |
| Directory | /workspace/82.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/82.xbar_smoke_large_delays.4291522896 |
| Short name | T1504 |
| Test name | |
| Test status | |
| Simulation time | 7904819514 ps |
| CPU time | 85.76 seconds |
| Started | Jun 23 07:38:31 PM PDT 24 |
| Finished | Jun 23 07:39:57 PM PDT 24 |
| Peak memory | 565216 kb |
| Host | smart-6ef7615c-371b-481b-9cf8-2d21918ee3fe |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4291522896 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 82.xbar_smoke_large_delays.4291522896 |
| Directory | /workspace/82.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/82.xbar_smoke_slow_rsp.2808532922 |
| Short name | T2621 |
| Test name | |
| Test status | |
| Simulation time | 3101167313 ps |
| CPU time | 54.7 seconds |
| Started | Jun 23 07:38:42 PM PDT 24 |
| Finished | Jun 23 07:39:37 PM PDT 24 |
| Peak memory | 565912 kb |
| Host | smart-6d2b0bc0-707f-43e8-8c67-c2dba164e04a |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2808532922 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 82.xbar_smoke_slow_rsp.2808532922 |
| Directory | /workspace/82.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/82.xbar_smoke_zero_delays.717389214 |
| Short name | T2266 |
| Test name | |
| Test status | |
| Simulation time | 52455003 ps |
| CPU time | 6.9 seconds |
| Started | Jun 23 07:38:35 PM PDT 24 |
| Finished | Jun 23 07:38:42 PM PDT 24 |
| Peak memory | 565616 kb |
| Host | smart-b6c2811b-86db-427c-b018-bd1f56dcd5b8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=717389214 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 82.xbar_smoke_zero_delays .717389214 |
| Directory | /workspace/82.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/82.xbar_stress_all.1585390833 |
| Short name | T552 |
| Test name | |
| Test status | |
| Simulation time | 11756196621 ps |
| CPU time | 430.22 seconds |
| Started | Jun 23 07:38:36 PM PDT 24 |
| Finished | Jun 23 07:45:46 PM PDT 24 |
| Peak memory | 574284 kb |
| Host | smart-afb3336f-1b6c-4444-a5b2-82ae1170c9e4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1585390833 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 82.xbar_stress_all.1585390833 |
| Directory | /workspace/82.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/82.xbar_stress_all_with_error.4017930799 |
| Short name | T2589 |
| Test name | |
| Test status | |
| Simulation time | 974705983 ps |
| CPU time | 80.89 seconds |
| Started | Jun 23 07:38:36 PM PDT 24 |
| Finished | Jun 23 07:39:58 PM PDT 24 |
| Peak memory | 574192 kb |
| Host | smart-28701fc9-c7cd-47ff-a3f5-8eaddb9bcc4a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4017930799 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 82.xbar_stress_all_with_error.4017930799 |
| Directory | /workspace/82.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/82.xbar_stress_all_with_rand_reset.1805513789 |
| Short name | T2335 |
| Test name | |
| Test status | |
| Simulation time | 98043049 ps |
| CPU time | 28.16 seconds |
| Started | Jun 23 07:38:41 PM PDT 24 |
| Finished | Jun 23 07:39:09 PM PDT 24 |
| Peak memory | 574212 kb |
| Host | smart-b4fa7481-c87a-4439-9ea0-efe49ab7c07e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1805513789 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 82.xbar_stress_all _with_rand_reset.1805513789 |
| Directory | /workspace/82.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/82.xbar_stress_all_with_reset_error.3101010587 |
| Short name | T868 |
| Test name | |
| Test status | |
| Simulation time | 7197387701 ps |
| CPU time | 522.2 seconds |
| Started | Jun 23 07:38:37 PM PDT 24 |
| Finished | Jun 23 07:47:20 PM PDT 24 |
| Peak memory | 576428 kb |
| Host | smart-ac4752f8-bd5d-4e69-a499-f756fe9fdfbe |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3101010587 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 82.xbar_stress_al l_with_reset_error.3101010587 |
| Directory | /workspace/82.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/82.xbar_unmapped_addr.1929354843 |
| Short name | T2114 |
| Test name | |
| Test status | |
| Simulation time | 170833176 ps |
| CPU time | 20.44 seconds |
| Started | Jun 23 07:38:41 PM PDT 24 |
| Finished | Jun 23 07:39:02 PM PDT 24 |
| Peak memory | 573464 kb |
| Host | smart-60bacd23-6f83-4178-836b-0e4c8b848596 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1929354843 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 82.xbar_unmapped_addr.1929354843 |
| Directory | /workspace/82.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/83.xbar_access_same_device.77812810 |
| Short name | T728 |
| Test name | |
| Test status | |
| Simulation time | 1279047613 ps |
| CPU time | 63.35 seconds |
| Started | Jun 23 07:38:42 PM PDT 24 |
| Finished | Jun 23 07:39:46 PM PDT 24 |
| Peak memory | 573416 kb |
| Host | smart-f615b0a0-1270-4f0d-ac2e-f402160026b2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77812810 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 83.xbar_access_same_device.77812810 |
| Directory | /workspace/83.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/83.xbar_access_same_device_slow_rsp.1405160034 |
| Short name | T859 |
| Test name | |
| Test status | |
| Simulation time | 24001687344 ps |
| CPU time | 402.32 seconds |
| Started | Jun 23 07:38:41 PM PDT 24 |
| Finished | Jun 23 07:45:24 PM PDT 24 |
| Peak memory | 574208 kb |
| Host | smart-7c4aaf50-e90b-46fe-91c6-9602396bbaa6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1405160034 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 83.xbar_access_same_ device_slow_rsp.1405160034 |
| Directory | /workspace/83.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/83.xbar_error_and_unmapped_addr.2622439380 |
| Short name | T2142 |
| Test name | |
| Test status | |
| Simulation time | 200507771 ps |
| CPU time | 23.4 seconds |
| Started | Jun 23 07:38:41 PM PDT 24 |
| Finished | Jun 23 07:39:05 PM PDT 24 |
| Peak memory | 573332 kb |
| Host | smart-0527bec1-53e6-4fde-b40c-df67ef11b599 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2622439380 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 83.xbar_error_and_unmapped_add r.2622439380 |
| Directory | /workspace/83.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/83.xbar_error_random.200458484 |
| Short name | T1928 |
| Test name | |
| Test status | |
| Simulation time | 561899143 ps |
| CPU time | 41.57 seconds |
| Started | Jun 23 07:38:39 PM PDT 24 |
| Finished | Jun 23 07:39:21 PM PDT 24 |
| Peak memory | 573628 kb |
| Host | smart-86f624ba-168f-4264-bd5b-afd1829065f5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=200458484 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 83.xbar_error_random.200458484 |
| Directory | /workspace/83.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/83.xbar_random.2527191290 |
| Short name | T2012 |
| Test name | |
| Test status | |
| Simulation time | 502098545 ps |
| CPU time | 42.33 seconds |
| Started | Jun 23 07:38:37 PM PDT 24 |
| Finished | Jun 23 07:39:20 PM PDT 24 |
| Peak memory | 573980 kb |
| Host | smart-3d046267-07ad-41ce-ae8c-c7430bb20fc0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2527191290 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 83.xbar_random.2527191290 |
| Directory | /workspace/83.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/83.xbar_random_large_delays.1169799293 |
| Short name | T2215 |
| Test name | |
| Test status | |
| Simulation time | 28934040605 ps |
| CPU time | 303.85 seconds |
| Started | Jun 23 07:38:37 PM PDT 24 |
| Finished | Jun 23 07:43:41 PM PDT 24 |
| Peak memory | 573520 kb |
| Host | smart-146c6131-1748-49f4-a54e-c82148dbd8ac |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1169799293 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 83.xbar_random_large_delays.1169799293 |
| Directory | /workspace/83.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/83.xbar_random_slow_rsp.1522493814 |
| Short name | T2706 |
| Test name | |
| Test status | |
| Simulation time | 35679140401 ps |
| CPU time | 626.08 seconds |
| Started | Jun 23 07:38:40 PM PDT 24 |
| Finished | Jun 23 07:49:06 PM PDT 24 |
| Peak memory | 574164 kb |
| Host | smart-b335c227-4211-4c50-a215-673a956bdb93 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1522493814 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 83.xbar_random_slow_rsp.1522493814 |
| Directory | /workspace/83.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/83.xbar_random_zero_delays.2775827680 |
| Short name | T667 |
| Test name | |
| Test status | |
| Simulation time | 509814504 ps |
| CPU time | 42.86 seconds |
| Started | Jun 23 07:38:34 PM PDT 24 |
| Finished | Jun 23 07:39:17 PM PDT 24 |
| Peak memory | 574064 kb |
| Host | smart-af1b9839-ee13-4107-92dc-1502304869d7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2775827680 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 83.xbar_random_zero_del ays.2775827680 |
| Directory | /workspace/83.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/83.xbar_same_source.4218744714 |
| Short name | T2308 |
| Test name | |
| Test status | |
| Simulation time | 286404270 ps |
| CPU time | 23.35 seconds |
| Started | Jun 23 07:38:35 PM PDT 24 |
| Finished | Jun 23 07:38:59 PM PDT 24 |
| Peak memory | 574392 kb |
| Host | smart-74a63cb2-f0e0-4dad-91fd-3db20bdd3546 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4218744714 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 83.xbar_same_source.4218744714 |
| Directory | /workspace/83.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/83.xbar_smoke.225223928 |
| Short name | T1923 |
| Test name | |
| Test status | |
| Simulation time | 56713099 ps |
| CPU time | 7 seconds |
| Started | Jun 23 07:38:36 PM PDT 24 |
| Finished | Jun 23 07:38:44 PM PDT 24 |
| Peak memory | 573680 kb |
| Host | smart-76d363f4-78b3-4010-ad77-e04b6826648f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=225223928 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 83.xbar_smoke.225223928 |
| Directory | /workspace/83.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/83.xbar_smoke_large_delays.4091255040 |
| Short name | T2877 |
| Test name | |
| Test status | |
| Simulation time | 5494030683 ps |
| CPU time | 54.39 seconds |
| Started | Jun 23 07:38:42 PM PDT 24 |
| Finished | Jun 23 07:39:37 PM PDT 24 |
| Peak memory | 565928 kb |
| Host | smart-5d1b094e-d0cd-483e-8b7e-af54345c7f56 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4091255040 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 83.xbar_smoke_large_delays.4091255040 |
| Directory | /workspace/83.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/83.xbar_smoke_slow_rsp.555056427 |
| Short name | T1534 |
| Test name | |
| Test status | |
| Simulation time | 4543508360 ps |
| CPU time | 72.87 seconds |
| Started | Jun 23 07:38:42 PM PDT 24 |
| Finished | Jun 23 07:39:55 PM PDT 24 |
| Peak memory | 565188 kb |
| Host | smart-cc6be04b-3947-4b9f-b7f1-5afb0ecf28e5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=555056427 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 83.xbar_smoke_slow_rsp.555056427 |
| Directory | /workspace/83.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/83.xbar_smoke_zero_delays.4113125263 |
| Short name | T2101 |
| Test name | |
| Test status | |
| Simulation time | 46285402 ps |
| CPU time | 5.98 seconds |
| Started | Jun 23 07:38:37 PM PDT 24 |
| Finished | Jun 23 07:38:43 PM PDT 24 |
| Peak memory | 565128 kb |
| Host | smart-6b8b5855-a19c-48dd-9860-4a2ca096864f |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4113125263 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 83.xbar_smoke_zero_delay s.4113125263 |
| Directory | /workspace/83.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/83.xbar_stress_all.200688393 |
| Short name | T1733 |
| Test name | |
| Test status | |
| Simulation time | 4867080304 ps |
| CPU time | 197.54 seconds |
| Started | Jun 23 07:38:36 PM PDT 24 |
| Finished | Jun 23 07:41:54 PM PDT 24 |
| Peak memory | 574300 kb |
| Host | smart-cd0424c0-71ee-4780-8b48-72600d244438 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=200688393 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 83.xbar_stress_all.200688393 |
| Directory | /workspace/83.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/83.xbar_stress_all_with_error.248229857 |
| Short name | T2076 |
| Test name | |
| Test status | |
| Simulation time | 2467780384 ps |
| CPU time | 156.3 seconds |
| Started | Jun 23 07:38:36 PM PDT 24 |
| Finished | Jun 23 07:41:12 PM PDT 24 |
| Peak memory | 574348 kb |
| Host | smart-a8192527-33bb-4031-9972-c109427d085c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=248229857 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 83.xbar_stress_all_with_error.248229857 |
| Directory | /workspace/83.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/83.xbar_stress_all_with_rand_reset.2414800587 |
| Short name | T1648 |
| Test name | |
| Test status | |
| Simulation time | 671207283 ps |
| CPU time | 312.28 seconds |
| Started | Jun 23 07:38:39 PM PDT 24 |
| Finished | Jun 23 07:43:51 PM PDT 24 |
| Peak memory | 576296 kb |
| Host | smart-b235a9da-234e-449f-8d60-cbf85525357c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2414800587 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 83.xbar_stress_all _with_rand_reset.2414800587 |
| Directory | /workspace/83.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/83.xbar_stress_all_with_reset_error.4138016591 |
| Short name | T2312 |
| Test name | |
| Test status | |
| Simulation time | 84186778 ps |
| CPU time | 23.4 seconds |
| Started | Jun 23 07:38:38 PM PDT 24 |
| Finished | Jun 23 07:39:02 PM PDT 24 |
| Peak memory | 576316 kb |
| Host | smart-2b5ed0e4-e549-4955-850f-f03b8cd51086 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4138016591 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 83.xbar_stress_al l_with_reset_error.4138016591 |
| Directory | /workspace/83.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/83.xbar_unmapped_addr.4205616020 |
| Short name | T2625 |
| Test name | |
| Test status | |
| Simulation time | 746930114 ps |
| CPU time | 30.17 seconds |
| Started | Jun 23 07:38:34 PM PDT 24 |
| Finished | Jun 23 07:39:04 PM PDT 24 |
| Peak memory | 574116 kb |
| Host | smart-fcd50ff5-953a-4d63-ab6e-dd6f12c447d1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4205616020 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 83.xbar_unmapped_addr.4205616020 |
| Directory | /workspace/83.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/84.xbar_access_same_device.4274241477 |
| Short name | T2744 |
| Test name | |
| Test status | |
| Simulation time | 3179994413 ps |
| CPU time | 115.96 seconds |
| Started | Jun 23 07:38:39 PM PDT 24 |
| Finished | Jun 23 07:40:35 PM PDT 24 |
| Peak memory | 573460 kb |
| Host | smart-7dc4ccaf-de73-4379-b99d-22240f819b20 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4274241477 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 84.xbar_access_same_device .4274241477 |
| Directory | /workspace/84.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/84.xbar_access_same_device_slow_rsp.521587126 |
| Short name | T1603 |
| Test name | |
| Test status | |
| Simulation time | 2744847640 ps |
| CPU time | 47.7 seconds |
| Started | Jun 23 07:38:38 PM PDT 24 |
| Finished | Jun 23 07:39:27 PM PDT 24 |
| Peak memory | 565560 kb |
| Host | smart-24f1d396-e0ec-4aa0-9ec3-e3b26e1752cb |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=521587126 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 84.xbar_access_same_d evice_slow_rsp.521587126 |
| Directory | /workspace/84.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/84.xbar_error_and_unmapped_addr.735730379 |
| Short name | T2045 |
| Test name | |
| Test status | |
| Simulation time | 96361402 ps |
| CPU time | 12.8 seconds |
| Started | Jun 23 07:38:46 PM PDT 24 |
| Finished | Jun 23 07:38:59 PM PDT 24 |
| Peak memory | 573724 kb |
| Host | smart-aecb1194-b328-4e43-ba62-764658691c43 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=735730379 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 84.xbar_error_and_unmapped_addr .735730379 |
| Directory | /workspace/84.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/84.xbar_error_random.2223827202 |
| Short name | T2366 |
| Test name | |
| Test status | |
| Simulation time | 2598280264 ps |
| CPU time | 90.27 seconds |
| Started | Jun 23 07:38:40 PM PDT 24 |
| Finished | Jun 23 07:40:11 PM PDT 24 |
| Peak memory | 573788 kb |
| Host | smart-c653c7b3-8287-408a-aa55-af50e0388a01 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2223827202 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 84.xbar_error_random.2223827202 |
| Directory | /workspace/84.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/84.xbar_random.1323391433 |
| Short name | T677 |
| Test name | |
| Test status | |
| Simulation time | 630381465 ps |
| CPU time | 54.96 seconds |
| Started | Jun 23 07:38:34 PM PDT 24 |
| Finished | Jun 23 07:39:30 PM PDT 24 |
| Peak memory | 573384 kb |
| Host | smart-5f108d2e-7859-4bab-a241-fdc8401437d3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1323391433 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 84.xbar_random.1323391433 |
| Directory | /workspace/84.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/84.xbar_random_large_delays.3804143533 |
| Short name | T2826 |
| Test name | |
| Test status | |
| Simulation time | 62668486110 ps |
| CPU time | 663.74 seconds |
| Started | Jun 23 07:38:38 PM PDT 24 |
| Finished | Jun 23 07:49:43 PM PDT 24 |
| Peak memory | 573476 kb |
| Host | smart-f73bc9b0-d1f0-4f71-a7da-4fac2bac0d07 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3804143533 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 84.xbar_random_large_delays.3804143533 |
| Directory | /workspace/84.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/84.xbar_random_slow_rsp.3685131293 |
| Short name | T2072 |
| Test name | |
| Test status | |
| Simulation time | 4149643453 ps |
| CPU time | 69.38 seconds |
| Started | Jun 23 07:38:41 PM PDT 24 |
| Finished | Jun 23 07:39:51 PM PDT 24 |
| Peak memory | 565924 kb |
| Host | smart-f097f30d-6263-43a7-9a2d-583413ace043 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3685131293 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 84.xbar_random_slow_rsp.3685131293 |
| Directory | /workspace/84.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/84.xbar_random_zero_delays.1710469024 |
| Short name | T1380 |
| Test name | |
| Test status | |
| Simulation time | 74359820 ps |
| CPU time | 7.94 seconds |
| Started | Jun 23 07:38:42 PM PDT 24 |
| Finished | Jun 23 07:38:51 PM PDT 24 |
| Peak memory | 574088 kb |
| Host | smart-be21c45f-05bd-4879-a3ab-8803690ec6d6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1710469024 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 84.xbar_random_zero_del ays.1710469024 |
| Directory | /workspace/84.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/84.xbar_same_source.2096535698 |
| Short name | T2187 |
| Test name | |
| Test status | |
| Simulation time | 293737444 ps |
| CPU time | 22.15 seconds |
| Started | Jun 23 07:38:43 PM PDT 24 |
| Finished | Jun 23 07:39:06 PM PDT 24 |
| Peak memory | 573420 kb |
| Host | smart-0e817e84-11a1-46b7-bb22-678eca0881a5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2096535698 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 84.xbar_same_source.2096535698 |
| Directory | /workspace/84.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/84.xbar_smoke.1270763983 |
| Short name | T2522 |
| Test name | |
| Test status | |
| Simulation time | 244350771 ps |
| CPU time | 10.14 seconds |
| Started | Jun 23 07:38:36 PM PDT 24 |
| Finished | Jun 23 07:38:47 PM PDT 24 |
| Peak memory | 573940 kb |
| Host | smart-c39d3c79-b941-4b98-b0bc-922982517808 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1270763983 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 84.xbar_smoke.1270763983 |
| Directory | /workspace/84.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/84.xbar_smoke_large_delays.3209027931 |
| Short name | T910 |
| Test name | |
| Test status | |
| Simulation time | 6333489984 ps |
| CPU time | 67.82 seconds |
| Started | Jun 23 07:38:40 PM PDT 24 |
| Finished | Jun 23 07:39:48 PM PDT 24 |
| Peak memory | 565896 kb |
| Host | smart-0df357a2-850c-4823-ae9a-153ff520cff9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3209027931 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 84.xbar_smoke_large_delays.3209027931 |
| Directory | /workspace/84.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/84.xbar_smoke_slow_rsp.837513494 |
| Short name | T1687 |
| Test name | |
| Test status | |
| Simulation time | 6140823352 ps |
| CPU time | 109.79 seconds |
| Started | Jun 23 07:38:34 PM PDT 24 |
| Finished | Jun 23 07:40:25 PM PDT 24 |
| Peak memory | 573400 kb |
| Host | smart-872f4eb9-67c2-4b1c-a720-7bf769d7de53 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=837513494 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 84.xbar_smoke_slow_rsp.837513494 |
| Directory | /workspace/84.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/84.xbar_smoke_zero_delays.712108515 |
| Short name | T1549 |
| Test name | |
| Test status | |
| Simulation time | 47464268 ps |
| CPU time | 6.84 seconds |
| Started | Jun 23 07:38:37 PM PDT 24 |
| Finished | Jun 23 07:38:44 PM PDT 24 |
| Peak memory | 565556 kb |
| Host | smart-0d1869de-a687-4926-84dc-86a4e9c31fb8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=712108515 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 84.xbar_smoke_zero_delays .712108515 |
| Directory | /workspace/84.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/84.xbar_stress_all.3712503069 |
| Short name | T2350 |
| Test name | |
| Test status | |
| Simulation time | 16484251664 ps |
| CPU time | 649.55 seconds |
| Started | Jun 23 07:38:44 PM PDT 24 |
| Finished | Jun 23 07:49:34 PM PDT 24 |
| Peak memory | 574316 kb |
| Host | smart-52517dd7-8cc3-4619-95c2-baa229a0306e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3712503069 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 84.xbar_stress_all.3712503069 |
| Directory | /workspace/84.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/84.xbar_stress_all_with_error.3299848349 |
| Short name | T1606 |
| Test name | |
| Test status | |
| Simulation time | 3052079349 ps |
| CPU time | 116.6 seconds |
| Started | Jun 23 07:38:43 PM PDT 24 |
| Finished | Jun 23 07:40:40 PM PDT 24 |
| Peak memory | 574112 kb |
| Host | smart-25d254cd-f7f5-4002-98db-9d24ca85f23b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3299848349 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 84.xbar_stress_all_with_error.3299848349 |
| Directory | /workspace/84.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/84.xbar_stress_all_with_rand_reset.4029834341 |
| Short name | T891 |
| Test name | |
| Test status | |
| Simulation time | 8024884352 ps |
| CPU time | 346.57 seconds |
| Started | Jun 23 07:38:44 PM PDT 24 |
| Finished | Jun 23 07:44:31 PM PDT 24 |
| Peak memory | 574312 kb |
| Host | smart-b2d4bb42-686a-4c3e-8ba3-ce4c408e1d82 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4029834341 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 84.xbar_stress_all _with_rand_reset.4029834341 |
| Directory | /workspace/84.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/84.xbar_stress_all_with_reset_error.3591318294 |
| Short name | T1680 |
| Test name | |
| Test status | |
| Simulation time | 3959920068 ps |
| CPU time | 331.87 seconds |
| Started | Jun 23 07:38:53 PM PDT 24 |
| Finished | Jun 23 07:44:26 PM PDT 24 |
| Peak memory | 574348 kb |
| Host | smart-ef4cc48c-b695-4c5b-9309-858e1cdfd0f3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3591318294 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 84.xbar_stress_al l_with_reset_error.3591318294 |
| Directory | /workspace/84.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/84.xbar_unmapped_addr.3961186285 |
| Short name | T1777 |
| Test name | |
| Test status | |
| Simulation time | 1198705617 ps |
| CPU time | 51.82 seconds |
| Started | Jun 23 07:38:41 PM PDT 24 |
| Finished | Jun 23 07:39:33 PM PDT 24 |
| Peak memory | 574108 kb |
| Host | smart-fc364bd9-1605-4641-ba4f-541b7bcf93c8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3961186285 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 84.xbar_unmapped_addr.3961186285 |
| Directory | /workspace/84.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/85.xbar_access_same_device.1014005795 |
| Short name | T2648 |
| Test name | |
| Test status | |
| Simulation time | 423516020 ps |
| CPU time | 20.35 seconds |
| Started | Jun 23 07:38:53 PM PDT 24 |
| Finished | Jun 23 07:39:14 PM PDT 24 |
| Peak memory | 573940 kb |
| Host | smart-3adeb91e-5e3e-49b0-be42-3c7ea7a441ea |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1014005795 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 85.xbar_access_same_device .1014005795 |
| Directory | /workspace/85.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/85.xbar_access_same_device_slow_rsp.783833382 |
| Short name | T2433 |
| Test name | |
| Test status | |
| Simulation time | 33049498264 ps |
| CPU time | 555.35 seconds |
| Started | Jun 23 07:38:50 PM PDT 24 |
| Finished | Jun 23 07:48:06 PM PDT 24 |
| Peak memory | 574336 kb |
| Host | smart-c13210c1-a3fc-4ad6-a58a-2047fac1adaa |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=783833382 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 85.xbar_access_same_d evice_slow_rsp.783833382 |
| Directory | /workspace/85.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/85.xbar_error_and_unmapped_addr.2256036408 |
| Short name | T1384 |
| Test name | |
| Test status | |
| Simulation time | 968033551 ps |
| CPU time | 37.79 seconds |
| Started | Jun 23 07:38:56 PM PDT 24 |
| Finished | Jun 23 07:39:35 PM PDT 24 |
| Peak memory | 573400 kb |
| Host | smart-6c0c91a7-8dc2-4672-a27b-02a9104e019c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2256036408 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 85.xbar_error_and_unmapped_add r.2256036408 |
| Directory | /workspace/85.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/85.xbar_error_random.2289915912 |
| Short name | T2622 |
| Test name | |
| Test status | |
| Simulation time | 167165357 ps |
| CPU time | 16.44 seconds |
| Started | Jun 23 07:38:57 PM PDT 24 |
| Finished | Jun 23 07:39:14 PM PDT 24 |
| Peak memory | 573192 kb |
| Host | smart-0bcb43b2-dc6f-4021-9959-7dbc88b0cc49 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2289915912 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 85.xbar_error_random.2289915912 |
| Directory | /workspace/85.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/85.xbar_random.1118358551 |
| Short name | T429 |
| Test name | |
| Test status | |
| Simulation time | 2357102453 ps |
| CPU time | 78.54 seconds |
| Started | Jun 23 07:38:51 PM PDT 24 |
| Finished | Jun 23 07:40:10 PM PDT 24 |
| Peak memory | 574164 kb |
| Host | smart-a858278a-eebe-4577-b103-c36d9f4b5743 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1118358551 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 85.xbar_random.1118358551 |
| Directory | /workspace/85.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/85.xbar_random_large_delays.3121516074 |
| Short name | T2039 |
| Test name | |
| Test status | |
| Simulation time | 15563694622 ps |
| CPU time | 157.47 seconds |
| Started | Jun 23 07:38:48 PM PDT 24 |
| Finished | Jun 23 07:41:26 PM PDT 24 |
| Peak memory | 573488 kb |
| Host | smart-79ed8808-18a0-4557-b207-d76f62914062 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3121516074 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 85.xbar_random_large_delays.3121516074 |
| Directory | /workspace/85.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/85.xbar_random_slow_rsp.387712606 |
| Short name | T2438 |
| Test name | |
| Test status | |
| Simulation time | 53526503143 ps |
| CPU time | 964.28 seconds |
| Started | Jun 23 07:38:49 PM PDT 24 |
| Finished | Jun 23 07:54:54 PM PDT 24 |
| Peak memory | 574140 kb |
| Host | smart-576f97f7-547f-4d66-b6ce-7f0408b713cd |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=387712606 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 85.xbar_random_slow_rsp.387712606 |
| Directory | /workspace/85.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/85.xbar_random_zero_delays.3673925261 |
| Short name | T2144 |
| Test name | |
| Test status | |
| Simulation time | 375676036 ps |
| CPU time | 36.83 seconds |
| Started | Jun 23 07:38:48 PM PDT 24 |
| Finished | Jun 23 07:39:25 PM PDT 24 |
| Peak memory | 574052 kb |
| Host | smart-24883fba-b290-4340-a2e3-4ea7abf804ff |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3673925261 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 85.xbar_random_zero_del ays.3673925261 |
| Directory | /workspace/85.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/85.xbar_same_source.2771497061 |
| Short name | T2670 |
| Test name | |
| Test status | |
| Simulation time | 391192189 ps |
| CPU time | 14.21 seconds |
| Started | Jun 23 07:38:48 PM PDT 24 |
| Finished | Jun 23 07:39:03 PM PDT 24 |
| Peak memory | 574076 kb |
| Host | smart-2634947b-76e8-494e-9bab-35f0469e6dcb |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2771497061 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 85.xbar_same_source.2771497061 |
| Directory | /workspace/85.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/85.xbar_smoke.1193024795 |
| Short name | T1611 |
| Test name | |
| Test status | |
| Simulation time | 46472330 ps |
| CPU time | 6 seconds |
| Started | Jun 23 07:38:50 PM PDT 24 |
| Finished | Jun 23 07:38:57 PM PDT 24 |
| Peak memory | 565484 kb |
| Host | smart-a88e51c4-b9cf-490b-b621-97ef9ce7f434 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1193024795 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 85.xbar_smoke.1193024795 |
| Directory | /workspace/85.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/85.xbar_smoke_large_delays.414998864 |
| Short name | T1378 |
| Test name | |
| Test status | |
| Simulation time | 10987148029 ps |
| CPU time | 108.42 seconds |
| Started | Jun 23 07:38:50 PM PDT 24 |
| Finished | Jun 23 07:40:39 PM PDT 24 |
| Peak memory | 566064 kb |
| Host | smart-554a1ead-a660-477e-a6b8-ac49c4af30f1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=414998864 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 85.xbar_smoke_large_delays.414998864 |
| Directory | /workspace/85.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/85.xbar_smoke_slow_rsp.3913270677 |
| Short name | T2393 |
| Test name | |
| Test status | |
| Simulation time | 5677303008 ps |
| CPU time | 98.4 seconds |
| Started | Jun 23 07:38:47 PM PDT 24 |
| Finished | Jun 23 07:40:26 PM PDT 24 |
| Peak memory | 565276 kb |
| Host | smart-83bcf128-9294-4eb0-9c8f-4d5d26d14dea |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3913270677 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 85.xbar_smoke_slow_rsp.3913270677 |
| Directory | /workspace/85.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/85.xbar_smoke_zero_delays.4109419768 |
| Short name | T2630 |
| Test name | |
| Test status | |
| Simulation time | 48127565 ps |
| CPU time | 5.96 seconds |
| Started | Jun 23 07:38:47 PM PDT 24 |
| Finished | Jun 23 07:38:54 PM PDT 24 |
| Peak memory | 573360 kb |
| Host | smart-796a5e1e-79d0-42ce-955d-7c2448733c55 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4109419768 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 85.xbar_smoke_zero_delay s.4109419768 |
| Directory | /workspace/85.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/85.xbar_stress_all.515626251 |
| Short name | T2841 |
| Test name | |
| Test status | |
| Simulation time | 630873370 ps |
| CPU time | 52.27 seconds |
| Started | Jun 23 07:38:57 PM PDT 24 |
| Finished | Jun 23 07:39:49 PM PDT 24 |
| Peak memory | 574204 kb |
| Host | smart-dcc40cbd-2f8b-4f04-b058-ee371acf9856 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=515626251 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 85.xbar_stress_all.515626251 |
| Directory | /workspace/85.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/85.xbar_stress_all_with_error.3549118634 |
| Short name | T2297 |
| Test name | |
| Test status | |
| Simulation time | 7679258868 ps |
| CPU time | 286.75 seconds |
| Started | Jun 23 07:38:58 PM PDT 24 |
| Finished | Jun 23 07:43:45 PM PDT 24 |
| Peak memory | 574344 kb |
| Host | smart-9ecf062d-5d33-4435-ae4e-4e49bee6930f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3549118634 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 85.xbar_stress_all_with_error.3549118634 |
| Directory | /workspace/85.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/85.xbar_stress_all_with_rand_reset.4057041678 |
| Short name | T472 |
| Test name | |
| Test status | |
| Simulation time | 6739564402 ps |
| CPU time | 372.3 seconds |
| Started | Jun 23 07:38:57 PM PDT 24 |
| Finished | Jun 23 07:45:09 PM PDT 24 |
| Peak memory | 574276 kb |
| Host | smart-7ea50491-4a16-4ab4-960e-ef8146d2ff07 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4057041678 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 85.xbar_stress_all _with_rand_reset.4057041678 |
| Directory | /workspace/85.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/85.xbar_stress_all_with_reset_error.4286999890 |
| Short name | T899 |
| Test name | |
| Test status | |
| Simulation time | 178764445 ps |
| CPU time | 40.23 seconds |
| Started | Jun 23 07:38:56 PM PDT 24 |
| Finished | Jun 23 07:39:37 PM PDT 24 |
| Peak memory | 573512 kb |
| Host | smart-7ae30fa2-54bb-4dc6-ac35-7678d2077588 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4286999890 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 85.xbar_stress_al l_with_reset_error.4286999890 |
| Directory | /workspace/85.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/85.xbar_unmapped_addr.3613093614 |
| Short name | T2545 |
| Test name | |
| Test status | |
| Simulation time | 166694137 ps |
| CPU time | 11.15 seconds |
| Started | Jun 23 07:38:57 PM PDT 24 |
| Finished | Jun 23 07:39:09 PM PDT 24 |
| Peak memory | 565172 kb |
| Host | smart-d997aed5-2e9c-431e-90a1-80c1eed2bbd3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3613093614 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 85.xbar_unmapped_addr.3613093614 |
| Directory | /workspace/85.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/86.xbar_access_same_device.1678308885 |
| Short name | T2159 |
| Test name | |
| Test status | |
| Simulation time | 203325391 ps |
| CPU time | 16.77 seconds |
| Started | Jun 23 07:39:01 PM PDT 24 |
| Finished | Jun 23 07:39:18 PM PDT 24 |
| Peak memory | 574056 kb |
| Host | smart-a1c5bf6e-20a5-4fde-9f10-ba9fefb01f82 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1678308885 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 86.xbar_access_same_device .1678308885 |
| Directory | /workspace/86.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/86.xbar_access_same_device_slow_rsp.850607002 |
| Short name | T1984 |
| Test name | |
| Test status | |
| Simulation time | 102501504209 ps |
| CPU time | 1896.19 seconds |
| Started | Jun 23 07:39:02 PM PDT 24 |
| Finished | Jun 23 08:10:39 PM PDT 24 |
| Peak memory | 574256 kb |
| Host | smart-8af63a18-a9f4-496f-9083-f961b9fe7cb6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=850607002 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 86.xbar_access_same_d evice_slow_rsp.850607002 |
| Directory | /workspace/86.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/86.xbar_error_and_unmapped_addr.255811751 |
| Short name | T1567 |
| Test name | |
| Test status | |
| Simulation time | 413503521 ps |
| CPU time | 18.76 seconds |
| Started | Jun 23 07:39:04 PM PDT 24 |
| Finished | Jun 23 07:39:23 PM PDT 24 |
| Peak memory | 573796 kb |
| Host | smart-9971188f-82c7-4e4b-a903-6cfecb94af20 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=255811751 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 86.xbar_error_and_unmapped_addr .255811751 |
| Directory | /workspace/86.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/86.xbar_error_random.45254241 |
| Short name | T1399 |
| Test name | |
| Test status | |
| Simulation time | 546322069 ps |
| CPU time | 22.3 seconds |
| Started | Jun 23 07:39:02 PM PDT 24 |
| Finished | Jun 23 07:39:24 PM PDT 24 |
| Peak memory | 573776 kb |
| Host | smart-b3ba3e08-a80d-4579-af27-bad742b33284 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45254241 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 86.xbar_error_random.45254241 |
| Directory | /workspace/86.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/86.xbar_random.3829831586 |
| Short name | T1625 |
| Test name | |
| Test status | |
| Simulation time | 68110539 ps |
| CPU time | 9.27 seconds |
| Started | Jun 23 07:39:06 PM PDT 24 |
| Finished | Jun 23 07:39:16 PM PDT 24 |
| Peak memory | 574112 kb |
| Host | smart-8988d08c-b4f6-4bf3-95fc-348b1f5f6552 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3829831586 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 86.xbar_random.3829831586 |
| Directory | /workspace/86.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/86.xbar_random_large_delays.3801034123 |
| Short name | T1563 |
| Test name | |
| Test status | |
| Simulation time | 100121815183 ps |
| CPU time | 1045.99 seconds |
| Started | Jun 23 07:39:02 PM PDT 24 |
| Finished | Jun 23 07:56:28 PM PDT 24 |
| Peak memory | 574160 kb |
| Host | smart-cd67367f-0f35-41f0-9f37-d095fa9ee269 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3801034123 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 86.xbar_random_large_delays.3801034123 |
| Directory | /workspace/86.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/86.xbar_random_slow_rsp.60139749 |
| Short name | T1938 |
| Test name | |
| Test status | |
| Simulation time | 29938647105 ps |
| CPU time | 536.02 seconds |
| Started | Jun 23 07:39:00 PM PDT 24 |
| Finished | Jun 23 07:47:56 PM PDT 24 |
| Peak memory | 574184 kb |
| Host | smart-e1c62022-644b-49e4-a7b4-7398b756ce27 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60139749 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 86.xbar_random_slow_rsp.60139749 |
| Directory | /workspace/86.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/86.xbar_random_zero_delays.256268897 |
| Short name | T1382 |
| Test name | |
| Test status | |
| Simulation time | 97558404 ps |
| CPU time | 12.08 seconds |
| Started | Jun 23 07:39:06 PM PDT 24 |
| Finished | Jun 23 07:39:18 PM PDT 24 |
| Peak memory | 573840 kb |
| Host | smart-99e935db-58e7-4a94-81fa-2ae6949bf47c |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=256268897 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 86.xbar_random_zero_dela ys.256268897 |
| Directory | /workspace/86.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/86.xbar_same_source.3163165794 |
| Short name | T2671 |
| Test name | |
| Test status | |
| Simulation time | 247651515 ps |
| CPU time | 20.44 seconds |
| Started | Jun 23 07:39:00 PM PDT 24 |
| Finished | Jun 23 07:39:21 PM PDT 24 |
| Peak memory | 574000 kb |
| Host | smart-4cac19fc-2025-43ae-a452-5a4efc099c8d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3163165794 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 86.xbar_same_source.3163165794 |
| Directory | /workspace/86.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/86.xbar_smoke.3290539181 |
| Short name | T1444 |
| Test name | |
| Test status | |
| Simulation time | 227148931 ps |
| CPU time | 9.14 seconds |
| Started | Jun 23 07:39:02 PM PDT 24 |
| Finished | Jun 23 07:39:11 PM PDT 24 |
| Peak memory | 565204 kb |
| Host | smart-1265a67f-db07-4705-a57a-952823cdaa07 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3290539181 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 86.xbar_smoke.3290539181 |
| Directory | /workspace/86.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/86.xbar_smoke_large_delays.1007469543 |
| Short name | T1853 |
| Test name | |
| Test status | |
| Simulation time | 6854810223 ps |
| CPU time | 70.52 seconds |
| Started | Jun 23 07:39:01 PM PDT 24 |
| Finished | Jun 23 07:40:11 PM PDT 24 |
| Peak memory | 565528 kb |
| Host | smart-1e54ee53-4815-4405-9bea-16d512b2b0b9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1007469543 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 86.xbar_smoke_large_delays.1007469543 |
| Directory | /workspace/86.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/86.xbar_smoke_slow_rsp.216544412 |
| Short name | T1571 |
| Test name | |
| Test status | |
| Simulation time | 3347836599 ps |
| CPU time | 54.49 seconds |
| Started | Jun 23 07:39:03 PM PDT 24 |
| Finished | Jun 23 07:39:58 PM PDT 24 |
| Peak memory | 565924 kb |
| Host | smart-2d920ee8-ddf4-4c79-a510-c17a0541826d |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=216544412 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 86.xbar_smoke_slow_rsp.216544412 |
| Directory | /workspace/86.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/86.xbar_smoke_zero_delays.2523744112 |
| Short name | T2064 |
| Test name | |
| Test status | |
| Simulation time | 44360574 ps |
| CPU time | 5.93 seconds |
| Started | Jun 23 07:39:01 PM PDT 24 |
| Finished | Jun 23 07:39:07 PM PDT 24 |
| Peak memory | 565204 kb |
| Host | smart-d3ef9505-7ce0-4900-8892-23d320511ae6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2523744112 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 86.xbar_smoke_zero_delay s.2523744112 |
| Directory | /workspace/86.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/86.xbar_stress_all.3403909009 |
| Short name | T2752 |
| Test name | |
| Test status | |
| Simulation time | 9709947744 ps |
| CPU time | 367.58 seconds |
| Started | Jun 23 07:39:06 PM PDT 24 |
| Finished | Jun 23 07:45:13 PM PDT 24 |
| Peak memory | 574280 kb |
| Host | smart-73d4bb63-78ae-42b2-9789-1aea1c968080 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3403909009 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 86.xbar_stress_all.3403909009 |
| Directory | /workspace/86.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/86.xbar_stress_all_with_error.3444923292 |
| Short name | T2078 |
| Test name | |
| Test status | |
| Simulation time | 4345615634 ps |
| CPU time | 152.15 seconds |
| Started | Jun 23 07:39:01 PM PDT 24 |
| Finished | Jun 23 07:41:33 PM PDT 24 |
| Peak memory | 574284 kb |
| Host | smart-ac96aad5-9feb-426d-b495-99a4ef1ff257 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3444923292 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 86.xbar_stress_all_with_error.3444923292 |
| Directory | /workspace/86.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/86.xbar_stress_all_with_rand_reset.393900248 |
| Short name | T2876 |
| Test name | |
| Test status | |
| Simulation time | 5155762446 ps |
| CPU time | 217.44 seconds |
| Started | Jun 23 07:39:00 PM PDT 24 |
| Finished | Jun 23 07:42:38 PM PDT 24 |
| Peak memory | 574312 kb |
| Host | smart-8b754af4-37a6-4e56-abe1-a3a57971516b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=393900248 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_res et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 86.xbar_stress_all_ with_rand_reset.393900248 |
| Directory | /workspace/86.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/86.xbar_stress_all_with_reset_error.3927970501 |
| Short name | T2247 |
| Test name | |
| Test status | |
| Simulation time | 8430025987 ps |
| CPU time | 341.91 seconds |
| Started | Jun 23 07:39:03 PM PDT 24 |
| Finished | Jun 23 07:44:46 PM PDT 24 |
| Peak memory | 574380 kb |
| Host | smart-71674550-96d4-4369-9e76-3f45bb2a7a2e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3927970501 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 86.xbar_stress_al l_with_reset_error.3927970501 |
| Directory | /workspace/86.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/86.xbar_unmapped_addr.3486511519 |
| Short name | T2445 |
| Test name | |
| Test status | |
| Simulation time | 154154039 ps |
| CPU time | 18.32 seconds |
| Started | Jun 23 07:39:06 PM PDT 24 |
| Finished | Jun 23 07:39:25 PM PDT 24 |
| Peak memory | 574124 kb |
| Host | smart-3ebbe2d8-d932-441d-85e2-3db702f34e4a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3486511519 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 86.xbar_unmapped_addr.3486511519 |
| Directory | /workspace/86.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/87.xbar_access_same_device.115923262 |
| Short name | T2156 |
| Test name | |
| Test status | |
| Simulation time | 1798163996 ps |
| CPU time | 75.93 seconds |
| Started | Jun 23 07:39:08 PM PDT 24 |
| Finished | Jun 23 07:40:24 PM PDT 24 |
| Peak memory | 573492 kb |
| Host | smart-48854d75-62ff-407d-964e-ae6330b4ff8d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=115923262 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 87.xbar_access_same_device. 115923262 |
| Directory | /workspace/87.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/87.xbar_access_same_device_slow_rsp.2214680612 |
| Short name | T2140 |
| Test name | |
| Test status | |
| Simulation time | 8924160584 ps |
| CPU time | 150.61 seconds |
| Started | Jun 23 07:39:21 PM PDT 24 |
| Finished | Jun 23 07:41:52 PM PDT 24 |
| Peak memory | 565928 kb |
| Host | smart-804f06c0-0b24-48b7-af4a-ab0b9d5cf472 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2214680612 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 87.xbar_access_same_ device_slow_rsp.2214680612 |
| Directory | /workspace/87.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/87.xbar_error_and_unmapped_addr.934966835 |
| Short name | T1403 |
| Test name | |
| Test status | |
| Simulation time | 65974328 ps |
| CPU time | 9.06 seconds |
| Started | Jun 23 07:39:20 PM PDT 24 |
| Finished | Jun 23 07:39:29 PM PDT 24 |
| Peak memory | 573720 kb |
| Host | smart-a9c80322-5162-4137-b650-7ca77cda2c6d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=934966835 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 87.xbar_error_and_unmapped_addr .934966835 |
| Directory | /workspace/87.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/87.xbar_error_random.1449312241 |
| Short name | T2200 |
| Test name | |
| Test status | |
| Simulation time | 1542166919 ps |
| CPU time | 44.96 seconds |
| Started | Jun 23 07:39:19 PM PDT 24 |
| Finished | Jun 23 07:40:04 PM PDT 24 |
| Peak memory | 573680 kb |
| Host | smart-a892644e-2c17-4f05-ba52-0efe354f3ea6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1449312241 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 87.xbar_error_random.1449312241 |
| Directory | /workspace/87.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/87.xbar_random.503679145 |
| Short name | T1607 |
| Test name | |
| Test status | |
| Simulation time | 414677504 ps |
| CPU time | 17.13 seconds |
| Started | Jun 23 07:39:06 PM PDT 24 |
| Finished | Jun 23 07:39:23 PM PDT 24 |
| Peak memory | 574076 kb |
| Host | smart-81eab603-3707-47d9-9bcb-5c7f3dd0b95e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=503679145 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 87.xbar_random.503679145 |
| Directory | /workspace/87.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/87.xbar_random_large_delays.1516101945 |
| Short name | T1540 |
| Test name | |
| Test status | |
| Simulation time | 89314498146 ps |
| CPU time | 986.91 seconds |
| Started | Jun 23 07:39:05 PM PDT 24 |
| Finished | Jun 23 07:55:33 PM PDT 24 |
| Peak memory | 573540 kb |
| Host | smart-f78c0c52-7a18-4e93-92b0-7754d3472a85 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1516101945 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 87.xbar_random_large_delays.1516101945 |
| Directory | /workspace/87.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/87.xbar_random_slow_rsp.3252864713 |
| Short name | T1759 |
| Test name | |
| Test status | |
| Simulation time | 4436427392 ps |
| CPU time | 71.95 seconds |
| Started | Jun 23 07:39:06 PM PDT 24 |
| Finished | Jun 23 07:40:19 PM PDT 24 |
| Peak memory | 565944 kb |
| Host | smart-709bafa5-66dc-44d2-8c6d-73db16ce7cd1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3252864713 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 87.xbar_random_slow_rsp.3252864713 |
| Directory | /workspace/87.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/87.xbar_random_zero_delays.3788853866 |
| Short name | T1546 |
| Test name | |
| Test status | |
| Simulation time | 71131183 ps |
| CPU time | 8.96 seconds |
| Started | Jun 23 07:39:04 PM PDT 24 |
| Finished | Jun 23 07:39:14 PM PDT 24 |
| Peak memory | 574092 kb |
| Host | smart-44170328-60b4-4b30-a24a-4183ebedae20 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3788853866 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 87.xbar_random_zero_del ays.3788853866 |
| Directory | /workspace/87.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/87.xbar_same_source.615820139 |
| Short name | T2567 |
| Test name | |
| Test status | |
| Simulation time | 1158638418 ps |
| CPU time | 30.17 seconds |
| Started | Jun 23 07:39:25 PM PDT 24 |
| Finished | Jun 23 07:39:56 PM PDT 24 |
| Peak memory | 573384 kb |
| Host | smart-f04da97d-d364-42e7-9507-f270902c0fcc |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=615820139 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 87.xbar_same_source.615820139 |
| Directory | /workspace/87.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/87.xbar_smoke.2185981437 |
| Short name | T2722 |
| Test name | |
| Test status | |
| Simulation time | 41867752 ps |
| CPU time | 6.08 seconds |
| Started | Jun 23 07:39:05 PM PDT 24 |
| Finished | Jun 23 07:39:11 PM PDT 24 |
| Peak memory | 565612 kb |
| Host | smart-911eebf3-9a2f-436e-96b4-b95bfa1e77a3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2185981437 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 87.xbar_smoke.2185981437 |
| Directory | /workspace/87.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/87.xbar_smoke_large_delays.62302280 |
| Short name | T1582 |
| Test name | |
| Test status | |
| Simulation time | 4229817085 ps |
| CPU time | 41.92 seconds |
| Started | Jun 23 07:39:04 PM PDT 24 |
| Finished | Jun 23 07:39:46 PM PDT 24 |
| Peak memory | 565884 kb |
| Host | smart-7aa6a145-e0ea-41ff-96fd-535086d44579 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62302280 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 87.xbar_smoke_large_delays.62302280 |
| Directory | /workspace/87.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/87.xbar_smoke_slow_rsp.1547108774 |
| Short name | T2225 |
| Test name | |
| Test status | |
| Simulation time | 5162848465 ps |
| CPU time | 83.69 seconds |
| Started | Jun 23 07:39:05 PM PDT 24 |
| Finished | Jun 23 07:40:29 PM PDT 24 |
| Peak memory | 565936 kb |
| Host | smart-d19eeb9a-eafe-43d7-98ec-fdc525cecf59 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1547108774 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 87.xbar_smoke_slow_rsp.1547108774 |
| Directory | /workspace/87.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/87.xbar_smoke_zero_delays.491804898 |
| Short name | T2658 |
| Test name | |
| Test status | |
| Simulation time | 39162107 ps |
| CPU time | 5.67 seconds |
| Started | Jun 23 07:39:08 PM PDT 24 |
| Finished | Jun 23 07:39:14 PM PDT 24 |
| Peak memory | 565528 kb |
| Host | smart-53b13ca6-906d-4053-8cd3-7fab34791d5b |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=491804898 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 87.xbar_smoke_zero_delays .491804898 |
| Directory | /workspace/87.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/87.xbar_stress_all.8887367 |
| Short name | T618 |
| Test name | |
| Test status | |
| Simulation time | 15058234127 ps |
| CPU time | 612.18 seconds |
| Started | Jun 23 07:39:19 PM PDT 24 |
| Finished | Jun 23 07:49:32 PM PDT 24 |
| Peak memory | 574312 kb |
| Host | smart-b8d954e8-9e2b-4ee7-acad-2246bbfe55f6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=8887367 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 87.xbar_stress_all.8887367 |
| Directory | /workspace/87.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/87.xbar_stress_all_with_error.3061654565 |
| Short name | T2701 |
| Test name | |
| Test status | |
| Simulation time | 2257795523 ps |
| CPU time | 177.27 seconds |
| Started | Jun 23 07:39:24 PM PDT 24 |
| Finished | Jun 23 07:42:22 PM PDT 24 |
| Peak memory | 574364 kb |
| Host | smart-0367fdf2-72cd-4013-8322-a0bce4e7565d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3061654565 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 87.xbar_stress_all_with_error.3061654565 |
| Directory | /workspace/87.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/87.xbar_stress_all_with_rand_reset.539480051 |
| Short name | T475 |
| Test name | |
| Test status | |
| Simulation time | 2044257379 ps |
| CPU time | 246.21 seconds |
| Started | Jun 23 07:39:19 PM PDT 24 |
| Finished | Jun 23 07:43:26 PM PDT 24 |
| Peak memory | 574252 kb |
| Host | smart-e0494d0a-1ea6-4714-8cee-a6dabf8ace96 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=539480051 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_res et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 87.xbar_stress_all_ with_rand_reset.539480051 |
| Directory | /workspace/87.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/87.xbar_stress_all_with_reset_error.3434160589 |
| Short name | T887 |
| Test name | |
| Test status | |
| Simulation time | 5403541863 ps |
| CPU time | 311.21 seconds |
| Started | Jun 23 07:39:25 PM PDT 24 |
| Finished | Jun 23 07:44:37 PM PDT 24 |
| Peak memory | 574372 kb |
| Host | smart-b8f778f1-f2bd-4894-b760-d504db2ad766 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3434160589 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 87.xbar_stress_al l_with_reset_error.3434160589 |
| Directory | /workspace/87.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/87.xbar_unmapped_addr.946294962 |
| Short name | T2775 |
| Test name | |
| Test status | |
| Simulation time | 498939700 ps |
| CPU time | 21.44 seconds |
| Started | Jun 23 07:39:19 PM PDT 24 |
| Finished | Jun 23 07:39:40 PM PDT 24 |
| Peak memory | 574104 kb |
| Host | smart-b5051cc1-e71f-40fd-a218-faca3b4d5fd9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=946294962 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 87.xbar_unmapped_addr.946294962 |
| Directory | /workspace/87.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/88.xbar_access_same_device.2984075070 |
| Short name | T2804 |
| Test name | |
| Test status | |
| Simulation time | 212669468 ps |
| CPU time | 14.76 seconds |
| Started | Jun 23 07:39:25 PM PDT 24 |
| Finished | Jun 23 07:39:40 PM PDT 24 |
| Peak memory | 573952 kb |
| Host | smart-2322c5e3-333e-4ed3-8486-3fd94a47a22c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2984075070 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 88.xbar_access_same_device .2984075070 |
| Directory | /workspace/88.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/88.xbar_access_same_device_slow_rsp.3474626858 |
| Short name | T851 |
| Test name | |
| Test status | |
| Simulation time | 27713425553 ps |
| CPU time | 488.08 seconds |
| Started | Jun 23 07:39:24 PM PDT 24 |
| Finished | Jun 23 07:47:33 PM PDT 24 |
| Peak memory | 574204 kb |
| Host | smart-60ff071c-0f95-4d1f-8ee6-db8159dcc566 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3474626858 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 88.xbar_access_same_ device_slow_rsp.3474626858 |
| Directory | /workspace/88.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/88.xbar_error_and_unmapped_addr.620169262 |
| Short name | T2659 |
| Test name | |
| Test status | |
| Simulation time | 39480307 ps |
| CPU time | 6.97 seconds |
| Started | Jun 23 07:39:24 PM PDT 24 |
| Finished | Jun 23 07:39:31 PM PDT 24 |
| Peak memory | 565456 kb |
| Host | smart-69af49fc-2a6d-4d67-bffe-35bec14b21a2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=620169262 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 88.xbar_error_and_unmapped_addr .620169262 |
| Directory | /workspace/88.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/88.xbar_error_random.2998010814 |
| Short name | T1574 |
| Test name | |
| Test status | |
| Simulation time | 248500131 ps |
| CPU time | 11.09 seconds |
| Started | Jun 23 07:39:24 PM PDT 24 |
| Finished | Jun 23 07:39:36 PM PDT 24 |
| Peak memory | 573712 kb |
| Host | smart-60472c22-73a4-4daa-a41f-714994f84343 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2998010814 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 88.xbar_error_random.2998010814 |
| Directory | /workspace/88.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/88.xbar_random.293128029 |
| Short name | T1631 |
| Test name | |
| Test status | |
| Simulation time | 363217245 ps |
| CPU time | 33.28 seconds |
| Started | Jun 23 07:39:26 PM PDT 24 |
| Finished | Jun 23 07:40:00 PM PDT 24 |
| Peak memory | 573444 kb |
| Host | smart-34440fd8-1367-49e9-9b30-0fb9abebd25b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=293128029 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 88.xbar_random.293128029 |
| Directory | /workspace/88.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/88.xbar_random_large_delays.2744220559 |
| Short name | T2435 |
| Test name | |
| Test status | |
| Simulation time | 12330786267 ps |
| CPU time | 130.71 seconds |
| Started | Jun 23 07:39:24 PM PDT 24 |
| Finished | Jun 23 07:41:35 PM PDT 24 |
| Peak memory | 574204 kb |
| Host | smart-9b73d79e-b14b-4a8a-b6e9-ced28ed26b3b |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2744220559 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 88.xbar_random_large_delays.2744220559 |
| Directory | /workspace/88.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/88.xbar_random_slow_rsp.94991156 |
| Short name | T653 |
| Test name | |
| Test status | |
| Simulation time | 62920977980 ps |
| CPU time | 1154.28 seconds |
| Started | Jun 23 07:39:24 PM PDT 24 |
| Finished | Jun 23 07:58:39 PM PDT 24 |
| Peak memory | 574184 kb |
| Host | smart-20d8b9d6-320b-4350-99cc-9b96ffa8b3fc |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94991156 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 88.xbar_random_slow_rsp.94991156 |
| Directory | /workspace/88.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/88.xbar_random_zero_delays.3766208033 |
| Short name | T2502 |
| Test name | |
| Test status | |
| Simulation time | 229518375 ps |
| CPU time | 21.5 seconds |
| Started | Jun 23 07:39:26 PM PDT 24 |
| Finished | Jun 23 07:39:48 PM PDT 24 |
| Peak memory | 574072 kb |
| Host | smart-ce771979-b8f3-47d3-8061-b1e66e610063 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3766208033 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 88.xbar_random_zero_del ays.3766208033 |
| Directory | /workspace/88.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/88.xbar_same_source.536516253 |
| Short name | T2023 |
| Test name | |
| Test status | |
| Simulation time | 1422571785 ps |
| CPU time | 40.95 seconds |
| Started | Jun 23 07:39:24 PM PDT 24 |
| Finished | Jun 23 07:40:06 PM PDT 24 |
| Peak memory | 574036 kb |
| Host | smart-390b351c-4091-49c3-9f3a-8dd9c4c4cb7e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=536516253 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 88.xbar_same_source.536516253 |
| Directory | /workspace/88.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/88.xbar_smoke.3140951236 |
| Short name | T2147 |
| Test name | |
| Test status | |
| Simulation time | 167172391 ps |
| CPU time | 8.23 seconds |
| Started | Jun 23 07:39:26 PM PDT 24 |
| Finished | Jun 23 07:39:35 PM PDT 24 |
| Peak memory | 565476 kb |
| Host | smart-6444699b-c9ac-40bd-9b08-33d936e6e567 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3140951236 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 88.xbar_smoke.3140951236 |
| Directory | /workspace/88.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/88.xbar_smoke_large_delays.2813044241 |
| Short name | T2066 |
| Test name | |
| Test status | |
| Simulation time | 8866751647 ps |
| CPU time | 90.1 seconds |
| Started | Jun 23 07:39:27 PM PDT 24 |
| Finished | Jun 23 07:40:57 PM PDT 24 |
| Peak memory | 565204 kb |
| Host | smart-d000af50-574f-4f05-a73a-c5e4097b3545 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2813044241 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 88.xbar_smoke_large_delays.2813044241 |
| Directory | /workspace/88.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/88.xbar_smoke_slow_rsp.1212438825 |
| Short name | T2514 |
| Test name | |
| Test status | |
| Simulation time | 4582429757 ps |
| CPU time | 76.91 seconds |
| Started | Jun 23 07:39:25 PM PDT 24 |
| Finished | Jun 23 07:40:42 PM PDT 24 |
| Peak memory | 573744 kb |
| Host | smart-d1ae832a-a94e-4320-afb3-734edee83bc3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1212438825 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 88.xbar_smoke_slow_rsp.1212438825 |
| Directory | /workspace/88.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/88.xbar_smoke_zero_delays.1128461256 |
| Short name | T1477 |
| Test name | |
| Test status | |
| Simulation time | 44690967 ps |
| CPU time | 5.97 seconds |
| Started | Jun 23 07:39:25 PM PDT 24 |
| Finished | Jun 23 07:39:31 PM PDT 24 |
| Peak memory | 573380 kb |
| Host | smart-220ec3f4-365e-4363-91d1-c22b29c59aa2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1128461256 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 88.xbar_smoke_zero_delay s.1128461256 |
| Directory | /workspace/88.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/88.xbar_stress_all.1444168214 |
| Short name | T2874 |
| Test name | |
| Test status | |
| Simulation time | 7722616209 ps |
| CPU time | 299.89 seconds |
| Started | Jun 23 07:39:24 PM PDT 24 |
| Finished | Jun 23 07:44:25 PM PDT 24 |
| Peak memory | 574324 kb |
| Host | smart-74486fd8-ca32-424a-9ed4-7c59a46e71c2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1444168214 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 88.xbar_stress_all.1444168214 |
| Directory | /workspace/88.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/88.xbar_stress_all_with_error.3863438555 |
| Short name | T1586 |
| Test name | |
| Test status | |
| Simulation time | 7987402265 ps |
| CPU time | 312.03 seconds |
| Started | Jun 23 07:39:27 PM PDT 24 |
| Finished | Jun 23 07:44:39 PM PDT 24 |
| Peak memory | 574288 kb |
| Host | smart-e6b0e0f6-0caa-47af-a6e7-2b16e0dbbc49 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3863438555 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 88.xbar_stress_all_with_error.3863438555 |
| Directory | /workspace/88.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/88.xbar_stress_all_with_reset_error.1886324876 |
| Short name | T2656 |
| Test name | |
| Test status | |
| Simulation time | 64047012 ps |
| CPU time | 34.12 seconds |
| Started | Jun 23 07:39:25 PM PDT 24 |
| Finished | Jun 23 07:40:00 PM PDT 24 |
| Peak memory | 575316 kb |
| Host | smart-1e76b9cf-8388-4a81-b12a-dbf2ad9d4eb2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1886324876 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 88.xbar_stress_al l_with_reset_error.1886324876 |
| Directory | /workspace/88.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/88.xbar_unmapped_addr.1108200962 |
| Short name | T637 |
| Test name | |
| Test status | |
| Simulation time | 783651731 ps |
| CPU time | 33.34 seconds |
| Started | Jun 23 07:39:25 PM PDT 24 |
| Finished | Jun 23 07:39:59 PM PDT 24 |
| Peak memory | 574064 kb |
| Host | smart-914f43d7-af23-4f9a-810f-b76133ce23f7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1108200962 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 88.xbar_unmapped_addr.1108200962 |
| Directory | /workspace/88.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/89.xbar_access_same_device.221964565 |
| Short name | T704 |
| Test name | |
| Test status | |
| Simulation time | 632176402 ps |
| CPU time | 51.57 seconds |
| Started | Jun 23 07:39:33 PM PDT 24 |
| Finished | Jun 23 07:40:25 PM PDT 24 |
| Peak memory | 574124 kb |
| Host | smart-35b8fd04-e437-4750-87f6-309a7b40700b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=221964565 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 89.xbar_access_same_device. 221964565 |
| Directory | /workspace/89.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/89.xbar_access_same_device_slow_rsp.4107217026 |
| Short name | T873 |
| Test name | |
| Test status | |
| Simulation time | 111784179961 ps |
| CPU time | 2071.62 seconds |
| Started | Jun 23 07:39:32 PM PDT 24 |
| Finished | Jun 23 08:14:05 PM PDT 24 |
| Peak memory | 573544 kb |
| Host | smart-58391427-04a8-43c2-bcc5-e26ae20bfc69 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4107217026 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 89.xbar_access_same_ device_slow_rsp.4107217026 |
| Directory | /workspace/89.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/89.xbar_error_and_unmapped_addr.2354769004 |
| Short name | T1412 |
| Test name | |
| Test status | |
| Simulation time | 1398570513 ps |
| CPU time | 45.63 seconds |
| Started | Jun 23 07:39:42 PM PDT 24 |
| Finished | Jun 23 07:40:28 PM PDT 24 |
| Peak memory | 573736 kb |
| Host | smart-becd074f-3845-4ab6-81cc-f3d440058de2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2354769004 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 89.xbar_error_and_unmapped_add r.2354769004 |
| Directory | /workspace/89.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/89.xbar_error_random.2383110731 |
| Short name | T1739 |
| Test name | |
| Test status | |
| Simulation time | 513093529 ps |
| CPU time | 20.99 seconds |
| Started | Jun 23 07:39:34 PM PDT 24 |
| Finished | Jun 23 07:39:55 PM PDT 24 |
| Peak memory | 573644 kb |
| Host | smart-c2622a5f-b174-480e-8c47-c5f59ab36498 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2383110731 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 89.xbar_error_random.2383110731 |
| Directory | /workspace/89.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/89.xbar_random.896121386 |
| Short name | T2463 |
| Test name | |
| Test status | |
| Simulation time | 269085226 ps |
| CPU time | 22.46 seconds |
| Started | Jun 23 07:39:30 PM PDT 24 |
| Finished | Jun 23 07:39:53 PM PDT 24 |
| Peak memory | 574124 kb |
| Host | smart-372265ea-6def-4a55-8980-2da51a253777 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=896121386 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 89.xbar_random.896121386 |
| Directory | /workspace/89.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/89.xbar_random_large_delays.3634644948 |
| Short name | T1850 |
| Test name | |
| Test status | |
| Simulation time | 91773356703 ps |
| CPU time | 1047.8 seconds |
| Started | Jun 23 07:39:30 PM PDT 24 |
| Finished | Jun 23 07:56:58 PM PDT 24 |
| Peak memory | 574148 kb |
| Host | smart-4b7c9f74-774a-4fef-bd68-7320ceb22b10 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3634644948 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 89.xbar_random_large_delays.3634644948 |
| Directory | /workspace/89.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/89.xbar_random_slow_rsp.3480731005 |
| Short name | T1651 |
| Test name | |
| Test status | |
| Simulation time | 8908741094 ps |
| CPU time | 148.43 seconds |
| Started | Jun 23 07:39:41 PM PDT 24 |
| Finished | Jun 23 07:42:09 PM PDT 24 |
| Peak memory | 574164 kb |
| Host | smart-51fe9191-2c14-42f3-a1dd-ef687f1882ed |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3480731005 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 89.xbar_random_slow_rsp.3480731005 |
| Directory | /workspace/89.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/89.xbar_random_zero_delays.3053209730 |
| Short name | T1821 |
| Test name | |
| Test status | |
| Simulation time | 165806378 ps |
| CPU time | 19.5 seconds |
| Started | Jun 23 07:39:32 PM PDT 24 |
| Finished | Jun 23 07:39:52 PM PDT 24 |
| Peak memory | 574052 kb |
| Host | smart-48e267bc-9af9-467e-b167-1f67062e4ba7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3053209730 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 89.xbar_random_zero_del ays.3053209730 |
| Directory | /workspace/89.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/89.xbar_same_source.4274546672 |
| Short name | T2584 |
| Test name | |
| Test status | |
| Simulation time | 921032566 ps |
| CPU time | 31.63 seconds |
| Started | Jun 23 07:39:33 PM PDT 24 |
| Finished | Jun 23 07:40:05 PM PDT 24 |
| Peak memory | 574076 kb |
| Host | smart-6abc1512-e59d-437e-b359-214c3f6946a4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4274546672 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 89.xbar_same_source.4274546672 |
| Directory | /workspace/89.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/89.xbar_smoke.2951274590 |
| Short name | T1369 |
| Test name | |
| Test status | |
| Simulation time | 180529991 ps |
| CPU time | 8.18 seconds |
| Started | Jun 23 07:39:29 PM PDT 24 |
| Finished | Jun 23 07:39:37 PM PDT 24 |
| Peak memory | 565616 kb |
| Host | smart-9759f4ab-3001-49c0-9e5e-bec47955d64f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2951274590 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 89.xbar_smoke.2951274590 |
| Directory | /workspace/89.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/89.xbar_smoke_large_delays.3472576774 |
| Short name | T2611 |
| Test name | |
| Test status | |
| Simulation time | 9086712327 ps |
| CPU time | 96.23 seconds |
| Started | Jun 23 07:39:27 PM PDT 24 |
| Finished | Jun 23 07:41:04 PM PDT 24 |
| Peak memory | 565928 kb |
| Host | smart-fce8c6e4-63f9-42ad-ade4-537571b5d3e3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3472576774 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 89.xbar_smoke_large_delays.3472576774 |
| Directory | /workspace/89.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/89.xbar_smoke_slow_rsp.261320011 |
| Short name | T2017 |
| Test name | |
| Test status | |
| Simulation time | 6063428288 ps |
| CPU time | 103.14 seconds |
| Started | Jun 23 07:39:29 PM PDT 24 |
| Finished | Jun 23 07:41:12 PM PDT 24 |
| Peak memory | 565916 kb |
| Host | smart-947205db-2ade-41a0-a1f5-c364160c3c39 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=261320011 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 89.xbar_smoke_slow_rsp.261320011 |
| Directory | /workspace/89.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/89.xbar_smoke_zero_delays.728802850 |
| Short name | T2059 |
| Test name | |
| Test status | |
| Simulation time | 47829837 ps |
| CPU time | 6.13 seconds |
| Started | Jun 23 07:39:30 PM PDT 24 |
| Finished | Jun 23 07:39:36 PM PDT 24 |
| Peak memory | 565488 kb |
| Host | smart-672f7162-a28c-4555-9464-241a984ae671 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=728802850 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 89.xbar_smoke_zero_delays .728802850 |
| Directory | /workspace/89.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/89.xbar_stress_all.934843336 |
| Short name | T2198 |
| Test name | |
| Test status | |
| Simulation time | 1318572926 ps |
| CPU time | 107.33 seconds |
| Started | Jun 23 07:39:36 PM PDT 24 |
| Finished | Jun 23 07:41:24 PM PDT 24 |
| Peak memory | 574228 kb |
| Host | smart-3e308b59-bb30-404e-9ecf-a7074bdcf352 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=934843336 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 89.xbar_stress_all.934843336 |
| Directory | /workspace/89.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/89.xbar_stress_all_with_error.2018498797 |
| Short name | T2806 |
| Test name | |
| Test status | |
| Simulation time | 228373739 ps |
| CPU time | 19.47 seconds |
| Started | Jun 23 07:39:38 PM PDT 24 |
| Finished | Jun 23 07:39:58 PM PDT 24 |
| Peak memory | 574172 kb |
| Host | smart-beaa0373-d892-4958-9944-63c5bd2c57cf |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2018498797 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 89.xbar_stress_all_with_error.2018498797 |
| Directory | /workspace/89.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/89.xbar_stress_all_with_rand_reset.2637088958 |
| Short name | T612 |
| Test name | |
| Test status | |
| Simulation time | 401710421 ps |
| CPU time | 212.73 seconds |
| Started | Jun 23 07:39:46 PM PDT 24 |
| Finished | Jun 23 07:43:19 PM PDT 24 |
| Peak memory | 574252 kb |
| Host | smart-b1d1402c-4530-4a1c-9915-1b239096bdc4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2637088958 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 89.xbar_stress_all _with_rand_reset.2637088958 |
| Directory | /workspace/89.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/89.xbar_stress_all_with_reset_error.2609825833 |
| Short name | T1557 |
| Test name | |
| Test status | |
| Simulation time | 1021083105 ps |
| CPU time | 65.72 seconds |
| Started | Jun 23 07:39:46 PM PDT 24 |
| Finished | Jun 23 07:40:52 PM PDT 24 |
| Peak memory | 574284 kb |
| Host | smart-a65db54b-d452-419c-a83a-1b13e2df69c1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2609825833 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 89.xbar_stress_al l_with_reset_error.2609825833 |
| Directory | /workspace/89.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/89.xbar_unmapped_addr.1678160693 |
| Short name | T1927 |
| Test name | |
| Test status | |
| Simulation time | 228596758 ps |
| CPU time | 25.8 seconds |
| Started | Jun 23 07:39:36 PM PDT 24 |
| Finished | Jun 23 07:40:03 PM PDT 24 |
| Peak memory | 574120 kb |
| Host | smart-22479671-a6cb-49ed-aedd-859dbbe7a7cf |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1678160693 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 89.xbar_unmapped_addr.1678160693 |
| Directory | /workspace/89.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/9.chip_csr_rw.1520171830 |
| Short name | T1893 |
| Test name | |
| Test status | |
| Simulation time | 4381529666 ps |
| CPU time | 276.6 seconds |
| Started | Jun 23 07:22:59 PM PDT 24 |
| Finished | Jun 23 07:27:36 PM PDT 24 |
| Peak memory | 595184 kb |
| Host | smart-1c22601d-1b24-4a2f-a59a-95566d276a7b |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1520171830 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.chip_csr_rw.1520171830 |
| Directory | /workspace/9.chip_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/9.chip_same_csr_outstanding.4114262891 |
| Short name | T2523 |
| Test name | |
| Test status | |
| Simulation time | 29870215617 ps |
| CPU time | 4942.61 seconds |
| Started | Jun 23 07:22:50 PM PDT 24 |
| Finished | Jun 23 08:45:13 PM PDT 24 |
| Peak memory | 591292 kb |
| Host | smart-3cbda968-9df3-4429-a6ff-02f34d7f61f5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +run_same_csr_outstanding +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4114262891 -assert nopostproc +UVM_TE STNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb - cm_log /dev/null -cm_name 9.chip_same_csr_outstanding.4114262891 |
| Directory | /workspace/9.chip_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/9.chip_tl_errors.3327263760 |
| Short name | T724 |
| Test name | |
| Test status | |
| Simulation time | 3926127998 ps |
| CPU time | 355.09 seconds |
| Started | Jun 23 07:22:42 PM PDT 24 |
| Finished | Jun 23 07:28:37 PM PDT 24 |
| Peak memory | 596380 kb |
| Host | smart-38a231b8-06a5-495c-980a-f62db3774ce5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3327263760 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.chip_tl_errors.3327263760 |
| Directory | /workspace/9.chip_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/9.xbar_access_same_device.2393322334 |
| Short name | T2500 |
| Test name | |
| Test status | |
| Simulation time | 1845533732 ps |
| CPU time | 74.75 seconds |
| Started | Jun 23 07:22:44 PM PDT 24 |
| Finished | Jun 23 07:23:59 PM PDT 24 |
| Peak memory | 573452 kb |
| Host | smart-dae362c2-1caf-4131-aeb1-c5abd9477a89 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2393322334 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.xbar_access_same_device. 2393322334 |
| Directory | /workspace/9.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/9.xbar_access_same_device_slow_rsp.2343866954 |
| Short name | T2251 |
| Test name | |
| Test status | |
| Simulation time | 75043173440 ps |
| CPU time | 1235.1 seconds |
| Started | Jun 23 07:22:46 PM PDT 24 |
| Finished | Jun 23 07:43:22 PM PDT 24 |
| Peak memory | 574244 kb |
| Host | smart-063086c3-efb1-4ee9-b295-e03d6c05cda9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2343866954 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.xbar_access_same_d evice_slow_rsp.2343866954 |
| Directory | /workspace/9.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/9.xbar_error_and_unmapped_addr.641959165 |
| Short name | T2653 |
| Test name | |
| Test status | |
| Simulation time | 1468012170 ps |
| CPU time | 57.6 seconds |
| Started | Jun 23 07:22:53 PM PDT 24 |
| Finished | Jun 23 07:23:51 PM PDT 24 |
| Peak memory | 573664 kb |
| Host | smart-e2973bf6-5496-41a8-af09-30670ee9233b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=641959165 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.xbar_error_and_unmapped_addr. 641959165 |
| Directory | /workspace/9.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/9.xbar_error_random.4137650056 |
| Short name | T2189 |
| Test name | |
| Test status | |
| Simulation time | 1032577390 ps |
| CPU time | 34.52 seconds |
| Started | Jun 23 07:22:53 PM PDT 24 |
| Finished | Jun 23 07:23:28 PM PDT 24 |
| Peak memory | 573712 kb |
| Host | smart-d948fc5b-89a3-4728-be41-8bea57aa8174 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4137650056 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.xbar_error_random.4137650056 |
| Directory | /workspace/9.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/9.xbar_random.755853181 |
| Short name | T2415 |
| Test name | |
| Test status | |
| Simulation time | 1766002278 ps |
| CPU time | 71.04 seconds |
| Started | Jun 23 07:22:47 PM PDT 24 |
| Finished | Jun 23 07:23:58 PM PDT 24 |
| Peak memory | 574088 kb |
| Host | smart-0775f6ee-6913-4f54-bf14-a14ec6922be6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=755853181 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.xbar_random.755853181 |
| Directory | /workspace/9.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/9.xbar_random_large_delays.339366765 |
| Short name | T2707 |
| Test name | |
| Test status | |
| Simulation time | 62699246989 ps |
| CPU time | 694.45 seconds |
| Started | Jun 23 07:22:46 PM PDT 24 |
| Finished | Jun 23 07:34:21 PM PDT 24 |
| Peak memory | 574188 kb |
| Host | smart-61b1f86b-069d-4ecc-9414-2ee61d239514 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=339366765 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.xbar_random_large_delays.339366765 |
| Directory | /workspace/9.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/9.xbar_random_slow_rsp.425616692 |
| Short name | T1922 |
| Test name | |
| Test status | |
| Simulation time | 41513535695 ps |
| CPU time | 731.99 seconds |
| Started | Jun 23 07:22:47 PM PDT 24 |
| Finished | Jun 23 07:34:59 PM PDT 24 |
| Peak memory | 574184 kb |
| Host | smart-916fd956-2458-4908-985c-20c59f0df9c2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=425616692 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.xbar_random_slow_rsp.425616692 |
| Directory | /workspace/9.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/9.xbar_random_zero_delays.2899089496 |
| Short name | T537 |
| Test name | |
| Test status | |
| Simulation time | 222118263 ps |
| CPU time | 22.34 seconds |
| Started | Jun 23 07:22:45 PM PDT 24 |
| Finished | Jun 23 07:23:08 PM PDT 24 |
| Peak memory | 574080 kb |
| Host | smart-13d97b78-4f07-4511-8805-853b8d1fe36b |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2899089496 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.xbar_random_zero_dela ys.2899089496 |
| Directory | /workspace/9.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/9.xbar_same_source.1110465109 |
| Short name | T2664 |
| Test name | |
| Test status | |
| Simulation time | 387519228 ps |
| CPU time | 28.29 seconds |
| Started | Jun 23 07:22:47 PM PDT 24 |
| Finished | Jun 23 07:23:16 PM PDT 24 |
| Peak memory | 573412 kb |
| Host | smart-d3f63535-3c0a-49b5-9c37-ebd5ab21f7fd |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1110465109 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.xbar_same_source.1110465109 |
| Directory | /workspace/9.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/9.xbar_smoke.1387227726 |
| Short name | T2329 |
| Test name | |
| Test status | |
| Simulation time | 51302890 ps |
| CPU time | 6.9 seconds |
| Started | Jun 23 07:22:43 PM PDT 24 |
| Finished | Jun 23 07:22:50 PM PDT 24 |
| Peak memory | 565456 kb |
| Host | smart-63c9678e-b44f-404b-97cd-491056f43a96 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1387227726 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.xbar_smoke.1387227726 |
| Directory | /workspace/9.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/9.xbar_smoke_large_delays.4206672781 |
| Short name | T1993 |
| Test name | |
| Test status | |
| Simulation time | 8526132900 ps |
| CPU time | 87.56 seconds |
| Started | Jun 23 07:22:43 PM PDT 24 |
| Finished | Jun 23 07:24:10 PM PDT 24 |
| Peak memory | 565940 kb |
| Host | smart-e18d8387-2063-443e-ac6e-c9bd7a1d319c |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4206672781 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.xbar_smoke_large_delays.4206672781 |
| Directory | /workspace/9.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/9.xbar_smoke_slow_rsp.3581578491 |
| Short name | T1823 |
| Test name | |
| Test status | |
| Simulation time | 3892611891 ps |
| CPU time | 64.69 seconds |
| Started | Jun 23 07:22:50 PM PDT 24 |
| Finished | Jun 23 07:23:55 PM PDT 24 |
| Peak memory | 565532 kb |
| Host | smart-b2c07b8b-967f-4b5b-9c6b-aec6ca5e19a8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3581578491 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.xbar_smoke_slow_rsp.3581578491 |
| Directory | /workspace/9.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/9.xbar_smoke_zero_delays.2028616228 |
| Short name | T2777 |
| Test name | |
| Test status | |
| Simulation time | 48667959 ps |
| CPU time | 6.39 seconds |
| Started | Jun 23 07:22:45 PM PDT 24 |
| Finished | Jun 23 07:22:52 PM PDT 24 |
| Peak memory | 565116 kb |
| Host | smart-d555e903-fdd4-424d-af04-f842fc5b20fe |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2028616228 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.xbar_smoke_zero_delays .2028616228 |
| Directory | /workspace/9.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/9.xbar_stress_all.3637373992 |
| Short name | T2740 |
| Test name | |
| Test status | |
| Simulation time | 2267906362 ps |
| CPU time | 191.77 seconds |
| Started | Jun 23 07:22:51 PM PDT 24 |
| Finished | Jun 23 07:26:03 PM PDT 24 |
| Peak memory | 574316 kb |
| Host | smart-eeaf0583-1343-4df0-833e-831dde55d566 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3637373992 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.xbar_stress_all.3637373992 |
| Directory | /workspace/9.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/9.xbar_stress_all_with_error.2303730285 |
| Short name | T2111 |
| Test name | |
| Test status | |
| Simulation time | 5117170677 ps |
| CPU time | 161.92 seconds |
| Started | Jun 23 07:22:50 PM PDT 24 |
| Finished | Jun 23 07:25:32 PM PDT 24 |
| Peak memory | 573520 kb |
| Host | smart-96f954b6-3f30-4be7-8a0b-ca822271ea78 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2303730285 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.xbar_stress_all_with_error.2303730285 |
| Directory | /workspace/9.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/9.xbar_stress_all_with_rand_reset.41414295 |
| Short name | T904 |
| Test name | |
| Test status | |
| Simulation time | 82334630 ps |
| CPU time | 76.78 seconds |
| Started | Jun 23 07:22:51 PM PDT 24 |
| Finished | Jun 23 07:24:08 PM PDT 24 |
| Peak memory | 574232 kb |
| Host | smart-6e792877-fa07-4207-8755-cd12cfedb003 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41414295 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_rese t_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.xbar_stress_all_wi th_rand_reset.41414295 |
| Directory | /workspace/9.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/9.xbar_stress_all_with_reset_error.273677689 |
| Short name | T1880 |
| Test name | |
| Test status | |
| Simulation time | 3665549556 ps |
| CPU time | 310.99 seconds |
| Started | Jun 23 07:22:55 PM PDT 24 |
| Finished | Jun 23 07:28:07 PM PDT 24 |
| Peak memory | 576388 kb |
| Host | smart-b758cbe8-18b1-4c92-857b-122c06505b2b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=273677689 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.xbar_stress_all_ with_reset_error.273677689 |
| Directory | /workspace/9.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/9.xbar_unmapped_addr.3668779675 |
| Short name | T2842 |
| Test name | |
| Test status | |
| Simulation time | 870153109 ps |
| CPU time | 31.3 seconds |
| Started | Jun 23 07:22:54 PM PDT 24 |
| Finished | Jun 23 07:23:25 PM PDT 24 |
| Peak memory | 574140 kb |
| Host | smart-dd0182c7-220c-46f9-9783-fbd081905936 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3668779675 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.xbar_unmapped_addr.3668779675 |
| Directory | /workspace/9.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/90.xbar_access_same_device.3423715762 |
| Short name | T2764 |
| Test name | |
| Test status | |
| Simulation time | 226988704 ps |
| CPU time | 21.05 seconds |
| Started | Jun 23 07:40:02 PM PDT 24 |
| Finished | Jun 23 07:40:23 PM PDT 24 |
| Peak memory | 574088 kb |
| Host | smart-7ddc1b3e-a3b8-4328-90ee-7ac087c5cd3d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3423715762 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 90.xbar_access_same_device .3423715762 |
| Directory | /workspace/90.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/90.xbar_access_same_device_slow_rsp.705990933 |
| Short name | T2799 |
| Test name | |
| Test status | |
| Simulation time | 48271295047 ps |
| CPU time | 826.58 seconds |
| Started | Jun 23 07:40:02 PM PDT 24 |
| Finished | Jun 23 07:53:50 PM PDT 24 |
| Peak memory | 574224 kb |
| Host | smart-764ba8df-4bab-461a-8864-55bded46301b |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=705990933 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 90.xbar_access_same_d evice_slow_rsp.705990933 |
| Directory | /workspace/90.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/90.xbar_error_and_unmapped_addr.3125582046 |
| Short name | T1994 |
| Test name | |
| Test status | |
| Simulation time | 1221076356 ps |
| CPU time | 43.17 seconds |
| Started | Jun 23 07:40:00 PM PDT 24 |
| Finished | Jun 23 07:40:44 PM PDT 24 |
| Peak memory | 573800 kb |
| Host | smart-e42d830c-af7c-4d80-95f6-9a8d0cb6722a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3125582046 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 90.xbar_error_and_unmapped_add r.3125582046 |
| Directory | /workspace/90.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/90.xbar_error_random.2547682057 |
| Short name | T1975 |
| Test name | |
| Test status | |
| Simulation time | 1223704866 ps |
| CPU time | 39.59 seconds |
| Started | Jun 23 07:40:00 PM PDT 24 |
| Finished | Jun 23 07:40:40 PM PDT 24 |
| Peak memory | 573636 kb |
| Host | smart-af818cab-2a59-402d-9103-3afce35df4f8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2547682057 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 90.xbar_error_random.2547682057 |
| Directory | /workspace/90.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/90.xbar_random.3409221323 |
| Short name | T2857 |
| Test name | |
| Test status | |
| Simulation time | 217833134 ps |
| CPU time | 20.32 seconds |
| Started | Jun 23 07:39:56 PM PDT 24 |
| Finished | Jun 23 07:40:17 PM PDT 24 |
| Peak memory | 574100 kb |
| Host | smart-98dd2502-1610-41e6-8647-0fa800a32be2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3409221323 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 90.xbar_random.3409221323 |
| Directory | /workspace/90.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/90.xbar_random_large_delays.2651491009 |
| Short name | T2157 |
| Test name | |
| Test status | |
| Simulation time | 59209273162 ps |
| CPU time | 635.82 seconds |
| Started | Jun 23 07:39:57 PM PDT 24 |
| Finished | Jun 23 07:50:33 PM PDT 24 |
| Peak memory | 573528 kb |
| Host | smart-056705a5-8a7c-4290-8459-717806f14c6d |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2651491009 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 90.xbar_random_large_delays.2651491009 |
| Directory | /workspace/90.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/90.xbar_random_slow_rsp.3097105389 |
| Short name | T2645 |
| Test name | |
| Test status | |
| Simulation time | 47780542266 ps |
| CPU time | 872.43 seconds |
| Started | Jun 23 07:40:10 PM PDT 24 |
| Finished | Jun 23 07:54:43 PM PDT 24 |
| Peak memory | 574208 kb |
| Host | smart-5c8e6266-04fb-4eb2-911f-66e7c14866ef |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3097105389 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 90.xbar_random_slow_rsp.3097105389 |
| Directory | /workspace/90.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/90.xbar_random_zero_delays.1962602259 |
| Short name | T2158 |
| Test name | |
| Test status | |
| Simulation time | 124427112 ps |
| CPU time | 13.47 seconds |
| Started | Jun 23 07:39:58 PM PDT 24 |
| Finished | Jun 23 07:40:12 PM PDT 24 |
| Peak memory | 574104 kb |
| Host | smart-2d430b27-10ac-4921-9ecd-8ecc2ccc28bb |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1962602259 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 90.xbar_random_zero_del ays.1962602259 |
| Directory | /workspace/90.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/90.xbar_same_source.509438564 |
| Short name | T2585 |
| Test name | |
| Test status | |
| Simulation time | 478378556 ps |
| CPU time | 34.75 seconds |
| Started | Jun 23 07:40:00 PM PDT 24 |
| Finished | Jun 23 07:40:35 PM PDT 24 |
| Peak memory | 574200 kb |
| Host | smart-7c3956c7-2be1-4cd2-988e-a3cf4be39d2f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=509438564 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 90.xbar_same_source.509438564 |
| Directory | /workspace/90.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/90.xbar_smoke.339212040 |
| Short name | T1896 |
| Test name | |
| Test status | |
| Simulation time | 46370895 ps |
| CPU time | 6.7 seconds |
| Started | Jun 23 07:39:58 PM PDT 24 |
| Finished | Jun 23 07:40:05 PM PDT 24 |
| Peak memory | 573708 kb |
| Host | smart-1e810726-9508-45dd-8493-a75284bbaceb |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=339212040 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 90.xbar_smoke.339212040 |
| Directory | /workspace/90.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/90.xbar_smoke_large_delays.1440237804 |
| Short name | T1906 |
| Test name | |
| Test status | |
| Simulation time | 9138563172 ps |
| CPU time | 91.49 seconds |
| Started | Jun 23 07:39:56 PM PDT 24 |
| Finished | Jun 23 07:41:28 PM PDT 24 |
| Peak memory | 565924 kb |
| Host | smart-00322964-1b6a-4bba-b040-1d7d27dd1d72 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1440237804 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 90.xbar_smoke_large_delays.1440237804 |
| Directory | /workspace/90.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/90.xbar_smoke_slow_rsp.802684108 |
| Short name | T1501 |
| Test name | |
| Test status | |
| Simulation time | 4231158961 ps |
| CPU time | 68.22 seconds |
| Started | Jun 23 07:39:57 PM PDT 24 |
| Finished | Jun 23 07:41:05 PM PDT 24 |
| Peak memory | 565516 kb |
| Host | smart-d8a4b4e3-f90d-40e3-a4bb-bffc8db11a97 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=802684108 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 90.xbar_smoke_slow_rsp.802684108 |
| Directory | /workspace/90.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/90.xbar_smoke_zero_delays.922569935 |
| Short name | T1910 |
| Test name | |
| Test status | |
| Simulation time | 43673683 ps |
| CPU time | 6.95 seconds |
| Started | Jun 23 07:39:57 PM PDT 24 |
| Finished | Jun 23 07:40:04 PM PDT 24 |
| Peak memory | 565552 kb |
| Host | smart-3043a419-9a05-4a25-b007-b90edafb9964 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=922569935 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 90.xbar_smoke_zero_delays .922569935 |
| Directory | /workspace/90.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/90.xbar_stress_all.3660709630 |
| Short name | T499 |
| Test name | |
| Test status | |
| Simulation time | 375693600 ps |
| CPU time | 40.17 seconds |
| Started | Jun 23 07:40:03 PM PDT 24 |
| Finished | Jun 23 07:40:43 PM PDT 24 |
| Peak memory | 574188 kb |
| Host | smart-ec08bc7f-ce69-48fe-9242-69dd38b4d25b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3660709630 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 90.xbar_stress_all.3660709630 |
| Directory | /workspace/90.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/90.xbar_stress_all_with_error.2806801078 |
| Short name | T1930 |
| Test name | |
| Test status | |
| Simulation time | 2166012564 ps |
| CPU time | 64.72 seconds |
| Started | Jun 23 07:40:02 PM PDT 24 |
| Finished | Jun 23 07:41:07 PM PDT 24 |
| Peak memory | 573732 kb |
| Host | smart-b8bf1258-ed62-4f72-9ac9-af02794232f8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2806801078 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 90.xbar_stress_all_with_error.2806801078 |
| Directory | /workspace/90.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/90.xbar_stress_all_with_rand_reset.708971277 |
| Short name | T2672 |
| Test name | |
| Test status | |
| Simulation time | 745176713 ps |
| CPU time | 270.49 seconds |
| Started | Jun 23 07:40:09 PM PDT 24 |
| Finished | Jun 23 07:44:40 PM PDT 24 |
| Peak memory | 576248 kb |
| Host | smart-38668d50-0a17-480d-a43e-26f1ebeab5ca |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=708971277 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_res et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 90.xbar_stress_all_ with_rand_reset.708971277 |
| Directory | /workspace/90.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/90.xbar_stress_all_with_reset_error.3068797231 |
| Short name | T2394 |
| Test name | |
| Test status | |
| Simulation time | 2639803562 ps |
| CPU time | 214.65 seconds |
| Started | Jun 23 07:40:09 PM PDT 24 |
| Finished | Jun 23 07:43:44 PM PDT 24 |
| Peak memory | 574376 kb |
| Host | smart-1bc997e2-95b5-4208-a011-bcf5d5aa23fa |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3068797231 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 90.xbar_stress_al l_with_reset_error.3068797231 |
| Directory | /workspace/90.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/90.xbar_unmapped_addr.1138284270 |
| Short name | T647 |
| Test name | |
| Test status | |
| Simulation time | 219327033 ps |
| CPU time | 26.04 seconds |
| Started | Jun 23 07:40:02 PM PDT 24 |
| Finished | Jun 23 07:40:28 PM PDT 24 |
| Peak memory | 574152 kb |
| Host | smart-01d5b69c-6654-495f-8265-edfa9c2ff25c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1138284270 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 90.xbar_unmapped_addr.1138284270 |
| Directory | /workspace/90.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/91.xbar_access_same_device.877708464 |
| Short name | T877 |
| Test name | |
| Test status | |
| Simulation time | 693575016 ps |
| CPU time | 57.21 seconds |
| Started | Jun 23 07:40:02 PM PDT 24 |
| Finished | Jun 23 07:41:00 PM PDT 24 |
| Peak memory | 574124 kb |
| Host | smart-36580fcc-f5b6-4566-a785-12bc9af01e83 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=877708464 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 91.xbar_access_same_device. 877708464 |
| Directory | /workspace/91.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/91.xbar_access_same_device_slow_rsp.3741960593 |
| Short name | T1914 |
| Test name | |
| Test status | |
| Simulation time | 10639477414 ps |
| CPU time | 171.74 seconds |
| Started | Jun 23 07:40:02 PM PDT 24 |
| Finished | Jun 23 07:42:54 PM PDT 24 |
| Peak memory | 565236 kb |
| Host | smart-7cdf78f9-11dd-4bce-aa5a-02173b4b587b |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3741960593 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 91.xbar_access_same_ device_slow_rsp.3741960593 |
| Directory | /workspace/91.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/91.xbar_error_and_unmapped_addr.3677636121 |
| Short name | T2732 |
| Test name | |
| Test status | |
| Simulation time | 820341340 ps |
| CPU time | 32.61 seconds |
| Started | Jun 23 07:40:02 PM PDT 24 |
| Finished | Jun 23 07:40:35 PM PDT 24 |
| Peak memory | 573384 kb |
| Host | smart-fc479790-1b82-499b-bf81-dd5e637767ad |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3677636121 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 91.xbar_error_and_unmapped_add r.3677636121 |
| Directory | /workspace/91.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/91.xbar_error_random.2380174682 |
| Short name | T1475 |
| Test name | |
| Test status | |
| Simulation time | 931692586 ps |
| CPU time | 32.93 seconds |
| Started | Jun 23 07:40:00 PM PDT 24 |
| Finished | Jun 23 07:40:33 PM PDT 24 |
| Peak memory | 573356 kb |
| Host | smart-9f458f47-1628-444a-ba41-0c46c5be9567 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2380174682 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 91.xbar_error_random.2380174682 |
| Directory | /workspace/91.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/91.xbar_random.1878656762 |
| Short name | T2398 |
| Test name | |
| Test status | |
| Simulation time | 2468638495 ps |
| CPU time | 93.4 seconds |
| Started | Jun 23 07:40:03 PM PDT 24 |
| Finished | Jun 23 07:41:36 PM PDT 24 |
| Peak memory | 574172 kb |
| Host | smart-78187e5e-fcf6-449c-8274-0baaee1f6178 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1878656762 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 91.xbar_random.1878656762 |
| Directory | /workspace/91.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/91.xbar_random_large_delays.217422087 |
| Short name | T490 |
| Test name | |
| Test status | |
| Simulation time | 34154240251 ps |
| CPU time | 361.37 seconds |
| Started | Jun 23 07:40:01 PM PDT 24 |
| Finished | Jun 23 07:46:03 PM PDT 24 |
| Peak memory | 573484 kb |
| Host | smart-f4c8f7ef-7f02-4b45-b35b-6ff60ff9446c |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=217422087 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 91.xbar_random_large_delays.217422087 |
| Directory | /workspace/91.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/91.xbar_random_slow_rsp.3421585570 |
| Short name | T1724 |
| Test name | |
| Test status | |
| Simulation time | 31428885612 ps |
| CPU time | 575.94 seconds |
| Started | Jun 23 07:40:01 PM PDT 24 |
| Finished | Jun 23 07:49:37 PM PDT 24 |
| Peak memory | 574168 kb |
| Host | smart-cf63d9b1-d0b5-4d62-9001-32c74eaad3e3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3421585570 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 91.xbar_random_slow_rsp.3421585570 |
| Directory | /workspace/91.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/91.xbar_random_zero_delays.3682251828 |
| Short name | T1926 |
| Test name | |
| Test status | |
| Simulation time | 38174596 ps |
| CPU time | 6.24 seconds |
| Started | Jun 23 07:41:03 PM PDT 24 |
| Finished | Jun 23 07:41:10 PM PDT 24 |
| Peak memory | 565552 kb |
| Host | smart-12654f23-79bd-4cfd-947a-9edef423544f |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3682251828 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 91.xbar_random_zero_del ays.3682251828 |
| Directory | /workspace/91.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/91.xbar_same_source.2399401997 |
| Short name | T2218 |
| Test name | |
| Test status | |
| Simulation time | 2675815200 ps |
| CPU time | 77.18 seconds |
| Started | Jun 23 07:39:59 PM PDT 24 |
| Finished | Jun 23 07:41:16 PM PDT 24 |
| Peak memory | 574128 kb |
| Host | smart-146b0043-428c-4536-9f0f-7cb46a94dbe4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2399401997 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 91.xbar_same_source.2399401997 |
| Directory | /workspace/91.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/91.xbar_smoke.1901780939 |
| Short name | T1989 |
| Test name | |
| Test status | |
| Simulation time | 198044443 ps |
| CPU time | 9.55 seconds |
| Started | Jun 23 07:40:00 PM PDT 24 |
| Finished | Jun 23 07:40:10 PM PDT 24 |
| Peak memory | 565188 kb |
| Host | smart-71e3f3be-41dc-4689-88db-91a4921783c5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1901780939 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 91.xbar_smoke.1901780939 |
| Directory | /workspace/91.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/91.xbar_smoke_large_delays.1780596220 |
| Short name | T1735 |
| Test name | |
| Test status | |
| Simulation time | 7405633261 ps |
| CPU time | 73.99 seconds |
| Started | Jun 23 07:40:07 PM PDT 24 |
| Finished | Jun 23 07:41:21 PM PDT 24 |
| Peak memory | 565908 kb |
| Host | smart-33968a1a-5d7b-42d7-aab7-3fd53c24bbcc |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1780596220 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 91.xbar_smoke_large_delays.1780596220 |
| Directory | /workspace/91.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/91.xbar_smoke_slow_rsp.1734725936 |
| Short name | T1391 |
| Test name | |
| Test status | |
| Simulation time | 4972075057 ps |
| CPU time | 85.23 seconds |
| Started | Jun 23 07:40:00 PM PDT 24 |
| Finished | Jun 23 07:41:26 PM PDT 24 |
| Peak memory | 565228 kb |
| Host | smart-afac856f-157f-46a3-8ec5-805cfdfdee0b |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1734725936 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 91.xbar_smoke_slow_rsp.1734725936 |
| Directory | /workspace/91.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/91.xbar_smoke_zero_delays.2263746276 |
| Short name | T2675 |
| Test name | |
| Test status | |
| Simulation time | 49318630 ps |
| CPU time | 6.65 seconds |
| Started | Jun 23 07:40:06 PM PDT 24 |
| Finished | Jun 23 07:40:13 PM PDT 24 |
| Peak memory | 565468 kb |
| Host | smart-2954415b-58f4-4564-98df-4fa82933d981 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2263746276 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 91.xbar_smoke_zero_delay s.2263746276 |
| Directory | /workspace/91.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/91.xbar_stress_all.3817696841 |
| Short name | T1419 |
| Test name | |
| Test status | |
| Simulation time | 6542777 ps |
| CPU time | 3.79 seconds |
| Started | Jun 23 07:40:07 PM PDT 24 |
| Finished | Jun 23 07:40:11 PM PDT 24 |
| Peak memory | 564960 kb |
| Host | smart-43a5780d-9c8b-443b-9f41-621a3bb70271 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3817696841 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 91.xbar_stress_all.3817696841 |
| Directory | /workspace/91.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/91.xbar_stress_all_with_error.504393469 |
| Short name | T2193 |
| Test name | |
| Test status | |
| Simulation time | 4903814284 ps |
| CPU time | 181.85 seconds |
| Started | Jun 23 07:40:02 PM PDT 24 |
| Finished | Jun 23 07:43:04 PM PDT 24 |
| Peak memory | 574356 kb |
| Host | smart-8873bcee-de01-4c77-9a86-dcfacabcc208 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=504393469 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 91.xbar_stress_all_with_error.504393469 |
| Directory | /workspace/91.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/91.xbar_stress_all_with_rand_reset.2555082427 |
| Short name | T2042 |
| Test name | |
| Test status | |
| Simulation time | 245564711 ps |
| CPU time | 88.37 seconds |
| Started | Jun 23 07:40:01 PM PDT 24 |
| Finished | Jun 23 07:41:30 PM PDT 24 |
| Peak memory | 576200 kb |
| Host | smart-1aa7e4ca-99a4-418f-8dcd-854932f15a7b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2555082427 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 91.xbar_stress_all _with_rand_reset.2555082427 |
| Directory | /workspace/91.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/91.xbar_stress_all_with_reset_error.3577592603 |
| Short name | T1573 |
| Test name | |
| Test status | |
| Simulation time | 1962225964 ps |
| CPU time | 235.2 seconds |
| Started | Jun 23 07:40:00 PM PDT 24 |
| Finished | Jun 23 07:43:56 PM PDT 24 |
| Peak memory | 574324 kb |
| Host | smart-3e680fa9-ac8c-4346-8153-cce1e78e0160 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3577592603 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 91.xbar_stress_al l_with_reset_error.3577592603 |
| Directory | /workspace/91.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/91.xbar_unmapped_addr.3572587888 |
| Short name | T2252 |
| Test name | |
| Test status | |
| Simulation time | 1086971980 ps |
| CPU time | 50 seconds |
| Started | Jun 23 07:40:02 PM PDT 24 |
| Finished | Jun 23 07:40:52 PM PDT 24 |
| Peak memory | 574136 kb |
| Host | smart-286ef412-e945-4d34-b184-a02e62f80896 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3572587888 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 91.xbar_unmapped_addr.3572587888 |
| Directory | /workspace/91.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/92.xbar_access_same_device.677755094 |
| Short name | T463 |
| Test name | |
| Test status | |
| Simulation time | 2233846646 ps |
| CPU time | 92.33 seconds |
| Started | Jun 23 07:40:10 PM PDT 24 |
| Finished | Jun 23 07:41:42 PM PDT 24 |
| Peak memory | 573420 kb |
| Host | smart-f9cf9da0-dbfd-44ba-8515-2de5dc06b0c4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=677755094 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 92.xbar_access_same_device. 677755094 |
| Directory | /workspace/92.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/92.xbar_access_same_device_slow_rsp.1680557623 |
| Short name | T2631 |
| Test name | |
| Test status | |
| Simulation time | 26200269173 ps |
| CPU time | 456.48 seconds |
| Started | Jun 23 07:40:09 PM PDT 24 |
| Finished | Jun 23 07:47:46 PM PDT 24 |
| Peak memory | 574200 kb |
| Host | smart-0f6614f3-d8d8-4701-b6e1-65561701b2d0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1680557623 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 92.xbar_access_same_ device_slow_rsp.1680557623 |
| Directory | /workspace/92.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/92.xbar_error_and_unmapped_addr.4032666512 |
| Short name | T2817 |
| Test name | |
| Test status | |
| Simulation time | 1296268794 ps |
| CPU time | 47.36 seconds |
| Started | Jun 23 07:40:05 PM PDT 24 |
| Finished | Jun 23 07:40:52 PM PDT 24 |
| Peak memory | 573732 kb |
| Host | smart-8d9ebe7b-c458-4601-921a-41486f5dc249 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4032666512 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 92.xbar_error_and_unmapped_add r.4032666512 |
| Directory | /workspace/92.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/92.xbar_error_random.967291537 |
| Short name | T1974 |
| Test name | |
| Test status | |
| Simulation time | 967760326 ps |
| CPU time | 37.03 seconds |
| Started | Jun 23 07:40:04 PM PDT 24 |
| Finished | Jun 23 07:40:42 PM PDT 24 |
| Peak memory | 573292 kb |
| Host | smart-7450d9a2-f610-45a0-b28c-5da26285dd57 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=967291537 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 92.xbar_error_random.967291537 |
| Directory | /workspace/92.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/92.xbar_random.2194795216 |
| Short name | T1948 |
| Test name | |
| Test status | |
| Simulation time | 989582194 ps |
| CPU time | 37.7 seconds |
| Started | Jun 23 07:40:00 PM PDT 24 |
| Finished | Jun 23 07:40:39 PM PDT 24 |
| Peak memory | 574120 kb |
| Host | smart-363583e0-f674-476e-bb31-b3a6fb617c30 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2194795216 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 92.xbar_random.2194795216 |
| Directory | /workspace/92.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/92.xbar_random_large_delays.632667245 |
| Short name | T1556 |
| Test name | |
| Test status | |
| Simulation time | 13330435151 ps |
| CPU time | 136.4 seconds |
| Started | Jun 23 07:40:00 PM PDT 24 |
| Finished | Jun 23 07:42:17 PM PDT 24 |
| Peak memory | 574192 kb |
| Host | smart-76cd1f4a-d5ce-45d4-b6f0-cf197c7d9b4b |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=632667245 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 92.xbar_random_large_delays.632667245 |
| Directory | /workspace/92.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/92.xbar_random_slow_rsp.1686125651 |
| Short name | T636 |
| Test name | |
| Test status | |
| Simulation time | 45912471787 ps |
| CPU time | 884.99 seconds |
| Started | Jun 23 07:40:08 PM PDT 24 |
| Finished | Jun 23 07:54:53 PM PDT 24 |
| Peak memory | 573504 kb |
| Host | smart-02e67353-573d-4d97-9915-a8cd9a3315ad |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1686125651 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 92.xbar_random_slow_rsp.1686125651 |
| Directory | /workspace/92.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/92.xbar_random_zero_delays.3357654664 |
| Short name | T2633 |
| Test name | |
| Test status | |
| Simulation time | 264412376 ps |
| CPU time | 24.79 seconds |
| Started | Jun 23 07:40:02 PM PDT 24 |
| Finished | Jun 23 07:40:28 PM PDT 24 |
| Peak memory | 574088 kb |
| Host | smart-cacf56d1-35aa-4ee7-828b-275d13bc918b |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3357654664 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 92.xbar_random_zero_del ays.3357654664 |
| Directory | /workspace/92.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/92.xbar_same_source.2189857589 |
| Short name | T433 |
| Test name | |
| Test status | |
| Simulation time | 377809342 ps |
| CPU time | 27.25 seconds |
| Started | Jun 23 07:40:08 PM PDT 24 |
| Finished | Jun 23 07:40:36 PM PDT 24 |
| Peak memory | 573436 kb |
| Host | smart-a0eaea69-677e-4f5c-ad58-65744e59460a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2189857589 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 92.xbar_same_source.2189857589 |
| Directory | /workspace/92.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/92.xbar_smoke.182591827 |
| Short name | T1917 |
| Test name | |
| Test status | |
| Simulation time | 49460998 ps |
| CPU time | 6.75 seconds |
| Started | Jun 23 07:40:06 PM PDT 24 |
| Finished | Jun 23 07:40:13 PM PDT 24 |
| Peak memory | 565152 kb |
| Host | smart-a6b26c13-c4ec-447d-93ee-683e25b61c97 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=182591827 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 92.xbar_smoke.182591827 |
| Directory | /workspace/92.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/92.xbar_smoke_large_delays.1093729790 |
| Short name | T2782 |
| Test name | |
| Test status | |
| Simulation time | 9304917800 ps |
| CPU time | 94.11 seconds |
| Started | Jun 23 07:40:01 PM PDT 24 |
| Finished | Jun 23 07:41:35 PM PDT 24 |
| Peak memory | 565924 kb |
| Host | smart-56f7cd27-c4a5-407a-b98d-d83357976b15 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1093729790 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 92.xbar_smoke_large_delays.1093729790 |
| Directory | /workspace/92.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/92.xbar_smoke_slow_rsp.715872655 |
| Short name | T1797 |
| Test name | |
| Test status | |
| Simulation time | 4926645891 ps |
| CPU time | 85.67 seconds |
| Started | Jun 23 07:40:02 PM PDT 24 |
| Finished | Jun 23 07:41:29 PM PDT 24 |
| Peak memory | 565264 kb |
| Host | smart-60811a20-670d-460c-be42-214c4d82e27e |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=715872655 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 92.xbar_smoke_slow_rsp.715872655 |
| Directory | /workspace/92.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/92.xbar_smoke_zero_delays.81480904 |
| Short name | T1388 |
| Test name | |
| Test status | |
| Simulation time | 57006786 ps |
| CPU time | 7.1 seconds |
| Started | Jun 23 07:40:07 PM PDT 24 |
| Finished | Jun 23 07:40:15 PM PDT 24 |
| Peak memory | 573732 kb |
| Host | smart-98d055d9-440c-42d2-be24-6d1416940f42 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81480904 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 92.xbar_smoke_zero_delays.81480904 |
| Directory | /workspace/92.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/92.xbar_stress_all.1468202615 |
| Short name | T488 |
| Test name | |
| Test status | |
| Simulation time | 3061996720 ps |
| CPU time | 288.87 seconds |
| Started | Jun 23 07:40:03 PM PDT 24 |
| Finished | Jun 23 07:44:53 PM PDT 24 |
| Peak memory | 573604 kb |
| Host | smart-1b185a60-5860-4bea-b043-3192297c2dd0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1468202615 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 92.xbar_stress_all.1468202615 |
| Directory | /workspace/92.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/92.xbar_stress_all_with_error.1930361159 |
| Short name | T1961 |
| Test name | |
| Test status | |
| Simulation time | 12373461117 ps |
| CPU time | 478.75 seconds |
| Started | Jun 23 07:40:08 PM PDT 24 |
| Finished | Jun 23 07:48:08 PM PDT 24 |
| Peak memory | 574320 kb |
| Host | smart-744d53f3-f845-42d3-af35-2df410f48ecb |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1930361159 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 92.xbar_stress_all_with_error.1930361159 |
| Directory | /workspace/92.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/92.xbar_stress_all_with_rand_reset.1839541269 |
| Short name | T908 |
| Test name | |
| Test status | |
| Simulation time | 535949314 ps |
| CPU time | 214.14 seconds |
| Started | Jun 23 07:40:05 PM PDT 24 |
| Finished | Jun 23 07:43:40 PM PDT 24 |
| Peak memory | 574224 kb |
| Host | smart-8625f51f-fdfe-4286-a7f6-d9a08dcfbb02 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1839541269 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 92.xbar_stress_all _with_rand_reset.1839541269 |
| Directory | /workspace/92.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/92.xbar_stress_all_with_reset_error.3727650658 |
| Short name | T2210 |
| Test name | |
| Test status | |
| Simulation time | 1030760261 ps |
| CPU time | 118.25 seconds |
| Started | Jun 23 07:40:07 PM PDT 24 |
| Finished | Jun 23 07:42:06 PM PDT 24 |
| Peak memory | 576328 kb |
| Host | smart-43267178-3a33-4e7f-be57-12caac264c42 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3727650658 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 92.xbar_stress_al l_with_reset_error.3727650658 |
| Directory | /workspace/92.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/92.xbar_unmapped_addr.2246489641 |
| Short name | T2368 |
| Test name | |
| Test status | |
| Simulation time | 677475488 ps |
| CPU time | 30.14 seconds |
| Started | Jun 23 07:40:09 PM PDT 24 |
| Finished | Jun 23 07:40:39 PM PDT 24 |
| Peak memory | 574128 kb |
| Host | smart-7ccce05b-d090-4e11-9d0e-618fb4dda171 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2246489641 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 92.xbar_unmapped_addr.2246489641 |
| Directory | /workspace/92.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/93.xbar_access_same_device.1920857133 |
| Short name | T866 |
| Test name | |
| Test status | |
| Simulation time | 1689582785 ps |
| CPU time | 76.42 seconds |
| Started | Jun 23 07:40:10 PM PDT 24 |
| Finished | Jun 23 07:41:27 PM PDT 24 |
| Peak memory | 574132 kb |
| Host | smart-c911e846-2c47-4a92-8e47-3743e218ad70 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1920857133 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 93.xbar_access_same_device .1920857133 |
| Directory | /workspace/93.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/93.xbar_access_same_device_slow_rsp.3742336958 |
| Short name | T2029 |
| Test name | |
| Test status | |
| Simulation time | 9721306759 ps |
| CPU time | 161.02 seconds |
| Started | Jun 23 07:40:12 PM PDT 24 |
| Finished | Jun 23 07:42:53 PM PDT 24 |
| Peak memory | 565944 kb |
| Host | smart-5ccc7de4-48b7-4841-a751-28c1621bd497 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3742336958 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 93.xbar_access_same_ device_slow_rsp.3742336958 |
| Directory | /workspace/93.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/93.xbar_error_and_unmapped_addr.3944330822 |
| Short name | T1691 |
| Test name | |
| Test status | |
| Simulation time | 554048375 ps |
| CPU time | 23.58 seconds |
| Started | Jun 23 07:40:13 PM PDT 24 |
| Finished | Jun 23 07:40:36 PM PDT 24 |
| Peak memory | 573388 kb |
| Host | smart-0a015303-811e-4cee-bae4-bde7f16f4cb6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3944330822 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 93.xbar_error_and_unmapped_add r.3944330822 |
| Directory | /workspace/93.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/93.xbar_error_random.1482996332 |
| Short name | T1602 |
| Test name | |
| Test status | |
| Simulation time | 2341600529 ps |
| CPU time | 73.81 seconds |
| Started | Jun 23 07:40:15 PM PDT 24 |
| Finished | Jun 23 07:41:29 PM PDT 24 |
| Peak memory | 573804 kb |
| Host | smart-7f9fd3c7-11a9-4cad-9bdf-42ba0f9e4a57 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1482996332 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 93.xbar_error_random.1482996332 |
| Directory | /workspace/93.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/93.xbar_random.26066756 |
| Short name | T659 |
| Test name | |
| Test status | |
| Simulation time | 1439075113 ps |
| CPU time | 46.53 seconds |
| Started | Jun 23 07:40:08 PM PDT 24 |
| Finished | Jun 23 07:40:55 PM PDT 24 |
| Peak memory | 574112 kb |
| Host | smart-ebe49a22-fec8-494e-a4fd-e4efb93bb142 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26066756 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 93.xbar_random.26066756 |
| Directory | /workspace/93.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/93.xbar_random_large_delays.89842284 |
| Short name | T2507 |
| Test name | |
| Test status | |
| Simulation time | 86915933171 ps |
| CPU time | 887.05 seconds |
| Started | Jun 23 07:40:11 PM PDT 24 |
| Finished | Jun 23 07:54:59 PM PDT 24 |
| Peak memory | 573528 kb |
| Host | smart-517acf7c-0df2-4471-8805-8188f4f7f4c6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89842284 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 93.xbar_random_large_delays.89842284 |
| Directory | /workspace/93.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/93.xbar_random_slow_rsp.1032369501 |
| Short name | T2743 |
| Test name | |
| Test status | |
| Simulation time | 44575930094 ps |
| CPU time | 782.42 seconds |
| Started | Jun 23 07:40:09 PM PDT 24 |
| Finished | Jun 23 07:53:12 PM PDT 24 |
| Peak memory | 573488 kb |
| Host | smart-ae467a43-a767-4e60-9e15-9b3e6b98411f |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1032369501 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 93.xbar_random_slow_rsp.1032369501 |
| Directory | /workspace/93.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/93.xbar_random_zero_delays.2201666889 |
| Short name | T2521 |
| Test name | |
| Test status | |
| Simulation time | 276431492 ps |
| CPU time | 26.68 seconds |
| Started | Jun 23 07:40:09 PM PDT 24 |
| Finished | Jun 23 07:40:36 PM PDT 24 |
| Peak memory | 574088 kb |
| Host | smart-6502ffc9-4a67-4d68-bb69-41bbefa205fa |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2201666889 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 93.xbar_random_zero_del ays.2201666889 |
| Directory | /workspace/93.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/93.xbar_same_source.2751823862 |
| Short name | T2321 |
| Test name | |
| Test status | |
| Simulation time | 1210053004 ps |
| CPU time | 35.66 seconds |
| Started | Jun 23 07:40:12 PM PDT 24 |
| Finished | Jun 23 07:40:48 PM PDT 24 |
| Peak memory | 573900 kb |
| Host | smart-275a692f-2b82-41ef-a5ce-b85e4adb25b2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2751823862 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 93.xbar_same_source.2751823862 |
| Directory | /workspace/93.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/93.xbar_smoke.3782493125 |
| Short name | T2856 |
| Test name | |
| Test status | |
| Simulation time | 184759395 ps |
| CPU time | 8.79 seconds |
| Started | Jun 23 07:40:05 PM PDT 24 |
| Finished | Jun 23 07:40:14 PM PDT 24 |
| Peak memory | 565488 kb |
| Host | smart-d6315a88-d806-44ac-8c3a-e75d2f80db13 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3782493125 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 93.xbar_smoke.3782493125 |
| Directory | /workspace/93.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/93.xbar_smoke_large_delays.4241063745 |
| Short name | T1966 |
| Test name | |
| Test status | |
| Simulation time | 8782097411 ps |
| CPU time | 89.11 seconds |
| Started | Jun 23 07:40:09 PM PDT 24 |
| Finished | Jun 23 07:41:38 PM PDT 24 |
| Peak memory | 565232 kb |
| Host | smart-9be2f523-e89c-424a-afb2-627dedd5b482 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4241063745 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 93.xbar_smoke_large_delays.4241063745 |
| Directory | /workspace/93.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/93.xbar_smoke_slow_rsp.476610836 |
| Short name | T1912 |
| Test name | |
| Test status | |
| Simulation time | 6441150767 ps |
| CPU time | 107.43 seconds |
| Started | Jun 23 07:40:09 PM PDT 24 |
| Finished | Jun 23 07:41:57 PM PDT 24 |
| Peak memory | 565200 kb |
| Host | smart-011a682b-c646-4a84-b5c6-864be1d229ca |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=476610836 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 93.xbar_smoke_slow_rsp.476610836 |
| Directory | /workspace/93.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/93.xbar_smoke_zero_delays.214256288 |
| Short name | T2482 |
| Test name | |
| Test status | |
| Simulation time | 52970552 ps |
| CPU time | 6.48 seconds |
| Started | Jun 23 07:40:09 PM PDT 24 |
| Finished | Jun 23 07:40:16 PM PDT 24 |
| Peak memory | 565176 kb |
| Host | smart-a96766a7-4d97-4ffc-b9ce-55fbf36dae65 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=214256288 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 93.xbar_smoke_zero_delays .214256288 |
| Directory | /workspace/93.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/93.xbar_stress_all.2232589956 |
| Short name | T678 |
| Test name | |
| Test status | |
| Simulation time | 2642983746 ps |
| CPU time | 252.05 seconds |
| Started | Jun 23 07:40:13 PM PDT 24 |
| Finished | Jun 23 07:44:25 PM PDT 24 |
| Peak memory | 574300 kb |
| Host | smart-0416116a-3671-453c-b143-50b35b9bd812 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2232589956 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 93.xbar_stress_all.2232589956 |
| Directory | /workspace/93.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/93.xbar_stress_all_with_error.1074758345 |
| Short name | T2068 |
| Test name | |
| Test status | |
| Simulation time | 22397836345 ps |
| CPU time | 1020.48 seconds |
| Started | Jun 23 07:40:14 PM PDT 24 |
| Finished | Jun 23 07:57:15 PM PDT 24 |
| Peak memory | 574352 kb |
| Host | smart-37830229-d353-4adb-8498-6ea417813c88 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1074758345 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 93.xbar_stress_all_with_error.1074758345 |
| Directory | /workspace/93.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/93.xbar_stress_all_with_rand_reset.385708723 |
| Short name | T2770 |
| Test name | |
| Test status | |
| Simulation time | 337110911 ps |
| CPU time | 122.35 seconds |
| Started | Jun 23 07:40:14 PM PDT 24 |
| Finished | Jun 23 07:42:17 PM PDT 24 |
| Peak memory | 576296 kb |
| Host | smart-f72749a5-4741-427c-8458-e05331c32fb2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=385708723 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_res et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 93.xbar_stress_all_ with_rand_reset.385708723 |
| Directory | /workspace/93.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/93.xbar_stress_all_with_reset_error.4212708908 |
| Short name | T1656 |
| Test name | |
| Test status | |
| Simulation time | 7859738647 ps |
| CPU time | 409.04 seconds |
| Started | Jun 23 07:40:15 PM PDT 24 |
| Finished | Jun 23 07:47:04 PM PDT 24 |
| Peak memory | 576400 kb |
| Host | smart-1690e70b-f6fb-4ee0-b032-9bc0266cf285 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4212708908 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 93.xbar_stress_al l_with_reset_error.4212708908 |
| Directory | /workspace/93.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/93.xbar_unmapped_addr.1835583163 |
| Short name | T2791 |
| Test name | |
| Test status | |
| Simulation time | 185041878 ps |
| CPU time | 20.67 seconds |
| Started | Jun 23 07:40:13 PM PDT 24 |
| Finished | Jun 23 07:40:34 PM PDT 24 |
| Peak memory | 574120 kb |
| Host | smart-e5d5b367-cbba-44e4-9b68-5fea85e6c455 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1835583163 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 93.xbar_unmapped_addr.1835583163 |
| Directory | /workspace/93.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/94.xbar_access_same_device.3931406145 |
| Short name | T2395 |
| Test name | |
| Test status | |
| Simulation time | 768624264 ps |
| CPU time | 59.69 seconds |
| Started | Jun 23 07:40:43 PM PDT 24 |
| Finished | Jun 23 07:41:44 PM PDT 24 |
| Peak memory | 574112 kb |
| Host | smart-1fa94738-b3b6-4db9-af99-934095393ebc |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3931406145 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 94.xbar_access_same_device .3931406145 |
| Directory | /workspace/94.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/94.xbar_access_same_device_slow_rsp.1159076876 |
| Short name | T2003 |
| Test name | |
| Test status | |
| Simulation time | 10769634127 ps |
| CPU time | 183.06 seconds |
| Started | Jun 23 07:40:40 PM PDT 24 |
| Finished | Jun 23 07:43:44 PM PDT 24 |
| Peak memory | 565988 kb |
| Host | smart-1743fbba-346d-4705-bf4e-c425e312e8db |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1159076876 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 94.xbar_access_same_ device_slow_rsp.1159076876 |
| Directory | /workspace/94.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/94.xbar_error_and_unmapped_addr.3280064225 |
| Short name | T1595 |
| Test name | |
| Test status | |
| Simulation time | 596215384 ps |
| CPU time | 28 seconds |
| Started | Jun 23 07:40:43 PM PDT 24 |
| Finished | Jun 23 07:41:12 PM PDT 24 |
| Peak memory | 573744 kb |
| Host | smart-4ec53996-c6ec-4f63-a954-27270963440e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3280064225 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 94.xbar_error_and_unmapped_add r.3280064225 |
| Directory | /workspace/94.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/94.xbar_error_random.266373259 |
| Short name | T1936 |
| Test name | |
| Test status | |
| Simulation time | 70333649 ps |
| CPU time | 8.11 seconds |
| Started | Jun 23 07:40:41 PM PDT 24 |
| Finished | Jun 23 07:40:50 PM PDT 24 |
| Peak memory | 573648 kb |
| Host | smart-3a3f3b13-4cf7-4c5b-8854-e9f4f7fc1c6d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=266373259 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 94.xbar_error_random.266373259 |
| Directory | /workspace/94.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/94.xbar_random.378526615 |
| Short name | T2832 |
| Test name | |
| Test status | |
| Simulation time | 316525158 ps |
| CPU time | 29.23 seconds |
| Started | Jun 23 07:40:43 PM PDT 24 |
| Finished | Jun 23 07:41:13 PM PDT 24 |
| Peak memory | 574128 kb |
| Host | smart-9c560807-f622-4056-8fee-c2fdc4b3743a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=378526615 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 94.xbar_random.378526615 |
| Directory | /workspace/94.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/94.xbar_random_large_delays.1046937989 |
| Short name | T2280 |
| Test name | |
| Test status | |
| Simulation time | 93568142087 ps |
| CPU time | 1057.92 seconds |
| Started | Jun 23 07:40:42 PM PDT 24 |
| Finished | Jun 23 07:58:21 PM PDT 24 |
| Peak memory | 574180 kb |
| Host | smart-d5a5cb80-717a-409f-8315-bb746469a041 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1046937989 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 94.xbar_random_large_delays.1046937989 |
| Directory | /workspace/94.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/94.xbar_random_slow_rsp.2534864288 |
| Short name | T1901 |
| Test name | |
| Test status | |
| Simulation time | 44198092491 ps |
| CPU time | 779.92 seconds |
| Started | Jun 23 07:40:43 PM PDT 24 |
| Finished | Jun 23 07:53:44 PM PDT 24 |
| Peak memory | 573532 kb |
| Host | smart-ad95429d-4486-4b06-aa1d-38a27dbfed37 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2534864288 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 94.xbar_random_slow_rsp.2534864288 |
| Directory | /workspace/94.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/94.xbar_random_zero_delays.3785690720 |
| Short name | T2190 |
| Test name | |
| Test status | |
| Simulation time | 408423798 ps |
| CPU time | 36.02 seconds |
| Started | Jun 23 07:40:40 PM PDT 24 |
| Finished | Jun 23 07:41:16 PM PDT 24 |
| Peak memory | 574076 kb |
| Host | smart-be3f8443-3ae5-4b80-8e5b-f6a0873be7ca |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3785690720 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 94.xbar_random_zero_del ays.3785690720 |
| Directory | /workspace/94.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/94.xbar_same_source.3754490777 |
| Short name | T2181 |
| Test name | |
| Test status | |
| Simulation time | 2258026609 ps |
| CPU time | 66.98 seconds |
| Started | Jun 23 07:40:42 PM PDT 24 |
| Finished | Jun 23 07:41:50 PM PDT 24 |
| Peak memory | 574140 kb |
| Host | smart-bda5f5c2-ae57-4f30-a03b-0f15fd0b5fe2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3754490777 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 94.xbar_same_source.3754490777 |
| Directory | /workspace/94.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/94.xbar_smoke.1639157222 |
| Short name | T621 |
| Test name | |
| Test status | |
| Simulation time | 165039705 ps |
| CPU time | 8.07 seconds |
| Started | Jun 23 07:40:14 PM PDT 24 |
| Finished | Jun 23 07:40:22 PM PDT 24 |
| Peak memory | 565868 kb |
| Host | smart-96506b6d-f6b6-47cf-8745-30f38f509823 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1639157222 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 94.xbar_smoke.1639157222 |
| Directory | /workspace/94.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/94.xbar_smoke_large_delays.419621830 |
| Short name | T2472 |
| Test name | |
| Test status | |
| Simulation time | 5287698071 ps |
| CPU time | 56.71 seconds |
| Started | Jun 23 07:40:43 PM PDT 24 |
| Finished | Jun 23 07:41:40 PM PDT 24 |
| Peak memory | 565552 kb |
| Host | smart-4be209b2-1c74-4b63-ba0d-c62dffcd0479 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=419621830 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 94.xbar_smoke_large_delays.419621830 |
| Directory | /workspace/94.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/94.xbar_smoke_slow_rsp.3907245157 |
| Short name | T2452 |
| Test name | |
| Test status | |
| Simulation time | 4924036587 ps |
| CPU time | 87.41 seconds |
| Started | Jun 23 07:40:42 PM PDT 24 |
| Finished | Jun 23 07:42:10 PM PDT 24 |
| Peak memory | 565520 kb |
| Host | smart-35574042-1030-48d8-9479-6a2dfc32531c |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3907245157 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 94.xbar_smoke_slow_rsp.3907245157 |
| Directory | /workspace/94.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/94.xbar_smoke_zero_delays.1997415287 |
| Short name | T1503 |
| Test name | |
| Test status | |
| Simulation time | 61037331 ps |
| CPU time | 7.19 seconds |
| Started | Jun 23 07:40:42 PM PDT 24 |
| Finished | Jun 23 07:40:50 PM PDT 24 |
| Peak memory | 565200 kb |
| Host | smart-04506076-5c9d-4768-9d0e-c61d8279342a |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1997415287 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 94.xbar_smoke_zero_delay s.1997415287 |
| Directory | /workspace/94.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/94.xbar_stress_all.3786735936 |
| Short name | T1868 |
| Test name | |
| Test status | |
| Simulation time | 9671135132 ps |
| CPU time | 352.89 seconds |
| Started | Jun 23 07:40:52 PM PDT 24 |
| Finished | Jun 23 07:46:46 PM PDT 24 |
| Peak memory | 574304 kb |
| Host | smart-cce868b1-876a-45e0-bd2b-277d3a3a1b13 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3786735936 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 94.xbar_stress_all.3786735936 |
| Directory | /workspace/94.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/94.xbar_stress_all_with_error.1060731618 |
| Short name | T670 |
| Test name | |
| Test status | |
| Simulation time | 7397265031 ps |
| CPU time | 264.06 seconds |
| Started | Jun 23 07:40:52 PM PDT 24 |
| Finished | Jun 23 07:45:17 PM PDT 24 |
| Peak memory | 574248 kb |
| Host | smart-71c513c3-c58c-4a19-9fc3-80862e843d83 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1060731618 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 94.xbar_stress_all_with_error.1060731618 |
| Directory | /workspace/94.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/94.xbar_stress_all_with_rand_reset.3548028867 |
| Short name | T2305 |
| Test name | |
| Test status | |
| Simulation time | 6443943478 ps |
| CPU time | 858.49 seconds |
| Started | Jun 23 07:40:49 PM PDT 24 |
| Finished | Jun 23 07:55:08 PM PDT 24 |
| Peak memory | 574312 kb |
| Host | smart-f8ef3c2b-98ff-414f-8318-8f6665e299bb |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3548028867 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 94.xbar_stress_all _with_rand_reset.3548028867 |
| Directory | /workspace/94.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/94.xbar_stress_all_with_reset_error.303157446 |
| Short name | T2300 |
| Test name | |
| Test status | |
| Simulation time | 262181608 ps |
| CPU time | 35.22 seconds |
| Started | Jun 23 07:40:47 PM PDT 24 |
| Finished | Jun 23 07:41:22 PM PDT 24 |
| Peak memory | 576308 kb |
| Host | smart-f512efa4-f583-4c2c-8771-be5b1048c87b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=303157446 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 94.xbar_stress_all _with_reset_error.303157446 |
| Directory | /workspace/94.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/94.xbar_unmapped_addr.3400537328 |
| Short name | T480 |
| Test name | |
| Test status | |
| Simulation time | 777847365 ps |
| CPU time | 33.1 seconds |
| Started | Jun 23 07:40:42 PM PDT 24 |
| Finished | Jun 23 07:41:16 PM PDT 24 |
| Peak memory | 574128 kb |
| Host | smart-78ac4918-127c-4709-9ee5-3f33f255c4b4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3400537328 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 94.xbar_unmapped_addr.3400537328 |
| Directory | /workspace/94.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/95.xbar_access_same_device.663442630 |
| Short name | T2755 |
| Test name | |
| Test status | |
| Simulation time | 740333569 ps |
| CPU time | 33.83 seconds |
| Started | Jun 23 07:40:51 PM PDT 24 |
| Finished | Jun 23 07:41:26 PM PDT 24 |
| Peak memory | 574120 kb |
| Host | smart-18148be8-a731-48f2-9d13-15503db919bd |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=663442630 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 95.xbar_access_same_device. 663442630 |
| Directory | /workspace/95.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/95.xbar_access_same_device_slow_rsp.1035187966 |
| Short name | T469 |
| Test name | |
| Test status | |
| Simulation time | 126149150774 ps |
| CPU time | 2246.78 seconds |
| Started | Jun 23 07:40:53 PM PDT 24 |
| Finished | Jun 23 08:18:21 PM PDT 24 |
| Peak memory | 574192 kb |
| Host | smart-b77b5bb0-a37c-47a4-9159-2b8bd3123d76 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1035187966 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 95.xbar_access_same_ device_slow_rsp.1035187966 |
| Directory | /workspace/95.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/95.xbar_error_and_unmapped_addr.3543826771 |
| Short name | T2361 |
| Test name | |
| Test status | |
| Simulation time | 1027605628 ps |
| CPU time | 39.53 seconds |
| Started | Jun 23 07:40:50 PM PDT 24 |
| Finished | Jun 23 07:41:29 PM PDT 24 |
| Peak memory | 573772 kb |
| Host | smart-ad3ed9cc-5583-4552-960b-e688165b783d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3543826771 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 95.xbar_error_and_unmapped_add r.3543826771 |
| Directory | /workspace/95.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/95.xbar_error_random.1727243954 |
| Short name | T1490 |
| Test name | |
| Test status | |
| Simulation time | 368519975 ps |
| CPU time | 15.88 seconds |
| Started | Jun 23 07:40:52 PM PDT 24 |
| Finished | Jun 23 07:41:09 PM PDT 24 |
| Peak memory | 573604 kb |
| Host | smart-37af69e7-73bd-41cf-bc31-d913debb8943 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1727243954 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 95.xbar_error_random.1727243954 |
| Directory | /workspace/95.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/95.xbar_random.2165806970 |
| Short name | T2851 |
| Test name | |
| Test status | |
| Simulation time | 543131653 ps |
| CPU time | 46.31 seconds |
| Started | Jun 23 07:40:51 PM PDT 24 |
| Finished | Jun 23 07:41:38 PM PDT 24 |
| Peak memory | 574156 kb |
| Host | smart-14ce93fb-93e5-4cc5-b6af-e3d431b09ac2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2165806970 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 95.xbar_random.2165806970 |
| Directory | /workspace/95.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/95.xbar_random_large_delays.4244534118 |
| Short name | T2056 |
| Test name | |
| Test status | |
| Simulation time | 10445983383 ps |
| CPU time | 111.94 seconds |
| Started | Jun 23 07:40:51 PM PDT 24 |
| Finished | Jun 23 07:42:44 PM PDT 24 |
| Peak memory | 565872 kb |
| Host | smart-b1387240-2af8-4d48-aff9-cda79ed6ef64 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4244534118 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 95.xbar_random_large_delays.4244534118 |
| Directory | /workspace/95.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/95.xbar_random_slow_rsp.1174569843 |
| Short name | T2543 |
| Test name | |
| Test status | |
| Simulation time | 31380440920 ps |
| CPU time | 543.58 seconds |
| Started | Jun 23 07:40:57 PM PDT 24 |
| Finished | Jun 23 07:50:01 PM PDT 24 |
| Peak memory | 573548 kb |
| Host | smart-f4d1e203-5d5b-4d0a-929f-422a6caf9bbe |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1174569843 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 95.xbar_random_slow_rsp.1174569843 |
| Directory | /workspace/95.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/95.xbar_random_zero_delays.2632044623 |
| Short name | T2746 |
| Test name | |
| Test status | |
| Simulation time | 239200561 ps |
| CPU time | 23.84 seconds |
| Started | Jun 23 07:40:50 PM PDT 24 |
| Finished | Jun 23 07:41:14 PM PDT 24 |
| Peak memory | 574092 kb |
| Host | smart-345a2979-d3fd-4c53-9cd1-6fe7d231dd9a |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2632044623 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 95.xbar_random_zero_del ays.2632044623 |
| Directory | /workspace/95.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/95.xbar_same_source.1516272693 |
| Short name | T2424 |
| Test name | |
| Test status | |
| Simulation time | 580029993 ps |
| CPU time | 45.45 seconds |
| Started | Jun 23 07:40:58 PM PDT 24 |
| Finished | Jun 23 07:41:44 PM PDT 24 |
| Peak memory | 574088 kb |
| Host | smart-7557f0c9-a3e6-48f0-b200-4fc1f77a8510 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1516272693 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 95.xbar_same_source.1516272693 |
| Directory | /workspace/95.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/95.xbar_smoke.2119762690 |
| Short name | T2413 |
| Test name | |
| Test status | |
| Simulation time | 198141302 ps |
| CPU time | 8.65 seconds |
| Started | Jun 23 07:40:54 PM PDT 24 |
| Finished | Jun 23 07:41:03 PM PDT 24 |
| Peak memory | 565724 kb |
| Host | smart-72c48057-f07c-4bbb-a7e1-6d664ed764c4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2119762690 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 95.xbar_smoke.2119762690 |
| Directory | /workspace/95.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/95.xbar_smoke_large_delays.2271310049 |
| Short name | T1681 |
| Test name | |
| Test status | |
| Simulation time | 6394967909 ps |
| CPU time | 66.53 seconds |
| Started | Jun 23 07:40:48 PM PDT 24 |
| Finished | Jun 23 07:41:55 PM PDT 24 |
| Peak memory | 565908 kb |
| Host | smart-5ac23c89-e42e-4d15-b559-7e8e05e5430e |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2271310049 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 95.xbar_smoke_large_delays.2271310049 |
| Directory | /workspace/95.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/95.xbar_smoke_slow_rsp.472398921 |
| Short name | T2542 |
| Test name | |
| Test status | |
| Simulation time | 3279367677 ps |
| CPU time | 55.91 seconds |
| Started | Jun 23 07:40:48 PM PDT 24 |
| Finished | Jun 23 07:41:44 PM PDT 24 |
| Peak memory | 565260 kb |
| Host | smart-07cbe8a7-dbe3-4555-9076-5a9b70203cc1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=472398921 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 95.xbar_smoke_slow_rsp.472398921 |
| Directory | /workspace/95.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/95.xbar_smoke_zero_delays.1722319750 |
| Short name | T1426 |
| Test name | |
| Test status | |
| Simulation time | 48821158 ps |
| CPU time | 5.97 seconds |
| Started | Jun 23 07:40:49 PM PDT 24 |
| Finished | Jun 23 07:40:55 PM PDT 24 |
| Peak memory | 565668 kb |
| Host | smart-68ac4c13-9140-484a-bd02-bd6a22a5ef6a |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1722319750 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 95.xbar_smoke_zero_delay s.1722319750 |
| Directory | /workspace/95.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/95.xbar_stress_all.1847153429 |
| Short name | T438 |
| Test name | |
| Test status | |
| Simulation time | 3828754188 ps |
| CPU time | 299.65 seconds |
| Started | Jun 23 07:40:52 PM PDT 24 |
| Finished | Jun 23 07:45:52 PM PDT 24 |
| Peak memory | 574272 kb |
| Host | smart-43c498fa-a168-474f-9217-cadd8df45e38 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1847153429 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 95.xbar_stress_all.1847153429 |
| Directory | /workspace/95.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/95.xbar_stress_all_with_rand_reset.813394753 |
| Short name | T1840 |
| Test name | |
| Test status | |
| Simulation time | 3748290552 ps |
| CPU time | 375 seconds |
| Started | Jun 23 07:40:52 PM PDT 24 |
| Finished | Jun 23 07:47:08 PM PDT 24 |
| Peak memory | 577384 kb |
| Host | smart-612c50b7-2971-4051-b0ab-21bfcb93788a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=813394753 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_res et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 95.xbar_stress_all_ with_rand_reset.813394753 |
| Directory | /workspace/95.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/95.xbar_stress_all_with_reset_error.3011550014 |
| Short name | T2690 |
| Test name | |
| Test status | |
| Simulation time | 3635148487 ps |
| CPU time | 391.85 seconds |
| Started | Jun 23 07:40:49 PM PDT 24 |
| Finished | Jun 23 07:47:21 PM PDT 24 |
| Peak memory | 574300 kb |
| Host | smart-4c5c0c65-ebaa-40df-90d1-2b53619ae112 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3011550014 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 95.xbar_stress_al l_with_reset_error.3011550014 |
| Directory | /workspace/95.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/95.xbar_unmapped_addr.3156682135 |
| Short name | T2216 |
| Test name | |
| Test status | |
| Simulation time | 345809758 ps |
| CPU time | 17.38 seconds |
| Started | Jun 23 07:40:49 PM PDT 24 |
| Finished | Jun 23 07:41:06 PM PDT 24 |
| Peak memory | 574132 kb |
| Host | smart-1656553c-8b29-49b5-9658-4a0bd3ac0d48 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3156682135 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 95.xbar_unmapped_addr.3156682135 |
| Directory | /workspace/95.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/96.xbar_access_same_device.2354972912 |
| Short name | T1517 |
| Test name | |
| Test status | |
| Simulation time | 86714797 ps |
| CPU time | 8.22 seconds |
| Started | Jun 23 07:40:48 PM PDT 24 |
| Finished | Jun 23 07:40:56 PM PDT 24 |
| Peak memory | 565160 kb |
| Host | smart-b3b314c7-3997-46a4-bf87-85c6515a274a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2354972912 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 96.xbar_access_same_device .2354972912 |
| Directory | /workspace/96.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/96.xbar_error_and_unmapped_addr.3677914152 |
| Short name | T1848 |
| Test name | |
| Test status | |
| Simulation time | 792549901 ps |
| CPU time | 33.4 seconds |
| Started | Jun 23 07:40:57 PM PDT 24 |
| Finished | Jun 23 07:41:31 PM PDT 24 |
| Peak memory | 573248 kb |
| Host | smart-7f43f6b2-01e8-4f84-b2a2-b8571a2a6a15 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3677914152 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 96.xbar_error_and_unmapped_add r.3677914152 |
| Directory | /workspace/96.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/96.xbar_error_random.813816835 |
| Short name | T2192 |
| Test name | |
| Test status | |
| Simulation time | 595297384 ps |
| CPU time | 53.35 seconds |
| Started | Jun 23 07:40:58 PM PDT 24 |
| Finished | Jun 23 07:41:52 PM PDT 24 |
| Peak memory | 573708 kb |
| Host | smart-334e6684-66fd-47bf-bfa9-0c1c3f7df39a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=813816835 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 96.xbar_error_random.813816835 |
| Directory | /workspace/96.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/96.xbar_random.3619122854 |
| Short name | T2665 |
| Test name | |
| Test status | |
| Simulation time | 398369405 ps |
| CPU time | 16.22 seconds |
| Started | Jun 23 07:40:52 PM PDT 24 |
| Finished | Jun 23 07:41:09 PM PDT 24 |
| Peak memory | 574076 kb |
| Host | smart-7dc905b1-341c-4a5e-8a86-37c440685642 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3619122854 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 96.xbar_random.3619122854 |
| Directory | /workspace/96.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/96.xbar_random_large_delays.4137595453 |
| Short name | T2295 |
| Test name | |
| Test status | |
| Simulation time | 55289646793 ps |
| CPU time | 622.52 seconds |
| Started | Jun 23 07:40:49 PM PDT 24 |
| Finished | Jun 23 07:51:12 PM PDT 24 |
| Peak memory | 573492 kb |
| Host | smart-b8c209b1-6d87-4ad1-842d-dfc227e6f3d3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4137595453 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 96.xbar_random_large_delays.4137595453 |
| Directory | /workspace/96.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/96.xbar_random_slow_rsp.2063053722 |
| Short name | T1996 |
| Test name | |
| Test status | |
| Simulation time | 52060714494 ps |
| CPU time | 999.95 seconds |
| Started | Jun 23 07:40:56 PM PDT 24 |
| Finished | Jun 23 07:57:36 PM PDT 24 |
| Peak memory | 573376 kb |
| Host | smart-fa65fb1b-766c-49cd-89c5-f745c0fd8a15 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2063053722 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 96.xbar_random_slow_rsp.2063053722 |
| Directory | /workspace/96.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/96.xbar_random_zero_delays.951753754 |
| Short name | T1705 |
| Test name | |
| Test status | |
| Simulation time | 100885359 ps |
| CPU time | 10.91 seconds |
| Started | Jun 23 07:40:55 PM PDT 24 |
| Finished | Jun 23 07:41:06 PM PDT 24 |
| Peak memory | 573328 kb |
| Host | smart-1d1cd4b4-c7ba-4cec-83f7-b19d5dc05d59 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=951753754 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 96.xbar_random_zero_dela ys.951753754 |
| Directory | /workspace/96.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/96.xbar_same_source.3576032005 |
| Short name | T2253 |
| Test name | |
| Test status | |
| Simulation time | 720069580 ps |
| CPU time | 23.75 seconds |
| Started | Jun 23 07:40:51 PM PDT 24 |
| Finished | Jun 23 07:41:16 PM PDT 24 |
| Peak memory | 573948 kb |
| Host | smart-7641ecaa-c3bc-46d6-9c1e-bb4987548c5e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3576032005 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 96.xbar_same_source.3576032005 |
| Directory | /workspace/96.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/96.xbar_smoke.1345385677 |
| Short name | T1708 |
| Test name | |
| Test status | |
| Simulation time | 189245507 ps |
| CPU time | 8.29 seconds |
| Started | Jun 23 07:40:48 PM PDT 24 |
| Finished | Jun 23 07:40:56 PM PDT 24 |
| Peak memory | 565652 kb |
| Host | smart-c00dc990-9827-4c35-994a-05ca3e6a5a07 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1345385677 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 96.xbar_smoke.1345385677 |
| Directory | /workspace/96.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/96.xbar_smoke_large_delays.1259767039 |
| Short name | T2123 |
| Test name | |
| Test status | |
| Simulation time | 10480951413 ps |
| CPU time | 123.49 seconds |
| Started | Jun 23 07:40:52 PM PDT 24 |
| Finished | Jun 23 07:42:56 PM PDT 24 |
| Peak memory | 566048 kb |
| Host | smart-d4e4c5ae-cd29-460c-83b7-09c09656ddb8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1259767039 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 96.xbar_smoke_large_delays.1259767039 |
| Directory | /workspace/96.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/96.xbar_smoke_slow_rsp.763588137 |
| Short name | T1429 |
| Test name | |
| Test status | |
| Simulation time | 3635248420 ps |
| CPU time | 62.59 seconds |
| Started | Jun 23 07:40:58 PM PDT 24 |
| Finished | Jun 23 07:42:01 PM PDT 24 |
| Peak memory | 565232 kb |
| Host | smart-f1f75c0b-25eb-4739-9c43-3eee9f0527e6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=763588137 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 96.xbar_smoke_slow_rsp.763588137 |
| Directory | /workspace/96.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/96.xbar_smoke_zero_delays.1006743284 |
| Short name | T2230 |
| Test name | |
| Test status | |
| Simulation time | 47189761 ps |
| CPU time | 6.31 seconds |
| Started | Jun 23 07:40:53 PM PDT 24 |
| Finished | Jun 23 07:40:59 PM PDT 24 |
| Peak memory | 565516 kb |
| Host | smart-72cf0458-113e-47f5-89ab-0cbc5ac9368c |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1006743284 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 96.xbar_smoke_zero_delay s.1006743284 |
| Directory | /workspace/96.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/96.xbar_stress_all.3453744255 |
| Short name | T2628 |
| Test name | |
| Test status | |
| Simulation time | 2502087732 ps |
| CPU time | 241.32 seconds |
| Started | Jun 23 07:40:51 PM PDT 24 |
| Finished | Jun 23 07:44:54 PM PDT 24 |
| Peak memory | 574440 kb |
| Host | smart-fd3126ea-8430-46fc-93a8-9bed24027ef4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3453744255 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 96.xbar_stress_all.3453744255 |
| Directory | /workspace/96.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/96.xbar_stress_all_with_error.3828558486 |
| Short name | T508 |
| Test name | |
| Test status | |
| Simulation time | 1583394127 ps |
| CPU time | 121.16 seconds |
| Started | Jun 23 07:40:50 PM PDT 24 |
| Finished | Jun 23 07:42:52 PM PDT 24 |
| Peak memory | 573532 kb |
| Host | smart-b58a413a-c26e-48a0-a6fa-f1de4629ab6d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3828558486 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 96.xbar_stress_all_with_error.3828558486 |
| Directory | /workspace/96.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/96.xbar_stress_all_with_rand_reset.162457140 |
| Short name | T551 |
| Test name | |
| Test status | |
| Simulation time | 1071225120 ps |
| CPU time | 127.56 seconds |
| Started | Jun 23 07:40:51 PM PDT 24 |
| Finished | Jun 23 07:42:59 PM PDT 24 |
| Peak memory | 576240 kb |
| Host | smart-4e3a5281-4eb6-401e-8ac8-1b7c301da2b0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=162457140 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_res et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 96.xbar_stress_all_ with_rand_reset.162457140 |
| Directory | /workspace/96.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/96.xbar_stress_all_with_reset_error.3258296206 |
| Short name | T1827 |
| Test name | |
| Test status | |
| Simulation time | 2441355330 ps |
| CPU time | 154.97 seconds |
| Started | Jun 23 07:40:55 PM PDT 24 |
| Finished | Jun 23 07:43:30 PM PDT 24 |
| Peak memory | 576356 kb |
| Host | smart-071b0871-7761-44b1-9456-a1ae3af34e61 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3258296206 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 96.xbar_stress_al l_with_reset_error.3258296206 |
| Directory | /workspace/96.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/96.xbar_unmapped_addr.3885765828 |
| Short name | T2370 |
| Test name | |
| Test status | |
| Simulation time | 343486028 ps |
| CPU time | 40.62 seconds |
| Started | Jun 23 07:40:53 PM PDT 24 |
| Finished | Jun 23 07:41:34 PM PDT 24 |
| Peak memory | 574140 kb |
| Host | smart-804fa8a5-0974-43d4-940a-67763c27d18e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3885765828 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 96.xbar_unmapped_addr.3885765828 |
| Directory | /workspace/96.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/97.xbar_access_same_device.3087331363 |
| Short name | T2696 |
| Test name | |
| Test status | |
| Simulation time | 1394785649 ps |
| CPU time | 63.68 seconds |
| Started | Jun 23 07:40:51 PM PDT 24 |
| Finished | Jun 23 07:41:56 PM PDT 24 |
| Peak memory | 574136 kb |
| Host | smart-c14f4ae5-c863-4729-8101-fd7ba744244b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3087331363 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 97.xbar_access_same_device .3087331363 |
| Directory | /workspace/97.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/97.xbar_error_and_unmapped_addr.1492702191 |
| Short name | T1433 |
| Test name | |
| Test status | |
| Simulation time | 840509471 ps |
| CPU time | 33.56 seconds |
| Started | Jun 23 07:40:57 PM PDT 24 |
| Finished | Jun 23 07:41:31 PM PDT 24 |
| Peak memory | 573300 kb |
| Host | smart-2a7b18e5-e5f2-424c-aff5-09f96eaa8304 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1492702191 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 97.xbar_error_and_unmapped_add r.1492702191 |
| Directory | /workspace/97.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/97.xbar_error_random.1739113534 |
| Short name | T1598 |
| Test name | |
| Test status | |
| Simulation time | 296439582 ps |
| CPU time | 13.27 seconds |
| Started | Jun 23 07:40:52 PM PDT 24 |
| Finished | Jun 23 07:41:06 PM PDT 24 |
| Peak memory | 573352 kb |
| Host | smart-4b7fe5ca-42f1-4213-af60-53cb305d2b07 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1739113534 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 97.xbar_error_random.1739113534 |
| Directory | /workspace/97.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/97.xbar_random.1515699735 |
| Short name | T1957 |
| Test name | |
| Test status | |
| Simulation time | 387577891 ps |
| CPU time | 33.23 seconds |
| Started | Jun 23 07:40:51 PM PDT 24 |
| Finished | Jun 23 07:41:25 PM PDT 24 |
| Peak memory | 574116 kb |
| Host | smart-dc46854f-5e04-4622-a288-21c4d592e6f7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1515699735 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 97.xbar_random.1515699735 |
| Directory | /workspace/97.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/97.xbar_random_large_delays.1470504060 |
| Short name | T542 |
| Test name | |
| Test status | |
| Simulation time | 60865247886 ps |
| CPU time | 626.13 seconds |
| Started | Jun 23 07:40:56 PM PDT 24 |
| Finished | Jun 23 07:51:22 PM PDT 24 |
| Peak memory | 574228 kb |
| Host | smart-734d4aab-fbb0-4f8c-8ef8-c0e6ab5aadb4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1470504060 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 97.xbar_random_large_delays.1470504060 |
| Directory | /workspace/97.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/97.xbar_random_slow_rsp.1356259345 |
| Short name | T2793 |
| Test name | |
| Test status | |
| Simulation time | 7876914754 ps |
| CPU time | 129.31 seconds |
| Started | Jun 23 07:40:57 PM PDT 24 |
| Finished | Jun 23 07:43:07 PM PDT 24 |
| Peak memory | 574188 kb |
| Host | smart-1c20976f-ffa5-4275-801e-30a1a8c98154 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1356259345 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 97.xbar_random_slow_rsp.1356259345 |
| Directory | /workspace/97.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/97.xbar_random_zero_delays.3681559726 |
| Short name | T2448 |
| Test name | |
| Test status | |
| Simulation time | 625644082 ps |
| CPU time | 52.51 seconds |
| Started | Jun 23 07:40:54 PM PDT 24 |
| Finished | Jun 23 07:41:47 PM PDT 24 |
| Peak memory | 574116 kb |
| Host | smart-3c6d5cd2-2192-4475-8dbe-73ea8e2f2259 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3681559726 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 97.xbar_random_zero_del ays.3681559726 |
| Directory | /workspace/97.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/97.xbar_same_source.657438581 |
| Short name | T2283 |
| Test name | |
| Test status | |
| Simulation time | 996297197 ps |
| CPU time | 30.53 seconds |
| Started | Jun 23 07:40:52 PM PDT 24 |
| Finished | Jun 23 07:41:23 PM PDT 24 |
| Peak memory | 574072 kb |
| Host | smart-0f2d7f3d-21f2-4134-b2ae-b24f358e5945 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=657438581 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 97.xbar_same_source.657438581 |
| Directory | /workspace/97.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/97.xbar_smoke.2292894242 |
| Short name | T1468 |
| Test name | |
| Test status | |
| Simulation time | 35914146 ps |
| CPU time | 5.41 seconds |
| Started | Jun 23 07:40:50 PM PDT 24 |
| Finished | Jun 23 07:40:56 PM PDT 24 |
| Peak memory | 565648 kb |
| Host | smart-bc1bbe54-6268-470c-a544-6bd26ae48fa2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2292894242 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 97.xbar_smoke.2292894242 |
| Directory | /workspace/97.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/97.xbar_smoke_large_delays.8276449 |
| Short name | T1514 |
| Test name | |
| Test status | |
| Simulation time | 9414620704 ps |
| CPU time | 96.86 seconds |
| Started | Jun 23 07:40:52 PM PDT 24 |
| Finished | Jun 23 07:42:30 PM PDT 24 |
| Peak memory | 565256 kb |
| Host | smart-d28c422d-53cd-4a31-a725-fc419e1bc24d |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=8276449 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 97.xbar_smoke_large_delays.8276449 |
| Directory | /workspace/97.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/97.xbar_smoke_slow_rsp.33202943 |
| Short name | T1801 |
| Test name | |
| Test status | |
| Simulation time | 4859481975 ps |
| CPU time | 79.91 seconds |
| Started | Jun 23 07:40:58 PM PDT 24 |
| Finished | Jun 23 07:42:19 PM PDT 24 |
| Peak memory | 565520 kb |
| Host | smart-6512ad4b-aecc-4844-9b11-f5e2000bddba |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33202943 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 97.xbar_smoke_slow_rsp.33202943 |
| Directory | /workspace/97.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/97.xbar_smoke_zero_delays.3645155483 |
| Short name | T1374 |
| Test name | |
| Test status | |
| Simulation time | 51370623 ps |
| CPU time | 6.28 seconds |
| Started | Jun 23 07:40:50 PM PDT 24 |
| Finished | Jun 23 07:40:57 PM PDT 24 |
| Peak memory | 565532 kb |
| Host | smart-562cb4bb-3be6-45b0-99c1-4856297b3fdd |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3645155483 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 97.xbar_smoke_zero_delay s.3645155483 |
| Directory | /workspace/97.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/97.xbar_stress_all.2282335664 |
| Short name | T436 |
| Test name | |
| Test status | |
| Simulation time | 6719549730 ps |
| CPU time | 259.26 seconds |
| Started | Jun 23 07:40:57 PM PDT 24 |
| Finished | Jun 23 07:45:17 PM PDT 24 |
| Peak memory | 574164 kb |
| Host | smart-ae94436b-713d-4e34-8119-d743f23a4a4c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2282335664 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 97.xbar_stress_all.2282335664 |
| Directory | /workspace/97.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/97.xbar_stress_all_with_error.3836181152 |
| Short name | T1532 |
| Test name | |
| Test status | |
| Simulation time | 10195282025 ps |
| CPU time | 407.64 seconds |
| Started | Jun 23 07:41:03 PM PDT 24 |
| Finished | Jun 23 07:47:51 PM PDT 24 |
| Peak memory | 574364 kb |
| Host | smart-c5336eca-7314-4017-b605-a8f5cb357f03 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3836181152 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 97.xbar_stress_all_with_error.3836181152 |
| Directory | /workspace/97.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/97.xbar_stress_all_with_rand_reset.3718227930 |
| Short name | T580 |
| Test name | |
| Test status | |
| Simulation time | 3902964580 ps |
| CPU time | 583.34 seconds |
| Started | Jun 23 07:41:02 PM PDT 24 |
| Finished | Jun 23 07:50:46 PM PDT 24 |
| Peak memory | 576356 kb |
| Host | smart-6ebdbb6d-5ed0-487c-a54a-b4525e6c458d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3718227930 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 97.xbar_stress_all _with_rand_reset.3718227930 |
| Directory | /workspace/97.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/97.xbar_stress_all_with_reset_error.1325921531 |
| Short name | T2586 |
| Test name | |
| Test status | |
| Simulation time | 2647176625 ps |
| CPU time | 433.84 seconds |
| Started | Jun 23 07:41:01 PM PDT 24 |
| Finished | Jun 23 07:48:15 PM PDT 24 |
| Peak memory | 574352 kb |
| Host | smart-86126830-5e52-4ab0-ab71-ecfaedb5d676 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1325921531 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 97.xbar_stress_al l_with_reset_error.1325921531 |
| Directory | /workspace/97.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/97.xbar_unmapped_addr.3322846524 |
| Short name | T1767 |
| Test name | |
| Test status | |
| Simulation time | 1144924776 ps |
| CPU time | 41.66 seconds |
| Started | Jun 23 07:41:02 PM PDT 24 |
| Finished | Jun 23 07:41:44 PM PDT 24 |
| Peak memory | 573432 kb |
| Host | smart-5455dd8d-82eb-4974-a0b4-5b940b27cf1f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3322846524 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 97.xbar_unmapped_addr.3322846524 |
| Directory | /workspace/97.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/98.xbar_access_same_device.3372876088 |
| Short name | T2276 |
| Test name | |
| Test status | |
| Simulation time | 2889337224 ps |
| CPU time | 127.6 seconds |
| Started | Jun 23 07:41:03 PM PDT 24 |
| Finished | Jun 23 07:43:11 PM PDT 24 |
| Peak memory | 574176 kb |
| Host | smart-7688138e-3822-42f0-8183-ba77b06c365c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3372876088 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 98.xbar_access_same_device .3372876088 |
| Directory | /workspace/98.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/98.xbar_access_same_device_slow_rsp.416791471 |
| Short name | T2494 |
| Test name | |
| Test status | |
| Simulation time | 103336093726 ps |
| CPU time | 1831.83 seconds |
| Started | Jun 23 07:40:58 PM PDT 24 |
| Finished | Jun 23 08:11:31 PM PDT 24 |
| Peak memory | 574228 kb |
| Host | smart-270109fd-cc31-4ff8-a19b-cff1d6c8cfd7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=416791471 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 98.xbar_access_same_d evice_slow_rsp.416791471 |
| Directory | /workspace/98.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/98.xbar_error_and_unmapped_addr.310217614 |
| Short name | T512 |
| Test name | |
| Test status | |
| Simulation time | 564085483 ps |
| CPU time | 27.19 seconds |
| Started | Jun 23 07:41:00 PM PDT 24 |
| Finished | Jun 23 07:41:28 PM PDT 24 |
| Peak memory | 573316 kb |
| Host | smart-1a5086c0-2407-4da3-b7a0-c6438b62e3a7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=310217614 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 98.xbar_error_and_unmapped_addr .310217614 |
| Directory | /workspace/98.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/98.xbar_error_random.3087054844 |
| Short name | T1970 |
| Test name | |
| Test status | |
| Simulation time | 2129964736 ps |
| CPU time | 67.7 seconds |
| Started | Jun 23 07:41:00 PM PDT 24 |
| Finished | Jun 23 07:42:08 PM PDT 24 |
| Peak memory | 573740 kb |
| Host | smart-db828167-8769-49dc-9c08-aed436b8ae32 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3087054844 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 98.xbar_error_random.3087054844 |
| Directory | /workspace/98.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/98.xbar_random.775553816 |
| Short name | T581 |
| Test name | |
| Test status | |
| Simulation time | 167517158 ps |
| CPU time | 17.52 seconds |
| Started | Jun 23 07:40:57 PM PDT 24 |
| Finished | Jun 23 07:41:15 PM PDT 24 |
| Peak memory | 574104 kb |
| Host | smart-5a95504e-ad49-4ea3-b28c-9b11ae54e574 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=775553816 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 98.xbar_random.775553816 |
| Directory | /workspace/98.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/98.xbar_random_large_delays.2263405633 |
| Short name | T567 |
| Test name | |
| Test status | |
| Simulation time | 78198277239 ps |
| CPU time | 932.81 seconds |
| Started | Jun 23 07:40:58 PM PDT 24 |
| Finished | Jun 23 07:56:31 PM PDT 24 |
| Peak memory | 574120 kb |
| Host | smart-46bbd558-4e80-47a2-baa9-0c7b08c77719 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2263405633 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 98.xbar_random_large_delays.2263405633 |
| Directory | /workspace/98.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/98.xbar_random_slow_rsp.2564890094 |
| Short name | T489 |
| Test name | |
| Test status | |
| Simulation time | 51845549896 ps |
| CPU time | 943.09 seconds |
| Started | Jun 23 07:41:02 PM PDT 24 |
| Finished | Jun 23 07:56:46 PM PDT 24 |
| Peak memory | 574200 kb |
| Host | smart-67576e85-7e63-4b39-9df1-0ad3e45ffd13 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2564890094 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 98.xbar_random_slow_rsp.2564890094 |
| Directory | /workspace/98.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/98.xbar_random_zero_delays.4122688492 |
| Short name | T2561 |
| Test name | |
| Test status | |
| Simulation time | 271762209 ps |
| CPU time | 24.77 seconds |
| Started | Jun 23 07:40:58 PM PDT 24 |
| Finished | Jun 23 07:41:24 PM PDT 24 |
| Peak memory | 573944 kb |
| Host | smart-06cd65dd-416a-4235-b387-2c5a8b3c4a8d |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4122688492 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 98.xbar_random_zero_del ays.4122688492 |
| Directory | /workspace/98.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/98.xbar_same_source.3424844086 |
| Short name | T2279 |
| Test name | |
| Test status | |
| Simulation time | 2175937914 ps |
| CPU time | 66.38 seconds |
| Started | Jun 23 07:40:57 PM PDT 24 |
| Finished | Jun 23 07:42:04 PM PDT 24 |
| Peak memory | 573460 kb |
| Host | smart-5eb2ff03-6642-4ded-8b49-c39c9c2e33c8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3424844086 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 98.xbar_same_source.3424844086 |
| Directory | /workspace/98.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/98.xbar_smoke.695919603 |
| Short name | T2617 |
| Test name | |
| Test status | |
| Simulation time | 44860756 ps |
| CPU time | 6.62 seconds |
| Started | Jun 23 07:40:52 PM PDT 24 |
| Finished | Jun 23 07:40:59 PM PDT 24 |
| Peak memory | 573308 kb |
| Host | smart-1168aa32-33b1-4313-8951-f73698710b3e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=695919603 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 98.xbar_smoke.695919603 |
| Directory | /workspace/98.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/98.xbar_smoke_large_delays.2911253074 |
| Short name | T1500 |
| Test name | |
| Test status | |
| Simulation time | 6822628779 ps |
| CPU time | 68.62 seconds |
| Started | Jun 23 07:41:01 PM PDT 24 |
| Finished | Jun 23 07:42:10 PM PDT 24 |
| Peak memory | 565932 kb |
| Host | smart-43d8c523-8e82-4521-b2d7-d9aebfa6fdd0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2911253074 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 98.xbar_smoke_large_delays.2911253074 |
| Directory | /workspace/98.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/98.xbar_smoke_slow_rsp.2320963224 |
| Short name | T1431 |
| Test name | |
| Test status | |
| Simulation time | 5011142123 ps |
| CPU time | 83.84 seconds |
| Started | Jun 23 07:40:58 PM PDT 24 |
| Finished | Jun 23 07:42:23 PM PDT 24 |
| Peak memory | 565532 kb |
| Host | smart-68743f3a-5e0e-4904-982d-03da67a5716a |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2320963224 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 98.xbar_smoke_slow_rsp.2320963224 |
| Directory | /workspace/98.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/98.xbar_smoke_zero_delays.817528060 |
| Short name | T1458 |
| Test name | |
| Test status | |
| Simulation time | 44996625 ps |
| CPU time | 5.97 seconds |
| Started | Jun 23 07:41:03 PM PDT 24 |
| Finished | Jun 23 07:41:09 PM PDT 24 |
| Peak memory | 565464 kb |
| Host | smart-05670eb2-b2df-4cd0-ae4e-efe9bf27aa79 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=817528060 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 98.xbar_smoke_zero_delays .817528060 |
| Directory | /workspace/98.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/98.xbar_stress_all.45831898 |
| Short name | T476 |
| Test name | |
| Test status | |
| Simulation time | 6790325453 ps |
| CPU time | 223.38 seconds |
| Started | Jun 23 07:41:00 PM PDT 24 |
| Finished | Jun 23 07:44:44 PM PDT 24 |
| Peak memory | 574296 kb |
| Host | smart-2adfd2bb-0fc7-4294-9728-f9878635d937 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45831898 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 98.xbar_stress_all.45831898 |
| Directory | /workspace/98.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/98.xbar_stress_all_with_error.2122156653 |
| Short name | T2259 |
| Test name | |
| Test status | |
| Simulation time | 2001828459 ps |
| CPU time | 149.23 seconds |
| Started | Jun 23 07:42:01 PM PDT 24 |
| Finished | Jun 23 07:44:30 PM PDT 24 |
| Peak memory | 574296 kb |
| Host | smart-e010d51c-eef2-457b-94f9-95633f876ae1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2122156653 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 98.xbar_stress_all_with_error.2122156653 |
| Directory | /workspace/98.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/98.xbar_stress_all_with_rand_reset.1173374916 |
| Short name | T539 |
| Test name | |
| Test status | |
| Simulation time | 230518384 ps |
| CPU time | 72.58 seconds |
| Started | Jun 23 07:41:06 PM PDT 24 |
| Finished | Jun 23 07:42:19 PM PDT 24 |
| Peak memory | 574208 kb |
| Host | smart-f7ef8a8b-de2d-495b-afff-4ede0dc7f973 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1173374916 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 98.xbar_stress_all _with_rand_reset.1173374916 |
| Directory | /workspace/98.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/98.xbar_stress_all_with_reset_error.138290298 |
| Short name | T1710 |
| Test name | |
| Test status | |
| Simulation time | 165621672 ps |
| CPU time | 19.07 seconds |
| Started | Jun 23 07:41:08 PM PDT 24 |
| Finished | Jun 23 07:41:27 PM PDT 24 |
| Peak memory | 576260 kb |
| Host | smart-d2b5320e-2eba-4acc-9187-f46e0ccdc61a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=138290298 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 98.xbar_stress_all _with_reset_error.138290298 |
| Directory | /workspace/98.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/98.xbar_unmapped_addr.1557194682 |
| Short name | T1812 |
| Test name | |
| Test status | |
| Simulation time | 252441200 ps |
| CPU time | 30.33 seconds |
| Started | Jun 23 07:41:00 PM PDT 24 |
| Finished | Jun 23 07:41:31 PM PDT 24 |
| Peak memory | 574136 kb |
| Host | smart-2b676ab1-4717-40a1-b0be-ef3294998d39 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1557194682 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 98.xbar_unmapped_addr.1557194682 |
| Directory | /workspace/98.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/99.xbar_access_same_device.1460854378 |
| Short name | T2550 |
| Test name | |
| Test status | |
| Simulation time | 872995061 ps |
| CPU time | 66.28 seconds |
| Started | Jun 23 07:41:07 PM PDT 24 |
| Finished | Jun 23 07:42:13 PM PDT 24 |
| Peak memory | 574116 kb |
| Host | smart-3023a1e2-32ba-481b-812a-90788fac4d44 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1460854378 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 99.xbar_access_same_device .1460854378 |
| Directory | /workspace/99.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/99.xbar_access_same_device_slow_rsp.1607265764 |
| Short name | T2570 |
| Test name | |
| Test status | |
| Simulation time | 106811298746 ps |
| CPU time | 1836.93 seconds |
| Started | Jun 23 07:41:07 PM PDT 24 |
| Finished | Jun 23 08:11:45 PM PDT 24 |
| Peak memory | 574224 kb |
| Host | smart-4dafac67-1f38-4927-8693-0b858bedb5d8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1607265764 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 99.xbar_access_same_ device_slow_rsp.1607265764 |
| Directory | /workspace/99.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/99.xbar_error_and_unmapped_addr.2907755550 |
| Short name | T1552 |
| Test name | |
| Test status | |
| Simulation time | 341322268 ps |
| CPU time | 16.52 seconds |
| Started | Jun 23 07:41:10 PM PDT 24 |
| Finished | Jun 23 07:41:27 PM PDT 24 |
| Peak memory | 573680 kb |
| Host | smart-2f514d3f-0968-49aa-9eec-3f6c19bb7b3c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2907755550 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 99.xbar_error_and_unmapped_add r.2907755550 |
| Directory | /workspace/99.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/99.xbar_error_random.3918556015 |
| Short name | T2695 |
| Test name | |
| Test status | |
| Simulation time | 2692709258 ps |
| CPU time | 106.09 seconds |
| Started | Jun 23 07:41:11 PM PDT 24 |
| Finished | Jun 23 07:42:57 PM PDT 24 |
| Peak memory | 573820 kb |
| Host | smart-800e60ed-baba-44c4-8905-20958ed06508 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3918556015 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 99.xbar_error_random.3918556015 |
| Directory | /workspace/99.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/99.xbar_random.251726479 |
| Short name | T2560 |
| Test name | |
| Test status | |
| Simulation time | 1756913033 ps |
| CPU time | 65.63 seconds |
| Started | Jun 23 07:41:06 PM PDT 24 |
| Finished | Jun 23 07:42:12 PM PDT 24 |
| Peak memory | 573408 kb |
| Host | smart-f46d65d9-8371-4290-9d6a-3b2a3c13f451 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=251726479 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 99.xbar_random.251726479 |
| Directory | /workspace/99.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/99.xbar_random_large_delays.4240551463 |
| Short name | T2488 |
| Test name | |
| Test status | |
| Simulation time | 24999342169 ps |
| CPU time | 287.27 seconds |
| Started | Jun 23 07:41:08 PM PDT 24 |
| Finished | Jun 23 07:45:56 PM PDT 24 |
| Peak memory | 574192 kb |
| Host | smart-ffd53b99-6449-42a2-9f7b-451f4c9d8822 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4240551463 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 99.xbar_random_large_delays.4240551463 |
| Directory | /workspace/99.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/99.xbar_random_slow_rsp.430001068 |
| Short name | T1619 |
| Test name | |
| Test status | |
| Simulation time | 64892378519 ps |
| CPU time | 1164.15 seconds |
| Started | Jun 23 07:41:07 PM PDT 24 |
| Finished | Jun 23 08:00:32 PM PDT 24 |
| Peak memory | 573464 kb |
| Host | smart-52095212-3919-4f63-80c5-0637e00d5709 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=430001068 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 99.xbar_random_slow_rsp.430001068 |
| Directory | /workspace/99.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/99.xbar_random_zero_delays.2500320396 |
| Short name | T2027 |
| Test name | |
| Test status | |
| Simulation time | 556234275 ps |
| CPU time | 44.65 seconds |
| Started | Jun 23 07:41:05 PM PDT 24 |
| Finished | Jun 23 07:41:50 PM PDT 24 |
| Peak memory | 574092 kb |
| Host | smart-436b19b5-f06e-452e-9e9a-761a485f285b |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2500320396 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 99.xbar_random_zero_del ays.2500320396 |
| Directory | /workspace/99.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/99.xbar_same_source.3786189991 |
| Short name | T1804 |
| Test name | |
| Test status | |
| Simulation time | 1927498203 ps |
| CPU time | 58.88 seconds |
| Started | Jun 23 07:41:13 PM PDT 24 |
| Finished | Jun 23 07:42:12 PM PDT 24 |
| Peak memory | 574084 kb |
| Host | smart-546debc2-a783-4040-885f-0cb330cdec46 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3786189991 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 99.xbar_same_source.3786189991 |
| Directory | /workspace/99.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/99.xbar_smoke.3647542825 |
| Short name | T2516 |
| Test name | |
| Test status | |
| Simulation time | 220886735 ps |
| CPU time | 9.08 seconds |
| Started | Jun 23 07:41:01 PM PDT 24 |
| Finished | Jun 23 07:41:10 PM PDT 24 |
| Peak memory | 565168 kb |
| Host | smart-a053a624-8881-4b73-bf7d-49da17ae3d70 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3647542825 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 99.xbar_smoke.3647542825 |
| Directory | /workspace/99.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/99.xbar_smoke_large_delays.2809380527 |
| Short name | T2674 |
| Test name | |
| Test status | |
| Simulation time | 8674522000 ps |
| CPU time | 87.54 seconds |
| Started | Jun 23 07:41:02 PM PDT 24 |
| Finished | Jun 23 07:42:30 PM PDT 24 |
| Peak memory | 573460 kb |
| Host | smart-ab5bae4e-fc82-4140-9a5e-fb453c4a3246 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2809380527 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 99.xbar_smoke_large_delays.2809380527 |
| Directory | /workspace/99.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/99.xbar_smoke_slow_rsp.1103449531 |
| Short name | T1544 |
| Test name | |
| Test status | |
| Simulation time | 4453574069 ps |
| CPU time | 80.08 seconds |
| Started | Jun 23 07:41:06 PM PDT 24 |
| Finished | Jun 23 07:42:27 PM PDT 24 |
| Peak memory | 565952 kb |
| Host | smart-e3f6d3cc-0543-4635-8da2-4f7a690e63c3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1103449531 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 99.xbar_smoke_slow_rsp.1103449531 |
| Directory | /workspace/99.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/99.xbar_smoke_zero_delays.653321460 |
| Short name | T1713 |
| Test name | |
| Test status | |
| Simulation time | 36657896 ps |
| CPU time | 5.62 seconds |
| Started | Jun 23 07:41:03 PM PDT 24 |
| Finished | Jun 23 07:41:09 PM PDT 24 |
| Peak memory | 565532 kb |
| Host | smart-4aee675f-c260-44e4-b44a-028ccfd2b012 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=653321460 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 99.xbar_smoke_zero_delays .653321460 |
| Directory | /workspace/99.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/99.xbar_stress_all.3727447491 |
| Short name | T455 |
| Test name | |
| Test status | |
| Simulation time | 4162231999 ps |
| CPU time | 153.05 seconds |
| Started | Jun 23 07:41:11 PM PDT 24 |
| Finished | Jun 23 07:43:44 PM PDT 24 |
| Peak memory | 574300 kb |
| Host | smart-0f2cf5d8-6551-44f0-9a59-a260e83db54a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3727447491 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 99.xbar_stress_all.3727447491 |
| Directory | /workspace/99.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/99.xbar_stress_all_with_error.811677003 |
| Short name | T2367 |
| Test name | |
| Test status | |
| Simulation time | 3496866734 ps |
| CPU time | 123.17 seconds |
| Started | Jun 23 07:41:09 PM PDT 24 |
| Finished | Jun 23 07:43:13 PM PDT 24 |
| Peak memory | 574232 kb |
| Host | smart-91399446-6d1d-4514-bfbd-227477a5f23d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=811677003 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 99.xbar_stress_all_with_error.811677003 |
| Directory | /workspace/99.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/99.xbar_stress_all_with_reset_error.326297060 |
| Short name | T2465 |
| Test name | |
| Test status | |
| Simulation time | 3636368538 ps |
| CPU time | 359.34 seconds |
| Started | Jun 23 07:41:11 PM PDT 24 |
| Finished | Jun 23 07:47:11 PM PDT 24 |
| Peak memory | 574380 kb |
| Host | smart-5fbb0f14-a849-4f75-a23b-655e15e5a38d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=326297060 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 99.xbar_stress_all _with_reset_error.326297060 |
| Directory | /workspace/99.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/99.xbar_unmapped_addr.1918016726 |
| Short name | T2483 |
| Test name | |
| Test status | |
| Simulation time | 355311867 ps |
| CPU time | 16.13 seconds |
| Started | Jun 23 07:41:12 PM PDT 24 |
| Finished | Jun 23 07:41:28 PM PDT 24 |
| Peak memory | 574132 kb |
| Host | smart-c170b0dc-1dd4-47df-ad58-fd2e798db4d9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1918016726 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 99.xbar_unmapped_addr.1918016726 |
| Directory | /workspace/99.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/default/0.chip_jtag_csr_rw.1926883117 |
| Short name | T74 |
| Test name | |
| Test status | |
| Simulation time | 10610563248 ps |
| CPU time | 1297.71 seconds |
| Started | Jun 23 07:43:09 PM PDT 24 |
| Finished | Jun 23 08:04:47 PM PDT 24 |
| Peak memory | 604712 kb |
| Host | smart-4b34aabc-df98-40d9-896c-eeda45cc9d2a |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +csr_rw +create_jtag_riscv_map=1 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1926883117 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_T EST_SEQ=chip_jtag_csr_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.c hip_jtag_csr_rw.1926883117 |
| Directory | /workspace/0.chip_jtag_csr_rw/latest |
| Test location | /workspace/coverage/default/0.chip_jtag_mem_access.2143663275 |
| Short name | T194 |
| Test name | |
| Test status | |
| Simulation time | 13253440278 ps |
| CPU time | 1474.67 seconds |
| Started | Jun 23 07:43:13 PM PDT 24 |
| Finished | Jun 23 08:07:48 PM PDT 24 |
| Peak memory | 605084 kb |
| Host | smart-79e40932-1581-4f04-b71e-d088d77eaff2 |
| User | root |
| Command | /workspace/default/simv +create_jtag_riscv_map=1 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2143663275 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_jtag_ mem_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_jtag_mem_access.2 143663275 |
| Directory | /workspace/0.chip_jtag_mem_access/latest |
| Test location | /workspace/coverage/default/0.chip_rv_dm_ndm_reset_req.1100899691 |
| Short name | T399 |
| Test name | |
| Test status | |
| Simulation time | 5030509714 ps |
| CPU time | 388.19 seconds |
| Started | Jun 23 07:51:37 PM PDT 24 |
| Finished | Jun 23 07:58:06 PM PDT 24 |
| Peak memory | 617608 kb |
| Host | smart-5c24ef0f-90de-4a9c-959e-74d10becd21e |
| User | root |
| Command | /workspace/default/simv +en_scb_tl_err_chk=0 +use_jtag_dmi=1 +sw_build_device=sim_dv +sw_images=rv_dm_ndm_reset_req_rma:1:new_rules,test_rom:0 +cdc_in strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1 100899691 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_rv_dm_ndm_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_rv_dm_ndm_reset_req.1100899691 |
| Directory | /workspace/0.chip_rv_dm_ndm_reset_req/latest |
| Test location | /workspace/coverage/default/0.chip_sival_flash_info_access.3978166800 |
| Short name | T164 |
| Test name | |
| Test status | |
| Simulation time | 3090669330 ps |
| CPU time | 368.69 seconds |
| Started | Jun 23 07:49:13 PM PDT 24 |
| Finished | Jun 23 07:55:22 PM PDT 24 |
| Peak memory | 607632 kb |
| Host | smart-13d3bd1e-e660-4de3-9de5-779aed656894 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStTestUnlocked0 +sw_build_device=sim_dv +sw_images=flash_ctrl_info_access_lc:1:new_rules,test_rom:0 +c dc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_s eed=3978166800 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sival_flash_info_access.3978166800 |
| Directory | /workspace/0.chip_sival_flash_info_access/latest |
| Test location | /workspace/coverage/default/0.chip_sw_aes_enc.3963853614 |
| Short name | T1217 |
| Test name | |
| Test status | |
| Simulation time | 3301336754 ps |
| CPU time | 351.08 seconds |
| Started | Jun 23 07:49:17 PM PDT 24 |
| Finished | Jun 23 07:55:08 PM PDT 24 |
| Peak memory | 606756 kb |
| Host | smart-1cf50601-33ee-44fe-b091-f1316bbea112 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=22_000_000 +sw_build_device=sim_dv +sw_images=aes_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3963853614 -asser t nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag e/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_aes_enc.3963853614 |
| Directory | /workspace/0.chip_sw_aes_enc/latest |
| Test location | /workspace/coverage/default/0.chip_sw_aes_enc_jitter_en.1721876741 |
| Short name | T1043 |
| Test name | |
| Test status | |
| Simulation time | 3559293517 ps |
| CPU time | 237.55 seconds |
| Started | Jun 23 07:53:03 PM PDT 24 |
| Finished | Jun 23 07:57:00 PM PDT 24 |
| Peak memory | 606764 kb |
| Host | smart-6b7f2fb9-4459-4fb8-ae3b-93bfc27dfb5e |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=26_000_000 +en_jitter=1 +sw_build_device=sim_dv +sw_images=aes_smoketest:1:new_rules,test_rom:0 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1721 876741 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work space/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_aes_enc_jitter_en.1721876741 |
| Directory | /workspace/0.chip_sw_aes_enc_jitter_en/latest |
| Test location | /workspace/coverage/default/0.chip_sw_aes_enc_jitter_en_reduced_freq.2946239039 |
| Short name | T1341 |
| Test name | |
| Test status | |
| Simulation time | 2841437444 ps |
| CPU time | 278.18 seconds |
| Started | Jun 23 07:53:33 PM PDT 24 |
| Finished | Jun 23 07:58:12 PM PDT 24 |
| Peak memory | 606896 kb |
| Host | smart-9e6c0637-2b43-4924-941f-05d04e0619b5 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=26_000_000 +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=aes_smoketest:1:new_rules, test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2946239039 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_aes_enc_jitter_en_reduced_freq.2946239039 |
| Directory | /workspace/0.chip_sw_aes_enc_jitter_en_reduced_freq/latest |
| Test location | /workspace/coverage/default/0.chip_sw_aes_entropy.3588398239 |
| Short name | T1011 |
| Test name | |
| Test status | |
| Simulation time | 2638786180 ps |
| CPU time | 315.01 seconds |
| Started | Jun 23 07:52:57 PM PDT 24 |
| Finished | Jun 23 07:58:13 PM PDT 24 |
| Peak memory | 606752 kb |
| Host | smart-82506354-33b7-41c0-829f-8ca50443bb72 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=15_000_000 +sw_build_device=sim_dv +sw_images=aes_entropy_test:1:new_rules,test_rom:0 +cdc_instrumentation _enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3588398239 -as sert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove rage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_aes_entropy.3588398239 |
| Directory | /workspace/0.chip_sw_aes_entropy/latest |
| Test location | /workspace/coverage/default/0.chip_sw_aes_idle.1004578964 |
| Short name | T959 |
| Test name | |
| Test status | |
| Simulation time | 3164332060 ps |
| CPU time | 219.18 seconds |
| Started | Jun 23 07:49:32 PM PDT 24 |
| Finished | Jun 23 07:53:12 PM PDT 24 |
| Peak memory | 606860 kb |
| Host | smart-a989ce67-f87f-4ae4-88a7-ca2bd50e36e1 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=25_000_000 +sw_build_device=sim_dv +sw_images=aes_idle_test:1:new_rules,test_rom:0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1004578964 -asser t nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag e/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_aes_idle.1004578964 |
| Directory | /workspace/0.chip_sw_aes_idle/latest |
| Test location | /workspace/coverage/default/0.chip_sw_aes_masking_off.378682440 |
| Short name | T1169 |
| Test name | |
| Test status | |
| Simulation time | 2444610158 ps |
| CPU time | 363.09 seconds |
| Started | Jun 23 07:50:49 PM PDT 24 |
| Finished | Jun 23 07:56:53 PM PDT 24 |
| Peak memory | 607600 kb |
| Host | smart-6017e4b2-2a9b-4957-aed5-e80537beefd7 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=aes_masking_off_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=378682440 -assert nopostproc +UVM_TESTNAM E=chip_base_test +UVM_TEST_SEQ=chip_sw_aes_masking_off_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_aes_masking_off.378682440 |
| Directory | /workspace/0.chip_sw_aes_masking_off/latest |
| Test location | /workspace/coverage/default/0.chip_sw_aes_smoketest.68103662 |
| Short name | T1018 |
| Test name | |
| Test status | |
| Simulation time | 3735187856 ps |
| CPU time | 305.68 seconds |
| Started | Jun 23 07:56:12 PM PDT 24 |
| Finished | Jun 23 08:01:18 PM PDT 24 |
| Peak memory | 607572 kb |
| Host | smart-679698c8-be65-4081-bb2a-cd25b57eb6ef |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=aes_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68103662 -assert nopostproc +UVM_TESTNAME=chip_b ase_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 0.chip_sw_aes_smoketest.68103662 |
| Directory | /workspace/0.chip_sw_aes_smoketest/latest |
| Test location | /workspace/coverage/default/0.chip_sw_alert_handler_entropy.1567130908 |
| Short name | T1330 |
| Test name | |
| Test status | |
| Simulation time | 3117355204 ps |
| CPU time | 375.37 seconds |
| Started | Jun 23 07:50:29 PM PDT 24 |
| Finished | Jun 23 07:56:45 PM PDT 24 |
| Peak memory | 607816 kb |
| Host | smart-2375f18a-09f7-4697-959c-1c1519676107 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=alert_handler_entropy_test:1:new_rules,test_ro m:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=1567130908 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_alert_handler_entropy.1567130908 |
| Directory | /workspace/0.chip_sw_alert_handler_entropy/latest |
| Test location | /workspace/coverage/default/0.chip_sw_alert_handler_escalation.3314193660 |
| Short name | T1055 |
| Test name | |
| Test status | |
| Simulation time | 5914161880 ps |
| CPU time | 604.14 seconds |
| Started | Jun 23 07:49:56 PM PDT 24 |
| Finished | Jun 23 08:00:01 PM PDT 24 |
| Peak memory | 616972 kb |
| Host | smart-e58542ab-d6ab-48c8-add2-2e7088046b18 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=alert_handler_escalation_test:1:new_rules,test _rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb _random_seed=3314193660 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_alert_handler_escalation_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_alert_handler_escalation.3314193660 |
| Directory | /workspace/0.chip_sw_alert_handler_escalation/latest |
| Test location | /workspace/coverage/default/0.chip_sw_alert_handler_lpg_reset_toggle.224970432 |
| Short name | T1159 |
| Test name | |
| Test status | |
| Simulation time | 7432183548 ps |
| CPU time | 1555.12 seconds |
| Started | Jun 23 07:50:57 PM PDT 24 |
| Finished | Jun 23 08:16:53 PM PDT 24 |
| Peak memory | 607944 kb |
| Host | smart-1b722b11-67a1-44ea-b197-54e9206f43ef |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +sw_build_device=sim_dv +sw_images=alert_handler_lpg_reset_toggle_test:1:new_rules, test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=224970432 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_alert_handler_shorten_ping_wait_cycle_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_alert_handler_lpg_reset_toggle.224970432 |
| Directory | /workspace/0.chip_sw_alert_handler_lpg_reset_toggle/latest |
| Test location | /workspace/coverage/default/0.chip_sw_alert_handler_lpg_sleep_mode_pings.1183501277 |
| Short name | T79 |
| Test name | |
| Test status | |
| Simulation time | 10409218400 ps |
| CPU time | 1203.79 seconds |
| Started | Jun 23 07:49:56 PM PDT 24 |
| Finished | Jun 23 08:10:00 PM PDT 24 |
| Peak memory | 608716 kb |
| Host | smart-09f7194b-029c-4493-bbd4-761a6e515a9c |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=alert_handler _lpg_sleep_mode_pings_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1183501277 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_alert_han dler_shorten_ping_wait_cycle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_alert_handler_lpg_sleep_mode_pings.1183501277 |
| Directory | /workspace/0.chip_sw_alert_handler_lpg_sleep_mode_pings/latest |
| Test location | /workspace/coverage/default/0.chip_sw_alert_handler_ping_ok.3796315531 |
| Short name | T1028 |
| Test name | |
| Test status | |
| Simulation time | 7705632880 ps |
| CPU time | 1415.32 seconds |
| Started | Jun 23 07:50:50 PM PDT 24 |
| Finished | Jun 23 08:14:26 PM PDT 24 |
| Peak memory | 607020 kb |
| Host | smart-f2bfd16f-ec72-407a-900e-8341db29f0f4 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=24000000 +sw_build_device=sim_dv +sw_images=alert_handler_ping_ok_test:1:new_rules,test_rom:0 +c dc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_s eed=3796315531 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_alert_handler_ping_ok.3796315531 |
| Directory | /workspace/0.chip_sw_alert_handler_ping_ok/latest |
| Test location | /workspace/coverage/default/0.chip_sw_alert_handler_ping_timeout.1615390658 |
| Short name | T99 |
| Test name | |
| Test status | |
| Simulation time | 3684998430 ps |
| CPU time | 310.05 seconds |
| Started | Jun 23 07:51:56 PM PDT 24 |
| Finished | Jun 23 07:57:07 PM PDT 24 |
| Peak memory | 606832 kb |
| Host | smart-631af008-89ff-4fc7-b9c1-f51a829a5355 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=24000000 +sw_build_device=sim_dv +sw_images=alert_handler_ping_timeout_test:1:new_rules,test_rom :0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=1615390658 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_alert_handler_ping_timeout.1615390658 |
| Directory | /workspace/0.chip_sw_alert_handler_ping_timeout/latest |
| Test location | /workspace/coverage/default/0.chip_sw_alert_handler_reverse_ping_in_deep_sleep.2493459650 |
| Short name | T156 |
| Test name | |
| Test status | |
| Simulation time | 256075211188 ps |
| CPU time | 11406.8 seconds |
| Started | Jun 23 07:51:44 PM PDT 24 |
| Finished | Jun 23 11:01:53 PM PDT 24 |
| Peak memory | 608652 kb |
| Host | smart-00a81e75-b240-4e98-a437-6145fbf04a66 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=300_000_000 +sw_build_device=sim_dv +sw_images=alert_handler_reverse_ping_in_deep_sleep_test:1:n ew_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2493459650 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_alert_handler_reverse_ping_in_deep_sleep.2493459650 |
| Directory | /workspace/0.chip_sw_alert_handler_reverse_ping_in_deep_sleep/latest |
| Test location | /workspace/coverage/default/0.chip_sw_alert_test.4082032729 |
| Short name | T60 |
| Test name | |
| Test status | |
| Simulation time | 2401457510 ps |
| CPU time | 229.62 seconds |
| Started | Jun 23 07:50:21 PM PDT 24 |
| Finished | Jun 23 07:54:11 PM PDT 24 |
| Peak memory | 606952 kb |
| Host | smart-0e95c155-9d45-440d-aa63-1a149cf5959e |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=alert_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4082032729 -assert nopostproc +UVM_TESTNAME=chip_ba se_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 0.chip_sw_alert_test.4082032729 |
| Directory | /workspace/0.chip_sw_alert_test/latest |
| Test location | /workspace/coverage/default/0.chip_sw_aon_timer_irq.3117409283 |
| Short name | T351 |
| Test name | |
| Test status | |
| Simulation time | 3033840836 ps |
| CPU time | 418.65 seconds |
| Started | Jun 23 07:49:35 PM PDT 24 |
| Finished | Jun 23 07:56:34 PM PDT 24 |
| Peak memory | 606752 kb |
| Host | smart-c7eb0095-da17-4766-a978-3eb2c5b880a8 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=aon_timer_irq_test:1:new_rules,test_rom:0 +cdc_instrumentati on_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3117409283 - assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co verage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_aon_timer_irq.3117409283 |
| Directory | /workspace/0.chip_sw_aon_timer_irq/latest |
| Test location | /workspace/coverage/default/0.chip_sw_aon_timer_sleep_wdog_sleep_pause.3867030469 |
| Short name | T1345 |
| Test name | |
| Test status | |
| Simulation time | 7033265680 ps |
| CPU time | 584.36 seconds |
| Started | Jun 23 07:53:54 PM PDT 24 |
| Finished | Jun 23 08:03:38 PM PDT 24 |
| Peak memory | 607420 kb |
| Host | smart-e87cb04f-f5e2-4ee1-9340-fa9fd6338fa9 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=aon_timer_sleep_wdog_sleep_pause_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=3867030469 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_aon_timer_sleep_wdog_sleep_pause.3867030469 |
| Directory | /workspace/0.chip_sw_aon_timer_sleep_wdog_sleep_pause/latest |
| Test location | /workspace/coverage/default/0.chip_sw_aon_timer_smoketest.1681439861 |
| Short name | T1168 |
| Test name | |
| Test status | |
| Simulation time | 2775067066 ps |
| CPU time | 257.34 seconds |
| Started | Jun 23 07:53:51 PM PDT 24 |
| Finished | Jun 23 07:58:09 PM PDT 24 |
| Peak memory | 606916 kb |
| Host | smart-349e65bb-1864-4641-8303-4b7a549cbc9e |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=aon_timer_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1681439861 -assert nopostproc +UVM_TESTNAM E=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 0.chip_sw_aon_timer_smoketest.1681439861 |
| Directory | /workspace/0.chip_sw_aon_timer_smoketest/latest |
| Test location | /workspace/coverage/default/0.chip_sw_aon_timer_wdog_bite_reset.1268628359 |
| Short name | T1210 |
| Test name | |
| Test status | |
| Simulation time | 7339073628 ps |
| CPU time | 663.12 seconds |
| Started | Jun 23 07:49:36 PM PDT 24 |
| Finished | Jun 23 08:00:39 PM PDT 24 |
| Peak memory | 608480 kb |
| Host | smart-2b313871-35a8-4605-bee1-4d95d13bbfcb |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=aon_timer_wdog_bite_reset_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 1268628359 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_aon_timer_wdog_bite_reset.1268628359 |
| Directory | /workspace/0.chip_sw_aon_timer_wdog_bite_reset/latest |
| Test location | /workspace/coverage/default/0.chip_sw_aon_timer_wdog_lc_escalate.1237781199 |
| Short name | T1092 |
| Test name | |
| Test status | |
| Simulation time | 5213582220 ps |
| CPU time | 558.68 seconds |
| Started | Jun 23 07:50:49 PM PDT 24 |
| Finished | Jun 23 08:00:08 PM PDT 24 |
| Peak memory | 608528 kb |
| Host | smart-2061e854-bf67-4af3-96cc-6c2b6a5f3cf4 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=aon_timer_wdog_lc_escalate_test:1:new_rules,test_rom:0 +cdc_ instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed =1237781199 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_aon_timer_wdog_lc_escalate.1237781199 |
| Directory | /workspace/0.chip_sw_aon_timer_wdog_lc_escalate/latest |
| Test location | /workspace/coverage/default/0.chip_sw_ast_clk_outputs.762132923 |
| Short name | T1014 |
| Test name | |
| Test status | |
| Simulation time | 8680493312 ps |
| CPU time | 1000.2 seconds |
| Started | Jun 23 07:53:43 PM PDT 24 |
| Finished | Jun 23 08:10:24 PM PDT 24 |
| Peak memory | 613860 kb |
| Host | smart-f2864049-bb1d-4169-8618-45cd321c4bde |
| User | root |
| Command | /workspace/default/simv +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=ast_clk_outs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled= 1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=762132923 -assert nopos tproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_ast_clk_outputs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov erage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_ast_clk_outputs.762132923 |
| Directory | /workspace/0.chip_sw_ast_clk_outputs/latest |
| Test location | /workspace/coverage/default/0.chip_sw_ast_clk_rst_inputs.3974010274 |
| Short name | T136 |
| Test name | |
| Test status | |
| Simulation time | 18777149045 ps |
| CPU time | 2784.58 seconds |
| Started | Jun 23 07:50:49 PM PDT 24 |
| Finished | Jun 23 08:37:15 PM PDT 24 |
| Peak memory | 608464 kb |
| Host | smart-5c9e6c02-c4cc-43ff-9944-d77b17faf58c |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=200_000_000 +sw_build_device=sim_dv +sw_images=ast_clk_rst_inputs:1:new_rules,test_rom:0 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3974010274 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_ast_clk_rst_inputs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_ast_clk_rst_inputs.3974010274 |
| Directory | /workspace/0.chip_sw_ast_clk_rst_inputs/latest |
| Test location | /workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_lc.3659392892 |
| Short name | T1281 |
| Test name | |
| Test status | |
| Simulation time | 5943136167 ps |
| CPU time | 441.2 seconds |
| Started | Jun 23 07:52:16 PM PDT 24 |
| Finished | Jun 23 07:59:38 PM PDT 24 |
| Peak memory | 619000 kb |
| Host | smart-0642a21a-5941-487d-b258-afe33f0f239e |
| User | root |
| Command | /workspace/default/simv +chip_clock_source=ChipClockSourceExternal48Mhz +sw_build_device=sim_dv +sw_images=clkmgr_external_clk_src_for_lc_test:1:new_r ules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim .tcl +ntb_random_seed=3659392892 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_transition_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_clkmgr_external_clk_src_for_lc.3659392892 |
| Directory | /workspace/0.chip_sw_clkmgr_external_clk_src_for_lc/latest |
| Test location | /workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_fast_dev.1502224679 |
| Short name | T1221 |
| Test name | |
| Test status | |
| Simulation time | 4524907832 ps |
| CPU time | 695.57 seconds |
| Started | Jun 23 07:50:42 PM PDT 24 |
| Finished | Jun 23 08:02:18 PM PDT 24 |
| Peak memory | 611536 kb |
| Host | smart-87eb1f62-89be-477d-b519-c81aafda38d3 |
| User | root |
| Command | /workspace/default/simv +chip_clock_source=ChipClockSourceExternal96Mhz +calibrate_usb_clk=1 +src_dec_state=DecLcStDev +sw_build_device=sim_dv +sw_ima ges=clkmgr_external_clk_src_for_sw_fast_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1502224679 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ =chip_sw_lc_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_c lkmgr_external_clk_src_for_sw_fast_dev.1502224679 |
| Directory | /workspace/0.chip_sw_clkmgr_external_clk_src_for_sw_fast_dev/latest |
| Test location | /workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_fast_rma.1870891512 |
| Short name | T937 |
| Test name | |
| Test status | |
| Simulation time | 4484362856 ps |
| CPU time | 662.81 seconds |
| Started | Jun 23 07:50:47 PM PDT 24 |
| Finished | Jun 23 08:01:50 PM PDT 24 |
| Peak memory | 611448 kb |
| Host | smart-b4db00f4-8a69-42fc-82c7-e4673f101e90 |
| User | root |
| Command | /workspace/default/simv +chip_clock_source=ChipClockSourceExternal96Mhz +calibrate_usb_clk=1 +src_dec_state=DecLcStRma +sw_build_device=sim_dv +sw_ima ges=clkmgr_external_clk_src_for_sw_fast_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1870891512 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ =chip_sw_lc_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_c lkmgr_external_clk_src_for_sw_fast_rma.1870891512 |
| Directory | /workspace/0.chip_sw_clkmgr_external_clk_src_for_sw_fast_rma/latest |
| Test location | /workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0.7112867 |
| Short name | T1128 |
| Test name | |
| Test status | |
| Simulation time | 4067391608 ps |
| CPU time | 703.64 seconds |
| Started | Jun 23 07:55:12 PM PDT 24 |
| Finished | Jun 23 08:06:57 PM PDT 24 |
| Peak memory | 611792 kb |
| Host | smart-ced6ddf7-df24-482c-91ec-ee56dbf56561 |
| User | root |
| Command | /workspace/default/simv +chip_clock_source=ChipClockSourceExternal96Mhz +calibrate_usb_clk=1 +src_dec_state=DecLcStTestUnlocked0 +sw_build_device=sim_ dv +sw_images=clkmgr_external_clk_src_for_sw_fast_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=7112867 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_T EST_SEQ=chip_sw_lc_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.ch ip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0.7112867 |
| Directory | /workspace/0.chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0/latest |
| Test location | /workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_slow_dev.2655521822 |
| Short name | T1232 |
| Test name | |
| Test status | |
| Simulation time | 5349262360 ps |
| CPU time | 624.28 seconds |
| Started | Jun 23 07:51:42 PM PDT 24 |
| Finished | Jun 23 08:02:06 PM PDT 24 |
| Peak memory | 610264 kb |
| Host | smart-c98db971-e06f-4c0f-b784-b87abbe5871c |
| User | root |
| Command | /workspace/default/simv +chip_clock_source=ChipClockSourceExternal48Mhz +calibrate_usb_clk=1 +src_dec_state=DecLcStDev +sw_build_device=sim_dv +sw_ima ges=clkmgr_external_clk_src_for_sw_slow_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2655521822 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ =chip_sw_lc_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_c lkmgr_external_clk_src_for_sw_slow_dev.2655521822 |
| Directory | /workspace/0.chip_sw_clkmgr_external_clk_src_for_sw_slow_dev/latest |
| Test location | /workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0.1514826973 |
| Short name | T371 |
| Test name | |
| Test status | |
| Simulation time | 4826176378 ps |
| CPU time | 745.23 seconds |
| Started | Jun 23 07:51:31 PM PDT 24 |
| Finished | Jun 23 08:03:57 PM PDT 24 |
| Peak memory | 611600 kb |
| Host | smart-6128f9a0-cb15-4d89-99e0-e9e62886ceb6 |
| User | root |
| Command | /workspace/default/simv +chip_clock_source=ChipClockSourceExternal48Mhz +calibrate_usb_clk=1 +src_dec_state=DecLcStTestUnlocked0 +sw_build_device=sim_ dv +sw_images=clkmgr_external_clk_src_for_sw_slow_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1514826973 -assert nopostproc +UVM_TESTNAME=chip_base_test +UV M_TEST_SEQ=chip_sw_lc_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0 .chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0.1514826973 |
| Directory | /workspace/0.chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0/latest |
| Test location | /workspace/coverage/default/0.chip_sw_clkmgr_jitter.112607697 |
| Short name | T990 |
| Test name | |
| Test status | |
| Simulation time | 2676406054 ps |
| CPU time | 307.52 seconds |
| Started | Jun 23 07:49:58 PM PDT 24 |
| Finished | Jun 23 07:55:06 PM PDT 24 |
| Peak memory | 607576 kb |
| Host | smart-eb1153ad-9d8e-4082-9d54-2f601fbeae7f |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_jitter_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=112607697 -assert nopostproc +UVM_TESTNAME= chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/ null -cm_name 0.chip_sw_clkmgr_jitter.112607697 |
| Directory | /workspace/0.chip_sw_clkmgr_jitter/latest |
| Test location | /workspace/coverage/default/0.chip_sw_clkmgr_jitter_frequency.790151158 |
| Short name | T1331 |
| Test name | |
| Test status | |
| Simulation time | 3174893756 ps |
| CPU time | 564.52 seconds |
| Started | Jun 23 07:53:55 PM PDT 24 |
| Finished | Jun 23 08:03:20 PM PDT 24 |
| Peak memory | 606928 kb |
| Host | smart-e05471b7-2e06-4afd-96ee-8c9085baa1b3 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_jitter_frequency_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=790151158 -assert nopostproc +UVM _TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm _log /dev/null -cm_name 0.chip_sw_clkmgr_jitter_frequency.790151158 |
| Directory | /workspace/0.chip_sw_clkmgr_jitter_frequency/latest |
| Test location | /workspace/coverage/default/0.chip_sw_clkmgr_jitter_reduced_freq.2611150418 |
| Short name | T111 |
| Test name | |
| Test status | |
| Simulation time | 2794846387 ps |
| CPU time | 236.11 seconds |
| Started | Jun 23 07:51:24 PM PDT 24 |
| Finished | Jun 23 07:55:21 PM PDT 24 |
| Peak memory | 607572 kb |
| Host | smart-158d7f98-aa9f-47f0-b4b2-436f57523bf2 |
| User | root |
| Command | /workspace/default/simv +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=clkmgr_jitter_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2611150418 -assert nop ostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def ault.vdb -cm_log /dev/null -cm_name 0.chip_sw_clkmgr_jitter_reduced_freq.2611150418 |
| Directory | /workspace/0.chip_sw_clkmgr_jitter_reduced_freq/latest |
| Test location | /workspace/coverage/default/0.chip_sw_clkmgr_off_aes_trans.3025812839 |
| Short name | T187 |
| Test name | |
| Test status | |
| Simulation time | 5698795036 ps |
| CPU time | 369.15 seconds |
| Started | Jun 23 07:52:16 PM PDT 24 |
| Finished | Jun 23 07:58:26 PM PDT 24 |
| Peak memory | 607824 kb |
| Host | smart-901ae3b5-bf07-42f7-8bff-8e4e18dbfc8c |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_off_aes_trans_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3025812839 -assert nopostproc +UVM_T ESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l og /dev/null -cm_name 0.chip_sw_clkmgr_off_aes_trans.3025812839 |
| Directory | /workspace/0.chip_sw_clkmgr_off_aes_trans/latest |
| Test location | /workspace/coverage/default/0.chip_sw_clkmgr_off_hmac_trans.609166923 |
| Short name | T924 |
| Test name | |
| Test status | |
| Simulation time | 4039034316 ps |
| CPU time | 551.22 seconds |
| Started | Jun 23 07:50:47 PM PDT 24 |
| Finished | Jun 23 07:59:59 PM PDT 24 |
| Peak memory | 606976 kb |
| Host | smart-cf515179-8822-4e0c-ac85-641c67b911a8 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_off_hmac_trans_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=609166923 -assert nopostproc +UVM_T ESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l og /dev/null -cm_name 0.chip_sw_clkmgr_off_hmac_trans.609166923 |
| Directory | /workspace/0.chip_sw_clkmgr_off_hmac_trans/latest |
| Test location | /workspace/coverage/default/0.chip_sw_clkmgr_off_kmac_trans.1159288511 |
| Short name | T1165 |
| Test name | |
| Test status | |
| Simulation time | 5732210836 ps |
| CPU time | 596.75 seconds |
| Started | Jun 23 07:51:01 PM PDT 24 |
| Finished | Jun 23 08:00:58 PM PDT 24 |
| Peak memory | 607140 kb |
| Host | smart-6471477c-3276-4972-a764-385cfcde8ea4 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_off_kmac_trans_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1159288511 -assert nopostproc +UVM_ TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_ log /dev/null -cm_name 0.chip_sw_clkmgr_off_kmac_trans.1159288511 |
| Directory | /workspace/0.chip_sw_clkmgr_off_kmac_trans/latest |
| Test location | /workspace/coverage/default/0.chip_sw_clkmgr_off_otbn_trans.3696944828 |
| Short name | T921 |
| Test name | |
| Test status | |
| Simulation time | 4567152856 ps |
| CPU time | 502.65 seconds |
| Started | Jun 23 07:51:41 PM PDT 24 |
| Finished | Jun 23 08:00:04 PM PDT 24 |
| Peak memory | 607740 kb |
| Host | smart-d463fee8-a572-4648-90cd-3ae387b0684a |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_off_otbn_trans_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3696944828 -assert nopostproc +UVM_ TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_ log /dev/null -cm_name 0.chip_sw_clkmgr_off_otbn_trans.3696944828 |
| Directory | /workspace/0.chip_sw_clkmgr_off_otbn_trans/latest |
| Test location | /workspace/coverage/default/0.chip_sw_clkmgr_off_peri.2262781256 |
| Short name | T239 |
| Test name | |
| Test status | |
| Simulation time | 11486254920 ps |
| CPU time | 1874.12 seconds |
| Started | Jun 23 07:53:10 PM PDT 24 |
| Finished | Jun 23 08:24:25 PM PDT 24 |
| Peak memory | 608460 kb |
| Host | smart-75bc18ad-5233-473f-a456-50b72c6ad9c3 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=30_000_000 +sw_build_device=sim_dv +sw_images=clkmgr_off_peri_test:1:new_rules,test_rom:0 +cdc_instrumenta tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2262781256 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/ coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_clkmgr_off_peri.2262781256 |
| Directory | /workspace/0.chip_sw_clkmgr_off_peri/latest |
| Test location | /workspace/coverage/default/0.chip_sw_clkmgr_reset_frequency.2456091035 |
| Short name | T263 |
| Test name | |
| Test status | |
| Simulation time | 3572142957 ps |
| CPU time | 514.02 seconds |
| Started | Jun 23 07:50:08 PM PDT 24 |
| Finished | Jun 23 07:58:42 PM PDT 24 |
| Peak memory | 606956 kb |
| Host | smart-9452de07-4100-4759-bc64-4d8386585935 |
| User | root |
| Command | /workspace/default/simv +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=clkmgr_reset_frequency_test:1:new_rules,test_rom:0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2456091035 -a ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov erage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_clkmgr_reset_frequency.2456091035 |
| Directory | /workspace/0.chip_sw_clkmgr_reset_frequency/latest |
| Test location | /workspace/coverage/default/0.chip_sw_clkmgr_sleep_frequency.144734071 |
| Short name | T931 |
| Test name | |
| Test status | |
| Simulation time | 4560458744 ps |
| CPU time | 672.39 seconds |
| Started | Jun 23 07:52:19 PM PDT 24 |
| Finished | Jun 23 08:03:32 PM PDT 24 |
| Peak memory | 607996 kb |
| Host | smart-cc1ed113-04a9-40b8-97ff-62a315ce5b8c |
| User | root |
| Command | /workspace/default/simv +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=clkmgr_sleep_frequency_test:1:new_rules,test_rom:0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=144734071 -as sert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove rage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_clkmgr_sleep_frequency.144734071 |
| Directory | /workspace/0.chip_sw_clkmgr_sleep_frequency/latest |
| Test location | /workspace/coverage/default/0.chip_sw_clkmgr_smoketest.1240213420 |
| Short name | T18 |
| Test name | |
| Test status | |
| Simulation time | 3136854400 ps |
| CPU time | 228.67 seconds |
| Started | Jun 23 07:56:28 PM PDT 24 |
| Finished | Jun 23 08:00:17 PM PDT 24 |
| Peak memory | 607576 kb |
| Host | smart-8842326c-b6c0-42cc-bc5a-3f8b86bda6df |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1240213420 -assert nopostproc +UVM_TESTNAME=c hip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n ull -cm_name 0.chip_sw_clkmgr_smoketest.1240213420 |
| Directory | /workspace/0.chip_sw_clkmgr_smoketest/latest |
| Test location | /workspace/coverage/default/0.chip_sw_csrng_edn_concurrency.2935704775 |
| Short name | T957 |
| Test name | |
| Test status | |
| Simulation time | 16273539410 ps |
| CPU time | 4592.59 seconds |
| Started | Jun 23 07:52:37 PM PDT 24 |
| Finished | Jun 23 09:09:11 PM PDT 24 |
| Peak memory | 607024 kb |
| Host | smart-490d7e82-1d1b-4a31-a5ff-99b39d8f3f1f |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=140_000_000 +rng_srate_value_min=15 +rng_srate_value_max=20 +accelerate_cold_power_up_time=3 +accelerate_r egulators_power_up_time=2 +sw_build_device=sim_dv +sw_images=csrng_edn_concurrency_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2935704775 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd b -cm_log /dev/null -cm_name 0.chip_sw_csrng_edn_concurrency.2935704775 |
| Directory | /workspace/0.chip_sw_csrng_edn_concurrency/latest |
| Test location | /workspace/coverage/default/0.chip_sw_csrng_fuse_en_sw_app_read_test.1329884285 |
| Short name | T1322 |
| Test name | |
| Test status | |
| Simulation time | 5495786456 ps |
| CPU time | 614.66 seconds |
| Started | Jun 23 07:50:27 PM PDT 24 |
| Finished | Jun 23 08:00:44 PM PDT 24 |
| Peak memory | 608136 kb |
| Host | smart-5e011cfb-6f02-4932-990e-f654d328c24f |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=15_000_000 +sw_build_device=sim_dv +sw_images=csrng_fuse_en_sw_app_read:1:new_rules,test_rom:0 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13298 84285 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_entropy_src_fuse_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_csrng_fuse_en_sw_app_read_test.1329884285 |
| Directory | /workspace/0.chip_sw_csrng_fuse_en_sw_app_read_test/latest |
| Test location | /workspace/coverage/default/0.chip_sw_csrng_kat_test.1254610896 |
| Short name | T1361 |
| Test name | |
| Test status | |
| Simulation time | 2229062096 ps |
| CPU time | 264.03 seconds |
| Started | Jun 23 07:51:06 PM PDT 24 |
| Finished | Jun 23 07:55:31 PM PDT 24 |
| Peak memory | 606932 kb |
| Host | smart-905437f1-4798-4943-a62a-b5f7089830ba |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=csrng_kat_test:1:new_rules,test_rom:0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1254610896 -asse rt nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera ge/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_csrng_kat_test.1254610896 |
| Directory | /workspace/0.chip_sw_csrng_kat_test/latest |
| Test location | /workspace/coverage/default/0.chip_sw_csrng_lc_hw_debug_en_test.4075584065 |
| Short name | T1027 |
| Test name | |
| Test status | |
| Simulation time | 6220812000 ps |
| CPU time | 817.78 seconds |
| Started | Jun 23 07:51:43 PM PDT 24 |
| Finished | Jun 23 08:05:21 PM PDT 24 |
| Peak memory | 607740 kb |
| Host | smart-d3835b78-1989-4418-88f8-d1d50f8124a2 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=15_000_000 +rng_srate_value_min=15 +use_otp_image=OtpTypeLcStTestUnlocked0 +sw_build_device=sim_dv +sw_ima ges=csrng_lc_hw_debug_en_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4075584065 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_csrng_ lc_hw_debug_en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_csr ng_lc_hw_debug_en_test.4075584065 |
| Directory | /workspace/0.chip_sw_csrng_lc_hw_debug_en_test/latest |
| Test location | /workspace/coverage/default/0.chip_sw_csrng_smoketest.1463523862 |
| Short name | T1273 |
| Test name | |
| Test status | |
| Simulation time | 2883975600 ps |
| CPU time | 237.69 seconds |
| Started | Jun 23 07:52:31 PM PDT 24 |
| Finished | Jun 23 07:56:29 PM PDT 24 |
| Peak memory | 606852 kb |
| Host | smart-2dcace8f-cdda-4eb0-bd5e-bb13eab13535 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=csrng_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1463523862 -assert nopostproc +UVM_TESTNAME=ch ip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu ll -cm_name 0.chip_sw_csrng_smoketest.1463523862 |
| Directory | /workspace/0.chip_sw_csrng_smoketest/latest |
| Test location | /workspace/coverage/default/0.chip_sw_data_integrity_escalation.3594035845 |
| Short name | T270 |
| Test name | |
| Test status | |
| Simulation time | 6131926412 ps |
| CPU time | 1060.81 seconds |
| Started | Jun 23 07:48:09 PM PDT 24 |
| Finished | Jun 23 08:05:51 PM PDT 24 |
| Peak memory | 608476 kb |
| Host | smart-69a1f5a8-b026-4a9a-802c-292d12d178a8 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=data_integrity_escalation_reset_test:1:new_rules,test_ro m:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=3594035845 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_data_integrity_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_data_integrity_escalation.3594035845 |
| Directory | /workspace/0.chip_sw_data_integrity_escalation/latest |
| Test location | /workspace/coverage/default/0.chip_sw_edn_auto_mode.2442696711 |
| Short name | T1038 |
| Test name | |
| Test status | |
| Simulation time | 5071449216 ps |
| CPU time | 1230.83 seconds |
| Started | Jun 23 07:52:16 PM PDT 24 |
| Finished | Jun 23 08:12:47 PM PDT 24 |
| Peak memory | 607240 kb |
| Host | smart-9969cb59-9bba-4a78-8367-1ecea33b633e |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +rng_srate_value=5 +accelerate_cold_power_up_time=3 +accelerate_regulators_power_up_time=2 +sw_ build_device=sim_dv +sw_images=edn_auto_mode:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2442696711 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ =chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_edn_ auto_mode.2442696711 |
| Directory | /workspace/0.chip_sw_edn_auto_mode/latest |
| Test location | /workspace/coverage/default/0.chip_sw_edn_entropy_reqs_jitter.3690717566 |
| Short name | T425 |
| Test name | |
| Test status | |
| Simulation time | 7585996781 ps |
| CPU time | 1182.87 seconds |
| Started | Jun 23 07:50:23 PM PDT 24 |
| Finished | Jun 23 08:10:06 PM PDT 24 |
| Peak memory | 608524 kb |
| Host | smart-d17e9e0f-d025-4fb8-80d9-b91e2d078c07 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=15000000 +rng_srate_value_min=15 +rng_srate_value_max=30 +en_jitter=1 +sw_build_device=sim_dv +sw_images=e ntropy_src_edn_reqs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3690717566 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_edn_entropy_reqs_jitter.3690717566 |
| Directory | /workspace/0.chip_sw_edn_entropy_reqs_jitter/latest |
| Test location | /workspace/coverage/default/0.chip_sw_edn_kat.1028734396 |
| Short name | T1078 |
| Test name | |
| Test status | |
| Simulation time | 3499621560 ps |
| CPU time | 530.87 seconds |
| Started | Jun 23 07:53:34 PM PDT 24 |
| Finished | Jun 23 08:02:26 PM PDT 24 |
| Peak memory | 613344 kb |
| Host | smart-0e9e59ff-2a51-4122-89f0-de351af7b109 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +rng_srate_value=5 +disable_assert_edn_output_diff_from_prev=1 +accelerate_cold_power_up_time=3 +accelerate_regulators_power_up_time=2 +sw_build_device=sim_dv +sw_images=edn_kat:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1028734396 -assert nopostproc +UVM _TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm _log /dev/null -cm_name 0.chip_sw_edn_kat.1028734396 |
| Directory | /workspace/0.chip_sw_edn_kat/latest |
| Test location | /workspace/coverage/default/0.chip_sw_edn_sw_mode.194976417 |
| Short name | T1124 |
| Test name | |
| Test status | |
| Simulation time | 10115802650 ps |
| CPU time | 2438.47 seconds |
| Started | Jun 23 07:52:20 PM PDT 24 |
| Finished | Jun 23 08:32:59 PM PDT 24 |
| Peak memory | 607652 kb |
| Host | smart-b483e567-277c-4333-ba6e-903e7595e517 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=edn_sw_mode:1:new_rules,test_rom:0 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=194976417 -assert n opostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/d efault.vdb -cm_log /dev/null -cm_name 0.chip_sw_edn_sw_mode.194976417 |
| Directory | /workspace/0.chip_sw_edn_sw_mode/latest |
| Test location | /workspace/coverage/default/0.chip_sw_entropy_src_ast_rng_req.1865830492 |
| Short name | T914 |
| Test name | |
| Test status | |
| Simulation time | 2867390060 ps |
| CPU time | 191.65 seconds |
| Started | Jun 23 07:54:57 PM PDT 24 |
| Finished | Jun 23 07:58:09 PM PDT 24 |
| Peak memory | 607472 kb |
| Host | smart-a9089891-caed-4e7c-8bc9-621fef409043 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=15_000_000 +sw_build_device=sim_dv +sw_images=entropy_src_ast_rng_req_test:1:new_rules,test_rom:0 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18 65830492 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_entropy_src_ast_rng_req.1865830492 |
| Directory | /workspace/0.chip_sw_entropy_src_ast_rng_req/latest |
| Test location | /workspace/coverage/default/0.chip_sw_entropy_src_kat_test.1933468786 |
| Short name | T1053 |
| Test name | |
| Test status | |
| Simulation time | 2460541704 ps |
| CPU time | 226.82 seconds |
| Started | Jun 23 07:50:19 PM PDT 24 |
| Finished | Jun 23 07:54:06 PM PDT 24 |
| Peak memory | 606848 kb |
| Host | smart-9f83354e-7df8-40b3-8a43-a5e822099903 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=entropy_src_kat_test:1:new_rules,test_rom:0 +cdc_instrumenta tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1933468786 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/ coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_entropy_src_kat_test.1933468786 |
| Directory | /workspace/0.chip_sw_entropy_src_kat_test/latest |
| Test location | /workspace/coverage/default/0.chip_sw_entropy_src_smoketest.1654099453 |
| Short name | T1009 |
| Test name | |
| Test status | |
| Simulation time | 2906319760 ps |
| CPU time | 450.63 seconds |
| Started | Jun 23 07:54:53 PM PDT 24 |
| Finished | Jun 23 08:02:25 PM PDT 24 |
| Peak memory | 607588 kb |
| Host | smart-c6469ee2-90cd-4263-bbf5-be7c08f46e0c |
| User | root |
| Command | /workspace/default/simv +rng_srate_value_min=15 +rng_srate_value_max=30 +sw_build_device=sim_dv +sw_images=entropy_src_smoketest:1:new_rules,test_rom: 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand om_seed=1654099453 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_entropy_src_smoketest.1654099453 |
| Directory | /workspace/0.chip_sw_entropy_src_smoketest/latest |
| Test location | /workspace/coverage/default/0.chip_sw_example_concurrency.1491799065 |
| Short name | T996 |
| Test name | |
| Test status | |
| Simulation time | 2262598096 ps |
| CPU time | 263.16 seconds |
| Started | Jun 23 07:49:55 PM PDT 24 |
| Finished | Jun 23 07:54:19 PM PDT 24 |
| Peak memory | 606852 kb |
| Host | smart-d3d594f1-9aeb-45c9-91a0-ddcfd3debdfa |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=example_concurrency_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1491799065 -assert nopostproc +UVM_TE STNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo g /dev/null -cm_name 0.chip_sw_example_concurrency.1491799065 |
| Directory | /workspace/0.chip_sw_example_concurrency/latest |
| Test location | /workspace/coverage/default/0.chip_sw_example_flash.1609772428 |
| Short name | T292 |
| Test name | |
| Test status | |
| Simulation time | 2882487150 ps |
| CPU time | 388.61 seconds |
| Started | Jun 23 07:50:57 PM PDT 24 |
| Finished | Jun 23 07:57:27 PM PDT 24 |
| Peak memory | 607096 kb |
| Host | smart-bd98f14b-0691-4dab-b68c-a8c14dfdba03 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=example_test_from_flash:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1609772428 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_example_flash.1609772428 |
| Directory | /workspace/0.chip_sw_example_flash/latest |
| Test location | /workspace/coverage/default/0.chip_sw_example_manufacturer.2107005480 |
| Short name | T1306 |
| Test name | |
| Test status | |
| Simulation time | 2727991728 ps |
| CPU time | 191.51 seconds |
| Started | Jun 23 07:48:06 PM PDT 24 |
| Finished | Jun 23 07:51:19 PM PDT 24 |
| Peak memory | 606936 kb |
| Host | smart-ca93bbe8-df2b-473a-bfe5-5219e03d775f |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=example_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2107005480 -assert nopostproc +UVM_TESTNAME=chip_ base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_example_manufacturer.2107005480 |
| Directory | /workspace/0.chip_sw_example_manufacturer/latest |
| Test location | /workspace/coverage/default/0.chip_sw_example_rom.4056326231 |
| Short name | T942 |
| Test name | |
| Test status | |
| Simulation time | 2705591940 ps |
| CPU time | 129.58 seconds |
| Started | Jun 23 07:47:19 PM PDT 24 |
| Finished | Jun 23 07:49:29 PM PDT 24 |
| Peak memory | 607600 kb |
| Host | smart-4c077780-923d-4ff9-889f-0db15f783628 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:test_in_rom:new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4056326231 -assert nopostproc +UVM_TEST NAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_example_rom.4056326231 |
| Directory | /workspace/0.chip_sw_example_rom/latest |
| Test location | /workspace/coverage/default/0.chip_sw_exit_test_unlocked_bootstrap.3032822130 |
| Short name | T151 |
| Test name | |
| Test status | |
| Simulation time | 58428127193 ps |
| CPU time | 10668.8 seconds |
| Started | Jun 23 07:49:00 PM PDT 24 |
| Finished | Jun 23 10:46:51 PM PDT 24 |
| Peak memory | 623348 kb |
| Host | smart-1968317a-e7b1-4644-bc5a-c3f02a965920 |
| User | root |
| Command | /workspace/default/simv +flash_program_latency=5 +sw_test_timeout_ns=150_000_000 +sw_build_device=sim_dv +sw_images=exit_test_unlocked_bootstrap:1:new _rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/s im.tcl +ntb_random_seed=3032822130 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_exit_test_unlocked_bootstrap_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_exit_test_unlocked_bootstrap.3032822130 |
| Directory | /workspace/0.chip_sw_exit_test_unlocked_bootstrap/latest |
| Test location | /workspace/coverage/default/0.chip_sw_flash_crash_alert.2987402794 |
| Short name | T1076 |
| Test name | |
| Test status | |
| Simulation time | 4849190096 ps |
| CPU time | 566.48 seconds |
| Started | Jun 23 07:51:47 PM PDT 24 |
| Finished | Jun 23 08:01:14 PM PDT 24 |
| Peak memory | 608832 kb |
| Host | smart-ba7ba7fc-90ea-47f9-a76b-c2fd707d938c |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=8_000_000 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1: new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tool s/sim.tcl +ntb_random_seed=2987402794 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_flash_host_gnt_err_inj_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_flash_crash_alert.2987402794 |
| Directory | /workspace/0.chip_sw_flash_crash_alert/latest |
| Test location | /workspace/coverage/default/0.chip_sw_flash_ctrl_access.1140957707 |
| Short name | T1112 |
| Test name | |
| Test status | |
| Simulation time | 6073245868 ps |
| CPU time | 1159.01 seconds |
| Started | Jun 23 07:51:34 PM PDT 24 |
| Finished | Jun 23 08:10:54 PM PDT 24 |
| Peak memory | 606900 kb |
| Host | smart-69cdc7bd-67e5-4a51-b0c3-d70b14da0d8b |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=flash_ctrl_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1140957707 -assert nopostproc +UVM_TESTNAME=ch ip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu ll -cm_name 0.chip_sw_flash_ctrl_access.1140957707 |
| Directory | /workspace/0.chip_sw_flash_ctrl_access/latest |
| Test location | /workspace/coverage/default/0.chip_sw_flash_ctrl_access_jitter_en.847712887 |
| Short name | T1329 |
| Test name | |
| Test status | |
| Simulation time | 5847302897 ps |
| CPU time | 1088.91 seconds |
| Started | Jun 23 07:48:43 PM PDT 24 |
| Finished | Jun 23 08:06:52 PM PDT 24 |
| Peak memory | 606940 kb |
| Host | smart-43911c38-f959-4843-9bab-c2f20ada9da7 |
| User | root |
| Command | /workspace/default/simv +en_jitter=1 +sw_build_device=sim_dv +sw_images=flash_ctrl_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=847712887 -assert nopostproc +UVM _TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm _log /dev/null -cm_name 0.chip_sw_flash_ctrl_access_jitter_en.847712887 |
| Directory | /workspace/0.chip_sw_flash_ctrl_access_jitter_en/latest |
| Test location | /workspace/coverage/default/0.chip_sw_flash_ctrl_access_jitter_en_reduced_freq.283559549 |
| Short name | T1111 |
| Test name | |
| Test status | |
| Simulation time | 7217685003 ps |
| CPU time | 1281.53 seconds |
| Started | Jun 23 07:52:24 PM PDT 24 |
| Finished | Jun 23 08:13:46 PM PDT 24 |
| Peak memory | 607012 kb |
| Host | smart-f5617e5e-e673-4dc4-ac99-d8eab1883218 |
| User | root |
| Command | /workspace/default/simv +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=flash_ctrl_test:1:new_rules,test_rom:0 +cdc_instrumentati on_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=283559549 -a ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov erage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_flash_ctrl_access_jitter_en_reduced_freq.283559549 |
| Directory | /workspace/0.chip_sw_flash_ctrl_access_jitter_en_reduced_freq/latest |
| Test location | /workspace/coverage/default/0.chip_sw_flash_ctrl_clock_freqs.253982950 |
| Short name | T920 |
| Test name | |
| Test status | |
| Simulation time | 5641326242 ps |
| CPU time | 1049.11 seconds |
| Started | Jun 23 07:49:27 PM PDT 24 |
| Finished | Jun 23 08:06:56 PM PDT 24 |
| Peak memory | 606936 kb |
| Host | smart-a91c9935-5a92-491f-afaf-3bcf062d4ab2 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=flash_ctrl_clock_freqs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=253982950 -assert nopostproc +UVM_ TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_ log /dev/null -cm_name 0.chip_sw_flash_ctrl_clock_freqs.253982950 |
| Directory | /workspace/0.chip_sw_flash_ctrl_clock_freqs/latest |
| Test location | /workspace/coverage/default/0.chip_sw_flash_ctrl_idle_low_power.1253133335 |
| Short name | T987 |
| Test name | |
| Test status | |
| Simulation time | 3273131064 ps |
| CPU time | 310.32 seconds |
| Started | Jun 23 07:53:43 PM PDT 24 |
| Finished | Jun 23 07:58:54 PM PDT 24 |
| Peak memory | 607232 kb |
| Host | smart-1aad70af-ae6a-40b2-9369-f334787a2e76 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=flash_ctrl_idle_low_power_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1253133335 -assert nopostproc + UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_flash_ctrl_idle_low_power.1253133335 |
| Directory | /workspace/0.chip_sw_flash_ctrl_idle_low_power/latest |
| Test location | /workspace/coverage/default/0.chip_sw_flash_ctrl_lc_rw_en.1662230447 |
| Short name | T234 |
| Test name | |
| Test status | |
| Simulation time | 5552941052 ps |
| CPU time | 559.73 seconds |
| Started | Jun 23 07:48:56 PM PDT 24 |
| Finished | Jun 23 07:58:16 PM PDT 24 |
| Peak memory | 608232 kb |
| Host | smart-1284cbf6-c49f-40b2-b131-6121088b05a3 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=flash_ctrl_lc_rw_en_test:1:new_rules,test_rom:0 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16 62230447 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_flash_ctrl_lc_rw_en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_flash_ctrl_lc_rw_en.1662230447 |
| Directory | /workspace/0.chip_sw_flash_ctrl_lc_rw_en/latest |
| Test location | /workspace/coverage/default/0.chip_sw_flash_ctrl_mem_protection.1401790133 |
| Short name | T1214 |
| Test name | |
| Test status | |
| Simulation time | 5267263420 ps |
| CPU time | 1019.06 seconds |
| Started | Jun 23 07:51:46 PM PDT 24 |
| Finished | Jun 23 08:08:45 PM PDT 24 |
| Peak memory | 607128 kb |
| Host | smart-f78460d6-16b8-4cef-9240-1dd7dab69f9f |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=flash_ctrl_mem_protection_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1401790133 -assert nopostproc + UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_flash_ctrl_mem_protection.1401790133 |
| Directory | /workspace/0.chip_sw_flash_ctrl_mem_protection/latest |
| Test location | /workspace/coverage/default/0.chip_sw_flash_ctrl_ops.2220097966 |
| Short name | T1353 |
| Test name | |
| Test status | |
| Simulation time | 3961065920 ps |
| CPU time | 710.97 seconds |
| Started | Jun 23 07:49:24 PM PDT 24 |
| Finished | Jun 23 08:01:15 PM PDT 24 |
| Peak memory | 606864 kb |
| Host | smart-539bf1bf-5bb7-4aac-a1ee-82b17173c898 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=50_000_000 +sw_build_device=sim_dv +sw_images=flash_ctrl_ops_test:1:new_rules,test_rom:0 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2220097966 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/c overage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_flash_ctrl_ops.2220097966 |
| Directory | /workspace/0.chip_sw_flash_ctrl_ops/latest |
| Test location | /workspace/coverage/default/0.chip_sw_flash_ctrl_ops_jitter_en.2530366058 |
| Short name | T332 |
| Test name | |
| Test status | |
| Simulation time | 4619299364 ps |
| CPU time | 741.91 seconds |
| Started | Jun 23 07:50:55 PM PDT 24 |
| Finished | Jun 23 08:03:17 PM PDT 24 |
| Peak memory | 607756 kb |
| Host | smart-aa3c318d-7dc9-45d0-9afa-deecf33b6455 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=50_000_000 +en_jitter=1 +sw_build_device=sim_dv +sw_images=flash_ctrl_ops_test:1:new_rules,test_rom:0 +cdc _instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see d=2530366058 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_flash_ctrl_ops_jitter_en.2530366058 |
| Directory | /workspace/0.chip_sw_flash_ctrl_ops_jitter_en/latest |
| Test location | /workspace/coverage/default/0.chip_sw_flash_ctrl_ops_jitter_en_reduced_freq.1592532293 |
| Short name | T1355 |
| Test name | |
| Test status | |
| Simulation time | 4790673007 ps |
| CPU time | 751.85 seconds |
| Started | Jun 23 07:52:04 PM PDT 24 |
| Finished | Jun 23 08:04:36 PM PDT 24 |
| Peak memory | 607152 kb |
| Host | smart-2315b018-b3c8-480e-8e4b-473fc339088c |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=50_000_000 +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=flash_ctrl_ops_test:1:new_ rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si m.tcl +ntb_random_seed=1592532293 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_flash_ctrl_ops_jitter_en_reduced_freq.1592532293 |
| Directory | /workspace/0.chip_sw_flash_ctrl_ops_jitter_en_reduced_freq/latest |
| Test location | /workspace/coverage/default/0.chip_sw_flash_ctrl_write_clear.3277381054 |
| Short name | T287 |
| Test name | |
| Test status | |
| Simulation time | 3247732280 ps |
| CPU time | 314.98 seconds |
| Started | Jun 23 07:55:31 PM PDT 24 |
| Finished | Jun 23 08:00:46 PM PDT 24 |
| Peak memory | 607232 kb |
| Host | smart-6fbeda6b-b47a-4221-851d-3a6b0b208ec8 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=8_000_000 +sw_build_device=sim_dv +sw_images=flash_ctrl_write_clear_test:1:new_rules,test_rom:0 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3277381 054 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_flash_ctrl_write_clear.3277381054 |
| Directory | /workspace/0.chip_sw_flash_ctrl_write_clear/latest |
| Test location | /workspace/coverage/default/0.chip_sw_flash_init.2431965513 |
| Short name | T236 |
| Test name | |
| Test status | |
| Simulation time | 22284981460 ps |
| CPU time | 1934.38 seconds |
| Started | Jun 23 07:52:02 PM PDT 24 |
| Finished | Jun 23 08:24:18 PM PDT 24 |
| Peak memory | 610360 kb |
| Host | smart-c50ba90e-93a1-405d-bc33-d7611d21141f |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=25_000_000 +sw_build_device=sim_dv +sw_images=flash_init_test:0:test_in_rom:new_rules +cdc_instrumentation _enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2431965513 -as sert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_flash_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac e/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_flash_init.2431965513 |
| Directory | /workspace/0.chip_sw_flash_init/latest |
| Test location | /workspace/coverage/default/0.chip_sw_flash_scrambling_smoketest.783807772 |
| Short name | T1001 |
| Test name | |
| Test status | |
| Simulation time | 3047787826 ps |
| CPU time | 272.4 seconds |
| Started | Jun 23 07:57:12 PM PDT 24 |
| Finished | Jun 23 08:01:45 PM PDT 24 |
| Peak memory | 607948 kb |
| Host | smart-087d07f4-439a-40a6-a5ef-e52f76e3652b |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=flash_scrambling_smoketest:1:new_rules,flash_scrambling_smoket est_otp_img_rma:4,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=783807772 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_flash_scrambling_smoketest.783807772 |
| Directory | /workspace/0.chip_sw_flash_scrambling_smoketest/latest |
| Test location | /workspace/coverage/default/0.chip_sw_gpio_smoketest.961048903 |
| Short name | T1284 |
| Test name | |
| Test status | |
| Simulation time | 2668691510 ps |
| CPU time | 224.42 seconds |
| Started | Jun 23 07:54:36 PM PDT 24 |
| Finished | Jun 23 07:58:21 PM PDT 24 |
| Peak memory | 607864 kb |
| Host | smart-11fe9941-2ce2-4a0d-a071-93917a3b0d65 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=gpio_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=961048903 -assert nopostproc +UVM_TESTNAME=chip _base_test +UVM_TEST_SEQ=chip_sw_gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 0.chip_sw_gpio_smoketest.961048903 |
| Directory | /workspace/0.chip_sw_gpio_smoketest/latest |
| Test location | /workspace/coverage/default/0.chip_sw_hmac_enc.2589004746 |
| Short name | T284 |
| Test name | |
| Test status | |
| Simulation time | 2961619924 ps |
| CPU time | 252.8 seconds |
| Started | Jun 23 07:50:31 PM PDT 24 |
| Finished | Jun 23 07:54:44 PM PDT 24 |
| Peak memory | 607836 kb |
| Host | smart-87b9b1ee-4ec1-419b-867f-792510587667 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=hmac_enc_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2589004746 -assert nopostproc +UVM_TESTNAME=chip _base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_hmac_enc.2589004746 |
| Directory | /workspace/0.chip_sw_hmac_enc/latest |
| Test location | /workspace/coverage/default/0.chip_sw_hmac_enc_idle.3790903198 |
| Short name | T1083 |
| Test name | |
| Test status | |
| Simulation time | 3606226176 ps |
| CPU time | 341.93 seconds |
| Started | Jun 23 07:50:25 PM PDT 24 |
| Finished | Jun 23 07:56:08 PM PDT 24 |
| Peak memory | 607580 kb |
| Host | smart-5d0b7b08-9c7d-40d2-a24b-7f44f5936448 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=hmac_enc_idle_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3790903198 -assert nopostproc +UVM_TESTNAME =chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 0.chip_sw_hmac_enc_idle.3790903198 |
| Directory | /workspace/0.chip_sw_hmac_enc_idle/latest |
| Test location | /workspace/coverage/default/0.chip_sw_hmac_enc_jitter_en_reduced_freq.1067457542 |
| Short name | T354 |
| Test name | |
| Test status | |
| Simulation time | 2789816788 ps |
| CPU time | 314.53 seconds |
| Started | Jun 23 07:54:53 PM PDT 24 |
| Finished | Jun 23 08:00:09 PM PDT 24 |
| Peak memory | 606920 kb |
| Host | smart-06c22307-c667-4035-86c8-07e3a1119f44 |
| User | root |
| Command | /workspace/default/simv +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=hmac_enc_test:1:new_rules,test_rom:0 +cdc_instrumentation _enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1067457542 -as sert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove rage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_hmac_enc_jitter_en_reduced_freq.1067457542 |
| Directory | /workspace/0.chip_sw_hmac_enc_jitter_en_reduced_freq/latest |
| Test location | /workspace/coverage/default/0.chip_sw_hmac_multistream.2104429311 |
| Short name | T1265 |
| Test name | |
| Test status | |
| Simulation time | 6996800484 ps |
| CPU time | 1742.75 seconds |
| Started | Jun 23 07:50:06 PM PDT 24 |
| Finished | Jun 23 08:19:10 PM PDT 24 |
| Peak memory | 607520 kb |
| Host | smart-ac201076-c21a-49f7-92cc-2f901f63f3c3 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=hmac_multistream_functest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2104429311 -assert nopostproc +UVM_T ESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l og /dev/null -cm_name 0.chip_sw_hmac_multistream.2104429311 |
| Directory | /workspace/0.chip_sw_hmac_multistream/latest |
| Test location | /workspace/coverage/default/0.chip_sw_hmac_oneshot.2754997214 |
| Short name | T948 |
| Test name | |
| Test status | |
| Simulation time | 2693772002 ps |
| CPU time | 396.3 seconds |
| Started | Jun 23 07:52:25 PM PDT 24 |
| Finished | Jun 23 07:59:02 PM PDT 24 |
| Peak memory | 607600 kb |
| Host | smart-314387d9-bf63-4f7e-af63-78985fabe9ae |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=hmac_functest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2754997214 -assert nopostproc +UVM_TESTNAME=chip _base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_hmac_oneshot.2754997214 |
| Directory | /workspace/0.chip_sw_hmac_oneshot/latest |
| Test location | /workspace/coverage/default/0.chip_sw_hmac_smoketest.2920377546 |
| Short name | T1105 |
| Test name | |
| Test status | |
| Simulation time | 2778155940 ps |
| CPU time | 338.67 seconds |
| Started | Jun 23 07:53:57 PM PDT 24 |
| Finished | Jun 23 07:59:36 PM PDT 24 |
| Peak memory | 606856 kb |
| Host | smart-e4aa585d-55fc-4c21-857c-c8730499499e |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=hmac_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2920377546 -assert nopostproc +UVM_TESTNAME=chi p_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul l -cm_name 0.chip_sw_hmac_smoketest.2920377546 |
| Directory | /workspace/0.chip_sw_hmac_smoketest/latest |
| Test location | /workspace/coverage/default/0.chip_sw_i2c_device_tx_rx.1394430817 |
| Short name | T1141 |
| Test name | |
| Test status | |
| Simulation time | 4067131428 ps |
| CPU time | 442.06 seconds |
| Started | Jun 23 07:50:09 PM PDT 24 |
| Finished | Jun 23 07:57:33 PM PDT 24 |
| Peak memory | 608016 kb |
| Host | smart-b1e6e2af-bf6b-4f86-8898-a155b11f957d |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=i2c_device_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1394430817 -assert nopostproc +UVM_TESTN AME=chip_base_test +UVM_TEST_SEQ=chip_sw_i2c_device_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v db -cm_log /dev/null -cm_name 0.chip_sw_i2c_device_tx_rx.1394430817 |
| Directory | /workspace/0.chip_sw_i2c_device_tx_rx/latest |
| Test location | /workspace/coverage/default/0.chip_sw_i2c_host_tx_rx.1510950629 |
| Short name | T208 |
| Test name | |
| Test status | |
| Simulation time | 4187263208 ps |
| CPU time | 825.28 seconds |
| Started | Jun 23 07:49:05 PM PDT 24 |
| Finished | Jun 23 08:02:51 PM PDT 24 |
| Peak memory | 607072 kb |
| Host | smart-7fb2f9e6-e6af-4aa4-ba0a-b9b8a8fb0d05 |
| User | root |
| Command | /workspace/default/simv +i2c_idx=0 +sw_build_device=sim_dv +sw_images=i2c_host_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1510950629 -assert nopostproc + UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_i2c_host_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de fault.vdb -cm_log /dev/null -cm_name 0.chip_sw_i2c_host_tx_rx.1510950629 |
| Directory | /workspace/0.chip_sw_i2c_host_tx_rx/latest |
| Test location | /workspace/coverage/default/0.chip_sw_inject_scramble_seed.2513474277 |
| Short name | T1031 |
| Test name | |
| Test status | |
| Simulation time | 64591546326 ps |
| CPU time | 10972.6 seconds |
| Started | Jun 23 07:48:31 PM PDT 24 |
| Finished | Jun 23 10:51:26 PM PDT 24 |
| Peak memory | 616844 kb |
| Host | smart-f63cc894-ea0c-4f9a-b6e3-95fc49171819 |
| User | root |
| Command | /workspace/default/simv +lc_at_prod=1 +flash_program_latency=5 +sw_test_timeout_ns=150_000_000 +sw_build_device=sim_dv +sw_images=inject_scramble_seed :1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=2513474277 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_inject_scramble_seed_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_inject_scramble_seed.2513474277 |
| Directory | /workspace/0.chip_sw_inject_scramble_seed/latest |
| Test location | /workspace/coverage/default/0.chip_sw_keymgr_key_derivation.3557418272 |
| Short name | T226 |
| Test name | |
| Test status | |
| Simulation time | 10545196504 ps |
| CPU time | 2336.6 seconds |
| Started | Jun 23 07:54:05 PM PDT 24 |
| Finished | Jun 23 08:33:02 PM PDT 24 |
| Peak memory | 614408 kb |
| Host | smart-9587d92f-59b4-473e-9cc8-9616211f7f47 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=20_000_000 +sw_build_device=sim_dv +sw_images=keymgr_key_derivation_test:1:new_rules,test_rom:0 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3557 418272 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_keymgr_key_derivation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_keymgr_key_derivation.3557418272 |
| Directory | /workspace/0.chip_sw_keymgr_key_derivation/latest |
| Test location | /workspace/coverage/default/0.chip_sw_keymgr_key_derivation_jitter_en.3109038846 |
| Short name | T1097 |
| Test name | |
| Test status | |
| Simulation time | 11723485573 ps |
| CPU time | 2402.3 seconds |
| Started | Jun 23 07:49:53 PM PDT 24 |
| Finished | Jun 23 08:29:56 PM PDT 24 |
| Peak memory | 614424 kb |
| Host | smart-04667842-4b1a-4caf-b922-9169050047d7 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=20_000_000 +en_jitter=1 +sw_build_device=sim_dv +sw_images=keymgr_key_derivation_test:1:new_rules,test_rom :0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=3109038846 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_keymgr_key_derivation_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_keymgr_key_derivation_jitter_en.3109038846 |
| Directory | /workspace/0.chip_sw_keymgr_key_derivation_jitter_en/latest |
| Test location | /workspace/coverage/default/0.chip_sw_keymgr_key_derivation_jitter_en_reduced_freq.1819581038 |
| Short name | T1187 |
| Test name | |
| Test status | |
| Simulation time | 11068848232 ps |
| CPU time | 1985.14 seconds |
| Started | Jun 23 07:50:48 PM PDT 24 |
| Finished | Jun 23 08:23:54 PM PDT 24 |
| Peak memory | 615496 kb |
| Host | smart-c1f35a46-6c90-44d3-8f55-ed2e22d44ca0 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=20_000_000 +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=keymgr_key_derivation_test :1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=1819581038 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_keymgr_key_derivation_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_keymgr_key_derivation_jitter_en _reduced_freq.1819581038 |
| Directory | /workspace/0.chip_sw_keymgr_key_derivation_jitter_en_reduced_freq/latest |
| Test location | /workspace/coverage/default/0.chip_sw_keymgr_key_derivation_prod.1978126927 |
| Short name | T1339 |
| Test name | |
| Test status | |
| Simulation time | 9763322672 ps |
| CPU time | 2172.66 seconds |
| Started | Jun 23 07:52:28 PM PDT 24 |
| Finished | Jun 23 08:28:41 PM PDT 24 |
| Peak memory | 615468 kb |
| Host | smart-8383849c-9c56-436e-938b-9791d6cb5962 |
| User | root |
| Command | /workspace/default/simv +lc_at_prod=1 +sw_test_timeout_ns=20_000_000 +sw_build_device=sim_dv +sw_images=keymgr_key_derivation_test:1:new_rules,test_ro m:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=1978126927 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_keymgr_key_derivation_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_keymgr_key_derivation_prod.1978126927 |
| Directory | /workspace/0.chip_sw_keymgr_key_derivation_prod/latest |
| Test location | /workspace/coverage/default/0.chip_sw_keymgr_sideload_aes.3136353832 |
| Short name | T225 |
| Test name | |
| Test status | |
| Simulation time | 6787678984 ps |
| CPU time | 1220.01 seconds |
| Started | Jun 23 07:50:15 PM PDT 24 |
| Finished | Jun 23 08:10:35 PM PDT 24 |
| Peak memory | 607840 kb |
| Host | smart-e2a0ccfd-0110-435e-bddc-4591dd6454db |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=20_000_000 +sw_build_device=sim_dv +sw_images=keymgr_sideload_aes_test:1:new_rules,test_rom:0 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=313635 3832 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_keymgr_sideload_aes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_keymgr_sideload_aes.3136353832 |
| Directory | /workspace/0.chip_sw_keymgr_sideload_aes/latest |
| Test location | /workspace/coverage/default/0.chip_sw_kmac_app_rom.2813503374 |
| Short name | T397 |
| Test name | |
| Test status | |
| Simulation time | 3030596082 ps |
| CPU time | 266.53 seconds |
| Started | Jun 23 07:52:08 PM PDT 24 |
| Finished | Jun 23 07:56:36 PM PDT 24 |
| Peak memory | 606856 kb |
| Host | smart-f4e77287-f1d0-4a54-9aab-836d89af4026 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=kmac_app_rom_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2813503374 -assert nopostproc +UVM_TESTNAME= chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/ null -cm_name 0.chip_sw_kmac_app_rom.2813503374 |
| Directory | /workspace/0.chip_sw_kmac_app_rom/latest |
| Test location | /workspace/coverage/default/0.chip_sw_kmac_entropy.2587749886 |
| Short name | T1278 |
| Test name | |
| Test status | |
| Simulation time | 3178858980 ps |
| CPU time | 277.57 seconds |
| Started | Jun 23 07:50:04 PM PDT 24 |
| Finished | Jun 23 07:54:42 PM PDT 24 |
| Peak memory | 607816 kb |
| Host | smart-f0406d3f-a1d2-4d32-a51f-6cb6dccebab1 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=kmac_entropy_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2587749886 -assert nopostproc +UVM_TESTNAME= chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/ null -cm_name 0.chip_sw_kmac_entropy.2587749886 |
| Directory | /workspace/0.chip_sw_kmac_entropy/latest |
| Test location | /workspace/coverage/default/0.chip_sw_kmac_idle.3984083112 |
| Short name | T306 |
| Test name | |
| Test status | |
| Simulation time | 2728492392 ps |
| CPU time | 257 seconds |
| Started | Jun 23 07:50:55 PM PDT 24 |
| Finished | Jun 23 07:55:12 PM PDT 24 |
| Peak memory | 607368 kb |
| Host | smart-c6167a4e-7f09-4a02-b3bc-397556d7a0f0 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=kmac_idle_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3984083112 -assert nopostproc +UVM_TESTNAME=chi p_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul l -cm_name 0.chip_sw_kmac_idle.3984083112 |
| Directory | /workspace/0.chip_sw_kmac_idle/latest |
| Test location | /workspace/coverage/default/0.chip_sw_kmac_mode_cshake.2132975824 |
| Short name | T1219 |
| Test name | |
| Test status | |
| Simulation time | 2819079908 ps |
| CPU time | 276.05 seconds |
| Started | Jun 23 07:51:03 PM PDT 24 |
| Finished | Jun 23 07:55:39 PM PDT 24 |
| Peak memory | 606828 kb |
| Host | smart-ecf8cdfd-1ff8-457d-834a-eb3e06c2c365 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=kmac_mode_cshake_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2132975824 -assert nopostproc +UVM_TESTN AME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log / dev/null -cm_name 0.chip_sw_kmac_mode_cshake.2132975824 |
| Directory | /workspace/0.chip_sw_kmac_mode_cshake/latest |
| Test location | /workspace/coverage/default/0.chip_sw_kmac_mode_kmac.3807448884 |
| Short name | T1239 |
| Test name | |
| Test status | |
| Simulation time | 3244709176 ps |
| CPU time | 263.81 seconds |
| Started | Jun 23 07:54:54 PM PDT 24 |
| Finished | Jun 23 07:59:18 PM PDT 24 |
| Peak memory | 606860 kb |
| Host | smart-817ff6a2-f41e-4d42-a7b4-78e5d441b6f0 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=kmac_mode_kmac_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3807448884 -assert nopostproc +UVM_TESTNAM E=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 0.chip_sw_kmac_mode_kmac.3807448884 |
| Directory | /workspace/0.chip_sw_kmac_mode_kmac/latest |
| Test location | /workspace/coverage/default/0.chip_sw_kmac_mode_kmac_jitter_en.1370032592 |
| Short name | T923 |
| Test name | |
| Test status | |
| Simulation time | 3171835618 ps |
| CPU time | 279.1 seconds |
| Started | Jun 23 07:50:48 PM PDT 24 |
| Finished | Jun 23 07:55:28 PM PDT 24 |
| Peak memory | 607820 kb |
| Host | smart-9fd805b5-3e85-4bbe-a2d6-ba302c9493cd |
| User | root |
| Command | /workspace/default/simv +en_jitter=1 +sw_build_device=sim_dv +sw_images=kmac_mode_kmac_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1370032592 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd b -cm_log /dev/null -cm_name 0.chip_sw_kmac_mode_kmac_jitter_en.1370032592 |
| Directory | /workspace/0.chip_sw_kmac_mode_kmac_jitter_en/latest |
| Test location | /workspace/coverage/default/0.chip_sw_kmac_mode_kmac_jitter_en_reduced_freq.2141647163 |
| Short name | T1156 |
| Test name | |
| Test status | |
| Simulation time | 3310237178 ps |
| CPU time | 281.03 seconds |
| Started | Jun 23 07:51:47 PM PDT 24 |
| Finished | Jun 23 07:56:29 PM PDT 24 |
| Peak memory | 606804 kb |
| Host | smart-f74e3a91-52df-4205-8163-5ac244fd55a0 |
| User | root |
| Command | /workspace/default/simv +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=kmac_mode_kmac_test:1:new_rules,test_rom:0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21416471 63 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac e/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_kmac_mode_kmac_jitter_en_reduced_freq.2141647163 |
| Directory | /workspace/0.chip_sw_kmac_mode_kmac_jitter_en_reduced_freq/latest |
| Test location | /workspace/coverage/default/0.chip_sw_kmac_smoketest.1261395442 |
| Short name | T1044 |
| Test name | |
| Test status | |
| Simulation time | 3050868392 ps |
| CPU time | 271.77 seconds |
| Started | Jun 23 07:54:32 PM PDT 24 |
| Finished | Jun 23 07:59:04 PM PDT 24 |
| Peak memory | 606836 kb |
| Host | smart-e7cd2434-2512-4bd5-9ce0-b04da70ae51c |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=kmac_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1261395442 -assert nopostproc +UVM_TESTNAME=chi p_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul l -cm_name 0.chip_sw_kmac_smoketest.1261395442 |
| Directory | /workspace/0.chip_sw_kmac_smoketest/latest |
| Test location | /workspace/coverage/default/0.chip_sw_lc_ctrl_otp_hw_cfg0.142083179 |
| Short name | T1041 |
| Test name | |
| Test status | |
| Simulation time | 2703482200 ps |
| CPU time | 388.66 seconds |
| Started | Jun 23 07:49:08 PM PDT 24 |
| Finished | Jun 23 07:55:37 PM PDT 24 |
| Peak memory | 606916 kb |
| Host | smart-dc3429f7-8bda-4d86-9f9e-faa1aa4e27e6 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=lc_ctrl_otp_hw_cfg0_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=142083179 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_lc_ctrl_otp_hw_cfg0.142083179 |
| Directory | /workspace/0.chip_sw_lc_ctrl_otp_hw_cfg0/latest |
| Test location | /workspace/coverage/default/0.chip_sw_lc_ctrl_rand_to_scrap.1055446685 |
| Short name | T264 |
| Test name | |
| Test status | |
| Simulation time | 3596340525 ps |
| CPU time | 155.23 seconds |
| Started | Jun 23 07:48:56 PM PDT 24 |
| Finished | Jun 23 07:51:31 PM PDT 24 |
| Peak memory | 617660 kb |
| Host | smart-2f4393e2-b8f8-43bc-affe-5d843517eee3 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=lc_ctrl_scrap_test:1:new_rules,test_rom:0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10554466 85 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_scrap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_lc_ctrl_rand_to_scrap.1055446685 |
| Directory | /workspace/0.chip_sw_lc_ctrl_rand_to_scrap/latest |
| Test location | /workspace/coverage/default/0.chip_sw_lc_ctrl_raw_to_scrap.3442978856 |
| Short name | T115 |
| Test name | |
| Test status | |
| Simulation time | 2807061638 ps |
| CPU time | 134.41 seconds |
| Started | Jun 23 07:49:16 PM PDT 24 |
| Finished | Jun 23 07:51:31 PM PDT 24 |
| Peak memory | 617600 kb |
| Host | smart-967c4b78-20a6-4aab-b045-30d46e37b995 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +src_dec_state=DecLcStRaw +sw_build_device=sim_dv +sw_images=lc_ctrl_scrap_test:1:new_rules ,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3442978856 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_scrap_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_lc_ctrl_raw_to_scrap.3442978856 |
| Directory | /workspace/0.chip_sw_lc_ctrl_raw_to_scrap/latest |
| Test location | /workspace/coverage/default/0.chip_sw_lc_ctrl_rma_to_scrap.3650171821 |
| Short name | T169 |
| Test name | |
| Test status | |
| Simulation time | 2320854133 ps |
| CPU time | 128.61 seconds |
| Started | Jun 23 07:49:11 PM PDT 24 |
| Finished | Jun 23 07:51:20 PM PDT 24 |
| Peak memory | 617900 kb |
| Host | smart-3b47e713-f4b8-48a0-b0b6-74a91a84bd80 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +src_dec_state=DecLcStRma +sw_build_device=sim_dv +sw_images=lc_ctrl_scrap_test:1:new_rules ,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3650171821 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_scrap_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_lc_ctrl_rma_to_scrap.3650171821 |
| Directory | /workspace/0.chip_sw_lc_ctrl_rma_to_scrap/latest |
| Test location | /workspace/coverage/default/0.chip_sw_lc_ctrl_test_locked0_to_scrap.1959931423 |
| Short name | T260 |
| Test name | |
| Test status | |
| Simulation time | 2690861866 ps |
| CPU time | 154.63 seconds |
| Started | Jun 23 07:51:36 PM PDT 24 |
| Finished | Jun 23 07:54:11 PM PDT 24 |
| Peak memory | 617644 kb |
| Host | smart-9190400e-f172-4444-9266-305853defa89 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +src_dec_state=DecLcStTestLocked0 +sw_build_device=sim_dv +sw_images=lc_ctrl_scrap_test:1:n ew_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1959931423 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_scrap_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_lc_ctrl_test_locked0_to_scrap.1959931423 |
| Directory | /workspace/0.chip_sw_lc_ctrl_test_locked0_to_scrap/latest |
| Test location | /workspace/coverage/default/0.chip_sw_lc_ctrl_transition.2799582994 |
| Short name | T1319 |
| Test name | |
| Test status | |
| Simulation time | 13068128112 ps |
| CPU time | 1081.23 seconds |
| Started | Jun 23 07:48:47 PM PDT 24 |
| Finished | Jun 23 08:06:49 PM PDT 24 |
| Peak memory | 621324 kb |
| Host | smart-f4fc777d-25ea-4354-a5c0-e1236966b1c4 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=lc_ctrl_transition_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2799582994 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_transition_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau lt.vdb -cm_log /dev/null -cm_name 0.chip_sw_lc_ctrl_transition.2799582994 |
| Directory | /workspace/0.chip_sw_lc_ctrl_transition/latest |
| Test location | /workspace/coverage/default/0.chip_sw_lc_ctrl_volatile_raw_unlock.4051078800 |
| Short name | T695 |
| Test name | |
| Test status | |
| Simulation time | 2027870803 ps |
| CPU time | 103.92 seconds |
| Started | Jun 23 07:50:06 PM PDT 24 |
| Finished | Jun 23 07:51:51 PM PDT 24 |
| Peak memory | 615528 kb |
| Host | smart-74af08d0-92d9-4c64-afaf-fc66da7566cb |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStRaw +exp_volatile_raw_unlock_en=0 +sw_build_device=sim_dv +sw_images=lc_ctrl_volatile_raw_unlock_tes t:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/ tools/sim.tcl +ntb_random_seed=4051078800 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_volatile_raw_unlock_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_lc_ctrl_volatile_raw_unlock.4051078800 |
| Directory | /workspace/0.chip_sw_lc_ctrl_volatile_raw_unlock/latest |
| Test location | /workspace/coverage/default/0.chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz.1435706350 |
| Short name | T116 |
| Test name | |
| Test status | |
| Simulation time | 2753180852 ps |
| CPU time | 120.84 seconds |
| Started | Jun 23 07:49:14 PM PDT 24 |
| Finished | Jun 23 07:51:15 PM PDT 24 |
| Peak memory | 613480 kb |
| Host | smart-a70c25f3-34b4-4c37-bec8-0c339b9315da |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStRaw +chip_clock_source=ChipClockSourceExternal48Mhz +exp_volatile_raw_unlock_en=0 +sw_build_device=s im_dv +sw_images=lc_ctrl_volatile_raw_unlock_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1435706350 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TES T_SEQ=chip_sw_lc_volatile_raw_unlock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz.1435706350 |
| Directory | /workspace/0.chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz/latest |
| Test location | /workspace/coverage/default/0.chip_sw_lc_walkthrough_prodend.606977518 |
| Short name | T963 |
| Test name | |
| Test status | |
| Simulation time | 9504294183 ps |
| CPU time | 954.4 seconds |
| Started | Jun 23 07:48:38 PM PDT 24 |
| Finished | Jun 23 08:04:33 PM PDT 24 |
| Peak memory | 615224 kb |
| Host | smart-e20b317a-bd8f-4766-a68c-163421dcc161 |
| User | root |
| Command | /workspace/default/simv +flash_program_latency=5 +use_otp_image=OtpTypeLcStRaw +dest_dec_state=DecLcStProdEnd +sw_build_device=sim_dv +sw_images=lc_wa lkthrough_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=606977518 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_walkthrough_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_lc_walkthrough_prodend.606977518 |
| Directory | /workspace/0.chip_sw_lc_walkthrough_prodend/latest |
| Test location | /workspace/coverage/default/0.chip_sw_lc_walkthrough_rma.1251449701 |
| Short name | T231 |
| Test name | |
| Test status | |
| Simulation time | 47352733012 ps |
| CPU time | 5881.75 seconds |
| Started | Jun 23 07:49:52 PM PDT 24 |
| Finished | Jun 23 09:27:55 PM PDT 24 |
| Peak memory | 615412 kb |
| Host | smart-cc991d7c-3a05-4f50-a703-cec7a7bc102d |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStRaw +dest_dec_state=DecLcStRma +flash_program_latency=5 +sw_test_timeout_ns=200_000_000 +sw_build_de vice=sim_dv +sw_images=lc_walkthrough_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1251449701 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=c hip_sw_lc_walkthrough_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip _sw_lc_walkthrough_rma.1251449701 |
| Directory | /workspace/0.chip_sw_lc_walkthrough_rma/latest |
| Test location | /workspace/coverage/default/0.chip_sw_lc_walkthrough_testunlocks.971987484 |
| Short name | T961 |
| Test name | |
| Test status | |
| Simulation time | 32594221247 ps |
| CPU time | 1999.1 seconds |
| Started | Jun 23 07:49:06 PM PDT 24 |
| Finished | Jun 23 08:22:26 PM PDT 24 |
| Peak memory | 615256 kb |
| Host | smart-7c2df7a8-1fb7-492c-8d66-ad0bb61347d6 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStRaw +dest_dec_state=DecLcStTestUnlock7 +sw_build_device=sim_dv +sw_images=lc_walkthrough_testunlocks _test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=971987484 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_walkthrough_testunlocks_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_lc_walkthrough_testunl ocks.971987484 |
| Directory | /workspace/0.chip_sw_lc_walkthrough_testunlocks/latest |
| Test location | /workspace/coverage/default/0.chip_sw_otbn_ecdsa_op_irq.2581183217 |
| Short name | T1347 |
| Test name | |
| Test status | |
| Simulation time | 16997104900 ps |
| CPU time | 3661.35 seconds |
| Started | Jun 23 07:50:04 PM PDT 24 |
| Finished | Jun 23 08:51:06 PM PDT 24 |
| Peak memory | 608268 kb |
| Host | smart-885450f7-0398-43e0-ae38-19e6839c7a81 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=28_000_000 +rng_srate_value=30 +sw_build_device=sim_dv +sw_images=otbn_ecdsa_op_irq_test:1:new_rules,test_ rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ random_seed=2581183217 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_otbn_ecdsa_op_irq.2581183217 |
| Directory | /workspace/0.chip_sw_otbn_ecdsa_op_irq/latest |
| Test location | /workspace/coverage/default/0.chip_sw_otbn_ecdsa_op_irq_jitter_en.1300630106 |
| Short name | T1077 |
| Test name | |
| Test status | |
| Simulation time | 18728886007 ps |
| CPU time | 4411.99 seconds |
| Started | Jun 23 07:50:46 PM PDT 24 |
| Finished | Jun 23 09:04:19 PM PDT 24 |
| Peak memory | 608276 kb |
| Host | smart-049885c9-c470-43c7-8ddd-ab8790bb0227 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=33_000_000 +rng_srate_value=30 +en_jitter=1 +sw_build_device=sim_dv +sw_images=otbn_ecdsa_op_irq_test:1:ne w_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/ sim.tcl +ntb_random_seed=1300630106 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tg l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_otbn_ecdsa_op_irq_jitter_en.1300630106 |
| Directory | /workspace/0.chip_sw_otbn_ecdsa_op_irq_jitter_en/latest |
| Test location | /workspace/coverage/default/0.chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq.2407551616 |
| Short name | T108 |
| Test name | |
| Test status | |
| Simulation time | 24852689530 ps |
| CPU time | 4013.25 seconds |
| Started | Jun 23 07:53:09 PM PDT 24 |
| Finished | Jun 23 09:00:02 PM PDT 24 |
| Peak memory | 607284 kb |
| Host | smart-2db50415-00b6-49d2-9330-887cfd2fe48d |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=33_000_000 +rng_srate_value=30 +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=otbn_e cdsa_op_irq_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/ repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2407551616 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_otbn_ecdsa_op_irq_jitter_en_redu ced_freq.2407551616 |
| Directory | /workspace/0.chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq/latest |
| Test location | /workspace/coverage/default/0.chip_sw_otbn_mem_scramble.1309779580 |
| Short name | T174 |
| Test name | |
| Test status | |
| Simulation time | 4026813944 ps |
| CPU time | 472.11 seconds |
| Started | Jun 23 07:51:06 PM PDT 24 |
| Finished | Jun 23 07:58:59 PM PDT 24 |
| Peak memory | 607064 kb |
| Host | smart-6a9117ee-6d19-4873-9f0e-315f33a67994 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=15_000_000 +en_scb_tl_err_chk=0 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=otbn _mem_scramble_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1309779580 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_otbn_mem_scramble.1309779580 |
| Directory | /workspace/0.chip_sw_otbn_mem_scramble/latest |
| Test location | /workspace/coverage/default/0.chip_sw_otbn_randomness.3544508001 |
| Short name | T1144 |
| Test name | |
| Test status | |
| Simulation time | 5597102312 ps |
| CPU time | 1030.93 seconds |
| Started | Jun 23 07:53:36 PM PDT 24 |
| Finished | Jun 23 08:10:48 PM PDT 24 |
| Peak memory | 608004 kb |
| Host | smart-f9bfa3de-1cae-4c86-9736-9c401e1b1088 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +rng_srate_value=30 +sw_build_device=sim_dv +sw_images=otbn_randomness_test:1:new_rules,test_ro m:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=3544508001 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_otbn_randomness.3544508001 |
| Directory | /workspace/0.chip_sw_otbn_randomness/latest |
| Test location | /workspace/coverage/default/0.chip_sw_otbn_smoketest.1907950417 |
| Short name | T149 |
| Test name | |
| Test status | |
| Simulation time | 6348623380 ps |
| CPU time | 1391.27 seconds |
| Started | Jun 23 07:56:47 PM PDT 24 |
| Finished | Jun 23 08:19:59 PM PDT 24 |
| Peak memory | 607044 kb |
| Host | smart-da958272-d182-4c7e-ab74-e545469023f7 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=otbn_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1907950417 -assert nopostproc +UVM_TESTNAME=chi p_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul l -cm_name 0.chip_sw_otbn_smoketest.1907950417 |
| Directory | /workspace/0.chip_sw_otbn_smoketest/latest |
| Test location | /workspace/coverage/default/0.chip_sw_otp_ctrl_dai_lock.291960218 |
| Short name | T1283 |
| Test name | |
| Test status | |
| Simulation time | 26846494896 ps |
| CPU time | 5986.16 seconds |
| Started | Jun 23 07:51:33 PM PDT 24 |
| Finished | Jun 23 09:31:20 PM PDT 24 |
| Peak memory | 607024 kb |
| Host | smart-2c8d45d2-fa2b-4fb5-9796-95ec94db79dc |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=30_000_000 +sw_build_device=sim_dv +sw_images=otp_ctrl_mem_access_test:1:new_rules,test_rom:0 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=291960 218 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_otp_ctrl_dai_lock.291960218 |
| Directory | /workspace/0.chip_sw_otp_ctrl_dai_lock/latest |
| Test location | /workspace/coverage/default/0.chip_sw_otp_ctrl_ecc_error_vendor_test.742859268 |
| Short name | T1308 |
| Test name | |
| Test status | |
| Simulation time | 2623211057 ps |
| CPU time | 190.51 seconds |
| Started | Jun 23 07:49:33 PM PDT 24 |
| Finished | Jun 23 07:52:44 PM PDT 24 |
| Peak memory | 607392 kb |
| Host | smart-84961115-dae9-406a-9119-9192b165c8ee |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=otp_ctrl_vendor_test_ecc_error_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=742859268 -assert nopostpr oc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_otp_ctrl_vendor_test_ecc_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_otp_ctrl_ecc_error_vendor_test.742859268 |
| Directory | /workspace/0.chip_sw_otp_ctrl_ecc_error_vendor_test/latest |
| Test location | /workspace/coverage/default/0.chip_sw_otp_ctrl_escalation.3265680409 |
| Short name | T1296 |
| Test name | |
| Test status | |
| Simulation time | 5874334512 ps |
| CPU time | 650.79 seconds |
| Started | Jun 23 07:49:29 PM PDT 24 |
| Finished | Jun 23 08:00:21 PM PDT 24 |
| Peak memory | 608756 kb |
| Host | smart-272f039b-e070-4e5b-8ee8-14bae490f74d |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 3265680409 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_otp_ctrl_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_otp_ctrl_escalation.3265680409 |
| Directory | /workspace/0.chip_sw_otp_ctrl_escalation/latest |
| Test location | /workspace/coverage/default/0.chip_sw_otp_ctrl_lc_signals_dev.2567384865 |
| Short name | T1194 |
| Test name | |
| Test status | |
| Simulation time | 8618145900 ps |
| CPU time | 1219.43 seconds |
| Started | Jun 23 07:53:30 PM PDT 24 |
| Finished | Jun 23 08:13:50 PM PDT 24 |
| Peak memory | 608276 kb |
| Host | smart-c52ac3a8-9fb1-4236-84b2-b2c37532d854 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStDev +otp_clear_secret2=1 +sw_build_device=sim_dv +sw_images=otp_ctrl_lc_signals_test:1:new_rules,tes t_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +nt b_random_seed=2567384865 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_otp_ctrl_lc_signals_dev.2567384865 |
| Directory | /workspace/0.chip_sw_otp_ctrl_lc_signals_dev/latest |
| Test location | /workspace/coverage/default/0.chip_sw_otp_ctrl_lc_signals_prod.4239682963 |
| Short name | T1185 |
| Test name | |
| Test status | |
| Simulation time | 9204714448 ps |
| CPU time | 1582.33 seconds |
| Started | Jun 23 07:52:08 PM PDT 24 |
| Finished | Jun 23 08:18:32 PM PDT 24 |
| Peak memory | 608524 kb |
| Host | smart-881da4d4-3e19-49d3-9c78-cdca34cedb3d |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStProd +otp_clear_secret2=1 +sw_build_device=sim_dv +sw_images=otp_ctrl_lc_signals_test:1:new_rules,te st_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n tb_random_seed=4239682963 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_otp_ctrl_lc_signals_prod.4239682963 |
| Directory | /workspace/0.chip_sw_otp_ctrl_lc_signals_prod/latest |
| Test location | /workspace/coverage/default/0.chip_sw_otp_ctrl_lc_signals_rma.4291140225 |
| Short name | T964 |
| Test name | |
| Test status | |
| Simulation time | 6961601756 ps |
| CPU time | 1648.37 seconds |
| Started | Jun 23 07:51:24 PM PDT 24 |
| Finished | Jun 23 08:18:53 PM PDT 24 |
| Peak memory | 607068 kb |
| Host | smart-16733f52-3aba-4046-ae10-61e4c6635995 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStRma +otp_clear_secret2=1 +sw_build_device=sim_dv +sw_images=otp_ctrl_lc_signals_test:1:new_rules,tes t_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +nt b_random_seed=4291140225 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_otp_ctrl_lc_signals_rma.4291140225 |
| Directory | /workspace/0.chip_sw_otp_ctrl_lc_signals_rma/latest |
| Test location | /workspace/coverage/default/0.chip_sw_otp_ctrl_lc_signals_test_unlocked0.3508184694 |
| Short name | T1075 |
| Test name | |
| Test status | |
| Simulation time | 4430561512 ps |
| CPU time | 703.6 seconds |
| Started | Jun 23 07:48:46 PM PDT 24 |
| Finished | Jun 23 08:00:30 PM PDT 24 |
| Peak memory | 606976 kb |
| Host | smart-da16954d-9205-4196-bd15-101af5a7a369 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStTestUnlocked0 +otp_clear_secret2=1 +sw_build_device=sim_dv +sw_images=otp_ctrl_lc_signals_test:1:new _rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/s im.tcl +ntb_random_seed=3508184694 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_otp_ctrl_lc_signals_test_unlocked0.3508184694 |
| Directory | /workspace/0.chip_sw_otp_ctrl_lc_signals_test_unlocked0/latest |
| Test location | /workspace/coverage/default/0.chip_sw_otp_ctrl_smoketest.3843482148 |
| Short name | T936 |
| Test name | |
| Test status | |
| Simulation time | 2712636008 ps |
| CPU time | 256.32 seconds |
| Started | Jun 23 07:53:55 PM PDT 24 |
| Finished | Jun 23 07:58:12 PM PDT 24 |
| Peak memory | 606920 kb |
| Host | smart-d5b1be01-4114-49f9-afaf-e0dc7a8bb792 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=otp_ctrl_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3843482148 -assert nopostproc +UVM_TESTNAME =chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 0.chip_sw_otp_ctrl_smoketest.3843482148 |
| Directory | /workspace/0.chip_sw_otp_ctrl_smoketest/latest |
| Test location | /workspace/coverage/default/0.chip_sw_power_sleep_load.2865230364 |
| Short name | T1300 |
| Test name | |
| Test status | |
| Simulation time | 9512724358 ps |
| CPU time | 548.51 seconds |
| Started | Jun 23 07:51:16 PM PDT 24 |
| Finished | Jun 23 08:00:25 PM PDT 24 |
| Peak memory | 608636 kb |
| Host | smart-1ad760b8-8d1b-48c3-9df0-820917c31164 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=chip_power_sleep_load:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2865230364 -assert nopostproc +UVM_TESTN AME=chip_base_test +UVM_TEST_SEQ=chip_sw_power_sleep_load_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v db -cm_log /dev/null -cm_name 0.chip_sw_power_sleep_load.2865230364 |
| Directory | /workspace/0.chip_sw_power_sleep_load/latest |
| Test location | /workspace/coverage/default/0.chip_sw_pwrmgr_all_reset_reqs.298109574 |
| Short name | T998 |
| Test name | |
| Test status | |
| Simulation time | 9932316911 ps |
| CPU time | 1864.79 seconds |
| Started | Jun 23 07:49:34 PM PDT 24 |
| Finished | Jun 23 08:20:40 PM PDT 24 |
| Peak memory | 608700 kb |
| Host | smart-d8f32899-8e8b-4003-9406-b56a36e8c65a |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=50_000_000 +sw_build_device=sim_dv +sw_images=pwrmgr_all_reset_reqs_test:1:new_rules,test_rom:0 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2981 09574 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_deep_sleep_all_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_all_reset_reqs.298109574 |
| Directory | /workspace/0.chip_sw_pwrmgr_all_reset_reqs/latest |
| Test location | /workspace/coverage/default/0.chip_sw_pwrmgr_b2b_sleep_reset_req.321342670 |
| Short name | T1039 |
| Test name | |
| Test status | |
| Simulation time | 20861397606 ps |
| CPU time | 1829.4 seconds |
| Started | Jun 23 07:52:30 PM PDT 24 |
| Finished | Jun 23 08:23:00 PM PDT 24 |
| Peak memory | 607464 kb |
| Host | smart-10f8d67e-09e0-4f8a-bc00-4f3ed9e04a1c |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=35_000_000 +sw_build_device=sim_dv +sw_images=pwrmgr_b2b_sleep_reset_test:1:new_rules,test_rom:0 +cdc_inst rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=321 342670 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_repeat_reset_wkup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_b2b_sleep_reset_req.321342670 |
| Directory | /workspace/0.chip_sw_pwrmgr_b2b_sleep_reset_req/latest |
| Test location | /workspace/coverage/default/0.chip_sw_pwrmgr_deep_sleep_all_reset_reqs.2291115550 |
| Short name | T1327 |
| Test name | |
| Test status | |
| Simulation time | 12812675665 ps |
| CPU time | 1153.32 seconds |
| Started | Jun 23 07:50:23 PM PDT 24 |
| Finished | Jun 23 08:09:38 PM PDT 24 |
| Peak memory | 608860 kb |
| Host | smart-8db53af0-a730-4a03-9ff6-92cff0e147eb |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=50_000_000 +sw_build_device=sim_dv +sw_images=pwrmgr_deep_sleep_all_reset_reqs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=2291115550 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_deep_sleep_all_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_deep_sleep_all_reset_reqs.2291115550 |
| Directory | /workspace/0.chip_sw_pwrmgr_deep_sleep_all_reset_reqs/latest |
| Test location | /workspace/coverage/default/0.chip_sw_pwrmgr_deep_sleep_all_wake_ups.1849802299 |
| Short name | T95 |
| Test name | |
| Test status | |
| Simulation time | 22433639400 ps |
| CPU time | 1833.59 seconds |
| Started | Jun 23 07:53:31 PM PDT 24 |
| Finished | Jun 23 08:24:05 PM PDT 24 |
| Peak memory | 608692 kb |
| Host | smart-0368ed23-21d7-4a79-8b87-24facfb93fc8 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=pwrmgr_deep_sleep_all_wake_ups:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 1849802299 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_pwrmgr_deep_sleep_all_wake_ups_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_deep_sleep_all_wake_ups.1849802299 |
| Directory | /workspace/0.chip_sw_pwrmgr_deep_sleep_all_wake_ups/latest |
| Test location | /workspace/coverage/default/0.chip_sw_pwrmgr_deep_sleep_por_reset.1516113929 |
| Short name | T1114 |
| Test name | |
| Test status | |
| Simulation time | 8786327466 ps |
| CPU time | 669.58 seconds |
| Started | Jun 23 07:50:46 PM PDT 24 |
| Finished | Jun 23 08:01:56 PM PDT 24 |
| Peak memory | 607596 kb |
| Host | smart-a2a972c5-f85a-42c1-abc2-862a3f2effc7 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_deep_sleep_por_reset_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1516113929 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sleep_por_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage /default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_deep_sleep_por_reset.1516113929 |
| Directory | /workspace/0.chip_sw_pwrmgr_deep_sleep_por_reset/latest |
| Test location | /workspace/coverage/default/0.chip_sw_pwrmgr_deep_sleep_power_glitch_reset.875391545 |
| Short name | T1359 |
| Test name | |
| Test status | |
| Simulation time | 7844062010 ps |
| CPU time | 558.63 seconds |
| Started | Jun 23 07:50:43 PM PDT 24 |
| Finished | Jun 23 08:00:02 PM PDT 24 |
| Peak memory | 614972 kb |
| Host | smart-35e7e58c-5179-4cd8-96bc-01521814d51b |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=pwrmgr_deep_sleep_power_glitch_test:1:new_rules,test_rom :0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=875391545 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_deep_power_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_deep_sleep_power_glitch_reset.875391545 |
| Directory | /workspace/0.chip_sw_pwrmgr_deep_sleep_power_glitch_reset/latest |
| Test location | /workspace/coverage/default/0.chip_sw_pwrmgr_normal_sleep_all_wake_ups.1882774745 |
| Short name | T3 |
| Test name | |
| Test status | |
| Simulation time | 7530170880 ps |
| CPU time | 453.77 seconds |
| Started | Jun 23 07:55:04 PM PDT 24 |
| Finished | Jun 23 08:02:38 PM PDT 24 |
| Peak memory | 608024 kb |
| Host | smart-f2e77b13-9e06-47a1-bdd3-5a60d36a4569 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_normal_sleep_all_wake_ups:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1882774745 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_pwrmgr_deep_sleep_all_wake_ups_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_normal_sleep_all_wake_ups.1882774745 |
| Directory | /workspace/0.chip_sw_pwrmgr_normal_sleep_all_wake_ups/latest |
| Test location | /workspace/coverage/default/0.chip_sw_pwrmgr_normal_sleep_por_reset.2385312583 |
| Short name | T1138 |
| Test name | |
| Test status | |
| Simulation time | 7604546636 ps |
| CPU time | 794.26 seconds |
| Started | Jun 23 07:53:00 PM PDT 24 |
| Finished | Jun 23 08:06:15 PM PDT 24 |
| Peak memory | 607180 kb |
| Host | smart-c5d923c1-4196-46c2-9861-67d792bd7291 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_normal_sleep_por_reset_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2385312583 -assert nopostpr oc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sleep_por_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera ge/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_normal_sleep_por_reset.2385312583 |
| Directory | /workspace/0.chip_sw_pwrmgr_normal_sleep_por_reset/latest |
| Test location | /workspace/coverage/default/0.chip_sw_pwrmgr_random_sleep_all_reset_reqs.3443113366 |
| Short name | T1093 |
| Test name | |
| Test status | |
| Simulation time | 29076454284 ps |
| CPU time | 3040.33 seconds |
| Started | Jun 23 07:49:07 PM PDT 24 |
| Finished | Jun 23 08:39:48 PM PDT 24 |
| Peak memory | 608904 kb |
| Host | smart-06d3067d-756f-4472-9431-e61cd99bbfac |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=50_000_000 +sw_build_device=sim_dv +sw_images=pwrmgr_random_sleep_all_reset_reqs_test:1:new_rules,test_rom :0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=3443113366 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_deep_sleep_all_reset_vseq +en_cov=1 -cm line+cond+fsm+tg l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_random_sleep_all_reset_reqs.3443113366 |
| Directory | /workspace/0.chip_sw_pwrmgr_random_sleep_all_reset_reqs/latest |
| Test location | /workspace/coverage/default/0.chip_sw_pwrmgr_random_sleep_all_wake_ups.1765907013 |
| Short name | T9 |
| Test name | |
| Test status | |
| Simulation time | 22917396864 ps |
| CPU time | 2022.49 seconds |
| Started | Jun 23 07:52:16 PM PDT 24 |
| Finished | Jun 23 08:25:59 PM PDT 24 |
| Peak memory | 608640 kb |
| Host | smart-d9b25330-fb55-493d-a297-5998acb515b2 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +do_random=1 +sw_build_device=sim_dv +sw_images=pwrmgr_random_sleep_all_wake_ups:1:new_rules,te st_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n tb_random_seed=1765907013 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_pwrmgr_deep_sleep_all_wake_ups_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_random_sleep_all_wake_ups.1765907013 |
| Directory | /workspace/0.chip_sw_pwrmgr_random_sleep_all_wake_ups/latest |
| Test location | /workspace/coverage/default/0.chip_sw_pwrmgr_random_sleep_power_glitch_reset.2843941030 |
| Short name | T349 |
| Test name | |
| Test status | |
| Simulation time | 30524148090 ps |
| CPU time | 3281.69 seconds |
| Started | Jun 23 07:52:27 PM PDT 24 |
| Finished | Jun 23 08:47:10 PM PDT 24 |
| Peak memory | 609972 kb |
| Host | smart-3312a864-873f-4634-9dbf-2332d07ef4f5 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_test_timeout_ns=24_000_000 +sw_build_device=sim_dv +sw_images=pwrmgr_random_sleep_power _glitch_reset_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2843941030 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_random_power_glit ch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_random_s leep_power_glitch_reset.2843941030 |
| Directory | /workspace/0.chip_sw_pwrmgr_random_sleep_power_glitch_reset/latest |
| Test location | /workspace/coverage/default/0.chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up.3936490327 |
| Short name | T368 |
| Test name | |
| Test status | |
| Simulation time | 5583364380 ps |
| CPU time | 487.25 seconds |
| Started | Jun 23 07:53:57 PM PDT 24 |
| Finished | Jun 23 08:02:05 PM PDT 24 |
| Peak memory | 608564 kb |
| Host | smart-49a33f39-59dc-472a-9951-0061ab2763f5 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +do_random=1 +sw_build_device=sim_dv +sw_images=pwrmgr_sensor_ctrl_deep_sleep_wake_up:1:new_rul es,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t cl +ntb_random_seed=3936490327 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_sensor_ctrl_deep_s leep_wake_up.3936490327 |
| Directory | /workspace/0.chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up/latest |
| Test location | /workspace/coverage/default/0.chip_sw_pwrmgr_sleep_disabled.1072087137 |
| Short name | T715 |
| Test name | |
| Test status | |
| Simulation time | 2566143640 ps |
| CPU time | 219.04 seconds |
| Started | Jun 23 07:50:24 PM PDT 24 |
| Finished | Jun 23 07:54:03 PM PDT 24 |
| Peak memory | 606952 kb |
| Host | smart-eef51cb6-e227-4a57-a125-941da5fcc8db |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_sleep_disabled_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1072087137 -assert nopostproc +UVM_ TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_ log /dev/null -cm_name 0.chip_sw_pwrmgr_sleep_disabled.1072087137 |
| Directory | /workspace/0.chip_sw_pwrmgr_sleep_disabled/latest |
| Test location | /workspace/coverage/default/0.chip_sw_pwrmgr_sleep_power_glitch_reset.3730568755 |
| Short name | T1005 |
| Test name | |
| Test status | |
| Simulation time | 6489038541 ps |
| CPU time | 550.06 seconds |
| Started | Jun 23 07:50:34 PM PDT 24 |
| Finished | Jun 23 07:59:44 PM PDT 24 |
| Peak memory | 614276 kb |
| Host | smart-0b7084a2-22fa-49e4-8449-562f97a93cb5 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=pwrmgr_sleep_power_glitch_test:1:new_rules,test_rom:0 +c dc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_s eed=3730568755 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_main_power_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_sleep_power_glitch_reset.3730568755 |
| Directory | /workspace/0.chip_sw_pwrmgr_sleep_power_glitch_reset/latest |
| Test location | /workspace/coverage/default/0.chip_sw_pwrmgr_sleep_wake_5_bug.1588805747 |
| Short name | T1229 |
| Test name | |
| Test status | |
| Simulation time | 6804290678 ps |
| CPU time | 522.65 seconds |
| Started | Jun 23 07:53:36 PM PDT 24 |
| Finished | Jun 23 08:02:19 PM PDT 24 |
| Peak memory | 608668 kb |
| Host | smart-103514cc-b41b-4e66-8537-2dba5ccbbc9c |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +do_random=1 +sw_build_device=sim_dv +sw_images=pwrmgr_sleep_wake_5_bug_test:1:new_rules,test_r om:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r andom_seed=1588805747 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_sleep_wake_5_bug.1588805747 |
| Directory | /workspace/0.chip_sw_pwrmgr_sleep_wake_5_bug/latest |
| Test location | /workspace/coverage/default/0.chip_sw_pwrmgr_smoketest.1769887161 |
| Short name | T943 |
| Test name | |
| Test status | |
| Simulation time | 6156695338 ps |
| CPU time | 432.34 seconds |
| Started | Jun 23 07:55:47 PM PDT 24 |
| Finished | Jun 23 08:02:59 PM PDT 24 |
| Peak memory | 607852 kb |
| Host | smart-c942ea20-4870-4352-85a8-aabf42a7af42 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=10000000 +sw_build_device=sim_dv +sw_images=pwrmgr_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1769887161 -asse rt nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera ge/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_smoketest.1769887161 |
| Directory | /workspace/0.chip_sw_pwrmgr_smoketest/latest |
| Test location | /workspace/coverage/default/0.chip_sw_pwrmgr_sysrst_ctrl_reset.1428830587 |
| Short name | T1134 |
| Test name | |
| Test status | |
| Simulation time | 9753197676 ps |
| CPU time | 1439.66 seconds |
| Started | Jun 23 07:50:46 PM PDT 24 |
| Finished | Jun 23 08:14:46 PM PDT 24 |
| Peak memory | 607624 kb |
| Host | smart-992ced45-e1ef-4801-9f8e-ffb9a58276ad |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_sysrst_ctrl_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1428830587 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_sysrst_ctrl_reset.1428830587 |
| Directory | /workspace/0.chip_sw_pwrmgr_sysrst_ctrl_reset/latest |
| Test location | /workspace/coverage/default/0.chip_sw_pwrmgr_usb_clk_disabled_when_active.1834677012 |
| Short name | T1079 |
| Test name | |
| Test status | |
| Simulation time | 5137317760 ps |
| CPU time | 503.91 seconds |
| Started | Jun 23 07:50:50 PM PDT 24 |
| Finished | Jun 23 07:59:15 PM PDT 24 |
| Peak memory | 607148 kb |
| Host | smart-ddeaa4e9-c33e-412e-b06e-cc7c2d7717f5 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_usb_clk_disabled_when_active_test:1:new_rules,test_rom:0 +cdc_instrumentation_enable d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1834677012 -assert no postproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de fault.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_usb_clk_disabled_when_active.1834677012 |
| Directory | /workspace/0.chip_sw_pwrmgr_usb_clk_disabled_when_active/latest |
| Test location | /workspace/coverage/default/0.chip_sw_pwrmgr_usbdev_smoketest.1379543287 |
| Short name | T395 |
| Test name | |
| Test status | |
| Simulation time | 6193382884 ps |
| CPU time | 530.53 seconds |
| Started | Jun 23 07:55:16 PM PDT 24 |
| Finished | Jun 23 08:04:07 PM PDT 24 |
| Peak memory | 607772 kb |
| Host | smart-9d9fe7b1-5e3e-4494-9ce2-0978e97e6f19 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_usbdev_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1379543287 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_usbdev_smoketest.1379543287 |
| Directory | /workspace/0.chip_sw_pwrmgr_usbdev_smoketest/latest |
| Test location | /workspace/coverage/default/0.chip_sw_pwrmgr_wdog_reset.412411396 |
| Short name | T93 |
| Test name | |
| Test status | |
| Simulation time | 4858353030 ps |
| CPU time | 721.23 seconds |
| Started | Jun 23 07:53:05 PM PDT 24 |
| Finished | Jun 23 08:05:07 PM PDT 24 |
| Peak memory | 608536 kb |
| Host | smart-aa027e04-328c-4f73-afd6-137a7842bffe |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=pwrmgr_wdog_reset_reqs_test:1:new_rules,test_rom:0 +cdc_inst rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=412 411396 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work space/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_wdog_reset.412411396 |
| Directory | /workspace/0.chip_sw_pwrmgr_wdog_reset/latest |
| Test location | /workspace/coverage/default/0.chip_sw_rom_ctrl_integrity_check.837980896 |
| Short name | T1252 |
| Test name | |
| Test status | |
| Simulation time | 10041035109 ps |
| CPU time | 478.2 seconds |
| Started | Jun 23 07:49:54 PM PDT 24 |
| Finished | Jun 23 07:57:52 PM PDT 24 |
| Peak memory | 607508 kb |
| Host | smart-8434bf56-5665-497d-a8cf-0769b2d8004b |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=rom_ctrl_integrity_check_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=837980896 -assert nopostproc +UV M_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_ctrl_integrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov erage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_rom_ctrl_integrity_check.837980896 |
| Directory | /workspace/0.chip_sw_rom_ctrl_integrity_check/latest |
| Test location | /workspace/coverage/default/0.chip_sw_rstmgr_alert_info.1148856491 |
| Short name | T317 |
| Test name | |
| Test status | |
| Simulation time | 10515768552 ps |
| CPU time | 1743.19 seconds |
| Started | Jun 23 07:50:22 PM PDT 24 |
| Finished | Jun 23 08:19:26 PM PDT 24 |
| Peak memory | 608868 kb |
| Host | smart-c99712ef-4087-41cf-bf90-b83c9245e88c |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=30_000_000 +en_scb_tl_err_chk=0 +sw_build_device=sim_dv +sw_images=rstmgr_alert_info_test:1:new_rules,test _rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb _random_seed=1148856491 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_rstmgr_alert_info.1148856491 |
| Directory | /workspace/0.chip_sw_rstmgr_alert_info/latest |
| Test location | /workspace/coverage/default/0.chip_sw_rstmgr_cpu_info.1853995375 |
| Short name | T254 |
| Test name | |
| Test status | |
| Simulation time | 7361992056 ps |
| CPU time | 754.99 seconds |
| Started | Jun 23 07:52:27 PM PDT 24 |
| Finished | Jun 23 08:05:03 PM PDT 24 |
| Peak memory | 606944 kb |
| Host | smart-e5c9afcc-d2fb-4b6d-9044-810bd7af1d2c |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=rstmgr_cpu_info_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1853995375 -assert nopostproc +UVM_TESTNA ME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 0.chip_sw_rstmgr_cpu_info.1853995375 |
| Directory | /workspace/0.chip_sw_rstmgr_cpu_info/latest |
| Test location | /workspace/coverage/default/0.chip_sw_rstmgr_rst_cnsty_escalation.4036962598 |
| Short name | T746 |
| Test name | |
| Test status | |
| Simulation time | 4932494080 ps |
| CPU time | 667.21 seconds |
| Started | Jun 23 07:49:01 PM PDT 24 |
| Finished | Jun 23 08:00:09 PM PDT 24 |
| Peak memory | 639588 kb |
| Host | smart-f0c9e2ca-4bc2-4e4f-be6d-a603dbfa832e |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 4036962598 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rstmgr_cnsty_fault_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_rstmgr_rst_cnsty_escalation.4036962598 |
| Directory | /workspace/0.chip_sw_rstmgr_rst_cnsty_escalation/latest |
| Test location | /workspace/coverage/default/0.chip_sw_rstmgr_smoketest.3431365939 |
| Short name | T912 |
| Test name | |
| Test status | |
| Simulation time | 2888525410 ps |
| CPU time | 181.13 seconds |
| Started | Jun 23 07:53:13 PM PDT 24 |
| Finished | Jun 23 07:56:14 PM PDT 24 |
| Peak memory | 606836 kb |
| Host | smart-f7f9b197-4888-4c8e-af98-6618cb1426c7 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=rstmgr_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3431365939 -assert nopostproc +UVM_TESTNAME=c hip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n ull -cm_name 0.chip_sw_rstmgr_smoketest.3431365939 |
| Directory | /workspace/0.chip_sw_rstmgr_smoketest/latest |
| Test location | /workspace/coverage/default/0.chip_sw_rstmgr_sw_req.4089985898 |
| Short name | T1179 |
| Test name | |
| Test status | |
| Simulation time | 4220747544 ps |
| CPU time | 385.49 seconds |
| Started | Jun 23 07:50:17 PM PDT 24 |
| Finished | Jun 23 07:56:42 PM PDT 24 |
| Peak memory | 607896 kb |
| Host | smart-9252fbb7-989f-492e-a556-c6390bacab95 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=rstmgr_sw_req_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4089985898 -assert nopostproc +UVM_TESTNAME =chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 0.chip_sw_rstmgr_sw_req.4089985898 |
| Directory | /workspace/0.chip_sw_rstmgr_sw_req/latest |
| Test location | /workspace/coverage/default/0.chip_sw_rstmgr_sw_rst.872364535 |
| Short name | T1080 |
| Test name | |
| Test status | |
| Simulation time | 2555921004 ps |
| CPU time | 273.58 seconds |
| Started | Jun 23 07:49:00 PM PDT 24 |
| Finished | Jun 23 07:53:34 PM PDT 24 |
| Peak memory | 606812 kb |
| Host | smart-459c73fc-929d-49e6-a99c-0b3da8d240b5 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=rstmgr_sw_rst_ctrl_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=872364535 -assert nopostproc +UVM_TEST NAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_rstmgr_sw_rst.872364535 |
| Directory | /workspace/0.chip_sw_rstmgr_sw_rst/latest |
| Test location | /workspace/coverage/default/0.chip_sw_rv_core_ibex_address_translation.3411054041 |
| Short name | T173 |
| Test name | |
| Test status | |
| Simulation time | 3494556456 ps |
| CPU time | 316.65 seconds |
| Started | Jun 23 07:52:56 PM PDT 24 |
| Finished | Jun 23 07:58:13 PM PDT 24 |
| Peak memory | 606952 kb |
| Host | smart-cee95fb8-92db-4d50-beab-17672f78c44d |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=7_000_000 +sw_build_device=sim_dv +sw_images=rv_core_ibex_address_translation_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=3411054041 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_rv_core_ibex_address_translation.3411054041 |
| Directory | /workspace/0.chip_sw_rv_core_ibex_address_translation/latest |
| Test location | /workspace/coverage/default/0.chip_sw_rv_core_ibex_icache_invalidate.3222246103 |
| Short name | T295 |
| Test name | |
| Test status | |
| Simulation time | 3008748216 ps |
| CPU time | 285.13 seconds |
| Started | Jun 23 07:54:11 PM PDT 24 |
| Finished | Jun 23 07:58:57 PM PDT 24 |
| Peak memory | 607048 kb |
| Host | smart-c57530cd-26f4-474c-9728-201e1fc4f016 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=rv_core_ibex_icache_invalidate_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3222246103 -assert nopostp roc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rv_core_ibex_icache_invalidate_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_rv_core_ibex_icache_invalidate.3222246103 |
| Directory | /workspace/0.chip_sw_rv_core_ibex_icache_invalidate/latest |
| Test location | /workspace/coverage/default/0.chip_sw_rv_core_ibex_rnd.575842500 |
| Short name | T925 |
| Test name | |
| Test status | |
| Simulation time | 5016552400 ps |
| CPU time | 1049.78 seconds |
| Started | Jun 23 07:48:19 PM PDT 24 |
| Finished | Jun 23 08:05:49 PM PDT 24 |
| Peak memory | 606820 kb |
| Host | smart-5b8fedb7-5646-4421-9d67-57ad4b125ce0 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=20_000_000 +rng_srate_value_max=32 +sw_build_device=sim_dv +sw_images=rv_core_ibex_rnd_test:1:new_rules,te st_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n tb_random_seed=575842500 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_rv_core_ibex_rnd.575842500 |
| Directory | /workspace/0.chip_sw_rv_core_ibex_rnd/latest |
| Test location | /workspace/coverage/default/0.chip_sw_rv_dm_access_after_escalation_reset.462781592 |
| Short name | T694 |
| Test name | |
| Test status | |
| Simulation time | 5862490572 ps |
| CPU time | 380.48 seconds |
| Started | Jun 23 07:49:25 PM PDT 24 |
| Finished | Jun 23 07:55:46 PM PDT 24 |
| Peak memory | 615336 kb |
| Host | smart-b917cf61-78ee-4969-bbfc-8be0aa001dfe |
| User | root |
| Command | /workspace/default/simv +use_jtag_dmi=1 +sw_build_device=sim_dv +sw_images=alert_handler_escalation_test:1:new_rules,test_rom:0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=462781592 -asser t nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rv_dm_access_after_escalation_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_rv_dm_access_after_escalation_reset.462781592 |
| Directory | /workspace/0.chip_sw_rv_dm_access_after_escalation_reset/latest |
| Test location | /workspace/coverage/default/0.chip_sw_rv_plic_smoketest.182849705 |
| Short name | T1334 |
| Test name | |
| Test status | |
| Simulation time | 2635048408 ps |
| CPU time | 227.44 seconds |
| Started | Jun 23 07:57:12 PM PDT 24 |
| Finished | Jun 23 08:01:00 PM PDT 24 |
| Peak memory | 607832 kb |
| Host | smart-4a867d64-eaf7-4973-ac60-8d7378e0ecc2 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=rv_plic_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=182849705 -assert nopostproc +UVM_TESTNAME=c hip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n ull -cm_name 0.chip_sw_rv_plic_smoketest.182849705 |
| Directory | /workspace/0.chip_sw_rv_plic_smoketest/latest |
| Test location | /workspace/coverage/default/0.chip_sw_rv_timer_irq.558902060 |
| Short name | T1226 |
| Test name | |
| Test status | |
| Simulation time | 2723711096 ps |
| CPU time | 320.22 seconds |
| Started | Jun 23 07:52:57 PM PDT 24 |
| Finished | Jun 23 07:58:17 PM PDT 24 |
| Peak memory | 606864 kb |
| Host | smart-a0318d57-f7f9-4e6a-9d78-a2331cb754d2 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=rv_timer_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=558902060 -assert nopostproc +UVM_TESTNAME= chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/ null -cm_name 0.chip_sw_rv_timer_irq.558902060 |
| Directory | /workspace/0.chip_sw_rv_timer_irq/latest |
| Test location | /workspace/coverage/default/0.chip_sw_rv_timer_smoketest.2796952970 |
| Short name | T244 |
| Test name | |
| Test status | |
| Simulation time | 2804930870 ps |
| CPU time | 214.43 seconds |
| Started | Jun 23 07:53:24 PM PDT 24 |
| Finished | Jun 23 07:56:59 PM PDT 24 |
| Peak memory | 606856 kb |
| Host | smart-969dd112-e812-4f67-a3ff-9f54650f12aa |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=rv_timer_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2796952970 -assert nopostproc +UVM_TESTNAME =chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 0.chip_sw_rv_timer_smoketest.2796952970 |
| Directory | /workspace/0.chip_sw_rv_timer_smoketest/latest |
| Test location | /workspace/coverage/default/0.chip_sw_sensor_ctrl_status.312441131 |
| Short name | T139 |
| Test name | |
| Test status | |
| Simulation time | 2590755273 ps |
| CPU time | 246.6 seconds |
| Started | Jun 23 07:49:51 PM PDT 24 |
| Finished | Jun 23 07:53:58 PM PDT 24 |
| Peak memory | 608036 kb |
| Host | smart-e62c7e32-3c82-40dc-9bb5-68f9e2b228cd |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=40_000_000 +sw_build_device=sim_dv +sw_images=sensor_ctrl_status_test:1:new_rules,test_rom:0 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3124411 31 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sensor_ctrl_status_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_sensor_ctrl_status.312441131 |
| Directory | /workspace/0.chip_sw_sensor_ctrl_status/latest |
| Test location | /workspace/coverage/default/0.chip_sw_sleep_pin_retention.2648504751 |
| Short name | T14 |
| Test name | |
| Test status | |
| Simulation time | 4250414800 ps |
| CPU time | 303.06 seconds |
| Started | Jun 23 07:50:29 PM PDT 24 |
| Finished | Jun 23 07:55:33 PM PDT 24 |
| Peak memory | 606920 kb |
| Host | smart-a1684817-9148-4548-b37f-f558883b698a |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=sleep_pin_retention_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2648504751 -assert nopostproc +UVM_TE STNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sleep_pin_retention_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def ault.vdb -cm_log /dev/null -cm_name 0.chip_sw_sleep_pin_retention.2648504751 |
| Directory | /workspace/0.chip_sw_sleep_pin_retention/latest |
| Test location | /workspace/coverage/default/0.chip_sw_sleep_pwm_pulses.969437041 |
| Short name | T1259 |
| Test name | |
| Test status | |
| Simulation time | 9816512084 ps |
| CPU time | 1798.61 seconds |
| Started | Jun 23 07:50:19 PM PDT 24 |
| Finished | Jun 23 08:20:21 PM PDT 24 |
| Peak memory | 608520 kb |
| Host | smart-0f234043-39e5-4ba3-9488-339484990490 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=sleep_pwm_pulses_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=969437041 -assert nopostproc +UVM_TESTNA ME=chip_base_test +UVM_TEST_SEQ=chip_sw_pwm_pulses_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_ log /dev/null -cm_name 0.chip_sw_sleep_pwm_pulses.969437041 |
| Directory | /workspace/0.chip_sw_sleep_pwm_pulses/latest |
| Test location | /workspace/coverage/default/0.chip_sw_sleep_sram_ret_contents_no_scramble.1689053142 |
| Short name | T120 |
| Test name | |
| Test status | |
| Simulation time | 9484926298 ps |
| CPU time | 937.75 seconds |
| Started | Jun 23 07:52:32 PM PDT 24 |
| Finished | Jun 23 08:08:10 PM PDT 24 |
| Peak memory | 608292 kb |
| Host | smart-29520c0e-549e-4643-b349-8b0e5487c838 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=20_000_000 +en_scb_tl_err_chk=0 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=sram _ctrl_sleep_sram_ret_contents_no_scramble_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1689053142 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_S EQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_sl eep_sram_ret_contents_no_scramble.1689053142 |
| Directory | /workspace/0.chip_sw_sleep_sram_ret_contents_no_scramble/latest |
| Test location | /workspace/coverage/default/0.chip_sw_sleep_sram_ret_contents_scramble.1788702025 |
| Short name | T1161 |
| Test name | |
| Test status | |
| Simulation time | 7922146312 ps |
| CPU time | 523.19 seconds |
| Started | Jun 23 07:51:51 PM PDT 24 |
| Finished | Jun 23 08:00:34 PM PDT 24 |
| Peak memory | 608540 kb |
| Host | smart-1fe4881a-ffd7-41e0-8689-cc6907483c89 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=20_000_000 +en_scb_tl_err_chk=0 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=sram _ctrl_sleep_sram_ret_contents_scramble_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1788702025 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ= chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_sleep _sram_ret_contents_scramble.1788702025 |
| Directory | /workspace/0.chip_sw_sleep_sram_ret_contents_scramble/latest |
| Test location | /workspace/coverage/default/0.chip_sw_spi_device_pass_through.2500170700 |
| Short name | T190 |
| Test name | |
| Test status | |
| Simulation time | 7800492892 ps |
| CPU time | 840.69 seconds |
| Started | Jun 23 07:52:48 PM PDT 24 |
| Finished | Jun 23 08:06:50 PM PDT 24 |
| Peak memory | 623512 kb |
| Host | smart-dc4383d0-ad69-40c1-8f89-42c0ce07f216 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=spi_passthrough_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2500170700 -assert nopostproc +UVM_TESTNA ME=chip_base_test +UVM_TEST_SEQ=chip_sw_spi_passthrough_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_spi_device_pass_through.2500170700 |
| Directory | /workspace/0.chip_sw_spi_device_pass_through/latest |
| Test location | /workspace/coverage/default/0.chip_sw_spi_device_tpm.1604899124 |
| Short name | T52 |
| Test name | |
| Test status | |
| Simulation time | 3259138842 ps |
| CPU time | 481.12 seconds |
| Started | Jun 23 07:50:56 PM PDT 24 |
| Finished | Jun 23 07:58:57 PM PDT 24 |
| Peak memory | 616312 kb |
| Host | smart-5efd1112-c4e6-4fc1-afb5-f104d5ba4165 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=spi_device_tpm_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1604899124 -assert nopostproc +UVM_T ESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_spi_device_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default .vdb -cm_log /dev/null -cm_name 0.chip_sw_spi_device_tpm.1604899124 |
| Directory | /workspace/0.chip_sw_spi_device_tpm/latest |
| Test location | /workspace/coverage/default/0.chip_sw_spi_host_tx_rx.2172258980 |
| Short name | T26 |
| Test name | |
| Test status | |
| Simulation time | 2922264738 ps |
| CPU time | 358.16 seconds |
| Started | Jun 23 07:49:19 PM PDT 24 |
| Finished | Jun 23 07:55:18 PM PDT 24 |
| Peak memory | 606940 kb |
| Host | smart-2cfbb690-0de7-4603-96c4-2f40b7829ff4 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=spi_host_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2172258980 -assert nopostproc +UVM_TESTNAM E=chip_base_test +UVM_TEST_SEQ=chip_sw_spi_host_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb - cm_log /dev/null -cm_name 0.chip_sw_spi_host_tx_rx.2172258980 |
| Directory | /workspace/0.chip_sw_spi_host_tx_rx/latest |
| Test location | /workspace/coverage/default/0.chip_sw_sram_ctrl_scrambled_access.1797541771 |
| Short name | T504 |
| Test name | |
| Test status | |
| Simulation time | 4028748024 ps |
| CPU time | 562.5 seconds |
| Started | Jun 23 07:52:14 PM PDT 24 |
| Finished | Jun 23 08:01:38 PM PDT 24 |
| Peak memory | 608460 kb |
| Host | smart-fcad6b20-d948-43e2-8949-5367c15a770e |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=12_000_000 +en_scb_tl_err_chk=0 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=sram _ctrl_scrambled_access_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1797541771 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sram_ctr l_scrambled_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw _sram_ctrl_scrambled_access.1797541771 |
| Directory | /workspace/0.chip_sw_sram_ctrl_scrambled_access/latest |
| Test location | /workspace/coverage/default/0.chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq.643944229 |
| Short name | T113 |
| Test name | |
| Test status | |
| Simulation time | 4032257642 ps |
| CPU time | 587.62 seconds |
| Started | Jun 23 07:51:41 PM PDT 24 |
| Finished | Jun 23 08:01:30 PM PDT 24 |
| Peak memory | 608136 kb |
| Host | smart-d0fb17bf-8319-45f8-a848-5a62857f661a |
| User | root |
| Command | /workspace/default/simv +mem_sel=main +sw_test_timeout_ns=12_000_000 +bypass_alert_ready_to_end_check=1 +en_jitter=1 +en_scb_tl_err_chk=0 +cal_sys_clk _70mhz=1 +sw_build_device=sim_dv +sw_images=sram_ctrl_scrambled_access_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=643944229 -assert nopostproc +UVM_TESTNAM E=chip_base_test +UVM_TEST_SEQ=chip_sw_sram_ctrl_scrambled_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/d efault.vdb -cm_log /dev/null -cm_name 0.chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq.643944229 |
| Directory | /workspace/0.chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq/latest |
| Test location | /workspace/coverage/default/0.chip_sw_sram_ctrl_smoketest.109285705 |
| Short name | T417 |
| Test name | |
| Test status | |
| Simulation time | 2618438252 ps |
| CPU time | 235.76 seconds |
| Started | Jun 23 07:57:04 PM PDT 24 |
| Finished | Jun 23 08:01:01 PM PDT 24 |
| Peak memory | 606924 kb |
| Host | smart-8db9efc0-4a6a-4aef-af8d-f65dcee563f1 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=sram_ctrl_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=109285705 -assert nopostproc +UVM_TESTNAME =chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 0.chip_sw_sram_ctrl_smoketest.109285705 |
| Directory | /workspace/0.chip_sw_sram_ctrl_smoketest/latest |
| Test location | /workspace/coverage/default/0.chip_sw_sysrst_ctrl_in_irq.557754545 |
| Short name | T200 |
| Test name | |
| Test status | |
| Simulation time | 4955880409 ps |
| CPU time | 591.08 seconds |
| Started | Jun 23 07:49:45 PM PDT 24 |
| Finished | Jun 23 07:59:38 PM PDT 24 |
| Peak memory | 611296 kb |
| Host | smart-48290cf9-dbd3-4702-8332-d9c05ad3e602 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=sysrst_ctrl_in_irq_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=557754545 -assert nopostproc +UVM_TEST NAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_in_irq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul t.vdb -cm_log /dev/null -cm_name 0.chip_sw_sysrst_ctrl_in_irq.557754545 |
| Directory | /workspace/0.chip_sw_sysrst_ctrl_in_irq/latest |
| Test location | /workspace/coverage/default/0.chip_sw_sysrst_ctrl_inputs.1018755492 |
| Short name | T199 |
| Test name | |
| Test status | |
| Simulation time | 3279421631 ps |
| CPU time | 374.95 seconds |
| Started | Jun 23 07:49:52 PM PDT 24 |
| Finished | Jun 23 07:56:08 PM PDT 24 |
| Peak memory | 610852 kb |
| Host | smart-b90818bd-e71a-45ff-951b-25fe9a7eeac9 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=sysrst_ctrl_inputs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1018755492 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_inputs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau lt.vdb -cm_log /dev/null -cm_name 0.chip_sw_sysrst_ctrl_inputs.1018755492 |
| Directory | /workspace/0.chip_sw_sysrst_ctrl_inputs/latest |
| Test location | /workspace/coverage/default/0.chip_sw_sysrst_ctrl_outputs.3170787532 |
| Short name | T35 |
| Test name | |
| Test status | |
| Simulation time | 3489463094 ps |
| CPU time | 424.37 seconds |
| Started | Jun 23 07:50:25 PM PDT 24 |
| Finished | Jun 23 07:57:31 PM PDT 24 |
| Peak memory | 607824 kb |
| Host | smart-7b0baae2-889d-43fa-844c-1140d014c792 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=sysrst_ctrl_outputs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3170787532 -assert nopostproc +UVM_TE STNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_outputs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def ault.vdb -cm_log /dev/null -cm_name 0.chip_sw_sysrst_ctrl_outputs.3170787532 |
| Directory | /workspace/0.chip_sw_sysrst_ctrl_outputs/latest |
| Test location | /workspace/coverage/default/0.chip_sw_sysrst_ctrl_reset.3669882981 |
| Short name | T202 |
| Test name | |
| Test status | |
| Simulation time | 24868335090 ps |
| CPU time | 1980.86 seconds |
| Started | Jun 23 07:51:59 PM PDT 24 |
| Finished | Jun 23 08:25:00 PM PDT 24 |
| Peak memory | 612952 kb |
| Host | smart-750d1a2f-164e-409c-905b-30e581afe1a4 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=36_000_000 +sw_build_device=sim_dv +sw_images=sysrst_ctrl_reset_test:1:new_rules,test_rom:0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36698829 81 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_sysrst_ctrl_reset.3669882981 |
| Directory | /workspace/0.chip_sw_sysrst_ctrl_reset/latest |
| Test location | /workspace/coverage/default/0.chip_sw_sysrst_ctrl_ulp_z3_wakeup.4054561696 |
| Short name | T48 |
| Test name | |
| Test status | |
| Simulation time | 5096503940 ps |
| CPU time | 445.31 seconds |
| Started | Jun 23 07:49:53 PM PDT 24 |
| Finished | Jun 23 07:57:19 PM PDT 24 |
| Peak memory | 607268 kb |
| Host | smart-65d9b8d7-d353-4aa6-a296-740756684824 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=sysrst_ctrl_ulp_z3_wakeup_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4054561696 -assert nopostproc + UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_ulp_z3_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/ coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_sysrst_ctrl_ulp_z3_wakeup.4054561696 |
| Directory | /workspace/0.chip_sw_sysrst_ctrl_ulp_z3_wakeup/latest |
| Test location | /workspace/coverage/default/0.chip_sw_uart_rand_baudrate.3544015537 |
| Short name | T212 |
| Test name | |
| Test status | |
| Simulation time | 3723006304 ps |
| CPU time | 623.09 seconds |
| Started | Jun 23 07:53:06 PM PDT 24 |
| Finished | Jun 23 08:03:30 PM PDT 24 |
| Peak memory | 619472 kb |
| Host | smart-aaa2248d-2eaf-4061-aa28-02696545d6d1 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=3544015537 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_uart_rand_baudrate.3544015537 |
| Directory | /workspace/0.chip_sw_uart_rand_baudrate/latest |
| Test location | /workspace/coverage/default/0.chip_sw_uart_smoketest.114044959 |
| Short name | T275 |
| Test name | |
| Test status | |
| Simulation time | 3272712136 ps |
| CPU time | 326.44 seconds |
| Started | Jun 23 07:54:55 PM PDT 24 |
| Finished | Jun 23 08:00:22 PM PDT 24 |
| Peak memory | 609868 kb |
| Host | smart-00b83baf-347d-4c6c-93d8-92b88d23b536 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=uart_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=114044959 -assert nopostproc +UVM_TESTNAME=chip _base_test +UVM_TEST_SEQ=chip_sw_uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 0.chip_sw_uart_smoketest.114044959 |
| Directory | /workspace/0.chip_sw_uart_smoketest/latest |
| Test location | /workspace/coverage/default/0.chip_sw_uart_tx_rx_alt_clk_freq.558576637 |
| Short name | T1056 |
| Test name | |
| Test status | |
| Simulation time | 4571498892 ps |
| CPU time | 637.75 seconds |
| Started | Jun 23 07:52:54 PM PDT 24 |
| Finished | Jun 23 08:03:33 PM PDT 24 |
| Peak memory | 618748 kb |
| Host | smart-70930089-6cce-4d79-862f-7b3a43c117fc |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=80_000_000 +chip_clock_source=ChipClockSourceExternal96Mhz +calibrate_usb_clk=1 +sw_build_device=sim_dv +s w_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=558576637 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_ba udrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_uart_tx_rx_ alt_clk_freq.558576637 |
| Directory | /workspace/0.chip_sw_uart_tx_rx_alt_clk_freq/latest |
| Test location | /workspace/coverage/default/0.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.2128598425 |
| Short name | T1139 |
| Test name | |
| Test status | |
| Simulation time | 8417120727 ps |
| CPU time | 1411.79 seconds |
| Started | Jun 23 07:49:36 PM PDT 24 |
| Finished | Jun 23 08:13:10 PM PDT 24 |
| Peak memory | 618484 kb |
| Host | smart-e9edd19f-607c-4cf0-8bb0-ac2d54f265ea |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +chip_clock_source=ChipClockSourceExternal48Mhz +sw_build_device=sim_dv +s w_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2128598425 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_b audrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_uart_tx_rx _alt_clk_freq_low_speed.2128598425 |
| Directory | /workspace/0.chip_sw_uart_tx_rx_alt_clk_freq_low_speed/latest |
| Test location | /workspace/coverage/default/0.chip_sw_uart_tx_rx_bootstrap.4189793974 |
| Short name | T30 |
| Test name | |
| Test status | |
| Simulation time | 77528733433 ps |
| CPU time | 12970.4 seconds |
| Started | Jun 23 07:50:17 PM PDT 24 |
| Finished | Jun 23 11:26:29 PM PDT 24 |
| Peak memory | 633732 kb |
| Host | smart-0aa70925-a6e6-4042-8246-02ee67483043 |
| User | root |
| Command | /workspace/default/simv +use_spi_load_bootstrap=1 +calibrate_usb_clk=1 +test_timeout_ns=160_000_000 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test :1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=4189793974 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_uart_tx_rx_bootstrap.4189793974 |
| Directory | /workspace/0.chip_sw_uart_tx_rx_bootstrap/latest |
| Test location | /workspace/coverage/default/0.chip_sw_uart_tx_rx_idx1.965458414 |
| Short name | T1163 |
| Test name | |
| Test status | |
| Simulation time | 4114740100 ps |
| CPU time | 686.3 seconds |
| Started | Jun 23 07:50:17 PM PDT 24 |
| Finished | Jun 23 08:01:45 PM PDT 24 |
| Peak memory | 615096 kb |
| Host | smart-2c542b09-2cc5-4dbf-970a-04118d4bc4fb |
| User | root |
| Command | /workspace/default/simv +uart_idx=1 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=965458414 -as sert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac e/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_uart_tx_rx_idx1.965458414 |
| Directory | /workspace/0.chip_sw_uart_tx_rx_idx1/latest |
| Test location | /workspace/coverage/default/0.chip_sw_uart_tx_rx_idx2.3490955955 |
| Short name | T1272 |
| Test name | |
| Test status | |
| Simulation time | 3846878772 ps |
| CPU time | 753.07 seconds |
| Started | Jun 23 07:50:47 PM PDT 24 |
| Finished | Jun 23 08:03:20 PM PDT 24 |
| Peak memory | 615080 kb |
| Host | smart-fd6ed551-22f9-4bb5-8531-71b5855f0879 |
| User | root |
| Command | /workspace/default/simv +uart_idx=2 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3490955955 -a ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_uart_tx_rx_idx2.3490955955 |
| Directory | /workspace/0.chip_sw_uart_tx_rx_idx2/latest |
| Test location | /workspace/coverage/default/0.chip_sw_uart_tx_rx_idx3.595283259 |
| Short name | T1262 |
| Test name | |
| Test status | |
| Simulation time | 4278559320 ps |
| CPU time | 736.61 seconds |
| Started | Jun 23 07:48:35 PM PDT 24 |
| Finished | Jun 23 08:00:53 PM PDT 24 |
| Peak memory | 615152 kb |
| Host | smart-30023b58-7ea0-4820-bbab-71392d7f55b9 |
| User | root |
| Command | /workspace/default/simv +uart_idx=3 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=595283259 -as sert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac e/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_uart_tx_rx_idx3.595283259 |
| Directory | /workspace/0.chip_sw_uart_tx_rx_idx3/latest |
| Test location | /workspace/coverage/default/0.chip_sw_usb_ast_clk_calib.4175865659 |
| Short name | T954 |
| Test name | |
| Test status | |
| Simulation time | 3738569908 ps |
| CPU time | 356.89 seconds |
| Started | Jun 23 07:51:50 PM PDT 24 |
| Finished | Jun 23 07:57:48 PM PDT 24 |
| Peak memory | 607768 kb |
| Host | smart-e9a8d8ab-8c64-4799-b066-bc4ec03111e0 |
| User | root |
| Command | /workspace/default/simv +usb_max_drift=1 +usb_fast_sof=1 +sw_build_device=sim_dv +sw_images=ast_usb_clk_calib:1:new_rules,test_rom:0 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4175865659 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_usb_ast_clk_calib_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_usb_ast_clk_calib.4175865659 |
| Directory | /workspace/0.chip_sw_usb_ast_clk_calib/latest |
| Test location | /workspace/coverage/default/0.chip_sw_usbdev_dpi.2587186989 |
| Short name | T33 |
| Test name | |
| Test status | |
| Simulation time | 12558007750 ps |
| CPU time | 3173.25 seconds |
| Started | Jun 23 07:48:13 PM PDT 24 |
| Finished | Jun 23 08:41:07 PM PDT 24 |
| Peak memory | 607116 kb |
| Host | smart-34fb05ed-7d09-4b08-8ee8-b845bf2587ee |
| User | root |
| Command | /workspace/default/simv +uart_idx=0 +calibrate_usb_clk=1 +sw_test_timeout_ns=30_000_000 +sw_build_device=sim_dv +sw_images=usbdev_test:1:new_rules,tes t_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +nt b_random_seed=2587186989 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_usbdev_dpi_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_usbdev_dpi.2587186989 |
| Directory | /workspace/0.chip_sw_usbdev_dpi/latest |
| Test location | /workspace/coverage/default/0.chip_sw_usbdev_pincfg.1859699057 |
| Short name | T38 |
| Test name | |
| Test status | |
| Simulation time | 31453654540 ps |
| CPU time | 6983.75 seconds |
| Started | Jun 23 07:48:43 PM PDT 24 |
| Finished | Jun 23 09:45:08 PM PDT 24 |
| Peak memory | 607876 kb |
| Host | smart-0f4c6f5e-c39d-49b5-8f0e-d2a04c6e9996 |
| User | root |
| Command | /workspace/default/simv +uart_idx=0 +calibrate_usb_clk=1 +sw_test_timeout_ns=100_000_000 +sw_build_device=sim_dv +sw_images=usbdev_pincfg_test:1:new_r ules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim .tcl +ntb_random_seed=1859699057 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_usbdev_dpi_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_usbdev_pincfg.1859699057 |
| Directory | /workspace/0.chip_sw_usbdev_pincfg/latest |
| Test location | /workspace/coverage/default/0.chip_sw_usbdev_pullup.59046225 |
| Short name | T32 |
| Test name | |
| Test status | |
| Simulation time | 2510269134 ps |
| CPU time | 253.6 seconds |
| Started | Jun 23 07:53:07 PM PDT 24 |
| Finished | Jun 23 07:57:21 PM PDT 24 |
| Peak memory | 606672 kb |
| Host | smart-3cc353dc-c6a0-4b60-86bb-b75a5954632c |
| User | root |
| Command | /workspace/default/simv +uart_idx=0 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=usbdev_pullup_test:1:new_rules,test_rom:0 +cdc_instrumenta tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59046225 - assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_usbdev_dpi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_usbdev_pullup.59046225 |
| Directory | /workspace/0.chip_sw_usbdev_pullup/latest |
| Test location | /workspace/coverage/default/0.chip_sw_usbdev_setuprx.2679750455 |
| Short name | T289 |
| Test name | |
| Test status | |
| Simulation time | 3684824984 ps |
| CPU time | 582.08 seconds |
| Started | Jun 23 07:48:29 PM PDT 24 |
| Finished | Jun 23 07:58:12 PM PDT 24 |
| Peak memory | 606460 kb |
| Host | smart-6b288f4d-3c25-493c-97f3-48b391a06911 |
| User | root |
| Command | /workspace/default/simv +uart_idx=0 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=usbdev_setuprx_test:1:new_rules,test_rom:0 +cdc_instrument ation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=267975045 5 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_usbdev_dpi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_usbdev_setuprx.2679750455 |
| Directory | /workspace/0.chip_sw_usbdev_setuprx/latest |
| Test location | /workspace/coverage/default/0.chip_sw_usbdev_stream.3923677813 |
| Short name | T1000 |
| Test name | |
| Test status | |
| Simulation time | 18755934760 ps |
| CPU time | 4534.52 seconds |
| Started | Jun 23 07:48:44 PM PDT 24 |
| Finished | Jun 23 09:04:20 PM PDT 24 |
| Peak memory | 607148 kb |
| Host | smart-705ffc9b-6918-4f50-b2f2-360b9f9b302a |
| User | root |
| Command | /workspace/default/simv +uart_idx=0 +calibrate_usb_clk=1 +sw_test_timeout_ns=60_000_000 +sw_build_device=sim_dv +sw_images=usbdev_stream_test:1:new_ru les,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim. tcl +ntb_random_seed=3923677813 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_usbdev_stream_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_usbdev_stream.3923677813 |
| Directory | /workspace/0.chip_sw_usbdev_stream/latest |
| Test location | /workspace/coverage/default/0.chip_sw_usbdev_vbus.2271947665 |
| Short name | T1250 |
| Test name | |
| Test status | |
| Simulation time | 3654672232 ps |
| CPU time | 282.99 seconds |
| Started | Jun 23 07:49:53 PM PDT 24 |
| Finished | Jun 23 07:54:38 PM PDT 24 |
| Peak memory | 606888 kb |
| Host | smart-9221a9bc-4c52-4912-bb11-cadd0ffb12d7 |
| User | root |
| Command | /workspace/default/simv +uart_idx=0 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=usbdev_vbus_test:1:new_rules,test_rom:0 +cdc_instrumentati on_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2271947665 - assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_usbdev_dpi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_usbdev_vbus.2271947665 |
| Directory | /workspace/0.chip_sw_usbdev_vbus/latest |
| Test location | /workspace/coverage/default/0.chip_tap_straps_dev.3608279044 |
| Short name | T1070 |
| Test name | |
| Test status | |
| Simulation time | 2865631657 ps |
| CPU time | 144.89 seconds |
| Started | Jun 23 07:49:55 PM PDT 24 |
| Finished | Jun 23 07:52:21 PM PDT 24 |
| Peak memory | 617392 kb |
| Host | smart-719b984f-8b2d-40b5-8895-1de6daba17a4 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStDev +create_jtag_riscv_map=1 +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:test_in_rom: new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=3608279044 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_tap_straps_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_tap_straps_dev.3608279044 |
| Directory | /workspace/0.chip_tap_straps_dev/latest |
| Test location | /workspace/coverage/default/0.chip_tap_straps_prod.573762975 |
| Short name | T216 |
| Test name | |
| Test status | |
| Simulation time | 10024493795 ps |
| CPU time | 1159.02 seconds |
| Started | Jun 23 07:51:01 PM PDT 24 |
| Finished | Jun 23 08:10:21 PM PDT 24 |
| Peak memory | 620180 kb |
| Host | smart-6ca97b47-bd49-46b5-b395-a8bd215a49cf |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStProd +create_jtag_riscv_map=1 +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:test_in_rom :new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=573762975 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_tap_straps_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_tap_straps_prod.573762975 |
| Directory | /workspace/0.chip_tap_straps_prod/latest |
| Test location | /workspace/coverage/default/0.chip_tap_straps_rma.1932155803 |
| Short name | T66 |
| Test name | |
| Test status | |
| Simulation time | 8269191212 ps |
| CPU time | 910.58 seconds |
| Started | Jun 23 07:50:24 PM PDT 24 |
| Finished | Jun 23 08:05:34 PM PDT 24 |
| Peak memory | 622280 kb |
| Host | smart-f48d9b8b-71ed-447b-8a91-af1c10a66c23 |
| User | root |
| Command | /workspace/default/simv +create_jtag_riscv_map=1 +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:test_in_rom:new_rules +cdc_instrumentation _enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1932155803 -as sert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_tap_straps_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/c overage/default.vdb -cm_log /dev/null -cm_name 0.chip_tap_straps_rma.1932155803 |
| Directory | /workspace/0.chip_tap_straps_rma/latest |
| Test location | /workspace/coverage/default/0.chip_tap_straps_testunlock0.4100032995 |
| Short name | T67 |
| Test name | |
| Test status | |
| Simulation time | 4905189309 ps |
| CPU time | 471.8 seconds |
| Started | Jun 23 07:52:38 PM PDT 24 |
| Finished | Jun 23 08:00:30 PM PDT 24 |
| Peak memory | 620188 kb |
| Host | smart-008da1cc-f2a0-45cd-a002-0b1569cb48c6 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStTestUnlocked0 +create_jtag_riscv_map=1 +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:te st_in_rom:new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4100032995 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_tap_straps_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_tap_straps_testunlock0.4100032995 |
| Directory | /workspace/0.chip_tap_straps_testunlock0/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_asm_init_dev.4130181980 |
| Short name | T955 |
| Test name | |
| Test status | |
| Simulation time | 15844006036 ps |
| CPU time | 3621.12 seconds |
| Started | Jun 23 07:58:56 PM PDT 24 |
| Finished | Jun 23 08:59:19 PM PDT 24 |
| Peak memory | 606712 kb |
| Host | smart-34751585-ed2d-4427-a9ae-465212710069 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeCustom +sw_test_timeout_ns=20000000 +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_prod _key_0:1:ot_flash_binary,otp_img_e2e_bootstrap_entry_dev:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4130181980 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_S EQ=chip_sw_rom_e2e_asm_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_asm_init_dev.4130181980 |
| Directory | /workspace/0.rom_e2e_asm_init_dev/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_asm_init_prod.2183822783 |
| Short name | T1297 |
| Test name | |
| Test status | |
| Simulation time | 16440744276 ps |
| CPU time | 3881.4 seconds |
| Started | Jun 23 07:59:46 PM PDT 24 |
| Finished | Jun 23 09:04:28 PM PDT 24 |
| Peak memory | 608276 kb |
| Host | smart-e5726a2e-4769-42db-908e-ed9a4ce3d1f1 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeCustom +sw_test_timeout_ns=20000000 +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_prod _key_0:1:ot_flash_binary,otp_img_e2e_bootstrap_entry_prod:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2183822783 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_ SEQ=chip_sw_rom_e2e_asm_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_asm_init_prod.2183822783 |
| Directory | /workspace/0.rom_e2e_asm_init_prod/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_asm_init_prod_end.139510479 |
| Short name | T363 |
| Test name | |
| Test status | |
| Simulation time | 15865193116 ps |
| CPU time | 4588.68 seconds |
| Started | Jun 23 07:58:45 PM PDT 24 |
| Finished | Jun 23 09:15:15 PM PDT 24 |
| Peak memory | 606780 kb |
| Host | smart-30dc040a-4bad-4fa9-ba30-16348e9d53e6 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeCustom +sw_test_timeout_ns=20000000 +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_prod _key_0:1:ot_flash_binary,otp_img_e2e_bootstrap_entry_prod_end:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=139510479 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TE ST_SEQ=chip_sw_rom_e2e_asm_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n ame 0.rom_e2e_asm_init_prod_end.139510479 |
| Directory | /workspace/0.rom_e2e_asm_init_prod_end/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_asm_init_rma.1870896744 |
| Short name | T1158 |
| Test name | |
| Test status | |
| Simulation time | 14939155260 ps |
| CPU time | 3501.37 seconds |
| Started | Jun 23 07:59:15 PM PDT 24 |
| Finished | Jun 23 08:57:38 PM PDT 24 |
| Peak memory | 606780 kb |
| Host | smart-1be75467-ac72-492d-b688-e57e60a509d7 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeCustom +sw_test_timeout_ns=20000000 +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_prod _key_0:1:ot_flash_binary,otp_img_e2e_bootstrap_entry_rma:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1870896744 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_S EQ=chip_sw_rom_e2e_asm_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_asm_init_rma.1870896744 |
| Directory | /workspace/0.rom_e2e_asm_init_rma/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_asm_init_test_unlocked0.3166040886 |
| Short name | T979 |
| Test name | |
| Test status | |
| Simulation time | 11687546927 ps |
| CPU time | 3401.22 seconds |
| Started | Jun 23 07:59:12 PM PDT 24 |
| Finished | Jun 23 08:55:54 PM PDT 24 |
| Peak memory | 608344 kb |
| Host | smart-a6eda089-520b-44df-bc2a-6246375774ec |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeCustom +sw_test_timeout_ns=410_000_000 +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_p rod_key_0:1:ot_flash_binary,otp_img_e2e_bootstrap_entry_test_unlocked0:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY =UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3166040886 -assert nopostproc +UVM_TESTNAME=chip_base_te st +UVM_TEST_SEQ=chip_sw_rom_e2e_asm_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/ null -cm_name 0.rom_e2e_asm_init_test_unlocked0.3166040886 |
| Directory | /workspace/0.rom_e2e_asm_init_test_unlocked0/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_bad_b_good_prod.1234909831 |
| Short name | T384 |
| Test name | |
| Test status | |
| Simulation time | 24748686800 ps |
| CPU time | 5586.71 seconds |
| Started | Jun 23 07:58:37 PM PDT 24 |
| Finished | Jun 23 09:31:45 PM PDT 24 |
| Peak memory | 608164 kb |
| Host | smart-8a6ccfb2-fa2f-4e03-941d-bb52beca7789 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_corrupted:1: ot_flash_binary:signed:fake_ecdsa_prod_key_0,empty_test_slot_b_fake_ecdsa_prod_key_0:2:ot_flash_binary,otp_img_boot_policy_valid_prod:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=1234909831 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_boot_policy_valid_a_bad_b_good_prod.1234909831 |
| Directory | /workspace/0.rom_e2e_boot_policy_valid_a_bad_b_good_prod/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_bad_b_good_prod_end.2623276850 |
| Short name | T364 |
| Test name | |
| Test status | |
| Simulation time | 25024033222 ps |
| CPU time | 6181.08 seconds |
| Started | Jun 23 07:58:48 PM PDT 24 |
| Finished | Jun 23 09:41:50 PM PDT 24 |
| Peak memory | 608152 kb |
| Host | smart-0ea1f750-d161-42e9-a149-1f6cf288ff69 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_corrupted:1: ot_flash_binary:signed:fake_ecdsa_prod_key_0,empty_test_slot_b_fake_ecdsa_prod_key_0:2:ot_flash_binary,otp_img_boot_policy_valid_prod_end:4,mask_r om:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r andom_seed=2623276850 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_boot_policy_valid_a_bad_b_good_prod_end.2623276850 |
| Directory | /workspace/0.rom_e2e_boot_policy_valid_a_bad_b_good_prod_end/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_bad_b_good_rma.2906343387 |
| Short name | T383 |
| Test name | |
| Test status | |
| Simulation time | 23647548078 ps |
| CPU time | 5154.68 seconds |
| Started | Jun 23 07:58:01 PM PDT 24 |
| Finished | Jun 23 09:23:56 PM PDT 24 |
| Peak memory | 607044 kb |
| Host | smart-86167512-845d-4dc6-a299-4f2f7cd48d8e |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_corrupted:1: ot_flash_binary:signed:fake_ecdsa_prod_key_0,empty_test_slot_b_fake_ecdsa_prod_key_0:2:ot_flash_binary,otp_img_boot_policy_valid_rma:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=2906343387 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_boot_policy_valid_a_bad_b_good_rma.2906343387 |
| Directory | /workspace/0.rom_e2e_boot_policy_valid_a_bad_b_good_rma/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0.683811973 |
| Short name | T1136 |
| Test name | |
| Test status | |
| Simulation time | 18563218544 ps |
| CPU time | 5221.64 seconds |
| Started | Jun 23 08:01:22 PM PDT 24 |
| Finished | Jun 23 09:28:24 PM PDT 24 |
| Peak memory | 607072 kb |
| Host | smart-d19d4668-8849-4d95-850a-24890d7f535b |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=410_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_corrupted:1: ot_flash_binary:signed:fake_ecdsa_prod_key_0,empty_test_slot_b_fake_ecdsa_prod_key_0:2:ot_flash_binary,otp_img_boot_policy_valid_test_unlocked0:4, mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=683811973 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0.683811973 |
| Directory | /workspace/0.rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_bad_dev.2372364681 |
| Short name | T376 |
| Test name | |
| Test status | |
| Simulation time | 15428570488 ps |
| CPU time | 3561.26 seconds |
| Started | Jun 23 08:02:41 PM PDT 24 |
| Finished | Jun 23 09:02:03 PM PDT 24 |
| Peak memory | 608340 kb |
| Host | smart-fc41fd88-5cbe-45e1-a75d-964fc5beae2a |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_p rod_key_0:1:ot_flash_binary,empty_test_slot_b_corrupted:2:ot_flash_binary:signed:fake_ecdsa_prod_key_0,otp_img_boot_policy_valid_dev:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=2372364681 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_boot_policy_valid_a_good_b_bad_dev.2372364681 |
| Directory | /workspace/0.rom_e2e_boot_policy_valid_a_good_b_bad_dev/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_bad_prod.3026351209 |
| Short name | T1123 |
| Test name | |
| Test status | |
| Simulation time | 15524171432 ps |
| CPU time | 3497.86 seconds |
| Started | Jun 23 07:57:03 PM PDT 24 |
| Finished | Jun 23 08:55:22 PM PDT 24 |
| Peak memory | 608168 kb |
| Host | smart-c4cdff23-dd0f-45db-8e17-5d9ccbee3760 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_p rod_key_0:1:ot_flash_binary,empty_test_slot_b_corrupted:2:ot_flash_binary:signed:fake_ecdsa_prod_key_0,otp_img_boot_policy_valid_prod:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=3026351209 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_boot_policy_valid_a_good_b_bad_prod.3026351209 |
| Directory | /workspace/0.rom_e2e_boot_policy_valid_a_good_b_bad_prod/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_bad_prod_end.3028737545 |
| Short name | T362 |
| Test name | |
| Test status | |
| Simulation time | 16023608560 ps |
| CPU time | 4322.08 seconds |
| Started | Jun 23 08:00:48 PM PDT 24 |
| Finished | Jun 23 09:12:51 PM PDT 24 |
| Peak memory | 607048 kb |
| Host | smart-e0a0de3b-f8d8-4dbb-8b69-cd4913ca41d3 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_p rod_key_0:1:ot_flash_binary,empty_test_slot_b_corrupted:2:ot_flash_binary:signed:fake_ecdsa_prod_key_0,otp_img_boot_policy_valid_prod_end:4,mask_r om:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r andom_seed=3028737545 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_boot_policy_valid_a_good_b_bad_prod_end.3028737545 |
| Directory | /workspace/0.rom_e2e_boot_policy_valid_a_good_b_bad_prod_end/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_bad_rma.1632164628 |
| Short name | T1068 |
| Test name | |
| Test status | |
| Simulation time | 15225563448 ps |
| CPU time | 4208.85 seconds |
| Started | Jun 23 08:00:47 PM PDT 24 |
| Finished | Jun 23 09:10:57 PM PDT 24 |
| Peak memory | 607060 kb |
| Host | smart-543f62ab-4aa1-4cc1-8fd8-288bdf48eb55 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_p rod_key_0:1:ot_flash_binary,empty_test_slot_b_corrupted:2:ot_flash_binary:signed:fake_ecdsa_prod_key_0,otp_img_boot_policy_valid_rma:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=1632164628 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_boot_policy_valid_a_good_b_bad_rma.1632164628 |
| Directory | /workspace/0.rom_e2e_boot_policy_valid_a_good_b_bad_rma/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0.42237612 |
| Short name | T938 |
| Test name | |
| Test status | |
| Simulation time | 12296696270 ps |
| CPU time | 2836.45 seconds |
| Started | Jun 23 07:57:03 PM PDT 24 |
| Finished | Jun 23 08:44:20 PM PDT 24 |
| Peak memory | 608148 kb |
| Host | smart-8d9a02c7-943f-4622-98d7-b0342f43e809 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=410_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_p rod_key_0:1:ot_flash_binary,empty_test_slot_b_corrupted:2:ot_flash_binary:signed:fake_ecdsa_prod_key_0,otp_img_boot_policy_valid_test_unlocked0:4, mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42237612 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0.42237612 |
| Directory | /workspace/0.rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_good_dev.2588355704 |
| Short name | T983 |
| Test name | |
| Test status | |
| Simulation time | 15026505470 ps |
| CPU time | 4739.27 seconds |
| Started | Jun 23 07:57:22 PM PDT 24 |
| Finished | Jun 23 09:16:23 PM PDT 24 |
| Peak memory | 607884 kb |
| Host | smart-85351ec4-4d14-4b0b-a423-5977c832c3e6 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_p rod_key_0:1:ot_flash_binary,empty_test_slot_b_fake_ecdsa_prod_key_0:2:ot_flash_binary,otp_img_boot_policy_valid_dev:4,mask_rom:0 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2588355704 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/c overage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_boot_policy_valid_a_good_b_good_dev.2588355704 |
| Directory | /workspace/0.rom_e2e_boot_policy_valid_a_good_b_good_dev/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_good_prod.2351556336 |
| Short name | T1052 |
| Test name | |
| Test status | |
| Simulation time | 15828912824 ps |
| CPU time | 4305.96 seconds |
| Started | Jun 23 08:01:16 PM PDT 24 |
| Finished | Jun 23 09:13:03 PM PDT 24 |
| Peak memory | 608120 kb |
| Host | smart-767930b5-55ff-4e23-898c-3a62444b0d2b |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_p rod_key_0:1:ot_flash_binary,empty_test_slot_b_fake_ecdsa_prod_key_0:2:ot_flash_binary,otp_img_boot_policy_valid_prod:4,mask_rom:0 +cdc_instrumenta tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2351556336 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/ coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_boot_policy_valid_a_good_b_good_prod.2351556336 |
| Directory | /workspace/0.rom_e2e_boot_policy_valid_a_good_b_good_prod/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_good_prod_end.2630277002 |
| Short name | T1305 |
| Test name | |
| Test status | |
| Simulation time | 16171181776 ps |
| CPU time | 4091.54 seconds |
| Started | Jun 23 07:56:52 PM PDT 24 |
| Finished | Jun 23 09:05:05 PM PDT 24 |
| Peak memory | 607888 kb |
| Host | smart-33deeaf9-9185-402d-a28b-9438487a4d06 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_p rod_key_0:1:ot_flash_binary,empty_test_slot_b_fake_ecdsa_prod_key_0:2:ot_flash_binary,otp_img_boot_policy_valid_prod_end:4,mask_rom:0 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=263027 7002 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_boot_policy_valid_a_good_b_good_prod_end.2630277002 |
| Directory | /workspace/0.rom_e2e_boot_policy_valid_a_good_b_good_prod_end/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_good_rma.3385187469 |
| Short name | T1176 |
| Test name | |
| Test status | |
| Simulation time | 15129716420 ps |
| CPU time | 4174.12 seconds |
| Started | Jun 23 07:58:02 PM PDT 24 |
| Finished | Jun 23 09:07:37 PM PDT 24 |
| Peak memory | 608108 kb |
| Host | smart-3ccc2e22-9063-4d9a-81a6-4d31f6c21509 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_p rod_key_0:1:ot_flash_binary,empty_test_slot_b_fake_ecdsa_prod_key_0:2:ot_flash_binary,otp_img_boot_policy_valid_rma:4,mask_rom:0 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3385187469 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/c overage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_boot_policy_valid_a_good_b_good_rma.3385187469 |
| Directory | /workspace/0.rom_e2e_boot_policy_valid_a_good_b_good_rma/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0.808500312 |
| Short name | T999 |
| Test name | |
| Test status | |
| Simulation time | 12246810500 ps |
| CPU time | 3691.8 seconds |
| Started | Jun 23 07:57:43 PM PDT 24 |
| Finished | Jun 23 08:59:16 PM PDT 24 |
| Peak memory | 608088 kb |
| Host | smart-9d9d0c71-42ef-437e-a74f-f95522c78df1 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=410_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_p rod_key_0:1:ot_flash_binary,empty_test_slot_b_fake_ecdsa_prod_key_0:2:ot_flash_binary,otp_img_boot_policy_valid_test_unlocked0:4,mask_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 808500312 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0.808500312 |
| Directory | /workspace/0.rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_jtag_inject_dev.2066483852 |
| Short name | T246 |
| Test name | |
| Test status | |
| Simulation time | 32384409905 ps |
| CPU time | 2691.74 seconds |
| Started | Jun 23 07:56:30 PM PDT 24 |
| Finished | Jun 23 08:41:23 PM PDT 24 |
| Peak memory | 618796 kb |
| Host | smart-11e34659-5371-4fa3-bb41-40be8167370c |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=40_000_000 +use_jtag_dmi=1 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=img_dev_exec_di sabled:4,sram_program:5,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2066483852 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_e2e_jtag_inject_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_jtag_inject_dev.2066483852 |
| Directory | /workspace/0.rom_e2e_jtag_inject_dev/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_jtag_inject_rma.3805615145 |
| Short name | T73 |
| Test name | |
| Test status | |
| Simulation time | 30688853937 ps |
| CPU time | 3429.68 seconds |
| Started | Jun 23 07:54:10 PM PDT 24 |
| Finished | Jun 23 08:51:21 PM PDT 24 |
| Peak memory | 617940 kb |
| Host | smart-29464f43-e716-4922-8b03-eeebed13d403 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=40_000_000 +use_jtag_dmi=1 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=img_rma_exec_di sabled:4,sram_program:5,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3805615145 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_e2e_jtag_inject_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_jtag_inject_rma.3805615145 |
| Directory | /workspace/0.rom_e2e_jtag_inject_rma/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_jtag_inject_test_unlocked0.1300400211 |
| Short name | T247 |
| Test name | |
| Test status | |
| Simulation time | 44994565119 ps |
| CPU time | 3407.92 seconds |
| Started | Jun 23 07:58:18 PM PDT 24 |
| Finished | Jun 23 08:55:07 PM PDT 24 |
| Peak memory | 619716 kb |
| Host | smart-2bdc0bdd-01aa-4ae4-9007-93aa436aece4 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=40_000_000 +use_jtag_dmi=1 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=img_test_unlock ed0_exec_disabled:4,sram_program:5,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1300400211 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_e2e_jtag_ inject_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_jtag_inject _test_unlocked0.1300400211 |
| Directory | /workspace/0.rom_e2e_jtag_inject_test_unlocked0/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_keymgr_init_rom_ext_invalid_meas.323523549 |
| Short name | T951 |
| Test name | |
| Test status | |
| Simulation time | 15390892600 ps |
| CPU time | 3857.97 seconds |
| Started | Jun 23 07:57:44 PM PDT 24 |
| Finished | Jun 23 09:02:02 PM PDT 24 |
| Peak memory | 606908 kb |
| Host | smart-9ddf2d07-0c09-4a4b-8a51-0aef148bb0d3 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=40_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=rom_e2e_keymgr_init_otp_invalid _meas:1:new_rules,otp_img_keymgr_otp_invalid_meas:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=323523549 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_ sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_keymgr_ini t_rom_ext_invalid_meas.323523549 |
| Directory | /workspace/0.rom_e2e_keymgr_init_rom_ext_invalid_meas/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_keymgr_init_rom_ext_meas.2252759076 |
| Short name | T952 |
| Test name | |
| Test status | |
| Simulation time | 16070017100 ps |
| CPU time | 3520.48 seconds |
| Started | Jun 23 07:57:51 PM PDT 24 |
| Finished | Jun 23 08:56:32 PM PDT 24 |
| Peak memory | 608176 kb |
| Host | smart-d7cdc463-df94-46ed-a0e6-3471e286b825 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=40_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=rom_e2e_keymgr_init_otp_meas:1: new_rules,otp_img_keymgr_otp_meas:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2252759076 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_keymgr_init_rom_ext_meas.2252759076 |
| Directory | /workspace/0.rom_e2e_keymgr_init_rom_ext_meas/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_keymgr_init_rom_ext_no_meas.3044640506 |
| Short name | T1178 |
| Test name | |
| Test status | |
| Simulation time | 15908011124 ps |
| CPU time | 4069.03 seconds |
| Started | Jun 23 08:00:02 PM PDT 24 |
| Finished | Jun 23 09:07:52 PM PDT 24 |
| Peak memory | 608092 kb |
| Host | smart-aeba2888-2fe4-46ae-8104-57be061c9e98 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=40_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=rom_e2e_keymgr_init_otp_no_meas :1:new_rules,otp_img_keymgr_otp_no_meas:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3044640506 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_keymgr_init_rom_ext _no_meas.3044640506 |
| Directory | /workspace/0.rom_e2e_keymgr_init_rom_ext_no_meas/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_smoke.4249011476 |
| Short name | T973 |
| Test name | |
| Test status | |
| Simulation time | 15119255900 ps |
| CPU time | 4980.95 seconds |
| Started | Jun 23 07:57:01 PM PDT 24 |
| Finished | Jun 23 09:20:04 PM PDT 24 |
| Peak memory | 608092 kb |
| Host | smart-f7ed4aa4-e6cd-4d07-9f8a-8508e0c83253 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=40000000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=rom_e2e_smoke:1:new_rules,otp_img _secret2_locked_rma:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_to p/hw/dv/tools/sim.tcl +ntb_random_seed=4249011476 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_smoke.4249011476 |
| Directory | /workspace/0.rom_e2e_smoke/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_static_critical.3558813285 |
| Short name | T1122 |
| Test name | |
| Test status | |
| Simulation time | 16997192028 ps |
| CPU time | 5003.12 seconds |
| Started | Jun 23 08:02:27 PM PDT 24 |
| Finished | Jun 23 09:25:51 PM PDT 24 |
| Peak memory | 606824 kb |
| Host | smart-1ba1bf70-d3f9-4cfa-8b78-2596a32bd1ed |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=40000000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=rom_e2e_static_critical:1:new_rul es,otp_img_secret2_locked_rma:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3558813285 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_static_critical.3558813285 |
| Directory | /workspace/0.rom_e2e_static_critical/latest |
| Test location | /workspace/coverage/default/0.rom_keymgr_functest.2229161384 |
| Short name | T1067 |
| Test name | |
| Test status | |
| Simulation time | 5758627240 ps |
| CPU time | 662.67 seconds |
| Started | Jun 23 07:53:42 PM PDT 24 |
| Finished | Jun 23 08:04:45 PM PDT 24 |
| Peak memory | 608036 kb |
| Host | smart-3ec3c9fd-7f01-44df-ab14-454f03be4e00 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=10_000_000 +sw_build_device=sim_dv +sw_images=keymgr_functest:1:new_rules,test_rom:0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2229161384 -ass ert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 0.rom_keymgr_functest.2229161384 |
| Directory | /workspace/0.rom_keymgr_functest/latest |
| Test location | /workspace/coverage/default/0.rom_volatile_raw_unlock.2842900714 |
| Short name | T1054 |
| Test name | |
| Test status | |
| Simulation time | 2566912102 ps |
| CPU time | 101.05 seconds |
| Started | Jun 23 07:52:45 PM PDT 24 |
| Finished | Jun 23 07:54:27 PM PDT 24 |
| Peak memory | 613552 kb |
| Host | smart-c9ba961f-fed2-434c-8632-9ad4e09788ed |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=200_000_000 +use_otp_image=OtpTypeLcStRaw +chip_clock_source=ChipClockSourceExternal48Mhz +rom_prod_mode=1 +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_test_key_0:1:ot_flash_binary,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2842900714 -assert nopostproc +UVM_ TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_volatile_raw_unlock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag e/default.vdb -cm_log /dev/null -cm_name 0.rom_volatile_raw_unlock.2842900714 |
| Directory | /workspace/0.rom_volatile_raw_unlock/latest |
| Test location | /workspace/coverage/default/1.chip_jtag_mem_access.3813473439 |
| Short name | T75 |
| Test name | |
| Test status | |
| Simulation time | 13736176971 ps |
| CPU time | 1509.25 seconds |
| Started | Jun 23 07:55:20 PM PDT 24 |
| Finished | Jun 23 08:20:30 PM PDT 24 |
| Peak memory | 605692 kb |
| Host | smart-1960e055-5c1b-46bd-bea6-5174463ab890 |
| User | root |
| Command | /workspace/default/simv +create_jtag_riscv_map=1 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3813473439 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_jtag_ mem_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_jtag_mem_access.3 813473439 |
| Directory | /workspace/1.chip_jtag_mem_access/latest |
| Test location | /workspace/coverage/default/1.chip_rv_dm_ndm_reset_req.219204703 |
| Short name | T398 |
| Test name | |
| Test status | |
| Simulation time | 5000864264 ps |
| CPU time | 575.24 seconds |
| Started | Jun 23 08:03:04 PM PDT 24 |
| Finished | Jun 23 08:12:40 PM PDT 24 |
| Peak memory | 617660 kb |
| Host | smart-272f8341-5d3b-4c40-8d32-6b8c01125452 |
| User | root |
| Command | /workspace/default/simv +en_scb_tl_err_chk=0 +use_jtag_dmi=1 +sw_build_device=sim_dv +sw_images=rv_dm_ndm_reset_req_rma:1:new_rules,test_rom:0 +cdc_in strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2 19204703 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_rv_dm_ndm_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_rv_dm_ndm_reset_req.219204703 |
| Directory | /workspace/1.chip_rv_dm_ndm_reset_req/latest |
| Test location | /workspace/coverage/default/1.chip_sival_flash_info_access.3149954804 |
| Short name | T90 |
| Test name | |
| Test status | |
| Simulation time | 3791040536 ps |
| CPU time | 304.1 seconds |
| Started | Jun 23 07:54:28 PM PDT 24 |
| Finished | Jun 23 07:59:33 PM PDT 24 |
| Peak memory | 606940 kb |
| Host | smart-e3be23bc-f066-48f0-b307-7a4bc612dd7c |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStTestUnlocked0 +sw_build_device=sim_dv +sw_images=flash_ctrl_info_access_lc:1:new_rules,test_rom:0 +c dc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_s eed=3149954804 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sival_flash_info_access.3149954804 |
| Directory | /workspace/1.chip_sival_flash_info_access/latest |
| Test location | /workspace/coverage/default/1.chip_sw_adc_ctrl_sleep_debug_cable_wakeup.1955660457 |
| Short name | T339 |
| Test name | |
| Test status | |
| Simulation time | 17963694304 ps |
| CPU time | 517.84 seconds |
| Started | Jun 23 07:58:39 PM PDT 24 |
| Finished | Jun 23 08:07:18 PM PDT 24 |
| Peak memory | 615232 kb |
| Host | smart-af2ffe39-3a18-47e1-94a6-79b9a93d775f |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=adc_ctrl_sleep_debug_cable_wakeup_test:1:new_rules,test_rom: 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand om_seed=1955660457 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_adc_ctrl_sleep_debug_cable_wakeup_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_adc_ctrl_sleep_debug_cable_wakeup.1955660457 |
| Directory | /workspace/1.chip_sw_adc_ctrl_sleep_debug_cable_wakeup/latest |
| Test location | /workspace/coverage/default/1.chip_sw_aes_enc_jitter_en.2369113776 |
| Short name | T1173 |
| Test name | |
| Test status | |
| Simulation time | 2996796092 ps |
| CPU time | 306.82 seconds |
| Started | Jun 23 07:57:40 PM PDT 24 |
| Finished | Jun 23 08:02:47 PM PDT 24 |
| Peak memory | 606884 kb |
| Host | smart-8895e83b-fd04-4296-a48c-bbbbb19dc56e |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=26_000_000 +en_jitter=1 +sw_build_device=sim_dv +sw_images=aes_smoketest:1:new_rules,test_rom:0 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2369 113776 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work space/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_aes_enc_jitter_en.2369113776 |
| Directory | /workspace/1.chip_sw_aes_enc_jitter_en/latest |
| Test location | /workspace/coverage/default/1.chip_sw_aes_enc_jitter_en_reduced_freq.58730862 |
| Short name | T1157 |
| Test name | |
| Test status | |
| Simulation time | 3212790287 ps |
| CPU time | 250.26 seconds |
| Started | Jun 23 08:03:25 PM PDT 24 |
| Finished | Jun 23 08:07:36 PM PDT 24 |
| Peak memory | 606948 kb |
| Host | smart-25f4d902-7a51-44e3-9db7-317bdfcc7496 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=26_000_000 +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=aes_smoketest:1:new_rules, test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58730862 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_aes_enc_jitter_en_reduced_freq.58730862 |
| Directory | /workspace/1.chip_sw_aes_enc_jitter_en_reduced_freq/latest |
| Test location | /workspace/coverage/default/1.chip_sw_aes_entropy.3113650552 |
| Short name | T986 |
| Test name | |
| Test status | |
| Simulation time | 3428729182 ps |
| CPU time | 238.24 seconds |
| Started | Jun 23 07:58:09 PM PDT 24 |
| Finished | Jun 23 08:02:07 PM PDT 24 |
| Peak memory | 606772 kb |
| Host | smart-a557b8be-e2db-47fb-86c4-1763595ea18b |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=15_000_000 +sw_build_device=sim_dv +sw_images=aes_entropy_test:1:new_rules,test_rom:0 +cdc_instrumentation _enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3113650552 -as sert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove rage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_aes_entropy.3113650552 |
| Directory | /workspace/1.chip_sw_aes_entropy/latest |
| Test location | /workspace/coverage/default/1.chip_sw_aes_idle.3239508889 |
| Short name | T259 |
| Test name | |
| Test status | |
| Simulation time | 2391415044 ps |
| CPU time | 240.11 seconds |
| Started | Jun 23 07:59:49 PM PDT 24 |
| Finished | Jun 23 08:03:50 PM PDT 24 |
| Peak memory | 607356 kb |
| Host | smart-b076a419-b7b8-4dc4-9b8f-e900cff6f6d2 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=25_000_000 +sw_build_device=sim_dv +sw_images=aes_idle_test:1:new_rules,test_rom:0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3239508889 -asser t nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag e/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_aes_idle.3239508889 |
| Directory | /workspace/1.chip_sw_aes_idle/latest |
| Test location | /workspace/coverage/default/1.chip_sw_aes_masking_off.3265872113 |
| Short name | T1101 |
| Test name | |
| Test status | |
| Simulation time | 3081092181 ps |
| CPU time | 395.4 seconds |
| Started | Jun 23 07:57:03 PM PDT 24 |
| Finished | Jun 23 08:03:39 PM PDT 24 |
| Peak memory | 607888 kb |
| Host | smart-506eecb9-e52e-4ad1-a6e7-686af90bd7eb |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=aes_masking_off_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3265872113 -assert nopostproc +UVM_TESTNA ME=chip_base_test +UVM_TEST_SEQ=chip_sw_aes_masking_off_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_aes_masking_off.3265872113 |
| Directory | /workspace/1.chip_sw_aes_masking_off/latest |
| Test location | /workspace/coverage/default/1.chip_sw_aes_smoketest.2420789833 |
| Short name | T934 |
| Test name | |
| Test status | |
| Simulation time | 2821907934 ps |
| CPU time | 211.02 seconds |
| Started | Jun 23 08:05:54 PM PDT 24 |
| Finished | Jun 23 08:09:25 PM PDT 24 |
| Peak memory | 607772 kb |
| Host | smart-473bf0c2-7aff-4910-984e-78bfe58db5ee |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=aes_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2420789833 -assert nopostproc +UVM_TESTNAME=chip _base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_aes_smoketest.2420789833 |
| Directory | /workspace/1.chip_sw_aes_smoketest/latest |
| Test location | /workspace/coverage/default/1.chip_sw_alert_handler_entropy.3264091323 |
| Short name | T252 |
| Test name | |
| Test status | |
| Simulation time | 3280396578 ps |
| CPU time | 299.5 seconds |
| Started | Jun 23 07:58:33 PM PDT 24 |
| Finished | Jun 23 08:03:33 PM PDT 24 |
| Peak memory | 607752 kb |
| Host | smart-d0ab8690-060e-4938-9874-03f3d08dbabd |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=alert_handler_entropy_test:1:new_rules,test_ro m:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=3264091323 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_alert_handler_entropy.3264091323 |
| Directory | /workspace/1.chip_sw_alert_handler_entropy/latest |
| Test location | /workspace/coverage/default/1.chip_sw_alert_handler_escalation.1360504183 |
| Short name | T402 |
| Test name | |
| Test status | |
| Simulation time | 4574862760 ps |
| CPU time | 635.28 seconds |
| Started | Jun 23 08:00:27 PM PDT 24 |
| Finished | Jun 23 08:11:03 PM PDT 24 |
| Peak memory | 614156 kb |
| Host | smart-0d6b5ef9-2827-4848-981e-79e42f91f170 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=alert_handler_escalation_test:1:new_rules,test _rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb _random_seed=1360504183 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_alert_handler_escalation_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_alert_handler_escalation.1360504183 |
| Directory | /workspace/1.chip_sw_alert_handler_escalation/latest |
| Test location | /workspace/coverage/default/1.chip_sw_alert_handler_lpg_clkoff.2853457762 |
| Short name | T1062 |
| Test name | |
| Test status | |
| Simulation time | 7884803896 ps |
| CPU time | 1587.6 seconds |
| Started | Jun 23 07:58:58 PM PDT 24 |
| Finished | Jun 23 08:25:26 PM PDT 24 |
| Peak memory | 607980 kb |
| Host | smart-041d775d-7217-46c3-b8da-4633ab37bc80 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +sw_build_device=sim_dv +sw_images=alert_handler_lpg_clkoff_test:1:new_rules,test_r om:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r andom_seed=2853457762 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_alert_handler_lpg_clkoff_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_alert_handler_lpg_clkoff.2853457762 |
| Directory | /workspace/1.chip_sw_alert_handler_lpg_clkoff/latest |
| Test location | /workspace/coverage/default/1.chip_sw_alert_handler_lpg_reset_toggle.1638487510 |
| Short name | T205 |
| Test name | |
| Test status | |
| Simulation time | 8158474602 ps |
| CPU time | 1856.29 seconds |
| Started | Jun 23 07:58:59 PM PDT 24 |
| Finished | Jun 23 08:29:56 PM PDT 24 |
| Peak memory | 607104 kb |
| Host | smart-bfca51b9-8df6-443b-96a6-a6ef5370def7 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +sw_build_device=sim_dv +sw_images=alert_handler_lpg_reset_toggle_test:1:new_rules, test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1638487510 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_alert_handler_shorten_ping_wait_cycle_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_alert_handler_lpg_reset_togg le.1638487510 |
| Directory | /workspace/1.chip_sw_alert_handler_lpg_reset_toggle/latest |
| Test location | /workspace/coverage/default/1.chip_sw_alert_handler_ping_ok.3701620502 |
| Short name | T1089 |
| Test name | |
| Test status | |
| Simulation time | 7834438624 ps |
| CPU time | 1371.63 seconds |
| Started | Jun 23 07:59:16 PM PDT 24 |
| Finished | Jun 23 08:22:08 PM PDT 24 |
| Peak memory | 607060 kb |
| Host | smart-52370a6a-20a0-42dd-8ca7-062df957cc9e |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=24000000 +sw_build_device=sim_dv +sw_images=alert_handler_ping_ok_test:1:new_rules,test_rom:0 +c dc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_s eed=3701620502 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_alert_handler_ping_ok.3701620502 |
| Directory | /workspace/1.chip_sw_alert_handler_ping_ok/latest |
| Test location | /workspace/coverage/default/1.chip_sw_alert_handler_ping_timeout.2235546184 |
| Short name | T251 |
| Test name | |
| Test status | |
| Simulation time | 4229815000 ps |
| CPU time | 527.39 seconds |
| Started | Jun 23 07:58:40 PM PDT 24 |
| Finished | Jun 23 08:07:28 PM PDT 24 |
| Peak memory | 606716 kb |
| Host | smart-963735b6-9ca3-4a81-8ce5-b5e317f5e3d9 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=24000000 +sw_build_device=sim_dv +sw_images=alert_handler_ping_timeout_test:1:new_rules,test_rom :0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=2235546184 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_alert_handler_ping_timeout.2235546184 |
| Directory | /workspace/1.chip_sw_alert_handler_ping_timeout/latest |
| Test location | /workspace/coverage/default/1.chip_sw_alert_handler_reverse_ping_in_deep_sleep.3447181746 |
| Short name | T155 |
| Test name | |
| Test status | |
| Simulation time | 254835628384 ps |
| CPU time | 11655.7 seconds |
| Started | Jun 23 07:58:37 PM PDT 24 |
| Finished | Jun 23 11:12:55 PM PDT 24 |
| Peak memory | 608652 kb |
| Host | smart-d60eeda5-6402-4793-88e9-42b311fb56a4 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=300_000_000 +sw_build_device=sim_dv +sw_images=alert_handler_reverse_ping_in_deep_sleep_test:1:n ew_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3447181746 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_alert_handler_reverse_ping_in_deep_sleep.3447181746 |
| Directory | /workspace/1.chip_sw_alert_handler_reverse_ping_in_deep_sleep/latest |
| Test location | /workspace/coverage/default/1.chip_sw_aon_timer_irq.3695999329 |
| Short name | T350 |
| Test name | |
| Test status | |
| Simulation time | 3776783208 ps |
| CPU time | 426.26 seconds |
| Started | Jun 23 07:57:28 PM PDT 24 |
| Finished | Jun 23 08:04:35 PM PDT 24 |
| Peak memory | 607664 kb |
| Host | smart-5df04dd1-1590-4e03-9859-6e41ed2c41cc |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=aon_timer_irq_test:1:new_rules,test_rom:0 +cdc_instrumentati on_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3695999329 - assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co verage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_aon_timer_irq.3695999329 |
| Directory | /workspace/1.chip_sw_aon_timer_irq/latest |
| Test location | /workspace/coverage/default/1.chip_sw_aon_timer_sleep_wdog_sleep_pause.497561646 |
| Short name | T1085 |
| Test name | |
| Test status | |
| Simulation time | 5604361740 ps |
| CPU time | 301.25 seconds |
| Started | Jun 23 07:57:55 PM PDT 24 |
| Finished | Jun 23 08:02:56 PM PDT 24 |
| Peak memory | 608324 kb |
| Host | smart-cb8bb4cf-8bc4-44f2-a478-39c20fe73014 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=aon_timer_sleep_wdog_sleep_pause_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=497561646 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_aon_timer_sleep_wdog_sleep_pause.497561646 |
| Directory | /workspace/1.chip_sw_aon_timer_sleep_wdog_sleep_pause/latest |
| Test location | /workspace/coverage/default/1.chip_sw_aon_timer_smoketest.2404405088 |
| Short name | T1267 |
| Test name | |
| Test status | |
| Simulation time | 3236650280 ps |
| CPU time | 280.8 seconds |
| Started | Jun 23 08:04:46 PM PDT 24 |
| Finished | Jun 23 08:09:27 PM PDT 24 |
| Peak memory | 607340 kb |
| Host | smart-a11265e8-1a7f-4f6d-b4c4-9688426f5cad |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=aon_timer_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2404405088 -assert nopostproc +UVM_TESTNAM E=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 1.chip_sw_aon_timer_smoketest.2404405088 |
| Directory | /workspace/1.chip_sw_aon_timer_smoketest/latest |
| Test location | /workspace/coverage/default/1.chip_sw_aon_timer_wdog_bite_reset.286464974 |
| Short name | T365 |
| Test name | |
| Test status | |
| Simulation time | 7791563930 ps |
| CPU time | 759.39 seconds |
| Started | Jun 23 07:56:34 PM PDT 24 |
| Finished | Jun 23 08:09:14 PM PDT 24 |
| Peak memory | 608444 kb |
| Host | smart-a417eafd-6bb5-419b-83eb-927b07cc40e3 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=aon_timer_wdog_bite_reset_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 286464974 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_aon_timer_wdog_bite_reset.286464974 |
| Directory | /workspace/1.chip_sw_aon_timer_wdog_bite_reset/latest |
| Test location | /workspace/coverage/default/1.chip_sw_aon_timer_wdog_lc_escalate.4033584230 |
| Short name | T88 |
| Test name | |
| Test status | |
| Simulation time | 5699430572 ps |
| CPU time | 679.27 seconds |
| Started | Jun 23 07:58:02 PM PDT 24 |
| Finished | Jun 23 08:09:21 PM PDT 24 |
| Peak memory | 608488 kb |
| Host | smart-9a35bebe-e7b1-406c-879a-bd2518d9406f |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=aon_timer_wdog_lc_escalate_test:1:new_rules,test_rom:0 +cdc_ instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed =4033584230 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_aon_timer_wdog_lc_escalate.4033584230 |
| Directory | /workspace/1.chip_sw_aon_timer_wdog_lc_escalate/latest |
| Test location | /workspace/coverage/default/1.chip_sw_ast_clk_outputs.2544621468 |
| Short name | T278 |
| Test name | |
| Test status | |
| Simulation time | 7234423378 ps |
| CPU time | 1005.27 seconds |
| Started | Jun 23 08:03:08 PM PDT 24 |
| Finished | Jun 23 08:19:54 PM PDT 24 |
| Peak memory | 613880 kb |
| Host | smart-4658e307-0854-4ecf-bf80-ed993a1fa137 |
| User | root |
| Command | /workspace/default/simv +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=ast_clk_outs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled= 1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2544621468 -assert nopo stproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_ast_clk_outputs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co verage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_ast_clk_outputs.2544621468 |
| Directory | /workspace/1.chip_sw_ast_clk_outputs/latest |
| Test location | /workspace/coverage/default/1.chip_sw_ast_clk_rst_inputs.1850274688 |
| Short name | T135 |
| Test name | |
| Test status | |
| Simulation time | 16925351388 ps |
| CPU time | 2049.66 seconds |
| Started | Jun 23 08:03:37 PM PDT 24 |
| Finished | Jun 23 08:37:47 PM PDT 24 |
| Peak memory | 608788 kb |
| Host | smart-4c4465af-f2ad-47f9-aff6-f9007c4bc28a |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=200_000_000 +sw_build_device=sim_dv +sw_images=ast_clk_rst_inputs:1:new_rules,test_rom:0 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1850274688 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_ast_clk_rst_inputs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_ast_clk_rst_inputs.1850274688 |
| Directory | /workspace/1.chip_sw_ast_clk_rst_inputs/latest |
| Test location | /workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_lc.1030269431 |
| Short name | T1026 |
| Test name | |
| Test status | |
| Simulation time | 5294637790 ps |
| CPU time | 540.54 seconds |
| Started | Jun 23 08:02:01 PM PDT 24 |
| Finished | Jun 23 08:11:02 PM PDT 24 |
| Peak memory | 618744 kb |
| Host | smart-9916219f-ec0b-4271-832e-859200303be8 |
| User | root |
| Command | /workspace/default/simv +chip_clock_source=ChipClockSourceExternal48Mhz +sw_build_device=sim_dv +sw_images=clkmgr_external_clk_src_for_lc_test:1:new_r ules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim .tcl +ntb_random_seed=1030269431 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_transition_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_clkmgr_external_clk_src_for_lc.1030269431 |
| Directory | /workspace/1.chip_sw_clkmgr_external_clk_src_for_lc/latest |
| Test location | /workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_fast_dev.3895410047 |
| Short name | T119 |
| Test name | |
| Test status | |
| Simulation time | 4797452546 ps |
| CPU time | 828.18 seconds |
| Started | Jun 23 08:03:11 PM PDT 24 |
| Finished | Jun 23 08:16:59 PM PDT 24 |
| Peak memory | 611524 kb |
| Host | smart-3cbdddc6-ddf1-4fb8-8061-a8117dce54aa |
| User | root |
| Command | /workspace/default/simv +chip_clock_source=ChipClockSourceExternal96Mhz +calibrate_usb_clk=1 +src_dec_state=DecLcStDev +sw_build_device=sim_dv +sw_ima ges=clkmgr_external_clk_src_for_sw_fast_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3895410047 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ =chip_sw_lc_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_c lkmgr_external_clk_src_for_sw_fast_dev.3895410047 |
| Directory | /workspace/1.chip_sw_clkmgr_external_clk_src_for_sw_fast_dev/latest |
| Test location | /workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_fast_rma.2775963545 |
| Short name | T928 |
| Test name | |
| Test status | |
| Simulation time | 4565544528 ps |
| CPU time | 697.54 seconds |
| Started | Jun 23 08:02:19 PM PDT 24 |
| Finished | Jun 23 08:13:57 PM PDT 24 |
| Peak memory | 611400 kb |
| Host | smart-a5c99d91-e224-455d-bbde-fbba471efc39 |
| User | root |
| Command | /workspace/default/simv +chip_clock_source=ChipClockSourceExternal96Mhz +calibrate_usb_clk=1 +src_dec_state=DecLcStRma +sw_build_device=sim_dv +sw_ima ges=clkmgr_external_clk_src_for_sw_fast_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2775963545 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ =chip_sw_lc_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_c lkmgr_external_clk_src_for_sw_fast_rma.2775963545 |
| Directory | /workspace/1.chip_sw_clkmgr_external_clk_src_for_sw_fast_rma/latest |
| Test location | /workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0.1379523889 |
| Short name | T994 |
| Test name | |
| Test status | |
| Simulation time | 4188551264 ps |
| CPU time | 645.59 seconds |
| Started | Jun 23 08:01:42 PM PDT 24 |
| Finished | Jun 23 08:12:29 PM PDT 24 |
| Peak memory | 611560 kb |
| Host | smart-90988cc2-8d0a-47bd-8841-e9641a0fe658 |
| User | root |
| Command | /workspace/default/simv +chip_clock_source=ChipClockSourceExternal96Mhz +calibrate_usb_clk=1 +src_dec_state=DecLcStTestUnlocked0 +sw_build_device=sim_ dv +sw_images=clkmgr_external_clk_src_for_sw_fast_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1379523889 -assert nopostproc +UVM_TESTNAME=chip_base_test +UV M_TEST_SEQ=chip_sw_lc_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1 .chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0.1379523889 |
| Directory | /workspace/1.chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0/latest |
| Test location | /workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_slow_dev.770904407 |
| Short name | T375 |
| Test name | |
| Test status | |
| Simulation time | 4752481096 ps |
| CPU time | 800.11 seconds |
| Started | Jun 23 08:01:48 PM PDT 24 |
| Finished | Jun 23 08:15:08 PM PDT 24 |
| Peak memory | 611524 kb |
| Host | smart-456aec80-b696-45b4-b08d-f1961ef83a1a |
| User | root |
| Command | /workspace/default/simv +chip_clock_source=ChipClockSourceExternal48Mhz +calibrate_usb_clk=1 +src_dec_state=DecLcStDev +sw_build_device=sim_dv +sw_ima ges=clkmgr_external_clk_src_for_sw_slow_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=770904407 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ= chip_sw_lc_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_cl kmgr_external_clk_src_for_sw_slow_dev.770904407 |
| Directory | /workspace/1.chip_sw_clkmgr_external_clk_src_for_sw_slow_dev/latest |
| Test location | /workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_slow_rma.2689234310 |
| Short name | T1006 |
| Test name | |
| Test status | |
| Simulation time | 4294957364 ps |
| CPU time | 636.3 seconds |
| Started | Jun 23 08:02:27 PM PDT 24 |
| Finished | Jun 23 08:13:03 PM PDT 24 |
| Peak memory | 610584 kb |
| Host | smart-811f4763-666d-4b73-8169-12e976597560 |
| User | root |
| Command | /workspace/default/simv +chip_clock_source=ChipClockSourceExternal48Mhz +calibrate_usb_clk=1 +src_dec_state=DecLcStRma +sw_build_device=sim_dv +sw_ima ges=clkmgr_external_clk_src_for_sw_slow_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2689234310 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ =chip_sw_lc_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_c lkmgr_external_clk_src_for_sw_slow_rma.2689234310 |
| Directory | /workspace/1.chip_sw_clkmgr_external_clk_src_for_sw_slow_rma/latest |
| Test location | /workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0.2939287343 |
| Short name | T1120 |
| Test name | |
| Test status | |
| Simulation time | 5423784586 ps |
| CPU time | 681.14 seconds |
| Started | Jun 23 08:01:53 PM PDT 24 |
| Finished | Jun 23 08:13:15 PM PDT 24 |
| Peak memory | 610288 kb |
| Host | smart-e0f2f4cd-9c10-45ec-8b71-974e43f633a7 |
| User | root |
| Command | /workspace/default/simv +chip_clock_source=ChipClockSourceExternal48Mhz +calibrate_usb_clk=1 +src_dec_state=DecLcStTestUnlocked0 +sw_build_device=sim_ dv +sw_images=clkmgr_external_clk_src_for_sw_slow_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2939287343 -assert nopostproc +UVM_TESTNAME=chip_base_test +UV M_TEST_SEQ=chip_sw_lc_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1 .chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0.2939287343 |
| Directory | /workspace/1.chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0/latest |
| Test location | /workspace/coverage/default/1.chip_sw_clkmgr_jitter.1066713962 |
| Short name | T1303 |
| Test name | |
| Test status | |
| Simulation time | 2983722307 ps |
| CPU time | 274.66 seconds |
| Started | Jun 23 08:02:45 PM PDT 24 |
| Finished | Jun 23 08:07:20 PM PDT 24 |
| Peak memory | 606876 kb |
| Host | smart-22fdb845-b22d-44d7-ac5c-ae9445680cbd |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_jitter_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1066713962 -assert nopostproc +UVM_TESTNAME =chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 1.chip_sw_clkmgr_jitter.1066713962 |
| Directory | /workspace/1.chip_sw_clkmgr_jitter/latest |
| Test location | /workspace/coverage/default/1.chip_sw_clkmgr_jitter_frequency.321522239 |
| Short name | T1121 |
| Test name | |
| Test status | |
| Simulation time | 3557225564 ps |
| CPU time | 418.76 seconds |
| Started | Jun 23 08:03:41 PM PDT 24 |
| Finished | Jun 23 08:10:40 PM PDT 24 |
| Peak memory | 606940 kb |
| Host | smart-b75b2619-f8e5-4ab0-a514-b0dc82a8498b |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_jitter_frequency_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=321522239 -assert nopostproc +UVM _TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm _log /dev/null -cm_name 1.chip_sw_clkmgr_jitter_frequency.321522239 |
| Directory | /workspace/1.chip_sw_clkmgr_jitter_frequency/latest |
| Test location | /workspace/coverage/default/1.chip_sw_clkmgr_jitter_reduced_freq.1881399541 |
| Short name | T1127 |
| Test name | |
| Test status | |
| Simulation time | 2550297876 ps |
| CPU time | 260.74 seconds |
| Started | Jun 23 08:04:33 PM PDT 24 |
| Finished | Jun 23 08:08:55 PM PDT 24 |
| Peak memory | 607568 kb |
| Host | smart-2c507a03-c535-415d-bdeb-13542896b3ef |
| User | root |
| Command | /workspace/default/simv +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=clkmgr_jitter_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1881399541 -assert nop ostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def ault.vdb -cm_log /dev/null -cm_name 1.chip_sw_clkmgr_jitter_reduced_freq.1881399541 |
| Directory | /workspace/1.chip_sw_clkmgr_jitter_reduced_freq/latest |
| Test location | /workspace/coverage/default/1.chip_sw_clkmgr_off_aes_trans.1516147291 |
| Short name | T933 |
| Test name | |
| Test status | |
| Simulation time | 5269020488 ps |
| CPU time | 552.64 seconds |
| Started | Jun 23 08:01:27 PM PDT 24 |
| Finished | Jun 23 08:10:41 PM PDT 24 |
| Peak memory | 607196 kb |
| Host | smart-a5c33827-f968-43e2-9115-fd141f318e18 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_off_aes_trans_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1516147291 -assert nopostproc +UVM_T ESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l og /dev/null -cm_name 1.chip_sw_clkmgr_off_aes_trans.1516147291 |
| Directory | /workspace/1.chip_sw_clkmgr_off_aes_trans/latest |
| Test location | /workspace/coverage/default/1.chip_sw_clkmgr_off_hmac_trans.1560974890 |
| Short name | T1222 |
| Test name | |
| Test status | |
| Simulation time | 4997334500 ps |
| CPU time | 413.79 seconds |
| Started | Jun 23 08:03:11 PM PDT 24 |
| Finished | Jun 23 08:10:05 PM PDT 24 |
| Peak memory | 608176 kb |
| Host | smart-eefc8297-5aac-47e8-abd1-e1dad9276428 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_off_hmac_trans_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1560974890 -assert nopostproc +UVM_ TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_ log /dev/null -cm_name 1.chip_sw_clkmgr_off_hmac_trans.1560974890 |
| Directory | /workspace/1.chip_sw_clkmgr_off_hmac_trans/latest |
| Test location | /workspace/coverage/default/1.chip_sw_clkmgr_off_kmac_trans.1705119152 |
| Short name | T1162 |
| Test name | |
| Test status | |
| Simulation time | 3841102284 ps |
| CPU time | 701.03 seconds |
| Started | Jun 23 08:02:17 PM PDT 24 |
| Finished | Jun 23 08:13:59 PM PDT 24 |
| Peak memory | 606876 kb |
| Host | smart-9ff94b04-5861-4de3-a9cb-35eec5423651 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_off_kmac_trans_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1705119152 -assert nopostproc +UVM_ TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_ log /dev/null -cm_name 1.chip_sw_clkmgr_off_kmac_trans.1705119152 |
| Directory | /workspace/1.chip_sw_clkmgr_off_kmac_trans/latest |
| Test location | /workspace/coverage/default/1.chip_sw_clkmgr_off_otbn_trans.3701040479 |
| Short name | T1254 |
| Test name | |
| Test status | |
| Simulation time | 5858087382 ps |
| CPU time | 521.23 seconds |
| Started | Jun 23 08:04:07 PM PDT 24 |
| Finished | Jun 23 08:12:49 PM PDT 24 |
| Peak memory | 607196 kb |
| Host | smart-9266da7e-73be-4464-bdc6-297ed556673c |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_off_otbn_trans_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3701040479 -assert nopostproc +UVM_ TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_ log /dev/null -cm_name 1.chip_sw_clkmgr_off_otbn_trans.3701040479 |
| Directory | /workspace/1.chip_sw_clkmgr_off_otbn_trans/latest |
| Test location | /workspace/coverage/default/1.chip_sw_clkmgr_off_peri.2333507187 |
| Short name | T1337 |
| Test name | |
| Test status | |
| Simulation time | 9446432760 ps |
| CPU time | 1134.7 seconds |
| Started | Jun 23 08:01:24 PM PDT 24 |
| Finished | Jun 23 08:20:19 PM PDT 24 |
| Peak memory | 608444 kb |
| Host | smart-0d740d35-517b-46f4-9151-07e691511551 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=30_000_000 +sw_build_device=sim_dv +sw_images=clkmgr_off_peri_test:1:new_rules,test_rom:0 +cdc_instrumenta tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2333507187 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/ coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_clkmgr_off_peri.2333507187 |
| Directory | /workspace/1.chip_sw_clkmgr_off_peri/latest |
| Test location | /workspace/coverage/default/1.chip_sw_clkmgr_reset_frequency.3413186443 |
| Short name | T1081 |
| Test name | |
| Test status | |
| Simulation time | 3341619920 ps |
| CPU time | 489.06 seconds |
| Started | Jun 23 08:01:52 PM PDT 24 |
| Finished | Jun 23 08:10:02 PM PDT 24 |
| Peak memory | 607612 kb |
| Host | smart-ca93dacd-a955-45b5-8926-0eff21a9e8f9 |
| User | root |
| Command | /workspace/default/simv +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=clkmgr_reset_frequency_test:1:new_rules,test_rom:0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3413186443 -a ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov erage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_clkmgr_reset_frequency.3413186443 |
| Directory | /workspace/1.chip_sw_clkmgr_reset_frequency/latest |
| Test location | /workspace/coverage/default/1.chip_sw_clkmgr_sleep_frequency.3732277910 |
| Short name | T1286 |
| Test name | |
| Test status | |
| Simulation time | 4348501272 ps |
| CPU time | 623.83 seconds |
| Started | Jun 23 08:03:02 PM PDT 24 |
| Finished | Jun 23 08:13:27 PM PDT 24 |
| Peak memory | 607976 kb |
| Host | smart-0d6bdbea-85b0-4278-a5de-20717bbc6683 |
| User | root |
| Command | /workspace/default/simv +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=clkmgr_sleep_frequency_test:1:new_rules,test_rom:0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3732277910 -a ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov erage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_clkmgr_sleep_frequency.3732277910 |
| Directory | /workspace/1.chip_sw_clkmgr_sleep_frequency/latest |
| Test location | /workspace/coverage/default/1.chip_sw_clkmgr_smoketest.1228536088 |
| Short name | T946 |
| Test name | |
| Test status | |
| Simulation time | 3088197680 ps |
| CPU time | 340.53 seconds |
| Started | Jun 23 08:04:44 PM PDT 24 |
| Finished | Jun 23 08:10:25 PM PDT 24 |
| Peak memory | 607572 kb |
| Host | smart-9464fa31-bbdb-45c1-b170-231f3112c9aa |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1228536088 -assert nopostproc +UVM_TESTNAME=c hip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n ull -cm_name 1.chip_sw_clkmgr_smoketest.1228536088 |
| Directory | /workspace/1.chip_sw_clkmgr_smoketest/latest |
| Test location | /workspace/coverage/default/1.chip_sw_csrng_edn_concurrency.2167074740 |
| Short name | T1218 |
| Test name | |
| Test status | |
| Simulation time | 8662101350 ps |
| CPU time | 1834.64 seconds |
| Started | Jun 23 07:59:39 PM PDT 24 |
| Finished | Jun 23 08:30:15 PM PDT 24 |
| Peak memory | 607944 kb |
| Host | smart-9ebb3b36-3c00-4cfd-b9f9-378a9e2ab44d |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=140_000_000 +rng_srate_value_min=15 +rng_srate_value_max=20 +accelerate_cold_power_up_time=3 +accelerate_r egulators_power_up_time=2 +sw_build_device=sim_dv +sw_images=csrng_edn_concurrency_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2167074740 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd b -cm_log /dev/null -cm_name 1.chip_sw_csrng_edn_concurrency.2167074740 |
| Directory | /workspace/1.chip_sw_csrng_edn_concurrency/latest |
| Test location | /workspace/coverage/default/1.chip_sw_csrng_edn_concurrency_reduced_freq.759578929 |
| Short name | T105 |
| Test name | |
| Test status | |
| Simulation time | 27551139765 ps |
| CPU time | 4740.43 seconds |
| Started | Jun 23 08:04:41 PM PDT 24 |
| Finished | Jun 23 09:23:43 PM PDT 24 |
| Peak memory | 607312 kb |
| Host | smart-c338dbac-fca9-4a4e-94d7-93fc9cf535ea |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=360_000_000 +rng_srate_value_min=15 +rng_srate_value_max=20 +cal_sys_clk_70mhz=1 +en_jitter=1 +accelerate_ cold_power_up_time=3 +accelerate_regulators_power_up_time=2 +sw_build_device=sim_dv +sw_images=csrng_edn_concurrency_test:1:new_rules,test_rom:0 + cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_ seed=759578929 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_csrng_edn_concurrency_reduced_freq.759578929 |
| Directory | /workspace/1.chip_sw_csrng_edn_concurrency_reduced_freq/latest |
| Test location | /workspace/coverage/default/1.chip_sw_csrng_fuse_en_sw_app_read_test.1508012402 |
| Short name | T177 |
| Test name | |
| Test status | |
| Simulation time | 3718816572 ps |
| CPU time | 507.58 seconds |
| Started | Jun 23 08:00:32 PM PDT 24 |
| Finished | Jun 23 08:09:00 PM PDT 24 |
| Peak memory | 606876 kb |
| Host | smart-aa73c1ca-ffe7-44f6-a1e2-c23543477103 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=15_000_000 +sw_build_device=sim_dv +sw_images=csrng_fuse_en_sw_app_read:1:new_rules,test_rom:0 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15080 12402 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_entropy_src_fuse_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_csrng_fuse_en_sw_app_read_test.1508012402 |
| Directory | /workspace/1.chip_sw_csrng_fuse_en_sw_app_read_test/latest |
| Test location | /workspace/coverage/default/1.chip_sw_csrng_kat_test.2948419884 |
| Short name | T691 |
| Test name | |
| Test status | |
| Simulation time | 2779057790 ps |
| CPU time | 246.33 seconds |
| Started | Jun 23 07:59:53 PM PDT 24 |
| Finished | Jun 23 08:03:59 PM PDT 24 |
| Peak memory | 606768 kb |
| Host | smart-12c9e908-e5f0-4e3a-9c2e-02eec518a739 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=csrng_kat_test:1:new_rules,test_rom:0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2948419884 -asse rt nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera ge/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_csrng_kat_test.2948419884 |
| Directory | /workspace/1.chip_sw_csrng_kat_test/latest |
| Test location | /workspace/coverage/default/1.chip_sw_csrng_lc_hw_debug_en_test.1153700142 |
| Short name | T176 |
| Test name | |
| Test status | |
| Simulation time | 6878859963 ps |
| CPU time | 608.39 seconds |
| Started | Jun 23 07:58:19 PM PDT 24 |
| Finished | Jun 23 08:08:27 PM PDT 24 |
| Peak memory | 609064 kb |
| Host | smart-a79d8353-cb72-4a3f-be5a-c9460476c6e7 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=15_000_000 +rng_srate_value_min=15 +use_otp_image=OtpTypeLcStTestUnlocked0 +sw_build_device=sim_dv +sw_ima ges=csrng_lc_hw_debug_en_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1153700142 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_csrng_ lc_hw_debug_en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_csr ng_lc_hw_debug_en_test.1153700142 |
| Directory | /workspace/1.chip_sw_csrng_lc_hw_debug_en_test/latest |
| Test location | /workspace/coverage/default/1.chip_sw_csrng_smoketest.1420750971 |
| Short name | T1342 |
| Test name | |
| Test status | |
| Simulation time | 2565869032 ps |
| CPU time | 274.51 seconds |
| Started | Jun 23 08:10:17 PM PDT 24 |
| Finished | Jun 23 08:14:53 PM PDT 24 |
| Peak memory | 607836 kb |
| Host | smart-e787f7a1-fb26-499c-a83b-44c5508438d2 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=csrng_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1420750971 -assert nopostproc +UVM_TESTNAME=ch ip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu ll -cm_name 1.chip_sw_csrng_smoketest.1420750971 |
| Directory | /workspace/1.chip_sw_csrng_smoketest/latest |
| Test location | /workspace/coverage/default/1.chip_sw_data_integrity_escalation.3746265323 |
| Short name | T269 |
| Test name | |
| Test status | |
| Simulation time | 5854065840 ps |
| CPU time | 871.61 seconds |
| Started | Jun 23 07:55:33 PM PDT 24 |
| Finished | Jun 23 08:10:06 PM PDT 24 |
| Peak memory | 608716 kb |
| Host | smart-d9e19ab3-169f-4faa-a450-32bc1bd7b9d1 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=data_integrity_escalation_reset_test:1:new_rules,test_ro m:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=3746265323 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_data_integrity_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_data_integrity_escalation.3746265323 |
| Directory | /workspace/1.chip_sw_data_integrity_escalation/latest |
| Test location | /workspace/coverage/default/1.chip_sw_edn_auto_mode.2055862398 |
| Short name | T1045 |
| Test name | |
| Test status | |
| Simulation time | 6157405024 ps |
| CPU time | 1778.79 seconds |
| Started | Jun 23 08:01:57 PM PDT 24 |
| Finished | Jun 23 08:31:36 PM PDT 24 |
| Peak memory | 607216 kb |
| Host | smart-125c451b-a15b-4504-80cc-ad700dd31c3a |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +rng_srate_value=5 +accelerate_cold_power_up_time=3 +accelerate_regulators_power_up_time=2 +sw_ build_device=sim_dv +sw_images=edn_auto_mode:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2055862398 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ =chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_edn_ auto_mode.2055862398 |
| Directory | /workspace/1.chip_sw_edn_auto_mode/latest |
| Test location | /workspace/coverage/default/1.chip_sw_edn_boot_mode.745374970 |
| Short name | T689 |
| Test name | |
| Test status | |
| Simulation time | 3270529456 ps |
| CPU time | 713.21 seconds |
| Started | Jun 23 07:58:14 PM PDT 24 |
| Finished | Jun 23 08:10:08 PM PDT 24 |
| Peak memory | 607144 kb |
| Host | smart-87983ccc-d8d7-498c-89fe-33bfd0001e86 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +rng_srate_value=5 +accelerate_cold_power_up_time=3 +accelerate_regulators_power_up_time=2 +sw_ build_device=sim_dv +sw_images=edn_boot_mode:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=745374970 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ= chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_edn_b oot_mode.745374970 |
| Directory | /workspace/1.chip_sw_edn_boot_mode/latest |
| Test location | /workspace/coverage/default/1.chip_sw_edn_entropy_reqs_jitter.3649245229 |
| Short name | T1113 |
| Test name | |
| Test status | |
| Simulation time | 6251411283 ps |
| CPU time | 991.59 seconds |
| Started | Jun 23 07:58:34 PM PDT 24 |
| Finished | Jun 23 08:15:06 PM PDT 24 |
| Peak memory | 608836 kb |
| Host | smart-34aab8b1-9518-4e72-a43f-0b1434443ede |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=15000000 +rng_srate_value_min=15 +rng_srate_value_max=30 +en_jitter=1 +sw_build_device=sim_dv +sw_images=e ntropy_src_edn_reqs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3649245229 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_edn_entropy_reqs_jitter.3649245229 |
| Directory | /workspace/1.chip_sw_edn_entropy_reqs_jitter/latest |
| Test location | /workspace/coverage/default/1.chip_sw_edn_kat.2726092639 |
| Short name | T1195 |
| Test name | |
| Test status | |
| Simulation time | 3670477368 ps |
| CPU time | 693.56 seconds |
| Started | Jun 23 07:58:59 PM PDT 24 |
| Finished | Jun 23 08:10:33 PM PDT 24 |
| Peak memory | 613336 kb |
| Host | smart-896f7931-f871-4477-bc0b-8b94c97655cd |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +rng_srate_value=5 +disable_assert_edn_output_diff_from_prev=1 +accelerate_cold_power_up_time=3 +accelerate_regulators_power_up_time=2 +sw_build_device=sim_dv +sw_images=edn_kat:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2726092639 -assert nopostproc +UVM _TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm _log /dev/null -cm_name 1.chip_sw_edn_kat.2726092639 |
| Directory | /workspace/1.chip_sw_edn_kat/latest |
| Test location | /workspace/coverage/default/1.chip_sw_edn_sw_mode.3664809703 |
| Short name | T960 |
| Test name | |
| Test status | |
| Simulation time | 8538453040 ps |
| CPU time | 1949.15 seconds |
| Started | Jun 23 07:58:36 PM PDT 24 |
| Finished | Jun 23 08:31:07 PM PDT 24 |
| Peak memory | 608068 kb |
| Host | smart-d59551e2-c784-438b-8970-3210d719e846 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=edn_sw_mode:1:new_rules,test_rom:0 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3664809703 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/ default.vdb -cm_log /dev/null -cm_name 1.chip_sw_edn_sw_mode.3664809703 |
| Directory | /workspace/1.chip_sw_edn_sw_mode/latest |
| Test location | /workspace/coverage/default/1.chip_sw_entropy_src_ast_rng_req.3459502726 |
| Short name | T1357 |
| Test name | |
| Test status | |
| Simulation time | 2951693410 ps |
| CPU time | 306.92 seconds |
| Started | Jun 23 07:58:11 PM PDT 24 |
| Finished | Jun 23 08:03:18 PM PDT 24 |
| Peak memory | 607468 kb |
| Host | smart-09541ad1-bb60-4ce5-800e-5cc80c24de60 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=15_000_000 +sw_build_device=sim_dv +sw_images=entropy_src_ast_rng_req_test:1:new_rules,test_rom:0 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34 59502726 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_entropy_src_ast_rng_req.3459502726 |
| Directory | /workspace/1.chip_sw_entropy_src_ast_rng_req/latest |
| Test location | /workspace/coverage/default/1.chip_sw_entropy_src_csrng.3795282720 |
| Short name | T122 |
| Test name | |
| Test status | |
| Simulation time | 6186450386 ps |
| CPU time | 1505.85 seconds |
| Started | Jun 23 08:00:42 PM PDT 24 |
| Finished | Jun 23 08:25:49 PM PDT 24 |
| Peak memory | 607892 kb |
| Host | smart-6a56f4c2-508f-4b60-b52e-c1464ccdbba4 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=50_000_000 +rng_srate_value_min=15 +rng_srate_value_max=30 +sw_build_device=sim_dv +sw_images=entropy_src_ csrng_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3795282720 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_entropy_src_csrng.3795282720 |
| Directory | /workspace/1.chip_sw_entropy_src_csrng/latest |
| Test location | /workspace/coverage/default/1.chip_sw_entropy_src_kat_test.772498358 |
| Short name | T1264 |
| Test name | |
| Test status | |
| Simulation time | 2366562144 ps |
| CPU time | 234.33 seconds |
| Started | Jun 23 07:59:43 PM PDT 24 |
| Finished | Jun 23 08:03:38 PM PDT 24 |
| Peak memory | 607868 kb |
| Host | smart-533e17d3-d9d8-4a76-b205-8cd96481dd33 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=entropy_src_kat_test:1:new_rules,test_rom:0 +cdc_instrumenta tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=772498358 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/c overage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_entropy_src_kat_test.772498358 |
| Directory | /workspace/1.chip_sw_entropy_src_kat_test/latest |
| Test location | /workspace/coverage/default/1.chip_sw_entropy_src_smoketest.2834352882 |
| Short name | T1002 |
| Test name | |
| Test status | |
| Simulation time | 3681105640 ps |
| CPU time | 555.69 seconds |
| Started | Jun 23 08:06:12 PM PDT 24 |
| Finished | Jun 23 08:15:28 PM PDT 24 |
| Peak memory | 607816 kb |
| Host | smart-2fbedd81-7fdf-428e-bb0b-12aa0d12cf99 |
| User | root |
| Command | /workspace/default/simv +rng_srate_value_min=15 +rng_srate_value_max=30 +sw_build_device=sim_dv +sw_images=entropy_src_smoketest:1:new_rules,test_rom: 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand om_seed=2834352882 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_entropy_src_smoketest.2834352882 |
| Directory | /workspace/1.chip_sw_entropy_src_smoketest/latest |
| Test location | /workspace/coverage/default/1.chip_sw_example_concurrency.2263230679 |
| Short name | T87 |
| Test name | |
| Test status | |
| Simulation time | 2398084272 ps |
| CPU time | 302.29 seconds |
| Started | Jun 23 07:58:01 PM PDT 24 |
| Finished | Jun 23 08:03:04 PM PDT 24 |
| Peak memory | 606880 kb |
| Host | smart-62e04670-2c3e-41ba-a5c2-5633d887c776 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=example_concurrency_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2263230679 -assert nopostproc +UVM_TE STNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo g /dev/null -cm_name 1.chip_sw_example_concurrency.2263230679 |
| Directory | /workspace/1.chip_sw_example_concurrency/latest |
| Test location | /workspace/coverage/default/1.chip_sw_example_flash.3319224325 |
| Short name | T1170 |
| Test name | |
| Test status | |
| Simulation time | 2535369368 ps |
| CPU time | 194.54 seconds |
| Started | Jun 23 07:54:23 PM PDT 24 |
| Finished | Jun 23 07:57:38 PM PDT 24 |
| Peak memory | 607324 kb |
| Host | smart-7cb5cc6c-4080-4013-95d0-d35cb60ec75e |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=example_test_from_flash:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3319224325 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_example_flash.3319224325 |
| Directory | /workspace/1.chip_sw_example_flash/latest |
| Test location | /workspace/coverage/default/1.chip_sw_example_manufacturer.1128903285 |
| Short name | T1132 |
| Test name | |
| Test status | |
| Simulation time | 2541731672 ps |
| CPU time | 213.49 seconds |
| Started | Jun 23 07:55:57 PM PDT 24 |
| Finished | Jun 23 07:59:31 PM PDT 24 |
| Peak memory | 606952 kb |
| Host | smart-920ecc72-a80b-4310-9e51-51d46413b95e |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=example_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1128903285 -assert nopostproc +UVM_TESTNAME=chip_ base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_example_manufacturer.1128903285 |
| Directory | /workspace/1.chip_sw_example_manufacturer/latest |
| Test location | /workspace/coverage/default/1.chip_sw_example_rom.363003678 |
| Short name | T1244 |
| Test name | |
| Test status | |
| Simulation time | 1932464040 ps |
| CPU time | 133.4 seconds |
| Started | Jun 23 07:57:08 PM PDT 24 |
| Finished | Jun 23 07:59:23 PM PDT 24 |
| Peak memory | 607672 kb |
| Host | smart-34c8b273-8c21-4a63-9af0-eb9f9d55d53e |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:test_in_rom:new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=363003678 -assert nopostproc +UVM_TESTN AME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log / dev/null -cm_name 1.chip_sw_example_rom.363003678 |
| Directory | /workspace/1.chip_sw_example_rom/latest |
| Test location | /workspace/coverage/default/1.chip_sw_flash_crash_alert.1376215943 |
| Short name | T1307 |
| Test name | |
| Test status | |
| Simulation time | 4995841208 ps |
| CPU time | 769.01 seconds |
| Started | Jun 23 08:03:45 PM PDT 24 |
| Finished | Jun 23 08:16:34 PM PDT 24 |
| Peak memory | 608812 kb |
| Host | smart-ba589823-94c6-41a4-9b01-6e37a3154549 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=8_000_000 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1: new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tool s/sim.tcl +ntb_random_seed=1376215943 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_flash_host_gnt_err_inj_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_flash_crash_alert.1376215943 |
| Directory | /workspace/1.chip_sw_flash_crash_alert/latest |
| Test location | /workspace/coverage/default/1.chip_sw_flash_ctrl_access.2654657525 |
| Short name | T285 |
| Test name | |
| Test status | |
| Simulation time | 6037120852 ps |
| CPU time | 1202.31 seconds |
| Started | Jun 23 07:54:06 PM PDT 24 |
| Finished | Jun 23 08:14:09 PM PDT 24 |
| Peak memory | 607872 kb |
| Host | smart-ca9b59c8-7a45-4b3d-8249-e05ef3cd4257 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=flash_ctrl_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2654657525 -assert nopostproc +UVM_TESTNAME=ch ip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu ll -cm_name 1.chip_sw_flash_ctrl_access.2654657525 |
| Directory | /workspace/1.chip_sw_flash_ctrl_access/latest |
| Test location | /workspace/coverage/default/1.chip_sw_flash_ctrl_access_jitter_en.2040478884 |
| Short name | T1086 |
| Test name | |
| Test status | |
| Simulation time | 5635294050 ps |
| CPU time | 1066.19 seconds |
| Started | Jun 23 07:53:46 PM PDT 24 |
| Finished | Jun 23 08:11:32 PM PDT 24 |
| Peak memory | 607456 kb |
| Host | smart-15ddd9dd-5679-4bed-a2fe-3b5b58e8068c |
| User | root |
| Command | /workspace/default/simv +en_jitter=1 +sw_build_device=sim_dv +sw_images=flash_ctrl_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2040478884 -assert nopostproc +UV M_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -c m_log /dev/null -cm_name 1.chip_sw_flash_ctrl_access_jitter_en.2040478884 |
| Directory | /workspace/1.chip_sw_flash_ctrl_access_jitter_en/latest |
| Test location | /workspace/coverage/default/1.chip_sw_flash_ctrl_access_jitter_en_reduced_freq.3393268508 |
| Short name | T1110 |
| Test name | |
| Test status | |
| Simulation time | 8177185876 ps |
| CPU time | 1090.29 seconds |
| Started | Jun 23 08:05:44 PM PDT 24 |
| Finished | Jun 23 08:23:55 PM PDT 24 |
| Peak memory | 607568 kb |
| Host | smart-d8bfdadf-481b-4a4f-9bf3-93ea59bace93 |
| User | root |
| Command | /workspace/default/simv +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=flash_ctrl_test:1:new_rules,test_rom:0 +cdc_instrumentati on_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3393268508 - assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co verage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_flash_ctrl_access_jitter_en_reduced_freq.3393268508 |
| Directory | /workspace/1.chip_sw_flash_ctrl_access_jitter_en_reduced_freq/latest |
| Test location | /workspace/coverage/default/1.chip_sw_flash_ctrl_clock_freqs.137913130 |
| Short name | T110 |
| Test name | |
| Test status | |
| Simulation time | 5527545906 ps |
| CPU time | 923.51 seconds |
| Started | Jun 23 07:54:35 PM PDT 24 |
| Finished | Jun 23 08:09:59 PM PDT 24 |
| Peak memory | 607052 kb |
| Host | smart-cc44876a-22e3-4343-a581-08d3cf8abc7c |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=flash_ctrl_clock_freqs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=137913130 -assert nopostproc +UVM_ TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_ log /dev/null -cm_name 1.chip_sw_flash_ctrl_clock_freqs.137913130 |
| Directory | /workspace/1.chip_sw_flash_ctrl_clock_freqs/latest |
| Test location | /workspace/coverage/default/1.chip_sw_flash_ctrl_idle_low_power.3321630793 |
| Short name | T348 |
| Test name | |
| Test status | |
| Simulation time | 3582289984 ps |
| CPU time | 333.83 seconds |
| Started | Jun 23 07:55:58 PM PDT 24 |
| Finished | Jun 23 08:01:32 PM PDT 24 |
| Peak memory | 607812 kb |
| Host | smart-0072cf99-349d-4a9f-a280-a966e760a233 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=flash_ctrl_idle_low_power_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3321630793 -assert nopostproc + UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_flash_ctrl_idle_low_power.3321630793 |
| Directory | /workspace/1.chip_sw_flash_ctrl_idle_low_power/latest |
| Test location | /workspace/coverage/default/1.chip_sw_flash_ctrl_mem_protection.3956641280 |
| Short name | T1189 |
| Test name | |
| Test status | |
| Simulation time | 5794113240 ps |
| CPU time | 1162.93 seconds |
| Started | Jun 23 08:04:09 PM PDT 24 |
| Finished | Jun 23 08:23:32 PM PDT 24 |
| Peak memory | 607120 kb |
| Host | smart-a9a638f1-0ced-41ba-a161-483136f343d5 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=flash_ctrl_mem_protection_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3956641280 -assert nopostproc + UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_flash_ctrl_mem_protection.3956641280 |
| Directory | /workspace/1.chip_sw_flash_ctrl_mem_protection/latest |
| Test location | /workspace/coverage/default/1.chip_sw_flash_ctrl_ops_jitter_en.3925463100 |
| Short name | T331 |
| Test name | |
| Test status | |
| Simulation time | 4365587782 ps |
| CPU time | 681.61 seconds |
| Started | Jun 23 07:56:20 PM PDT 24 |
| Finished | Jun 23 08:07:42 PM PDT 24 |
| Peak memory | 606880 kb |
| Host | smart-2743376b-b0bf-44a9-98ba-1b81b7b93513 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=50_000_000 +en_jitter=1 +sw_build_device=sim_dv +sw_images=flash_ctrl_ops_test:1:new_rules,test_rom:0 +cdc _instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see d=3925463100 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_flash_ctrl_ops_jitter_en.3925463100 |
| Directory | /workspace/1.chip_sw_flash_ctrl_ops_jitter_en/latest |
| Test location | /workspace/coverage/default/1.chip_sw_flash_ctrl_write_clear.2752848812 |
| Short name | T945 |
| Test name | |
| Test status | |
| Simulation time | 2949379946 ps |
| CPU time | 349.23 seconds |
| Started | Jun 23 08:03:08 PM PDT 24 |
| Finished | Jun 23 08:08:57 PM PDT 24 |
| Peak memory | 607572 kb |
| Host | smart-95c45a3c-8527-4e10-9e89-d05ddea6a613 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=8_000_000 +sw_build_device=sim_dv +sw_images=flash_ctrl_write_clear_test:1:new_rules,test_rom:0 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2752848 812 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_flash_ctrl_write_clear.2752848812 |
| Directory | /workspace/1.chip_sw_flash_ctrl_write_clear/latest |
| Test location | /workspace/coverage/default/1.chip_sw_flash_init_reduced_freq.3743511720 |
| Short name | T233 |
| Test name | |
| Test status | |
| Simulation time | 18255924643 ps |
| CPU time | 1860.9 seconds |
| Started | Jun 23 08:02:53 PM PDT 24 |
| Finished | Jun 23 08:33:55 PM PDT 24 |
| Peak memory | 611360 kb |
| Host | smart-85935260-61a8-4b22-8ba6-272f0560f588 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=25_000_000 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=flash_init_test:0:test_in_rom:new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=3743511720 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_flash_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_flash_init_reduced_freq.3743511720 |
| Directory | /workspace/1.chip_sw_flash_init_reduced_freq/latest |
| Test location | /workspace/coverage/default/1.chip_sw_flash_scrambling_smoketest.104202484 |
| Short name | T1191 |
| Test name | |
| Test status | |
| Simulation time | 3303891464 ps |
| CPU time | 329.35 seconds |
| Started | Jun 23 08:08:23 PM PDT 24 |
| Finished | Jun 23 08:13:53 PM PDT 24 |
| Peak memory | 608032 kb |
| Host | smart-3cb11e2e-3714-4c59-9bed-5b0036bad020 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=flash_scrambling_smoketest:1:new_rules,flash_scrambling_smoket est_otp_img_rma:4,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=104202484 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_flash_scrambling_smoketest.104202484 |
| Directory | /workspace/1.chip_sw_flash_scrambling_smoketest/latest |
| Test location | /workspace/coverage/default/1.chip_sw_gpio_smoketest.291921532 |
| Short name | T81 |
| Test name | |
| Test status | |
| Simulation time | 2676265225 ps |
| CPU time | 255.49 seconds |
| Started | Jun 23 08:04:47 PM PDT 24 |
| Finished | Jun 23 08:09:03 PM PDT 24 |
| Peak memory | 607376 kb |
| Host | smart-badbadda-fa04-4336-9d8f-57d18839f8bc |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=gpio_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=291921532 -assert nopostproc +UVM_TESTNAME=chip _base_test +UVM_TEST_SEQ=chip_sw_gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 1.chip_sw_gpio_smoketest.291921532 |
| Directory | /workspace/1.chip_sw_gpio_smoketest/latest |
| Test location | /workspace/coverage/default/1.chip_sw_hmac_enc.1698215591 |
| Short name | T1147 |
| Test name | |
| Test status | |
| Simulation time | 2742828830 ps |
| CPU time | 276.19 seconds |
| Started | Jun 23 08:00:09 PM PDT 24 |
| Finished | Jun 23 08:04:46 PM PDT 24 |
| Peak memory | 607828 kb |
| Host | smart-72a1f22a-08d1-4ec8-b362-a187b2779517 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=hmac_enc_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1698215591 -assert nopostproc +UVM_TESTNAME=chip _base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_hmac_enc.1698215591 |
| Directory | /workspace/1.chip_sw_hmac_enc/latest |
| Test location | /workspace/coverage/default/1.chip_sw_hmac_enc_idle.1463747335 |
| Short name | T1155 |
| Test name | |
| Test status | |
| Simulation time | 2644933940 ps |
| CPU time | 228.93 seconds |
| Started | Jun 23 08:00:19 PM PDT 24 |
| Finished | Jun 23 08:04:08 PM PDT 24 |
| Peak memory | 606864 kb |
| Host | smart-743d89bf-b8a4-494e-b302-132b7c14dca8 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=hmac_enc_idle_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1463747335 -assert nopostproc +UVM_TESTNAME =chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 1.chip_sw_hmac_enc_idle.1463747335 |
| Directory | /workspace/1.chip_sw_hmac_enc_idle/latest |
| Test location | /workspace/coverage/default/1.chip_sw_hmac_enc_jitter_en.2187429610 |
| Short name | T1285 |
| Test name | |
| Test status | |
| Simulation time | 2898389706 ps |
| CPU time | 246.42 seconds |
| Started | Jun 23 07:58:54 PM PDT 24 |
| Finished | Jun 23 08:03:02 PM PDT 24 |
| Peak memory | 606860 kb |
| Host | smart-47e8a88d-a8d8-43e7-8df1-9d590fe1872d |
| User | root |
| Command | /workspace/default/simv +en_jitter=1 +sw_build_device=sim_dv +sw_images=hmac_enc_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2187429610 -assert nopostproc +UVM_ TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_ log /dev/null -cm_name 1.chip_sw_hmac_enc_jitter_en.2187429610 |
| Directory | /workspace/1.chip_sw_hmac_enc_jitter_en/latest |
| Test location | /workspace/coverage/default/1.chip_sw_hmac_enc_jitter_en_reduced_freq.125162312 |
| Short name | T929 |
| Test name | |
| Test status | |
| Simulation time | 2803155161 ps |
| CPU time | 221.31 seconds |
| Started | Jun 23 08:04:00 PM PDT 24 |
| Finished | Jun 23 08:07:42 PM PDT 24 |
| Peak memory | 607232 kb |
| Host | smart-e9d47263-1ed6-466c-9a15-a5cd46673889 |
| User | root |
| Command | /workspace/default/simv +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=hmac_enc_test:1:new_rules,test_rom:0 +cdc_instrumentation _enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=125162312 -ass ert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_hmac_enc_jitter_en_reduced_freq.125162312 |
| Directory | /workspace/1.chip_sw_hmac_enc_jitter_en_reduced_freq/latest |
| Test location | /workspace/coverage/default/1.chip_sw_hmac_multistream.3885661963 |
| Short name | T1220 |
| Test name | |
| Test status | |
| Simulation time | 6862470500 ps |
| CPU time | 1579.25 seconds |
| Started | Jun 23 08:01:20 PM PDT 24 |
| Finished | Jun 23 08:27:40 PM PDT 24 |
| Peak memory | 606936 kb |
| Host | smart-3ad65544-20bf-4756-b91e-a9c272fb7738 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=hmac_multistream_functest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3885661963 -assert nopostproc +UVM_T ESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l og /dev/null -cm_name 1.chip_sw_hmac_multistream.3885661963 |
| Directory | /workspace/1.chip_sw_hmac_multistream/latest |
| Test location | /workspace/coverage/default/1.chip_sw_hmac_oneshot.876763250 |
| Short name | T1198 |
| Test name | |
| Test status | |
| Simulation time | 3409556116 ps |
| CPU time | 356.53 seconds |
| Started | Jun 23 08:00:17 PM PDT 24 |
| Finished | Jun 23 08:06:14 PM PDT 24 |
| Peak memory | 606868 kb |
| Host | smart-7ca549d1-1ce9-4385-9e8e-fd0cbff1212a |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=hmac_functest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=876763250 -assert nopostproc +UVM_TESTNAME=chip_ base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_hmac_oneshot.876763250 |
| Directory | /workspace/1.chip_sw_hmac_oneshot/latest |
| Test location | /workspace/coverage/default/1.chip_sw_hmac_smoketest.4057951210 |
| Short name | T1007 |
| Test name | |
| Test status | |
| Simulation time | 2649520280 ps |
| CPU time | 319.03 seconds |
| Started | Jun 23 08:05:58 PM PDT 24 |
| Finished | Jun 23 08:11:17 PM PDT 24 |
| Peak memory | 607548 kb |
| Host | smart-a1bf3969-a70d-43be-82cd-494ba35173c3 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=hmac_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4057951210 -assert nopostproc +UVM_TESTNAME=chi p_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul l -cm_name 1.chip_sw_hmac_smoketest.4057951210 |
| Directory | /workspace/1.chip_sw_hmac_smoketest/latest |
| Test location | /workspace/coverage/default/1.chip_sw_i2c_device_tx_rx.1097617137 |
| Short name | T1312 |
| Test name | |
| Test status | |
| Simulation time | 4153108914 ps |
| CPU time | 783.48 seconds |
| Started | Jun 23 07:56:10 PM PDT 24 |
| Finished | Jun 23 08:09:15 PM PDT 24 |
| Peak memory | 608064 kb |
| Host | smart-fbea6e2d-775d-4445-ab03-5c8f14172880 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=i2c_device_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1097617137 -assert nopostproc +UVM_TESTN AME=chip_base_test +UVM_TEST_SEQ=chip_sw_i2c_device_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v db -cm_log /dev/null -cm_name 1.chip_sw_i2c_device_tx_rx.1097617137 |
| Directory | /workspace/1.chip_sw_i2c_device_tx_rx/latest |
| Test location | /workspace/coverage/default/1.chip_sw_i2c_host_tx_rx_idx1.1699784331 |
| Short name | T321 |
| Test name | |
| Test status | |
| Simulation time | 5185799832 ps |
| CPU time | 836.46 seconds |
| Started | Jun 23 07:55:49 PM PDT 24 |
| Finished | Jun 23 08:09:46 PM PDT 24 |
| Peak memory | 607280 kb |
| Host | smart-b2b9f588-6330-4f28-b0ba-2d407e14efdd |
| User | root |
| Command | /workspace/default/simv +i2c_idx=1 +sw_build_device=sim_dv +sw_images=i2c_host_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1699784331 -assert nopostproc + UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_i2c_host_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de fault.vdb -cm_log /dev/null -cm_name 1.chip_sw_i2c_host_tx_rx_idx1.1699784331 |
| Directory | /workspace/1.chip_sw_i2c_host_tx_rx_idx1/latest |
| Test location | /workspace/coverage/default/1.chip_sw_i2c_host_tx_rx_idx2.2525730847 |
| Short name | T325 |
| Test name | |
| Test status | |
| Simulation time | 4969031256 ps |
| CPU time | 758.23 seconds |
| Started | Jun 23 07:55:41 PM PDT 24 |
| Finished | Jun 23 08:08:20 PM PDT 24 |
| Peak memory | 608032 kb |
| Host | smart-7aebb39f-bff6-409c-82cd-2d1293a1b763 |
| User | root |
| Command | /workspace/default/simv +i2c_idx=2 +sw_build_device=sim_dv +sw_images=i2c_host_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2525730847 -assert nopostproc + UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_i2c_host_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de fault.vdb -cm_log /dev/null -cm_name 1.chip_sw_i2c_host_tx_rx_idx2.2525730847 |
| Directory | /workspace/1.chip_sw_i2c_host_tx_rx_idx2/latest |
| Test location | /workspace/coverage/default/1.chip_sw_inject_scramble_seed.1563890342 |
| Short name | T1192 |
| Test name | |
| Test status | |
| Simulation time | 65358885363 ps |
| CPU time | 10867 seconds |
| Started | Jun 23 07:54:12 PM PDT 24 |
| Finished | Jun 23 10:55:20 PM PDT 24 |
| Peak memory | 616080 kb |
| Host | smart-bc5246f7-e21d-4b53-a404-2096a4d7ab2a |
| User | root |
| Command | /workspace/default/simv +lc_at_prod=1 +flash_program_latency=5 +sw_test_timeout_ns=150_000_000 +sw_build_device=sim_dv +sw_images=inject_scramble_seed :1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=1563890342 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_inject_scramble_seed_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_inject_scramble_seed.1563890342 |
| Directory | /workspace/1.chip_sw_inject_scramble_seed/latest |
| Test location | /workspace/coverage/default/1.chip_sw_keymgr_key_derivation.3588413362 |
| Short name | T1071 |
| Test name | |
| Test status | |
| Simulation time | 10933546470 ps |
| CPU time | 2511.23 seconds |
| Started | Jun 23 07:59:53 PM PDT 24 |
| Finished | Jun 23 08:41:47 PM PDT 24 |
| Peak memory | 615424 kb |
| Host | smart-53c74a0f-fc85-47d9-a5f0-30ce69285502 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=20_000_000 +sw_build_device=sim_dv +sw_images=keymgr_key_derivation_test:1:new_rules,test_rom:0 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3588 413362 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_keymgr_key_derivation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_keymgr_key_derivation.3588413362 |
| Directory | /workspace/1.chip_sw_keymgr_key_derivation/latest |
| Test location | /workspace/coverage/default/1.chip_sw_keymgr_key_derivation_jitter_en.1891662873 |
| Short name | T1143 |
| Test name | |
| Test status | |
| Simulation time | 6282715221 ps |
| CPU time | 1144.45 seconds |
| Started | Jun 23 08:00:02 PM PDT 24 |
| Finished | Jun 23 08:19:07 PM PDT 24 |
| Peak memory | 615452 kb |
| Host | smart-e91c25e2-1f8d-4e63-b53a-7f4b087872e8 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=20_000_000 +en_jitter=1 +sw_build_device=sim_dv +sw_images=keymgr_key_derivation_test:1:new_rules,test_rom :0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=1891662873 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_keymgr_key_derivation_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_keymgr_key_derivation_jitter_en.1891662873 |
| Directory | /workspace/1.chip_sw_keymgr_key_derivation_jitter_en/latest |
| Test location | /workspace/coverage/default/1.chip_sw_keymgr_key_derivation_jitter_en_reduced_freq.2797322139 |
| Short name | T1208 |
| Test name | |
| Test status | |
| Simulation time | 10413427087 ps |
| CPU time | 1821.24 seconds |
| Started | Jun 23 08:04:53 PM PDT 24 |
| Finished | Jun 23 08:35:15 PM PDT 24 |
| Peak memory | 615464 kb |
| Host | smart-109f03b6-a1a6-4046-9726-87b9ce5be2da |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=20_000_000 +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=keymgr_key_derivation_test :1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=2797322139 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_keymgr_key_derivation_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_keymgr_key_derivation_jitter_en _reduced_freq.2797322139 |
| Directory | /workspace/1.chip_sw_keymgr_key_derivation_jitter_en_reduced_freq/latest |
| Test location | /workspace/coverage/default/1.chip_sw_keymgr_key_derivation_prod.1813524217 |
| Short name | T1193 |
| Test name | |
| Test status | |
| Simulation time | 8536112200 ps |
| CPU time | 1886.6 seconds |
| Started | Jun 23 08:01:06 PM PDT 24 |
| Finished | Jun 23 08:32:34 PM PDT 24 |
| Peak memory | 615124 kb |
| Host | smart-ce33145b-546c-4dcf-ac4b-7f4a2c58871e |
| User | root |
| Command | /workspace/default/simv +lc_at_prod=1 +sw_test_timeout_ns=20_000_000 +sw_build_device=sim_dv +sw_images=keymgr_key_derivation_test:1:new_rules,test_ro m:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=1813524217 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_keymgr_key_derivation_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_keymgr_key_derivation_prod.1813524217 |
| Directory | /workspace/1.chip_sw_keymgr_key_derivation_prod/latest |
| Test location | /workspace/coverage/default/1.chip_sw_keymgr_sideload_kmac.3160036666 |
| Short name | T1243 |
| Test name | |
| Test status | |
| Simulation time | 8937908412 ps |
| CPU time | 1869.2 seconds |
| Started | Jun 23 07:59:39 PM PDT 24 |
| Finished | Jun 23 08:30:49 PM PDT 24 |
| Peak memory | 608416 kb |
| Host | smart-26d43931-777d-4f02-b19a-fff7968fb751 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=20_000_000 +sw_build_device=sim_dv +sw_images=keymgr_sideload_kmac_test:1:new_rules,test_rom:0 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31600 36666 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_keymgr_sideload_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_keymgr_sideload_kmac.3160036666 |
| Directory | /workspace/1.chip_sw_keymgr_sideload_kmac/latest |
| Test location | /workspace/coverage/default/1.chip_sw_keymgr_sideload_otbn.3061439386 |
| Short name | T227 |
| Test name | |
| Test status | |
| Simulation time | 16341086838 ps |
| CPU time | 4316 seconds |
| Started | Jun 23 07:59:42 PM PDT 24 |
| Finished | Jun 23 09:11:38 PM PDT 24 |
| Peak memory | 608532 kb |
| Host | smart-47b42ba0-9074-4495-abf0-51d763485e41 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=20_000_000 +sw_build_device=sim_dv +sw_images=keymgr_sideload_otbn_test:1:new_rules,test_rom:0 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30614 39386 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_keymgr_sideload_otbn.3061439386 |
| Directory | /workspace/1.chip_sw_keymgr_sideload_otbn/latest |
| Test location | /workspace/coverage/default/1.chip_sw_kmac_app_rom.3542478900 |
| Short name | T1311 |
| Test name | |
| Test status | |
| Simulation time | 2691343400 ps |
| CPU time | 192.8 seconds |
| Started | Jun 23 08:00:42 PM PDT 24 |
| Finished | Jun 23 08:03:56 PM PDT 24 |
| Peak memory | 607584 kb |
| Host | smart-86995fa2-11dd-4796-8e03-072964d0bad2 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=kmac_app_rom_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3542478900 -assert nopostproc +UVM_TESTNAME= chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/ null -cm_name 1.chip_sw_kmac_app_rom.3542478900 |
| Directory | /workspace/1.chip_sw_kmac_app_rom/latest |
| Test location | /workspace/coverage/default/1.chip_sw_kmac_entropy.2071512260 |
| Short name | T423 |
| Test name | |
| Test status | |
| Simulation time | 2687208140 ps |
| CPU time | 265.12 seconds |
| Started | Jun 23 07:55:53 PM PDT 24 |
| Finished | Jun 23 08:00:19 PM PDT 24 |
| Peak memory | 607820 kb |
| Host | smart-5c4119a3-00b7-43a4-9949-7a1fee02df25 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=kmac_entropy_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2071512260 -assert nopostproc +UVM_TESTNAME= chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/ null -cm_name 1.chip_sw_kmac_entropy.2071512260 |
| Directory | /workspace/1.chip_sw_kmac_entropy/latest |
| Test location | /workspace/coverage/default/1.chip_sw_kmac_idle.4193092825 |
| Short name | T1116 |
| Test name | |
| Test status | |
| Simulation time | 2660950360 ps |
| CPU time | 270.8 seconds |
| Started | Jun 23 08:02:30 PM PDT 24 |
| Finished | Jun 23 08:07:02 PM PDT 24 |
| Peak memory | 607992 kb |
| Host | smart-804ca65f-8fff-44bc-b379-403dafd6cb2f |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=kmac_idle_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4193092825 -assert nopostproc +UVM_TESTNAME=chi p_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul l -cm_name 1.chip_sw_kmac_idle.4193092825 |
| Directory | /workspace/1.chip_sw_kmac_idle/latest |
| Test location | /workspace/coverage/default/1.chip_sw_kmac_mode_cshake.3456302207 |
| Short name | T421 |
| Test name | |
| Test status | |
| Simulation time | 2731345864 ps |
| CPU time | 267.07 seconds |
| Started | Jun 23 08:01:16 PM PDT 24 |
| Finished | Jun 23 08:05:44 PM PDT 24 |
| Peak memory | 606924 kb |
| Host | smart-9bc491d6-4d96-40a6-b57d-521235e5c5bc |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=kmac_mode_cshake_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3456302207 -assert nopostproc +UVM_TESTN AME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log / dev/null -cm_name 1.chip_sw_kmac_mode_cshake.3456302207 |
| Directory | /workspace/1.chip_sw_kmac_mode_cshake/latest |
| Test location | /workspace/coverage/default/1.chip_sw_kmac_mode_kmac.2351453786 |
| Short name | T1069 |
| Test name | |
| Test status | |
| Simulation time | 2756368544 ps |
| CPU time | 269.4 seconds |
| Started | Jun 23 07:59:13 PM PDT 24 |
| Finished | Jun 23 08:03:42 PM PDT 24 |
| Peak memory | 606856 kb |
| Host | smart-30478040-b7ee-4518-8fd8-94b787e93c5d |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=kmac_mode_kmac_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2351453786 -assert nopostproc +UVM_TESTNAM E=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 1.chip_sw_kmac_mode_kmac.2351453786 |
| Directory | /workspace/1.chip_sw_kmac_mode_kmac/latest |
| Test location | /workspace/coverage/default/1.chip_sw_kmac_mode_kmac_jitter_en.401731567 |
| Short name | T307 |
| Test name | |
| Test status | |
| Simulation time | 2660918048 ps |
| CPU time | 369.98 seconds |
| Started | Jun 23 08:01:14 PM PDT 24 |
| Finished | Jun 23 08:07:24 PM PDT 24 |
| Peak memory | 607188 kb |
| Host | smart-51a6c1fb-7c3a-4e99-8a75-3414a11389e2 |
| User | root |
| Command | /workspace/default/simv +en_jitter=1 +sw_build_device=sim_dv +sw_images=kmac_mode_kmac_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=401731567 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_kmac_mode_kmac_jitter_en.401731567 |
| Directory | /workspace/1.chip_sw_kmac_mode_kmac_jitter_en/latest |
| Test location | /workspace/coverage/default/1.chip_sw_kmac_mode_kmac_jitter_en_reduced_freq.1686640077 |
| Short name | T1292 |
| Test name | |
| Test status | |
| Simulation time | 2740720736 ps |
| CPU time | 341.25 seconds |
| Started | Jun 23 08:04:25 PM PDT 24 |
| Finished | Jun 23 08:10:07 PM PDT 24 |
| Peak memory | 607452 kb |
| Host | smart-525fb7ff-f800-4cff-9f03-cba92192a01b |
| User | root |
| Command | /workspace/default/simv +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=kmac_mode_kmac_test:1:new_rules,test_rom:0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16866400 77 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac e/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_kmac_mode_kmac_jitter_en_reduced_freq.1686640077 |
| Directory | /workspace/1.chip_sw_kmac_mode_kmac_jitter_en_reduced_freq/latest |
| Test location | /workspace/coverage/default/1.chip_sw_kmac_smoketest.2929937581 |
| Short name | T1117 |
| Test name | |
| Test status | |
| Simulation time | 2461649270 ps |
| CPU time | 314.59 seconds |
| Started | Jun 23 08:05:26 PM PDT 24 |
| Finished | Jun 23 08:10:41 PM PDT 24 |
| Peak memory | 607584 kb |
| Host | smart-a0e044e9-faf1-42c8-8ab4-fd371dea7a43 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=kmac_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2929937581 -assert nopostproc +UVM_TESTNAME=chi p_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul l -cm_name 1.chip_sw_kmac_smoketest.2929937581 |
| Directory | /workspace/1.chip_sw_kmac_smoketest/latest |
| Test location | /workspace/coverage/default/1.chip_sw_lc_ctrl_otp_hw_cfg0.1397435260 |
| Short name | T926 |
| Test name | |
| Test status | |
| Simulation time | 2731939100 ps |
| CPU time | 226.72 seconds |
| Started | Jun 23 07:55:29 PM PDT 24 |
| Finished | Jun 23 07:59:17 PM PDT 24 |
| Peak memory | 606940 kb |
| Host | smart-f0c59540-05ac-49e4-9d9d-4a040c8bb443 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=lc_ctrl_otp_hw_cfg0_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1397435260 -assert nopostproc +UVM_TE STNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo g /dev/null -cm_name 1.chip_sw_lc_ctrl_otp_hw_cfg0.1397435260 |
| Directory | /workspace/1.chip_sw_lc_ctrl_otp_hw_cfg0/latest |
| Test location | /workspace/coverage/default/1.chip_sw_lc_ctrl_rand_to_scrap.3840636194 |
| Short name | T262 |
| Test name | |
| Test status | |
| Simulation time | 3821555683 ps |
| CPU time | 253.49 seconds |
| Started | Jun 23 07:55:12 PM PDT 24 |
| Finished | Jun 23 07:59:26 PM PDT 24 |
| Peak memory | 618228 kb |
| Host | smart-58b4b699-78ed-4cc5-a762-8ed877b17acc |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=lc_ctrl_scrap_test:1:new_rules,test_rom:0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38406361 94 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_scrap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_lc_ctrl_rand_to_scrap.3840636194 |
| Directory | /workspace/1.chip_sw_lc_ctrl_rand_to_scrap/latest |
| Test location | /workspace/coverage/default/1.chip_sw_lc_ctrl_transition.4228262201 |
| Short name | T410 |
| Test name | |
| Test status | |
| Simulation time | 10989355597 ps |
| CPU time | 878.15 seconds |
| Started | Jun 23 07:58:27 PM PDT 24 |
| Finished | Jun 23 08:13:05 PM PDT 24 |
| Peak memory | 620416 kb |
| Host | smart-8fbe1453-7061-4363-a6c3-18fe2598c5aa |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=lc_ctrl_transition_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4228262201 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_transition_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau lt.vdb -cm_log /dev/null -cm_name 1.chip_sw_lc_ctrl_transition.4228262201 |
| Directory | /workspace/1.chip_sw_lc_ctrl_transition/latest |
| Test location | /workspace/coverage/default/1.chip_sw_lc_ctrl_volatile_raw_unlock.1530212776 |
| Short name | T261 |
| Test name | |
| Test status | |
| Simulation time | 2976368891 ps |
| CPU time | 107.91 seconds |
| Started | Jun 23 07:59:49 PM PDT 24 |
| Finished | Jun 23 08:01:37 PM PDT 24 |
| Peak memory | 615592 kb |
| Host | smart-f669d1ce-c87a-4adf-83db-8e606eb2380e |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStRaw +exp_volatile_raw_unlock_en=0 +sw_build_device=sim_dv +sw_images=lc_ctrl_volatile_raw_unlock_tes t:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/ tools/sim.tcl +ntb_random_seed=1530212776 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_volatile_raw_unlock_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_lc_ctrl_volatile_raw_unlock.1530212776 |
| Directory | /workspace/1.chip_sw_lc_ctrl_volatile_raw_unlock/latest |
| Test location | /workspace/coverage/default/1.chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz.1599300063 |
| Short name | T1050 |
| Test name | |
| Test status | |
| Simulation time | 2468466420 ps |
| CPU time | 111.17 seconds |
| Started | Jun 23 07:56:59 PM PDT 24 |
| Finished | Jun 23 07:58:50 PM PDT 24 |
| Peak memory | 613544 kb |
| Host | smart-619fc02b-49a1-451a-af0f-0135e1d57a9a |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStRaw +chip_clock_source=ChipClockSourceExternal48Mhz +exp_volatile_raw_unlock_en=0 +sw_build_device=s im_dv +sw_images=lc_ctrl_volatile_raw_unlock_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1599300063 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TES T_SEQ=chip_sw_lc_volatile_raw_unlock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz.1599300063 |
| Directory | /workspace/1.chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz/latest |
| Test location | /workspace/coverage/default/1.chip_sw_lc_walkthrough_dev.52750882 |
| Short name | T1154 |
| Test name | |
| Test status | |
| Simulation time | 49370933242 ps |
| CPU time | 5813.73 seconds |
| Started | Jun 23 07:55:32 PM PDT 24 |
| Finished | Jun 23 09:32:28 PM PDT 24 |
| Peak memory | 617424 kb |
| Host | smart-6f614ceb-2d4f-4221-9a4b-94c404a60664 |
| User | root |
| Command | /workspace/default/simv +flash_program_latency=5 +use_otp_image=OtpTypeLcStRaw +dest_dec_state=DecLcStDev +sw_test_timeout_ns=200_000_000 +sw_build_de vice=sim_dv +sw_images=lc_walkthrough_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52750882 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chi p_sw_lc_walkthrough_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_s w_lc_walkthrough_dev.52750882 |
| Directory | /workspace/1.chip_sw_lc_walkthrough_dev/latest |
| Test location | /workspace/coverage/default/1.chip_sw_lc_walkthrough_prod.228275517 |
| Short name | T235 |
| Test name | |
| Test status | |
| Simulation time | 50165106956 ps |
| CPU time | 5674.11 seconds |
| Started | Jun 23 07:57:51 PM PDT 24 |
| Finished | Jun 23 09:32:27 PM PDT 24 |
| Peak memory | 614392 kb |
| Host | smart-0ff87dee-9526-4431-96b1-1cfa68653835 |
| User | root |
| Command | /workspace/default/simv +flash_program_latency=5 +use_otp_image=OtpTypeLcStRaw +dest_dec_state=DecLcStProd +sw_test_timeout_ns=200_000_000 +sw_build_d evice=sim_dv +sw_images=lc_walkthrough_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=228275517 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=c hip_sw_lc_walkthrough_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip _sw_lc_walkthrough_prod.228275517 |
| Directory | /workspace/1.chip_sw_lc_walkthrough_prod/latest |
| Test location | /workspace/coverage/default/1.chip_sw_lc_walkthrough_prodend.1596258016 |
| Short name | T288 |
| Test name | |
| Test status | |
| Simulation time | 8301149208 ps |
| CPU time | 797.69 seconds |
| Started | Jun 23 07:59:02 PM PDT 24 |
| Finished | Jun 23 08:12:21 PM PDT 24 |
| Peak memory | 617888 kb |
| Host | smart-6ed5a47c-af18-46cf-b53f-186ece53e512 |
| User | root |
| Command | /workspace/default/simv +flash_program_latency=5 +use_otp_image=OtpTypeLcStRaw +dest_dec_state=DecLcStProdEnd +sw_build_device=sim_dv +sw_images=lc_wa lkthrough_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1596258016 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_walkthrough_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_lc_walkthrough_prodend.1596258016 |
| Directory | /workspace/1.chip_sw_lc_walkthrough_prodend/latest |
| Test location | /workspace/coverage/default/1.chip_sw_lc_walkthrough_rma.3455791561 |
| Short name | T1350 |
| Test name | |
| Test status | |
| Simulation time | 49858907280 ps |
| CPU time | 5549.26 seconds |
| Started | Jun 23 07:56:17 PM PDT 24 |
| Finished | Jun 23 09:28:47 PM PDT 24 |
| Peak memory | 618136 kb |
| Host | smart-5bbceda5-9024-4b40-a923-3854d15b10ef |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStRaw +dest_dec_state=DecLcStRma +flash_program_latency=5 +sw_test_timeout_ns=200_000_000 +sw_build_de vice=sim_dv +sw_images=lc_walkthrough_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3455791561 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=c hip_sw_lc_walkthrough_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip _sw_lc_walkthrough_rma.3455791561 |
| Directory | /workspace/1.chip_sw_lc_walkthrough_rma/latest |
| Test location | /workspace/coverage/default/1.chip_sw_otbn_ecdsa_op_irq.3131582020 |
| Short name | T303 |
| Test name | |
| Test status | |
| Simulation time | 17353413002 ps |
| CPU time | 3707.14 seconds |
| Started | Jun 23 07:57:42 PM PDT 24 |
| Finished | Jun 23 08:59:30 PM PDT 24 |
| Peak memory | 608228 kb |
| Host | smart-93f804df-a3fd-46b1-9534-af6d3cb6fc40 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=28_000_000 +rng_srate_value=30 +sw_build_device=sim_dv +sw_images=otbn_ecdsa_op_irq_test:1:new_rules,test_ rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ random_seed=3131582020 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_otbn_ecdsa_op_irq.3131582020 |
| Directory | /workspace/1.chip_sw_otbn_ecdsa_op_irq/latest |
| Test location | /workspace/coverage/default/1.chip_sw_otbn_ecdsa_op_irq_jitter_en.154957224 |
| Short name | T1360 |
| Test name | |
| Test status | |
| Simulation time | 17907021038 ps |
| CPU time | 3860.38 seconds |
| Started | Jun 23 07:57:15 PM PDT 24 |
| Finished | Jun 23 09:01:36 PM PDT 24 |
| Peak memory | 607916 kb |
| Host | smart-a037915c-52d0-49b5-b92a-601c57d30be3 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=33_000_000 +rng_srate_value=30 +en_jitter=1 +sw_build_device=sim_dv +sw_images=otbn_ecdsa_op_irq_test:1:ne w_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/ sim.tcl +ntb_random_seed=154957224 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_otbn_ecdsa_op_irq_jitter_en.154957224 |
| Directory | /workspace/1.chip_sw_otbn_ecdsa_op_irq_jitter_en/latest |
| Test location | /workspace/coverage/default/1.chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq.374973567 |
| Short name | T1049 |
| Test name | |
| Test status | |
| Simulation time | 25339515591 ps |
| CPU time | 3400.38 seconds |
| Started | Jun 23 08:03:45 PM PDT 24 |
| Finished | Jun 23 09:00:26 PM PDT 24 |
| Peak memory | 607952 kb |
| Host | smart-2b5e13c4-1f33-47bb-8ac2-eff067fb1871 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=33_000_000 +rng_srate_value=30 +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=otbn_e cdsa_op_irq_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/ repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=374973567 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_otbn_ecdsa_op_irq_jitter_en_reduc ed_freq.374973567 |
| Directory | /workspace/1.chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq/latest |
| Test location | /workspace/coverage/default/1.chip_sw_otbn_mem_scramble.3894325098 |
| Short name | T283 |
| Test name | |
| Test status | |
| Simulation time | 3259532248 ps |
| CPU time | 509.05 seconds |
| Started | Jun 23 07:59:24 PM PDT 24 |
| Finished | Jun 23 08:07:54 PM PDT 24 |
| Peak memory | 607828 kb |
| Host | smart-da8aa1a6-92b0-4bee-b140-f861558cf142 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=15_000_000 +en_scb_tl_err_chk=0 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=otbn _mem_scramble_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3894325098 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_otbn_mem_scramble.3894325098 |
| Directory | /workspace/1.chip_sw_otbn_mem_scramble/latest |
| Test location | /workspace/coverage/default/1.chip_sw_otbn_randomness.2800147790 |
| Short name | T1180 |
| Test name | |
| Test status | |
| Simulation time | 6297334162 ps |
| CPU time | 1009.49 seconds |
| Started | Jun 23 07:57:59 PM PDT 24 |
| Finished | Jun 23 08:14:49 PM PDT 24 |
| Peak memory | 608204 kb |
| Host | smart-afb62aa0-4085-44c0-a293-32a53d53c9b9 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +rng_srate_value=30 +sw_build_device=sim_dv +sw_images=otbn_randomness_test:1:new_rules,test_ro m:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=2800147790 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_otbn_randomness.2800147790 |
| Directory | /workspace/1.chip_sw_otbn_randomness/latest |
| Test location | /workspace/coverage/default/1.chip_sw_otbn_smoketest.1613708064 |
| Short name | T1213 |
| Test name | |
| Test status | |
| Simulation time | 5106768892 ps |
| CPU time | 1099.92 seconds |
| Started | Jun 23 08:05:10 PM PDT 24 |
| Finished | Jun 23 08:23:30 PM PDT 24 |
| Peak memory | 608052 kb |
| Host | smart-d1a0bb22-53d1-4754-935c-97ff009dadb3 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=otbn_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1613708064 -assert nopostproc +UVM_TESTNAME=chi p_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul l -cm_name 1.chip_sw_otbn_smoketest.1613708064 |
| Directory | /workspace/1.chip_sw_otbn_smoketest/latest |
| Test location | /workspace/coverage/default/1.chip_sw_otp_ctrl_ecc_error_vendor_test.1185047600 |
| Short name | T1099 |
| Test name | |
| Test status | |
| Simulation time | 3473386054 ps |
| CPU time | 312.86 seconds |
| Started | Jun 23 07:55:57 PM PDT 24 |
| Finished | Jun 23 08:01:10 PM PDT 24 |
| Peak memory | 607700 kb |
| Host | smart-f406a939-bc4f-4a41-8c79-430c21f0ffcf |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=otp_ctrl_vendor_test_ecc_error_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1185047600 -assert nopostp roc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_otp_ctrl_vendor_test_ecc_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_otp_ctrl_ecc_error_vendor_test.1185047600 |
| Directory | /workspace/1.chip_sw_otp_ctrl_ecc_error_vendor_test/latest |
| Test location | /workspace/coverage/default/1.chip_sw_otp_ctrl_lc_signals_dev.2394261349 |
| Short name | T219 |
| Test name | |
| Test status | |
| Simulation time | 8398925882 ps |
| CPU time | 1178.31 seconds |
| Started | Jun 23 07:56:02 PM PDT 24 |
| Finished | Jun 23 08:15:41 PM PDT 24 |
| Peak memory | 607352 kb |
| Host | smart-6ac4c0f4-d89b-4b1e-acdd-3b3ac41fc099 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStDev +otp_clear_secret2=1 +sw_build_device=sim_dv +sw_images=otp_ctrl_lc_signals_test:1:new_rules,tes t_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +nt b_random_seed=2394261349 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_otp_ctrl_lc_signals_dev.2394261349 |
| Directory | /workspace/1.chip_sw_otp_ctrl_lc_signals_dev/latest |
| Test location | /workspace/coverage/default/1.chip_sw_otp_ctrl_lc_signals_prod.2765044720 |
| Short name | T993 |
| Test name | |
| Test status | |
| Simulation time | 6319208756 ps |
| CPU time | 1526.94 seconds |
| Started | Jun 23 07:56:07 PM PDT 24 |
| Finished | Jun 23 08:21:34 PM PDT 24 |
| Peak memory | 608008 kb |
| Host | smart-8ab79ca1-b728-4797-8a40-436ec266e7e7 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStProd +otp_clear_secret2=1 +sw_build_device=sim_dv +sw_images=otp_ctrl_lc_signals_test:1:new_rules,te st_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n tb_random_seed=2765044720 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_otp_ctrl_lc_signals_prod.2765044720 |
| Directory | /workspace/1.chip_sw_otp_ctrl_lc_signals_prod/latest |
| Test location | /workspace/coverage/default/1.chip_sw_otp_ctrl_lc_signals_rma.1804724467 |
| Short name | T221 |
| Test name | |
| Test status | |
| Simulation time | 7125365558 ps |
| CPU time | 1179.77 seconds |
| Started | Jun 23 07:57:37 PM PDT 24 |
| Finished | Jun 23 08:17:17 PM PDT 24 |
| Peak memory | 607372 kb |
| Host | smart-7d5e045a-6fec-4d7b-8bad-5c478d8388aa |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStRma +otp_clear_secret2=1 +sw_build_device=sim_dv +sw_images=otp_ctrl_lc_signals_test:1:new_rules,tes t_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +nt b_random_seed=1804724467 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_otp_ctrl_lc_signals_rma.1804724467 |
| Directory | /workspace/1.chip_sw_otp_ctrl_lc_signals_rma/latest |
| Test location | /workspace/coverage/default/1.chip_sw_otp_ctrl_lc_signals_test_unlocked0.2718953907 |
| Short name | T1057 |
| Test name | |
| Test status | |
| Simulation time | 4522499502 ps |
| CPU time | 729.97 seconds |
| Started | Jun 23 07:56:36 PM PDT 24 |
| Finished | Jun 23 08:08:46 PM PDT 24 |
| Peak memory | 607836 kb |
| Host | smart-321d7a26-bdba-4222-8248-7540a9b0f93a |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStTestUnlocked0 +otp_clear_secret2=1 +sw_build_device=sim_dv +sw_images=otp_ctrl_lc_signals_test:1:new _rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/s im.tcl +ntb_random_seed=2718953907 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_otp_ctrl_lc_signals_test_unlocked0.2718953907 |
| Directory | /workspace/1.chip_sw_otp_ctrl_lc_signals_test_unlocked0/latest |
| Test location | /workspace/coverage/default/1.chip_sw_otp_ctrl_smoketest.2938707338 |
| Short name | T506 |
| Test name | |
| Test status | |
| Simulation time | 2578127020 ps |
| CPU time | 215.4 seconds |
| Started | Jun 23 08:06:13 PM PDT 24 |
| Finished | Jun 23 08:09:48 PM PDT 24 |
| Peak memory | 607272 kb |
| Host | smart-8097df69-9892-410e-a054-bec3b2c66918 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=otp_ctrl_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2938707338 -assert nopostproc +UVM_TESTNAME =chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 1.chip_sw_otp_ctrl_smoketest.2938707338 |
| Directory | /workspace/1.chip_sw_otp_ctrl_smoketest/latest |
| Test location | /workspace/coverage/default/1.chip_sw_pattgen_ios.167637279 |
| Short name | T730 |
| Test name | |
| Test status | |
| Simulation time | 3076058212 ps |
| CPU time | 324.84 seconds |
| Started | Jun 23 07:55:16 PM PDT 24 |
| Finished | Jun 23 08:00:42 PM PDT 24 |
| Peak memory | 608120 kb |
| Host | smart-7bb2dc03-baf5-4141-8d37-dcd6cf9c1ac6 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=5_000_000 +sw_build_device=sim_dv +sw_images=pattgen_ios_test:1:new_rules,test_rom:0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=167637279 -asse rt nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_patt_ios_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co verage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pattgen_ios.167637279 |
| Directory | /workspace/1.chip_sw_pattgen_ios/latest |
| Test location | /workspace/coverage/default/1.chip_sw_plic_sw_irq.3124656342 |
| Short name | T241 |
| Test name | |
| Test status | |
| Simulation time | 3253566190 ps |
| CPU time | 353.64 seconds |
| Started | Jun 23 08:01:06 PM PDT 24 |
| Finished | Jun 23 08:07:00 PM PDT 24 |
| Peak memory | 607584 kb |
| Host | smart-bbeb35ff-c1f1-4429-a88c-f8f0070fd67e |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=plic_sw_irq_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3124656342 -assert nopostproc +UVM_TESTNAME=c hip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n ull -cm_name 1.chip_sw_plic_sw_irq.3124656342 |
| Directory | /workspace/1.chip_sw_plic_sw_irq/latest |
| Test location | /workspace/coverage/default/1.chip_sw_power_idle_load.3129218458 |
| Short name | T1164 |
| Test name | |
| Test status | |
| Simulation time | 4400033460 ps |
| CPU time | 793.06 seconds |
| Started | Jun 23 08:04:17 PM PDT 24 |
| Finished | Jun 23 08:17:30 PM PDT 24 |
| Peak memory | 607296 kb |
| Host | smart-5758e3e5-2ddd-47bd-887a-755e2c4898cf |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=chip_power_idle_load:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3129218458 -assert nopostproc +UVM_TESTNA ME=chip_base_test +UVM_TEST_SEQ=chip_sw_power_idle_load_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_power_idle_load.3129218458 |
| Directory | /workspace/1.chip_sw_power_idle_load/latest |
| Test location | /workspace/coverage/default/1.chip_sw_power_sleep_load.157621993 |
| Short name | T725 |
| Test name | |
| Test status | |
| Simulation time | 4562930668 ps |
| CPU time | 464.3 seconds |
| Started | Jun 23 08:06:03 PM PDT 24 |
| Finished | Jun 23 08:13:48 PM PDT 24 |
| Peak memory | 607412 kb |
| Host | smart-d7c24969-0bd9-40e5-8091-67e72881e9ec |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=chip_power_sleep_load:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=157621993 -assert nopostproc +UVM_TESTNA ME=chip_base_test +UVM_TEST_SEQ=chip_sw_power_sleep_load_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd b -cm_log /dev/null -cm_name 1.chip_sw_power_sleep_load.157621993 |
| Directory | /workspace/1.chip_sw_power_sleep_load/latest |
| Test location | /workspace/coverage/default/1.chip_sw_pwrmgr_all_reset_reqs.1796577835 |
| Short name | T311 |
| Test name | |
| Test status | |
| Simulation time | 12860143308 ps |
| CPU time | 1467.09 seconds |
| Started | Jun 23 07:57:48 PM PDT 24 |
| Finished | Jun 23 08:22:16 PM PDT 24 |
| Peak memory | 609148 kb |
| Host | smart-b48b603a-dac7-4c49-899f-5b6c6d60651c |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=50_000_000 +sw_build_device=sim_dv +sw_images=pwrmgr_all_reset_reqs_test:1:new_rules,test_rom:0 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1796 577835 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_deep_sleep_all_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_all_reset_reqs.1796577835 |
| Directory | /workspace/1.chip_sw_pwrmgr_all_reset_reqs/latest |
| Test location | /workspace/coverage/default/1.chip_sw_pwrmgr_b2b_sleep_reset_req.575008970 |
| Short name | T1299 |
| Test name | |
| Test status | |
| Simulation time | 32814308684 ps |
| CPU time | 2401.33 seconds |
| Started | Jun 23 08:00:30 PM PDT 24 |
| Finished | Jun 23 08:40:31 PM PDT 24 |
| Peak memory | 608420 kb |
| Host | smart-da23f8d1-6b57-4431-8da0-185e5cb4b1e7 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=35_000_000 +sw_build_device=sim_dv +sw_images=pwrmgr_b2b_sleep_reset_test:1:new_rules,test_rom:0 +cdc_inst rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=575 008970 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_repeat_reset_wkup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_b2b_sleep_reset_req.575008970 |
| Directory | /workspace/1.chip_sw_pwrmgr_b2b_sleep_reset_req/latest |
| Test location | /workspace/coverage/default/1.chip_sw_pwrmgr_deep_sleep_all_reset_reqs.3140326878 |
| Short name | T1224 |
| Test name | |
| Test status | |
| Simulation time | 12118259736 ps |
| CPU time | 1377.8 seconds |
| Started | Jun 23 07:59:07 PM PDT 24 |
| Finished | Jun 23 08:22:05 PM PDT 24 |
| Peak memory | 609348 kb |
| Host | smart-efdfd0f2-7871-4d31-9d18-52eee4565375 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=50_000_000 +sw_build_device=sim_dv +sw_images=pwrmgr_deep_sleep_all_reset_reqs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=3140326878 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_deep_sleep_all_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_deep_sleep_all_reset_reqs.3140326878 |
| Directory | /workspace/1.chip_sw_pwrmgr_deep_sleep_all_reset_reqs/latest |
| Test location | /workspace/coverage/default/1.chip_sw_pwrmgr_deep_sleep_por_reset.30103640 |
| Short name | T1021 |
| Test name | |
| Test status | |
| Simulation time | 8033932800 ps |
| CPU time | 1041.76 seconds |
| Started | Jun 23 07:57:24 PM PDT 24 |
| Finished | Jun 23 08:14:46 PM PDT 24 |
| Peak memory | 607236 kb |
| Host | smart-4ac22ef8-d15e-445d-bffc-c2f87b6e2ca3 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_deep_sleep_por_reset_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30103640 -assert nopostproc + UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sleep_por_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/d efault.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_deep_sleep_por_reset.30103640 |
| Directory | /workspace/1.chip_sw_pwrmgr_deep_sleep_por_reset/latest |
| Test location | /workspace/coverage/default/1.chip_sw_pwrmgr_deep_sleep_power_glitch_reset.2423347586 |
| Short name | T1246 |
| Test name | |
| Test status | |
| Simulation time | 6729110200 ps |
| CPU time | 672.97 seconds |
| Started | Jun 23 07:58:33 PM PDT 24 |
| Finished | Jun 23 08:09:46 PM PDT 24 |
| Peak memory | 614596 kb |
| Host | smart-3255a37e-f2a4-4bb4-aefd-dffe399a0cc6 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=pwrmgr_deep_sleep_power_glitch_test:1:new_rules,test_rom :0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=2423347586 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_deep_power_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_deep_sleep_power_glitch_reset.2423347586 |
| Directory | /workspace/1.chip_sw_pwrmgr_deep_sleep_power_glitch_reset/latest |
| Test location | /workspace/coverage/default/1.chip_sw_pwrmgr_full_aon_reset.2123060103 |
| Short name | T1316 |
| Test name | |
| Test status | |
| Simulation time | 6118350504 ps |
| CPU time | 500.69 seconds |
| Started | Jun 23 07:57:46 PM PDT 24 |
| Finished | Jun 23 08:06:07 PM PDT 24 |
| Peak memory | 608468 kb |
| Host | smart-58fd4cac-15ca-4e4d-b87d-0138fdeda66a |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=rstmgr_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2123060103 -assert nopostproc +UVM_TESTNAME=c hip_base_test +UVM_TEST_SEQ=chip_sw_full_aon_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_ log /dev/null -cm_name 1.chip_sw_pwrmgr_full_aon_reset.2123060103 |
| Directory | /workspace/1.chip_sw_pwrmgr_full_aon_reset/latest |
| Test location | /workspace/coverage/default/1.chip_sw_pwrmgr_lowpower_cancel.3339363715 |
| Short name | T328 |
| Test name | |
| Test status | |
| Simulation time | 3778445234 ps |
| CPU time | 445.77 seconds |
| Started | Jun 23 08:02:12 PM PDT 24 |
| Finished | Jun 23 08:09:38 PM PDT 24 |
| Peak memory | 606944 kb |
| Host | smart-d93447b6-6601-4020-ba46-35b15d81df3c |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_lowpower_cancel_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3339363715 -assert nopostproc +UVM _TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm _log /dev/null -cm_name 1.chip_sw_pwrmgr_lowpower_cancel.3339363715 |
| Directory | /workspace/1.chip_sw_pwrmgr_lowpower_cancel/latest |
| Test location | /workspace/coverage/default/1.chip_sw_pwrmgr_main_power_glitch_reset.733588535 |
| Short name | T103 |
| Test name | |
| Test status | |
| Simulation time | 4254421048 ps |
| CPU time | 412.45 seconds |
| Started | Jun 23 08:01:36 PM PDT 24 |
| Finished | Jun 23 08:08:29 PM PDT 24 |
| Peak memory | 613544 kb |
| Host | smart-ec4e1668-a1e7-41f4-84c0-aba688e51e8b |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=pwrmgr_main_power_glitch_test:1:new_rules,test_rom:0 +cd c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se ed=733588535 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_main_power_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_main_power_glitch_reset.733588535 |
| Directory | /workspace/1.chip_sw_pwrmgr_main_power_glitch_reset/latest |
| Test location | /workspace/coverage/default/1.chip_sw_pwrmgr_normal_sleep_all_reset_reqs.2202105720 |
| Short name | T310 |
| Test name | |
| Test status | |
| Simulation time | 11072683171 ps |
| CPU time | 1052.03 seconds |
| Started | Jun 23 07:57:06 PM PDT 24 |
| Finished | Jun 23 08:14:38 PM PDT 24 |
| Peak memory | 608924 kb |
| Host | smart-88caa510-97e5-4c01-9fc5-f114a7221515 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_normal_sleep_all_reset_reqs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2202105720 -assert nop ostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_deep_sleep_all_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_normal_sleep_all_reset_reqs.2202105720 |
| Directory | /workspace/1.chip_sw_pwrmgr_normal_sleep_all_reset_reqs/latest |
| Test location | /workspace/coverage/default/1.chip_sw_pwrmgr_normal_sleep_all_wake_ups.2789550749 |
| Short name | T1 |
| Test name | |
| Test status | |
| Simulation time | 7668471310 ps |
| CPU time | 478.8 seconds |
| Started | Jun 23 08:03:31 PM PDT 24 |
| Finished | Jun 23 08:11:30 PM PDT 24 |
| Peak memory | 607380 kb |
| Host | smart-9e1a6dbb-1d9a-4caa-9ec0-acc8a512ec65 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_normal_sleep_all_wake_ups:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2789550749 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_pwrmgr_deep_sleep_all_wake_ups_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_normal_sleep_all_wake_ups.2789550749 |
| Directory | /workspace/1.chip_sw_pwrmgr_normal_sleep_all_wake_ups/latest |
| Test location | /workspace/coverage/default/1.chip_sw_pwrmgr_normal_sleep_por_reset.1890449882 |
| Short name | T431 |
| Test name | |
| Test status | |
| Simulation time | 5151806619 ps |
| CPU time | 662.27 seconds |
| Started | Jun 23 07:57:09 PM PDT 24 |
| Finished | Jun 23 08:08:12 PM PDT 24 |
| Peak memory | 607156 kb |
| Host | smart-b91809d5-0e0f-45ba-98de-683a3a1492a1 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_normal_sleep_por_reset_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1890449882 -assert nopostpr oc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sleep_por_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera ge/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_normal_sleep_por_reset.1890449882 |
| Directory | /workspace/1.chip_sw_pwrmgr_normal_sleep_por_reset/latest |
| Test location | /workspace/coverage/default/1.chip_sw_pwrmgr_random_sleep_all_reset_reqs.1286054753 |
| Short name | T1064 |
| Test name | |
| Test status | |
| Simulation time | 23689846564 ps |
| CPU time | 2762.79 seconds |
| Started | Jun 23 07:58:45 PM PDT 24 |
| Finished | Jun 23 08:44:48 PM PDT 24 |
| Peak memory | 609248 kb |
| Host | smart-455e7e00-27b1-4937-87af-0ba817163e48 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=50_000_000 +sw_build_device=sim_dv +sw_images=pwrmgr_random_sleep_all_reset_reqs_test:1:new_rules,test_rom :0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=1286054753 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_deep_sleep_all_reset_vseq +en_cov=1 -cm line+cond+fsm+tg l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_random_sleep_all_reset_reqs.1286054753 |
| Directory | /workspace/1.chip_sw_pwrmgr_random_sleep_all_reset_reqs/latest |
| Test location | /workspace/coverage/default/1.chip_sw_pwrmgr_random_sleep_all_wake_ups.3780664540 |
| Short name | T10 |
| Test name | |
| Test status | |
| Simulation time | 23576378440 ps |
| CPU time | 1739.84 seconds |
| Started | Jun 23 08:02:50 PM PDT 24 |
| Finished | Jun 23 08:31:51 PM PDT 24 |
| Peak memory | 608328 kb |
| Host | smart-3f4f0763-921f-4e1c-9386-bc890a807bf8 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +do_random=1 +sw_build_device=sim_dv +sw_images=pwrmgr_random_sleep_all_wake_ups:1:new_rules,te st_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n tb_random_seed=3780664540 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_pwrmgr_deep_sleep_all_wake_ups_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_random_sleep_all_wake_ups.3780664540 |
| Directory | /workspace/1.chip_sw_pwrmgr_random_sleep_all_wake_ups/latest |
| Test location | /workspace/coverage/default/1.chip_sw_pwrmgr_random_sleep_power_glitch_reset.299695544 |
| Short name | T1313 |
| Test name | |
| Test status | |
| Simulation time | 36064797713 ps |
| CPU time | 3582.17 seconds |
| Started | Jun 23 07:59:37 PM PDT 24 |
| Finished | Jun 23 08:59:21 PM PDT 24 |
| Peak memory | 609604 kb |
| Host | smart-f2b0ad6c-7bd7-4bf7-932d-4f9da2a03be1 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_test_timeout_ns=24_000_000 +sw_build_device=sim_dv +sw_images=pwrmgr_random_sleep_power _glitch_reset_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=299695544 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_random_power_glitc h_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_random_sl eep_power_glitch_reset.299695544 |
| Directory | /workspace/1.chip_sw_pwrmgr_random_sleep_power_glitch_reset/latest |
| Test location | /workspace/coverage/default/1.chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up.1841653087 |
| Short name | T369 |
| Test name | |
| Test status | |
| Simulation time | 6226397960 ps |
| CPU time | 501.71 seconds |
| Started | Jun 23 08:04:33 PM PDT 24 |
| Finished | Jun 23 08:12:56 PM PDT 24 |
| Peak memory | 608652 kb |
| Host | smart-6125a48c-c225-4f28-837e-d3f475f8b0df |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +do_random=1 +sw_build_device=sim_dv +sw_images=pwrmgr_sensor_ctrl_deep_sleep_wake_up:1:new_rul es,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t cl +ntb_random_seed=1841653087 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_sensor_ctrl_deep_s leep_wake_up.1841653087 |
| Directory | /workspace/1.chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up/latest |
| Test location | /workspace/coverage/default/1.chip_sw_pwrmgr_sleep_disabled.1467654044 |
| Short name | T714 |
| Test name | |
| Test status | |
| Simulation time | 2616894886 ps |
| CPU time | 328.29 seconds |
| Started | Jun 23 07:57:33 PM PDT 24 |
| Finished | Jun 23 08:03:02 PM PDT 24 |
| Peak memory | 606940 kb |
| Host | smart-1c662781-eec8-4315-a844-512f807795c0 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_sleep_disabled_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1467654044 -assert nopostproc +UVM_ TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_ log /dev/null -cm_name 1.chip_sw_pwrmgr_sleep_disabled.1467654044 |
| Directory | /workspace/1.chip_sw_pwrmgr_sleep_disabled/latest |
| Test location | /workspace/coverage/default/1.chip_sw_pwrmgr_sleep_power_glitch_reset.626264188 |
| Short name | T1107 |
| Test name | |
| Test status | |
| Simulation time | 4507313037 ps |
| CPU time | 414.22 seconds |
| Started | Jun 23 07:55:56 PM PDT 24 |
| Finished | Jun 23 08:02:51 PM PDT 24 |
| Peak memory | 614180 kb |
| Host | smart-4562ef0e-eb5c-45bb-94ca-f129ea849fa3 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=pwrmgr_sleep_power_glitch_test:1:new_rules,test_rom:0 +c dc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_s eed=626264188 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_main_power_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_sleep_power_glitch_reset.626264188 |
| Directory | /workspace/1.chip_sw_pwrmgr_sleep_power_glitch_reset/latest |
| Test location | /workspace/coverage/default/1.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup.2782830091 |
| Short name | T126 |
| Test name | |
| Test status | |
| Simulation time | 5400997260 ps |
| CPU time | 557.71 seconds |
| Started | Jun 23 08:01:24 PM PDT 24 |
| Finished | Jun 23 08:10:42 PM PDT 24 |
| Peak memory | 607088 kb |
| Host | smart-1af0b9b2-d500-4384-a96d-dd35f8e25e56 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=8_000_000 +sw_build_device=sim_dv +sw_images=sensor_ctrl_wakeup_test:1:new_rules,test_rom:0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27828300 91 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac e/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup.2782830091 |
| Directory | /workspace/1.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup/latest |
| Test location | /workspace/coverage/default/1.chip_sw_pwrmgr_sleep_wake_5_bug.3947447974 |
| Short name | T1348 |
| Test name | |
| Test status | |
| Simulation time | 6910719232 ps |
| CPU time | 546.67 seconds |
| Started | Jun 23 08:02:26 PM PDT 24 |
| Finished | Jun 23 08:11:34 PM PDT 24 |
| Peak memory | 608652 kb |
| Host | smart-301a993c-3fa4-47c9-8aa2-e608424f9021 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +do_random=1 +sw_build_device=sim_dv +sw_images=pwrmgr_sleep_wake_5_bug_test:1:new_rules,test_r om:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r andom_seed=3947447974 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_sleep_wake_5_bug.3947447974 |
| Directory | /workspace/1.chip_sw_pwrmgr_sleep_wake_5_bug/latest |
| Test location | /workspace/coverage/default/1.chip_sw_pwrmgr_smoketest.3576691288 |
| Short name | T1130 |
| Test name | |
| Test status | |
| Simulation time | 5758999020 ps |
| CPU time | 274.15 seconds |
| Started | Jun 23 08:05:50 PM PDT 24 |
| Finished | Jun 23 08:10:25 PM PDT 24 |
| Peak memory | 606940 kb |
| Host | smart-d060bb36-9b96-409f-8e04-c25886faafe8 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=10000000 +sw_build_device=sim_dv +sw_images=pwrmgr_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3576691288 -asse rt nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera ge/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_smoketest.3576691288 |
| Directory | /workspace/1.chip_sw_pwrmgr_smoketest/latest |
| Test location | /workspace/coverage/default/1.chip_sw_pwrmgr_sysrst_ctrl_reset.1109264878 |
| Short name | T1304 |
| Test name | |
| Test status | |
| Simulation time | 7284203788 ps |
| CPU time | 1075.62 seconds |
| Started | Jun 23 08:01:33 PM PDT 24 |
| Finished | Jun 23 08:19:29 PM PDT 24 |
| Peak memory | 607896 kb |
| Host | smart-454235e2-6a24-4bd2-9252-f969fb8dd632 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_sysrst_ctrl_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1109264878 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_sysrst_ctrl_reset.1109264878 |
| Directory | /workspace/1.chip_sw_pwrmgr_sysrst_ctrl_reset/latest |
| Test location | /workspace/coverage/default/1.chip_sw_pwrmgr_usb_clk_disabled_when_active.3656397504 |
| Short name | T1186 |
| Test name | |
| Test status | |
| Simulation time | 4630362232 ps |
| CPU time | 339.22 seconds |
| Started | Jun 23 07:55:54 PM PDT 24 |
| Finished | Jun 23 08:01:34 PM PDT 24 |
| Peak memory | 608132 kb |
| Host | smart-c2d13ee1-1674-4239-9f47-8d96bf581f68 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_usb_clk_disabled_when_active_test:1:new_rules,test_rom:0 +cdc_instrumentation_enable d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3656397504 -assert no postproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de fault.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_usb_clk_disabled_when_active.3656397504 |
| Directory | /workspace/1.chip_sw_pwrmgr_usb_clk_disabled_when_active/latest |
| Test location | /workspace/coverage/default/1.chip_sw_pwrmgr_usbdev_smoketest.2016876700 |
| Short name | T394 |
| Test name | |
| Test status | |
| Simulation time | 5542304632 ps |
| CPU time | 373.37 seconds |
| Started | Jun 23 08:06:55 PM PDT 24 |
| Finished | Jun 23 08:13:09 PM PDT 24 |
| Peak memory | 607124 kb |
| Host | smart-1e8283a4-e424-4fdf-8f12-3a22135c4127 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_usbdev_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2016876700 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_usbdev_smoketest.2016876700 |
| Directory | /workspace/1.chip_sw_pwrmgr_usbdev_smoketest/latest |
| Test location | /workspace/coverage/default/1.chip_sw_pwrmgr_wdog_reset.1163453324 |
| Short name | T1205 |
| Test name | |
| Test status | |
| Simulation time | 5900352444 ps |
| CPU time | 741.43 seconds |
| Started | Jun 23 07:58:05 PM PDT 24 |
| Finished | Jun 23 08:10:27 PM PDT 24 |
| Peak memory | 607076 kb |
| Host | smart-9a4929bd-5051-4110-849c-3e88d6264758 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=pwrmgr_wdog_reset_reqs_test:1:new_rules,test_rom:0 +cdc_inst rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=116 3453324 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_wdog_reset.1163453324 |
| Directory | /workspace/1.chip_sw_pwrmgr_wdog_reset/latest |
| Test location | /workspace/coverage/default/1.chip_sw_rom_ctrl_integrity_check.1820269566 |
| Short name | T266 |
| Test name | |
| Test status | |
| Simulation time | 9159383599 ps |
| CPU time | 556.66 seconds |
| Started | Jun 23 08:01:10 PM PDT 24 |
| Finished | Jun 23 08:10:28 PM PDT 24 |
| Peak memory | 606992 kb |
| Host | smart-656f7c6a-6dba-4881-a092-e8cd7175e154 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=rom_ctrl_integrity_check_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1820269566 -assert nopostproc +U VM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_ctrl_integrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co verage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_rom_ctrl_integrity_check.1820269566 |
| Directory | /workspace/1.chip_sw_rom_ctrl_integrity_check/latest |
| Test location | /workspace/coverage/default/1.chip_sw_rstmgr_cpu_info.2822067159 |
| Short name | T237 |
| Test name | |
| Test status | |
| Simulation time | 6305868544 ps |
| CPU time | 783.44 seconds |
| Started | Jun 23 08:01:32 PM PDT 24 |
| Finished | Jun 23 08:14:36 PM PDT 24 |
| Peak memory | 607212 kb |
| Host | smart-0cf6f1de-2fb4-47d9-b0e0-b7109dc83a35 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=rstmgr_cpu_info_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2822067159 -assert nopostproc +UVM_TESTNA ME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 1.chip_sw_rstmgr_cpu_info.2822067159 |
| Directory | /workspace/1.chip_sw_rstmgr_cpu_info/latest |
| Test location | /workspace/coverage/default/1.chip_sw_rstmgr_rst_cnsty_escalation.2371065405 |
| Short name | T1240 |
| Test name | |
| Test status | |
| Simulation time | 5221969800 ps |
| CPU time | 840.38 seconds |
| Started | Jun 23 07:55:48 PM PDT 24 |
| Finished | Jun 23 08:09:49 PM PDT 24 |
| Peak memory | 639528 kb |
| Host | smart-f1634243-0377-49b9-9b0e-f07aede89da0 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 2371065405 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rstmgr_cnsty_fault_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_rstmgr_rst_cnsty_escalation.2371065405 |
| Directory | /workspace/1.chip_sw_rstmgr_rst_cnsty_escalation/latest |
| Test location | /workspace/coverage/default/1.chip_sw_rstmgr_smoketest.3679817385 |
| Short name | T995 |
| Test name | |
| Test status | |
| Simulation time | 2703088600 ps |
| CPU time | 206.93 seconds |
| Started | Jun 23 08:05:14 PM PDT 24 |
| Finished | Jun 23 08:08:42 PM PDT 24 |
| Peak memory | 607800 kb |
| Host | smart-fb5b767a-4e91-4f8c-895f-c0b1afdd754f |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=rstmgr_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3679817385 -assert nopostproc +UVM_TESTNAME=c hip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n ull -cm_name 1.chip_sw_rstmgr_smoketest.3679817385 |
| Directory | /workspace/1.chip_sw_rstmgr_smoketest/latest |
| Test location | /workspace/coverage/default/1.chip_sw_rstmgr_sw_req.960044349 |
| Short name | T950 |
| Test name | |
| Test status | |
| Simulation time | 3737448376 ps |
| CPU time | 298.41 seconds |
| Started | Jun 23 07:56:32 PM PDT 24 |
| Finished | Jun 23 08:01:31 PM PDT 24 |
| Peak memory | 606900 kb |
| Host | smart-01677536-0c01-48aa-8759-d2314c0b0bad |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=rstmgr_sw_req_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=960044349 -assert nopostproc +UVM_TESTNAME= chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/ null -cm_name 1.chip_sw_rstmgr_sw_req.960044349 |
| Directory | /workspace/1.chip_sw_rstmgr_sw_req/latest |
| Test location | /workspace/coverage/default/1.chip_sw_rstmgr_sw_rst.384784061 |
| Short name | T380 |
| Test name | |
| Test status | |
| Simulation time | 2856144550 ps |
| CPU time | 250.05 seconds |
| Started | Jun 23 08:00:33 PM PDT 24 |
| Finished | Jun 23 08:04:44 PM PDT 24 |
| Peak memory | 606924 kb |
| Host | smart-cbc571d0-3588-4b23-899c-288e16809f52 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=rstmgr_sw_rst_ctrl_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=384784061 -assert nopostproc +UVM_TEST NAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_rstmgr_sw_rst.384784061 |
| Directory | /workspace/1.chip_sw_rstmgr_sw_rst/latest |
| Test location | /workspace/coverage/default/1.chip_sw_rv_core_ibex_address_translation.324374027 |
| Short name | T293 |
| Test name | |
| Test status | |
| Simulation time | 3099907624 ps |
| CPU time | 371.57 seconds |
| Started | Jun 23 08:03:31 PM PDT 24 |
| Finished | Jun 23 08:09:43 PM PDT 24 |
| Peak memory | 607428 kb |
| Host | smart-44c07332-96b3-45bd-a71c-83a1dadd9efb |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=7_000_000 +sw_build_device=sim_dv +sw_images=rv_core_ibex_address_translation_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=324374027 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_rv_core_ibex_address_translation.324374027 |
| Directory | /workspace/1.chip_sw_rv_core_ibex_address_translation/latest |
| Test location | /workspace/coverage/default/1.chip_sw_rv_core_ibex_icache_invalidate.2651794147 |
| Short name | T172 |
| Test name | |
| Test status | |
| Simulation time | 2895308463 ps |
| CPU time | 316.06 seconds |
| Started | Jun 23 08:03:40 PM PDT 24 |
| Finished | Jun 23 08:08:57 PM PDT 24 |
| Peak memory | 607012 kb |
| Host | smart-732dc134-5aae-4d47-afcd-d07ec177427d |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=rv_core_ibex_icache_invalidate_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2651794147 -assert nopostp roc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rv_core_ibex_icache_invalidate_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_rv_core_ibex_icache_invalidate.2651794147 |
| Directory | /workspace/1.chip_sw_rv_core_ibex_icache_invalidate/latest |
| Test location | /workspace/coverage/default/1.chip_sw_rv_core_ibex_lockstep_glitch.791435664 |
| Short name | T1282 |
| Test name | |
| Test status | |
| Simulation time | 2821750316 ps |
| CPU time | 179.07 seconds |
| Started | Jun 23 08:03:59 PM PDT 24 |
| Finished | Jun 23 08:06:59 PM PDT 24 |
| Peak memory | 643552 kb |
| Host | smart-96bf86a9-7be1-4118-af7f-1bf1b2292832 |
| User | root |
| Command | /workspace/default/simv +disable_assert_final_checks +sw_build_device=sim_dv +sw_images=aes_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=791435664 -assert n opostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rv_core_ibex_lockstep_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_rv_core_ibex_lockstep_glitch.791435664 |
| Directory | /workspace/1.chip_sw_rv_core_ibex_lockstep_glitch/latest |
| Test location | /workspace/coverage/default/1.chip_sw_rv_core_ibex_nmi_irq.2799951982 |
| Short name | T502 |
| Test name | |
| Test status | |
| Simulation time | 5534019718 ps |
| CPU time | 849.96 seconds |
| Started | Jun 23 07:59:58 PM PDT 24 |
| Finished | Jun 23 08:14:09 PM PDT 24 |
| Peak memory | 607924 kb |
| Host | smart-9576151f-7155-4291-a73d-77b791140f14 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=10_000_000 +sw_build_device=sim_dv +sw_images=rv_core_ibex_nmi_irq_test:1:new_rules,test_rom:0 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27999 51982 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_rv_core_ibex_nmi_irq.2799951982 |
| Directory | /workspace/1.chip_sw_rv_core_ibex_nmi_irq/latest |
| Test location | /workspace/coverage/default/1.chip_sw_rv_core_ibex_rnd.3114405589 |
| Short name | T1142 |
| Test name | |
| Test status | |
| Simulation time | 5469705800 ps |
| CPU time | 1301.17 seconds |
| Started | Jun 23 07:57:54 PM PDT 24 |
| Finished | Jun 23 08:19:36 PM PDT 24 |
| Peak memory | 607948 kb |
| Host | smart-0f6acb6a-eed4-44ba-ba2a-092de045ab57 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=20_000_000 +rng_srate_value_max=32 +sw_build_device=sim_dv +sw_images=rv_core_ibex_rnd_test:1:new_rules,te st_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n tb_random_seed=3114405589 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_rv_core_ibex_rnd.3114405589 |
| Directory | /workspace/1.chip_sw_rv_core_ibex_rnd/latest |
| Test location | /workspace/coverage/default/1.chip_sw_rv_dm_access_after_escalation_reset.3437964759 |
| Short name | T693 |
| Test name | |
| Test status | |
| Simulation time | 5978582658 ps |
| CPU time | 456.04 seconds |
| Started | Jun 23 08:02:27 PM PDT 24 |
| Finished | Jun 23 08:10:04 PM PDT 24 |
| Peak memory | 615172 kb |
| Host | smart-ca29c771-28f7-49c8-99bc-88211c81734f |
| User | root |
| Command | /workspace/default/simv +use_jtag_dmi=1 +sw_build_device=sim_dv +sw_images=alert_handler_escalation_test:1:new_rules,test_rom:0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3437964759 -asse rt nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rv_dm_access_after_escalation_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_rv_dm_access_after_escalation_reset.3437964759 |
| Directory | /workspace/1.chip_sw_rv_dm_access_after_escalation_reset/latest |
| Test location | /workspace/coverage/default/1.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted.3261422602 |
| Short name | T359 |
| Test name | |
| Test status | |
| Simulation time | 5644968528 ps |
| CPU time | 631.22 seconds |
| Started | Jun 23 08:02:41 PM PDT 24 |
| Finished | Jun 23 08:13:12 PM PDT 24 |
| Peak memory | 615228 kb |
| Host | smart-0a0486b9-db9a-45e7-a957-a3b55b4bf78d |
| User | root |
| Command | /workspace/default/simv +use_jtag_dmi=1 +sw_build_device=sim_dv +sw_images=rv_dm_ndm_reset_req_when_cpu_halted_rma:1:new_rules,test_rom:0 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=326142 2602 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rv_dm_ndm_reset_when_cpu_halted_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted.3261422602 |
| Directory | /workspace/1.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted/latest |
| Test location | /workspace/coverage/default/1.chip_sw_rv_plic_smoketest.107954321 |
| Short name | T947 |
| Test name | |
| Test status | |
| Simulation time | 2365306310 ps |
| CPU time | 279.87 seconds |
| Started | Jun 23 08:07:27 PM PDT 24 |
| Finished | Jun 23 08:12:09 PM PDT 24 |
| Peak memory | 607816 kb |
| Host | smart-dd36a6a2-9adb-40fe-853b-fb50a4b31d5c |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=rv_plic_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=107954321 -assert nopostproc +UVM_TESTNAME=c hip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n ull -cm_name 1.chip_sw_rv_plic_smoketest.107954321 |
| Directory | /workspace/1.chip_sw_rv_plic_smoketest/latest |
| Test location | /workspace/coverage/default/1.chip_sw_rv_timer_irq.3597770252 |
| Short name | T1160 |
| Test name | |
| Test status | |
| Simulation time | 2411346600 ps |
| CPU time | 197.23 seconds |
| Started | Jun 23 07:56:55 PM PDT 24 |
| Finished | Jun 23 08:00:13 PM PDT 24 |
| Peak memory | 607584 kb |
| Host | smart-aa5c1805-7af3-443d-9527-a67dadd6dcfe |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=rv_timer_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3597770252 -assert nopostproc +UVM_TESTNAME =chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 1.chip_sw_rv_timer_irq.3597770252 |
| Directory | /workspace/1.chip_sw_rv_timer_irq/latest |
| Test location | /workspace/coverage/default/1.chip_sw_rv_timer_smoketest.3711031154 |
| Short name | T1034 |
| Test name | |
| Test status | |
| Simulation time | 2591648980 ps |
| CPU time | 206.44 seconds |
| Started | Jun 23 08:05:17 PM PDT 24 |
| Finished | Jun 23 08:08:43 PM PDT 24 |
| Peak memory | 606924 kb |
| Host | smart-1377407e-eb01-44ab-8604-c98b24d4c77d |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=rv_timer_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3711031154 -assert nopostproc +UVM_TESTNAME =chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 1.chip_sw_rv_timer_smoketest.3711031154 |
| Directory | /workspace/1.chip_sw_rv_timer_smoketest/latest |
| Test location | /workspace/coverage/default/1.chip_sw_sensor_ctrl_alert.340116475 |
| Short name | T134 |
| Test name | |
| Test status | |
| Simulation time | 4859277510 ps |
| CPU time | 551.56 seconds |
| Started | Jun 23 08:00:41 PM PDT 24 |
| Finished | Jun 23 08:09:53 PM PDT 24 |
| Peak memory | 607160 kb |
| Host | smart-da108637-db12-4d61-bb0f-81488053260b |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=40_000_000 +sw_build_device=sim_dv +sw_images=sensor_ctrl_alert_test:1:new_rules,test_rom:0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34011647 5 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace /coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_sensor_ctrl_alert.340116475 |
| Directory | /workspace/1.chip_sw_sensor_ctrl_alert/latest |
| Test location | /workspace/coverage/default/1.chip_sw_sensor_ctrl_status.1421443609 |
| Short name | T140 |
| Test name | |
| Test status | |
| Simulation time | 3327190097 ps |
| CPU time | 286.8 seconds |
| Started | Jun 23 08:03:47 PM PDT 24 |
| Finished | Jun 23 08:08:35 PM PDT 24 |
| Peak memory | 608036 kb |
| Host | smart-d49c7926-e588-4fd5-b168-0c884dfc5f34 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=40_000_000 +sw_build_device=sim_dv +sw_images=sensor_ctrl_status_test:1:new_rules,test_rom:0 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1421443 609 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sensor_ctrl_status_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_sensor_ctrl_status.1421443609 |
| Directory | /workspace/1.chip_sw_sensor_ctrl_status/latest |
| Test location | /workspace/coverage/default/1.chip_sw_sleep_pin_retention.1276105281 |
| Short name | T13 |
| Test name | |
| Test status | |
| Simulation time | 3557061972 ps |
| CPU time | 396.22 seconds |
| Started | Jun 23 07:56:06 PM PDT 24 |
| Finished | Jun 23 08:02:42 PM PDT 24 |
| Peak memory | 607068 kb |
| Host | smart-0f6e2d7c-3a2a-47c3-8460-a4c0dfdca1b7 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=sleep_pin_retention_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1276105281 -assert nopostproc +UVM_TE STNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sleep_pin_retention_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def ault.vdb -cm_log /dev/null -cm_name 1.chip_sw_sleep_pin_retention.1276105281 |
| Directory | /workspace/1.chip_sw_sleep_pin_retention/latest |
| Test location | /workspace/coverage/default/1.chip_sw_sleep_pwm_pulses.121453967 |
| Short name | T1270 |
| Test name | |
| Test status | |
| Simulation time | 9482524696 ps |
| CPU time | 1409.03 seconds |
| Started | Jun 23 07:56:33 PM PDT 24 |
| Finished | Jun 23 08:20:02 PM PDT 24 |
| Peak memory | 608208 kb |
| Host | smart-f5f36b72-f1a9-42a1-89df-3431d334bb9c |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=sleep_pwm_pulses_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=121453967 -assert nopostproc +UVM_TESTNA ME=chip_base_test +UVM_TEST_SEQ=chip_sw_pwm_pulses_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_ log /dev/null -cm_name 1.chip_sw_sleep_pwm_pulses.121453967 |
| Directory | /workspace/1.chip_sw_sleep_pwm_pulses/latest |
| Test location | /workspace/coverage/default/1.chip_sw_sleep_sram_ret_contents_no_scramble.913852376 |
| Short name | T1279 |
| Test name | |
| Test status | |
| Simulation time | 8894499712 ps |
| CPU time | 713.74 seconds |
| Started | Jun 23 08:00:33 PM PDT 24 |
| Finished | Jun 23 08:12:28 PM PDT 24 |
| Peak memory | 608552 kb |
| Host | smart-bb1cdcf6-3bd0-407e-a118-c4f1defcc369 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=20_000_000 +en_scb_tl_err_chk=0 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=sram _ctrl_sleep_sram_ret_contents_no_scramble_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=913852376 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SE Q=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_sle ep_sram_ret_contents_no_scramble.913852376 |
| Directory | /workspace/1.chip_sw_sleep_sram_ret_contents_no_scramble/latest |
| Test location | /workspace/coverage/default/1.chip_sw_sleep_sram_ret_contents_scramble.3062203211 |
| Short name | T1140 |
| Test name | |
| Test status | |
| Simulation time | 6885105146 ps |
| CPU time | 705.4 seconds |
| Started | Jun 23 08:01:32 PM PDT 24 |
| Finished | Jun 23 08:13:18 PM PDT 24 |
| Peak memory | 608612 kb |
| Host | smart-a5fd58e9-d3d3-484a-aad9-a5aa28c47128 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=20_000_000 +en_scb_tl_err_chk=0 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=sram _ctrl_sleep_sram_ret_contents_scramble_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3062203211 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ= chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_sleep _sram_ret_contents_scramble.3062203211 |
| Directory | /workspace/1.chip_sw_sleep_sram_ret_contents_scramble/latest |
| Test location | /workspace/coverage/default/1.chip_sw_spi_device_pass_through.654439096 |
| Short name | T191 |
| Test name | |
| Test status | |
| Simulation time | 6251980967 ps |
| CPU time | 798.79 seconds |
| Started | Jun 23 07:53:42 PM PDT 24 |
| Finished | Jun 23 08:07:02 PM PDT 24 |
| Peak memory | 623528 kb |
| Host | smart-bb2d3eee-9d06-4e96-bc7b-3148c311f5c5 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=spi_passthrough_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=654439096 -assert nopostproc +UVM_TESTNAM E=chip_base_test +UVM_TEST_SEQ=chip_sw_spi_passthrough_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_spi_device_pass_through.654439096 |
| Directory | /workspace/1.chip_sw_spi_device_pass_through/latest |
| Test location | /workspace/coverage/default/1.chip_sw_spi_device_pass_through_collision.189116497 |
| Short name | T189 |
| Test name | |
| Test status | |
| Simulation time | 3631711685 ps |
| CPU time | 494.72 seconds |
| Started | Jun 23 07:56:48 PM PDT 24 |
| Finished | Jun 23 08:05:03 PM PDT 24 |
| Peak memory | 623708 kb |
| Host | smart-747d7255-870c-49c3-8556-6ac43da3062f |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=spi_passthrough_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=189116497 -assert nopostproc +UVM_TESTNAM E=chip_base_test +UVM_TEST_SEQ=chip_sw_spi_passthrough_collision_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de fault.vdb -cm_log /dev/null -cm_name 1.chip_sw_spi_device_pass_through_collision.189116497 |
| Directory | /workspace/1.chip_sw_spi_device_pass_through_collision/latest |
| Test location | /workspace/coverage/default/1.chip_sw_spi_device_tpm.2879249743 |
| Short name | T51 |
| Test name | |
| Test status | |
| Simulation time | 3572956984 ps |
| CPU time | 414.57 seconds |
| Started | Jun 23 07:54:48 PM PDT 24 |
| Finished | Jun 23 08:01:43 PM PDT 24 |
| Peak memory | 616316 kb |
| Host | smart-c498abc8-6644-4cb0-9b93-af2d47836f46 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=spi_device_tpm_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2879249743 -assert nopostproc +UVM_T ESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_spi_device_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default .vdb -cm_log /dev/null -cm_name 1.chip_sw_spi_device_tpm.2879249743 |
| Directory | /workspace/1.chip_sw_spi_device_tpm/latest |
| Test location | /workspace/coverage/default/1.chip_sw_spi_host_tx_rx.234764600 |
| Short name | T47 |
| Test name | |
| Test status | |
| Simulation time | 3028211644 ps |
| CPU time | 255.09 seconds |
| Started | Jun 23 07:54:32 PM PDT 24 |
| Finished | Jun 23 07:58:48 PM PDT 24 |
| Peak memory | 607116 kb |
| Host | smart-c0a1c83e-9a07-4530-b30f-ee51f789a0b8 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=spi_host_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=234764600 -assert nopostproc +UVM_TESTNAME =chip_base_test +UVM_TEST_SEQ=chip_sw_spi_host_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -c m_log /dev/null -cm_name 1.chip_sw_spi_host_tx_rx.234764600 |
| Directory | /workspace/1.chip_sw_spi_host_tx_rx/latest |
| Test location | /workspace/coverage/default/1.chip_sw_sram_ctrl_execution_main.609877708 |
| Short name | T298 |
| Test name | |
| Test status | |
| Simulation time | 8323410076 ps |
| CPU time | 691.14 seconds |
| Started | Jun 23 07:59:56 PM PDT 24 |
| Finished | Jun 23 08:11:27 PM PDT 24 |
| Peak memory | 607352 kb |
| Host | smart-144548d8-e639-430d-b479-c391473f9498 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=sram_ctrl_execution_main_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=609877708 -assert nopostproc +UV M_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sram_ctrl_execution_main_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov erage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_sram_ctrl_execution_main.609877708 |
| Directory | /workspace/1.chip_sw_sram_ctrl_execution_main/latest |
| Test location | /workspace/coverage/default/1.chip_sw_sram_ctrl_scrambled_access.3380008943 |
| Short name | T170 |
| Test name | |
| Test status | |
| Simulation time | 5144802120 ps |
| CPU time | 574.37 seconds |
| Started | Jun 23 08:00:59 PM PDT 24 |
| Finished | Jun 23 08:10:34 PM PDT 24 |
| Peak memory | 608804 kb |
| Host | smart-28b1d75a-2084-444e-888e-6359f8eea40a |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=12_000_000 +en_scb_tl_err_chk=0 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=sram _ctrl_scrambled_access_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3380008943 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sram_ctr l_scrambled_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw _sram_ctrl_scrambled_access.3380008943 |
| Directory | /workspace/1.chip_sw_sram_ctrl_scrambled_access/latest |
| Test location | /workspace/coverage/default/1.chip_sw_sram_ctrl_scrambled_access_jitter_en.1789676523 |
| Short name | T1354 |
| Test name | |
| Test status | |
| Simulation time | 5061026327 ps |
| CPU time | 572.34 seconds |
| Started | Jun 23 08:00:14 PM PDT 24 |
| Finished | Jun 23 08:09:47 PM PDT 24 |
| Peak memory | 608088 kb |
| Host | smart-faf405b1-7183-44b2-87bd-b1281311d6b9 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=12_000_000 +bypass_alert_ready_to_end_check=1 +en_jitter=1 +en_scb_tl_err_chk=0 +sw_build_device=sim_dv +s w_images=sram_ctrl_scrambled_access_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1789676523 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chi p_sw_sram_ctrl_scrambled_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n ame 1.chip_sw_sram_ctrl_scrambled_access_jitter_en.1789676523 |
| Directory | /workspace/1.chip_sw_sram_ctrl_scrambled_access_jitter_en/latest |
| Test location | /workspace/coverage/default/1.chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq.3222313245 |
| Short name | T114 |
| Test name | |
| Test status | |
| Simulation time | 4943487170 ps |
| CPU time | 612.18 seconds |
| Started | Jun 23 08:03:54 PM PDT 24 |
| Finished | Jun 23 08:14:07 PM PDT 24 |
| Peak memory | 608128 kb |
| Host | smart-f202d856-4ce0-489b-8e00-8a21f34a4366 |
| User | root |
| Command | /workspace/default/simv +mem_sel=main +sw_test_timeout_ns=12_000_000 +bypass_alert_ready_to_end_check=1 +en_jitter=1 +en_scb_tl_err_chk=0 +cal_sys_clk _70mhz=1 +sw_build_device=sim_dv +sw_images=sram_ctrl_scrambled_access_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3222313245 -assert nopostproc +UVM_TESTNA ME=chip_base_test +UVM_TEST_SEQ=chip_sw_sram_ctrl_scrambled_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/ default.vdb -cm_log /dev/null -cm_name 1.chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq.3222313245 |
| Directory | /workspace/1.chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq/latest |
| Test location | /workspace/coverage/default/1.chip_sw_sram_ctrl_smoketest.1168227714 |
| Short name | T984 |
| Test name | |
| Test status | |
| Simulation time | 3225471988 ps |
| CPU time | 255.42 seconds |
| Started | Jun 23 08:05:49 PM PDT 24 |
| Finished | Jun 23 08:10:04 PM PDT 24 |
| Peak memory | 606844 kb |
| Host | smart-e6615de3-de95-4c4c-bb89-110e2d57cd26 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=sram_ctrl_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1168227714 -assert nopostproc +UVM_TESTNAM E=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 1.chip_sw_sram_ctrl_smoketest.1168227714 |
| Directory | /workspace/1.chip_sw_sram_ctrl_smoketest/latest |
| Test location | /workspace/coverage/default/1.chip_sw_sysrst_ctrl_ec_rst_l.3505550336 |
| Short name | T215 |
| Test name | |
| Test status | |
| Simulation time | 20335276313 ps |
| CPU time | 3273.79 seconds |
| Started | Jun 23 07:57:38 PM PDT 24 |
| Finished | Jun 23 08:52:13 PM PDT 24 |
| Peak memory | 608348 kb |
| Host | smart-a659d635-12c1-4408-840f-1fc29a6cd9e6 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=sysrst_ctrl_ec_rst_l_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3505550336 -assert nopostproc +UVM_T ESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_ec_rst_l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/d efault.vdb -cm_log /dev/null -cm_name 1.chip_sw_sysrst_ctrl_ec_rst_l.3505550336 |
| Directory | /workspace/1.chip_sw_sysrst_ctrl_ec_rst_l/latest |
| Test location | /workspace/coverage/default/1.chip_sw_sysrst_ctrl_in_irq.401704278 |
| Short name | T204 |
| Test name | |
| Test status | |
| Simulation time | 4912010600 ps |
| CPU time | 510.1 seconds |
| Started | Jun 23 07:56:35 PM PDT 24 |
| Finished | Jun 23 08:05:07 PM PDT 24 |
| Peak memory | 611768 kb |
| Host | smart-1cb4981f-991d-48e3-9d5c-97cfcc5a35f4 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=sysrst_ctrl_in_irq_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=401704278 -assert nopostproc +UVM_TEST NAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_in_irq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul t.vdb -cm_log /dev/null -cm_name 1.chip_sw_sysrst_ctrl_in_irq.401704278 |
| Directory | /workspace/1.chip_sw_sysrst_ctrl_in_irq/latest |
| Test location | /workspace/coverage/default/1.chip_sw_sysrst_ctrl_inputs.841426542 |
| Short name | T1177 |
| Test name | |
| Test status | |
| Simulation time | 2776528977 ps |
| CPU time | 315.68 seconds |
| Started | Jun 23 07:57:50 PM PDT 24 |
| Finished | Jun 23 08:03:06 PM PDT 24 |
| Peak memory | 611252 kb |
| Host | smart-9da2701b-5a8f-45e2-bf47-a2e0562a55aa |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=sysrst_ctrl_inputs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=841426542 -assert nopostproc +UVM_TEST NAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_inputs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul t.vdb -cm_log /dev/null -cm_name 1.chip_sw_sysrst_ctrl_inputs.841426542 |
| Directory | /workspace/1.chip_sw_sysrst_ctrl_inputs/latest |
| Test location | /workspace/coverage/default/1.chip_sw_sysrst_ctrl_outputs.961350072 |
| Short name | T1207 |
| Test name | |
| Test status | |
| Simulation time | 3513513460 ps |
| CPU time | 455.7 seconds |
| Started | Jun 23 07:58:37 PM PDT 24 |
| Finished | Jun 23 08:06:14 PM PDT 24 |
| Peak memory | 606836 kb |
| Host | smart-c79be157-c6a6-4f49-ade7-7f33c4378575 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=sysrst_ctrl_outputs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=961350072 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_outputs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defa ult.vdb -cm_log /dev/null -cm_name 1.chip_sw_sysrst_ctrl_outputs.961350072 |
| Directory | /workspace/1.chip_sw_sysrst_ctrl_outputs/latest |
| Test location | /workspace/coverage/default/1.chip_sw_sysrst_ctrl_ulp_z3_wakeup.2158420050 |
| Short name | T50 |
| Test name | |
| Test status | |
| Simulation time | 7041203440 ps |
| CPU time | 436.64 seconds |
| Started | Jun 23 07:57:44 PM PDT 24 |
| Finished | Jun 23 08:05:01 PM PDT 24 |
| Peak memory | 607260 kb |
| Host | smart-6794219b-0734-4443-a2bd-2eba749e70b3 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=sysrst_ctrl_ulp_z3_wakeup_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2158420050 -assert nopostproc + UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_ulp_z3_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/ coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_sysrst_ctrl_ulp_z3_wakeup.2158420050 |
| Directory | /workspace/1.chip_sw_sysrst_ctrl_ulp_z3_wakeup/latest |
| Test location | /workspace/coverage/default/1.chip_sw_uart_rand_baudrate.2190482567 |
| Short name | T916 |
| Test name | |
| Test status | |
| Simulation time | 4403359316 ps |
| CPU time | 839.19 seconds |
| Started | Jun 23 07:56:09 PM PDT 24 |
| Finished | Jun 23 08:10:09 PM PDT 24 |
| Peak memory | 619164 kb |
| Host | smart-a6d3a0c6-1226-4905-87dd-15cfdcb682ce |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=2190482567 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_uart_rand_baudrate.2190482567 |
| Directory | /workspace/1.chip_sw_uart_rand_baudrate/latest |
| Test location | /workspace/coverage/default/1.chip_sw_uart_smoketest.1690249105 |
| Short name | T1190 |
| Test name | |
| Test status | |
| Simulation time | 3128803850 ps |
| CPU time | 347.06 seconds |
| Started | Jun 23 08:06:52 PM PDT 24 |
| Finished | Jun 23 08:12:39 PM PDT 24 |
| Peak memory | 611108 kb |
| Host | smart-6161a935-6686-40b2-9e43-de45d05cc2c6 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=uart_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1690249105 -assert nopostproc +UVM_TESTNAME=chi p_base_test +UVM_TEST_SEQ=chip_sw_uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 1.chip_sw_uart_smoketest.1690249105 |
| Directory | /workspace/1.chip_sw_uart_smoketest/latest |
| Test location | /workspace/coverage/default/1.chip_sw_uart_tx_rx.2816532122 |
| Short name | T1344 |
| Test name | |
| Test status | |
| Simulation time | 4424730264 ps |
| CPU time | 692.35 seconds |
| Started | Jun 23 07:55:21 PM PDT 24 |
| Finished | Jun 23 08:06:55 PM PDT 24 |
| Peak memory | 615052 kb |
| Host | smart-7eb3c26e-0242-42db-9189-2cc72416317f |
| User | root |
| Command | /workspace/default/simv +uart_idx=0 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2816532122 -a ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_uart_tx_rx.2816532122 |
| Directory | /workspace/1.chip_sw_uart_tx_rx/latest |
| Test location | /workspace/coverage/default/1.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.276864809 |
| Short name | T1182 |
| Test name | |
| Test status | |
| Simulation time | 8375877936 ps |
| CPU time | 1042.75 seconds |
| Started | Jun 23 07:54:18 PM PDT 24 |
| Finished | Jun 23 08:11:41 PM PDT 24 |
| Peak memory | 615020 kb |
| Host | smart-0c466902-fcfa-42bb-9c7e-ca2257f015b2 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +chip_clock_source=ChipClockSourceExternal48Mhz +sw_build_device=sim_dv +s w_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=276864809 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_ba udrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_uart_tx_rx_ alt_clk_freq_low_speed.276864809 |
| Directory | /workspace/1.chip_sw_uart_tx_rx_alt_clk_freq_low_speed/latest |
| Test location | /workspace/coverage/default/1.chip_sw_uart_tx_rx_bootstrap.2355719681 |
| Short name | T197 |
| Test name | |
| Test status | |
| Simulation time | 78885691572 ps |
| CPU time | 13504.1 seconds |
| Started | Jun 23 07:56:44 PM PDT 24 |
| Finished | Jun 23 11:41:50 PM PDT 24 |
| Peak memory | 632640 kb |
| Host | smart-4f34befa-7543-491f-b264-d2b1bf92805a |
| User | root |
| Command | /workspace/default/simv +use_spi_load_bootstrap=1 +calibrate_usb_clk=1 +test_timeout_ns=160_000_000 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test :1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=2355719681 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_uart_tx_rx_bootstrap.2355719681 |
| Directory | /workspace/1.chip_sw_uart_tx_rx_bootstrap/latest |
| Test location | /workspace/coverage/default/1.chip_sw_uart_tx_rx_idx1.1446154479 |
| Short name | T210 |
| Test name | |
| Test status | |
| Simulation time | 4528359640 ps |
| CPU time | 752.1 seconds |
| Started | Jun 23 07:54:08 PM PDT 24 |
| Finished | Jun 23 08:06:40 PM PDT 24 |
| Peak memory | 614052 kb |
| Host | smart-a8ee47cc-dae0-476b-be20-435d572fa91a |
| User | root |
| Command | /workspace/default/simv +uart_idx=1 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1446154479 -a ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_uart_tx_rx_idx1.1446154479 |
| Directory | /workspace/1.chip_sw_uart_tx_rx_idx1/latest |
| Test location | /workspace/coverage/default/1.chip_sw_uart_tx_rx_idx2.2514421495 |
| Short name | T319 |
| Test name | |
| Test status | |
| Simulation time | 4733574584 ps |
| CPU time | 809.93 seconds |
| Started | Jun 23 07:54:06 PM PDT 24 |
| Finished | Jun 23 08:07:36 PM PDT 24 |
| Peak memory | 613936 kb |
| Host | smart-8990a808-54ee-4667-990e-212cb4320413 |
| User | root |
| Command | /workspace/default/simv +uart_idx=2 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2514421495 -a ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_uart_tx_rx_idx2.2514421495 |
| Directory | /workspace/1.chip_sw_uart_tx_rx_idx2/latest |
| Test location | /workspace/coverage/default/1.chip_sw_uart_tx_rx_idx3.3105774394 |
| Short name | T1266 |
| Test name | |
| Test status | |
| Simulation time | 4499527124 ps |
| CPU time | 712.44 seconds |
| Started | Jun 23 07:56:54 PM PDT 24 |
| Finished | Jun 23 08:08:47 PM PDT 24 |
| Peak memory | 615108 kb |
| Host | smart-2fdfb115-0444-4659-b9b8-54a0e3935f84 |
| User | root |
| Command | /workspace/default/simv +uart_idx=3 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3105774394 -a ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_uart_tx_rx_idx3.3105774394 |
| Directory | /workspace/1.chip_sw_uart_tx_rx_idx3/latest |
| Test location | /workspace/coverage/default/1.chip_tap_straps_dev.319602096 |
| Short name | T1310 |
| Test name | |
| Test status | |
| Simulation time | 3660002726 ps |
| CPU time | 349.09 seconds |
| Started | Jun 23 08:02:28 PM PDT 24 |
| Finished | Jun 23 08:08:17 PM PDT 24 |
| Peak memory | 617948 kb |
| Host | smart-41338e64-f6f8-4712-bc3a-4ba5851a3790 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStDev +create_jtag_riscv_map=1 +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:test_in_rom: new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=319602096 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_tap_straps_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_tap_straps_dev.319602096 |
| Directory | /workspace/1.chip_tap_straps_dev/latest |
| Test location | /workspace/coverage/default/1.chip_tap_straps_prod.1990057135 |
| Short name | T1066 |
| Test name | |
| Test status | |
| Simulation time | 2186811763 ps |
| CPU time | 160.62 seconds |
| Started | Jun 23 08:02:29 PM PDT 24 |
| Finished | Jun 23 08:05:10 PM PDT 24 |
| Peak memory | 617384 kb |
| Host | smart-6fc20534-e839-474c-9fc7-f8b2f14c825e |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStProd +create_jtag_riscv_map=1 +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:test_in_rom :new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1990057135 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_tap_straps_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_tap_straps_prod.1990057135 |
| Directory | /workspace/1.chip_tap_straps_prod/latest |
| Test location | /workspace/coverage/default/1.chip_tap_straps_rma.2555201812 |
| Short name | T68 |
| Test name | |
| Test status | |
| Simulation time | 9010383150 ps |
| CPU time | 1022.25 seconds |
| Started | Jun 23 08:02:16 PM PDT 24 |
| Finished | Jun 23 08:19:19 PM PDT 24 |
| Peak memory | 620172 kb |
| Host | smart-e059478e-677e-4c6b-8195-4bfd319bbadb |
| User | root |
| Command | /workspace/default/simv +create_jtag_riscv_map=1 +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:test_in_rom:new_rules +cdc_instrumentation _enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2555201812 -as sert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_tap_straps_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/c overage/default.vdb -cm_log /dev/null -cm_name 1.chip_tap_straps_rma.2555201812 |
| Directory | /workspace/1.chip_tap_straps_rma/latest |
| Test location | /workspace/coverage/default/1.chip_tap_straps_testunlock0.115579398 |
| Short name | T1166 |
| Test name | |
| Test status | |
| Simulation time | 4009128540 ps |
| CPU time | 324.76 seconds |
| Started | Jun 23 08:03:18 PM PDT 24 |
| Finished | Jun 23 08:08:43 PM PDT 24 |
| Peak memory | 622056 kb |
| Host | smart-e04529d6-406a-49f9-987f-3210ec643968 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStTestUnlocked0 +create_jtag_riscv_map=1 +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:te st_in_rom:new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=115579398 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_tap_straps_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_tap_straps_testunlock0.115579398 |
| Directory | /workspace/1.chip_tap_straps_testunlock0/latest |
| Test location | /workspace/coverage/default/1.rom_e2e_asm_init_dev.3538699351 |
| Short name | T1231 |
| Test name | |
| Test status | |
| Simulation time | 16115561706 ps |
| CPU time | 3582.6 seconds |
| Started | Jun 23 08:10:36 PM PDT 24 |
| Finished | Jun 23 09:10:19 PM PDT 24 |
| Peak memory | 606944 kb |
| Host | smart-8c8cb75b-3cc8-49c2-babc-c4a5ecf18e07 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeCustom +sw_test_timeout_ns=20000000 +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_prod _key_0:1:ot_flash_binary,otp_img_e2e_bootstrap_entry_dev:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3538699351 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_S EQ=chip_sw_rom_e2e_asm_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_e2e_asm_init_dev.3538699351 |
| Directory | /workspace/1.rom_e2e_asm_init_dev/latest |
| Test location | /workspace/coverage/default/1.rom_e2e_asm_init_prod.3487197702 |
| Short name | T1060 |
| Test name | |
| Test status | |
| Simulation time | 16312102156 ps |
| CPU time | 4242.6 seconds |
| Started | Jun 23 08:16:13 PM PDT 24 |
| Finished | Jun 23 09:26:57 PM PDT 24 |
| Peak memory | 608272 kb |
| Host | smart-a320416f-9ef0-41c0-a557-3b01fdd18e69 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeCustom +sw_test_timeout_ns=20000000 +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_prod _key_0:1:ot_flash_binary,otp_img_e2e_bootstrap_entry_prod:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3487197702 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_ SEQ=chip_sw_rom_e2e_asm_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_e2e_asm_init_prod.3487197702 |
| Directory | /workspace/1.rom_e2e_asm_init_prod/latest |
| Test location | /workspace/coverage/default/1.rom_e2e_asm_init_prod_end.3351210996 |
| Short name | T1314 |
| Test name | |
| Test status | |
| Simulation time | 15321651542 ps |
| CPU time | 3929.75 seconds |
| Started | Jun 23 08:16:07 PM PDT 24 |
| Finished | Jun 23 09:21:38 PM PDT 24 |
| Peak memory | 608276 kb |
| Host | smart-47994e16-6059-4f28-ab14-d69bbac2024e |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeCustom +sw_test_timeout_ns=20000000 +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_prod _key_0:1:ot_flash_binary,otp_img_e2e_bootstrap_entry_prod_end:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3351210996 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_T EST_SEQ=chip_sw_rom_e2e_asm_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 1.rom_e2e_asm_init_prod_end.3351210996 |
| Directory | /workspace/1.rom_e2e_asm_init_prod_end/latest |
| Test location | /workspace/coverage/default/1.rom_e2e_asm_init_rma.1166545041 |
| Short name | T1017 |
| Test name | |
| Test status | |
| Simulation time | 15730380670 ps |
| CPU time | 3753.19 seconds |
| Started | Jun 23 08:10:12 PM PDT 24 |
| Finished | Jun 23 09:12:47 PM PDT 24 |
| Peak memory | 606740 kb |
| Host | smart-fe805deb-c81d-461e-ae8e-06bf4986d55c |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeCustom +sw_test_timeout_ns=20000000 +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_prod _key_0:1:ot_flash_binary,otp_img_e2e_bootstrap_entry_rma:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1166545041 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_S EQ=chip_sw_rom_e2e_asm_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_e2e_asm_init_rma.1166545041 |
| Directory | /workspace/1.rom_e2e_asm_init_rma/latest |
| Test location | /workspace/coverage/default/1.rom_e2e_asm_init_test_unlocked0.4208199379 |
| Short name | T56 |
| Test name | |
| Test status | |
| Simulation time | 11990377064 ps |
| CPU time | 3611.81 seconds |
| Started | Jun 23 08:16:14 PM PDT 24 |
| Finished | Jun 23 09:16:27 PM PDT 24 |
| Peak memory | 608344 kb |
| Host | smart-7648cc6f-c414-45c2-ae20-93b0eec60ea7 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeCustom +sw_test_timeout_ns=410_000_000 +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_p rod_key_0:1:ot_flash_binary,otp_img_e2e_bootstrap_entry_test_unlocked0:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY =UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4208199379 -assert nopostproc +UVM_TESTNAME=chip_base_te st +UVM_TEST_SEQ=chip_sw_rom_e2e_asm_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/ null -cm_name 1.rom_e2e_asm_init_test_unlocked0.4208199379 |
| Directory | /workspace/1.rom_e2e_asm_init_test_unlocked0/latest |
| Test location | /workspace/coverage/default/1.rom_e2e_keymgr_init_rom_ext_invalid_meas.3607757539 |
| Short name | T1023 |
| Test name | |
| Test status | |
| Simulation time | 15732084168 ps |
| CPU time | 3380.94 seconds |
| Started | Jun 23 08:09:45 PM PDT 24 |
| Finished | Jun 23 09:06:07 PM PDT 24 |
| Peak memory | 608040 kb |
| Host | smart-330434d8-b0ef-46af-bca6-b91b11e64e85 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=40_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=rom_e2e_keymgr_init_otp_invalid _meas:1:new_rules,otp_img_keymgr_otp_invalid_meas:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3607757539 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip _sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_e2e_keymgr_in it_rom_ext_invalid_meas.3607757539 |
| Directory | /workspace/1.rom_e2e_keymgr_init_rom_ext_invalid_meas/latest |
| Test location | /workspace/coverage/default/1.rom_e2e_keymgr_init_rom_ext_meas.1954933142 |
| Short name | T1209 |
| Test name | |
| Test status | |
| Simulation time | 15322136592 ps |
| CPU time | 3601.87 seconds |
| Started | Jun 23 08:09:49 PM PDT 24 |
| Finished | Jun 23 09:09:52 PM PDT 24 |
| Peak memory | 608168 kb |
| Host | smart-08deb815-7a23-46bc-80a8-a07bcb0b9fed |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=40_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=rom_e2e_keymgr_init_otp_meas:1: new_rules,otp_img_keymgr_otp_meas:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1954933142 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_e2e_keymgr_init_rom_ext_meas.1954933142 |
| Directory | /workspace/1.rom_e2e_keymgr_init_rom_ext_meas/latest |
| Test location | /workspace/coverage/default/1.rom_e2e_keymgr_init_rom_ext_no_meas.2303630566 |
| Short name | T956 |
| Test name | |
| Test status | |
| Simulation time | 15547354586 ps |
| CPU time | 4323.06 seconds |
| Started | Jun 23 08:08:39 PM PDT 24 |
| Finished | Jun 23 09:20:42 PM PDT 24 |
| Peak memory | 608092 kb |
| Host | smart-c2d84d87-e8b0-412f-94aa-81834fdbc6f4 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=40_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=rom_e2e_keymgr_init_otp_no_meas :1:new_rules,otp_img_keymgr_otp_no_meas:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2303630566 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_e2e_keymgr_init_rom_ext _no_meas.2303630566 |
| Directory | /workspace/1.rom_e2e_keymgr_init_rom_ext_no_meas/latest |
| Test location | /workspace/coverage/default/1.rom_e2e_smoke.3800835666 |
| Short name | T1065 |
| Test name | |
| Test status | |
| Simulation time | 15268310076 ps |
| CPU time | 4059 seconds |
| Started | Jun 23 08:15:57 PM PDT 24 |
| Finished | Jun 23 09:23:37 PM PDT 24 |
| Peak memory | 608076 kb |
| Host | smart-47bdc3f0-ff69-4685-87e8-46a81f82e92d |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=40000000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=rom_e2e_smoke:1:new_rules,otp_img _secret2_locked_rma:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_to p/hw/dv/tools/sim.tcl +ntb_random_seed=3800835666 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_e2e_smoke.3800835666 |
| Directory | /workspace/1.rom_e2e_smoke/latest |
| Test location | /workspace/coverage/default/1.rom_e2e_static_critical.1296616080 |
| Short name | T1204 |
| Test name | |
| Test status | |
| Simulation time | 16570077400 ps |
| CPU time | 3740.48 seconds |
| Started | Jun 23 08:08:46 PM PDT 24 |
| Finished | Jun 23 09:11:09 PM PDT 24 |
| Peak memory | 608100 kb |
| Host | smart-4475223d-05b9-472e-a0a6-ee7202b287c4 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=40000000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=rom_e2e_static_critical:1:new_rul es,otp_img_secret2_locked_rma:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1296616080 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_e2e_static_critical.1296616080 |
| Directory | /workspace/1.rom_e2e_static_critical/latest |
| Test location | /workspace/coverage/default/1.rom_keymgr_functest.2676868115 |
| Short name | T975 |
| Test name | |
| Test status | |
| Simulation time | 5313343560 ps |
| CPU time | 502.97 seconds |
| Started | Jun 23 08:04:36 PM PDT 24 |
| Finished | Jun 23 08:12:59 PM PDT 24 |
| Peak memory | 608000 kb |
| Host | smart-462ef0ff-c37c-428e-8352-845e43ae5915 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=10_000_000 +sw_build_device=sim_dv +sw_images=keymgr_functest:1:new_rules,test_rom:0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2676868115 -ass ert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 1.rom_keymgr_functest.2676868115 |
| Directory | /workspace/1.rom_keymgr_functest/latest |
| Test location | /workspace/coverage/default/1.rom_volatile_raw_unlock.869210453 |
| Short name | T1046 |
| Test name | |
| Test status | |
| Simulation time | 2550939127 ps |
| CPU time | 117.45 seconds |
| Started | Jun 23 08:05:23 PM PDT 24 |
| Finished | Jun 23 08:07:22 PM PDT 24 |
| Peak memory | 613552 kb |
| Host | smart-fae0de5b-3abd-4a11-85bc-8e7c75ab0fcb |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=200_000_000 +use_otp_image=OtpTypeLcStRaw +chip_clock_source=ChipClockSourceExternal48Mhz +rom_prod_mode=1 +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_test_key_0:1:ot_flash_binary,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=869210453 -assert nopostproc +UVM_T ESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_volatile_raw_unlock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage /default.vdb -cm_log /dev/null -cm_name 1.rom_volatile_raw_unlock.869210453 |
| Directory | /workspace/1.rom_volatile_raw_unlock/latest |
| Test location | /workspace/coverage/default/10.chip_sw_lc_ctrl_transition.3922866742 |
| Short name | T982 |
| Test name | |
| Test status | |
| Simulation time | 11413506212 ps |
| CPU time | 892.62 seconds |
| Started | Jun 23 08:19:29 PM PDT 24 |
| Finished | Jun 23 08:34:22 PM PDT 24 |
| Peak memory | 620100 kb |
| Host | smart-23d14749-49ab-4e1a-8f7c-3a786fd65b82 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=lc_ctrl_transition_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3922866742 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_transition_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau lt.vdb -cm_log /dev/null -cm_name 10.chip_sw_lc_ctrl_transition.3922866742 |
| Directory | /workspace/10.chip_sw_lc_ctrl_transition/latest |
| Test location | /workspace/coverage/default/10.chip_sw_uart_rand_baudrate.1107440293 |
| Short name | T1059 |
| Test name | |
| Test status | |
| Simulation time | 3110459160 ps |
| CPU time | 504.61 seconds |
| Started | Jun 23 08:19:04 PM PDT 24 |
| Finished | Jun 23 08:27:29 PM PDT 24 |
| Peak memory | 619476 kb |
| Host | smart-3ffe38ca-4af0-4e14-9377-ed7021a5e267 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=1107440293 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.chip_sw_uart_rand_baudrate.1107440293 |
| Directory | /workspace/10.chip_sw_uart_rand_baudrate/latest |
| Test location | /workspace/coverage/default/11.chip_sw_all_escalation_resets.2365133938 |
| Short name | T217 |
| Test name | |
| Test status | |
| Simulation time | 5660672440 ps |
| CPU time | 736.72 seconds |
| Started | Jun 23 08:19:37 PM PDT 24 |
| Finished | Jun 23 08:31:54 PM PDT 24 |
| Peak memory | 648440 kb |
| Host | smart-f3f82aa5-1477-4755-ad49-7181729c3265 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 2365133938 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.chip_sw_all_escalation_resets.2365133938 |
| Directory | /workspace/11.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/11.chip_sw_lc_ctrl_transition.1928539292 |
| Short name | T1216 |
| Test name | |
| Test status | |
| Simulation time | 6052894989 ps |
| CPU time | 841.7 seconds |
| Started | Jun 23 08:18:56 PM PDT 24 |
| Finished | Jun 23 08:32:58 PM PDT 24 |
| Peak memory | 620076 kb |
| Host | smart-9c5c613b-773d-447b-b0a4-f4ecd78261c6 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=lc_ctrl_transition_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1928539292 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_transition_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau lt.vdb -cm_log /dev/null -cm_name 11.chip_sw_lc_ctrl_transition.1928539292 |
| Directory | /workspace/11.chip_sw_lc_ctrl_transition/latest |
| Test location | /workspace/coverage/default/11.chip_sw_uart_rand_baudrate.664103768 |
| Short name | T1181 |
| Test name | |
| Test status | |
| Simulation time | 8337209992 ps |
| CPU time | 1314.64 seconds |
| Started | Jun 23 08:19:54 PM PDT 24 |
| Finished | Jun 23 08:41:50 PM PDT 24 |
| Peak memory | 620800 kb |
| Host | smart-966a5c90-fffb-4de2-af5f-67a9b5f3917d |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=664103768 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.chip_sw_uart_rand_baudrate.664103768 |
| Directory | /workspace/11.chip_sw_uart_rand_baudrate/latest |
| Test location | /workspace/coverage/default/12.chip_sw_lc_ctrl_transition.909889531 |
| Short name | T1091 |
| Test name | |
| Test status | |
| Simulation time | 9870115977 ps |
| CPU time | 1042.91 seconds |
| Started | Jun 23 08:19:58 PM PDT 24 |
| Finished | Jun 23 08:37:22 PM PDT 24 |
| Peak memory | 620852 kb |
| Host | smart-4b13eeb5-ada2-44e1-b794-d634a44ef1b0 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=lc_ctrl_transition_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=909889531 -assert nopostproc +UVM_TEST NAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_transition_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul t.vdb -cm_log /dev/null -cm_name 12.chip_sw_lc_ctrl_transition.909889531 |
| Directory | /workspace/12.chip_sw_lc_ctrl_transition/latest |
| Test location | /workspace/coverage/default/12.chip_sw_uart_rand_baudrate.2474760277 |
| Short name | T1058 |
| Test name | |
| Test status | |
| Simulation time | 7501857432 ps |
| CPU time | 1697.73 seconds |
| Started | Jun 23 08:19:04 PM PDT 24 |
| Finished | Jun 23 08:47:23 PM PDT 24 |
| Peak memory | 619480 kb |
| Host | smart-d75280fb-0bb9-4ebf-870c-ea3063f2cd95 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=2474760277 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.chip_sw_uart_rand_baudrate.2474760277 |
| Directory | /workspace/12.chip_sw_uart_rand_baudrate/latest |
| Test location | /workspace/coverage/default/13.chip_sw_lc_ctrl_transition.865759415 |
| Short name | T989 |
| Test name | |
| Test status | |
| Simulation time | 12763398704 ps |
| CPU time | 925.28 seconds |
| Started | Jun 23 08:21:43 PM PDT 24 |
| Finished | Jun 23 08:37:10 PM PDT 24 |
| Peak memory | 619984 kb |
| Host | smart-fa039bc5-35c9-4bb3-add5-437f02a925f3 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=lc_ctrl_transition_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=865759415 -assert nopostproc +UVM_TEST NAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_transition_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul t.vdb -cm_log /dev/null -cm_name 13.chip_sw_lc_ctrl_transition.865759415 |
| Directory | /workspace/13.chip_sw_lc_ctrl_transition/latest |
| Test location | /workspace/coverage/default/13.chip_sw_uart_rand_baudrate.1470423296 |
| Short name | T342 |
| Test name | |
| Test status | |
| Simulation time | 8228603750 ps |
| CPU time | 1500.66 seconds |
| Started | Jun 23 08:18:59 PM PDT 24 |
| Finished | Jun 23 08:44:00 PM PDT 24 |
| Peak memory | 619480 kb |
| Host | smart-2e378460-0d9d-4e0d-afb3-36673622ed04 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=1470423296 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.chip_sw_uart_rand_baudrate.1470423296 |
| Directory | /workspace/13.chip_sw_uart_rand_baudrate/latest |
| Test location | /workspace/coverage/default/14.chip_sw_lc_ctrl_transition.3891631694 |
| Short name | T1253 |
| Test name | |
| Test status | |
| Simulation time | 10466062180 ps |
| CPU time | 748.61 seconds |
| Started | Jun 23 08:18:54 PM PDT 24 |
| Finished | Jun 23 08:31:23 PM PDT 24 |
| Peak memory | 622208 kb |
| Host | smart-22938e2b-a2e3-4460-ae52-10316dfbfc31 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=lc_ctrl_transition_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3891631694 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_transition_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau lt.vdb -cm_log /dev/null -cm_name 14.chip_sw_lc_ctrl_transition.3891631694 |
| Directory | /workspace/14.chip_sw_lc_ctrl_transition/latest |
| Test location | /workspace/coverage/default/15.chip_sw_uart_rand_baudrate.3556047978 |
| Short name | T1037 |
| Test name | |
| Test status | |
| Simulation time | 13456725736 ps |
| CPU time | 2755.29 seconds |
| Started | Jun 23 08:20:53 PM PDT 24 |
| Finished | Jun 23 09:06:49 PM PDT 24 |
| Peak memory | 619764 kb |
| Host | smart-584d08f1-8351-46de-b863-430ce5717913 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=3556047978 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.chip_sw_uart_rand_baudrate.3556047978 |
| Directory | /workspace/15.chip_sw_uart_rand_baudrate/latest |
| Test location | /workspace/coverage/default/16.chip_sw_uart_rand_baudrate.1167977819 |
| Short name | T1223 |
| Test name | |
| Test status | |
| Simulation time | 8281827908 ps |
| CPU time | 1484.4 seconds |
| Started | Jun 23 08:20:54 PM PDT 24 |
| Finished | Jun 23 08:45:39 PM PDT 24 |
| Peak memory | 619568 kb |
| Host | smart-f479a221-4a5a-4e22-b923-b8b10d61acd3 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=1167977819 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.chip_sw_uart_rand_baudrate.1167977819 |
| Directory | /workspace/16.chip_sw_uart_rand_baudrate/latest |
| Test location | /workspace/coverage/default/17.chip_sw_uart_rand_baudrate.1644867747 |
| Short name | T1228 |
| Test name | |
| Test status | |
| Simulation time | 3802086452 ps |
| CPU time | 552.85 seconds |
| Started | Jun 23 08:19:47 PM PDT 24 |
| Finished | Jun 23 08:29:01 PM PDT 24 |
| Peak memory | 619120 kb |
| Host | smart-7851c1c5-fc51-49b4-b030-72cce1ff8f44 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=1644867747 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.chip_sw_uart_rand_baudrate.1644867747 |
| Directory | /workspace/17.chip_sw_uart_rand_baudrate/latest |
| Test location | /workspace/coverage/default/18.chip_sw_all_escalation_resets.2270199618 |
| Short name | T811 |
| Test name | |
| Test status | |
| Simulation time | 5701131870 ps |
| CPU time | 720.32 seconds |
| Started | Jun 23 08:20:23 PM PDT 24 |
| Finished | Jun 23 08:32:24 PM PDT 24 |
| Peak memory | 647680 kb |
| Host | smart-875d2022-1ad3-4c7b-a394-221404a2399f |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 2270199618 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.chip_sw_all_escalation_resets.2270199618 |
| Directory | /workspace/18.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/18.chip_sw_uart_rand_baudrate.4034181342 |
| Short name | T1095 |
| Test name | |
| Test status | |
| Simulation time | 8809613756 ps |
| CPU time | 1225.21 seconds |
| Started | Jun 23 08:19:48 PM PDT 24 |
| Finished | Jun 23 08:40:14 PM PDT 24 |
| Peak memory | 619780 kb |
| Host | smart-a50765d8-bea6-494f-882e-7e414a5f9267 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=4034181342 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.chip_sw_uart_rand_baudrate.4034181342 |
| Directory | /workspace/18.chip_sw_uart_rand_baudrate/latest |
| Test location | /workspace/coverage/default/19.chip_sw_alert_handler_lpg_sleep_mode_alerts.2993453734 |
| Short name | T823 |
| Test name | |
| Test status | |
| Simulation time | 3695238280 ps |
| CPU time | 443.18 seconds |
| Started | Jun 23 08:23:54 PM PDT 24 |
| Finished | Jun 23 08:31:18 PM PDT 24 |
| Peak memory | 642372 kb |
| Host | smart-fbf38d42-9afe-4a33-81a1-aba9e97fac94 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2993453734 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.chip_ sw_alert_handler_lpg_sleep_mode_alerts.2993453734 |
| Directory | /workspace/19.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/19.chip_sw_uart_rand_baudrate.3528911423 |
| Short name | T1251 |
| Test name | |
| Test status | |
| Simulation time | 13115529650 ps |
| CPU time | 2136.8 seconds |
| Started | Jun 23 08:20:35 PM PDT 24 |
| Finished | Jun 23 08:56:13 PM PDT 24 |
| Peak memory | 619480 kb |
| Host | smart-f01c64f0-0cb9-4114-8217-5a89d9522c1e |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=3528911423 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.chip_sw_uart_rand_baudrate.3528911423 |
| Directory | /workspace/19.chip_sw_uart_rand_baudrate/latest |
| Test location | /workspace/coverage/default/2.chip_jtag_csr_rw.1782161070 |
| Short name | T76 |
| Test name | |
| Test status | |
| Simulation time | 3881436150 ps |
| CPU time | 413.85 seconds |
| Started | Jun 23 08:06:06 PM PDT 24 |
| Finished | Jun 23 08:13:00 PM PDT 24 |
| Peak memory | 607688 kb |
| Host | smart-e2a0f613-6a40-4c16-8225-8672f4c2a32a |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +csr_rw +create_jtag_riscv_map=1 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1782161070 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_T EST_SEQ=chip_jtag_csr_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.c hip_jtag_csr_rw.1782161070 |
| Directory | /workspace/2.chip_jtag_csr_rw/latest |
| Test location | /workspace/coverage/default/2.chip_jtag_mem_access.2854716068 |
| Short name | T193 |
| Test name | |
| Test status | |
| Simulation time | 13455548240 ps |
| CPU time | 1282.24 seconds |
| Started | Jun 23 08:05:51 PM PDT 24 |
| Finished | Jun 23 08:27:14 PM PDT 24 |
| Peak memory | 605124 kb |
| Host | smart-34f3c41f-ff29-4406-9803-23352a24d7b2 |
| User | root |
| Command | /workspace/default/simv +create_jtag_riscv_map=1 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2854716068 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_jtag_ mem_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_jtag_mem_access.2 854716068 |
| Directory | /workspace/2.chip_jtag_mem_access/latest |
| Test location | /workspace/coverage/default/2.chip_rv_dm_ndm_reset_req.4265873937 |
| Short name | T8 |
| Test name | |
| Test status | |
| Simulation time | 3587631504 ps |
| CPU time | 436.73 seconds |
| Started | Jun 23 08:13:27 PM PDT 24 |
| Finished | Jun 23 08:20:44 PM PDT 24 |
| Peak memory | 617632 kb |
| Host | smart-25f07c10-8d4d-47da-b6ec-cbb6e8a1db2f |
| User | root |
| Command | /workspace/default/simv +en_scb_tl_err_chk=0 +use_jtag_dmi=1 +sw_build_device=sim_dv +sw_images=rv_dm_ndm_reset_req_rma:1:new_rules,test_rom:0 +cdc_in strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4 265873937 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_rv_dm_ndm_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_rv_dm_ndm_reset_req.4265873937 |
| Directory | /workspace/2.chip_rv_dm_ndm_reset_req/latest |
| Test location | /workspace/coverage/default/2.chip_sival_flash_info_access.3201655005 |
| Short name | T352 |
| Test name | |
| Test status | |
| Simulation time | 3353379568 ps |
| CPU time | 304.49 seconds |
| Started | Jun 23 08:06:28 PM PDT 24 |
| Finished | Jun 23 08:11:33 PM PDT 24 |
| Peak memory | 606880 kb |
| Host | smart-f6cc4e5a-1fb3-4c22-afba-f714c0f9c1de |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStTestUnlocked0 +sw_build_device=sim_dv +sw_images=flash_ctrl_info_access_lc:1:new_rules,test_rom:0 +c dc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_s eed=3201655005 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sival_flash_info_access.3201655005 |
| Directory | /workspace/2.chip_sival_flash_info_access/latest |
| Test location | /workspace/coverage/default/2.chip_sw_adc_ctrl_sleep_debug_cable_wakeup.1441725862 |
| Short name | T1325 |
| Test name | |
| Test status | |
| Simulation time | 18174074298 ps |
| CPU time | 628.23 seconds |
| Started | Jun 23 08:10:05 PM PDT 24 |
| Finished | Jun 23 08:20:35 PM PDT 24 |
| Peak memory | 615216 kb |
| Host | smart-c7261c10-3aa1-4500-824b-61c051cbe2e6 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=adc_ctrl_sleep_debug_cable_wakeup_test:1:new_rules,test_rom: 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand om_seed=1441725862 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_adc_ctrl_sleep_debug_cable_wakeup_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_adc_ctrl_sleep_debug_cable_wakeup.1441725862 |
| Directory | /workspace/2.chip_sw_adc_ctrl_sleep_debug_cable_wakeup/latest |
| Test location | /workspace/coverage/default/2.chip_sw_aes_enc.1559509882 |
| Short name | T935 |
| Test name | |
| Test status | |
| Simulation time | 2065584484 ps |
| CPU time | 193.35 seconds |
| Started | Jun 23 08:10:19 PM PDT 24 |
| Finished | Jun 23 08:13:33 PM PDT 24 |
| Peak memory | 607684 kb |
| Host | smart-12dbb662-eb7b-4952-85e7-aa9ea9aa113f |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=22_000_000 +sw_build_device=sim_dv +sw_images=aes_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1559509882 -asser t nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag e/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_aes_enc.1559509882 |
| Directory | /workspace/2.chip_sw_aes_enc/latest |
| Test location | /workspace/coverage/default/2.chip_sw_aes_enc_jitter_en.2537954970 |
| Short name | T1258 |
| Test name | |
| Test status | |
| Simulation time | 2788170278 ps |
| CPU time | 310.71 seconds |
| Started | Jun 23 08:08:49 PM PDT 24 |
| Finished | Jun 23 08:14:01 PM PDT 24 |
| Peak memory | 606872 kb |
| Host | smart-81b75ca6-1b29-46ad-a41c-cc1a4020a0f2 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=26_000_000 +en_jitter=1 +sw_build_device=sim_dv +sw_images=aes_smoketest:1:new_rules,test_rom:0 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2537 954970 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work space/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_aes_enc_jitter_en.2537954970 |
| Directory | /workspace/2.chip_sw_aes_enc_jitter_en/latest |
| Test location | /workspace/coverage/default/2.chip_sw_aes_enc_jitter_en_reduced_freq.465363227 |
| Short name | T918 |
| Test name | |
| Test status | |
| Simulation time | 3038373553 ps |
| CPU time | 266.01 seconds |
| Started | Jun 23 08:14:30 PM PDT 24 |
| Finished | Jun 23 08:18:56 PM PDT 24 |
| Peak memory | 607124 kb |
| Host | smart-d5c562a4-2d3f-441b-aa27-fd3e6e55f978 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=26_000_000 +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=aes_smoketest:1:new_rules, test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=465363227 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_aes_enc_jitter_en_reduced_freq.465363227 |
| Directory | /workspace/2.chip_sw_aes_enc_jitter_en_reduced_freq/latest |
| Test location | /workspace/coverage/default/2.chip_sw_aes_entropy.3042016119 |
| Short name | T1072 |
| Test name | |
| Test status | |
| Simulation time | 2796894140 ps |
| CPU time | 235.63 seconds |
| Started | Jun 23 08:09:32 PM PDT 24 |
| Finished | Jun 23 08:13:28 PM PDT 24 |
| Peak memory | 607352 kb |
| Host | smart-916c66f0-e2b5-4e5a-b451-384e65c334a2 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=15_000_000 +sw_build_device=sim_dv +sw_images=aes_entropy_test:1:new_rules,test_rom:0 +cdc_instrumentation _enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3042016119 -as sert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove rage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_aes_entropy.3042016119 |
| Directory | /workspace/2.chip_sw_aes_entropy/latest |
| Test location | /workspace/coverage/default/2.chip_sw_aes_idle.3176298232 |
| Short name | T408 |
| Test name | |
| Test status | |
| Simulation time | 2560793420 ps |
| CPU time | 201.94 seconds |
| Started | Jun 23 08:09:06 PM PDT 24 |
| Finished | Jun 23 08:12:29 PM PDT 24 |
| Peak memory | 606952 kb |
| Host | smart-ec4816f3-88ae-462d-b1a4-424632d5ca82 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=25_000_000 +sw_build_device=sim_dv +sw_images=aes_idle_test:1:new_rules,test_rom:0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3176298232 -asser t nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag e/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_aes_idle.3176298232 |
| Directory | /workspace/2.chip_sw_aes_idle/latest |
| Test location | /workspace/coverage/default/2.chip_sw_aes_masking_off.1579171807 |
| Short name | T687 |
| Test name | |
| Test status | |
| Simulation time | 2643808668 ps |
| CPU time | 415.69 seconds |
| Started | Jun 23 08:10:54 PM PDT 24 |
| Finished | Jun 23 08:17:50 PM PDT 24 |
| Peak memory | 607576 kb |
| Host | smart-c551161d-7afa-4d61-8e3c-279291554dd7 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=aes_masking_off_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1579171807 -assert nopostproc +UVM_TESTNA ME=chip_base_test +UVM_TEST_SEQ=chip_sw_aes_masking_off_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_aes_masking_off.1579171807 |
| Directory | /workspace/2.chip_sw_aes_masking_off/latest |
| Test location | /workspace/coverage/default/2.chip_sw_aes_smoketest.1259568785 |
| Short name | T1174 |
| Test name | |
| Test status | |
| Simulation time | 2850076696 ps |
| CPU time | 253.74 seconds |
| Started | Jun 23 08:16:36 PM PDT 24 |
| Finished | Jun 23 08:20:50 PM PDT 24 |
| Peak memory | 606876 kb |
| Host | smart-94d9bcbe-1ee7-4440-bc3c-73690e0d1182 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=aes_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1259568785 -assert nopostproc +UVM_TESTNAME=chip _base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_aes_smoketest.1259568785 |
| Directory | /workspace/2.chip_sw_aes_smoketest/latest |
| Test location | /workspace/coverage/default/2.chip_sw_alert_handler_entropy.382401612 |
| Short name | T80 |
| Test name | |
| Test status | |
| Simulation time | 2870969409 ps |
| CPU time | 300.59 seconds |
| Started | Jun 23 08:09:50 PM PDT 24 |
| Finished | Jun 23 08:14:51 PM PDT 24 |
| Peak memory | 607656 kb |
| Host | smart-961840e1-6d4a-4884-b898-06320e3c0210 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=alert_handler_entropy_test:1:new_rules,test_ro m:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=382401612 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_alert_handler_entropy.382401612 |
| Directory | /workspace/2.chip_sw_alert_handler_entropy/latest |
| Test location | /workspace/coverage/default/2.chip_sw_alert_handler_escalation.204532030 |
| Short name | T186 |
| Test name | |
| Test status | |
| Simulation time | 5517353432 ps |
| CPU time | 488.32 seconds |
| Started | Jun 23 08:10:57 PM PDT 24 |
| Finished | Jun 23 08:19:06 PM PDT 24 |
| Peak memory | 617016 kb |
| Host | smart-0378108c-b354-4399-8172-95c8af50f777 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=alert_handler_escalation_test:1:new_rules,test _rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb _random_seed=204532030 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_alert_handler_escalation_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_alert_handler_escalation.204532030 |
| Directory | /workspace/2.chip_sw_alert_handler_escalation/latest |
| Test location | /workspace/coverage/default/2.chip_sw_alert_handler_lpg_clkoff.2261417920 |
| Short name | T1321 |
| Test name | |
| Test status | |
| Simulation time | 6627101340 ps |
| CPU time | 1418.96 seconds |
| Started | Jun 23 08:10:20 PM PDT 24 |
| Finished | Jun 23 08:34:00 PM PDT 24 |
| Peak memory | 607964 kb |
| Host | smart-c9b9e3ce-d4d4-4fab-9e9c-5ea02c1512c5 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +sw_build_device=sim_dv +sw_images=alert_handler_lpg_clkoff_test:1:new_rules,test_r om:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r andom_seed=2261417920 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_alert_handler_lpg_clkoff_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_alert_handler_lpg_clkoff.2261417920 |
| Directory | /workspace/2.chip_sw_alert_handler_lpg_clkoff/latest |
| Test location | /workspace/coverage/default/2.chip_sw_alert_handler_lpg_reset_toggle.2433613666 |
| Short name | T1115 |
| Test name | |
| Test status | |
| Simulation time | 8199364232 ps |
| CPU time | 1462.54 seconds |
| Started | Jun 23 08:11:42 PM PDT 24 |
| Finished | Jun 23 08:36:05 PM PDT 24 |
| Peak memory | 607132 kb |
| Host | smart-ddcad7dc-c237-4051-bd16-59437fb071e4 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +sw_build_device=sim_dv +sw_images=alert_handler_lpg_reset_toggle_test:1:new_rules, test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2433613666 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_alert_handler_shorten_ping_wait_cycle_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_alert_handler_lpg_reset_togg le.2433613666 |
| Directory | /workspace/2.chip_sw_alert_handler_lpg_reset_toggle/latest |
| Test location | /workspace/coverage/default/2.chip_sw_alert_handler_lpg_sleep_mode_pings.331952383 |
| Short name | T89 |
| Test name | |
| Test status | |
| Simulation time | 11365457512 ps |
| CPU time | 1380.46 seconds |
| Started | Jun 23 08:10:57 PM PDT 24 |
| Finished | Jun 23 08:33:58 PM PDT 24 |
| Peak memory | 608808 kb |
| Host | smart-764a196a-0be1-4867-9c59-2facf6dee33a |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=alert_handler _lpg_sleep_mode_pings_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=331952383 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_alert_hand ler_shorten_ping_wait_cycle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_alert_handler_lpg_sleep_mode_pings.331952383 |
| Directory | /workspace/2.chip_sw_alert_handler_lpg_sleep_mode_pings/latest |
| Test location | /workspace/coverage/default/2.chip_sw_alert_handler_ping_ok.1277338755 |
| Short name | T1019 |
| Test name | |
| Test status | |
| Simulation time | 8541691724 ps |
| CPU time | 1198.38 seconds |
| Started | Jun 23 08:10:59 PM PDT 24 |
| Finished | Jun 23 08:30:58 PM PDT 24 |
| Peak memory | 607076 kb |
| Host | smart-4bfa8964-0100-4c3a-b51e-ab416198c8af |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=24000000 +sw_build_device=sim_dv +sw_images=alert_handler_ping_ok_test:1:new_rules,test_rom:0 +c dc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_s eed=1277338755 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_alert_handler_ping_ok.1277338755 |
| Directory | /workspace/2.chip_sw_alert_handler_ping_ok/latest |
| Test location | /workspace/coverage/default/2.chip_sw_alert_handler_ping_timeout.612626345 |
| Short name | T981 |
| Test name | |
| Test status | |
| Simulation time | 4973328350 ps |
| CPU time | 566.72 seconds |
| Started | Jun 23 08:10:47 PM PDT 24 |
| Finished | Jun 23 08:20:15 PM PDT 24 |
| Peak memory | 607124 kb |
| Host | smart-bf6be5f0-627b-420b-b310-588e68453f70 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=24000000 +sw_build_device=sim_dv +sw_images=alert_handler_ping_timeout_test:1:new_rules,test_rom :0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=612626345 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_alert_handler_ping_timeout.612626345 |
| Directory | /workspace/2.chip_sw_alert_handler_ping_timeout/latest |
| Test location | /workspace/coverage/default/2.chip_sw_alert_handler_reverse_ping_in_deep_sleep.701179381 |
| Short name | T1349 |
| Test name | |
| Test status | |
| Simulation time | 255062603848 ps |
| CPU time | 11407.5 seconds |
| Started | Jun 23 08:11:09 PM PDT 24 |
| Finished | Jun 23 11:21:18 PM PDT 24 |
| Peak memory | 608632 kb |
| Host | smart-8ba4ce16-c4ac-4843-aa86-30c3c53c94e6 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=300_000_000 +sw_build_device=sim_dv +sw_images=alert_handler_reverse_ping_in_deep_sleep_test:1:n ew_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=701179381 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tg l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_alert_handler_reverse_ping_in_deep_sleep.701179381 |
| Directory | /workspace/2.chip_sw_alert_handler_reverse_ping_in_deep_sleep/latest |
| Test location | /workspace/coverage/default/2.chip_sw_alert_test.2140942070 |
| Short name | T61 |
| Test name | |
| Test status | |
| Simulation time | 2921861470 ps |
| CPU time | 316.05 seconds |
| Started | Jun 23 08:09:50 PM PDT 24 |
| Finished | Jun 23 08:15:06 PM PDT 24 |
| Peak memory | 606920 kb |
| Host | smart-1ff47b1f-b19c-4926-9d81-3b715d7bdf7b |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=alert_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2140942070 -assert nopostproc +UVM_TESTNAME=chip_ba se_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 2.chip_sw_alert_test.2140942070 |
| Directory | /workspace/2.chip_sw_alert_test/latest |
| Test location | /workspace/coverage/default/2.chip_sw_aon_timer_irq.696195875 |
| Short name | T733 |
| Test name | |
| Test status | |
| Simulation time | 3992860780 ps |
| CPU time | 397.57 seconds |
| Started | Jun 23 08:08:17 PM PDT 24 |
| Finished | Jun 23 08:14:55 PM PDT 24 |
| Peak memory | 607464 kb |
| Host | smart-0a65a15f-9221-48fc-8e6c-3d62b4b5f01f |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=aon_timer_irq_test:1:new_rules,test_rom:0 +cdc_instrumentati on_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=696195875 -a ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov erage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_aon_timer_irq.696195875 |
| Directory | /workspace/2.chip_sw_aon_timer_irq/latest |
| Test location | /workspace/coverage/default/2.chip_sw_aon_timer_sleep_wdog_sleep_pause.586408679 |
| Short name | T1029 |
| Test name | |
| Test status | |
| Simulation time | 6714534002 ps |
| CPU time | 434.85 seconds |
| Started | Jun 23 08:08:29 PM PDT 24 |
| Finished | Jun 23 08:15:45 PM PDT 24 |
| Peak memory | 607132 kb |
| Host | smart-99185792-1bb6-412d-a438-7a961a5e1473 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=aon_timer_sleep_wdog_sleep_pause_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=586408679 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_aon_timer_sleep_wdog_sleep_pause.586408679 |
| Directory | /workspace/2.chip_sw_aon_timer_sleep_wdog_sleep_pause/latest |
| Test location | /workspace/coverage/default/2.chip_sw_aon_timer_smoketest.4159215310 |
| Short name | T1010 |
| Test name | |
| Test status | |
| Simulation time | 3150679030 ps |
| CPU time | 366.42 seconds |
| Started | Jun 23 08:22:56 PM PDT 24 |
| Finished | Jun 23 08:29:03 PM PDT 24 |
| Peak memory | 607108 kb |
| Host | smart-c9b01383-95d2-4c30-9707-bd4de22fb741 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=aon_timer_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4159215310 -assert nopostproc +UVM_TESTNAM E=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 2.chip_sw_aon_timer_smoketest.4159215310 |
| Directory | /workspace/2.chip_sw_aon_timer_smoketest/latest |
| Test location | /workspace/coverage/default/2.chip_sw_aon_timer_wdog_bite_reset.2398791779 |
| Short name | T953 |
| Test name | |
| Test status | |
| Simulation time | 9705728100 ps |
| CPU time | 625.24 seconds |
| Started | Jun 23 08:09:23 PM PDT 24 |
| Finished | Jun 23 08:19:49 PM PDT 24 |
| Peak memory | 608100 kb |
| Host | smart-6e2e6c1c-804f-4459-adc2-63fb5856a1a6 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=aon_timer_wdog_bite_reset_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 2398791779 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_aon_timer_wdog_bite_reset.2398791779 |
| Directory | /workspace/2.chip_sw_aon_timer_wdog_bite_reset/latest |
| Test location | /workspace/coverage/default/2.chip_sw_aon_timer_wdog_lc_escalate.2221659280 |
| Short name | T1025 |
| Test name | |
| Test status | |
| Simulation time | 4321869912 ps |
| CPU time | 619.42 seconds |
| Started | Jun 23 08:09:02 PM PDT 24 |
| Finished | Jun 23 08:19:22 PM PDT 24 |
| Peak memory | 608496 kb |
| Host | smart-7f53fc35-4601-411e-93f4-4af391db1d43 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=aon_timer_wdog_lc_escalate_test:1:new_rules,test_rom:0 +cdc_ instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed =2221659280 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_aon_timer_wdog_lc_escalate.2221659280 |
| Directory | /workspace/2.chip_sw_aon_timer_wdog_lc_escalate/latest |
| Test location | /workspace/coverage/default/2.chip_sw_ast_clk_outputs.1971426117 |
| Short name | T1335 |
| Test name | |
| Test status | |
| Simulation time | 7313037274 ps |
| CPU time | 799.38 seconds |
| Started | Jun 23 08:13:18 PM PDT 24 |
| Finished | Jun 23 08:26:37 PM PDT 24 |
| Peak memory | 613876 kb |
| Host | smart-c7027f47-246a-492e-9479-91461965c9f8 |
| User | root |
| Command | /workspace/default/simv +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=ast_clk_outs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled= 1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1971426117 -assert nopo stproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_ast_clk_outputs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co verage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_ast_clk_outputs.1971426117 |
| Directory | /workspace/2.chip_sw_ast_clk_outputs/latest |
| Test location | /workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_lc.455756348 |
| Short name | T930 |
| Test name | |
| Test status | |
| Simulation time | 12147892906 ps |
| CPU time | 853.94 seconds |
| Started | Jun 23 08:12:35 PM PDT 24 |
| Finished | Jun 23 08:26:49 PM PDT 24 |
| Peak memory | 621560 kb |
| Host | smart-e2fad042-18b0-4122-8595-ee37123e375e |
| User | root |
| Command | /workspace/default/simv +chip_clock_source=ChipClockSourceExternal48Mhz +sw_build_device=sim_dv +sw_images=clkmgr_external_clk_src_for_lc_test:1:new_r ules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim .tcl +ntb_random_seed=455756348 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_transition_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_clkmgr_external_clk_src_for_lc.455756348 |
| Directory | /workspace/2.chip_sw_clkmgr_external_clk_src_for_lc/latest |
| Test location | /workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_fast_dev.3622831719 |
| Short name | T1333 |
| Test name | |
| Test status | |
| Simulation time | 3762820860 ps |
| CPU time | 582.35 seconds |
| Started | Jun 23 08:12:10 PM PDT 24 |
| Finished | Jun 23 08:21:53 PM PDT 24 |
| Peak memory | 611472 kb |
| Host | smart-09d1fb1c-9f3d-42ad-98ac-3ef65c0ca584 |
| User | root |
| Command | /workspace/default/simv +chip_clock_source=ChipClockSourceExternal96Mhz +calibrate_usb_clk=1 +src_dec_state=DecLcStDev +sw_build_device=sim_dv +sw_ima ges=clkmgr_external_clk_src_for_sw_fast_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3622831719 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ =chip_sw_lc_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_c lkmgr_external_clk_src_for_sw_fast_dev.3622831719 |
| Directory | /workspace/2.chip_sw_clkmgr_external_clk_src_for_sw_fast_dev/latest |
| Test location | /workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_fast_rma.380499006 |
| Short name | T958 |
| Test name | |
| Test status | |
| Simulation time | 3766154330 ps |
| CPU time | 658.61 seconds |
| Started | Jun 23 08:12:17 PM PDT 24 |
| Finished | Jun 23 08:23:16 PM PDT 24 |
| Peak memory | 610564 kb |
| Host | smart-f0d7a4dd-4e40-47a4-b522-81edbdbe4787 |
| User | root |
| Command | /workspace/default/simv +chip_clock_source=ChipClockSourceExternal96Mhz +calibrate_usb_clk=1 +src_dec_state=DecLcStRma +sw_build_device=sim_dv +sw_ima ges=clkmgr_external_clk_src_for_sw_fast_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=380499006 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ= chip_sw_lc_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_cl kmgr_external_clk_src_for_sw_fast_rma.380499006 |
| Directory | /workspace/2.chip_sw_clkmgr_external_clk_src_for_sw_fast_rma/latest |
| Test location | /workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0.3152072444 |
| Short name | T977 |
| Test name | |
| Test status | |
| Simulation time | 3583297090 ps |
| CPU time | 663.61 seconds |
| Started | Jun 23 08:11:45 PM PDT 24 |
| Finished | Jun 23 08:22:49 PM PDT 24 |
| Peak memory | 611628 kb |
| Host | smart-4b122b40-e366-40be-aa54-b6fae27729da |
| User | root |
| Command | /workspace/default/simv +chip_clock_source=ChipClockSourceExternal96Mhz +calibrate_usb_clk=1 +src_dec_state=DecLcStTestUnlocked0 +sw_build_device=sim_ dv +sw_images=clkmgr_external_clk_src_for_sw_fast_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3152072444 -assert nopostproc +UVM_TESTNAME=chip_base_test +UV M_TEST_SEQ=chip_sw_lc_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2 .chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0.3152072444 |
| Directory | /workspace/2.chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0/latest |
| Test location | /workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_slow_dev.2209023606 |
| Short name | T1088 |
| Test name | |
| Test status | |
| Simulation time | 4632868450 ps |
| CPU time | 509.57 seconds |
| Started | Jun 23 08:12:05 PM PDT 24 |
| Finished | Jun 23 08:20:35 PM PDT 24 |
| Peak memory | 611496 kb |
| Host | smart-1210b14f-5f4f-46be-8018-e9ffd0227a5e |
| User | root |
| Command | /workspace/default/simv +chip_clock_source=ChipClockSourceExternal48Mhz +calibrate_usb_clk=1 +src_dec_state=DecLcStDev +sw_build_device=sim_dv +sw_ima ges=clkmgr_external_clk_src_for_sw_slow_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2209023606 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ =chip_sw_lc_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_c lkmgr_external_clk_src_for_sw_slow_dev.2209023606 |
| Directory | /workspace/2.chip_sw_clkmgr_external_clk_src_for_sw_slow_dev/latest |
| Test location | /workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_slow_rma.1195016461 |
| Short name | T118 |
| Test name | |
| Test status | |
| Simulation time | 4956695250 ps |
| CPU time | 740.7 seconds |
| Started | Jun 23 08:12:34 PM PDT 24 |
| Finished | Jun 23 08:24:55 PM PDT 24 |
| Peak memory | 611584 kb |
| Host | smart-38f479fe-cf7b-4f6d-86d8-49c14f581ea8 |
| User | root |
| Command | /workspace/default/simv +chip_clock_source=ChipClockSourceExternal48Mhz +calibrate_usb_clk=1 +src_dec_state=DecLcStRma +sw_build_device=sim_dv +sw_ima ges=clkmgr_external_clk_src_for_sw_slow_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1195016461 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ =chip_sw_lc_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_c lkmgr_external_clk_src_for_sw_slow_rma.1195016461 |
| Directory | /workspace/2.chip_sw_clkmgr_external_clk_src_for_sw_slow_rma/latest |
| Test location | /workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0.2246380478 |
| Short name | T932 |
| Test name | |
| Test status | |
| Simulation time | 4424164396 ps |
| CPU time | 703.99 seconds |
| Started | Jun 23 08:12:36 PM PDT 24 |
| Finished | Jun 23 08:24:20 PM PDT 24 |
| Peak memory | 611612 kb |
| Host | smart-55d12652-5a09-4cd4-9c0d-7672d09d349d |
| User | root |
| Command | /workspace/default/simv +chip_clock_source=ChipClockSourceExternal48Mhz +calibrate_usb_clk=1 +src_dec_state=DecLcStTestUnlocked0 +sw_build_device=sim_ dv +sw_images=clkmgr_external_clk_src_for_sw_slow_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2246380478 -assert nopostproc +UVM_TESTNAME=chip_base_test +UV M_TEST_SEQ=chip_sw_lc_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2 .chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0.2246380478 |
| Directory | /workspace/2.chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0/latest |
| Test location | /workspace/coverage/default/2.chip_sw_clkmgr_jitter.1051355480 |
| Short name | T305 |
| Test name | |
| Test status | |
| Simulation time | 1864043061 ps |
| CPU time | 193.04 seconds |
| Started | Jun 23 08:12:14 PM PDT 24 |
| Finished | Jun 23 08:15:27 PM PDT 24 |
| Peak memory | 607528 kb |
| Host | smart-622c9f9f-c86b-4669-9500-bcd8035751d2 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_jitter_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1051355480 -assert nopostproc +UVM_TESTNAME =chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 2.chip_sw_clkmgr_jitter.1051355480 |
| Directory | /workspace/2.chip_sw_clkmgr_jitter/latest |
| Test location | /workspace/coverage/default/2.chip_sw_clkmgr_jitter_frequency.3284870601 |
| Short name | T917 |
| Test name | |
| Test status | |
| Simulation time | 3702357440 ps |
| CPU time | 459.7 seconds |
| Started | Jun 23 08:14:02 PM PDT 24 |
| Finished | Jun 23 08:21:42 PM PDT 24 |
| Peak memory | 606928 kb |
| Host | smart-b9f583e4-0216-4a86-a4c6-321a3605f567 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_jitter_frequency_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3284870601 -assert nopostproc +UV M_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -c m_log /dev/null -cm_name 2.chip_sw_clkmgr_jitter_frequency.3284870601 |
| Directory | /workspace/2.chip_sw_clkmgr_jitter_frequency/latest |
| Test location | /workspace/coverage/default/2.chip_sw_clkmgr_jitter_reduced_freq.3904525168 |
| Short name | T1203 |
| Test name | |
| Test status | |
| Simulation time | 3558453023 ps |
| CPU time | 320.03 seconds |
| Started | Jun 23 08:15:23 PM PDT 24 |
| Finished | Jun 23 08:20:43 PM PDT 24 |
| Peak memory | 607580 kb |
| Host | smart-2314c53a-ba92-4f3d-a4d6-184f8c4ff241 |
| User | root |
| Command | /workspace/default/simv +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=clkmgr_jitter_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3904525168 -assert nop ostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def ault.vdb -cm_log /dev/null -cm_name 2.chip_sw_clkmgr_jitter_reduced_freq.3904525168 |
| Directory | /workspace/2.chip_sw_clkmgr_jitter_reduced_freq/latest |
| Test location | /workspace/coverage/default/2.chip_sw_clkmgr_off_aes_trans.1938487833 |
| Short name | T403 |
| Test name | |
| Test status | |
| Simulation time | 3883650620 ps |
| CPU time | 545.62 seconds |
| Started | Jun 23 08:11:54 PM PDT 24 |
| Finished | Jun 23 08:21:00 PM PDT 24 |
| Peak memory | 607852 kb |
| Host | smart-4fa1721d-28b9-48d1-b7ab-a52e80500f36 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_off_aes_trans_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1938487833 -assert nopostproc +UVM_T ESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l og /dev/null -cm_name 2.chip_sw_clkmgr_off_aes_trans.1938487833 |
| Directory | /workspace/2.chip_sw_clkmgr_off_aes_trans/latest |
| Test location | /workspace/coverage/default/2.chip_sw_clkmgr_off_hmac_trans.463986519 |
| Short name | T97 |
| Test name | |
| Test status | |
| Simulation time | 4276879460 ps |
| CPU time | 428.54 seconds |
| Started | Jun 23 08:12:43 PM PDT 24 |
| Finished | Jun 23 08:19:52 PM PDT 24 |
| Peak memory | 606936 kb |
| Host | smart-734ae459-9fe6-48e5-8261-67143a7d4344 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_off_hmac_trans_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=463986519 -assert nopostproc +UVM_T ESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l og /dev/null -cm_name 2.chip_sw_clkmgr_off_hmac_trans.463986519 |
| Directory | /workspace/2.chip_sw_clkmgr_off_hmac_trans/latest |
| Test location | /workspace/coverage/default/2.chip_sw_clkmgr_off_kmac_trans.3213095723 |
| Short name | T83 |
| Test name | |
| Test status | |
| Simulation time | 4197570000 ps |
| CPU time | 417.63 seconds |
| Started | Jun 23 08:13:41 PM PDT 24 |
| Finished | Jun 23 08:20:40 PM PDT 24 |
| Peak memory | 607884 kb |
| Host | smart-cd1d2907-ddb3-44ba-9418-033778e55679 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_off_kmac_trans_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3213095723 -assert nopostproc +UVM_ TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_ log /dev/null -cm_name 2.chip_sw_clkmgr_off_kmac_trans.3213095723 |
| Directory | /workspace/2.chip_sw_clkmgr_off_kmac_trans/latest |
| Test location | /workspace/coverage/default/2.chip_sw_clkmgr_off_otbn_trans.2901084806 |
| Short name | T1082 |
| Test name | |
| Test status | |
| Simulation time | 5514857686 ps |
| CPU time | 478.73 seconds |
| Started | Jun 23 08:11:41 PM PDT 24 |
| Finished | Jun 23 08:19:41 PM PDT 24 |
| Peak memory | 607840 kb |
| Host | smart-38afff8d-e2df-424c-91d8-eb70531ba78e |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_off_otbn_trans_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2901084806 -assert nopostproc +UVM_ TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_ log /dev/null -cm_name 2.chip_sw_clkmgr_off_otbn_trans.2901084806 |
| Directory | /workspace/2.chip_sw_clkmgr_off_otbn_trans/latest |
| Test location | /workspace/coverage/default/2.chip_sw_clkmgr_off_peri.7799188 |
| Short name | T308 |
| Test name | |
| Test status | |
| Simulation time | 10379861726 ps |
| CPU time | 1413.53 seconds |
| Started | Jun 23 08:11:30 PM PDT 24 |
| Finished | Jun 23 08:35:04 PM PDT 24 |
| Peak memory | 608152 kb |
| Host | smart-aca316e4-7ad7-4909-87bb-2c6358593dfb |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=30_000_000 +sw_build_device=sim_dv +sw_images=clkmgr_off_peri_test:1:new_rules,test_rom:0 +cdc_instrumenta tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=7799188 -a ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov erage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_clkmgr_off_peri.7799188 |
| Directory | /workspace/2.chip_sw_clkmgr_off_peri/latest |
| Test location | /workspace/coverage/default/2.chip_sw_clkmgr_reset_frequency.3112047936 |
| Short name | T747 |
| Test name | |
| Test status | |
| Simulation time | 3460142196 ps |
| CPU time | 474.13 seconds |
| Started | Jun 23 08:13:02 PM PDT 24 |
| Finished | Jun 23 08:20:56 PM PDT 24 |
| Peak memory | 607648 kb |
| Host | smart-8b158724-3f2f-4503-9606-66b0d4d4a2c9 |
| User | root |
| Command | /workspace/default/simv +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=clkmgr_reset_frequency_test:1:new_rules,test_rom:0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3112047936 -a ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov erage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_clkmgr_reset_frequency.3112047936 |
| Directory | /workspace/2.chip_sw_clkmgr_reset_frequency/latest |
| Test location | /workspace/coverage/default/2.chip_sw_clkmgr_sleep_frequency.3690294223 |
| Short name | T1336 |
| Test name | |
| Test status | |
| Simulation time | 5152483432 ps |
| CPU time | 601.5 seconds |
| Started | Jun 23 08:11:58 PM PDT 24 |
| Finished | Jun 23 08:22:00 PM PDT 24 |
| Peak memory | 607984 kb |
| Host | smart-be82bb67-1a1e-4986-a6d6-2d4f9d25f10c |
| User | root |
| Command | /workspace/default/simv +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=clkmgr_sleep_frequency_test:1:new_rules,test_rom:0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3690294223 -a ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov erage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_clkmgr_sleep_frequency.3690294223 |
| Directory | /workspace/2.chip_sw_clkmgr_sleep_frequency/latest |
| Test location | /workspace/coverage/default/2.chip_sw_clkmgr_smoketest.3655780316 |
| Short name | T940 |
| Test name | |
| Test status | |
| Simulation time | 2749641682 ps |
| CPU time | 251.85 seconds |
| Started | Jun 23 08:15:46 PM PDT 24 |
| Finished | Jun 23 08:19:58 PM PDT 24 |
| Peak memory | 607592 kb |
| Host | smart-c606940b-e8de-4218-a033-952b83ffbcf4 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3655780316 -assert nopostproc +UVM_TESTNAME=c hip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n ull -cm_name 2.chip_sw_clkmgr_smoketest.3655780316 |
| Directory | /workspace/2.chip_sw_clkmgr_smoketest/latest |
| Test location | /workspace/coverage/default/2.chip_sw_csrng_edn_concurrency.236636851 |
| Short name | T1125 |
| Test name | |
| Test status | |
| Simulation time | 25869495420 ps |
| CPU time | 5266.21 seconds |
| Started | Jun 23 08:11:14 PM PDT 24 |
| Finished | Jun 23 09:39:01 PM PDT 24 |
| Peak memory | 607332 kb |
| Host | smart-c11dacf9-f9f7-41a4-a17d-78776eade541 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=140_000_000 +rng_srate_value_min=15 +rng_srate_value_max=20 +accelerate_cold_power_up_time=3 +accelerate_r egulators_power_up_time=2 +sw_build_device=sim_dv +sw_images=csrng_edn_concurrency_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=236636851 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_csrng_edn_concurrency.236636851 |
| Directory | /workspace/2.chip_sw_csrng_edn_concurrency/latest |
| Test location | /workspace/coverage/default/2.chip_sw_csrng_edn_concurrency_reduced_freq.212072301 |
| Short name | T1241 |
| Test name | |
| Test status | |
| Simulation time | 10342940483 ps |
| CPU time | 1882.42 seconds |
| Started | Jun 23 08:14:35 PM PDT 24 |
| Finished | Jun 23 08:45:58 PM PDT 24 |
| Peak memory | 607344 kb |
| Host | smart-cc9f7490-f8f8-403e-8b5a-fdb080043e6c |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=360_000_000 +rng_srate_value_min=15 +rng_srate_value_max=20 +cal_sys_clk_70mhz=1 +en_jitter=1 +accelerate_ cold_power_up_time=3 +accelerate_regulators_power_up_time=2 +sw_build_device=sim_dv +sw_images=csrng_edn_concurrency_test:1:new_rules,test_rom:0 + cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_ seed=212072301 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_csrng_edn_concurrency_reduced_freq.212072301 |
| Directory | /workspace/2.chip_sw_csrng_edn_concurrency_reduced_freq/latest |
| Test location | /workspace/coverage/default/2.chip_sw_csrng_fuse_en_sw_app_read_test.4236576562 |
| Short name | T1234 |
| Test name | |
| Test status | |
| Simulation time | 3894279528 ps |
| CPU time | 395.38 seconds |
| Started | Jun 23 08:09:53 PM PDT 24 |
| Finished | Jun 23 08:16:29 PM PDT 24 |
| Peak memory | 608128 kb |
| Host | smart-5384cd26-9d33-4276-bb37-a14a8028d97c |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=15_000_000 +sw_build_device=sim_dv +sw_images=csrng_fuse_en_sw_app_read:1:new_rules,test_rom:0 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42365 76562 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_entropy_src_fuse_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_csrng_fuse_en_sw_app_read_test.4236576562 |
| Directory | /workspace/2.chip_sw_csrng_fuse_en_sw_app_read_test/latest |
| Test location | /workspace/coverage/default/2.chip_sw_csrng_kat_test.2781890340 |
| Short name | T1040 |
| Test name | |
| Test status | |
| Simulation time | 2149100282 ps |
| CPU time | 224.23 seconds |
| Started | Jun 23 08:12:04 PM PDT 24 |
| Finished | Jun 23 08:15:49 PM PDT 24 |
| Peak memory | 607768 kb |
| Host | smart-8f79df74-b31c-4c0a-a241-30cfdb1d8d82 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=csrng_kat_test:1:new_rules,test_rom:0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2781890340 -asse rt nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera ge/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_csrng_kat_test.2781890340 |
| Directory | /workspace/2.chip_sw_csrng_kat_test/latest |
| Test location | /workspace/coverage/default/2.chip_sw_csrng_smoketest.3416099698 |
| Short name | T913 |
| Test name | |
| Test status | |
| Simulation time | 2804103380 ps |
| CPU time | 282.62 seconds |
| Started | Jun 23 08:15:06 PM PDT 24 |
| Finished | Jun 23 08:19:49 PM PDT 24 |
| Peak memory | 607816 kb |
| Host | smart-d8989640-8203-42b8-8c07-81edacbf8976 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=csrng_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3416099698 -assert nopostproc +UVM_TESTNAME=ch ip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu ll -cm_name 2.chip_sw_csrng_smoketest.3416099698 |
| Directory | /workspace/2.chip_sw_csrng_smoketest/latest |
| Test location | /workspace/coverage/default/2.chip_sw_data_integrity_escalation.2382657562 |
| Short name | T271 |
| Test name | |
| Test status | |
| Simulation time | 4771786618 ps |
| CPU time | 849.61 seconds |
| Started | Jun 23 08:07:34 PM PDT 24 |
| Finished | Jun 23 08:21:44 PM PDT 24 |
| Peak memory | 608760 kb |
| Host | smart-70de2ab5-35f8-489e-a857-f78e9b969cca |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=data_integrity_escalation_reset_test:1:new_rules,test_ro m:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=2382657562 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_data_integrity_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_data_integrity_escalation.2382657562 |
| Directory | /workspace/2.chip_sw_data_integrity_escalation/latest |
| Test location | /workspace/coverage/default/2.chip_sw_edn_auto_mode.1477763523 |
| Short name | T1098 |
| Test name | |
| Test status | |
| Simulation time | 7754488736 ps |
| CPU time | 1849 seconds |
| Started | Jun 23 08:10:05 PM PDT 24 |
| Finished | Jun 23 08:40:55 PM PDT 24 |
| Peak memory | 607240 kb |
| Host | smart-aba6ec82-3ac1-4d07-bb73-a2a915499ae1 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +rng_srate_value=5 +accelerate_cold_power_up_time=3 +accelerate_regulators_power_up_time=2 +sw_ build_device=sim_dv +sw_images=edn_auto_mode:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1477763523 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ =chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_edn_ auto_mode.1477763523 |
| Directory | /workspace/2.chip_sw_edn_auto_mode/latest |
| Test location | /workspace/coverage/default/2.chip_sw_edn_boot_mode.3053868985 |
| Short name | T123 |
| Test name | |
| Test status | |
| Simulation time | 2869204336 ps |
| CPU time | 694.21 seconds |
| Started | Jun 23 08:11:23 PM PDT 24 |
| Finished | Jun 23 08:22:58 PM PDT 24 |
| Peak memory | 607140 kb |
| Host | smart-b589ab29-f60d-49c4-bfc6-54ab2853031d |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +rng_srate_value=5 +accelerate_cold_power_up_time=3 +accelerate_regulators_power_up_time=2 +sw_ build_device=sim_dv +sw_images=edn_boot_mode:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3053868985 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ =chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_edn_ boot_mode.3053868985 |
| Directory | /workspace/2.chip_sw_edn_boot_mode/latest |
| Test location | /workspace/coverage/default/2.chip_sw_edn_entropy_reqs.2746196340 |
| Short name | T1271 |
| Test name | |
| Test status | |
| Simulation time | 5762231756 ps |
| CPU time | 906.56 seconds |
| Started | Jun 23 08:12:25 PM PDT 24 |
| Finished | Jun 23 08:27:32 PM PDT 24 |
| Peak memory | 607820 kb |
| Host | smart-b1b6a192-6f0c-45a7-94b9-9128d52761f3 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=15000000 +rng_srate_value_min=15 +rng_srate_value_max=30 +sw_build_device=sim_dv +sw_images=entropy_src_ed n_reqs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2746196340 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_edn_entropy_reqs.2746196340 |
| Directory | /workspace/2.chip_sw_edn_entropy_reqs/latest |
| Test location | /workspace/coverage/default/2.chip_sw_edn_entropy_reqs_jitter.4030163986 |
| Short name | T1129 |
| Test name | |
| Test status | |
| Simulation time | 6582710153 ps |
| CPU time | 1214.08 seconds |
| Started | Jun 23 08:10:54 PM PDT 24 |
| Finished | Jun 23 08:31:09 PM PDT 24 |
| Peak memory | 608524 kb |
| Host | smart-84e594ad-6b67-463d-8182-20bdea3d6f6d |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=15000000 +rng_srate_value_min=15 +rng_srate_value_max=30 +en_jitter=1 +sw_build_device=sim_dv +sw_images=e ntropy_src_edn_reqs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4030163986 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_edn_entropy_reqs_jitter.4030163986 |
| Directory | /workspace/2.chip_sw_edn_entropy_reqs_jitter/latest |
| Test location | /workspace/coverage/default/2.chip_sw_edn_kat.876606184 |
| Short name | T405 |
| Test name | |
| Test status | |
| Simulation time | 3700900060 ps |
| CPU time | 659.61 seconds |
| Started | Jun 23 08:10:14 PM PDT 24 |
| Finished | Jun 23 08:21:14 PM PDT 24 |
| Peak memory | 613016 kb |
| Host | smart-b30ed96f-b17e-41d5-8285-411dc41137a8 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +rng_srate_value=5 +disable_assert_edn_output_diff_from_prev=1 +accelerate_cold_power_up_time=3 +accelerate_regulators_power_up_time=2 +sw_build_device=sim_dv +sw_images=edn_kat:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=876606184 -assert nopostproc +UVM_ TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_ log /dev/null -cm_name 2.chip_sw_edn_kat.876606184 |
| Directory | /workspace/2.chip_sw_edn_kat/latest |
| Test location | /workspace/coverage/default/2.chip_sw_edn_sw_mode.4037780078 |
| Short name | T991 |
| Test name | |
| Test status | |
| Simulation time | 9016653984 ps |
| CPU time | 1569.61 seconds |
| Started | Jun 23 08:10:37 PM PDT 24 |
| Finished | Jun 23 08:36:47 PM PDT 24 |
| Peak memory | 606844 kb |
| Host | smart-73081143-5baf-4e92-adb9-872d4dc097df |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=edn_sw_mode:1:new_rules,test_rom:0 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4037780078 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/ default.vdb -cm_log /dev/null -cm_name 2.chip_sw_edn_sw_mode.4037780078 |
| Directory | /workspace/2.chip_sw_edn_sw_mode/latest |
| Test location | /workspace/coverage/default/2.chip_sw_entropy_src_ast_rng_req.4013552339 |
| Short name | T272 |
| Test name | |
| Test status | |
| Simulation time | 2710941192 ps |
| CPU time | 185.34 seconds |
| Started | Jun 23 08:12:21 PM PDT 24 |
| Finished | Jun 23 08:15:27 PM PDT 24 |
| Peak memory | 607896 kb |
| Host | smart-5bd1b94e-fe95-41e3-9dce-a502cbdc60f2 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=15_000_000 +sw_build_device=sim_dv +sw_images=entropy_src_ast_rng_req_test:1:new_rules,test_rom:0 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40 13552339 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_entropy_src_ast_rng_req.4013552339 |
| Directory | /workspace/2.chip_sw_entropy_src_ast_rng_req/latest |
| Test location | /workspace/coverage/default/2.chip_sw_entropy_src_csrng.1718232508 |
| Short name | T318 |
| Test name | |
| Test status | |
| Simulation time | 7847646168 ps |
| CPU time | 1645.39 seconds |
| Started | Jun 23 08:11:31 PM PDT 24 |
| Finished | Jun 23 08:38:57 PM PDT 24 |
| Peak memory | 607256 kb |
| Host | smart-c8760254-becf-45d2-bd55-346fdc9bad87 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=50_000_000 +rng_srate_value_min=15 +rng_srate_value_max=30 +sw_build_device=sim_dv +sw_images=entropy_src_ csrng_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1718232508 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_entropy_src_csrng.1718232508 |
| Directory | /workspace/2.chip_sw_entropy_src_csrng/latest |
| Test location | /workspace/coverage/default/2.chip_sw_entropy_src_kat_test.1244942178 |
| Short name | T1274 |
| Test name | |
| Test status | |
| Simulation time | 2374648660 ps |
| CPU time | 333.59 seconds |
| Started | Jun 23 08:10:07 PM PDT 24 |
| Finished | Jun 23 08:15:41 PM PDT 24 |
| Peak memory | 607856 kb |
| Host | smart-71abff49-28a1-4038-87e1-50ca015d2030 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=entropy_src_kat_test:1:new_rules,test_rom:0 +cdc_instrumenta tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1244942178 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/ coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_entropy_src_kat_test.1244942178 |
| Directory | /workspace/2.chip_sw_entropy_src_kat_test/latest |
| Test location | /workspace/coverage/default/2.chip_sw_entropy_src_smoketest.3779281745 |
| Short name | T1351 |
| Test name | |
| Test status | |
| Simulation time | 2947612376 ps |
| CPU time | 416.51 seconds |
| Started | Jun 23 08:23:09 PM PDT 24 |
| Finished | Jun 23 08:30:06 PM PDT 24 |
| Peak memory | 607756 kb |
| Host | smart-8d6ff8dc-be4e-485a-bba2-b68137d3069b |
| User | root |
| Command | /workspace/default/simv +rng_srate_value_min=15 +rng_srate_value_max=30 +sw_build_device=sim_dv +sw_images=entropy_src_smoketest:1:new_rules,test_rom: 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand om_seed=3779281745 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_entropy_src_smoketest.3779281745 |
| Directory | /workspace/2.chip_sw_entropy_src_smoketest/latest |
| Test location | /workspace/coverage/default/2.chip_sw_example_concurrency.579863572 |
| Short name | T939 |
| Test name | |
| Test status | |
| Simulation time | 3188002432 ps |
| CPU time | 357.96 seconds |
| Started | Jun 23 08:07:02 PM PDT 24 |
| Finished | Jun 23 08:13:00 PM PDT 24 |
| Peak memory | 606856 kb |
| Host | smart-a1e4c316-e6b8-49e7-bce2-bae7c899a1c9 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=example_concurrency_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=579863572 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_example_concurrency.579863572 |
| Directory | /workspace/2.chip_sw_example_concurrency/latest |
| Test location | /workspace/coverage/default/2.chip_sw_example_flash.392389746 |
| Short name | T1033 |
| Test name | |
| Test status | |
| Simulation time | 3190209032 ps |
| CPU time | 273.92 seconds |
| Started | Jun 23 08:05:18 PM PDT 24 |
| Finished | Jun 23 08:09:52 PM PDT 24 |
| Peak memory | 606812 kb |
| Host | smart-11ee6609-2c46-430d-a64a-6045e2a7e401 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=example_test_from_flash:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=392389746 -assert nopostproc +UVM_TEST NAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_example_flash.392389746 |
| Directory | /workspace/2.chip_sw_example_flash/latest |
| Test location | /workspace/coverage/default/2.chip_sw_example_manufacturer.2992880857 |
| Short name | T277 |
| Test name | |
| Test status | |
| Simulation time | 2846862696 ps |
| CPU time | 213.6 seconds |
| Started | Jun 23 08:06:14 PM PDT 24 |
| Finished | Jun 23 08:09:48 PM PDT 24 |
| Peak memory | 606944 kb |
| Host | smart-406dc31d-c21d-4435-92af-86a16b091860 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=example_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2992880857 -assert nopostproc +UVM_TESTNAME=chip_ base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_example_manufacturer.2992880857 |
| Directory | /workspace/2.chip_sw_example_manufacturer/latest |
| Test location | /workspace/coverage/default/2.chip_sw_example_rom.3512746131 |
| Short name | T1247 |
| Test name | |
| Test status | |
| Simulation time | 2507186210 ps |
| CPU time | 159.18 seconds |
| Started | Jun 23 08:05:54 PM PDT 24 |
| Finished | Jun 23 08:08:34 PM PDT 24 |
| Peak memory | 607004 kb |
| Host | smart-0753d265-0c0f-4d72-81ed-4e36e8a7602b |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:test_in_rom:new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3512746131 -assert nopostproc +UVM_TEST NAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_example_rom.3512746131 |
| Directory | /workspace/2.chip_sw_example_rom/latest |
| Test location | /workspace/coverage/default/2.chip_sw_exit_test_unlocked_bootstrap.2289991546 |
| Short name | T63 |
| Test name | |
| Test status | |
| Simulation time | 57652618122 ps |
| CPU time | 10219.8 seconds |
| Started | Jun 23 08:08:21 PM PDT 24 |
| Finished | Jun 23 10:58:43 PM PDT 24 |
| Peak memory | 623552 kb |
| Host | smart-f6ac8a4a-ee93-4420-b1c3-0d341335f36a |
| User | root |
| Command | /workspace/default/simv +flash_program_latency=5 +sw_test_timeout_ns=150_000_000 +sw_build_device=sim_dv +sw_images=exit_test_unlocked_bootstrap:1:new _rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/s im.tcl +ntb_random_seed=2289991546 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_exit_test_unlocked_bootstrap_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_exit_test_unlocked_bootstrap.2289991546 |
| Directory | /workspace/2.chip_sw_exit_test_unlocked_bootstrap/latest |
| Test location | /workspace/coverage/default/2.chip_sw_flash_crash_alert.425059218 |
| Short name | T1094 |
| Test name | |
| Test status | |
| Simulation time | 5435801650 ps |
| CPU time | 758.22 seconds |
| Started | Jun 23 08:15:04 PM PDT 24 |
| Finished | Jun 23 08:27:43 PM PDT 24 |
| Peak memory | 608808 kb |
| Host | smart-0fe8fc4e-a9b8-4410-a51f-88399ab6b841 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=8_000_000 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1: new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tool s/sim.tcl +ntb_random_seed=425059218 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_flash_host_gnt_err_inj_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_flash_crash_alert.425059218 |
| Directory | /workspace/2.chip_sw_flash_crash_alert/latest |
| Test location | /workspace/coverage/default/2.chip_sw_flash_ctrl_access.2297063076 |
| Short name | T1004 |
| Test name | |
| Test status | |
| Simulation time | 5341149434 ps |
| CPU time | 1062.14 seconds |
| Started | Jun 23 08:09:24 PM PDT 24 |
| Finished | Jun 23 08:27:07 PM PDT 24 |
| Peak memory | 607968 kb |
| Host | smart-6b3247e5-5ab0-449d-bbf7-06d0cafc14fa |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=flash_ctrl_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2297063076 -assert nopostproc +UVM_TESTNAME=ch ip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu ll -cm_name 2.chip_sw_flash_ctrl_access.2297063076 |
| Directory | /workspace/2.chip_sw_flash_ctrl_access/latest |
| Test location | /workspace/coverage/default/2.chip_sw_flash_ctrl_access_jitter_en.1077212491 |
| Short name | T1230 |
| Test name | |
| Test status | |
| Simulation time | 6254168745 ps |
| CPU time | 1200.74 seconds |
| Started | Jun 23 08:07:26 PM PDT 24 |
| Finished | Jun 23 08:27:27 PM PDT 24 |
| Peak memory | 607532 kb |
| Host | smart-2da1836e-3523-4d73-b89e-71b6363f86ae |
| User | root |
| Command | /workspace/default/simv +en_jitter=1 +sw_build_device=sim_dv +sw_images=flash_ctrl_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1077212491 -assert nopostproc +UV M_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -c m_log /dev/null -cm_name 2.chip_sw_flash_ctrl_access_jitter_en.1077212491 |
| Directory | /workspace/2.chip_sw_flash_ctrl_access_jitter_en/latest |
| Test location | /workspace/coverage/default/2.chip_sw_flash_ctrl_access_jitter_en_reduced_freq.1192520752 |
| Short name | T911 |
| Test name | |
| Test status | |
| Simulation time | 7605554645 ps |
| CPU time | 1157.58 seconds |
| Started | Jun 23 08:14:53 PM PDT 24 |
| Finished | Jun 23 08:34:11 PM PDT 24 |
| Peak memory | 606888 kb |
| Host | smart-97401258-7474-4a09-b80f-ee467f377b0a |
| User | root |
| Command | /workspace/default/simv +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=flash_ctrl_test:1:new_rules,test_rom:0 +cdc_instrumentati on_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1192520752 - assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co verage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_flash_ctrl_access_jitter_en_reduced_freq.1192520752 |
| Directory | /workspace/2.chip_sw_flash_ctrl_access_jitter_en_reduced_freq/latest |
| Test location | /workspace/coverage/default/2.chip_sw_flash_ctrl_clock_freqs.1475460033 |
| Short name | T1317 |
| Test name | |
| Test status | |
| Simulation time | 5651561790 ps |
| CPU time | 1225.19 seconds |
| Started | Jun 23 08:07:31 PM PDT 24 |
| Finished | Jun 23 08:27:56 PM PDT 24 |
| Peak memory | 607020 kb |
| Host | smart-833e958f-e49d-4d8e-b32a-800b9a59e525 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=flash_ctrl_clock_freqs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1475460033 -assert nopostproc +UVM _TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm _log /dev/null -cm_name 2.chip_sw_flash_ctrl_clock_freqs.1475460033 |
| Directory | /workspace/2.chip_sw_flash_ctrl_clock_freqs/latest |
| Test location | /workspace/coverage/default/2.chip_sw_flash_ctrl_idle_low_power.1460844961 |
| Short name | T1030 |
| Test name | |
| Test status | |
| Simulation time | 3195358126 ps |
| CPU time | 401.34 seconds |
| Started | Jun 23 08:07:14 PM PDT 24 |
| Finished | Jun 23 08:13:56 PM PDT 24 |
| Peak memory | 607400 kb |
| Host | smart-ac54eda9-4cf3-4b6c-a8cc-73e668bb2dce |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=flash_ctrl_idle_low_power_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1460844961 -assert nopostproc + UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_flash_ctrl_idle_low_power.1460844961 |
| Directory | /workspace/2.chip_sw_flash_ctrl_idle_low_power/latest |
| Test location | /workspace/coverage/default/2.chip_sw_flash_ctrl_lc_rw_en.1829648203 |
| Short name | T232 |
| Test name | |
| Test status | |
| Simulation time | 5167871444 ps |
| CPU time | 446.45 seconds |
| Started | Jun 23 08:09:28 PM PDT 24 |
| Finished | Jun 23 08:16:55 PM PDT 24 |
| Peak memory | 608668 kb |
| Host | smart-438f49c3-0123-438a-82c6-d2a5bcfbdc2b |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=flash_ctrl_lc_rw_en_test:1:new_rules,test_rom:0 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18 29648203 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_flash_ctrl_lc_rw_en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_flash_ctrl_lc_rw_en.1829648203 |
| Directory | /workspace/2.chip_sw_flash_ctrl_lc_rw_en/latest |
| Test location | /workspace/coverage/default/2.chip_sw_flash_ctrl_mem_protection.2379066226 |
| Short name | T1202 |
| Test name | |
| Test status | |
| Simulation time | 5567678490 ps |
| CPU time | 1193.46 seconds |
| Started | Jun 23 08:15:00 PM PDT 24 |
| Finished | Jun 23 08:34:55 PM PDT 24 |
| Peak memory | 607148 kb |
| Host | smart-1f187047-26ed-4e52-a1fc-ce4b33e744c3 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=flash_ctrl_mem_protection_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2379066226 -assert nopostproc + UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_flash_ctrl_mem_protection.2379066226 |
| Directory | /workspace/2.chip_sw_flash_ctrl_mem_protection/latest |
| Test location | /workspace/coverage/default/2.chip_sw_flash_ctrl_ops.1941467730 |
| Short name | T353 |
| Test name | |
| Test status | |
| Simulation time | 3687507448 ps |
| CPU time | 638.38 seconds |
| Started | Jun 23 08:07:23 PM PDT 24 |
| Finished | Jun 23 08:18:02 PM PDT 24 |
| Peak memory | 606940 kb |
| Host | smart-1be9e2f4-8ea7-4aa4-8f8e-8fba58008f89 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=50_000_000 +sw_build_device=sim_dv +sw_images=flash_ctrl_ops_test:1:new_rules,test_rom:0 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1941467730 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/c overage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_flash_ctrl_ops.1941467730 |
| Directory | /workspace/2.chip_sw_flash_ctrl_ops/latest |
| Test location | /workspace/coverage/default/2.chip_sw_flash_ctrl_ops_jitter_en.2864555442 |
| Short name | T340 |
| Test name | |
| Test status | |
| Simulation time | 4581184347 ps |
| CPU time | 694.73 seconds |
| Started | Jun 23 08:08:12 PM PDT 24 |
| Finished | Jun 23 08:19:47 PM PDT 24 |
| Peak memory | 606872 kb |
| Host | smart-78a45a48-a058-4443-b400-f29cb94085f4 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=50_000_000 +en_jitter=1 +sw_build_device=sim_dv +sw_images=flash_ctrl_ops_test:1:new_rules,test_rom:0 +cdc _instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see d=2864555442 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_flash_ctrl_ops_jitter_en.2864555442 |
| Directory | /workspace/2.chip_sw_flash_ctrl_ops_jitter_en/latest |
| Test location | /workspace/coverage/default/2.chip_sw_flash_ctrl_ops_jitter_en_reduced_freq.1687294715 |
| Short name | T330 |
| Test name | |
| Test status | |
| Simulation time | 5049774633 ps |
| CPU time | 696.19 seconds |
| Started | Jun 23 08:14:11 PM PDT 24 |
| Finished | Jun 23 08:25:48 PM PDT 24 |
| Peak memory | 607112 kb |
| Host | smart-65d01092-b257-4d3b-a661-4e21f4fb4244 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=50_000_000 +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=flash_ctrl_ops_test:1:new_ rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si m.tcl +ntb_random_seed=1687294715 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_flash_ctrl_ops_jitter_en_reduced_freq.1687294715 |
| Directory | /workspace/2.chip_sw_flash_ctrl_ops_jitter_en_reduced_freq/latest |
| Test location | /workspace/coverage/default/2.chip_sw_flash_ctrl_write_clear.1399051257 |
| Short name | T1340 |
| Test name | |
| Test status | |
| Simulation time | 3604010312 ps |
| CPU time | 386.1 seconds |
| Started | Jun 23 08:14:26 PM PDT 24 |
| Finished | Jun 23 08:20:52 PM PDT 24 |
| Peak memory | 606872 kb |
| Host | smart-daba39f3-9cd9-4420-8439-9504aea7f00b |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=8_000_000 +sw_build_device=sim_dv +sw_images=flash_ctrl_write_clear_test:1:new_rules,test_rom:0 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1399051 257 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_flash_ctrl_write_clear.1399051257 |
| Directory | /workspace/2.chip_sw_flash_ctrl_write_clear/latest |
| Test location | /workspace/coverage/default/2.chip_sw_flash_init.3349383884 |
| Short name | T1183 |
| Test name | |
| Test status | |
| Simulation time | 21868819304 ps |
| CPU time | 1614.47 seconds |
| Started | Jun 23 08:06:55 PM PDT 24 |
| Finished | Jun 23 08:33:51 PM PDT 24 |
| Peak memory | 612400 kb |
| Host | smart-1cd4cc8d-932e-4d58-9909-538eaa52880b |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=25_000_000 +sw_build_device=sim_dv +sw_images=flash_init_test:0:test_in_rom:new_rules +cdc_instrumentation _enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3349383884 -as sert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_flash_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac e/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_flash_init.3349383884 |
| Directory | /workspace/2.chip_sw_flash_init/latest |
| Test location | /workspace/coverage/default/2.chip_sw_flash_init_reduced_freq.1263603727 |
| Short name | T167 |
| Test name | |
| Test status | |
| Simulation time | 18079278807 ps |
| CPU time | 1563.28 seconds |
| Started | Jun 23 08:13:56 PM PDT 24 |
| Finished | Jun 23 08:40:01 PM PDT 24 |
| Peak memory | 611364 kb |
| Host | smart-0fa63dd2-4824-4bf6-84a6-db42f0abaae7 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=25_000_000 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=flash_init_test:0:test_in_rom:new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=1263603727 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_flash_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_flash_init_reduced_freq.1263603727 |
| Directory | /workspace/2.chip_sw_flash_init_reduced_freq/latest |
| Test location | /workspace/coverage/default/2.chip_sw_flash_scrambling_smoketest.3619141221 |
| Short name | T944 |
| Test name | |
| Test status | |
| Simulation time | 3071243972 ps |
| CPU time | 255.27 seconds |
| Started | Jun 23 08:18:55 PM PDT 24 |
| Finished | Jun 23 08:23:11 PM PDT 24 |
| Peak memory | 608032 kb |
| Host | smart-9d9fdbab-99da-4788-ab46-03a87112f2fd |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=flash_scrambling_smoketest:1:new_rules,flash_scrambling_smoket est_otp_img_rma:4,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=3619141221 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_flash_scrambling_smoketest.3619141221 |
| Directory | /workspace/2.chip_sw_flash_scrambling_smoketest/latest |
| Test location | /workspace/coverage/default/2.chip_sw_gpio.257734246 |
| Short name | T41 |
| Test name | |
| Test status | |
| Simulation time | 3311980370 ps |
| CPU time | 499.79 seconds |
| Started | Jun 23 08:09:14 PM PDT 24 |
| Finished | Jun 23 08:17:35 PM PDT 24 |
| Peak memory | 608020 kb |
| Host | smart-87d4c534-99d8-4320-bcd0-55f914ccbe6d |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=gpio_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=257734246 -assert nopostproc +UVM_TESTNAME=chip_base _test +UVM_TEST_SEQ=chip_sw_gpio_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 2.chip_sw_gpio.257734246 |
| Directory | /workspace/2.chip_sw_gpio/latest |
| Test location | /workspace/coverage/default/2.chip_sw_gpio_smoketest.1117134493 |
| Short name | T1152 |
| Test name | |
| Test status | |
| Simulation time | 2686621212 ps |
| CPU time | 264.5 seconds |
| Started | Jun 23 08:15:45 PM PDT 24 |
| Finished | Jun 23 08:20:10 PM PDT 24 |
| Peak memory | 607992 kb |
| Host | smart-7940280c-a59a-4e82-9a23-65e0069fe270 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=gpio_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1117134493 -assert nopostproc +UVM_TESTNAME=chi p_base_test +UVM_TEST_SEQ=chip_sw_gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 2.chip_sw_gpio_smoketest.1117134493 |
| Directory | /workspace/2.chip_sw_gpio_smoketest/latest |
| Test location | /workspace/coverage/default/2.chip_sw_hmac_enc.3331693523 |
| Short name | T941 |
| Test name | |
| Test status | |
| Simulation time | 3189377572 ps |
| CPU time | 321.37 seconds |
| Started | Jun 23 08:11:17 PM PDT 24 |
| Finished | Jun 23 08:16:39 PM PDT 24 |
| Peak memory | 607828 kb |
| Host | smart-2275737a-d92e-4278-96ef-4d8e63dfc16a |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=hmac_enc_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3331693523 -assert nopostproc +UVM_TESTNAME=chip _base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_hmac_enc.3331693523 |
| Directory | /workspace/2.chip_sw_hmac_enc/latest |
| Test location | /workspace/coverage/default/2.chip_sw_hmac_enc_idle.1889245484 |
| Short name | T1096 |
| Test name | |
| Test status | |
| Simulation time | 2233819288 ps |
| CPU time | 237.08 seconds |
| Started | Jun 23 08:10:57 PM PDT 24 |
| Finished | Jun 23 08:14:55 PM PDT 24 |
| Peak memory | 607820 kb |
| Host | smart-4d513e77-bb6d-492f-881a-896a17899c87 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=hmac_enc_idle_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1889245484 -assert nopostproc +UVM_TESTNAME =chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 2.chip_sw_hmac_enc_idle.1889245484 |
| Directory | /workspace/2.chip_sw_hmac_enc_idle/latest |
| Test location | /workspace/coverage/default/2.chip_sw_hmac_enc_jitter_en.1260934644 |
| Short name | T355 |
| Test name | |
| Test status | |
| Simulation time | 3174261664 ps |
| CPU time | 344.01 seconds |
| Started | Jun 23 08:13:09 PM PDT 24 |
| Finished | Jun 23 08:18:54 PM PDT 24 |
| Peak memory | 606684 kb |
| Host | smart-126bec15-ed5f-413e-a060-592fad1627bd |
| User | root |
| Command | /workspace/default/simv +en_jitter=1 +sw_build_device=sim_dv +sw_images=hmac_enc_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1260934644 -assert nopostproc +UVM_ TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_ log /dev/null -cm_name 2.chip_sw_hmac_enc_jitter_en.1260934644 |
| Directory | /workspace/2.chip_sw_hmac_enc_jitter_en/latest |
| Test location | /workspace/coverage/default/2.chip_sw_hmac_enc_jitter_en_reduced_freq.569569111 |
| Short name | T333 |
| Test name | |
| Test status | |
| Simulation time | 2891269279 ps |
| CPU time | 223.93 seconds |
| Started | Jun 23 08:15:14 PM PDT 24 |
| Finished | Jun 23 08:18:59 PM PDT 24 |
| Peak memory | 606868 kb |
| Host | smart-2cae715e-6cfb-46f0-b007-f39a54b4b588 |
| User | root |
| Command | /workspace/default/simv +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=hmac_enc_test:1:new_rules,test_rom:0 +cdc_instrumentation _enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=569569111 -ass ert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_hmac_enc_jitter_en_reduced_freq.569569111 |
| Directory | /workspace/2.chip_sw_hmac_enc_jitter_en_reduced_freq/latest |
| Test location | /workspace/coverage/default/2.chip_sw_hmac_multistream.3760771446 |
| Short name | T1196 |
| Test name | |
| Test status | |
| Simulation time | 7173195868 ps |
| CPU time | 1371.52 seconds |
| Started | Jun 23 08:11:05 PM PDT 24 |
| Finished | Jun 23 08:33:57 PM PDT 24 |
| Peak memory | 606940 kb |
| Host | smart-fc7b07b5-fb9f-4a1a-bd01-91d1d18af061 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=hmac_multistream_functest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3760771446 -assert nopostproc +UVM_T ESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l og /dev/null -cm_name 2.chip_sw_hmac_multistream.3760771446 |
| Directory | /workspace/2.chip_sw_hmac_multistream/latest |
| Test location | /workspace/coverage/default/2.chip_sw_hmac_oneshot.3828680036 |
| Short name | T969 |
| Test name | |
| Test status | |
| Simulation time | 3380578560 ps |
| CPU time | 369.93 seconds |
| Started | Jun 23 08:11:03 PM PDT 24 |
| Finished | Jun 23 08:17:13 PM PDT 24 |
| Peak memory | 607544 kb |
| Host | smart-0da627ed-828d-43cc-89ec-1b1145cd5163 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=hmac_functest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3828680036 -assert nopostproc +UVM_TESTNAME=chip _base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_hmac_oneshot.3828680036 |
| Directory | /workspace/2.chip_sw_hmac_oneshot/latest |
| Test location | /workspace/coverage/default/2.chip_sw_hmac_smoketest.2767348155 |
| Short name | T968 |
| Test name | |
| Test status | |
| Simulation time | 2809108632 ps |
| CPU time | 379.92 seconds |
| Started | Jun 23 08:16:16 PM PDT 24 |
| Finished | Jun 23 08:22:36 PM PDT 24 |
| Peak memory | 606888 kb |
| Host | smart-c440f946-9ff8-463f-bbf7-df749de91415 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=hmac_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2767348155 -assert nopostproc +UVM_TESTNAME=chi p_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul l -cm_name 2.chip_sw_hmac_smoketest.2767348155 |
| Directory | /workspace/2.chip_sw_hmac_smoketest/latest |
| Test location | /workspace/coverage/default/2.chip_sw_i2c_host_tx_rx.4172496908 |
| Short name | T206 |
| Test name | |
| Test status | |
| Simulation time | 5214445220 ps |
| CPU time | 925.86 seconds |
| Started | Jun 23 08:06:39 PM PDT 24 |
| Finished | Jun 23 08:22:05 PM PDT 24 |
| Peak memory | 608016 kb |
| Host | smart-e2ba2caa-6a80-44f8-8292-112d99a07e7a |
| User | root |
| Command | /workspace/default/simv +i2c_idx=0 +sw_build_device=sim_dv +sw_images=i2c_host_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4172496908 -assert nopostproc + UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_i2c_host_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de fault.vdb -cm_log /dev/null -cm_name 2.chip_sw_i2c_host_tx_rx.4172496908 |
| Directory | /workspace/2.chip_sw_i2c_host_tx_rx/latest |
| Test location | /workspace/coverage/default/2.chip_sw_i2c_host_tx_rx_idx1.796331166 |
| Short name | T211 |
| Test name | |
| Test status | |
| Simulation time | 4530339190 ps |
| CPU time | 762.14 seconds |
| Started | Jun 23 08:07:22 PM PDT 24 |
| Finished | Jun 23 08:20:05 PM PDT 24 |
| Peak memory | 608028 kb |
| Host | smart-7b8bead0-d45d-4b14-a2c5-3472700d1546 |
| User | root |
| Command | /workspace/default/simv +i2c_idx=1 +sw_build_device=sim_dv +sw_images=i2c_host_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=796331166 -assert nopostproc +U VM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_i2c_host_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def ault.vdb -cm_log /dev/null -cm_name 2.chip_sw_i2c_host_tx_rx_idx1.796331166 |
| Directory | /workspace/2.chip_sw_i2c_host_tx_rx_idx1/latest |
| Test location | /workspace/coverage/default/2.chip_sw_i2c_host_tx_rx_idx2.3106357790 |
| Short name | T335 |
| Test name | |
| Test status | |
| Simulation time | 5613912050 ps |
| CPU time | 977.94 seconds |
| Started | Jun 23 08:07:50 PM PDT 24 |
| Finished | Jun 23 08:24:09 PM PDT 24 |
| Peak memory | 608028 kb |
| Host | smart-9e58f72e-9fb9-48c0-aa9e-660cab755f69 |
| User | root |
| Command | /workspace/default/simv +i2c_idx=2 +sw_build_device=sim_dv +sw_images=i2c_host_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3106357790 -assert nopostproc + UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_i2c_host_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de fault.vdb -cm_log /dev/null -cm_name 2.chip_sw_i2c_host_tx_rx_idx2.3106357790 |
| Directory | /workspace/2.chip_sw_i2c_host_tx_rx_idx2/latest |
| Test location | /workspace/coverage/default/2.chip_sw_inject_scramble_seed.1770326238 |
| Short name | T196 |
| Test name | |
| Test status | |
| Simulation time | 65822319996 ps |
| CPU time | 10654.8 seconds |
| Started | Jun 23 08:06:23 PM PDT 24 |
| Finished | Jun 23 11:03:59 PM PDT 24 |
| Peak memory | 616104 kb |
| Host | smart-3f98dc43-6b7a-491c-8464-7e768144282c |
| User | root |
| Command | /workspace/default/simv +lc_at_prod=1 +flash_program_latency=5 +sw_test_timeout_ns=150_000_000 +sw_build_device=sim_dv +sw_images=inject_scramble_seed :1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=1770326238 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_inject_scramble_seed_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_inject_scramble_seed.1770326238 |
| Directory | /workspace/2.chip_sw_inject_scramble_seed/latest |
| Test location | /workspace/coverage/default/2.chip_sw_keymgr_key_derivation.1333456828 |
| Short name | T1087 |
| Test name | |
| Test status | |
| Simulation time | 11303207592 ps |
| CPU time | 2465.78 seconds |
| Started | Jun 23 08:11:16 PM PDT 24 |
| Finished | Jun 23 08:52:23 PM PDT 24 |
| Peak memory | 615440 kb |
| Host | smart-e3da7ef6-a62f-4c31-ba5b-dae221b8750f |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=20_000_000 +sw_build_device=sim_dv +sw_images=keymgr_key_derivation_test:1:new_rules,test_rom:0 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1333 456828 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_keymgr_key_derivation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_keymgr_key_derivation.1333456828 |
| Directory | /workspace/2.chip_sw_keymgr_key_derivation/latest |
| Test location | /workspace/coverage/default/2.chip_sw_keymgr_key_derivation_jitter_en.4011552442 |
| Short name | T1328 |
| Test name | |
| Test status | |
| Simulation time | 12682109762 ps |
| CPU time | 2483.59 seconds |
| Started | Jun 23 08:12:14 PM PDT 24 |
| Finished | Jun 23 08:53:39 PM PDT 24 |
| Peak memory | 615156 kb |
| Host | smart-aa7b344d-f00e-4049-a2dc-623e292f3065 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=20_000_000 +en_jitter=1 +sw_build_device=sim_dv +sw_images=keymgr_key_derivation_test:1:new_rules,test_rom :0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=4011552442 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_keymgr_key_derivation_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_keymgr_key_derivation_jitter_en.4011552442 |
| Directory | /workspace/2.chip_sw_keymgr_key_derivation_jitter_en/latest |
| Test location | /workspace/coverage/default/2.chip_sw_keymgr_key_derivation_jitter_en_reduced_freq.3255765977 |
| Short name | T1133 |
| Test name | |
| Test status | |
| Simulation time | 10402949701 ps |
| CPU time | 1414.18 seconds |
| Started | Jun 23 08:14:47 PM PDT 24 |
| Finished | Jun 23 08:38:22 PM PDT 24 |
| Peak memory | 614128 kb |
| Host | smart-e442381d-c07e-4461-ae05-af656345e0f3 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=20_000_000 +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=keymgr_key_derivation_test :1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=3255765977 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_keymgr_key_derivation_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_keymgr_key_derivation_jitter_en _reduced_freq.3255765977 |
| Directory | /workspace/2.chip_sw_keymgr_key_derivation_jitter_en_reduced_freq/latest |
| Test location | /workspace/coverage/default/2.chip_sw_keymgr_key_derivation_prod.4013690201 |
| Short name | T222 |
| Test name | |
| Test status | |
| Simulation time | 6747933376 ps |
| CPU time | 1379.45 seconds |
| Started | Jun 23 08:11:00 PM PDT 24 |
| Finished | Jun 23 08:33:59 PM PDT 24 |
| Peak memory | 614708 kb |
| Host | smart-d52447b2-0084-476c-89dc-be2a1e870fe7 |
| User | root |
| Command | /workspace/default/simv +lc_at_prod=1 +sw_test_timeout_ns=20_000_000 +sw_build_device=sim_dv +sw_images=keymgr_key_derivation_test:1:new_rules,test_ro m:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=4013690201 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_keymgr_key_derivation_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_keymgr_key_derivation_prod.4013690201 |
| Directory | /workspace/2.chip_sw_keymgr_key_derivation_prod/latest |
| Test location | /workspace/coverage/default/2.chip_sw_keymgr_sideload_aes.3649089419 |
| Short name | T223 |
| Test name | |
| Test status | |
| Simulation time | 12375971716 ps |
| CPU time | 2183.6 seconds |
| Started | Jun 23 08:12:55 PM PDT 24 |
| Finished | Jun 23 08:49:20 PM PDT 24 |
| Peak memory | 608848 kb |
| Host | smart-f356e9a7-6425-4dc5-8d2a-578330cd317f |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=20_000_000 +sw_build_device=sim_dv +sw_images=keymgr_sideload_aes_test:1:new_rules,test_rom:0 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=364908 9419 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_keymgr_sideload_aes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_keymgr_sideload_aes.3649089419 |
| Directory | /workspace/2.chip_sw_keymgr_sideload_aes/latest |
| Test location | /workspace/coverage/default/2.chip_sw_keymgr_sideload_kmac.1562988129 |
| Short name | T1104 |
| Test name | |
| Test status | |
| Simulation time | 7670867080 ps |
| CPU time | 1305.84 seconds |
| Started | Jun 23 08:11:01 PM PDT 24 |
| Finished | Jun 23 08:32:48 PM PDT 24 |
| Peak memory | 608736 kb |
| Host | smart-ea9cf283-7acf-4d44-b4e2-2497e4208430 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=20_000_000 +sw_build_device=sim_dv +sw_images=keymgr_sideload_kmac_test:1:new_rules,test_rom:0 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15629 88129 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_keymgr_sideload_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_keymgr_sideload_kmac.1562988129 |
| Directory | /workspace/2.chip_sw_keymgr_sideload_kmac/latest |
| Test location | /workspace/coverage/default/2.chip_sw_keymgr_sideload_otbn.3852040573 |
| Short name | T228 |
| Test name | |
| Test status | |
| Simulation time | 16552398596 ps |
| CPU time | 3636.35 seconds |
| Started | Jun 23 08:13:17 PM PDT 24 |
| Finished | Jun 23 09:13:54 PM PDT 24 |
| Peak memory | 608852 kb |
| Host | smart-f2a1330c-b24f-4d01-9d37-29a5775eb2c9 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=20_000_000 +sw_build_device=sim_dv +sw_images=keymgr_sideload_otbn_test:1:new_rules,test_rom:0 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38520 40573 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_keymgr_sideload_otbn.3852040573 |
| Directory | /workspace/2.chip_sw_keymgr_sideload_otbn/latest |
| Test location | /workspace/coverage/default/2.chip_sw_kmac_app_rom.2845747875 |
| Short name | T1288 |
| Test name | |
| Test status | |
| Simulation time | 2937361978 ps |
| CPU time | 290.79 seconds |
| Started | Jun 23 08:11:49 PM PDT 24 |
| Finished | Jun 23 08:16:40 PM PDT 24 |
| Peak memory | 607568 kb |
| Host | smart-3dcad63b-490b-415e-9528-51fd6a52fabc |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=kmac_app_rom_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2845747875 -assert nopostproc +UVM_TESTNAME= chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/ null -cm_name 2.chip_sw_kmac_app_rom.2845747875 |
| Directory | /workspace/2.chip_sw_kmac_app_rom/latest |
| Test location | /workspace/coverage/default/2.chip_sw_kmac_entropy.3924086234 |
| Short name | T1063 |
| Test name | |
| Test status | |
| Simulation time | 2624341624 ps |
| CPU time | 317.61 seconds |
| Started | Jun 23 08:07:55 PM PDT 24 |
| Finished | Jun 23 08:13:13 PM PDT 24 |
| Peak memory | 607512 kb |
| Host | smart-3959b311-3c88-4314-9468-d48635033503 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=kmac_entropy_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3924086234 -assert nopostproc +UVM_TESTNAME= chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/ null -cm_name 2.chip_sw_kmac_entropy.3924086234 |
| Directory | /workspace/2.chip_sw_kmac_entropy/latest |
| Test location | /workspace/coverage/default/2.chip_sw_kmac_idle.1979739065 |
| Short name | T915 |
| Test name | |
| Test status | |
| Simulation time | 2887167344 ps |
| CPU time | 254.2 seconds |
| Started | Jun 23 08:11:24 PM PDT 24 |
| Finished | Jun 23 08:15:39 PM PDT 24 |
| Peak memory | 606900 kb |
| Host | smart-09aa74db-1eaf-468e-b468-1b77185ec4cf |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=kmac_idle_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1979739065 -assert nopostproc +UVM_TESTNAME=chi p_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul l -cm_name 2.chip_sw_kmac_idle.1979739065 |
| Directory | /workspace/2.chip_sw_kmac_idle/latest |
| Test location | /workspace/coverage/default/2.chip_sw_kmac_mode_cshake.123089471 |
| Short name | T366 |
| Test name | |
| Test status | |
| Simulation time | 3291938360 ps |
| CPU time | 288.73 seconds |
| Started | Jun 23 08:13:04 PM PDT 24 |
| Finished | Jun 23 08:17:53 PM PDT 24 |
| Peak memory | 607332 kb |
| Host | smart-13282243-5958-42df-a475-f08614283cb7 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=kmac_mode_cshake_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=123089471 -assert nopostproc +UVM_TESTNA ME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 2.chip_sw_kmac_mode_cshake.123089471 |
| Directory | /workspace/2.chip_sw_kmac_mode_cshake/latest |
| Test location | /workspace/coverage/default/2.chip_sw_kmac_mode_kmac.310692781 |
| Short name | T1084 |
| Test name | |
| Test status | |
| Simulation time | 2842118596 ps |
| CPU time | 258.21 seconds |
| Started | Jun 23 08:11:27 PM PDT 24 |
| Finished | Jun 23 08:15:46 PM PDT 24 |
| Peak memory | 607588 kb |
| Host | smart-4525cdcc-610d-46dd-a122-dc37af099426 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=kmac_mode_kmac_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=310692781 -assert nopostproc +UVM_TESTNAME =chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 2.chip_sw_kmac_mode_kmac.310692781 |
| Directory | /workspace/2.chip_sw_kmac_mode_kmac/latest |
| Test location | /workspace/coverage/default/2.chip_sw_kmac_mode_kmac_jitter_en.1233129043 |
| Short name | T1131 |
| Test name | |
| Test status | |
| Simulation time | 2898827930 ps |
| CPU time | 333.74 seconds |
| Started | Jun 23 08:11:08 PM PDT 24 |
| Finished | Jun 23 08:16:43 PM PDT 24 |
| Peak memory | 606444 kb |
| Host | smart-f6cb2a91-e4c5-4564-bb52-9cfb545837dc |
| User | root |
| Command | /workspace/default/simv +en_jitter=1 +sw_build_device=sim_dv +sw_images=kmac_mode_kmac_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1233129043 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd b -cm_log /dev/null -cm_name 2.chip_sw_kmac_mode_kmac_jitter_en.1233129043 |
| Directory | /workspace/2.chip_sw_kmac_mode_kmac_jitter_en/latest |
| Test location | /workspace/coverage/default/2.chip_sw_kmac_mode_kmac_jitter_en_reduced_freq.3888089716 |
| Short name | T970 |
| Test name | |
| Test status | |
| Simulation time | 3085920870 ps |
| CPU time | 288.12 seconds |
| Started | Jun 23 08:14:29 PM PDT 24 |
| Finished | Jun 23 08:19:17 PM PDT 24 |
| Peak memory | 607236 kb |
| Host | smart-7e9e582a-eefc-4fc1-9117-d61d599952b6 |
| User | root |
| Command | /workspace/default/simv +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=kmac_mode_kmac_test:1:new_rules,test_rom:0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38880897 16 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac e/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_kmac_mode_kmac_jitter_en_reduced_freq.3888089716 |
| Directory | /workspace/2.chip_sw_kmac_mode_kmac_jitter_en_reduced_freq/latest |
| Test location | /workspace/coverage/default/2.chip_sw_kmac_smoketest.575877067 |
| Short name | T1146 |
| Test name | |
| Test status | |
| Simulation time | 3112483430 ps |
| CPU time | 257.84 seconds |
| Started | Jun 23 08:15:41 PM PDT 24 |
| Finished | Jun 23 08:19:59 PM PDT 24 |
| Peak memory | 607788 kb |
| Host | smart-b64947e1-aaf4-4d65-9800-537e29cc3fbd |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=kmac_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=575877067 -assert nopostproc +UVM_TESTNAME=chip _base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_kmac_smoketest.575877067 |
| Directory | /workspace/2.chip_sw_kmac_smoketest/latest |
| Test location | /workspace/coverage/default/2.chip_sw_lc_ctrl_otp_hw_cfg0.1306904617 |
| Short name | T1035 |
| Test name | |
| Test status | |
| Simulation time | 3249190240 ps |
| CPU time | 315.1 seconds |
| Started | Jun 23 08:08:41 PM PDT 24 |
| Finished | Jun 23 08:13:57 PM PDT 24 |
| Peak memory | 606924 kb |
| Host | smart-edfd44a7-ddaf-43e8-844d-5000fababa0d |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=lc_ctrl_otp_hw_cfg0_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1306904617 -assert nopostproc +UVM_TE STNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo g /dev/null -cm_name 2.chip_sw_lc_ctrl_otp_hw_cfg0.1306904617 |
| Directory | /workspace/2.chip_sw_lc_ctrl_otp_hw_cfg0/latest |
| Test location | /workspace/coverage/default/2.chip_sw_lc_ctrl_transition.2925730573 |
| Short name | T1298 |
| Test name | |
| Test status | |
| Simulation time | 4345181169 ps |
| CPU time | 382.23 seconds |
| Started | Jun 23 08:09:48 PM PDT 24 |
| Finished | Jun 23 08:16:11 PM PDT 24 |
| Peak memory | 618912 kb |
| Host | smart-d66700e2-7b73-4c0f-ab6c-3a09e4cd23a0 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=lc_ctrl_transition_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2925730573 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_transition_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau lt.vdb -cm_log /dev/null -cm_name 2.chip_sw_lc_ctrl_transition.2925730573 |
| Directory | /workspace/2.chip_sw_lc_ctrl_transition/latest |
| Test location | /workspace/coverage/default/2.chip_sw_lc_ctrl_volatile_raw_unlock.3400755833 |
| Short name | T6 |
| Test name | |
| Test status | |
| Simulation time | 2250959123 ps |
| CPU time | 107.45 seconds |
| Started | Jun 23 08:08:21 PM PDT 24 |
| Finished | Jun 23 08:10:09 PM PDT 24 |
| Peak memory | 614484 kb |
| Host | smart-18d6f18a-2058-4d9d-97e7-0f7178b7f016 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStRaw +exp_volatile_raw_unlock_en=0 +sw_build_device=sim_dv +sw_images=lc_ctrl_volatile_raw_unlock_tes t:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/ tools/sim.tcl +ntb_random_seed=3400755833 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_volatile_raw_unlock_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_lc_ctrl_volatile_raw_unlock.3400755833 |
| Directory | /workspace/2.chip_sw_lc_ctrl_volatile_raw_unlock/latest |
| Test location | /workspace/coverage/default/2.chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz.2936473846 |
| Short name | T1260 |
| Test name | |
| Test status | |
| Simulation time | 2555431395 ps |
| CPU time | 116.5 seconds |
| Started | Jun 23 08:07:21 PM PDT 24 |
| Finished | Jun 23 08:09:18 PM PDT 24 |
| Peak memory | 613564 kb |
| Host | smart-2d4e88ff-79a0-4778-8ea0-648b5d8a0432 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStRaw +chip_clock_source=ChipClockSourceExternal48Mhz +exp_volatile_raw_unlock_en=0 +sw_build_device=s im_dv +sw_images=lc_ctrl_volatile_raw_unlock_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2936473846 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TES T_SEQ=chip_sw_lc_volatile_raw_unlock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz.2936473846 |
| Directory | /workspace/2.chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz/latest |
| Test location | /workspace/coverage/default/2.chip_sw_lc_walkthrough_dev.110332956 |
| Short name | T230 |
| Test name | |
| Test status | |
| Simulation time | 48788066988 ps |
| CPU time | 6258.47 seconds |
| Started | Jun 23 08:09:07 PM PDT 24 |
| Finished | Jun 23 09:53:26 PM PDT 24 |
| Peak memory | 615424 kb |
| Host | smart-35e71904-4d8e-456b-9fe1-accead11fcbc |
| User | root |
| Command | /workspace/default/simv +flash_program_latency=5 +use_otp_image=OtpTypeLcStRaw +dest_dec_state=DecLcStDev +sw_test_timeout_ns=200_000_000 +sw_build_de vice=sim_dv +sw_images=lc_walkthrough_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=110332956 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=ch ip_sw_lc_walkthrough_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_ sw_lc_walkthrough_dev.110332956 |
| Directory | /workspace/2.chip_sw_lc_walkthrough_dev/latest |
| Test location | /workspace/coverage/default/2.chip_sw_lc_walkthrough_prod.3300007096 |
| Short name | T1255 |
| Test name | |
| Test status | |
| Simulation time | 50826212108 ps |
| CPU time | 5544.57 seconds |
| Started | Jun 23 08:08:38 PM PDT 24 |
| Finished | Jun 23 09:41:04 PM PDT 24 |
| Peak memory | 615496 kb |
| Host | smart-139004fb-24a8-48c6-a131-c65a06ee17a1 |
| User | root |
| Command | /workspace/default/simv +flash_program_latency=5 +use_otp_image=OtpTypeLcStRaw +dest_dec_state=DecLcStProd +sw_test_timeout_ns=200_000_000 +sw_build_d evice=sim_dv +sw_images=lc_walkthrough_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3300007096 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ= chip_sw_lc_walkthrough_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chi p_sw_lc_walkthrough_prod.3300007096 |
| Directory | /workspace/2.chip_sw_lc_walkthrough_prod/latest |
| Test location | /workspace/coverage/default/2.chip_sw_lc_walkthrough_prodend.3938685262 |
| Short name | T1109 |
| Test name | |
| Test status | |
| Simulation time | 10247774061 ps |
| CPU time | 729.75 seconds |
| Started | Jun 23 08:07:46 PM PDT 24 |
| Finished | Jun 23 08:19:56 PM PDT 24 |
| Peak memory | 616860 kb |
| Host | smart-b215cffc-d06f-4760-ad8c-33ab3b471b04 |
| User | root |
| Command | /workspace/default/simv +flash_program_latency=5 +use_otp_image=OtpTypeLcStRaw +dest_dec_state=DecLcStProdEnd +sw_build_device=sim_dv +sw_images=lc_wa lkthrough_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3938685262 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_walkthrough_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_lc_walkthrough_prodend.3938685262 |
| Directory | /workspace/2.chip_sw_lc_walkthrough_prodend/latest |
| Test location | /workspace/coverage/default/2.chip_sw_lc_walkthrough_rma.1594812969 |
| Short name | T1268 |
| Test name | |
| Test status | |
| Simulation time | 47432139073 ps |
| CPU time | 5074.07 seconds |
| Started | Jun 23 08:08:00 PM PDT 24 |
| Finished | Jun 23 09:32:36 PM PDT 24 |
| Peak memory | 615504 kb |
| Host | smart-8e9afb6f-8101-4b7e-9428-19ac6c73ff9d |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStRaw +dest_dec_state=DecLcStRma +flash_program_latency=5 +sw_test_timeout_ns=200_000_000 +sw_build_de vice=sim_dv +sw_images=lc_walkthrough_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1594812969 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=c hip_sw_lc_walkthrough_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip _sw_lc_walkthrough_rma.1594812969 |
| Directory | /workspace/2.chip_sw_lc_walkthrough_rma/latest |
| Test location | /workspace/coverage/default/2.chip_sw_lc_walkthrough_testunlocks.672470451 |
| Short name | T165 |
| Test name | |
| Test status | |
| Simulation time | 22816823770 ps |
| CPU time | 1845.43 seconds |
| Started | Jun 23 08:07:59 PM PDT 24 |
| Finished | Jun 23 08:38:45 PM PDT 24 |
| Peak memory | 615284 kb |
| Host | smart-e8f6f870-29d2-47fb-9156-7f794d46feb3 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStRaw +dest_dec_state=DecLcStTestUnlock7 +sw_build_device=sim_dv +sw_images=lc_walkthrough_testunlocks _test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=672470451 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_walkthrough_testunlocks_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_lc_walkthrough_testunl ocks.672470451 |
| Directory | /workspace/2.chip_sw_lc_walkthrough_testunlocks/latest |
| Test location | /workspace/coverage/default/2.chip_sw_otbn_ecdsa_op_irq.3487049386 |
| Short name | T971 |
| Test name | |
| Test status | |
| Simulation time | 17028112050 ps |
| CPU time | 3505.91 seconds |
| Started | Jun 23 08:08:44 PM PDT 24 |
| Finished | Jun 23 09:07:11 PM PDT 24 |
| Peak memory | 608252 kb |
| Host | smart-0455ba99-018a-44e7-81bc-c59465491b8c |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=28_000_000 +rng_srate_value=30 +sw_build_device=sim_dv +sw_images=otbn_ecdsa_op_irq_test:1:new_rules,test_ rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ random_seed=3487049386 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_otbn_ecdsa_op_irq.3487049386 |
| Directory | /workspace/2.chip_sw_otbn_ecdsa_op_irq/latest |
| Test location | /workspace/coverage/default/2.chip_sw_otbn_ecdsa_op_irq_jitter_en.3653559079 |
| Short name | T109 |
| Test name | |
| Test status | |
| Simulation time | 18891018382 ps |
| CPU time | 3358.02 seconds |
| Started | Jun 23 08:08:54 PM PDT 24 |
| Finished | Jun 23 09:04:53 PM PDT 24 |
| Peak memory | 608284 kb |
| Host | smart-54a377db-979e-4138-96d1-035153e5a829 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=33_000_000 +rng_srate_value=30 +en_jitter=1 +sw_build_device=sim_dv +sw_images=otbn_ecdsa_op_irq_test:1:ne w_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/ sim.tcl +ntb_random_seed=3653559079 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tg l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_otbn_ecdsa_op_irq_jitter_en.3653559079 |
| Directory | /workspace/2.chip_sw_otbn_ecdsa_op_irq_jitter_en/latest |
| Test location | /workspace/coverage/default/2.chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq.283953145 |
| Short name | T1249 |
| Test name | |
| Test status | |
| Simulation time | 25008371648 ps |
| CPU time | 3948.51 seconds |
| Started | Jun 23 08:14:50 PM PDT 24 |
| Finished | Jun 23 09:20:40 PM PDT 24 |
| Peak memory | 607280 kb |
| Host | smart-47d6c2c8-ccae-4d10-9e69-734afdb0119e |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=33_000_000 +rng_srate_value=30 +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=otbn_e cdsa_op_irq_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/ repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=283953145 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_otbn_ecdsa_op_irq_jitter_en_reduc ed_freq.283953145 |
| Directory | /workspace/2.chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq/latest |
| Test location | /workspace/coverage/default/2.chip_sw_otbn_mem_scramble.2364594424 |
| Short name | T279 |
| Test name | |
| Test status | |
| Simulation time | 3623066160 ps |
| CPU time | 521.82 seconds |
| Started | Jun 23 08:09:02 PM PDT 24 |
| Finished | Jun 23 08:17:45 PM PDT 24 |
| Peak memory | 607800 kb |
| Host | smart-bcc3023d-b634-41a5-a895-2a6d39745be3 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=15_000_000 +en_scb_tl_err_chk=0 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=otbn _mem_scramble_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2364594424 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_otbn_mem_scramble.2364594424 |
| Directory | /workspace/2.chip_sw_otbn_mem_scramble/latest |
| Test location | /workspace/coverage/default/2.chip_sw_otbn_randomness.2850953147 |
| Short name | T1332 |
| Test name | |
| Test status | |
| Simulation time | 5886795564 ps |
| CPU time | 897.66 seconds |
| Started | Jun 23 08:09:46 PM PDT 24 |
| Finished | Jun 23 08:24:45 PM PDT 24 |
| Peak memory | 607172 kb |
| Host | smart-c0b0935c-b3f6-4bc1-951f-b300aa0b8db3 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +rng_srate_value=30 +sw_build_device=sim_dv +sw_images=otbn_randomness_test:1:new_rules,test_ro m:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=2850953147 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_otbn_randomness.2850953147 |
| Directory | /workspace/2.chip_sw_otbn_randomness/latest |
| Test location | /workspace/coverage/default/2.chip_sw_otbn_smoketest.1460232240 |
| Short name | T1024 |
| Test name | |
| Test status | |
| Simulation time | 6024333008 ps |
| CPU time | 1036.63 seconds |
| Started | Jun 23 08:16:27 PM PDT 24 |
| Finished | Jun 23 08:33:44 PM PDT 24 |
| Peak memory | 607032 kb |
| Host | smart-8ab3e47d-0bd9-4303-99ee-1e64a8186143 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=otbn_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1460232240 -assert nopostproc +UVM_TESTNAME=chi p_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul l -cm_name 2.chip_sw_otbn_smoketest.1460232240 |
| Directory | /workspace/2.chip_sw_otbn_smoketest/latest |
| Test location | /workspace/coverage/default/2.chip_sw_otp_ctrl_ecc_error_vendor_test.3448219224 |
| Short name | T1171 |
| Test name | |
| Test status | |
| Simulation time | 2452628444 ps |
| CPU time | 210.41 seconds |
| Started | Jun 23 08:08:04 PM PDT 24 |
| Finished | Jun 23 08:11:35 PM PDT 24 |
| Peak memory | 607396 kb |
| Host | smart-29bf6f39-4022-4fd2-bc8d-d5cb064cdeea |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=otp_ctrl_vendor_test_ecc_error_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3448219224 -assert nopostp roc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_otp_ctrl_vendor_test_ecc_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_otp_ctrl_ecc_error_vendor_test.3448219224 |
| Directory | /workspace/2.chip_sw_otp_ctrl_ecc_error_vendor_test/latest |
| Test location | /workspace/coverage/default/2.chip_sw_otp_ctrl_lc_signals_dev.260737737 |
| Short name | T1126 |
| Test name | |
| Test status | |
| Simulation time | 8551829800 ps |
| CPU time | 1448.27 seconds |
| Started | Jun 23 08:08:00 PM PDT 24 |
| Finished | Jun 23 08:32:09 PM PDT 24 |
| Peak memory | 607292 kb |
| Host | smart-725c2893-612c-4277-bb1c-7193ab5d9ae7 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStDev +otp_clear_secret2=1 +sw_build_device=sim_dv +sw_images=otp_ctrl_lc_signals_test:1:new_rules,tes t_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +nt b_random_seed=260737737 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_otp_ctrl_lc_signals_dev.260737737 |
| Directory | /workspace/2.chip_sw_otp_ctrl_lc_signals_dev/latest |
| Test location | /workspace/coverage/default/2.chip_sw_otp_ctrl_lc_signals_prod.2998252499 |
| Short name | T372 |
| Test name | |
| Test status | |
| Simulation time | 9178963660 ps |
| CPU time | 1203.06 seconds |
| Started | Jun 23 08:07:06 PM PDT 24 |
| Finished | Jun 23 08:27:09 PM PDT 24 |
| Peak memory | 608008 kb |
| Host | smart-c22c33a6-df53-44e9-a82b-7b610ebfe32a |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStProd +otp_clear_secret2=1 +sw_build_device=sim_dv +sw_images=otp_ctrl_lc_signals_test:1:new_rules,te st_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n tb_random_seed=2998252499 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_otp_ctrl_lc_signals_prod.2998252499 |
| Directory | /workspace/2.chip_sw_otp_ctrl_lc_signals_prod/latest |
| Test location | /workspace/coverage/default/2.chip_sw_otp_ctrl_lc_signals_rma.2044325006 |
| Short name | T997 |
| Test name | |
| Test status | |
| Simulation time | 8847962600 ps |
| CPU time | 1341.09 seconds |
| Started | Jun 23 08:08:39 PM PDT 24 |
| Finished | Jun 23 08:31:00 PM PDT 24 |
| Peak memory | 607280 kb |
| Host | smart-3cb142f1-b421-4b05-9b05-63e50de3fa22 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStRma +otp_clear_secret2=1 +sw_build_device=sim_dv +sw_images=otp_ctrl_lc_signals_test:1:new_rules,tes t_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +nt b_random_seed=2044325006 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_otp_ctrl_lc_signals_rma.2044325006 |
| Directory | /workspace/2.chip_sw_otp_ctrl_lc_signals_rma/latest |
| Test location | /workspace/coverage/default/2.chip_sw_otp_ctrl_lc_signals_test_unlocked0.2677412561 |
| Short name | T1289 |
| Test name | |
| Test status | |
| Simulation time | 3756604056 ps |
| CPU time | 680.98 seconds |
| Started | Jun 23 08:07:27 PM PDT 24 |
| Finished | Jun 23 08:18:49 PM PDT 24 |
| Peak memory | 606844 kb |
| Host | smart-85da5622-a543-4a7b-a9f7-cedb71cab796 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStTestUnlocked0 +otp_clear_secret2=1 +sw_build_device=sim_dv +sw_images=otp_ctrl_lc_signals_test:1:new _rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/s im.tcl +ntb_random_seed=2677412561 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_otp_ctrl_lc_signals_test_unlocked0.2677412561 |
| Directory | /workspace/2.chip_sw_otp_ctrl_lc_signals_test_unlocked0/latest |
| Test location | /workspace/coverage/default/2.chip_sw_otp_ctrl_smoketest.3743163652 |
| Short name | T1151 |
| Test name | |
| Test status | |
| Simulation time | 3111776540 ps |
| CPU time | 322.45 seconds |
| Started | Jun 23 08:15:26 PM PDT 24 |
| Finished | Jun 23 08:20:49 PM PDT 24 |
| Peak memory | 606928 kb |
| Host | smart-f15d4c63-15e7-45d6-9822-b48c10667f14 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=otp_ctrl_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3743163652 -assert nopostproc +UVM_TESTNAME =chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 2.chip_sw_otp_ctrl_smoketest.3743163652 |
| Directory | /workspace/2.chip_sw_otp_ctrl_smoketest/latest |
| Test location | /workspace/coverage/default/2.chip_sw_pattgen_ios.3201966054 |
| Short name | T729 |
| Test name | |
| Test status | |
| Simulation time | 2951596560 ps |
| CPU time | 235.06 seconds |
| Started | Jun 23 08:07:58 PM PDT 24 |
| Finished | Jun 23 08:11:54 PM PDT 24 |
| Peak memory | 608116 kb |
| Host | smart-b4355019-50e1-46c0-aed7-0be503d03805 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=5_000_000 +sw_build_device=sim_dv +sw_images=pattgen_ios_test:1:new_rules,test_rom:0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3201966054 -ass ert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_patt_ios_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/c overage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pattgen_ios.3201966054 |
| Directory | /workspace/2.chip_sw_pattgen_ios/latest |
| Test location | /workspace/coverage/default/2.chip_sw_plic_sw_irq.2378955222 |
| Short name | T243 |
| Test name | |
| Test status | |
| Simulation time | 3459033800 ps |
| CPU time | 330.35 seconds |
| Started | Jun 23 08:11:24 PM PDT 24 |
| Finished | Jun 23 08:16:54 PM PDT 24 |
| Peak memory | 607760 kb |
| Host | smart-3c95bd43-0cbc-4a7d-8922-e502973244a8 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=plic_sw_irq_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2378955222 -assert nopostproc +UVM_TESTNAME=c hip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n ull -cm_name 2.chip_sw_plic_sw_irq.2378955222 |
| Directory | /workspace/2.chip_sw_plic_sw_irq/latest |
| Test location | /workspace/coverage/default/2.chip_sw_power_idle_load.443875803 |
| Short name | T727 |
| Test name | |
| Test status | |
| Simulation time | 4531590704 ps |
| CPU time | 634.58 seconds |
| Started | Jun 23 08:15:09 PM PDT 24 |
| Finished | Jun 23 08:25:44 PM PDT 24 |
| Peak memory | 607340 kb |
| Host | smart-5db03577-87b1-4ce0-a762-78e36fbde53d |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=chip_power_idle_load:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=443875803 -assert nopostproc +UVM_TESTNAM E=chip_base_test +UVM_TEST_SEQ=chip_sw_power_idle_load_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_power_idle_load.443875803 |
| Directory | /workspace/2.chip_sw_power_idle_load/latest |
| Test location | /workspace/coverage/default/2.chip_sw_power_sleep_load.3472829078 |
| Short name | T147 |
| Test name | |
| Test status | |
| Simulation time | 9446751296 ps |
| CPU time | 491.02 seconds |
| Started | Jun 23 08:15:42 PM PDT 24 |
| Finished | Jun 23 08:23:54 PM PDT 24 |
| Peak memory | 607956 kb |
| Host | smart-83dfd7cf-3f97-4a88-a19d-e70f016aca78 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=chip_power_sleep_load:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3472829078 -assert nopostproc +UVM_TESTN AME=chip_base_test +UVM_TEST_SEQ=chip_sw_power_sleep_load_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v db -cm_log /dev/null -cm_name 2.chip_sw_power_sleep_load.3472829078 |
| Directory | /workspace/2.chip_sw_power_sleep_load/latest |
| Test location | /workspace/coverage/default/2.chip_sw_pwrmgr_all_reset_reqs.4247637899 |
| Short name | T1074 |
| Test name | |
| Test status | |
| Simulation time | 11010259469 ps |
| CPU time | 1407.87 seconds |
| Started | Jun 23 08:08:52 PM PDT 24 |
| Finished | Jun 23 08:32:20 PM PDT 24 |
| Peak memory | 609172 kb |
| Host | smart-e9f707ae-a1ba-44e9-926a-9cb753aea554 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=50_000_000 +sw_build_device=sim_dv +sw_images=pwrmgr_all_reset_reqs_test:1:new_rules,test_rom:0 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4247 637899 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_deep_sleep_all_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_all_reset_reqs.4247637899 |
| Directory | /workspace/2.chip_sw_pwrmgr_all_reset_reqs/latest |
| Test location | /workspace/coverage/default/2.chip_sw_pwrmgr_b2b_sleep_reset_req.2347882193 |
| Short name | T1003 |
| Test name | |
| Test status | |
| Simulation time | 21505821824 ps |
| CPU time | 1488.98 seconds |
| Started | Jun 23 08:12:38 PM PDT 24 |
| Finished | Jun 23 08:37:27 PM PDT 24 |
| Peak memory | 608772 kb |
| Host | smart-a75c9362-3aec-4b5c-bd07-e30d26cc6e86 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=35_000_000 +sw_build_device=sim_dv +sw_images=pwrmgr_b2b_sleep_reset_test:1:new_rules,test_rom:0 +cdc_inst rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=234 7882193 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_repeat_reset_wkup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_b2b_sleep_reset_req.2347882193 |
| Directory | /workspace/2.chip_sw_pwrmgr_b2b_sleep_reset_req/latest |
| Test location | /workspace/coverage/default/2.chip_sw_pwrmgr_deep_sleep_all_reset_reqs.4064854950 |
| Short name | T373 |
| Test name | |
| Test status | |
| Simulation time | 16411254300 ps |
| CPU time | 1072.14 seconds |
| Started | Jun 23 08:08:45 PM PDT 24 |
| Finished | Jun 23 08:26:39 PM PDT 24 |
| Peak memory | 609200 kb |
| Host | smart-dc08c09e-9fa5-43ff-a718-4c146c87924d |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=50_000_000 +sw_build_device=sim_dv +sw_images=pwrmgr_deep_sleep_all_reset_reqs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=4064854950 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_deep_sleep_all_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_deep_sleep_all_reset_reqs.4064854950 |
| Directory | /workspace/2.chip_sw_pwrmgr_deep_sleep_all_reset_reqs/latest |
| Test location | /workspace/coverage/default/2.chip_sw_pwrmgr_deep_sleep_all_wake_ups.3029311359 |
| Short name | T411 |
| Test name | |
| Test status | |
| Simulation time | 26687129050 ps |
| CPU time | 1663.72 seconds |
| Started | Jun 23 08:12:57 PM PDT 24 |
| Finished | Jun 23 08:40:42 PM PDT 24 |
| Peak memory | 608740 kb |
| Host | smart-2a1b2d79-033e-4019-ae63-4c1c3a02dcc4 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=pwrmgr_deep_sleep_all_wake_ups:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 3029311359 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_pwrmgr_deep_sleep_all_wake_ups_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_deep_sleep_all_wake_ups.3029311359 |
| Directory | /workspace/2.chip_sw_pwrmgr_deep_sleep_all_wake_ups/latest |
| Test location | /workspace/coverage/default/2.chip_sw_pwrmgr_deep_sleep_por_reset.655660619 |
| Short name | T1135 |
| Test name | |
| Test status | |
| Simulation time | 8361215784 ps |
| CPU time | 840.76 seconds |
| Started | Jun 23 08:08:39 PM PDT 24 |
| Finished | Jun 23 08:22:40 PM PDT 24 |
| Peak memory | 608560 kb |
| Host | smart-123ed630-3375-421b-90ce-9a0744ab551b |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_deep_sleep_por_reset_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=655660619 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sleep_por_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/ default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_deep_sleep_por_reset.655660619 |
| Directory | /workspace/2.chip_sw_pwrmgr_deep_sleep_por_reset/latest |
| Test location | /workspace/coverage/default/2.chip_sw_pwrmgr_deep_sleep_power_glitch_reset.2121403960 |
| Short name | T927 |
| Test name | |
| Test status | |
| Simulation time | 5327127528 ps |
| CPU time | 399.07 seconds |
| Started | Jun 23 08:10:16 PM PDT 24 |
| Finished | Jun 23 08:16:55 PM PDT 24 |
| Peak memory | 613900 kb |
| Host | smart-6880543e-2fc2-413a-bcce-218e03ce491c |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=pwrmgr_deep_sleep_power_glitch_test:1:new_rules,test_rom :0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=2121403960 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_deep_power_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_deep_sleep_power_glitch_reset.2121403960 |
| Directory | /workspace/2.chip_sw_pwrmgr_deep_sleep_power_glitch_reset/latest |
| Test location | /workspace/coverage/default/2.chip_sw_pwrmgr_full_aon_reset.2550857264 |
| Short name | T141 |
| Test name | |
| Test status | |
| Simulation time | 6480817906 ps |
| CPU time | 523.08 seconds |
| Started | Jun 23 08:08:33 PM PDT 24 |
| Finished | Jun 23 08:17:17 PM PDT 24 |
| Peak memory | 608644 kb |
| Host | smart-83e7d946-6849-4454-8874-a9ebe1ef01b6 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=rstmgr_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2550857264 -assert nopostproc +UVM_TESTNAME=c hip_base_test +UVM_TEST_SEQ=chip_sw_full_aon_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_ log /dev/null -cm_name 2.chip_sw_pwrmgr_full_aon_reset.2550857264 |
| Directory | /workspace/2.chip_sw_pwrmgr_full_aon_reset/latest |
| Test location | /workspace/coverage/default/2.chip_sw_pwrmgr_main_power_glitch_reset.3039588061 |
| Short name | T1215 |
| Test name | |
| Test status | |
| Simulation time | 4357866108 ps |
| CPU time | 473.13 seconds |
| Started | Jun 23 08:08:17 PM PDT 24 |
| Finished | Jun 23 08:16:10 PM PDT 24 |
| Peak memory | 614008 kb |
| Host | smart-7af4c042-941c-4e7a-8e46-7d3843cbfc63 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=pwrmgr_main_power_glitch_test:1:new_rules,test_rom:0 +cd c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se ed=3039588061 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_main_power_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_main_power_glitch_reset.3039588061 |
| Directory | /workspace/2.chip_sw_pwrmgr_main_power_glitch_reset/latest |
| Test location | /workspace/coverage/default/2.chip_sw_pwrmgr_normal_sleep_all_reset_reqs.1526375128 |
| Short name | T4 |
| Test name | |
| Test status | |
| Simulation time | 14274652707 ps |
| CPU time | 1544.25 seconds |
| Started | Jun 23 08:08:23 PM PDT 24 |
| Finished | Jun 23 08:34:08 PM PDT 24 |
| Peak memory | 609216 kb |
| Host | smart-f4e0824f-7ac6-4fff-b394-3633cc47aee8 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_normal_sleep_all_reset_reqs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1526375128 -assert nop ostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_deep_sleep_all_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_normal_sleep_all_reset_reqs.1526375128 |
| Directory | /workspace/2.chip_sw_pwrmgr_normal_sleep_all_reset_reqs/latest |
| Test location | /workspace/coverage/default/2.chip_sw_pwrmgr_normal_sleep_all_wake_ups.1368576667 |
| Short name | T96 |
| Test name | |
| Test status | |
| Simulation time | 7930394396 ps |
| CPU time | 530.01 seconds |
| Started | Jun 23 08:13:02 PM PDT 24 |
| Finished | Jun 23 08:21:53 PM PDT 24 |
| Peak memory | 607336 kb |
| Host | smart-203138fd-9fd7-48e7-a106-316a15669309 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_normal_sleep_all_wake_ups:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1368576667 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_pwrmgr_deep_sleep_all_wake_ups_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_normal_sleep_all_wake_ups.1368576667 |
| Directory | /workspace/2.chip_sw_pwrmgr_normal_sleep_all_wake_ups/latest |
| Test location | /workspace/coverage/default/2.chip_sw_pwrmgr_normal_sleep_por_reset.974140250 |
| Short name | T1356 |
| Test name | |
| Test status | |
| Simulation time | 6021730036 ps |
| CPU time | 742.63 seconds |
| Started | Jun 23 08:09:40 PM PDT 24 |
| Finished | Jun 23 08:22:04 PM PDT 24 |
| Peak memory | 608584 kb |
| Host | smart-78e6de4f-1c30-4dc7-b6e4-3624ea5014ec |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_normal_sleep_por_reset_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=974140250 -assert nopostpro c +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sleep_por_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag e/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_normal_sleep_por_reset.974140250 |
| Directory | /workspace/2.chip_sw_pwrmgr_normal_sleep_por_reset/latest |
| Test location | /workspace/coverage/default/2.chip_sw_pwrmgr_random_sleep_all_reset_reqs.3505898334 |
| Short name | T972 |
| Test name | |
| Test status | |
| Simulation time | 24007728243 ps |
| CPU time | 2372.76 seconds |
| Started | Jun 23 08:10:24 PM PDT 24 |
| Finished | Jun 23 08:49:57 PM PDT 24 |
| Peak memory | 608892 kb |
| Host | smart-a19da1e3-aa74-43c2-94a1-8c9191542518 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=50_000_000 +sw_build_device=sim_dv +sw_images=pwrmgr_random_sleep_all_reset_reqs_test:1:new_rules,test_rom :0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=3505898334 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_deep_sleep_all_reset_vseq +en_cov=1 -cm line+cond+fsm+tg l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_random_sleep_all_reset_reqs.3505898334 |
| Directory | /workspace/2.chip_sw_pwrmgr_random_sleep_all_reset_reqs/latest |
| Test location | /workspace/coverage/default/2.chip_sw_pwrmgr_random_sleep_all_wake_ups.4293870131 |
| Short name | T11 |
| Test name | |
| Test status | |
| Simulation time | 21299407688 ps |
| CPU time | 1718.72 seconds |
| Started | Jun 23 08:12:56 PM PDT 24 |
| Finished | Jun 23 08:41:35 PM PDT 24 |
| Peak memory | 608660 kb |
| Host | smart-41755b4b-21a7-43b5-b641-e0dcd18863c1 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +do_random=1 +sw_build_device=sim_dv +sw_images=pwrmgr_random_sleep_all_wake_ups:1:new_rules,te st_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n tb_random_seed=4293870131 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_pwrmgr_deep_sleep_all_wake_ups_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_random_sleep_all_wake_ups.4293870131 |
| Directory | /workspace/2.chip_sw_pwrmgr_random_sleep_all_wake_ups/latest |
| Test location | /workspace/coverage/default/2.chip_sw_pwrmgr_random_sleep_power_glitch_reset.487932865 |
| Short name | T290 |
| Test name | |
| Test status | |
| Simulation time | 30615852294 ps |
| CPU time | 3554.63 seconds |
| Started | Jun 23 08:08:25 PM PDT 24 |
| Finished | Jun 23 09:07:40 PM PDT 24 |
| Peak memory | 609980 kb |
| Host | smart-7d19bc4a-e2f8-498b-a8ef-9403745fc864 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_test_timeout_ns=24_000_000 +sw_build_device=sim_dv +sw_images=pwrmgr_random_sleep_power _glitch_reset_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=487932865 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_random_power_glitc h_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_random_sl eep_power_glitch_reset.487932865 |
| Directory | /workspace/2.chip_sw_pwrmgr_random_sleep_power_glitch_reset/latest |
| Test location | /workspace/coverage/default/2.chip_sw_pwrmgr_sleep_disabled.3865144226 |
| Short name | T713 |
| Test name | |
| Test status | |
| Simulation time | 2977002224 ps |
| CPU time | 238.77 seconds |
| Started | Jun 23 08:14:02 PM PDT 24 |
| Finished | Jun 23 08:18:01 PM PDT 24 |
| Peak memory | 606940 kb |
| Host | smart-7a7a57e3-5948-46f1-b2e9-6c75de22951a |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_sleep_disabled_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3865144226 -assert nopostproc +UVM_ TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_ log /dev/null -cm_name 2.chip_sw_pwrmgr_sleep_disabled.3865144226 |
| Directory | /workspace/2.chip_sw_pwrmgr_sleep_disabled/latest |
| Test location | /workspace/coverage/default/2.chip_sw_pwrmgr_sleep_power_glitch_reset.3320097698 |
| Short name | T967 |
| Test name | |
| Test status | |
| Simulation time | 4071572840 ps |
| CPU time | 383.33 seconds |
| Started | Jun 23 08:10:25 PM PDT 24 |
| Finished | Jun 23 08:16:49 PM PDT 24 |
| Peak memory | 613736 kb |
| Host | smart-3df8a72e-806b-4b99-b790-cb45a851b19f |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=pwrmgr_sleep_power_glitch_test:1:new_rules,test_rom:0 +c dc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_s eed=3320097698 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_main_power_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_sleep_power_glitch_reset.3320097698 |
| Directory | /workspace/2.chip_sw_pwrmgr_sleep_power_glitch_reset/latest |
| Test location | /workspace/coverage/default/2.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup.2667180823 |
| Short name | T125 |
| Test name | |
| Test status | |
| Simulation time | 4837979360 ps |
| CPU time | 488.75 seconds |
| Started | Jun 23 08:11:23 PM PDT 24 |
| Finished | Jun 23 08:19:32 PM PDT 24 |
| Peak memory | 607916 kb |
| Host | smart-d3edda7b-6999-4232-bb83-24f0f3599f47 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=8_000_000 +sw_build_device=sim_dv +sw_images=sensor_ctrl_wakeup_test:1:new_rules,test_rom:0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26671808 23 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac e/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup.2667180823 |
| Directory | /workspace/2.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup/latest |
| Test location | /workspace/coverage/default/2.chip_sw_pwrmgr_sleep_wake_5_bug.513449859 |
| Short name | T1020 |
| Test name | |
| Test status | |
| Simulation time | 6248135782 ps |
| CPU time | 525.27 seconds |
| Started | Jun 23 08:12:30 PM PDT 24 |
| Finished | Jun 23 08:21:16 PM PDT 24 |
| Peak memory | 608312 kb |
| Host | smart-a24a650c-2327-4bc2-8843-62f77af52fd8 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +do_random=1 +sw_build_device=sim_dv +sw_images=pwrmgr_sleep_wake_5_bug_test:1:new_rules,test_r om:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r andom_seed=513449859 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_sleep_wake_5_bug.513449859 |
| Directory | /workspace/2.chip_sw_pwrmgr_sleep_wake_5_bug/latest |
| Test location | /workspace/coverage/default/2.chip_sw_pwrmgr_smoketest.2644289645 |
| Short name | T1227 |
| Test name | |
| Test status | |
| Simulation time | 5043212760 ps |
| CPU time | 455.43 seconds |
| Started | Jun 23 08:24:30 PM PDT 24 |
| Finished | Jun 23 08:32:05 PM PDT 24 |
| Peak memory | 608344 kb |
| Host | smart-40b541af-4700-4028-b84b-11db0a7f2343 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=10000000 +sw_build_device=sim_dv +sw_images=pwrmgr_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2644289645 -asse rt nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera ge/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_smoketest.2644289645 |
| Directory | /workspace/2.chip_sw_pwrmgr_smoketest/latest |
| Test location | /workspace/coverage/default/2.chip_sw_pwrmgr_sysrst_ctrl_reset.1057370979 |
| Short name | T966 |
| Test name | |
| Test status | |
| Simulation time | 5864984677 ps |
| CPU time | 912.03 seconds |
| Started | Jun 23 08:09:13 PM PDT 24 |
| Finished | Jun 23 08:24:25 PM PDT 24 |
| Peak memory | 607960 kb |
| Host | smart-07b8beaf-d1b4-4d93-83d1-ab1803c46485 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_sysrst_ctrl_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1057370979 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_sysrst_ctrl_reset.1057370979 |
| Directory | /workspace/2.chip_sw_pwrmgr_sysrst_ctrl_reset/latest |
| Test location | /workspace/coverage/default/2.chip_sw_pwrmgr_usb_clk_disabled_when_active.1054636685 |
| Short name | T374 |
| Test name | |
| Test status | |
| Simulation time | 5343688472 ps |
| CPU time | 583.53 seconds |
| Started | Jun 23 08:09:47 PM PDT 24 |
| Finished | Jun 23 08:19:31 PM PDT 24 |
| Peak memory | 607128 kb |
| Host | smart-1ac0ba5b-26a9-4868-9eb6-5273a423bb0c |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_usb_clk_disabled_when_active_test:1:new_rules,test_rom:0 +cdc_instrumentation_enable d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1054636685 -assert no postproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de fault.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_usb_clk_disabled_when_active.1054636685 |
| Directory | /workspace/2.chip_sw_pwrmgr_usb_clk_disabled_when_active/latest |
| Test location | /workspace/coverage/default/2.chip_sw_pwrmgr_usbdev_smoketest.1447254384 |
| Short name | T1237 |
| Test name | |
| Test status | |
| Simulation time | 5827617640 ps |
| CPU time | 477.2 seconds |
| Started | Jun 23 08:17:12 PM PDT 24 |
| Finished | Jun 23 08:25:09 PM PDT 24 |
| Peak memory | 607244 kb |
| Host | smart-d6662b0a-3ad0-4746-9e95-9cba97ac1a10 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_usbdev_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1447254384 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_usbdev_smoketest.1447254384 |
| Directory | /workspace/2.chip_sw_pwrmgr_usbdev_smoketest/latest |
| Test location | /workspace/coverage/default/2.chip_sw_pwrmgr_wdog_reset.3782430195 |
| Short name | T976 |
| Test name | |
| Test status | |
| Simulation time | 5258255744 ps |
| CPU time | 543.55 seconds |
| Started | Jun 23 08:10:00 PM PDT 24 |
| Finished | Jun 23 08:19:04 PM PDT 24 |
| Peak memory | 607264 kb |
| Host | smart-7c5157c9-8340-462d-a0e3-c15e0b8867e9 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=pwrmgr_wdog_reset_reqs_test:1:new_rules,test_rom:0 +cdc_inst rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=378 2430195 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_wdog_reset.3782430195 |
| Directory | /workspace/2.chip_sw_pwrmgr_wdog_reset/latest |
| Test location | /workspace/coverage/default/2.chip_sw_rom_ctrl_integrity_check.2212060166 |
| Short name | T265 |
| Test name | |
| Test status | |
| Simulation time | 8389266620 ps |
| CPU time | 597.41 seconds |
| Started | Jun 23 08:12:35 PM PDT 24 |
| Finished | Jun 23 08:22:33 PM PDT 24 |
| Peak memory | 606980 kb |
| Host | smart-38e4bf1e-49d9-4ea8-ba49-075bf63c067e |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=rom_ctrl_integrity_check_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2212060166 -assert nopostproc +U VM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_ctrl_integrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co verage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_rom_ctrl_integrity_check.2212060166 |
| Directory | /workspace/2.chip_sw_rom_ctrl_integrity_check/latest |
| Test location | /workspace/coverage/default/2.chip_sw_rstmgr_cpu_info.3107724480 |
| Short name | T238 |
| Test name | |
| Test status | |
| Simulation time | 7476912080 ps |
| CPU time | 930.11 seconds |
| Started | Jun 23 08:09:19 PM PDT 24 |
| Finished | Jun 23 08:24:50 PM PDT 24 |
| Peak memory | 607200 kb |
| Host | smart-fffa583b-9173-4a01-8757-32fd95d26079 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=rstmgr_cpu_info_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3107724480 -assert nopostproc +UVM_TESTNA ME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 2.chip_sw_rstmgr_cpu_info.3107724480 |
| Directory | /workspace/2.chip_sw_rstmgr_cpu_info/latest |
| Test location | /workspace/coverage/default/2.chip_sw_rstmgr_rst_cnsty_escalation.3750255446 |
| Short name | T1200 |
| Test name | |
| Test status | |
| Simulation time | 5743998072 ps |
| CPU time | 863.96 seconds |
| Started | Jun 23 08:07:01 PM PDT 24 |
| Finished | Jun 23 08:21:26 PM PDT 24 |
| Peak memory | 639588 kb |
| Host | smart-e5179911-2868-4e4c-b3d8-efea0236e13b |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 3750255446 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rstmgr_cnsty_fault_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_rstmgr_rst_cnsty_escalation.3750255446 |
| Directory | /workspace/2.chip_sw_rstmgr_rst_cnsty_escalation/latest |
| Test location | /workspace/coverage/default/2.chip_sw_rstmgr_smoketest.1615411869 |
| Short name | T1338 |
| Test name | |
| Test status | |
| Simulation time | 2575937212 ps |
| CPU time | 256.59 seconds |
| Started | Jun 23 08:26:29 PM PDT 24 |
| Finished | Jun 23 08:31:07 PM PDT 24 |
| Peak memory | 607032 kb |
| Host | smart-fe3de8b7-5a86-4bd7-8d23-1424176b60f7 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=rstmgr_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1615411869 -assert nopostproc +UVM_TESTNAME=c hip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n ull -cm_name 2.chip_sw_rstmgr_smoketest.1615411869 |
| Directory | /workspace/2.chip_sw_rstmgr_smoketest/latest |
| Test location | /workspace/coverage/default/2.chip_sw_rstmgr_sw_req.1853876437 |
| Short name | T1238 |
| Test name | |
| Test status | |
| Simulation time | 3905172952 ps |
| CPU time | 407.48 seconds |
| Started | Jun 23 08:08:21 PM PDT 24 |
| Finished | Jun 23 08:15:09 PM PDT 24 |
| Peak memory | 607788 kb |
| Host | smart-02a20f1d-9ed7-4c0c-a306-2d27ccccd41a |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=rstmgr_sw_req_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1853876437 -assert nopostproc +UVM_TESTNAME =chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 2.chip_sw_rstmgr_sw_req.1853876437 |
| Directory | /workspace/2.chip_sw_rstmgr_sw_req/latest |
| Test location | /workspace/coverage/default/2.chip_sw_rstmgr_sw_rst.740405983 |
| Short name | T381 |
| Test name | |
| Test status | |
| Simulation time | 3186952280 ps |
| CPU time | 278.96 seconds |
| Started | Jun 23 08:08:34 PM PDT 24 |
| Finished | Jun 23 08:13:14 PM PDT 24 |
| Peak memory | 607340 kb |
| Host | smart-5b553d10-f880-4377-adc8-85dd4a1c3237 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=rstmgr_sw_rst_ctrl_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=740405983 -assert nopostproc +UVM_TEST NAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_rstmgr_sw_rst.740405983 |
| Directory | /workspace/2.chip_sw_rstmgr_sw_rst/latest |
| Test location | /workspace/coverage/default/2.chip_sw_rv_core_ibex_icache_invalidate.1597996427 |
| Short name | T294 |
| Test name | |
| Test status | |
| Simulation time | 2589802247 ps |
| CPU time | 187.81 seconds |
| Started | Jun 23 08:14:19 PM PDT 24 |
| Finished | Jun 23 08:17:27 PM PDT 24 |
| Peak memory | 606932 kb |
| Host | smart-aa2e59a7-366f-4333-bc68-e97405c07f11 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=rv_core_ibex_icache_invalidate_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1597996427 -assert nopostp roc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rv_core_ibex_icache_invalidate_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_rv_core_ibex_icache_invalidate.1597996427 |
| Directory | /workspace/2.chip_sw_rv_core_ibex_icache_invalidate/latest |
| Test location | /workspace/coverage/default/2.chip_sw_rv_core_ibex_lockstep_glitch.4088477256 |
| Short name | T386 |
| Test name | |
| Test status | |
| Simulation time | 2341865970 ps |
| CPU time | 150.76 seconds |
| Started | Jun 23 08:14:02 PM PDT 24 |
| Finished | Jun 23 08:16:34 PM PDT 24 |
| Peak memory | 615268 kb |
| Host | smart-c0d55aa7-a743-478e-a42a-778b7153fb1f |
| User | root |
| Command | /workspace/default/simv +disable_assert_final_checks +sw_build_device=sim_dv +sw_images=aes_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4088477256 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rv_core_ibex_lockstep_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_rv_core_ibex_lockstep_glitch.4088477256 |
| Directory | /workspace/2.chip_sw_rv_core_ibex_lockstep_glitch/latest |
| Test location | /workspace/coverage/default/2.chip_sw_rv_core_ibex_nmi_irq.694246588 |
| Short name | T503 |
| Test name | |
| Test status | |
| Simulation time | 5090137050 ps |
| CPU time | 773.34 seconds |
| Started | Jun 23 08:09:45 PM PDT 24 |
| Finished | Jun 23 08:22:39 PM PDT 24 |
| Peak memory | 606900 kb |
| Host | smart-8a194b0b-a11d-4782-89b8-c2fc9ec951dd |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=10_000_000 +sw_build_device=sim_dv +sw_images=rv_core_ibex_nmi_irq_test:1:new_rules,test_rom:0 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69424 6588 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_rv_core_ibex_nmi_irq.694246588 |
| Directory | /workspace/2.chip_sw_rv_core_ibex_nmi_irq/latest |
| Test location | /workspace/coverage/default/2.chip_sw_rv_core_ibex_rnd.238708483 |
| Short name | T1090 |
| Test name | |
| Test status | |
| Simulation time | 5572911448 ps |
| CPU time | 1118.74 seconds |
| Started | Jun 23 08:10:04 PM PDT 24 |
| Finished | Jun 23 08:28:44 PM PDT 24 |
| Peak memory | 607984 kb |
| Host | smart-0336d461-4e9b-4886-b844-5d182197e169 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=20_000_000 +rng_srate_value_max=32 +sw_build_device=sim_dv +sw_images=rv_core_ibex_rnd_test:1:new_rules,te st_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n tb_random_seed=238708483 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_rv_core_ibex_rnd.238708483 |
| Directory | /workspace/2.chip_sw_rv_core_ibex_rnd/latest |
| Test location | /workspace/coverage/default/2.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted.3894366222 |
| Short name | T358 |
| Test name | |
| Test status | |
| Simulation time | 4416841536 ps |
| CPU time | 497.17 seconds |
| Started | Jun 23 08:17:25 PM PDT 24 |
| Finished | Jun 23 08:25:43 PM PDT 24 |
| Peak memory | 615256 kb |
| Host | smart-dc0f814b-f627-4745-9d4e-d7fcc528f349 |
| User | root |
| Command | /workspace/default/simv +use_jtag_dmi=1 +sw_build_device=sim_dv +sw_images=rv_dm_ndm_reset_req_when_cpu_halted_rma:1:new_rules,test_rom:0 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=389436 6222 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rv_dm_ndm_reset_when_cpu_halted_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted.3894366222 |
| Directory | /workspace/2.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted/latest |
| Test location | /workspace/coverage/default/2.chip_sw_rv_plic_smoketest.1172645732 |
| Short name | T413 |
| Test name | |
| Test status | |
| Simulation time | 3028867844 ps |
| CPU time | 267.29 seconds |
| Started | Jun 23 08:16:09 PM PDT 24 |
| Finished | Jun 23 08:20:37 PM PDT 24 |
| Peak memory | 607344 kb |
| Host | smart-b0491a51-14b2-4605-b4d9-d866dccc5b9e |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=rv_plic_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1172645732 -assert nopostproc +UVM_TESTNAME= chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/ null -cm_name 2.chip_sw_rv_plic_smoketest.1172645732 |
| Directory | /workspace/2.chip_sw_rv_plic_smoketest/latest |
| Test location | /workspace/coverage/default/2.chip_sw_rv_timer_irq.2781461198 |
| Short name | T1324 |
| Test name | |
| Test status | |
| Simulation time | 2756011660 ps |
| CPU time | 195.32 seconds |
| Started | Jun 23 08:14:26 PM PDT 24 |
| Finished | Jun 23 08:17:43 PM PDT 24 |
| Peak memory | 607808 kb |
| Host | smart-0d85d9f3-7f8a-4e46-ac86-b1e9d7ff7cbc |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=rv_timer_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2781461198 -assert nopostproc +UVM_TESTNAME =chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 2.chip_sw_rv_timer_irq.2781461198 |
| Directory | /workspace/2.chip_sw_rv_timer_irq/latest |
| Test location | /workspace/coverage/default/2.chip_sw_rv_timer_smoketest.1674761542 |
| Short name | T1315 |
| Test name | |
| Test status | |
| Simulation time | 2780470780 ps |
| CPU time | 323.36 seconds |
| Started | Jun 23 08:17:25 PM PDT 24 |
| Finished | Jun 23 08:22:49 PM PDT 24 |
| Peak memory | 606876 kb |
| Host | smart-7b2a6db0-130f-483f-aab1-01eb1f04d57d |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=rv_timer_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1674761542 -assert nopostproc +UVM_TESTNAME =chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 2.chip_sw_rv_timer_smoketest.1674761542 |
| Directory | /workspace/2.chip_sw_rv_timer_smoketest/latest |
| Test location | /workspace/coverage/default/2.chip_sw_sensor_ctrl_status.1738790061 |
| Short name | T1301 |
| Test name | |
| Test status | |
| Simulation time | 2223113271 ps |
| CPU time | 237.65 seconds |
| Started | Jun 23 08:12:10 PM PDT 24 |
| Finished | Jun 23 08:16:08 PM PDT 24 |
| Peak memory | 608148 kb |
| Host | smart-c1c6201c-7592-4dae-bd67-84c64589dd14 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=40_000_000 +sw_build_device=sim_dv +sw_images=sensor_ctrl_status_test:1:new_rules,test_rom:0 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1738790 061 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sensor_ctrl_status_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_sensor_ctrl_status.1738790061 |
| Directory | /workspace/2.chip_sw_sensor_ctrl_status/latest |
| Test location | /workspace/coverage/default/2.chip_sw_sleep_pin_wake.1332030092 |
| Short name | T15 |
| Test name | |
| Test status | |
| Simulation time | 2885972164 ps |
| CPU time | 218.27 seconds |
| Started | Jun 23 08:06:17 PM PDT 24 |
| Finished | Jun 23 08:09:56 PM PDT 24 |
| Peak memory | 606992 kb |
| Host | smart-e8e7cec7-49ea-4d43-8669-076f00206672 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStProd +sw_build_device=sim_dv +sw_images=sleep_pin_wake_test:1:new_rules,test_rom:0 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1332030092 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sleep_pin_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_sleep_pin_wake.1332030092 |
| Directory | /workspace/2.chip_sw_sleep_pin_wake/latest |
| Test location | /workspace/coverage/default/2.chip_sw_sleep_pwm_pulses.3454600735 |
| Short name | T1188 |
| Test name | |
| Test status | |
| Simulation time | 8801879236 ps |
| CPU time | 1418.21 seconds |
| Started | Jun 23 08:07:32 PM PDT 24 |
| Finished | Jun 23 08:31:11 PM PDT 24 |
| Peak memory | 607508 kb |
| Host | smart-d1c45e67-0a0c-471e-913d-34425387f68e |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=sleep_pwm_pulses_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3454600735 -assert nopostproc +UVM_TESTN AME=chip_base_test +UVM_TEST_SEQ=chip_sw_pwm_pulses_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm _log /dev/null -cm_name 2.chip_sw_sleep_pwm_pulses.3454600735 |
| Directory | /workspace/2.chip_sw_sleep_pwm_pulses/latest |
| Test location | /workspace/coverage/default/2.chip_sw_sleep_sram_ret_contents_no_scramble.879603464 |
| Short name | T922 |
| Test name | |
| Test status | |
| Simulation time | 8094973522 ps |
| CPU time | 961.52 seconds |
| Started | Jun 23 08:12:48 PM PDT 24 |
| Finished | Jun 23 08:28:50 PM PDT 24 |
| Peak memory | 608268 kb |
| Host | smart-53335bda-b8f0-416d-8ff6-d95176312622 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=20_000_000 +en_scb_tl_err_chk=0 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=sram _ctrl_sleep_sram_ret_contents_no_scramble_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=879603464 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SE Q=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_sle ep_sram_ret_contents_no_scramble.879603464 |
| Directory | /workspace/2.chip_sw_sleep_sram_ret_contents_no_scramble/latest |
| Test location | /workspace/coverage/default/2.chip_sw_sleep_sram_ret_contents_scramble.2777742748 |
| Short name | T1201 |
| Test name | |
| Test status | |
| Simulation time | 7535671144 ps |
| CPU time | 811.89 seconds |
| Started | Jun 23 08:12:29 PM PDT 24 |
| Finished | Jun 23 08:26:01 PM PDT 24 |
| Peak memory | 608560 kb |
| Host | smart-14288854-bd83-454e-84f8-c48d8a787513 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=20_000_000 +en_scb_tl_err_chk=0 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=sram _ctrl_sleep_sram_ret_contents_scramble_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2777742748 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ= chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_sleep _sram_ret_contents_scramble.2777742748 |
| Directory | /workspace/2.chip_sw_sleep_sram_ret_contents_scramble/latest |
| Test location | /workspace/coverage/default/2.chip_sw_spi_device_pass_through.3354234175 |
| Short name | T192 |
| Test name | |
| Test status | |
| Simulation time | 7768114023 ps |
| CPU time | 1019.14 seconds |
| Started | Jun 23 08:07:15 PM PDT 24 |
| Finished | Jun 23 08:24:14 PM PDT 24 |
| Peak memory | 624456 kb |
| Host | smart-507f7c6d-c2ff-4887-945f-8a5d08bba997 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=spi_passthrough_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3354234175 -assert nopostproc +UVM_TESTNA ME=chip_base_test +UVM_TEST_SEQ=chip_sw_spi_passthrough_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_spi_device_pass_through.3354234175 |
| Directory | /workspace/2.chip_sw_spi_device_pass_through/latest |
| Test location | /workspace/coverage/default/2.chip_sw_spi_device_pass_through_collision.1454133861 |
| Short name | T28 |
| Test name | |
| Test status | |
| Simulation time | 5174962334 ps |
| CPU time | 576.25 seconds |
| Started | Jun 23 08:09:29 PM PDT 24 |
| Finished | Jun 23 08:19:05 PM PDT 24 |
| Peak memory | 624540 kb |
| Host | smart-e1de977f-d65a-4d13-97ef-32bbf0524a7e |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=spi_passthrough_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1454133861 -assert nopostproc +UVM_TESTNA ME=chip_base_test +UVM_TEST_SEQ=chip_sw_spi_passthrough_collision_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/d efault.vdb -cm_log /dev/null -cm_name 2.chip_sw_spi_device_pass_through_collision.1454133861 |
| Directory | /workspace/2.chip_sw_spi_device_pass_through_collision/latest |
| Test location | /workspace/coverage/default/2.chip_sw_spi_device_tpm.1118319691 |
| Short name | T53 |
| Test name | |
| Test status | |
| Simulation time | 3423147601 ps |
| CPU time | 504.64 seconds |
| Started | Jun 23 08:07:53 PM PDT 24 |
| Finished | Jun 23 08:16:18 PM PDT 24 |
| Peak memory | 616360 kb |
| Host | smart-7dbd77f1-3779-42c1-9095-d19f85176fa6 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=spi_device_tpm_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1118319691 -assert nopostproc +UVM_T ESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_spi_device_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default .vdb -cm_log /dev/null -cm_name 2.chip_sw_spi_device_tpm.1118319691 |
| Directory | /workspace/2.chip_sw_spi_device_tpm/latest |
| Test location | /workspace/coverage/default/2.chip_sw_sram_ctrl_execution_main.3963971877 |
| Short name | T299 |
| Test name | |
| Test status | |
| Simulation time | 8468626253 ps |
| CPU time | 837.43 seconds |
| Started | Jun 23 08:12:15 PM PDT 24 |
| Finished | Jun 23 08:26:13 PM PDT 24 |
| Peak memory | 607460 kb |
| Host | smart-451525f0-8e32-458f-8f88-17448188e6a2 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=sram_ctrl_execution_main_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3963971877 -assert nopostproc +U VM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sram_ctrl_execution_main_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co verage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_sram_ctrl_execution_main.3963971877 |
| Directory | /workspace/2.chip_sw_sram_ctrl_execution_main/latest |
| Test location | /workspace/coverage/default/2.chip_sw_sram_ctrl_scrambled_access.4211725010 |
| Short name | T1358 |
| Test name | |
| Test status | |
| Simulation time | 4490712452 ps |
| CPU time | 683.35 seconds |
| Started | Jun 23 08:12:02 PM PDT 24 |
| Finished | Jun 23 08:23:26 PM PDT 24 |
| Peak memory | 608104 kb |
| Host | smart-1a4c9e8e-56ee-48a5-8ff5-5d0e1a2d92d0 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=12_000_000 +en_scb_tl_err_chk=0 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=sram _ctrl_scrambled_access_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4211725010 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sram_ctr l_scrambled_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw _sram_ctrl_scrambled_access.4211725010 |
| Directory | /workspace/2.chip_sw_sram_ctrl_scrambled_access/latest |
| Test location | /workspace/coverage/default/2.chip_sw_sram_ctrl_scrambled_access_jitter_en.1295573952 |
| Short name | T281 |
| Test name | |
| Test status | |
| Simulation time | 4632370121 ps |
| CPU time | 606.1 seconds |
| Started | Jun 23 08:10:36 PM PDT 24 |
| Finished | Jun 23 08:20:43 PM PDT 24 |
| Peak memory | 608732 kb |
| Host | smart-140e6928-8577-4d58-a056-935081feccde |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=12_000_000 +bypass_alert_ready_to_end_check=1 +en_jitter=1 +en_scb_tl_err_chk=0 +sw_build_device=sim_dv +s w_images=sram_ctrl_scrambled_access_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1295573952 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chi p_sw_sram_ctrl_scrambled_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n ame 2.chip_sw_sram_ctrl_scrambled_access_jitter_en.1295573952 |
| Directory | /workspace/2.chip_sw_sram_ctrl_scrambled_access_jitter_en/latest |
| Test location | /workspace/coverage/default/2.chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq.1616693347 |
| Short name | T282 |
| Test name | |
| Test status | |
| Simulation time | 4868773300 ps |
| CPU time | 530.6 seconds |
| Started | Jun 23 08:14:21 PM PDT 24 |
| Finished | Jun 23 08:23:13 PM PDT 24 |
| Peak memory | 608156 kb |
| Host | smart-094e0303-d1c2-4fac-8e4e-73b36a1c4c76 |
| User | root |
| Command | /workspace/default/simv +mem_sel=main +sw_test_timeout_ns=12_000_000 +bypass_alert_ready_to_end_check=1 +en_jitter=1 +en_scb_tl_err_chk=0 +cal_sys_clk _70mhz=1 +sw_build_device=sim_dv +sw_images=sram_ctrl_scrambled_access_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1616693347 -assert nopostproc +UVM_TESTNA ME=chip_base_test +UVM_TEST_SEQ=chip_sw_sram_ctrl_scrambled_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/ default.vdb -cm_log /dev/null -cm_name 2.chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq.1616693347 |
| Directory | /workspace/2.chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq/latest |
| Test location | /workspace/coverage/default/2.chip_sw_sram_ctrl_smoketest.3254815670 |
| Short name | T1008 |
| Test name | |
| Test status | |
| Simulation time | 2682870358 ps |
| CPU time | 194.61 seconds |
| Started | Jun 23 08:28:06 PM PDT 24 |
| Finished | Jun 23 08:31:51 PM PDT 24 |
| Peak memory | 607124 kb |
| Host | smart-5bd934e3-8c8a-4ca0-953a-95a83f07ce48 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=sram_ctrl_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3254815670 -assert nopostproc +UVM_TESTNAM E=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 2.chip_sw_sram_ctrl_smoketest.3254815670 |
| Directory | /workspace/2.chip_sw_sram_ctrl_smoketest/latest |
| Test location | /workspace/coverage/default/2.chip_sw_sysrst_ctrl_ec_rst_l.1895373363 |
| Short name | T1206 |
| Test name | |
| Test status | |
| Simulation time | 21269963302 ps |
| CPU time | 2838.02 seconds |
| Started | Jun 23 08:08:46 PM PDT 24 |
| Finished | Jun 23 08:56:06 PM PDT 24 |
| Peak memory | 607172 kb |
| Host | smart-8fd32f09-f671-4106-9f70-3a70a3ee1c19 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=sysrst_ctrl_ec_rst_l_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1895373363 -assert nopostproc +UVM_T ESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_ec_rst_l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/d efault.vdb -cm_log /dev/null -cm_name 2.chip_sw_sysrst_ctrl_ec_rst_l.1895373363 |
| Directory | /workspace/2.chip_sw_sysrst_ctrl_ec_rst_l/latest |
| Test location | /workspace/coverage/default/2.chip_sw_sysrst_ctrl_in_irq.2138434576 |
| Short name | T201 |
| Test name | |
| Test status | |
| Simulation time | 4795646371 ps |
| CPU time | 678.38 seconds |
| Started | Jun 23 08:09:32 PM PDT 24 |
| Finished | Jun 23 08:20:52 PM PDT 24 |
| Peak memory | 611808 kb |
| Host | smart-33d7aed6-4e0f-46ee-8411-33b969491c3d |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=sysrst_ctrl_in_irq_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2138434576 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_in_irq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau lt.vdb -cm_log /dev/null -cm_name 2.chip_sw_sysrst_ctrl_in_irq.2138434576 |
| Directory | /workspace/2.chip_sw_sysrst_ctrl_in_irq/latest |
| Test location | /workspace/coverage/default/2.chip_sw_sysrst_ctrl_inputs.1628442142 |
| Short name | T198 |
| Test name | |
| Test status | |
| Simulation time | 3324562695 ps |
| CPU time | 354.06 seconds |
| Started | Jun 23 08:13:34 PM PDT 24 |
| Finished | Jun 23 08:19:30 PM PDT 24 |
| Peak memory | 610920 kb |
| Host | smart-b046f946-96c9-45a6-9d50-a3865cf6a1ca |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=sysrst_ctrl_inputs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1628442142 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_inputs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau lt.vdb -cm_log /dev/null -cm_name 2.chip_sw_sysrst_ctrl_inputs.1628442142 |
| Directory | /workspace/2.chip_sw_sysrst_ctrl_inputs/latest |
| Test location | /workspace/coverage/default/2.chip_sw_sysrst_ctrl_outputs.2608998057 |
| Short name | T1150 |
| Test name | |
| Test status | |
| Simulation time | 2948634672 ps |
| CPU time | 310 seconds |
| Started | Jun 23 08:09:17 PM PDT 24 |
| Finished | Jun 23 08:14:28 PM PDT 24 |
| Peak memory | 607808 kb |
| Host | smart-026a53bf-cca2-43c3-a9a6-0f7cbf33f3e1 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=sysrst_ctrl_outputs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2608998057 -assert nopostproc +UVM_TE STNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_outputs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def ault.vdb -cm_log /dev/null -cm_name 2.chip_sw_sysrst_ctrl_outputs.2608998057 |
| Directory | /workspace/2.chip_sw_sysrst_ctrl_outputs/latest |
| Test location | /workspace/coverage/default/2.chip_sw_sysrst_ctrl_reset.3785956311 |
| Short name | T203 |
| Test name | |
| Test status | |
| Simulation time | 23953671534 ps |
| CPU time | 1906.41 seconds |
| Started | Jun 23 08:10:00 PM PDT 24 |
| Finished | Jun 23 08:41:47 PM PDT 24 |
| Peak memory | 611572 kb |
| Host | smart-7922f92a-bf9d-4782-8b62-b12aca4e04e7 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=36_000_000 +sw_build_device=sim_dv +sw_images=sysrst_ctrl_reset_test:1:new_rules,test_rom:0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37859563 11 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_sysrst_ctrl_reset.3785956311 |
| Directory | /workspace/2.chip_sw_sysrst_ctrl_reset/latest |
| Test location | /workspace/coverage/default/2.chip_sw_sysrst_ctrl_ulp_z3_wakeup.3089351034 |
| Short name | T49 |
| Test name | |
| Test status | |
| Simulation time | 6045398798 ps |
| CPU time | 490.07 seconds |
| Started | Jun 23 08:09:35 PM PDT 24 |
| Finished | Jun 23 08:17:46 PM PDT 24 |
| Peak memory | 607568 kb |
| Host | smart-f6d5276b-5d9f-4eb8-9471-e0aedc76def2 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=sysrst_ctrl_ulp_z3_wakeup_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3089351034 -assert nopostproc + UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_ulp_z3_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/ coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_sysrst_ctrl_ulp_z3_wakeup.3089351034 |
| Directory | /workspace/2.chip_sw_sysrst_ctrl_ulp_z3_wakeup/latest |
| Test location | /workspace/coverage/default/2.chip_sw_uart_rand_baudrate.469416449 |
| Short name | T1102 |
| Test name | |
| Test status | |
| Simulation time | 7514751044 ps |
| CPU time | 1831.06 seconds |
| Started | Jun 23 08:06:05 PM PDT 24 |
| Finished | Jun 23 08:36:36 PM PDT 24 |
| Peak memory | 619492 kb |
| Host | smart-95b331ba-2785-488b-90ca-29653a00bb80 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=469416449 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_uart_rand_baudrate.469416449 |
| Directory | /workspace/2.chip_sw_uart_rand_baudrate/latest |
| Test location | /workspace/coverage/default/2.chip_sw_uart_smoketest.231844481 |
| Short name | T1318 |
| Test name | |
| Test status | |
| Simulation time | 2856523910 ps |
| CPU time | 226.83 seconds |
| Started | Jun 23 08:15:59 PM PDT 24 |
| Finished | Jun 23 08:19:46 PM PDT 24 |
| Peak memory | 609896 kb |
| Host | smart-bc4ff10f-fb2e-4dbc-b04a-fa16318b8c3b |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=uart_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=231844481 -assert nopostproc +UVM_TESTNAME=chip _base_test +UVM_TEST_SEQ=chip_sw_uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 2.chip_sw_uart_smoketest.231844481 |
| Directory | /workspace/2.chip_sw_uart_smoketest/latest |
| Test location | /workspace/coverage/default/2.chip_sw_uart_tx_rx.2552102932 |
| Short name | T334 |
| Test name | |
| Test status | |
| Simulation time | 3425809740 ps |
| CPU time | 620.09 seconds |
| Started | Jun 23 08:06:34 PM PDT 24 |
| Finished | Jun 23 08:16:54 PM PDT 24 |
| Peak memory | 615108 kb |
| Host | smart-8e492bfb-c158-421a-9ccb-de6bc34a56d5 |
| User | root |
| Command | /workspace/default/simv +uart_idx=0 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2552102932 -a ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_uart_tx_rx.2552102932 |
| Directory | /workspace/2.chip_sw_uart_tx_rx/latest |
| Test location | /workspace/coverage/default/2.chip_sw_uart_tx_rx_alt_clk_freq.3144110438 |
| Short name | T31 |
| Test name | |
| Test status | |
| Simulation time | 3849504851 ps |
| CPU time | 762.4 seconds |
| Started | Jun 23 08:07:23 PM PDT 24 |
| Finished | Jun 23 08:20:06 PM PDT 24 |
| Peak memory | 618424 kb |
| Host | smart-09fbf57a-9c74-4f6a-afb5-1415dbd7a6eb |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=80_000_000 +chip_clock_source=ChipClockSourceExternal96Mhz +calibrate_usb_clk=1 +sw_build_device=sim_dv +s w_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3144110438 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_b audrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_uart_tx_rx _alt_clk_freq.3144110438 |
| Directory | /workspace/2.chip_sw_uart_tx_rx_alt_clk_freq/latest |
| Test location | /workspace/coverage/default/2.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.3816266990 |
| Short name | T117 |
| Test name | |
| Test status | |
| Simulation time | 12909920356 ps |
| CPU time | 2011.02 seconds |
| Started | Jun 23 08:06:16 PM PDT 24 |
| Finished | Jun 23 08:39:48 PM PDT 24 |
| Peak memory | 618472 kb |
| Host | smart-510a975a-6efe-48fa-941b-f0c2b5d0133d |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +chip_clock_source=ChipClockSourceExternal48Mhz +sw_build_device=sim_dv +s w_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3816266990 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_b audrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_uart_tx_rx _alt_clk_freq_low_speed.3816266990 |
| Directory | /workspace/2.chip_sw_uart_tx_rx_alt_clk_freq_low_speed/latest |
| Test location | /workspace/coverage/default/2.chip_sw_uart_tx_rx_bootstrap.1404319041 |
| Short name | T195 |
| Test name | |
| Test status | |
| Simulation time | 78918710838 ps |
| CPU time | 12735 seconds |
| Started | Jun 23 08:08:19 PM PDT 24 |
| Finished | Jun 23 11:40:36 PM PDT 24 |
| Peak memory | 636796 kb |
| Host | smart-8af644bc-7a75-41de-a457-b660e61f90aa |
| User | root |
| Command | /workspace/default/simv +use_spi_load_bootstrap=1 +calibrate_usb_clk=1 +test_timeout_ns=160_000_000 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test :1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=1404319041 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_uart_tx_rx_bootstrap.1404319041 |
| Directory | /workspace/2.chip_sw_uart_tx_rx_bootstrap/latest |
| Test location | /workspace/coverage/default/2.chip_sw_uart_tx_rx_idx1.2929776685 |
| Short name | T919 |
| Test name | |
| Test status | |
| Simulation time | 4149679476 ps |
| CPU time | 766.72 seconds |
| Started | Jun 23 08:06:10 PM PDT 24 |
| Finished | Jun 23 08:18:57 PM PDT 24 |
| Peak memory | 613956 kb |
| Host | smart-e03cd1c5-6eff-45e7-8ec4-7451101d0363 |
| User | root |
| Command | /workspace/default/simv +uart_idx=1 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2929776685 -a ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_uart_tx_rx_idx1.2929776685 |
| Directory | /workspace/2.chip_sw_uart_tx_rx_idx1/latest |
| Test location | /workspace/coverage/default/2.chip_sw_uart_tx_rx_idx2.3879024241 |
| Short name | T1309 |
| Test name | |
| Test status | |
| Simulation time | 4521214860 ps |
| CPU time | 693.3 seconds |
| Started | Jun 23 08:05:52 PM PDT 24 |
| Finished | Jun 23 08:17:26 PM PDT 24 |
| Peak memory | 615076 kb |
| Host | smart-1bf88434-6ef8-443f-aeaf-9763ae7e3575 |
| User | root |
| Command | /workspace/default/simv +uart_idx=2 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3879024241 -a ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_uart_tx_rx_idx2.3879024241 |
| Directory | /workspace/2.chip_sw_uart_tx_rx_idx2/latest |
| Test location | /workspace/coverage/default/2.chip_sw_uart_tx_rx_idx3.3509989510 |
| Short name | T949 |
| Test name | |
| Test status | |
| Simulation time | 4602794384 ps |
| CPU time | 803.27 seconds |
| Started | Jun 23 08:06:22 PM PDT 24 |
| Finished | Jun 23 08:19:46 PM PDT 24 |
| Peak memory | 615096 kb |
| Host | smart-92b1d8c3-fb49-4de6-87be-7618de2f2840 |
| User | root |
| Command | /workspace/default/simv +uart_idx=3 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3509989510 -a ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_uart_tx_rx_idx3.3509989510 |
| Directory | /workspace/2.chip_sw_uart_tx_rx_idx3/latest |
| Test location | /workspace/coverage/default/2.chip_tap_straps_dev.2580106971 |
| Short name | T1100 |
| Test name | |
| Test status | |
| Simulation time | 7042326081 ps |
| CPU time | 786.81 seconds |
| Started | Jun 23 08:12:00 PM PDT 24 |
| Finished | Jun 23 08:25:07 PM PDT 24 |
| Peak memory | 620056 kb |
| Host | smart-e9b84dbf-97e6-44d1-9d5e-9d19c8e7d1c5 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStDev +create_jtag_riscv_map=1 +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:test_in_rom: new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=2580106971 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_tap_straps_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_tap_straps_dev.2580106971 |
| Directory | /workspace/2.chip_tap_straps_dev/latest |
| Test location | /workspace/coverage/default/2.chip_tap_straps_prod.1233908845 |
| Short name | T1276 |
| Test name | |
| Test status | |
| Simulation time | 7224186351 ps |
| CPU time | 726.75 seconds |
| Started | Jun 23 08:13:13 PM PDT 24 |
| Finished | Jun 23 08:25:20 PM PDT 24 |
| Peak memory | 620164 kb |
| Host | smart-dd79bb10-17b8-45d8-8554-3b78b03547ed |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStProd +create_jtag_riscv_map=1 +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:test_in_rom :new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1233908845 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_tap_straps_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_tap_straps_prod.1233908845 |
| Directory | /workspace/2.chip_tap_straps_prod/latest |
| Test location | /workspace/coverage/default/2.chip_tap_straps_rma.1407286602 |
| Short name | T1293 |
| Test name | |
| Test status | |
| Simulation time | 5807204454 ps |
| CPU time | 617.86 seconds |
| Started | Jun 23 08:12:11 PM PDT 24 |
| Finished | Jun 23 08:22:29 PM PDT 24 |
| Peak memory | 622300 kb |
| Host | smart-0c9cf62b-6ff3-466f-9985-13d4ef86db1f |
| User | root |
| Command | /workspace/default/simv +create_jtag_riscv_map=1 +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:test_in_rom:new_rules +cdc_instrumentation _enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1407286602 -as sert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_tap_straps_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/c overage/default.vdb -cm_log /dev/null -cm_name 2.chip_tap_straps_rma.1407286602 |
| Directory | /workspace/2.chip_tap_straps_rma/latest |
| Test location | /workspace/coverage/default/2.chip_tap_straps_testunlock0.3920971997 |
| Short name | T1248 |
| Test name | |
| Test status | |
| Simulation time | 7708867416 ps |
| CPU time | 659.05 seconds |
| Started | Jun 23 08:13:25 PM PDT 24 |
| Finished | Jun 23 08:24:24 PM PDT 24 |
| Peak memory | 620212 kb |
| Host | smart-d2c72ab9-6f5b-48c6-8fb3-dfbbbd4f2443 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStTestUnlocked0 +create_jtag_riscv_map=1 +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:te st_in_rom:new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3920971997 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_tap_straps_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_tap_straps_testunlock0.3920971997 |
| Directory | /workspace/2.chip_tap_straps_testunlock0/latest |
| Test location | /workspace/coverage/default/2.rom_e2e_asm_init_dev.3484718716 |
| Short name | T1061 |
| Test name | |
| Test status | |
| Simulation time | 15828817113 ps |
| CPU time | 3148.38 seconds |
| Started | Jun 23 08:28:22 PM PDT 24 |
| Finished | Jun 23 09:21:21 PM PDT 24 |
| Peak memory | 608456 kb |
| Host | smart-54740288-6d8b-474b-90df-997f912bff8e |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeCustom +sw_test_timeout_ns=20000000 +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_prod _key_0:1:ot_flash_binary,otp_img_e2e_bootstrap_entry_dev:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3484718716 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_S EQ=chip_sw_rom_e2e_asm_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_e2e_asm_init_dev.3484718716 |
| Directory | /workspace/2.rom_e2e_asm_init_dev/latest |
| Test location | /workspace/coverage/default/2.rom_e2e_asm_init_prod.2150519360 |
| Short name | T1256 |
| Test name | |
| Test status | |
| Simulation time | 15952976855 ps |
| CPU time | 3870.82 seconds |
| Started | Jun 23 08:21:44 PM PDT 24 |
| Finished | Jun 23 09:26:15 PM PDT 24 |
| Peak memory | 608292 kb |
| Host | smart-b619d49d-f375-469c-a408-501c40a4bc1c |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeCustom +sw_test_timeout_ns=20000000 +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_prod _key_0:1:ot_flash_binary,otp_img_e2e_bootstrap_entry_prod:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2150519360 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_ SEQ=chip_sw_rom_e2e_asm_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_e2e_asm_init_prod.2150519360 |
| Directory | /workspace/2.rom_e2e_asm_init_prod/latest |
| Test location | /workspace/coverage/default/2.rom_e2e_asm_init_prod_end.632831929 |
| Short name | T1277 |
| Test name | |
| Test status | |
| Simulation time | 15968920636 ps |
| CPU time | 4404.85 seconds |
| Started | Jun 23 08:21:55 PM PDT 24 |
| Finished | Jun 23 09:35:20 PM PDT 24 |
| Peak memory | 608288 kb |
| Host | smart-053c8adf-da38-4953-8d38-f07152257987 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeCustom +sw_test_timeout_ns=20000000 +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_prod _key_0:1:ot_flash_binary,otp_img_e2e_bootstrap_entry_prod_end:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=632831929 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TE ST_SEQ=chip_sw_rom_e2e_asm_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n ame 2.rom_e2e_asm_init_prod_end.632831929 |
| Directory | /workspace/2.rom_e2e_asm_init_prod_end/latest |
| Test location | /workspace/coverage/default/2.rom_e2e_asm_init_rma.2918190395 |
| Short name | T92 |
| Test name | |
| Test status | |
| Simulation time | 15356787802 ps |
| CPU time | 3576.65 seconds |
| Started | Jun 23 08:19:06 PM PDT 24 |
| Finished | Jun 23 09:18:43 PM PDT 24 |
| Peak memory | 608288 kb |
| Host | smart-ff87f63b-12cd-4108-bbd2-186fd804a357 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeCustom +sw_test_timeout_ns=20000000 +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_prod _key_0:1:ot_flash_binary,otp_img_e2e_bootstrap_entry_rma:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2918190395 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_S EQ=chip_sw_rom_e2e_asm_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_e2e_asm_init_rma.2918190395 |
| Directory | /workspace/2.rom_e2e_asm_init_rma/latest |
| Test location | /workspace/coverage/default/2.rom_e2e_asm_init_test_unlocked0.783626711 |
| Short name | T1047 |
| Test name | |
| Test status | |
| Simulation time | 12148922642 ps |
| CPU time | 3099.09 seconds |
| Started | Jun 23 08:18:00 PM PDT 24 |
| Finished | Jun 23 09:09:40 PM PDT 24 |
| Peak memory | 608296 kb |
| Host | smart-504c14d3-8b9c-48fd-b407-85f89dbec175 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeCustom +sw_test_timeout_ns=410_000_000 +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_p rod_key_0:1:ot_flash_binary,otp_img_e2e_bootstrap_entry_test_unlocked0:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY =UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=783626711 -assert nopostproc +UVM_TESTNAME=chip_base_tes t +UVM_TEST_SEQ=chip_sw_rom_e2e_asm_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n ull -cm_name 2.rom_e2e_asm_init_test_unlocked0.783626711 |
| Directory | /workspace/2.rom_e2e_asm_init_test_unlocked0/latest |
| Test location | /workspace/coverage/default/2.rom_e2e_keymgr_init_rom_ext_meas.306319944 |
| Short name | T1013 |
| Test name | |
| Test status | |
| Simulation time | 15631964120 ps |
| CPU time | 3126.33 seconds |
| Started | Jun 23 08:20:17 PM PDT 24 |
| Finished | Jun 23 09:12:24 PM PDT 24 |
| Peak memory | 608164 kb |
| Host | smart-5690066f-9f1b-43a4-a056-f86efb17ec13 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=40_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=rom_e2e_keymgr_init_otp_meas:1: new_rules,otp_img_keymgr_otp_meas:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=306319944 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_e2e_keymgr_init_rom_ext_meas.306319944 |
| Directory | /workspace/2.rom_e2e_keymgr_init_rom_ext_meas/latest |
| Test location | /workspace/coverage/default/2.rom_e2e_keymgr_init_rom_ext_no_meas.1119396396 |
| Short name | T696 |
| Test name | |
| Test status | |
| Simulation time | 15238348296 ps |
| CPU time | 3322 seconds |
| Started | Jun 23 08:20:51 PM PDT 24 |
| Finished | Jun 23 09:16:14 PM PDT 24 |
| Peak memory | 608148 kb |
| Host | smart-f55f03de-220c-4d25-a562-be53ed40dfa0 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=40_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=rom_e2e_keymgr_init_otp_no_meas :1:new_rules,otp_img_keymgr_otp_no_meas:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1119396396 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_e2e_keymgr_init_rom_ext _no_meas.1119396396 |
| Directory | /workspace/2.rom_e2e_keymgr_init_rom_ext_no_meas/latest |
| Test location | /workspace/coverage/default/2.rom_e2e_smoke.1014710416 |
| Short name | T55 |
| Test name | |
| Test status | |
| Simulation time | 15818869432 ps |
| CPU time | 3656.77 seconds |
| Started | Jun 23 08:20:36 PM PDT 24 |
| Finished | Jun 23 09:21:34 PM PDT 24 |
| Peak memory | 608080 kb |
| Host | smart-96de2bc9-29ca-45f8-8487-4facf7571c56 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=40000000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=rom_e2e_smoke:1:new_rules,otp_img _secret2_locked_rma:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_to p/hw/dv/tools/sim.tcl +ntb_random_seed=1014710416 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_e2e_smoke.1014710416 |
| Directory | /workspace/2.rom_e2e_smoke/latest |
| Test location | /workspace/coverage/default/2.rom_e2e_static_critical.1217354549 |
| Short name | T985 |
| Test name | |
| Test status | |
| Simulation time | 17319659910 ps |
| CPU time | 3721.27 seconds |
| Started | Jun 23 08:19:55 PM PDT 24 |
| Finished | Jun 23 09:21:57 PM PDT 24 |
| Peak memory | 608100 kb |
| Host | smart-9f46aea3-7bec-4fb1-a784-b7d770658eda |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=40000000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=rom_e2e_static_critical:1:new_rul es,otp_img_secret2_locked_rma:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1217354549 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_e2e_static_critical.1217354549 |
| Directory | /workspace/2.rom_e2e_static_critical/latest |
| Test location | /workspace/coverage/default/2.rom_keymgr_functest.1981183193 |
| Short name | T1015 |
| Test name | |
| Test status | |
| Simulation time | 4157855400 ps |
| CPU time | 474.53 seconds |
| Started | Jun 23 08:14:54 PM PDT 24 |
| Finished | Jun 23 08:22:49 PM PDT 24 |
| Peak memory | 607056 kb |
| Host | smart-7c054633-7942-4563-af19-a4f0ccae1a8b |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=10_000_000 +sw_build_device=sim_dv +sw_images=keymgr_functest:1:new_rules,test_rom:0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1981183193 -ass ert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 2.rom_keymgr_functest.1981183193 |
| Directory | /workspace/2.rom_keymgr_functest/latest |
| Test location | /workspace/coverage/default/2.rom_volatile_raw_unlock.1220820237 |
| Short name | T1320 |
| Test name | |
| Test status | |
| Simulation time | 2269089559 ps |
| CPU time | 101.21 seconds |
| Started | Jun 23 08:15:30 PM PDT 24 |
| Finished | Jun 23 08:17:12 PM PDT 24 |
| Peak memory | 613548 kb |
| Host | smart-35ae7f3f-7595-44b9-8530-eb0f0df7b8c8 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=200_000_000 +use_otp_image=OtpTypeLcStRaw +chip_clock_source=ChipClockSourceExternal48Mhz +rom_prod_mode=1 +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_test_key_0:1:ot_flash_binary,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1220820237 -assert nopostproc +UVM_ TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_volatile_raw_unlock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag e/default.vdb -cm_log /dev/null -cm_name 2.rom_volatile_raw_unlock.1220820237 |
| Directory | /workspace/2.rom_volatile_raw_unlock/latest |
| Test location | /workspace/coverage/default/23.chip_sw_all_escalation_resets.4029105751 |
| Short name | T412 |
| Test name | |
| Test status | |
| Simulation time | 6129843280 ps |
| CPU time | 522.31 seconds |
| Started | Jun 23 08:20:59 PM PDT 24 |
| Finished | Jun 23 08:29:42 PM PDT 24 |
| Peak memory | 648144 kb |
| Host | smart-d32c1cce-44d4-4691-b281-5a60544b9ba2 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 4029105751 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.chip_sw_all_escalation_resets.4029105751 |
| Directory | /workspace/23.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/25.chip_sw_alert_handler_lpg_sleep_mode_alerts.163189696 |
| Short name | T797 |
| Test name | |
| Test status | |
| Simulation time | 4159059800 ps |
| CPU time | 438.98 seconds |
| Started | Jun 23 08:22:15 PM PDT 24 |
| Finished | Jun 23 08:29:34 PM PDT 24 |
| Peak memory | 647244 kb |
| Host | smart-e5999f9d-d849-472e-8723-b83da3f9a3ac |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=163189696 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all _escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.chip_s w_alert_handler_lpg_sleep_mode_alerts.163189696 |
| Directory | /workspace/25.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/26.chip_sw_all_escalation_resets.2770000037 |
| Short name | T1343 |
| Test name | |
| Test status | |
| Simulation time | 6029675948 ps |
| CPU time | 693.8 seconds |
| Started | Jun 23 08:21:26 PM PDT 24 |
| Finished | Jun 23 08:33:00 PM PDT 24 |
| Peak memory | 648368 kb |
| Host | smart-9ebefc1f-5f8d-41f4-a28e-a109e3fe6dbb |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 2770000037 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.chip_sw_all_escalation_resets.2770000037 |
| Directory | /workspace/26.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/3.chip_sw_alert_handler_lpg_sleep_mode_alerts.1588080640 |
| Short name | T1199 |
| Test name | |
| Test status | |
| Simulation time | 4136991336 ps |
| CPU time | 431.22 seconds |
| Started | Jun 23 08:17:06 PM PDT 24 |
| Finished | Jun 23 08:24:18 PM PDT 24 |
| Peak memory | 642552 kb |
| Host | smart-89fd64c3-b011-4d6b-9a57-3c0b985bbf2b |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1588080640 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.chip_s w_alert_handler_lpg_sleep_mode_alerts.1588080640 |
| Directory | /workspace/3.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/3.chip_sw_aon_timer_sleep_wdog_sleep_pause.1980230045 |
| Short name | T1269 |
| Test name | |
| Test status | |
| Simulation time | 6456696930 ps |
| CPU time | 584.98 seconds |
| Started | Jun 23 08:17:01 PM PDT 24 |
| Finished | Jun 23 08:26:46 PM PDT 24 |
| Peak memory | 608404 kb |
| Host | smart-6245755c-101f-4d49-b12b-705c92eb6590 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=aon_timer_sleep_wdog_sleep_pause_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=1980230045 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.chip_sw_aon_timer_sleep_wdog_sleep_pause.1980230045 |
| Directory | /workspace/3.chip_sw_aon_timer_sleep_wdog_sleep_pause/latest |
| Test location | /workspace/coverage/default/3.chip_sw_data_integrity_escalation.491994942 |
| Short name | T280 |
| Test name | |
| Test status | |
| Simulation time | 5774841976 ps |
| CPU time | 484.76 seconds |
| Started | Jun 23 08:27:49 PM PDT 24 |
| Finished | Jun 23 08:36:27 PM PDT 24 |
| Peak memory | 608972 kb |
| Host | smart-a7ced398-26e0-4f27-976a-0cf0dbf46ff5 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=data_integrity_escalation_reset_test:1:new_rules,test_ro m:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=491994942 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_data_integrity_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.chip_sw_data_integrity_escalation.491994942 |
| Directory | /workspace/3.chip_sw_data_integrity_escalation/latest |
| Test location | /workspace/coverage/default/3.chip_sw_lc_ctrl_transition.1917991305 |
| Short name | T1022 |
| Test name | |
| Test status | |
| Simulation time | 6086828115 ps |
| CPU time | 516.27 seconds |
| Started | Jun 23 08:18:40 PM PDT 24 |
| Finished | Jun 23 08:27:18 PM PDT 24 |
| Peak memory | 619948 kb |
| Host | smart-92043ecb-d83d-4cde-8896-c53289f5e413 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=lc_ctrl_transition_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1917991305 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_transition_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau lt.vdb -cm_log /dev/null -cm_name 3.chip_sw_lc_ctrl_transition.1917991305 |
| Directory | /workspace/3.chip_sw_lc_ctrl_transition/latest |
| Test location | /workspace/coverage/default/3.chip_sw_uart_rand_baudrate.3055447329 |
| Short name | T1323 |
| Test name | |
| Test status | |
| Simulation time | 8260154946 ps |
| CPU time | 1350.24 seconds |
| Started | Jun 23 08:19:09 PM PDT 24 |
| Finished | Jun 23 08:41:41 PM PDT 24 |
| Peak memory | 619384 kb |
| Host | smart-06d92c9f-7fbe-4e73-bd9d-d965cfcc0f9b |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=3055447329 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.chip_sw_uart_rand_baudrate.3055447329 |
| Directory | /workspace/3.chip_sw_uart_rand_baudrate/latest |
| Test location | /workspace/coverage/default/3.chip_sw_uart_tx_rx.1072528442 |
| Short name | T1073 |
| Test name | |
| Test status | |
| Simulation time | 3784061446 ps |
| CPU time | 406.23 seconds |
| Started | Jun 23 08:27:07 PM PDT 24 |
| Finished | Jun 23 08:34:26 PM PDT 24 |
| Peak memory | 615272 kb |
| Host | smart-18f94a7f-a2c4-4133-b248-415fd351c9eb |
| User | root |
| Command | /workspace/default/simv +uart_idx=0 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1072528442 -a ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/default.vdb -cm_log /dev/null -cm_name 3.chip_sw_uart_tx_rx.1072528442 |
| Directory | /workspace/3.chip_sw_uart_tx_rx/latest |
| Test location | /workspace/coverage/default/3.chip_sw_uart_tx_rx_alt_clk_freq.91167136 |
| Short name | T988 |
| Test name | |
| Test status | |
| Simulation time | 4158195870 ps |
| CPU time | 620.27 seconds |
| Started | Jun 23 08:18:05 PM PDT 24 |
| Finished | Jun 23 08:28:26 PM PDT 24 |
| Peak memory | 618420 kb |
| Host | smart-eb6cd663-26cc-468a-b8e1-aecda7e01127 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=80_000_000 +chip_clock_source=ChipClockSourceExternal96Mhz +calibrate_usb_clk=1 +sw_build_device=sim_dv +s w_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=91167136 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_bau drate_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.chip_sw_uart_tx_rx_a lt_clk_freq.91167136 |
| Directory | /workspace/3.chip_sw_uart_tx_rx_alt_clk_freq/latest |
| Test location | /workspace/coverage/default/3.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.2743926190 |
| Short name | T1167 |
| Test name | |
| Test status | |
| Simulation time | 8810737062 ps |
| CPU time | 1186.29 seconds |
| Started | Jun 23 08:17:25 PM PDT 24 |
| Finished | Jun 23 08:37:12 PM PDT 24 |
| Peak memory | 623304 kb |
| Host | smart-89914422-2111-41b2-b083-6f244bdc35d9 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +chip_clock_source=ChipClockSourceExternal48Mhz +sw_build_device=sim_dv +s w_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2743926190 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_b audrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.chip_sw_uart_tx_rx _alt_clk_freq_low_speed.2743926190 |
| Directory | /workspace/3.chip_sw_uart_tx_rx_alt_clk_freq_low_speed/latest |
| Test location | /workspace/coverage/default/3.chip_sw_uart_tx_rx_idx1.4024449169 |
| Short name | T1184 |
| Test name | |
| Test status | |
| Simulation time | 4921713028 ps |
| CPU time | 466.48 seconds |
| Started | Jun 23 08:28:19 PM PDT 24 |
| Finished | Jun 23 08:36:35 PM PDT 24 |
| Peak memory | 615276 kb |
| Host | smart-b0d376d9-4161-47bd-8c00-1c0763878d28 |
| User | root |
| Command | /workspace/default/simv +uart_idx=1 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4024449169 -a ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/default.vdb -cm_log /dev/null -cm_name 3.chip_sw_uart_tx_rx_idx1.4024449169 |
| Directory | /workspace/3.chip_sw_uart_tx_rx_idx1/latest |
| Test location | /workspace/coverage/default/3.chip_sw_uart_tx_rx_idx2.2057581421 |
| Short name | T146 |
| Test name | |
| Test status | |
| Simulation time | 4556576452 ps |
| CPU time | 830.75 seconds |
| Started | Jun 23 08:16:48 PM PDT 24 |
| Finished | Jun 23 08:30:40 PM PDT 24 |
| Peak memory | 615096 kb |
| Host | smart-fa012a95-fe39-406c-bea0-30ad192159b1 |
| User | root |
| Command | /workspace/default/simv +uart_idx=2 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2057581421 -a ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/default.vdb -cm_log /dev/null -cm_name 3.chip_sw_uart_tx_rx_idx2.2057581421 |
| Directory | /workspace/3.chip_sw_uart_tx_rx_idx2/latest |
| Test location | /workspace/coverage/default/3.chip_sw_uart_tx_rx_idx3.633337308 |
| Short name | T91 |
| Test name | |
| Test status | |
| Simulation time | 3633238998 ps |
| CPU time | 484.51 seconds |
| Started | Jun 23 08:17:13 PM PDT 24 |
| Finished | Jun 23 08:25:18 PM PDT 24 |
| Peak memory | 614020 kb |
| Host | smart-60b18e52-34b3-4625-9306-88fbdeeed61d |
| User | root |
| Command | /workspace/default/simv +uart_idx=3 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=633337308 -as sert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac e/coverage/default.vdb -cm_log /dev/null -cm_name 3.chip_sw_uart_tx_rx_idx3.633337308 |
| Directory | /workspace/3.chip_sw_uart_tx_rx_idx3/latest |
| Test location | /workspace/coverage/default/3.chip_tap_straps_dev.2065809439 |
| Short name | T1242 |
| Test name | |
| Test status | |
| Simulation time | 3120998552 ps |
| CPU time | 156.99 seconds |
| Started | Jun 23 08:17:33 PM PDT 24 |
| Finished | Jun 23 08:20:10 PM PDT 24 |
| Peak memory | 617588 kb |
| Host | smart-953d5309-a869-4720-b5b6-c35c81b06624 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStDev +create_jtag_riscv_map=1 +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:test_in_rom: new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=2065809439 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_tap_straps_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.chip_tap_straps_dev.2065809439 |
| Directory | /workspace/3.chip_tap_straps_dev/latest |
| Test location | /workspace/coverage/default/3.chip_tap_straps_prod.3485843569 |
| Short name | T1016 |
| Test name | |
| Test status | |
| Simulation time | 2785762025 ps |
| CPU time | 165.61 seconds |
| Started | Jun 23 08:16:27 PM PDT 24 |
| Finished | Jun 23 08:19:13 PM PDT 24 |
| Peak memory | 617204 kb |
| Host | smart-a7ad3bc1-2f93-4ad7-81f2-3a93306614a1 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStProd +create_jtag_riscv_map=1 +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:test_in_rom :new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3485843569 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_tap_straps_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.chip_tap_straps_prod.3485843569 |
| Directory | /workspace/3.chip_tap_straps_prod/latest |
| Test location | /workspace/coverage/default/3.chip_tap_straps_rma.2840726137 |
| Short name | T65 |
| Test name | |
| Test status | |
| Simulation time | 4759462346 ps |
| CPU time | 421.75 seconds |
| Started | Jun 23 08:17:35 PM PDT 24 |
| Finished | Jun 23 08:24:37 PM PDT 24 |
| Peak memory | 620164 kb |
| Host | smart-95ec0a6a-a726-4586-a3fb-222f410e7153 |
| User | root |
| Command | /workspace/default/simv +create_jtag_riscv_map=1 +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:test_in_rom:new_rules +cdc_instrumentation _enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2840726137 -as sert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_tap_straps_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/c overage/default.vdb -cm_log /dev/null -cm_name 3.chip_tap_straps_rma.2840726137 |
| Directory | /workspace/3.chip_tap_straps_rma/latest |
| Test location | /workspace/coverage/default/3.chip_tap_straps_testunlock0.3168137584 |
| Short name | T1103 |
| Test name | |
| Test status | |
| Simulation time | 4432088590 ps |
| CPU time | 404.84 seconds |
| Started | Jun 23 08:17:24 PM PDT 24 |
| Finished | Jun 23 08:24:09 PM PDT 24 |
| Peak memory | 620204 kb |
| Host | smart-1d26162c-3a99-4749-9237-5ad5f73d73c0 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStTestUnlocked0 +create_jtag_riscv_map=1 +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:te st_in_rom:new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3168137584 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_tap_straps_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.chip_tap_straps_testunlock0.3168137584 |
| Directory | /workspace/3.chip_tap_straps_testunlock0/latest |
| Test location | /workspace/coverage/default/30.chip_sw_alert_handler_lpg_sleep_mode_alerts.937885045 |
| Short name | T301 |
| Test name | |
| Test status | |
| Simulation time | 3751130162 ps |
| CPU time | 373.19 seconds |
| Started | Jun 23 08:23:13 PM PDT 24 |
| Finished | Jun 23 08:29:27 PM PDT 24 |
| Peak memory | 642684 kb |
| Host | smart-d85d4f28-b04a-43d5-b540-a9f28bf9f65c |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=937885045 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all _escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.chip_s w_alert_handler_lpg_sleep_mode_alerts.937885045 |
| Directory | /workspace/30.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/31.chip_sw_alert_handler_lpg_sleep_mode_alerts.375122105 |
| Short name | T309 |
| Test name | |
| Test status | |
| Simulation time | 3885021300 ps |
| CPU time | 483.48 seconds |
| Started | Jun 23 08:21:23 PM PDT 24 |
| Finished | Jun 23 08:29:27 PM PDT 24 |
| Peak memory | 642412 kb |
| Host | smart-66a1fd35-1605-4b5a-9c84-aca41e3e6494 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=375122105 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all _escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.chip_s w_alert_handler_lpg_sleep_mode_alerts.375122105 |
| Directory | /workspace/31.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/31.chip_sw_all_escalation_resets.3251355464 |
| Short name | T1137 |
| Test name | |
| Test status | |
| Simulation time | 5162039320 ps |
| CPU time | 528.84 seconds |
| Started | Jun 23 08:22:50 PM PDT 24 |
| Finished | Jun 23 08:31:40 PM PDT 24 |
| Peak memory | 617364 kb |
| Host | smart-8163dec7-44b9-433f-850e-512d5258c68d |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 3251355464 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.chip_sw_all_escalation_resets.3251355464 |
| Directory | /workspace/31.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/32.chip_sw_all_escalation_resets.843298918 |
| Short name | T778 |
| Test name | |
| Test status | |
| Simulation time | 6427191028 ps |
| CPU time | 469.98 seconds |
| Started | Jun 23 08:20:44 PM PDT 24 |
| Finished | Jun 23 08:28:35 PM PDT 24 |
| Peak memory | 648000 kb |
| Host | smart-da1b006e-c932-4cd9-875f-49a8ec487ce3 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 843298918 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.chip_sw_all_escalation_resets.843298918 |
| Directory | /workspace/32.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/33.chip_sw_all_escalation_resets.1301984200 |
| Short name | T1106 |
| Test name | |
| Test status | |
| Simulation time | 4251113408 ps |
| CPU time | 550.74 seconds |
| Started | Jun 23 08:21:50 PM PDT 24 |
| Finished | Jun 23 08:31:01 PM PDT 24 |
| Peak memory | 647648 kb |
| Host | smart-cfae02f2-2372-4781-9f37-10d9507559f8 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 1301984200 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.chip_sw_all_escalation_resets.1301984200 |
| Directory | /workspace/33.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/34.chip_sw_alert_handler_lpg_sleep_mode_alerts.1887831050 |
| Short name | T1145 |
| Test name | |
| Test status | |
| Simulation time | 3984412100 ps |
| CPU time | 433.87 seconds |
| Started | Jun 23 08:21:01 PM PDT 24 |
| Finished | Jun 23 08:28:15 PM PDT 24 |
| Peak memory | 642912 kb |
| Host | smart-be6a8eb9-13d8-4dd9-83b0-12ca11a914d9 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1887831050 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.chip_ sw_alert_handler_lpg_sleep_mode_alerts.1887831050 |
| Directory | /workspace/34.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/34.chip_sw_all_escalation_resets.2360162071 |
| Short name | T816 |
| Test name | |
| Test status | |
| Simulation time | 6193275186 ps |
| CPU time | 578.6 seconds |
| Started | Jun 23 08:20:45 PM PDT 24 |
| Finished | Jun 23 08:30:24 PM PDT 24 |
| Peak memory | 643784 kb |
| Host | smart-d22489a0-42d3-4306-bd9d-7857bc8407fb |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 2360162071 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.chip_sw_all_escalation_resets.2360162071 |
| Directory | /workspace/34.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/35.chip_sw_alert_handler_lpg_sleep_mode_alerts.2078029048 |
| Short name | T737 |
| Test name | |
| Test status | |
| Simulation time | 3689015128 ps |
| CPU time | 491.6 seconds |
| Started | Jun 23 08:21:05 PM PDT 24 |
| Finished | Jun 23 08:29:17 PM PDT 24 |
| Peak memory | 642740 kb |
| Host | smart-88691c96-b1a7-4b26-b371-6855a7544c9e |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2078029048 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.chip_ sw_alert_handler_lpg_sleep_mode_alerts.2078029048 |
| Directory | /workspace/35.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/36.chip_sw_alert_handler_lpg_sleep_mode_alerts.1056186988 |
| Short name | T748 |
| Test name | |
| Test status | |
| Simulation time | 3958738000 ps |
| CPU time | 334.39 seconds |
| Started | Jun 23 08:21:33 PM PDT 24 |
| Finished | Jun 23 08:27:07 PM PDT 24 |
| Peak memory | 642644 kb |
| Host | smart-3f3473a1-efe7-42a5-9211-f3be518c8631 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1056186988 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.chip_ sw_alert_handler_lpg_sleep_mode_alerts.1056186988 |
| Directory | /workspace/36.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/37.chip_sw_alert_handler_lpg_sleep_mode_alerts.2050254851 |
| Short name | T826 |
| Test name | |
| Test status | |
| Simulation time | 3804629632 ps |
| CPU time | 431.25 seconds |
| Started | Jun 23 08:21:33 PM PDT 24 |
| Finished | Jun 23 08:28:45 PM PDT 24 |
| Peak memory | 642560 kb |
| Host | smart-2175be3e-9fd8-4e39-930e-f1113da82844 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2050254851 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.chip_ sw_alert_handler_lpg_sleep_mode_alerts.2050254851 |
| Directory | /workspace/37.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/4.chip_sw_alert_handler_lpg_sleep_mode_alerts.362371457 |
| Short name | T775 |
| Test name | |
| Test status | |
| Simulation time | 3819805756 ps |
| CPU time | 461.61 seconds |
| Started | Jun 23 08:18:51 PM PDT 24 |
| Finished | Jun 23 08:26:33 PM PDT 24 |
| Peak memory | 642516 kb |
| Host | smart-1cd1c0e1-24cf-427d-bae4-e8d56a5286f9 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=362371457 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all _escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.chip_sw _alert_handler_lpg_sleep_mode_alerts.362371457 |
| Directory | /workspace/4.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/4.chip_sw_aon_timer_sleep_wdog_sleep_pause.1792312694 |
| Short name | T1153 |
| Test name | |
| Test status | |
| Simulation time | 6587741376 ps |
| CPU time | 486.6 seconds |
| Started | Jun 23 08:17:45 PM PDT 24 |
| Finished | Jun 23 08:25:52 PM PDT 24 |
| Peak memory | 607400 kb |
| Host | smart-e4b0d339-09d9-4537-93bb-d2c566bd019a |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=aon_timer_sleep_wdog_sleep_pause_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=1792312694 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.chip_sw_aon_timer_sleep_wdog_sleep_pause.1792312694 |
| Directory | /workspace/4.chip_sw_aon_timer_sleep_wdog_sleep_pause/latest |
| Test location | /workspace/coverage/default/4.chip_sw_csrng_edn_concurrency.817416814 |
| Short name | T1148 |
| Test name | |
| Test status | |
| Simulation time | 25950176484 ps |
| CPU time | 5383.57 seconds |
| Started | Jun 23 08:18:33 PM PDT 24 |
| Finished | Jun 23 09:48:17 PM PDT 24 |
| Peak memory | 607312 kb |
| Host | smart-e811c990-6f55-4e83-800d-3e4537549571 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=140_000_000 +rng_srate_value_min=15 +rng_srate_value_max=20 +accelerate_cold_power_up_time=3 +accelerate_r egulators_power_up_time=2 +sw_build_device=sim_dv +sw_images=csrng_edn_concurrency_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=817416814 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.chip_sw_csrng_edn_concurrency.817416814 |
| Directory | /workspace/4.chip_sw_csrng_edn_concurrency/latest |
| Test location | /workspace/coverage/default/4.chip_sw_lc_ctrl_transition.185252055 |
| Short name | T1036 |
| Test name | |
| Test status | |
| Simulation time | 4676344057 ps |
| CPU time | 405.69 seconds |
| Started | Jun 23 08:17:40 PM PDT 24 |
| Finished | Jun 23 08:24:26 PM PDT 24 |
| Peak memory | 620092 kb |
| Host | smart-dd5cb0e2-daee-4c77-bdef-22f80dfdde50 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=lc_ctrl_transition_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=185252055 -assert nopostproc +UVM_TEST NAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_transition_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul t.vdb -cm_log /dev/null -cm_name 4.chip_sw_lc_ctrl_transition.185252055 |
| Directory | /workspace/4.chip_sw_lc_ctrl_transition/latest |
| Test location | /workspace/coverage/default/4.chip_sw_sensor_ctrl_alert.676085397 |
| Short name | T131 |
| Test name | |
| Test status | |
| Simulation time | 5570303398 ps |
| CPU time | 779.84 seconds |
| Started | Jun 23 08:19:51 PM PDT 24 |
| Finished | Jun 23 08:32:52 PM PDT 24 |
| Peak memory | 608468 kb |
| Host | smart-00bc7502-f13d-45e0-934b-25f8cd6c767c |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=40_000_000 +sw_build_device=sim_dv +sw_images=sensor_ctrl_alert_test:1:new_rules,test_rom:0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67608539 7 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace /coverage/default.vdb -cm_log /dev/null -cm_name 4.chip_sw_sensor_ctrl_alert.676085397 |
| Directory | /workspace/4.chip_sw_sensor_ctrl_alert/latest |
| Test location | /workspace/coverage/default/4.chip_sw_uart_rand_baudrate.2417909681 |
| Short name | T213 |
| Test name | |
| Test status | |
| Simulation time | 13102462780 ps |
| CPU time | 2288.83 seconds |
| Started | Jun 23 08:17:31 PM PDT 24 |
| Finished | Jun 23 08:55:41 PM PDT 24 |
| Peak memory | 619480 kb |
| Host | smart-845f8f16-6b81-454b-9947-2b4f63668165 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=2417909681 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.chip_sw_uart_rand_baudrate.2417909681 |
| Directory | /workspace/4.chip_sw_uart_rand_baudrate/latest |
| Test location | /workspace/coverage/default/4.chip_sw_uart_tx_rx.838736692 |
| Short name | T1346 |
| Test name | |
| Test status | |
| Simulation time | 3733577472 ps |
| CPU time | 609.25 seconds |
| Started | Jun 23 08:18:10 PM PDT 24 |
| Finished | Jun 23 08:28:20 PM PDT 24 |
| Peak memory | 614028 kb |
| Host | smart-27571a90-0256-49e8-88d7-5ce1558ca538 |
| User | root |
| Command | /workspace/default/simv +uart_idx=0 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=838736692 -as sert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac e/coverage/default.vdb -cm_log /dev/null -cm_name 4.chip_sw_uart_tx_rx.838736692 |
| Directory | /workspace/4.chip_sw_uart_tx_rx/latest |
| Test location | /workspace/coverage/default/4.chip_sw_uart_tx_rx_alt_clk_freq.931377270 |
| Short name | T974 |
| Test name | |
| Test status | |
| Simulation time | 4625737420 ps |
| CPU time | 612.38 seconds |
| Started | Jun 23 08:18:35 PM PDT 24 |
| Finished | Jun 23 08:28:48 PM PDT 24 |
| Peak memory | 618920 kb |
| Host | smart-6265b700-7ddd-44af-b98b-fe1cfa6d5a1e |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=80_000_000 +chip_clock_source=ChipClockSourceExternal96Mhz +calibrate_usb_clk=1 +sw_build_device=sim_dv +s w_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=931377270 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_ba udrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.chip_sw_uart_tx_rx_ alt_clk_freq.931377270 |
| Directory | /workspace/4.chip_sw_uart_tx_rx_alt_clk_freq/latest |
| Test location | /workspace/coverage/default/4.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.966648644 |
| Short name | T1048 |
| Test name | |
| Test status | |
| Simulation time | 8583620672 ps |
| CPU time | 1086.28 seconds |
| Started | Jun 23 08:18:06 PM PDT 24 |
| Finished | Jun 23 08:36:13 PM PDT 24 |
| Peak memory | 618468 kb |
| Host | smart-428ab9eb-0999-4be7-834c-d8573e3a143d |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +chip_clock_source=ChipClockSourceExternal48Mhz +sw_build_device=sim_dv +s w_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=966648644 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_ba udrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.chip_sw_uart_tx_rx_ alt_clk_freq_low_speed.966648644 |
| Directory | /workspace/4.chip_sw_uart_tx_rx_alt_clk_freq_low_speed/latest |
| Test location | /workspace/coverage/default/4.chip_sw_uart_tx_rx_idx1.1606442839 |
| Short name | T1295 |
| Test name | |
| Test status | |
| Simulation time | 4815545416 ps |
| CPU time | 850.71 seconds |
| Started | Jun 23 08:17:50 PM PDT 24 |
| Finished | Jun 23 08:32:01 PM PDT 24 |
| Peak memory | 615116 kb |
| Host | smart-19e21022-4992-4bb3-ae7a-dcffca4a30a7 |
| User | root |
| Command | /workspace/default/simv +uart_idx=1 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1606442839 -a ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/default.vdb -cm_log /dev/null -cm_name 4.chip_sw_uart_tx_rx_idx1.1606442839 |
| Directory | /workspace/4.chip_sw_uart_tx_rx_idx1/latest |
| Test location | /workspace/coverage/default/4.chip_sw_uart_tx_rx_idx3.1567244621 |
| Short name | T1197 |
| Test name | |
| Test status | |
| Simulation time | 3969103186 ps |
| CPU time | 550.65 seconds |
| Started | Jun 23 08:18:03 PM PDT 24 |
| Finished | Jun 23 08:27:14 PM PDT 24 |
| Peak memory | 614032 kb |
| Host | smart-2038073c-b1b0-40ab-8445-121f14d6a397 |
| User | root |
| Command | /workspace/default/simv +uart_idx=3 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1567244621 -a ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/default.vdb -cm_log /dev/null -cm_name 4.chip_sw_uart_tx_rx_idx3.1567244621 |
| Directory | /workspace/4.chip_sw_uart_tx_rx_idx3/latest |
| Test location | /workspace/coverage/default/4.chip_tap_straps_dev.1659472855 |
| Short name | T992 |
| Test name | |
| Test status | |
| Simulation time | 2307840530 ps |
| CPU time | 127.48 seconds |
| Started | Jun 23 08:17:22 PM PDT 24 |
| Finished | Jun 23 08:19:30 PM PDT 24 |
| Peak memory | 617380 kb |
| Host | smart-c12a24a2-9399-47f7-814b-0ca2cc63165a |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStDev +create_jtag_riscv_map=1 +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:test_in_rom: new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=1659472855 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_tap_straps_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.chip_tap_straps_dev.1659472855 |
| Directory | /workspace/4.chip_tap_straps_dev/latest |
| Test location | /workspace/coverage/default/4.chip_tap_straps_prod.2458681303 |
| Short name | T1012 |
| Test name | |
| Test status | |
| Simulation time | 3263667460 ps |
| CPU time | 162.38 seconds |
| Started | Jun 23 08:17:01 PM PDT 24 |
| Finished | Jun 23 08:19:43 PM PDT 24 |
| Peak memory | 621968 kb |
| Host | smart-ce32916c-ddfd-447e-9b17-b9645fb7823c |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStProd +create_jtag_riscv_map=1 +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:test_in_rom :new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2458681303 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_tap_straps_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.chip_tap_straps_prod.2458681303 |
| Directory | /workspace/4.chip_tap_straps_prod/latest |
| Test location | /workspace/coverage/default/4.chip_tap_straps_testunlock0.3862777899 |
| Short name | T1236 |
| Test name | |
| Test status | |
| Simulation time | 5828866022 ps |
| CPU time | 494.73 seconds |
| Started | Jun 23 08:18:38 PM PDT 24 |
| Finished | Jun 23 08:26:53 PM PDT 24 |
| Peak memory | 621456 kb |
| Host | smart-36368384-b216-4ec6-a441-9911454ac304 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStTestUnlocked0 +create_jtag_riscv_map=1 +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:te st_in_rom:new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3862777899 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_tap_straps_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.chip_tap_straps_testunlock0.3862777899 |
| Directory | /workspace/4.chip_tap_straps_testunlock0/latest |
| Test location | /workspace/coverage/default/41.chip_sw_alert_handler_lpg_sleep_mode_alerts.3426074869 |
| Short name | T735 |
| Test name | |
| Test status | |
| Simulation time | 3928785272 ps |
| CPU time | 420.03 seconds |
| Started | Jun 23 08:23:02 PM PDT 24 |
| Finished | Jun 23 08:30:02 PM PDT 24 |
| Peak memory | 642664 kb |
| Host | smart-b37ff666-885c-4369-9070-31b163dac1d9 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3426074869 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.chip_ sw_alert_handler_lpg_sleep_mode_alerts.3426074869 |
| Directory | /workspace/41.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/41.chip_sw_all_escalation_resets.1388145931 |
| Short name | T828 |
| Test name | |
| Test status | |
| Simulation time | 5886437656 ps |
| CPU time | 902.96 seconds |
| Started | Jun 23 08:21:59 PM PDT 24 |
| Finished | Jun 23 08:37:02 PM PDT 24 |
| Peak memory | 647776 kb |
| Host | smart-e5bded27-3b48-4786-b999-2c1b2a80c231 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 1388145931 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.chip_sw_all_escalation_resets.1388145931 |
| Directory | /workspace/41.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/42.chip_sw_all_escalation_resets.3099275490 |
| Short name | T825 |
| Test name | |
| Test status | |
| Simulation time | 4654214668 ps |
| CPU time | 681.98 seconds |
| Started | Jun 23 08:22:04 PM PDT 24 |
| Finished | Jun 23 08:33:26 PM PDT 24 |
| Peak memory | 648104 kb |
| Host | smart-2ab8eaf4-fda7-4e45-a53c-479bfa5d34ac |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 3099275490 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.chip_sw_all_escalation_resets.3099275490 |
| Directory | /workspace/42.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/43.chip_sw_alert_handler_lpg_sleep_mode_alerts.2402023033 |
| Short name | T818 |
| Test name | |
| Test status | |
| Simulation time | 4446302604 ps |
| CPU time | 373.86 seconds |
| Started | Jun 23 08:21:52 PM PDT 24 |
| Finished | Jun 23 08:28:07 PM PDT 24 |
| Peak memory | 643072 kb |
| Host | smart-1752a099-ba9e-459a-8c3b-cf96cfb40387 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2402023033 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.chip_ sw_alert_handler_lpg_sleep_mode_alerts.2402023033 |
| Directory | /workspace/43.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/43.chip_sw_all_escalation_resets.4213021947 |
| Short name | T82 |
| Test name | |
| Test status | |
| Simulation time | 5466788800 ps |
| CPU time | 613.13 seconds |
| Started | Jun 23 08:21:43 PM PDT 24 |
| Finished | Jun 23 08:31:57 PM PDT 24 |
| Peak memory | 643492 kb |
| Host | smart-76623958-a8cf-44a8-a4d8-2f4bc7c1e5cc |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 4213021947 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.chip_sw_all_escalation_resets.4213021947 |
| Directory | /workspace/43.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/44.chip_sw_alert_handler_lpg_sleep_mode_alerts.3965812430 |
| Short name | T274 |
| Test name | |
| Test status | |
| Simulation time | 3469409160 ps |
| CPU time | 365.94 seconds |
| Started | Jun 23 08:23:20 PM PDT 24 |
| Finished | Jun 23 08:29:27 PM PDT 24 |
| Peak memory | 642752 kb |
| Host | smart-0dfccee5-eb93-428f-9598-361ca790c402 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3965812430 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.chip_ sw_alert_handler_lpg_sleep_mode_alerts.3965812430 |
| Directory | /workspace/44.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/46.chip_sw_alert_handler_lpg_sleep_mode_alerts.16803027 |
| Short name | T800 |
| Test name | |
| Test status | |
| Simulation time | 4195342540 ps |
| CPU time | 380.87 seconds |
| Started | Jun 23 08:23:04 PM PDT 24 |
| Finished | Jun 23 08:29:25 PM PDT 24 |
| Peak memory | 642540 kb |
| Host | smart-d04a2a7e-7e6f-45b6-9f73-6ff2cd32aaa6 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16803027 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_ escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.chip_sw _alert_handler_lpg_sleep_mode_alerts.16803027 |
| Directory | /workspace/46.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/46.chip_sw_all_escalation_resets.3929904019 |
| Short name | T774 |
| Test name | |
| Test status | |
| Simulation time | 6045396848 ps |
| CPU time | 508.99 seconds |
| Started | Jun 23 08:23:20 PM PDT 24 |
| Finished | Jun 23 08:31:49 PM PDT 24 |
| Peak memory | 643512 kb |
| Host | smart-c3b23790-b010-466f-887a-d9eade14e3e8 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 3929904019 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.chip_sw_all_escalation_resets.3929904019 |
| Directory | /workspace/46.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/47.chip_sw_all_escalation_resets.3770902201 |
| Short name | T769 |
| Test name | |
| Test status | |
| Simulation time | 5319729160 ps |
| CPU time | 832.23 seconds |
| Started | Jun 23 08:23:08 PM PDT 24 |
| Finished | Jun 23 08:37:01 PM PDT 24 |
| Peak memory | 648416 kb |
| Host | smart-5134e621-eec1-481f-9c74-4d9b710f3d9f |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 3770902201 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.chip_sw_all_escalation_resets.3770902201 |
| Directory | /workspace/47.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/48.chip_sw_alert_handler_lpg_sleep_mode_alerts.1947056762 |
| Short name | T1280 |
| Test name | |
| Test status | |
| Simulation time | 4162385100 ps |
| CPU time | 425.4 seconds |
| Started | Jun 23 08:23:29 PM PDT 24 |
| Finished | Jun 23 08:30:35 PM PDT 24 |
| Peak memory | 642428 kb |
| Host | smart-0e1344d3-1144-413b-bb28-9438e0790899 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1947056762 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.chip_ sw_alert_handler_lpg_sleep_mode_alerts.1947056762 |
| Directory | /workspace/48.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/48.chip_sw_all_escalation_resets.3781743401 |
| Short name | T1119 |
| Test name | |
| Test status | |
| Simulation time | 5261618248 ps |
| CPU time | 576.6 seconds |
| Started | Jun 23 08:21:51 PM PDT 24 |
| Finished | Jun 23 08:31:28 PM PDT 24 |
| Peak memory | 647612 kb |
| Host | smart-9a5d84f2-157e-44f1-84ba-93e81f89778c |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 3781743401 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.chip_sw_all_escalation_resets.3781743401 |
| Directory | /workspace/48.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/49.chip_sw_alert_handler_lpg_sleep_mode_alerts.1797429567 |
| Short name | T771 |
| Test name | |
| Test status | |
| Simulation time | 3428744728 ps |
| CPU time | 386.22 seconds |
| Started | Jun 23 08:26:34 PM PDT 24 |
| Finished | Jun 23 08:33:26 PM PDT 24 |
| Peak memory | 647248 kb |
| Host | smart-804f5f0c-f0a1-4ddb-b1b4-dff182385cd9 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1797429567 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.chip_ sw_alert_handler_lpg_sleep_mode_alerts.1797429567 |
| Directory | /workspace/49.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/49.chip_sw_all_escalation_resets.2113120223 |
| Short name | T806 |
| Test name | |
| Test status | |
| Simulation time | 5375186494 ps |
| CPU time | 688.33 seconds |
| Started | Jun 23 08:23:28 PM PDT 24 |
| Finished | Jun 23 08:34:56 PM PDT 24 |
| Peak memory | 648020 kb |
| Host | smart-9ba70b89-6a1e-4072-bdd9-02e6ddcf2f8d |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 2113120223 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.chip_sw_all_escalation_resets.2113120223 |
| Directory | /workspace/49.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/5.chip_sw_all_escalation_resets.197199633 |
| Short name | T839 |
| Test name | |
| Test status | |
| Simulation time | 6093559852 ps |
| CPU time | 813.59 seconds |
| Started | Jun 23 08:18:47 PM PDT 24 |
| Finished | Jun 23 08:32:21 PM PDT 24 |
| Peak memory | 643508 kb |
| Host | smart-2e3826e5-8231-4ca4-af1b-9b8a1ce70c17 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 197199633 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.chip_sw_all_escalation_resets.197199633 |
| Directory | /workspace/5.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/5.chip_sw_csrng_edn_concurrency.117294025 |
| Short name | T978 |
| Test name | |
| Test status | |
| Simulation time | 16873471210 ps |
| CPU time | 3575.11 seconds |
| Started | Jun 23 08:18:40 PM PDT 24 |
| Finished | Jun 23 09:18:16 PM PDT 24 |
| Peak memory | 607344 kb |
| Host | smart-265eb2c0-a45b-42ff-9efb-1b4e0b5bf409 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=140_000_000 +rng_srate_value_min=15 +rng_srate_value_max=20 +accelerate_cold_power_up_time=3 +accelerate_r egulators_power_up_time=2 +sw_build_device=sim_dv +sw_images=csrng_edn_concurrency_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=117294025 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.chip_sw_csrng_edn_concurrency.117294025 |
| Directory | /workspace/5.chip_sw_csrng_edn_concurrency/latest |
| Test location | /workspace/coverage/default/5.chip_sw_data_integrity_escalation.4048434226 |
| Short name | T268 |
| Test name | |
| Test status | |
| Simulation time | 5846083460 ps |
| CPU time | 549.84 seconds |
| Started | Jun 23 08:18:51 PM PDT 24 |
| Finished | Jun 23 08:28:01 PM PDT 24 |
| Peak memory | 608436 kb |
| Host | smart-e42a19f3-f0ee-4f37-a543-f27478975f9b |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=data_integrity_escalation_reset_test:1:new_rules,test_ro m:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=4048434226 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_data_integrity_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.chip_sw_data_integrity_escalation.4048434226 |
| Directory | /workspace/5.chip_sw_data_integrity_escalation/latest |
| Test location | /workspace/coverage/default/5.chip_sw_lc_ctrl_transition.433637397 |
| Short name | T98 |
| Test name | |
| Test status | |
| Simulation time | 5894299875 ps |
| CPU time | 459.98 seconds |
| Started | Jun 23 08:18:10 PM PDT 24 |
| Finished | Jun 23 08:25:50 PM PDT 24 |
| Peak memory | 624504 kb |
| Host | smart-52670208-fe72-4824-b5d6-e90e92ef5e92 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=lc_ctrl_transition_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=433637397 -assert nopostproc +UVM_TEST NAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_transition_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul t.vdb -cm_log /dev/null -cm_name 5.chip_sw_lc_ctrl_transition.433637397 |
| Directory | /workspace/5.chip_sw_lc_ctrl_transition/latest |
| Test location | /workspace/coverage/default/5.chip_sw_uart_rand_baudrate.1071429804 |
| Short name | T1326 |
| Test name | |
| Test status | |
| Simulation time | 8681672360 ps |
| CPU time | 1339.13 seconds |
| Started | Jun 23 08:17:23 PM PDT 24 |
| Finished | Jun 23 08:39:42 PM PDT 24 |
| Peak memory | 619404 kb |
| Host | smart-3be56dfe-7ad0-4467-a3e3-ca12535086ba |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=1071429804 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.chip_sw_uart_rand_baudrate.1071429804 |
| Directory | /workspace/5.chip_sw_uart_rand_baudrate/latest |
| Test location | /workspace/coverage/default/50.chip_sw_alert_handler_lpg_sleep_mode_alerts.2734008785 |
| Short name | T785 |
| Test name | |
| Test status | |
| Simulation time | 3679758600 ps |
| CPU time | 398.07 seconds |
| Started | Jun 23 08:26:11 PM PDT 24 |
| Finished | Jun 23 08:32:51 PM PDT 24 |
| Peak memory | 642520 kb |
| Host | smart-3af1fa70-3ade-46e6-8d4d-c7d5553cf731 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2734008785 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.chip_ sw_alert_handler_lpg_sleep_mode_alerts.2734008785 |
| Directory | /workspace/50.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/50.chip_sw_all_escalation_resets.198507163 |
| Short name | T749 |
| Test name | |
| Test status | |
| Simulation time | 5206180776 ps |
| CPU time | 529.39 seconds |
| Started | Jun 23 08:21:55 PM PDT 24 |
| Finished | Jun 23 08:30:45 PM PDT 24 |
| Peak memory | 648028 kb |
| Host | smart-a433bd25-eb64-4ab5-a304-aa54f46573c9 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 198507163 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.chip_sw_all_escalation_resets.198507163 |
| Directory | /workspace/50.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/51.chip_sw_all_escalation_resets.3701207406 |
| Short name | T760 |
| Test name | |
| Test status | |
| Simulation time | 5194278600 ps |
| CPU time | 519.16 seconds |
| Started | Jun 23 08:21:53 PM PDT 24 |
| Finished | Jun 23 08:30:33 PM PDT 24 |
| Peak memory | 648024 kb |
| Host | smart-1cf2eff7-d648-41e0-bb32-a34f0f8b3731 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 3701207406 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.chip_sw_all_escalation_resets.3701207406 |
| Directory | /workspace/51.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/53.chip_sw_alert_handler_lpg_sleep_mode_alerts.2399559484 |
| Short name | T1118 |
| Test name | |
| Test status | |
| Simulation time | 4093811748 ps |
| CPU time | 404.32 seconds |
| Started | Jun 23 08:23:03 PM PDT 24 |
| Finished | Jun 23 08:29:48 PM PDT 24 |
| Peak memory | 646780 kb |
| Host | smart-9fe27f89-d4f2-4ebc-8005-dae2e25deded |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2399559484 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.chip_ sw_alert_handler_lpg_sleep_mode_alerts.2399559484 |
| Directory | /workspace/53.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/54.chip_sw_alert_handler_lpg_sleep_mode_alerts.2716969236 |
| Short name | T772 |
| Test name | |
| Test status | |
| Simulation time | 4418046450 ps |
| CPU time | 492.34 seconds |
| Started | Jun 23 08:22:53 PM PDT 24 |
| Finished | Jun 23 08:31:06 PM PDT 24 |
| Peak memory | 642744 kb |
| Host | smart-66061c39-0d89-4bfb-beb1-6bead2c6bc21 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2716969236 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.chip_ sw_alert_handler_lpg_sleep_mode_alerts.2716969236 |
| Directory | /workspace/54.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/54.chip_sw_all_escalation_resets.3822909254 |
| Short name | T1294 |
| Test name | |
| Test status | |
| Simulation time | 5440338892 ps |
| CPU time | 567.61 seconds |
| Started | Jun 23 08:22:53 PM PDT 24 |
| Finished | Jun 23 08:32:21 PM PDT 24 |
| Peak memory | 643864 kb |
| Host | smart-5dcd945d-616b-4ed3-88f3-a81e93144714 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 3822909254 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.chip_sw_all_escalation_resets.3822909254 |
| Directory | /workspace/54.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/55.chip_sw_alert_handler_lpg_sleep_mode_alerts.3593791923 |
| Short name | T780 |
| Test name | |
| Test status | |
| Simulation time | 3913464240 ps |
| CPU time | 355.68 seconds |
| Started | Jun 23 08:22:21 PM PDT 24 |
| Finished | Jun 23 08:28:17 PM PDT 24 |
| Peak memory | 642560 kb |
| Host | smart-e13916cb-7c02-4d30-8f09-266ef20e57c4 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3593791923 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.chip_ sw_alert_handler_lpg_sleep_mode_alerts.3593791923 |
| Directory | /workspace/55.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/55.chip_sw_all_escalation_resets.2600847576 |
| Short name | T346 |
| Test name | |
| Test status | |
| Simulation time | 5594710760 ps |
| CPU time | 564.49 seconds |
| Started | Jun 23 08:27:05 PM PDT 24 |
| Finished | Jun 23 08:37:02 PM PDT 24 |
| Peak memory | 647988 kb |
| Host | smart-5196be6e-9885-4ad0-aeb9-c85139da4d73 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 2600847576 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.chip_sw_all_escalation_resets.2600847576 |
| Directory | /workspace/55.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/56.chip_sw_all_escalation_resets.2512384598 |
| Short name | T765 |
| Test name | |
| Test status | |
| Simulation time | 5670803464 ps |
| CPU time | 570.73 seconds |
| Started | Jun 23 08:23:51 PM PDT 24 |
| Finished | Jun 23 08:33:22 PM PDT 24 |
| Peak memory | 643788 kb |
| Host | smart-17318fb1-962d-4ddf-86a7-731ab2ea41d3 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 2512384598 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.chip_sw_all_escalation_resets.2512384598 |
| Directory | /workspace/56.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/57.chip_sw_all_escalation_resets.1869941676 |
| Short name | T770 |
| Test name | |
| Test status | |
| Simulation time | 4656070840 ps |
| CPU time | 549.74 seconds |
| Started | Jun 23 08:23:21 PM PDT 24 |
| Finished | Jun 23 08:32:31 PM PDT 24 |
| Peak memory | 648448 kb |
| Host | smart-2838df72-cb0f-47da-99b5-eafc033e61b6 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 1869941676 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.chip_sw_all_escalation_resets.1869941676 |
| Directory | /workspace/57.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/58.chip_sw_alert_handler_lpg_sleep_mode_alerts.2779307468 |
| Short name | T1042 |
| Test name | |
| Test status | |
| Simulation time | 3424719760 ps |
| CPU time | 388.97 seconds |
| Started | Jun 23 08:22:55 PM PDT 24 |
| Finished | Jun 23 08:29:24 PM PDT 24 |
| Peak memory | 642420 kb |
| Host | smart-5a9b475b-5aec-4c88-adfc-a30c9568334a |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2779307468 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.chip_ sw_alert_handler_lpg_sleep_mode_alerts.2779307468 |
| Directory | /workspace/58.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/58.chip_sw_all_escalation_resets.1911579033 |
| Short name | T751 |
| Test name | |
| Test status | |
| Simulation time | 5375657208 ps |
| CPU time | 533.51 seconds |
| Started | Jun 23 08:25:19 PM PDT 24 |
| Finished | Jun 23 08:34:13 PM PDT 24 |
| Peak memory | 647936 kb |
| Host | smart-1bf190d3-9ca6-4258-9968-24b74b0eac58 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 1911579033 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.chip_sw_all_escalation_resets.1911579033 |
| Directory | /workspace/58.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/6.chip_sw_all_escalation_resets.3972989642 |
| Short name | T814 |
| Test name | |
| Test status | |
| Simulation time | 5245435332 ps |
| CPU time | 557.67 seconds |
| Started | Jun 23 08:18:19 PM PDT 24 |
| Finished | Jun 23 08:27:37 PM PDT 24 |
| Peak memory | 647776 kb |
| Host | smart-f9be9a36-6e13-47c7-8a7f-47251dfd5f46 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 3972989642 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.chip_sw_all_escalation_resets.3972989642 |
| Directory | /workspace/6.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/6.chip_sw_csrng_edn_concurrency.2290669705 |
| Short name | T250 |
| Test name | |
| Test status | |
| Simulation time | 13167851128 ps |
| CPU time | 2546.41 seconds |
| Started | Jun 23 08:18:25 PM PDT 24 |
| Finished | Jun 23 09:00:52 PM PDT 24 |
| Peak memory | 607352 kb |
| Host | smart-ef8c39f2-cac2-4443-98bc-728f4a69d6f5 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=140_000_000 +rng_srate_value_min=15 +rng_srate_value_max=20 +accelerate_cold_power_up_time=3 +accelerate_r egulators_power_up_time=2 +sw_build_device=sim_dv +sw_images=csrng_edn_concurrency_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2290669705 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd b -cm_log /dev/null -cm_name 6.chip_sw_csrng_edn_concurrency.2290669705 |
| Directory | /workspace/6.chip_sw_csrng_edn_concurrency/latest |
| Test location | /workspace/coverage/default/6.chip_sw_lc_ctrl_transition.989699059 |
| Short name | T404 |
| Test name | |
| Test status | |
| Simulation time | 6693395005 ps |
| CPU time | 505.36 seconds |
| Started | Jun 23 08:17:17 PM PDT 24 |
| Finished | Jun 23 08:25:42 PM PDT 24 |
| Peak memory | 618744 kb |
| Host | smart-541fcb36-9e19-42c9-a83e-54500ade4658 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=lc_ctrl_transition_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=989699059 -assert nopostproc +UVM_TEST NAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_transition_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul t.vdb -cm_log /dev/null -cm_name 6.chip_sw_lc_ctrl_transition.989699059 |
| Directory | /workspace/6.chip_sw_lc_ctrl_transition/latest |
| Test location | /workspace/coverage/default/6.chip_sw_uart_rand_baudrate.94527070 |
| Short name | T209 |
| Test name | |
| Test status | |
| Simulation time | 3386437132 ps |
| CPU time | 540.75 seconds |
| Started | Jun 23 08:18:31 PM PDT 24 |
| Finished | Jun 23 08:27:33 PM PDT 24 |
| Peak memory | 619152 kb |
| Host | smart-17979528-164b-4a56-9e9b-55558f8e43e6 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=94527070 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.chip_sw_uart_rand_baudrate.94527070 |
| Directory | /workspace/6.chip_sw_uart_rand_baudrate/latest |
| Test location | /workspace/coverage/default/60.chip_sw_alert_handler_lpg_sleep_mode_alerts.3256260851 |
| Short name | T1263 |
| Test name | |
| Test status | |
| Simulation time | 3162648320 ps |
| CPU time | 349.01 seconds |
| Started | Jun 23 08:23:13 PM PDT 24 |
| Finished | Jun 23 08:29:02 PM PDT 24 |
| Peak memory | 642620 kb |
| Host | smart-15c20556-b4e0-4810-bbbd-835ad3b3280c |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3256260851 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.chip_ sw_alert_handler_lpg_sleep_mode_alerts.3256260851 |
| Directory | /workspace/60.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/60.chip_sw_all_escalation_resets.148507752 |
| Short name | T302 |
| Test name | |
| Test status | |
| Simulation time | 5599175000 ps |
| CPU time | 438.31 seconds |
| Started | Jun 23 08:22:29 PM PDT 24 |
| Finished | Jun 23 08:29:47 PM PDT 24 |
| Peak memory | 648272 kb |
| Host | smart-3f4fffc2-abf3-4791-ad02-80d4b3b0a158 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 148507752 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.chip_sw_all_escalation_resets.148507752 |
| Directory | /workspace/60.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/61.chip_sw_alert_handler_lpg_sleep_mode_alerts.698969877 |
| Short name | T794 |
| Test name | |
| Test status | |
| Simulation time | 3335376936 ps |
| CPU time | 441.73 seconds |
| Started | Jun 23 08:28:04 PM PDT 24 |
| Finished | Jun 23 08:35:57 PM PDT 24 |
| Peak memory | 642764 kb |
| Host | smart-37efae1a-ad5e-4223-8363-69adaff39c8f |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=698969877 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all _escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.chip_s w_alert_handler_lpg_sleep_mode_alerts.698969877 |
| Directory | /workspace/61.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/61.chip_sw_all_escalation_resets.1909012696 |
| Short name | T161 |
| Test name | |
| Test status | |
| Simulation time | 4915989638 ps |
| CPU time | 447.82 seconds |
| Started | Jun 23 08:22:50 PM PDT 24 |
| Finished | Jun 23 08:30:18 PM PDT 24 |
| Peak memory | 617408 kb |
| Host | smart-c7a3d2c4-e01a-4afd-ac73-566196841a61 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 1909012696 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.chip_sw_all_escalation_resets.1909012696 |
| Directory | /workspace/61.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/62.chip_sw_alert_handler_lpg_sleep_mode_alerts.1438455082 |
| Short name | T787 |
| Test name | |
| Test status | |
| Simulation time | 3747722040 ps |
| CPU time | 364.48 seconds |
| Started | Jun 23 08:25:30 PM PDT 24 |
| Finished | Jun 23 08:31:35 PM PDT 24 |
| Peak memory | 642340 kb |
| Host | smart-7c7d3904-8402-476b-a7f6-61c75e2faf7f |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1438455082 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.chip_ sw_alert_handler_lpg_sleep_mode_alerts.1438455082 |
| Directory | /workspace/62.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/63.chip_sw_alert_handler_lpg_sleep_mode_alerts.3330678207 |
| Short name | T962 |
| Test name | |
| Test status | |
| Simulation time | 3590988190 ps |
| CPU time | 377.45 seconds |
| Started | Jun 23 08:24:25 PM PDT 24 |
| Finished | Jun 23 08:30:43 PM PDT 24 |
| Peak memory | 615452 kb |
| Host | smart-f43e1f06-9dd3-407a-941b-6d15488e29d9 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3330678207 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.chip_ sw_alert_handler_lpg_sleep_mode_alerts.3330678207 |
| Directory | /workspace/63.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/63.chip_sw_all_escalation_resets.2194073749 |
| Short name | T786 |
| Test name | |
| Test status | |
| Simulation time | 5083196456 ps |
| CPU time | 547.96 seconds |
| Started | Jun 23 08:24:05 PM PDT 24 |
| Finished | Jun 23 08:33:14 PM PDT 24 |
| Peak memory | 648108 kb |
| Host | smart-2dbc4e4a-27fa-4788-bbfb-a3d5f5699c5c |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 2194073749 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.chip_sw_all_escalation_resets.2194073749 |
| Directory | /workspace/63.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/64.chip_sw_alert_handler_lpg_sleep_mode_alerts.2716253757 |
| Short name | T817 |
| Test name | |
| Test status | |
| Simulation time | 3700142400 ps |
| CPU time | 286.56 seconds |
| Started | Jun 23 08:24:43 PM PDT 24 |
| Finished | Jun 23 08:29:29 PM PDT 24 |
| Peak memory | 647252 kb |
| Host | smart-b196000a-a61e-4943-aa90-f9bc4fadf20a |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2716253757 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.chip_ sw_alert_handler_lpg_sleep_mode_alerts.2716253757 |
| Directory | /workspace/64.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/64.chip_sw_all_escalation_resets.462264664 |
| Short name | T336 |
| Test name | |
| Test status | |
| Simulation time | 5336011000 ps |
| CPU time | 512.46 seconds |
| Started | Jun 23 08:22:30 PM PDT 24 |
| Finished | Jun 23 08:31:03 PM PDT 24 |
| Peak memory | 608628 kb |
| Host | smart-a06cacd2-2ac4-461d-87f6-713eb3d69683 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 462264664 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.chip_sw_all_escalation_resets.462264664 |
| Directory | /workspace/64.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/65.chip_sw_alert_handler_lpg_sleep_mode_alerts.1959006135 |
| Short name | T804 |
| Test name | |
| Test status | |
| Simulation time | 3440760200 ps |
| CPU time | 308.64 seconds |
| Started | Jun 23 08:24:47 PM PDT 24 |
| Finished | Jun 23 08:29:56 PM PDT 24 |
| Peak memory | 642580 kb |
| Host | smart-1f44a967-b739-456f-b246-d81e72adf0ab |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1959006135 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.chip_ sw_alert_handler_lpg_sleep_mode_alerts.1959006135 |
| Directory | /workspace/65.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/65.chip_sw_all_escalation_resets.2855747933 |
| Short name | T370 |
| Test name | |
| Test status | |
| Simulation time | 4694758888 ps |
| CPU time | 623.28 seconds |
| Started | Jun 23 08:22:57 PM PDT 24 |
| Finished | Jun 23 08:33:20 PM PDT 24 |
| Peak memory | 647716 kb |
| Host | smart-044aca99-79ec-449f-83cc-30e90943617f |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 2855747933 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.chip_sw_all_escalation_resets.2855747933 |
| Directory | /workspace/65.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/66.chip_sw_alert_handler_lpg_sleep_mode_alerts.3347428245 |
| Short name | T743 |
| Test name | |
| Test status | |
| Simulation time | 3249832700 ps |
| CPU time | 341.49 seconds |
| Started | Jun 23 08:24:45 PM PDT 24 |
| Finished | Jun 23 08:30:26 PM PDT 24 |
| Peak memory | 615524 kb |
| Host | smart-7a678ecb-cac2-4fbe-995e-d1fa4d890f7e |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3347428245 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.chip_ sw_alert_handler_lpg_sleep_mode_alerts.3347428245 |
| Directory | /workspace/66.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/66.chip_sw_all_escalation_resets.3403417788 |
| Short name | T337 |
| Test name | |
| Test status | |
| Simulation time | 6191592416 ps |
| CPU time | 571.55 seconds |
| Started | Jun 23 08:23:42 PM PDT 24 |
| Finished | Jun 23 08:33:14 PM PDT 24 |
| Peak memory | 643472 kb |
| Host | smart-50770658-cdc7-4d4d-91ed-695adfb9d8b0 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 3403417788 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.chip_sw_all_escalation_resets.3403417788 |
| Directory | /workspace/66.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/67.chip_sw_alert_handler_lpg_sleep_mode_alerts.989088190 |
| Short name | T1275 |
| Test name | |
| Test status | |
| Simulation time | 3682577352 ps |
| CPU time | 457.87 seconds |
| Started | Jun 23 08:24:29 PM PDT 24 |
| Finished | Jun 23 08:32:07 PM PDT 24 |
| Peak memory | 646856 kb |
| Host | smart-35820022-c943-4a32-a338-7b4a6642b908 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=989088190 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all _escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.chip_s w_alert_handler_lpg_sleep_mode_alerts.989088190 |
| Directory | /workspace/67.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/68.chip_sw_alert_handler_lpg_sleep_mode_alerts.755737267 |
| Short name | T1290 |
| Test name | |
| Test status | |
| Simulation time | 3877663440 ps |
| CPU time | 322.78 seconds |
| Started | Jun 23 08:23:22 PM PDT 24 |
| Finished | Jun 23 08:28:45 PM PDT 24 |
| Peak memory | 642460 kb |
| Host | smart-84bde3b5-fd8c-4d9e-9501-870788e8ef7b |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=755737267 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all _escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.chip_s w_alert_handler_lpg_sleep_mode_alerts.755737267 |
| Directory | /workspace/68.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/68.chip_sw_all_escalation_resets.3748133657 |
| Short name | T162 |
| Test name | |
| Test status | |
| Simulation time | 6202462800 ps |
| CPU time | 716.63 seconds |
| Started | Jun 23 08:23:20 PM PDT 24 |
| Finished | Jun 23 08:35:17 PM PDT 24 |
| Peak memory | 617140 kb |
| Host | smart-5a27becc-40d8-4272-9b5d-369ccc29a1bc |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 3748133657 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.chip_sw_all_escalation_resets.3748133657 |
| Directory | /workspace/68.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/69.chip_sw_alert_handler_lpg_sleep_mode_alerts.773043579 |
| Short name | T712 |
| Test name | |
| Test status | |
| Simulation time | 3377809238 ps |
| CPU time | 398.33 seconds |
| Started | Jun 23 08:24:35 PM PDT 24 |
| Finished | Jun 23 08:31:14 PM PDT 24 |
| Peak memory | 642572 kb |
| Host | smart-88552ff6-018b-4968-a733-d56e4a24e6ea |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=773043579 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all _escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.chip_s w_alert_handler_lpg_sleep_mode_alerts.773043579 |
| Directory | /workspace/69.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/7.chip_sw_alert_handler_lpg_sleep_mode_alerts.3567969089 |
| Short name | T766 |
| Test name | |
| Test status | |
| Simulation time | 3875923762 ps |
| CPU time | 354.85 seconds |
| Started | Jun 23 08:18:44 PM PDT 24 |
| Finished | Jun 23 08:24:39 PM PDT 24 |
| Peak memory | 642700 kb |
| Host | smart-d80d6815-5547-41d7-98c8-3904913ba59d |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3567969089 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.chip_s w_alert_handler_lpg_sleep_mode_alerts.3567969089 |
| Directory | /workspace/7.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/7.chip_sw_all_escalation_resets.3570694684 |
| Short name | T779 |
| Test name | |
| Test status | |
| Simulation time | 4931681006 ps |
| CPU time | 640.29 seconds |
| Started | Jun 23 08:18:52 PM PDT 24 |
| Finished | Jun 23 08:29:33 PM PDT 24 |
| Peak memory | 647768 kb |
| Host | smart-995f5299-b186-4c29-9b17-68a2492f23bb |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 3570694684 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.chip_sw_all_escalation_resets.3570694684 |
| Directory | /workspace/7.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/7.chip_sw_csrng_edn_concurrency.1905182111 |
| Short name | T248 |
| Test name | |
| Test status | |
| Simulation time | 23582296974 ps |
| CPU time | 5752.54 seconds |
| Started | Jun 23 08:17:43 PM PDT 24 |
| Finished | Jun 23 09:53:37 PM PDT 24 |
| Peak memory | 607340 kb |
| Host | smart-e9a369ce-01d4-4730-bd3d-37e66481ebe1 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=140_000_000 +rng_srate_value_min=15 +rng_srate_value_max=20 +accelerate_cold_power_up_time=3 +accelerate_r egulators_power_up_time=2 +sw_build_device=sim_dv +sw_images=csrng_edn_concurrency_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1905182111 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd b -cm_log /dev/null -cm_name 7.chip_sw_csrng_edn_concurrency.1905182111 |
| Directory | /workspace/7.chip_sw_csrng_edn_concurrency/latest |
| Test location | /workspace/coverage/default/7.chip_sw_lc_ctrl_transition.563637324 |
| Short name | T1291 |
| Test name | |
| Test status | |
| Simulation time | 5279145506 ps |
| CPU time | 470.04 seconds |
| Started | Jun 23 08:18:24 PM PDT 24 |
| Finished | Jun 23 08:26:15 PM PDT 24 |
| Peak memory | 620092 kb |
| Host | smart-dcecdd30-a974-4d46-a984-9ddc420b0310 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=lc_ctrl_transition_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=563637324 -assert nopostproc +UVM_TEST NAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_transition_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul t.vdb -cm_log /dev/null -cm_name 7.chip_sw_lc_ctrl_transition.563637324 |
| Directory | /workspace/7.chip_sw_lc_ctrl_transition/latest |
| Test location | /workspace/coverage/default/7.chip_sw_uart_rand_baudrate.70599103 |
| Short name | T214 |
| Test name | |
| Test status | |
| Simulation time | 8003477080 ps |
| CPU time | 1579.05 seconds |
| Started | Jun 23 08:20:02 PM PDT 24 |
| Finished | Jun 23 08:46:22 PM PDT 24 |
| Peak memory | 619480 kb |
| Host | smart-5021c57c-0dc2-47db-a391-bca34b5bdfd6 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=70599103 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.chip_sw_uart_rand_baudrate.70599103 |
| Directory | /workspace/7.chip_sw_uart_rand_baudrate/latest |
| Test location | /workspace/coverage/default/70.chip_sw_alert_handler_lpg_sleep_mode_alerts.1767097501 |
| Short name | T782 |
| Test name | |
| Test status | |
| Simulation time | 3521006346 ps |
| CPU time | 467.17 seconds |
| Started | Jun 23 08:24:21 PM PDT 24 |
| Finished | Jun 23 08:32:09 PM PDT 24 |
| Peak memory | 642488 kb |
| Host | smart-c8251c60-ee3e-4d8d-9caf-93a857926789 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1767097501 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.chip_ sw_alert_handler_lpg_sleep_mode_alerts.1767097501 |
| Directory | /workspace/70.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/70.chip_sw_all_escalation_resets.4291037514 |
| Short name | T756 |
| Test name | |
| Test status | |
| Simulation time | 6649187176 ps |
| CPU time | 599.85 seconds |
| Started | Jun 23 08:24:41 PM PDT 24 |
| Finished | Jun 23 08:34:41 PM PDT 24 |
| Peak memory | 647576 kb |
| Host | smart-c755193c-645e-48e5-a87f-853f06a698cb |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 4291037514 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.chip_sw_all_escalation_resets.4291037514 |
| Directory | /workspace/70.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/71.chip_sw_all_escalation_resets.4275921573 |
| Short name | T827 |
| Test name | |
| Test status | |
| Simulation time | 4918427072 ps |
| CPU time | 604.56 seconds |
| Started | Jun 23 08:23:25 PM PDT 24 |
| Finished | Jun 23 08:33:30 PM PDT 24 |
| Peak memory | 643596 kb |
| Host | smart-cf128978-da95-4237-85c7-77b130fd9fea |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 4275921573 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.chip_sw_all_escalation_resets.4275921573 |
| Directory | /workspace/71.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/72.chip_sw_alert_handler_lpg_sleep_mode_alerts.3166031192 |
| Short name | T802 |
| Test name | |
| Test status | |
| Simulation time | 4085024120 ps |
| CPU time | 431.65 seconds |
| Started | Jun 23 08:24:06 PM PDT 24 |
| Finished | Jun 23 08:31:18 PM PDT 24 |
| Peak memory | 642556 kb |
| Host | smart-350f6244-517a-4b60-9d8b-973e5137beae |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3166031192 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.chip_ sw_alert_handler_lpg_sleep_mode_alerts.3166031192 |
| Directory | /workspace/72.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/72.chip_sw_all_escalation_resets.1967197796 |
| Short name | T805 |
| Test name | |
| Test status | |
| Simulation time | 4942883912 ps |
| CPU time | 597.27 seconds |
| Started | Jun 23 08:24:17 PM PDT 24 |
| Finished | Jun 23 08:34:15 PM PDT 24 |
| Peak memory | 647988 kb |
| Host | smart-4847f1ce-c6a0-47c8-809d-3599a68d9a7e |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 1967197796 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.chip_sw_all_escalation_resets.1967197796 |
| Directory | /workspace/72.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/73.chip_sw_alert_handler_lpg_sleep_mode_alerts.2119656700 |
| Short name | T762 |
| Test name | |
| Test status | |
| Simulation time | 4437730960 ps |
| CPU time | 412.33 seconds |
| Started | Jun 23 08:24:51 PM PDT 24 |
| Finished | Jun 23 08:31:43 PM PDT 24 |
| Peak memory | 642788 kb |
| Host | smart-16d6805b-4228-4d0f-b96b-c9d23aac3c84 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2119656700 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.chip_ sw_alert_handler_lpg_sleep_mode_alerts.2119656700 |
| Directory | /workspace/73.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/73.chip_sw_all_escalation_resets.2637857472 |
| Short name | T842 |
| Test name | |
| Test status | |
| Simulation time | 6020278570 ps |
| CPU time | 637.84 seconds |
| Started | Jun 23 08:24:02 PM PDT 24 |
| Finished | Jun 23 08:34:40 PM PDT 24 |
| Peak memory | 647992 kb |
| Host | smart-81e6f4b1-1b94-4834-97ee-30954bebfa21 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 2637857472 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.chip_sw_all_escalation_resets.2637857472 |
| Directory | /workspace/73.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/74.chip_sw_alert_handler_lpg_sleep_mode_alerts.2001947310 |
| Short name | T831 |
| Test name | |
| Test status | |
| Simulation time | 3605829484 ps |
| CPU time | 452.99 seconds |
| Started | Jun 23 08:25:11 PM PDT 24 |
| Finished | Jun 23 08:32:45 PM PDT 24 |
| Peak memory | 642616 kb |
| Host | smart-7190e988-1b39-4707-af30-97921fe2abdc |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2001947310 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.chip_ sw_alert_handler_lpg_sleep_mode_alerts.2001947310 |
| Directory | /workspace/74.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/74.chip_sw_all_escalation_resets.3735822133 |
| Short name | T843 |
| Test name | |
| Test status | |
| Simulation time | 4866910416 ps |
| CPU time | 546.98 seconds |
| Started | Jun 23 08:24:01 PM PDT 24 |
| Finished | Jun 23 08:33:09 PM PDT 24 |
| Peak memory | 648124 kb |
| Host | smart-b5c94b34-95b1-4918-bc26-c9efd86b8901 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 3735822133 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.chip_sw_all_escalation_resets.3735822133 |
| Directory | /workspace/74.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/75.chip_sw_alert_handler_lpg_sleep_mode_alerts.4108743590 |
| Short name | T1235 |
| Test name | |
| Test status | |
| Simulation time | 3455999338 ps |
| CPU time | 452.49 seconds |
| Started | Jun 23 08:26:55 PM PDT 24 |
| Finished | Jun 23 08:34:59 PM PDT 24 |
| Peak memory | 642560 kb |
| Host | smart-cd49923e-bddb-4da1-a515-9387943f7082 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4108743590 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.chip_ sw_alert_handler_lpg_sleep_mode_alerts.4108743590 |
| Directory | /workspace/75.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/75.chip_sw_all_escalation_resets.3346171568 |
| Short name | T776 |
| Test name | |
| Test status | |
| Simulation time | 4978371352 ps |
| CPU time | 511.07 seconds |
| Started | Jun 23 08:26:38 PM PDT 24 |
| Finished | Jun 23 08:35:36 PM PDT 24 |
| Peak memory | 648040 kb |
| Host | smart-ca38e95f-0c88-48f2-a9be-de79b9227cec |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 3346171568 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.chip_sw_all_escalation_resets.3346171568 |
| Directory | /workspace/75.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/76.chip_sw_alert_handler_lpg_sleep_mode_alerts.222023550 |
| Short name | T761 |
| Test name | |
| Test status | |
| Simulation time | 3370999096 ps |
| CPU time | 316.26 seconds |
| Started | Jun 23 08:24:19 PM PDT 24 |
| Finished | Jun 23 08:29:35 PM PDT 24 |
| Peak memory | 642508 kb |
| Host | smart-9688f9a5-43ad-435c-a58a-529f73c76a27 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=222023550 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all _escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.chip_s w_alert_handler_lpg_sleep_mode_alerts.222023550 |
| Directory | /workspace/76.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/76.chip_sw_all_escalation_resets.689082409 |
| Short name | T1211 |
| Test name | |
| Test status | |
| Simulation time | 4742053056 ps |
| CPU time | 512.54 seconds |
| Started | Jun 23 08:24:09 PM PDT 24 |
| Finished | Jun 23 08:32:42 PM PDT 24 |
| Peak memory | 615456 kb |
| Host | smart-0b0aa2ed-4813-4447-a8dd-07f959c288c7 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 689082409 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.chip_sw_all_escalation_resets.689082409 |
| Directory | /workspace/76.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/77.chip_sw_alert_handler_lpg_sleep_mode_alerts.3117342423 |
| Short name | T739 |
| Test name | |
| Test status | |
| Simulation time | 3434636104 ps |
| CPU time | 292.52 seconds |
| Started | Jun 23 08:24:14 PM PDT 24 |
| Finished | Jun 23 08:29:07 PM PDT 24 |
| Peak memory | 642384 kb |
| Host | smart-cfe3f85a-debb-4e80-bbd9-7aec1fd62071 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3117342423 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.chip_ sw_alert_handler_lpg_sleep_mode_alerts.3117342423 |
| Directory | /workspace/77.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/77.chip_sw_all_escalation_resets.1528152401 |
| Short name | T845 |
| Test name | |
| Test status | |
| Simulation time | 4963450854 ps |
| CPU time | 543.65 seconds |
| Started | Jun 23 08:25:01 PM PDT 24 |
| Finished | Jun 23 08:34:05 PM PDT 24 |
| Peak memory | 647968 kb |
| Host | smart-51487406-099b-46aa-844a-cfc1220ba1d6 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 1528152401 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.chip_sw_all_escalation_resets.1528152401 |
| Directory | /workspace/77.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/78.chip_sw_alert_handler_lpg_sleep_mode_alerts.3652591467 |
| Short name | T741 |
| Test name | |
| Test status | |
| Simulation time | 3629668292 ps |
| CPU time | 386.79 seconds |
| Started | Jun 23 08:25:18 PM PDT 24 |
| Finished | Jun 23 08:31:45 PM PDT 24 |
| Peak memory | 646828 kb |
| Host | smart-49d73aa9-73d8-4481-bfd7-f3159b5ebe32 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3652591467 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.chip_ sw_alert_handler_lpg_sleep_mode_alerts.3652591467 |
| Directory | /workspace/78.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/78.chip_sw_all_escalation_resets.1271417590 |
| Short name | T407 |
| Test name | |
| Test status | |
| Simulation time | 5795625264 ps |
| CPU time | 564.86 seconds |
| Started | Jun 23 08:26:56 PM PDT 24 |
| Finished | Jun 23 08:36:53 PM PDT 24 |
| Peak memory | 643484 kb |
| Host | smart-aa909143-d0e2-4f67-8373-a276c36fc3d2 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 1271417590 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.chip_sw_all_escalation_resets.1271417590 |
| Directory | /workspace/78.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/79.chip_sw_all_escalation_resets.2515260215 |
| Short name | T361 |
| Test name | |
| Test status | |
| Simulation time | 4513917152 ps |
| CPU time | 514.4 seconds |
| Started | Jun 23 08:25:36 PM PDT 24 |
| Finished | Jun 23 08:34:11 PM PDT 24 |
| Peak memory | 647684 kb |
| Host | smart-32f9164a-9e2b-4c17-a215-b857308dee06 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 2515260215 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.chip_sw_all_escalation_resets.2515260215 |
| Directory | /workspace/79.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/8.chip_sw_alert_handler_lpg_sleep_mode_alerts.4067870584 |
| Short name | T124 |
| Test name | |
| Test status | |
| Simulation time | 4099959920 ps |
| CPU time | 494.53 seconds |
| Started | Jun 23 08:19:34 PM PDT 24 |
| Finished | Jun 23 08:27:49 PM PDT 24 |
| Peak memory | 642324 kb |
| Host | smart-0ea85d77-5b6f-4c7b-aff4-928b45525699 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4067870584 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.chip_s w_alert_handler_lpg_sleep_mode_alerts.4067870584 |
| Directory | /workspace/8.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/8.chip_sw_all_escalation_resets.2037909566 |
| Short name | T688 |
| Test name | |
| Test status | |
| Simulation time | 4143816216 ps |
| CPU time | 620.13 seconds |
| Started | Jun 23 08:17:49 PM PDT 24 |
| Finished | Jun 23 08:28:10 PM PDT 24 |
| Peak memory | 643504 kb |
| Host | smart-8a7e959b-c3a7-496d-a4f2-f77ffc9e5c5e |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 2037909566 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.chip_sw_all_escalation_resets.2037909566 |
| Directory | /workspace/8.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/8.chip_sw_csrng_edn_concurrency.235175809 |
| Short name | T1172 |
| Test name | |
| Test status | |
| Simulation time | 20466417480 ps |
| CPU time | 4665.3 seconds |
| Started | Jun 23 08:18:57 PM PDT 24 |
| Finished | Jun 23 09:36:43 PM PDT 24 |
| Peak memory | 607908 kb |
| Host | smart-59e6c954-1fd4-44ec-a884-998fbdc7cf8f |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=140_000_000 +rng_srate_value_min=15 +rng_srate_value_max=20 +accelerate_cold_power_up_time=3 +accelerate_r egulators_power_up_time=2 +sw_build_device=sim_dv +sw_images=csrng_edn_concurrency_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=235175809 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.chip_sw_csrng_edn_concurrency.235175809 |
| Directory | /workspace/8.chip_sw_csrng_edn_concurrency/latest |
| Test location | /workspace/coverage/default/8.chip_sw_lc_ctrl_transition.3421460725 |
| Short name | T1212 |
| Test name | |
| Test status | |
| Simulation time | 6767115341 ps |
| CPU time | 475.19 seconds |
| Started | Jun 23 08:19:28 PM PDT 24 |
| Finished | Jun 23 08:27:25 PM PDT 24 |
| Peak memory | 620092 kb |
| Host | smart-85f45d71-2838-4747-94b3-f38b5878d619 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=lc_ctrl_transition_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3421460725 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_transition_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau lt.vdb -cm_log /dev/null -cm_name 8.chip_sw_lc_ctrl_transition.3421460725 |
| Directory | /workspace/8.chip_sw_lc_ctrl_transition/latest |
| Test location | /workspace/coverage/default/8.chip_sw_uart_rand_baudrate.3145385797 |
| Short name | T980 |
| Test name | |
| Test status | |
| Simulation time | 8783494660 ps |
| CPU time | 1382.5 seconds |
| Started | Jun 23 08:19:20 PM PDT 24 |
| Finished | Jun 23 08:42:24 PM PDT 24 |
| Peak memory | 619768 kb |
| Host | smart-1023ff3c-01b5-4e1b-b3e1-f735ef8872a3 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=3145385797 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.chip_sw_uart_rand_baudrate.3145385797 |
| Directory | /workspace/8.chip_sw_uart_rand_baudrate/latest |
| Test location | /workspace/coverage/default/80.chip_sw_alert_handler_lpg_sleep_mode_alerts.813647103 |
| Short name | T840 |
| Test name | |
| Test status | |
| Simulation time | 3892763360 ps |
| CPU time | 382.96 seconds |
| Started | Jun 23 08:25:08 PM PDT 24 |
| Finished | Jun 23 08:31:31 PM PDT 24 |
| Peak memory | 646836 kb |
| Host | smart-27d5cce0-b073-4c50-a2f3-5f9499570bad |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=813647103 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all _escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 80.chip_s w_alert_handler_lpg_sleep_mode_alerts.813647103 |
| Directory | /workspace/80.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/80.chip_sw_all_escalation_resets.878294883 |
| Short name | T1352 |
| Test name | |
| Test status | |
| Simulation time | 5947678096 ps |
| CPU time | 593.18 seconds |
| Started | Jun 23 08:24:13 PM PDT 24 |
| Finished | Jun 23 08:34:07 PM PDT 24 |
| Peak memory | 647700 kb |
| Host | smart-d94441cc-c3df-47c5-b65e-d842a30f6b53 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 878294883 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 80.chip_sw_all_escalation_resets.878294883 |
| Directory | /workspace/80.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/81.chip_sw_all_escalation_resets.445084569 |
| Short name | T783 |
| Test name | |
| Test status | |
| Simulation time | 5818139418 ps |
| CPU time | 628.19 seconds |
| Started | Jun 23 08:25:42 PM PDT 24 |
| Finished | Jun 23 08:36:11 PM PDT 24 |
| Peak memory | 647944 kb |
| Host | smart-9b0fc697-8979-4e01-9eaa-291af53154e6 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 445084569 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 81.chip_sw_all_escalation_resets.445084569 |
| Directory | /workspace/81.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/82.chip_sw_alert_handler_lpg_sleep_mode_alerts.2004707538 |
| Short name | T799 |
| Test name | |
| Test status | |
| Simulation time | 3847892712 ps |
| CPU time | 336.72 seconds |
| Started | Jun 23 08:25:11 PM PDT 24 |
| Finished | Jun 23 08:30:48 PM PDT 24 |
| Peak memory | 642532 kb |
| Host | smart-6cfb1a9d-2d09-46a0-9dba-511459815412 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2004707538 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 82.chip_ sw_alert_handler_lpg_sleep_mode_alerts.2004707538 |
| Directory | /workspace/82.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/82.chip_sw_all_escalation_resets.3425005324 |
| Short name | T792 |
| Test name | |
| Test status | |
| Simulation time | 5500291152 ps |
| CPU time | 533.57 seconds |
| Started | Jun 23 08:25:30 PM PDT 24 |
| Finished | Jun 23 08:34:24 PM PDT 24 |
| Peak memory | 648128 kb |
| Host | smart-05cf84fd-3f51-42f2-81e4-1e267a56a555 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 3425005324 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 82.chip_sw_all_escalation_resets.3425005324 |
| Directory | /workspace/82.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/83.chip_sw_alert_handler_lpg_sleep_mode_alerts.3827758591 |
| Short name | T819 |
| Test name | |
| Test status | |
| Simulation time | 4013410528 ps |
| CPU time | 331.18 seconds |
| Started | Jun 23 08:25:07 PM PDT 24 |
| Finished | Jun 23 08:30:39 PM PDT 24 |
| Peak memory | 642436 kb |
| Host | smart-541cbaa3-d087-40f7-b524-e4d6430d8338 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3827758591 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 83.chip_ sw_alert_handler_lpg_sleep_mode_alerts.3827758591 |
| Directory | /workspace/83.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/83.chip_sw_all_escalation_resets.2043570555 |
| Short name | T347 |
| Test name | |
| Test status | |
| Simulation time | 5098536016 ps |
| CPU time | 747.15 seconds |
| Started | Jun 23 08:24:57 PM PDT 24 |
| Finished | Jun 23 08:37:25 PM PDT 24 |
| Peak memory | 617184 kb |
| Host | smart-688e8adb-72cc-4f0c-be4b-e6513e284ea7 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 2043570555 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 83.chip_sw_all_escalation_resets.2043570555 |
| Directory | /workspace/83.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/84.chip_sw_alert_handler_lpg_sleep_mode_alerts.3529836022 |
| Short name | T846 |
| Test name | |
| Test status | |
| Simulation time | 3311979464 ps |
| CPU time | 389.68 seconds |
| Started | Jun 23 08:25:01 PM PDT 24 |
| Finished | Jun 23 08:31:31 PM PDT 24 |
| Peak memory | 642508 kb |
| Host | smart-6a9fbc51-87a2-4edc-9d24-6d2f46410f77 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3529836022 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 84.chip_ sw_alert_handler_lpg_sleep_mode_alerts.3529836022 |
| Directory | /workspace/84.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/84.chip_sw_all_escalation_resets.742077602 |
| Short name | T744 |
| Test name | |
| Test status | |
| Simulation time | 5285173512 ps |
| CPU time | 642.99 seconds |
| Started | Jun 23 08:26:45 PM PDT 24 |
| Finished | Jun 23 08:37:57 PM PDT 24 |
| Peak memory | 647708 kb |
| Host | smart-3683d9b6-a267-47b9-b8df-7ed6115c205f |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 742077602 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 84.chip_sw_all_escalation_resets.742077602 |
| Directory | /workspace/84.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/85.chip_sw_alert_handler_lpg_sleep_mode_alerts.1982672620 |
| Short name | T965 |
| Test name | |
| Test status | |
| Simulation time | 4243640102 ps |
| CPU time | 380.52 seconds |
| Started | Jun 23 08:26:16 PM PDT 24 |
| Finished | Jun 23 08:32:41 PM PDT 24 |
| Peak memory | 615524 kb |
| Host | smart-0badeb7c-0fab-48c3-a30a-2e52ab4b4728 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1982672620 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 85.chip_ sw_alert_handler_lpg_sleep_mode_alerts.1982672620 |
| Directory | /workspace/85.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/85.chip_sw_all_escalation_resets.2146315705 |
| Short name | T1051 |
| Test name | |
| Test status | |
| Simulation time | 6266475472 ps |
| CPU time | 581.44 seconds |
| Started | Jun 23 08:24:50 PM PDT 24 |
| Finished | Jun 23 08:34:32 PM PDT 24 |
| Peak memory | 643764 kb |
| Host | smart-fa7e0d35-5ddd-4890-8d7c-2ab76b6b5676 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 2146315705 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 85.chip_sw_all_escalation_resets.2146315705 |
| Directory | /workspace/85.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/86.chip_sw_alert_handler_lpg_sleep_mode_alerts.2763501695 |
| Short name | T414 |
| Test name | |
| Test status | |
| Simulation time | 3459111604 ps |
| CPU time | 355.43 seconds |
| Started | Jun 23 08:24:56 PM PDT 24 |
| Finished | Jun 23 08:30:52 PM PDT 24 |
| Peak memory | 642404 kb |
| Host | smart-21e29ede-64f3-4f65-befe-c0ce9f2b69c6 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2763501695 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 86.chip_ sw_alert_handler_lpg_sleep_mode_alerts.2763501695 |
| Directory | /workspace/86.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/86.chip_sw_all_escalation_resets.691024171 |
| Short name | T734 |
| Test name | |
| Test status | |
| Simulation time | 6099990480 ps |
| CPU time | 730.01 seconds |
| Started | Jun 23 08:26:13 PM PDT 24 |
| Finished | Jun 23 08:38:26 PM PDT 24 |
| Peak memory | 648220 kb |
| Host | smart-49d94093-199b-44b4-bd90-b6517fd3a766 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 691024171 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 86.chip_sw_all_escalation_resets.691024171 |
| Directory | /workspace/86.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/87.chip_sw_alert_handler_lpg_sleep_mode_alerts.1319230482 |
| Short name | T835 |
| Test name | |
| Test status | |
| Simulation time | 3473366812 ps |
| CPU time | 350.62 seconds |
| Started | Jun 23 08:29:53 PM PDT 24 |
| Finished | Jun 23 08:36:11 PM PDT 24 |
| Peak memory | 642412 kb |
| Host | smart-e147c929-ade3-423e-98b5-f1172921d99b |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1319230482 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 87.chip_ sw_alert_handler_lpg_sleep_mode_alerts.1319230482 |
| Directory | /workspace/87.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/87.chip_sw_all_escalation_resets.508494012 |
| Short name | T810 |
| Test name | |
| Test status | |
| Simulation time | 4991385292 ps |
| CPU time | 525.33 seconds |
| Started | Jun 23 08:26:26 PM PDT 24 |
| Finished | Jun 23 08:35:29 PM PDT 24 |
| Peak memory | 647980 kb |
| Host | smart-40b65da8-78c2-4114-bd07-227272c335c3 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 508494012 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 87.chip_sw_all_escalation_resets.508494012 |
| Directory | /workspace/87.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/88.chip_sw_alert_handler_lpg_sleep_mode_alerts.1196202501 |
| Short name | T709 |
| Test name | |
| Test status | |
| Simulation time | 3597915316 ps |
| CPU time | 273.65 seconds |
| Started | Jun 23 08:26:08 PM PDT 24 |
| Finished | Jun 23 08:30:43 PM PDT 24 |
| Peak memory | 642420 kb |
| Host | smart-98d4a7db-543c-40e4-8979-7a9b8cafe55c |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1196202501 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 88.chip_ sw_alert_handler_lpg_sleep_mode_alerts.1196202501 |
| Directory | /workspace/88.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/88.chip_sw_all_escalation_resets.956638913 |
| Short name | T256 |
| Test name | |
| Test status | |
| Simulation time | 4762537280 ps |
| CPU time | 356.43 seconds |
| Started | Jun 23 08:26:19 PM PDT 24 |
| Finished | Jun 23 08:32:22 PM PDT 24 |
| Peak memory | 648208 kb |
| Host | smart-e12c1229-7d4b-4f11-afbb-494464e97ebf |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 956638913 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 88.chip_sw_all_escalation_resets.956638913 |
| Directory | /workspace/88.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/89.chip_sw_alert_handler_lpg_sleep_mode_alerts.598524828 |
| Short name | T808 |
| Test name | |
| Test status | |
| Simulation time | 4119940272 ps |
| CPU time | 342.14 seconds |
| Started | Jun 23 08:25:18 PM PDT 24 |
| Finished | Jun 23 08:31:00 PM PDT 24 |
| Peak memory | 642524 kb |
| Host | smart-48aca434-614a-4cc7-a78d-01f4ee4c3899 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=598524828 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all _escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 89.chip_s w_alert_handler_lpg_sleep_mode_alerts.598524828 |
| Directory | /workspace/89.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/89.chip_sw_all_escalation_resets.4274678252 |
| Short name | T1245 |
| Test name | |
| Test status | |
| Simulation time | 5618640774 ps |
| CPU time | 547.85 seconds |
| Started | Jun 23 08:26:30 PM PDT 24 |
| Finished | Jun 23 08:35:59 PM PDT 24 |
| Peak memory | 648088 kb |
| Host | smart-7740819b-e386-4601-8b2c-eff8f72fe263 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 4274678252 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 89.chip_sw_all_escalation_resets.4274678252 |
| Directory | /workspace/89.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/9.chip_sw_csrng_edn_concurrency.1814948180 |
| Short name | T1257 |
| Test name | |
| Test status | |
| Simulation time | 10976615216 ps |
| CPU time | 3342.78 seconds |
| Started | Jun 23 08:21:25 PM PDT 24 |
| Finished | Jun 23 09:17:10 PM PDT 24 |
| Peak memory | 607332 kb |
| Host | smart-938d527d-f94c-4da3-9a4d-b498e314b98a |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=140_000_000 +rng_srate_value_min=15 +rng_srate_value_max=20 +accelerate_cold_power_up_time=3 +accelerate_r egulators_power_up_time=2 +sw_build_device=sim_dv +sw_images=csrng_edn_concurrency_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1814948180 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd b -cm_log /dev/null -cm_name 9.chip_sw_csrng_edn_concurrency.1814948180 |
| Directory | /workspace/9.chip_sw_csrng_edn_concurrency/latest |
| Test location | /workspace/coverage/default/9.chip_sw_lc_ctrl_transition.722849876 |
| Short name | T1302 |
| Test name | |
| Test status | |
| Simulation time | 6178014919 ps |
| CPU time | 454.78 seconds |
| Started | Jun 23 08:18:43 PM PDT 24 |
| Finished | Jun 23 08:26:18 PM PDT 24 |
| Peak memory | 618704 kb |
| Host | smart-88ecc3a6-ed54-4e09-93cd-bf1f7a8213ad |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=lc_ctrl_transition_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=722849876 -assert nopostproc +UVM_TEST NAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_transition_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul t.vdb -cm_log /dev/null -cm_name 9.chip_sw_lc_ctrl_transition.722849876 |
| Directory | /workspace/9.chip_sw_lc_ctrl_transition/latest |
| Test location | /workspace/coverage/default/9.chip_sw_uart_rand_baudrate.4292225072 |
| Short name | T406 |
| Test name | |
| Test status | |
| Simulation time | 3843348834 ps |
| CPU time | 573.35 seconds |
| Started | Jun 23 08:19:15 PM PDT 24 |
| Finished | Jun 23 08:28:49 PM PDT 24 |
| Peak memory | 619036 kb |
| Host | smart-93f8880b-c04a-4435-8511-d5028646f770 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=4292225072 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.chip_sw_uart_rand_baudrate.4292225072 |
| Directory | /workspace/9.chip_sw_uart_rand_baudrate/latest |
| Test location | /workspace/coverage/default/90.chip_sw_all_escalation_resets.3123822389 |
| Short name | T790 |
| Test name | |
| Test status | |
| Simulation time | 5081093848 ps |
| CPU time | 562.24 seconds |
| Started | Jun 23 08:26:10 PM PDT 24 |
| Finished | Jun 23 08:35:34 PM PDT 24 |
| Peak memory | 647712 kb |
| Host | smart-f44d116c-a800-4460-a1cc-fdb4bcbd5a1c |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 3123822389 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 90.chip_sw_all_escalation_resets.3123822389 |
| Directory | /workspace/90.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/92.chip_sw_all_escalation_resets.4081456634 |
| Short name | T757 |
| Test name | |
| Test status | |
| Simulation time | 5577066936 ps |
| CPU time | 618.71 seconds |
| Started | Jun 23 08:25:51 PM PDT 24 |
| Finished | Jun 23 08:36:11 PM PDT 24 |
| Peak memory | 647724 kb |
| Host | smart-c1bb95ea-171b-4dfb-a4b4-e8f653080364 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 4081456634 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 92.chip_sw_all_escalation_resets.4081456634 |
| Directory | /workspace/92.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/93.chip_sw_all_escalation_resets.4128635685 |
| Short name | T276 |
| Test name | |
| Test status | |
| Simulation time | 3941052192 ps |
| CPU time | 436.67 seconds |
| Started | Jun 23 08:26:15 PM PDT 24 |
| Finished | Jun 23 08:33:35 PM PDT 24 |
| Peak memory | 647960 kb |
| Host | smart-06be1c4a-3b1d-4848-a5e0-7a9c7bda8779 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 4128635685 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 93.chip_sw_all_escalation_resets.4128635685 |
| Directory | /workspace/93.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/94.chip_sw_all_escalation_resets.1034393469 |
| Short name | T745 |
| Test name | |
| Test status | |
| Simulation time | 5687671944 ps |
| CPU time | 569.16 seconds |
| Started | Jun 23 08:25:52 PM PDT 24 |
| Finished | Jun 23 08:35:21 PM PDT 24 |
| Peak memory | 647980 kb |
| Host | smart-664af375-c2a1-4206-894c-d5aaa78595b3 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 1034393469 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 94.chip_sw_all_escalation_resets.1034393469 |
| Directory | /workspace/94.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/95.chip_sw_all_escalation_resets.2207186260 |
| Short name | T764 |
| Test name | |
| Test status | |
| Simulation time | 5625720384 ps |
| CPU time | 679.65 seconds |
| Started | Jun 23 08:25:57 PM PDT 24 |
| Finished | Jun 23 08:37:17 PM PDT 24 |
| Peak memory | 648276 kb |
| Host | smart-bbb6cae4-5931-4fb5-9f31-3e4eef09b328 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 2207186260 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 95.chip_sw_all_escalation_resets.2207186260 |
| Directory | /workspace/95.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/96.chip_sw_all_escalation_resets.250779818 |
| Short name | T344 |
| Test name | |
| Test status | |
| Simulation time | 4528257688 ps |
| CPU time | 562.65 seconds |
| Started | Jun 23 08:26:24 PM PDT 24 |
| Finished | Jun 23 08:36:00 PM PDT 24 |
| Peak memory | 648108 kb |
| Host | smart-d0ff63aa-9f28-49a2-b0c4-f062092855f0 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 250779818 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 96.chip_sw_all_escalation_resets.250779818 |
| Directory | /workspace/96.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/97.chip_sw_all_escalation_resets.393219507 |
| Short name | T291 |
| Test name | |
| Test status | |
| Simulation time | 5062841206 ps |
| CPU time | 600.49 seconds |
| Started | Jun 23 08:26:47 PM PDT 24 |
| Finished | Jun 23 08:37:18 PM PDT 24 |
| Peak memory | 647776 kb |
| Host | smart-405a30bc-aeb1-4c8c-80af-110b1afd2104 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 393219507 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 97.chip_sw_all_escalation_resets.393219507 |
| Directory | /workspace/97.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/98.chip_sw_all_escalation_resets.3159718362 |
| Short name | T505 |
| Test name | |
| Test status | |
| Simulation time | 5671603168 ps |
| CPU time | 685.43 seconds |
| Started | Jun 23 08:25:45 PM PDT 24 |
| Finished | Jun 23 08:37:11 PM PDT 24 |
| Peak memory | 647792 kb |
| Host | smart-ded4f228-b14a-44f6-b5ea-4d82a41a44ad |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 3159718362 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 98.chip_sw_all_escalation_resets.3159718362 |
| Directory | /workspace/98.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/99.chip_sw_all_escalation_resets.31274586 |
| Short name | T343 |
| Test name | |
| Test status | |
| Simulation time | 4834504536 ps |
| CPU time | 417.89 seconds |
| Started | Jun 23 08:25:44 PM PDT 24 |
| Finished | Jun 23 08:32:43 PM PDT 24 |
| Peak memory | 643764 kb |
| Host | smart-01336019-f9cb-4356-9ea1-02bd2f2a9938 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 31274586 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 99.chip_sw_all_escalation_resets.31274586 |
| Directory | /workspace/99.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/pad_ctrl_test_mode/1.chip_padctrl_attributes.587047245 |
| Short name | T44 |
| Test name | |
| Test status | |
| Simulation time | 5031524168 ps |
| CPU time | 331.95 seconds |
| Started | Jun 23 08:19:42 PM PDT 24 |
| Finished | Jun 23 08:25:15 PM PDT 24 |
| Peak memory | 641364 kb |
| Host | smart-17a10b62-2050-4431-8388-f7b72fdf4c1e |
| User | root |
| Command | /workspace/pad_ctrl_test_mode/simv +use_otp_image=OtpTypeLcStProd +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=587047245 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TES T_SEQ=chip_padctrl_attributes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/pad_ctrl_test_mode.vdb -cm_log /dev/n ull -cm_name 1.chip_padctrl_attributes.587047245 |
| Directory | /workspace/1.chip_padctrl_attributes/latest |
| Test location | /workspace/coverage/pad_ctrl_test_mode/2.chip_padctrl_attributes.3676098104 |
| Short name | T180 |
| Test name | |
| Test status | |
| Simulation time | 4491296904 ps |
| CPU time | 265.08 seconds |
| Started | Jun 23 08:19:41 PM PDT 24 |
| Finished | Jun 23 08:24:06 PM PDT 24 |
| Peak memory | 640580 kb |
| Host | smart-bb0b89fc-8d4f-4b91-8097-9e8aafde2c30 |
| User | root |
| Command | /workspace/pad_ctrl_test_mode/simv +use_otp_image=OtpTypeLcStProd +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3676098104 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TE ST_SEQ=chip_padctrl_attributes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/pad_ctrl_test_mode.vdb -cm_log /dev/ null -cm_name 2.chip_padctrl_attributes.3676098104 |
| Directory | /workspace/2.chip_padctrl_attributes/latest |
| Test location | /workspace/coverage/pad_ctrl_test_mode/3.chip_padctrl_attributes.3888883063 |
| Short name | T183 |
| Test name | |
| Test status | |
| Simulation time | 4973085734 ps |
| CPU time | 225.71 seconds |
| Started | Jun 23 08:19:49 PM PDT 24 |
| Finished | Jun 23 08:23:35 PM PDT 24 |
| Peak memory | 640648 kb |
| Host | smart-a247b5aa-a8bd-40db-a9cc-311e8b69b011 |
| User | root |
| Command | /workspace/pad_ctrl_test_mode/simv +use_otp_image=OtpTypeLcStProd +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3888883063 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TE ST_SEQ=chip_padctrl_attributes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/pad_ctrl_test_mode.vdb -cm_log /dev/ null -cm_name 3.chip_padctrl_attributes.3888883063 |
| Directory | /workspace/3.chip_padctrl_attributes/latest |
| Test location | /workspace/coverage/pad_ctrl_test_mode/4.chip_padctrl_attributes.3948511355 |
| Short name | T43 |
| Test name | |
| Test status | |
| Simulation time | 5673061766 ps |
| CPU time | 300.45 seconds |
| Started | Jun 23 08:19:58 PM PDT 24 |
| Finished | Jun 23 08:24:59 PM PDT 24 |
| Peak memory | 648856 kb |
| Host | smart-3d519f4d-029c-4dee-a6c5-19cc4bc27d13 |
| User | root |
| Command | /workspace/pad_ctrl_test_mode/simv +use_otp_image=OtpTypeLcStProd +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3948511355 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TE ST_SEQ=chip_padctrl_attributes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/pad_ctrl_test_mode.vdb -cm_log /dev/ null -cm_name 4.chip_padctrl_attributes.3948511355 |
| Directory | /workspace/4.chip_padctrl_attributes/latest |
| Test location | /workspace/coverage/pad_ctrl_test_mode/5.chip_padctrl_attributes.4242834143 |
| Short name | T188 |
| Test name | |
| Test status | |
| Simulation time | 4588023057 ps |
| CPU time | 273.66 seconds |
| Started | Jun 23 08:20:00 PM PDT 24 |
| Finished | Jun 23 08:24:34 PM PDT 24 |
| Peak memory | 640584 kb |
| Host | smart-5f868e4d-f38b-475c-b1eb-4d07a940bc8f |
| User | root |
| Command | /workspace/pad_ctrl_test_mode/simv +use_otp_image=OtpTypeLcStProd +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4242834143 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TE ST_SEQ=chip_padctrl_attributes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/pad_ctrl_test_mode.vdb -cm_log /dev/ null -cm_name 5.chip_padctrl_attributes.4242834143 |
| Directory | /workspace/5.chip_padctrl_attributes/latest |
| Test location | /workspace/coverage/pad_ctrl_test_mode/6.chip_padctrl_attributes.2449375178 |
| Short name | T181 |
| Test name | |
| Test status | |
| Simulation time | 5078961780 ps |
| CPU time | 306.91 seconds |
| Started | Jun 23 08:20:00 PM PDT 24 |
| Finished | Jun 23 08:25:08 PM PDT 24 |
| Peak memory | 640596 kb |
| Host | smart-57deeadf-3efc-4355-8a2a-a51b2972b8ff |
| User | root |
| Command | /workspace/pad_ctrl_test_mode/simv +use_otp_image=OtpTypeLcStProd +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2449375178 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TE ST_SEQ=chip_padctrl_attributes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/pad_ctrl_test_mode.vdb -cm_log /dev/ null -cm_name 6.chip_padctrl_attributes.2449375178 |
| Directory | /workspace/6.chip_padctrl_attributes/latest |
| Test location | /workspace/coverage/pad_ctrl_test_mode/7.chip_padctrl_attributes.1602427009 |
| Short name | T184 |
| Test name | |
| Test status | |
| Simulation time | 5013919410 ps |
| CPU time | 445.1 seconds |
| Started | Jun 23 08:20:06 PM PDT 24 |
| Finished | Jun 23 08:27:31 PM PDT 24 |
| Peak memory | 650508 kb |
| Host | smart-b043097d-1a45-4b4c-8c29-6d876d591edf |
| User | root |
| Command | /workspace/pad_ctrl_test_mode/simv +use_otp_image=OtpTypeLcStProd +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1602427009 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TE ST_SEQ=chip_padctrl_attributes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/pad_ctrl_test_mode.vdb -cm_log /dev/ null -cm_name 7.chip_padctrl_attributes.1602427009 |
| Directory | /workspace/7.chip_padctrl_attributes/latest |
| Test location | /workspace/coverage/pad_ctrl_test_mode/8.chip_padctrl_attributes.2027880926 |
| Short name | T182 |
| Test name | |
| Test status | |
| Simulation time | 4730408265 ps |
| CPU time | 326.24 seconds |
| Started | Jun 23 08:20:02 PM PDT 24 |
| Finished | Jun 23 08:25:29 PM PDT 24 |
| Peak memory | 649800 kb |
| Host | smart-7409fd91-69f1-42a2-a047-65eb4f5cb7c8 |
| User | root |
| Command | /workspace/pad_ctrl_test_mode/simv +use_otp_image=OtpTypeLcStProd +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2027880926 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TE ST_SEQ=chip_padctrl_attributes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/pad_ctrl_test_mode.vdb -cm_log /dev/ null -cm_name 8.chip_padctrl_attributes.2027880926 |
| Directory | /workspace/8.chip_padctrl_attributes/latest |
| 0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |