CHIP Simulation Results

Tuesday June 25 2024 23:02:40 UTC

GitHub Revision: `3fd3528c8c`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 44317642457786780768002458033256869318159334982704173107202396839344093642292

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	chip_sw_example_tests	chip_sw_example_flash	5.227m	2.771ms	3	3	100.00
		chip_sw_example_rom	2.621m	1.971ms	3	3	100.00
		chip_sw_example_manufacturer	4.298m	2.985ms	3	3	100.00
		chip_sw_example_concurrency	5.438m	2.910ms	3	3	100.00
V1	csr_hw_reset	chip_csr_hw_reset	7.194m	7.603ms	5	5	100.00
V1	csr_rw	chip_csr_rw	13.885m	6.452ms	20	20	100.00
V1	csr_bit_bash	chip_csr_bit_bash	1.746h	58.334ms	5	5	100.00
V1	csr_aliasing	chip_csr_aliasing	2.909h	71.299ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	chip_csr_mem_rw_with_rand_reset	2.154m	2.375ms	0	20	0.00
V1	regwen_csr_and_corresponding_lockable_csr	chip_csr_aliasing	2.909h	71.299ms	5	5	100.00
		chip_csr_rw	13.885m	6.452ms	20	20	100.00
V1	xbar_smoke	xbar_smoke	11.450s	252.841us	100	100	100.00
V1	chip_sw_gpio_out	chip_sw_gpio	9.286m	4.070ms	3	3	100.00
V1	chip_sw_gpio_in	chip_sw_gpio	9.286m	4.070ms	3	3	100.00
V1	chip_sw_gpio_irq	chip_sw_gpio	9.286m	4.070ms	3	3	100.00
V1	chip_sw_uart_tx_rx	chip_sw_uart_tx_rx	11.488m	3.916ms	5	5	100.00
V1	chip_sw_uart_rx_overflow	chip_sw_uart_tx_rx	11.488m	3.916ms	5	5	100.00
		chip_sw_uart_tx_rx_idx1	12.553m	4.192ms	5	5	100.00
		chip_sw_uart_tx_rx_idx2	13.102m	4.473ms	5	5	100.00
		chip_sw_uart_tx_rx_idx3	12.194m	4.261ms	5	5	100.00
V1	chip_sw_uart_baud_rate	chip_sw_uart_rand_baudrate	52.779m	13.270ms	20	20	100.00
V1	chip_sw_uart_tx_rx_alt_clk_freq	chip_sw_uart_tx_rx_alt_clk_freq	33.615m	9.199ms	5	5	100.00
		chip_sw_uart_tx_rx_alt_clk_freq_low_speed	41.205m	13.275ms	5	5	100.00
V1		TOTAL			200	220	90.91
V2	chip_pin_mux	chip_padctrl_attributes	5.960m	6.102ms	10	10	100.00
V2	chip_padctrl_attributes	chip_padctrl_attributes	5.960m	6.102ms	10	10	100.00
V2	chip_sw_sleep_pin_mio_dio_val	chip_sw_sleep_pin_mio_dio_val	5.027m	2.471ms	3	3	100.00
V2	chip_sw_sleep_pin_wake	chip_sw_sleep_pin_wake	10.783m	5.167ms	3	3	100.00
V2	chip_sw_sleep_pin_retention	chip_sw_sleep_pin_retention	5.686m	3.135ms	3	3	100.00
V2	chip_sw_tap_strap_sampling	chip_tap_straps_dev	14.871m	8.271ms	5	5	100.00
		chip_tap_straps_testunlock0	27.171m	14.979ms	4	5	80.00
		chip_tap_straps_rma	33.663m	16.794ms	3	5	60.00
		chip_tap_straps_prod	25.084m	14.347ms	4	5	80.00
V2	chip_sw_pattgen_ios	chip_sw_pattgen_ios	4.258m	2.577ms	3	3	100.00
V2	chip_sw_sleep_pwm_pulses	chip_sw_sleep_pwm_pulses	24.460m	8.855ms	3	3	100.00
V2	chip_sw_data_integrity	chip_sw_data_integrity_escalation	14.023m	5.275ms	6	6	100.00
V2	chip_sw_instruction_integrity	chip_sw_data_integrity_escalation	14.023m	5.275ms	6	6	100.00
V2	chip_sw_ast_clk_outputs	chip_sw_ast_clk_outputs	17.308m	7.911ms	3	3	100.00
V2	chip_sw_ast_clk_rst_inputs	chip_sw_ast_clk_rst_inputs	47.558m	16.615ms	1	3	33.33
V2	chip_sw_ast_sys_clk_jitter	chip_sw_flash_ctrl_ops_jitter_en	14.496m	4.400ms	3	3	100.00
		chip_sw_flash_ctrl_access_jitter_en	18.759m	6.409ms	3	3	100.00
		chip_sw_otbn_ecdsa_op_irq_jitter_en	1.177h	18.539ms	3	3	100.00
		chip_sw_aes_enc_jitter_en	6.696m	2.846ms	3	3	100.00
		chip_sw_edn_entropy_reqs_jitter	20.720m	6.452ms	3	3	100.00
		chip_sw_hmac_enc_jitter_en	5.296m	3.247ms	3	3	100.00
		chip_sw_keymgr_key_derivation_jitter_en	42.062m	9.758ms	3	3	100.00
		chip_sw_kmac_mode_kmac_jitter_en	6.311m	3.244ms	3	3	100.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en	13.767m	4.648ms	3	3	100.00
		chip_sw_clkmgr_jitter	5.452m	3.596ms	3	3	100.00
V2	chip_sw_ast_usb_clk_calib	chip_sw_usb_ast_clk_calib	4.869m	2.485ms	1	1	100.00
V2	chip_sw_sensor_ctrl_ast_alerts	chip_sw_sensor_ctrl_alert	14.752m	6.182ms	5	5	100.00
		chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup	8.839m	5.334ms	3	3	100.00
V2	chip_sw_sensor_ctrl_ast_status	chip_sw_sensor_ctrl_status	5.659m	3.726ms	3	3	100.00
V2	chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup	chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup	8.839m	5.334ms	3	3	100.00
V2	chip_sw_smoketest	chip_sw_flash_scrambling_smoketest	4.358m	3.424ms	3	3	100.00
		chip_sw_aes_smoketest	4.561m	3.644ms	3	3	100.00
		chip_sw_aon_timer_smoketest	7.135m	2.962ms	3	3	100.00
		chip_sw_clkmgr_smoketest	5.613m	3.342ms	3	3	100.00
		chip_sw_csrng_smoketest	4.883m	3.308ms	3	3	100.00
		chip_sw_entropy_src_smoketest	10.154m	4.071ms	3	3	100.00
		chip_sw_gpio_smoketest	5.016m	2.536ms	3	3	100.00
		chip_sw_hmac_smoketest	6.754m	3.647ms	3	3	100.00
		chip_sw_kmac_smoketest	5.719m	3.523ms	3	3	100.00
		chip_sw_otbn_smoketest	20.177m	5.959ms	3	3	100.00
		chip_sw_pwrmgr_smoketest	9.212m	6.411ms	3	3	100.00
		chip_sw_pwrmgr_usbdev_smoketest	8.558m	6.311ms	3	3	100.00
		chip_sw_rv_plic_smoketest	4.461m	2.540ms	3	3	100.00
		chip_sw_rv_timer_smoketest	4.842m	2.984ms	3	3	100.00
		chip_sw_rstmgr_smoketest	5.476m	2.804ms	3	3	100.00
		chip_sw_sram_ctrl_smoketest	4.442m	2.399ms	3	3	100.00
		chip_sw_uart_smoketest	4.544m	2.699ms	3	3	100.00
V2	chip_sw_otp_smoketest	chip_sw_otp_ctrl_smoketest	5.734m	2.428ms	3	3	100.00
V2	chip_sw_rom_functests	rom_keymgr_functest	12.789m	4.870ms	3	3	100.00
V2	chip_sw_boot	chip_sw_uart_tx_rx_bootstrap	4.097h	78.909ms	3	3	100.00
V2	chip_sw_secure_boot	rom_e2e_smoke	1.065h	14.525ms	3	3	100.00
V2	chip_sw_rom_raw_unlock	rom_raw_unlock	5.374h	205.059ms	0	3	0.00
V2	chip_sw_power_idle_load	chip_sw_power_idle_load	11.682m	3.949ms	3	3	100.00
V2	chip_sw_power_sleep_load	chip_sw_power_sleep_load	13.098m	9.891ms	3	3	100.00
V2	chip_sw_exit_test_unlocked_bootstrap	chip_sw_exit_test_unlocked_bootstrap	3.324h	58.055ms	3	3	100.00
V2	chip_sw_inject_scramble_seed	chip_sw_inject_scramble_seed	3.261h	63.795ms	3	3	100.00
V2	tl_d_oob_addr_access	chip_tl_errors	10.026m	5.044ms	30	30	100.00
V2	tl_d_illegal_access	chip_tl_errors	10.026m	5.044ms	30	30	100.00
V2	tl_d_outstanding_access	chip_csr_aliasing	2.909h	71.299ms	5	5	100.00
		chip_same_csr_outstanding	1.168h	32.244ms	20	20	100.00
		chip_csr_hw_reset	7.194m	7.603ms	5	5	100.00
		chip_csr_rw	13.885m	6.452ms	20	20	100.00
V2	tl_d_partial_access	chip_csr_aliasing	2.909h	71.299ms	5	5	100.00
		chip_same_csr_outstanding	1.168h	32.244ms	20	20	100.00
		chip_csr_hw_reset	7.194m	7.603ms	5	5	100.00
		chip_csr_rw	13.885m	6.452ms	20	20	100.00
V2	xbar_base_random_sequence	xbar_random	1.837m	2.582ms	100	100	100.00
V2	xbar_random_delay	xbar_smoke_zero_delays	7.910s	52.839us	100	100	100.00
		xbar_smoke_large_delays	2.114m	10.917ms	100	100	100.00
		xbar_smoke_slow_rsp	2.349m	7.338ms	100	100	100.00
		xbar_random_zero_delays	1.049m	674.453us	100	100	100.00
		xbar_random_large_delays	22.168m	104.837ms	100	100	100.00
		xbar_random_slow_rsp	22.444m	71.029ms	100	100	100.00
V2	xbar_unmapped_address	xbar_unmapped_addr	1.188m	1.456ms	100	100	100.00
		xbar_error_and_unmapped_addr	1.041m	1.345ms	100	100	100.00
V2	xbar_error_cases	xbar_error_random	1.681m	2.730ms	100	100	100.00
		xbar_error_and_unmapped_addr	1.041m	1.345ms	100	100	100.00
V2	xbar_all_access_same_device	xbar_access_same_device	2.597m	3.584ms	100	100	100.00
		xbar_access_same_device_slow_rsp	47.277m	167.963ms	100	100	100.00
V2	xbar_all_hosts_use_same_source_id	xbar_same_source	1.580m	2.712ms	100	100	100.00
V2	xbar_stress_all	xbar_stress_all	13.230m	22.033ms	100	100	100.00
		xbar_stress_all_with_error	15.422m	19.975ms	100	100	100.00
V2	xbar_stress_with_reset	xbar_stress_all_with_rand_reset	19.540m	21.171ms	100	100	100.00
		xbar_stress_all_with_reset_error	17.491m	11.212ms	100	100	100.00
V2	rom_e2e_smoke	rom_e2e_smoke	1.065h	14.525ms	3	3	100.00
V2	rom_e2e_shutdown_output	rom_e2e_shutdown_output	12.556m	6.483ms	0	3	0.00
V2	rom_e2e_shutdown_exception_c	rom_e2e_shutdown_exception_c	13.588m	4.845ms	0	3	0.00
V2	rom_e2e_boot_policy_valid	rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0	1.022h	11.718ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_good_dev	50.259m	15.837ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_good_prod	1.107h	16.346ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_good_prod_end	1.078h	15.879ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_good_rma	1.147h	15.225ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0	54.224m	11.772ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_bad_dev	1.259h	15.626ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_bad_prod	57.489m	15.377ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_bad_prod_end	1.214h	15.275ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_bad_rma	1.144h	14.380ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0	1.455h	17.830ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_bad_b_good_dev	1.793h	24.544ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_bad_b_good_prod	1.770h	24.791ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_bad_b_good_prod_end	2.087h	24.945ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_bad_b_good_rma	1.766h	23.758ms	1	1	100.00
V2	rom_e2e_sigverify_always	rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0	6.353m	3.526ms	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_dev	13.825m	5.665ms	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_prod	13.420m	5.472ms	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_prod_end	15.796m	5.421ms	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_rma	11.657m	4.641ms	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0	6.535m	4.210ms	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_dev	14.402m	5.910ms	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_prod	12.142m	5.311ms	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_prod_end	17.811m	5.852ms	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_rma	12.221m	4.847ms	0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0	5.959m	3.964ms	0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_dev	16.106m	5.668ms	0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_prod	17.597m	5.241ms	0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_prod_end	9.907m	4.841ms	0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_rma	10.821m	5.481ms	0	1	0.00
V2	rom_e2e_asm_init	rom_e2e_asm_init_test_unlocked0	1.028h	11.516ms	3	3	100.00
		rom_e2e_asm_init_dev	1.220h	16.013ms	3	3	100.00
		rom_e2e_asm_init_prod	1.396h	15.813ms	3	3	100.00
		rom_e2e_asm_init_prod_end	1.256h	15.467ms	3	3	100.00
		rom_e2e_asm_init_rma	1.227h	15.703ms	3	3	100.00
V2	rom_e2e_keymgr_init	rom_e2e_keymgr_init_rom_ext_meas	1.242h	15.692ms	3	3	100.00
		rom_e2e_keymgr_init_rom_ext_no_meas	1.252h	15.418ms	3	3	100.00
		rom_e2e_keymgr_init_rom_ext_invalid_meas	1.285h	15.461ms	3	3	100.00
V2	rom_e2e_static_critical	rom_e2e_static_critical	1.251h	17.190ms	3	3	100.00
V2	chip_sw_aes_enc	chip_sw_aes_enc	4.379m	3.002ms	3	3	100.00
		chip_sw_aes_enc_jitter_en	6.696m	2.846ms	3	3	100.00
V2	chip_sw_aes_multi_block	chip_sw_aes_multi_block			0	0	--
V2	chip_sw_aes_interrupt_encryption	chip_sw_aes_interrupt_encryption			0	0	--
V2	chip_sw_aes_entropy	chip_sw_aes_entropy	5.444m	2.962ms	3	3	100.00
V2	chip_sw_aes_prng_reseed	chip_sw_aes_prng_reseed			0	0	--
V2	chip_sw_aes_force_prng_reseed	chip_sw_aes_force_prng_reseed			0	0	--
V2	chip_sw_aes_idle	chip_sw_aes_idle	5.836m	3.431ms	3	3	100.00
V2	chip_sw_aes_sideload	chip_sw_keymgr_sideload_aes	51.047m	11.132ms	3	3	100.00
V2	chip_sw_adc_ctrl_debug_cable_irq	chip_sw_adc_ctrl_sleep_debug_cable_wakeup	8.166m	17.548ms	3	3	100.00
V2	chip_sw_adc_ctrl_sleep_debug_cable_wakeup	chip_sw_adc_ctrl_sleep_debug_cable_wakeup	8.166m	17.548ms	3	3	100.00
V2	chip_sw_aon_timer_wakeup_irq	chip_sw_aon_timer_irq	7.768m	3.621ms	3	3	100.00
V2	chip_sw_aon_timer_sleep_wakeup	chip_sw_pwrmgr_smoketest	9.212m	6.411ms	3	3	100.00
V2	chip_sw_aon_timer_wdog_bark_irq	chip_sw_aon_timer_irq	7.768m	3.621ms	3	3	100.00
V2	chip_sw_aon_timer_wdog_bite_reset	chip_sw_aon_timer_wdog_bite_reset	15.809m	8.620ms	3	3	100.00
V2	chip_sw_aon_timer_sleep_wdog_bite_reset	chip_sw_aon_timer_wdog_bite_reset	15.809m	8.620ms	3	3	100.00
V2	chip_sw_aon_timer_sleep_wdog_sleep_pause	chip_sw_aon_timer_sleep_wdog_sleep_pause	10.069m	6.799ms	5	5	100.00
V2	chip_sw_aon_timer_wdog_lc_escalate	chip_sw_aon_timer_wdog_lc_escalate	14.909m	5.737ms	3	3	100.00
V2	chip_sw_clkmgr_idle_trans	chip_sw_otbn_randomness	18.034m	6.506ms	3	3	100.00
		chip_sw_aes_idle	5.836m	3.431ms	3	3	100.00
		chip_sw_hmac_enc_idle	5.215m	2.743ms	3	3	100.00
		chip_sw_kmac_idle	4.366m	3.306ms	3	3	100.00
V2	chip_sw_clkmgr_off_trans	chip_sw_clkmgr_off_aes_trans	10.458m	4.359ms	3	3	100.00
		chip_sw_clkmgr_off_hmac_trans	9.338m	4.537ms	3	3	100.00
		chip_sw_clkmgr_off_kmac_trans	8.983m	3.810ms	3	3	100.00
		chip_sw_clkmgr_off_otbn_trans	8.173m	5.395ms	3	3	100.00
V2	chip_sw_clkmgr_off_peri	chip_sw_clkmgr_off_peri	30.269m	13.106ms	3	3	100.00
V2	chip_sw_clkmgr_div	chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0	14.721m	4.405ms	3	3	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0	14.510m	4.394ms	3	3	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	14.011m	4.302ms	3	3	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	10.388m	4.565ms	3	3	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_rma	12.956m	4.255ms	3	3	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_rma	11.355m	4.357ms	3	3	100.00
		chip_sw_ast_clk_outputs	17.308m	7.911ms	3	3	100.00
V2	chip_sw_clkmgr_external_clk_src_for_lc	chip_sw_clkmgr_external_clk_src_for_lc	22.445m	10.773ms	3	3	100.00
V2	chip_sw_clkmgr_external_clk_src_for_sw	chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	14.011m	4.302ms	3	3	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	10.388m	4.565ms	3	3	100.00
V2	chip_sw_clkmgr_jitter	chip_sw_flash_ctrl_ops_jitter_en	14.496m	4.400ms	3	3	100.00
		chip_sw_flash_ctrl_access_jitter_en	18.759m	6.409ms	3	3	100.00
		chip_sw_otbn_ecdsa_op_irq_jitter_en	1.177h	18.539ms	3	3	100.00
		chip_sw_aes_enc_jitter_en	6.696m	2.846ms	3	3	100.00
		chip_sw_edn_entropy_reqs_jitter	20.720m	6.452ms	3	3	100.00
		chip_sw_hmac_enc_jitter_en	5.296m	3.247ms	3	3	100.00
		chip_sw_keymgr_key_derivation_jitter_en	42.062m	9.758ms	3	3	100.00
		chip_sw_kmac_mode_kmac_jitter_en	6.311m	3.244ms	3	3	100.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en	13.767m	4.648ms	3	3	100.00
		chip_sw_clkmgr_jitter	5.452m	3.596ms	3	3	100.00
V2	chip_sw_clkmgr_extended_range	chip_sw_clkmgr_jitter_reduced_freq	4.113m	3.021ms	3	3	100.00
		chip_sw_flash_ctrl_ops_jitter_en_reduced_freq	12.211m	5.013ms	3	3	100.00
		chip_sw_flash_ctrl_access_jitter_en_reduced_freq	23.228m	8.062ms	3	3	100.00
		chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq	1.124h	24.678ms	3	3	100.00
		chip_sw_aes_enc_jitter_en_reduced_freq	4.805m	3.621ms	3	3	100.00
		chip_sw_hmac_enc_jitter_en_reduced_freq	5.375m	2.886ms	3	3	100.00
		chip_sw_keymgr_key_derivation_jitter_en_reduced_freq	40.364m	13.376ms	3	3	100.00
		chip_sw_kmac_mode_kmac_jitter_en_reduced_freq	6.266m	3.530ms	3	3	100.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq	10.706m	5.547ms	3	3	100.00
		chip_sw_flash_init_reduced_freq	41.327m	23.989ms	3	3	100.00
		chip_sw_csrng_edn_concurrency_reduced_freq	41.005m	14.907ms	1	3	33.33
V2	chip_sw_clkmgr_deep_sleep_frequency	chip_sw_ast_clk_outputs	17.308m	7.911ms	3	3	100.00
V2	chip_sw_clkmgr_sleep_frequency	chip_sw_clkmgr_sleep_frequency	12.937m	5.026ms	3	3	100.00
V2	chip_sw_clkmgr_reset_frequency	chip_sw_clkmgr_reset_frequency	8.806m	3.435ms	3	3	100.00
V2	chip_sw_clkmgr_escalation_reset	chip_sw_all_escalation_resets	15.921m	6.046ms	97	100	97.00
V2	chip_sw_clkmgr_alert_handler_clock_enables	chip_sw_alert_handler_lpg_clkoff	31.159m	8.243ms	3	3	100.00
V2	chip_sw_csrng_edn_cmd	chip_sw_entropy_src_csrng	27.830m	6.701ms	3	3	100.00
V2	chip_sw_csrng_fuse_en_sw_app_read	chip_sw_csrng_fuse_en_sw_app_read_test	11.735m	4.301ms	3	3	100.00
V2	chip_sw_csrng_lc_hw_debug_en	chip_sw_csrng_lc_hw_debug_en_test	18.237m	7.786ms	3	3	100.00
V2	chip_sw_csrng_known_answer_tests	chip_sw_csrng_kat_test	5.503m	3.067ms	3	3	100.00
V2	chip_sw_sysrst_ctrl_reset	chip_sw_pwrmgr_sysrst_ctrl_reset	24.320m	8.138ms	3	3	100.00
		chip_sw_sysrst_ctrl_reset	33.813m	24.440ms	3	3	100.00
V2	chip_sw_sysrst_ctrl_inputs	chip_sw_sysrst_ctrl_inputs	6.190m	3.205ms	3	3	100.00
V2	chip_sw_sysrst_ctrl_outputs	chip_sw_sysrst_ctrl_outputs	6.938m	3.733ms	3	3	100.00
V2	chip_sw_sysrst_ctrl_in_irq	chip_sw_sysrst_ctrl_in_irq	10.790m	4.684ms	3	3	100.00
V2	chip_sw_sysrst_ctrl_sleep_wakeup	chip_sw_sysrst_ctrl_reset	33.813m	24.440ms	3	3	100.00
V2	chip_sw_sysrst_ctrl_sleep_reset	chip_sw_sysrst_ctrl_reset	33.813m	24.440ms	3	3	100.00
V2	chip_sw_sysrst_ctrl_ec_rst_l	chip_sw_sysrst_ctrl_ec_rst_l	1.035h	20.906ms	3	3	100.00
V2	chip_sw_sysrst_ctrl_flash_wp_l	chip_sw_sysrst_ctrl_ec_rst_l	1.035h	20.906ms	3	3	100.00
V2	chip_sw_sysrst_ctrl_ulp_z3_wakeup	chip_sw_sysrst_ctrl_ulp_z3_wakeup	7.913m	5.243ms	3	3	100.00
		chip_sw_adc_ctrl_sleep_debug_cable_wakeup	8.166m	17.548ms	3	3	100.00
V2	chip_sw_edn_entropy_reqs	chip_sw_csrng_edn_concurrency	1.966h	30.724ms	10	10	100.00
		chip_sw_entropy_src_ast_rng_req	5.360m	3.093ms	3	3	100.00
		chip_sw_edn_entropy_reqs	28.075m	6.175ms	3	3	100.00
V2	chip_sw_entropy_src_ast_rng_req	chip_sw_entropy_src_ast_rng_req	5.360m	3.093ms	3	3	100.00
V2	chip_sw_entropy_src_csrng	chip_sw_entropy_src_csrng	27.830m	6.701ms	3	3	100.00
V2	chip_sw_entropy_src_fuse_en_fw_read	chip_sw_entropy_src_fuse_en_fw_read_test			0	0	--
V2	chip_sw_entropy_src_known_answer_tests	chip_sw_entropy_src_kat_test	5.180m	3.404ms	3	3	100.00
V2	chip_sw_entropy_src_fw_observe_many_contiguous	chip_sw_entropy_src_fw_observe_many_contiguous			0	0	--
V2	chip_sw_entropy_src_fw_extract_and_insert	chip_sw_entropy_src_fw_extract_and_insert			0	0	--
V2	chip_sw_flash_init	chip_sw_flash_init	43.723m	21.247ms	3	3	100.00
V2	chip_sw_flash_host_access	chip_sw_flash_ctrl_access	18.295m	6.081ms	3	3	100.00
		chip_sw_flash_ctrl_access_jitter_en	18.759m	6.409ms	3	3	100.00
V2	chip_sw_flash_ctrl_ops	chip_sw_flash_ctrl_ops	11.065m	3.674ms	3	3	100.00
		chip_sw_flash_ctrl_ops_jitter_en	14.496m	4.400ms	3	3	100.00
V2	chip_sw_flash_rma_unlocked	chip_sw_flash_rma_unlocked	1.475h	44.748ms	3	3	100.00
V2	chip_sw_flash_scramble	chip_sw_flash_init	43.723m	21.247ms	3	3	100.00
V2	chip_sw_flash_idle_low_power	chip_sw_flash_ctrl_idle_low_power	7.847m	3.043ms	3	3	100.00
V2	chip_sw_flash_keymgr_seeds	chip_sw_keymgr_key_derivation	39.994m	11.401ms	3	3	100.00
V2	chip_sw_flash_lc_creator_seed_sw_rw_en	chip_sw_flash_ctrl_lc_rw_en	9.896m	4.266ms	3	3	100.00
V2	chip_sw_flash_creator_seed_wipe_on_rma	chip_sw_flash_rma_unlocked	1.475h	44.748ms	3	3	100.00
V2	chip_sw_flash_lc_owner_seed_sw_rw_en	chip_sw_flash_ctrl_lc_rw_en	9.896m	4.266ms	3	3	100.00
V2	chip_sw_flash_lc_iso_part_sw_rd_en	chip_sw_flash_ctrl_lc_rw_en	9.896m	4.266ms	3	3	100.00
V2	chip_sw_flash_lc_iso_part_sw_wr_en	chip_sw_flash_ctrl_lc_rw_en	9.896m	4.266ms	3	3	100.00
V2	chip_sw_flash_lc_seed_hw_rd_en	chip_sw_flash_ctrl_lc_rw_en	9.896m	4.266ms	3	3	100.00
V2	chip_sw_flash_lc_escalate_en	chip_sw_all_escalation_resets	15.921m	6.046ms	97	100	97.00
V2	chip_sw_flash_prim_tl_access	chip_prim_tl_access	12.227m	18.809ms	3	3	100.00
V2	chip_sw_flash_ctrl_clock_freqs	chip_sw_flash_ctrl_clock_freqs	19.623m	5.778ms	3	3	100.00
V2	chip_sw_flash_ctrl_escalation_reset	chip_sw_flash_crash_alert	13.014m	6.081ms	3	3	100.00
V2	chip_sw_flash_ctrl_write_clear	chip_sw_flash_crash_alert	13.014m	6.081ms	3	3	100.00
V2	chip_sw_hmac_enc	chip_sw_hmac_enc	5.120m	2.220ms	3	3	100.00
		chip_sw_hmac_enc_jitter_en	5.296m	3.247ms	3	3	100.00
V2	chip_sw_hmac_idle	chip_sw_hmac_enc_idle	5.215m	2.743ms	3	3	100.00
V2	chip_sw_hmac_all_configurations	chip_sw_hmac_oneshot	6.810m	3.475ms	3	3	100.00
V2	chip_sw_hmac_multistream_mode	chip_sw_hmac_multistream	33.487m	8.453ms	3	3	100.00
V2	chip_sw_i2c_host_tx_rx	chip_sw_i2c_host_tx_rx	16.994m	5.234ms	3	3	100.00
		chip_sw_i2c_host_tx_rx_idx1	12.712m	4.479ms	3	3	100.00
		chip_sw_i2c_host_tx_rx_idx2	17.458m	5.353ms	3	3	100.00
V2	chip_sw_i2c_device_tx_rx	chip_sw_i2c_device_tx_rx	10.968m	4.461ms	3	3	100.00
V2	chip_sw_keymgr_key_derivation	chip_sw_keymgr_key_derivation	39.994m	11.401ms	3	3	100.00
		chip_sw_keymgr_key_derivation_jitter_en	42.062m	9.758ms	3	3	100.00
V2	chip_sw_keymgr_sideload_kmac	chip_sw_keymgr_sideload_kmac	30.099m	9.672ms	3	3	100.00
V2	chip_sw_keymgr_sideload_aes	chip_sw_keymgr_sideload_aes	51.047m	11.132ms	3	3	100.00
V2	chip_sw_keymgr_sideload_otbn	chip_sw_keymgr_sideload_otbn	1.144h	15.154ms	3	3	100.00
V2	chip_sw_kmac_enc	chip_sw_kmac_mode_cshake	4.551m	2.730ms	3	3	100.00
		chip_sw_kmac_mode_kmac	6.527m	3.152ms	3	3	100.00
		chip_sw_kmac_mode_kmac_jitter_en	6.311m	3.244ms	3	3	100.00
V2	chip_sw_kmac_app_keymgr	chip_sw_keymgr_key_derivation	39.994m	11.401ms	3	3	100.00
V2	chip_sw_kmac_app_lc	chip_sw_lc_ctrl_transition	20.498m	11.305ms	15	15	100.00
V2	chip_sw_kmac_app_rom	chip_sw_kmac_app_rom	5.810m	3.523ms	3	3	100.00
V2	chip_sw_kmac_entropy	chip_sw_kmac_entropy	5.671m	3.590ms	3	3	100.00
V2	chip_sw_kmac_idle	chip_sw_kmac_idle	4.366m	3.306ms	3	3	100.00
V2	chip_sw_lc_ctrl_alert_handler_escalation	chip_sw_alert_handler_escalation	10.298m	5.367ms	3	3	100.00
V2	chip_sw_lc_ctrl_jtag_access	chip_tap_straps_dev	14.871m	8.271ms	5	5	100.00
		chip_tap_straps_rma	33.663m	16.794ms	3	5	60.00
		chip_tap_straps_prod	25.084m	14.347ms	4	5	80.00
V2	chip_sw_lc_ctrl_otp_hw_cfg0	chip_sw_lc_ctrl_otp_hw_cfg0	5.171m	3.187ms	3	3	100.00
V2	chip_sw_lc_ctrl_init	chip_sw_lc_ctrl_transition	20.498m	11.305ms	15	15	100.00
V2	chip_sw_lc_ctrl_transitions	chip_sw_lc_ctrl_transition	20.498m	11.305ms	15	15	100.00
V2	chip_sw_lc_ctrl_kmac_req	chip_sw_lc_ctrl_transition	20.498m	11.305ms	15	15	100.00
V2	chip_sw_lc_ctrl_key_div	chip_sw_keymgr_key_derivation_prod	32.311m	9.185ms	3	3	100.00
V2	chip_sw_lc_ctrl_broadcast	chip_sw_flash_ctrl_lc_rw_en	9.896m	4.266ms	3	3	100.00
		chip_sw_flash_rma_unlocked	1.475h	44.748ms	3	3	100.00
		chip_sw_otp_ctrl_lc_signals_test_unlocked0	12.608m	4.606ms	3	3	100.00
		chip_sw_otp_ctrl_lc_signals_dev	24.204m	8.162ms	3	3	100.00
		chip_sw_otp_ctrl_lc_signals_prod	22.334m	8.722ms	3	3	100.00
		chip_sw_otp_ctrl_lc_signals_rma	25.806m	7.747ms	3	3	100.00
		chip_sw_lc_ctrl_transition	20.498m	11.305ms	15	15	100.00
		chip_sw_keymgr_key_derivation	39.994m	11.401ms	3	3	100.00
		chip_sw_rom_ctrl_integrity_check	8.894m	9.120ms	3	3	100.00
		chip_sw_sram_ctrl_execution_main	18.090m	10.158ms	3	3	100.00
		chip_prim_tl_access	12.227m	18.809ms	3	3	100.00
		chip_sw_clkmgr_external_clk_src_for_lc	22.445m	10.773ms	3	3	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0	14.721m	4.405ms	3	3	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0	14.510m	4.394ms	3	3	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	14.011m	4.302ms	3	3	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	10.388m	4.565ms	3	3	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_rma	12.956m	4.255ms	3	3	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_rma	11.355m	4.357ms	3	3	100.00
		chip_tap_straps_dev	14.871m	8.271ms	5	5	100.00
		chip_tap_straps_rma	33.663m	16.794ms	3	5	60.00
		chip_tap_straps_prod	25.084m	14.347ms	4	5	80.00
		chip_rv_dm_lc_disabled	9.839m	10.155ms	3	3	100.00
V2	chip_lc_scrap	chip_sw_lc_ctrl_rma_to_scrap	2.490m	3.337ms	1	1	100.00
		chip_sw_lc_ctrl_raw_to_scrap	2.202m	3.607ms	1	1	100.00
		chip_sw_lc_ctrl_test_locked0_to_scrap	2.801m	3.633ms	1	1	100.00
		chip_sw_lc_ctrl_rand_to_scrap	6.023m	3.830ms	3	3	100.00
V2	chip_lc_test_locked	chip_sw_lc_walkthrough_testunlocks	40.802m	34.777ms	3	3	100.00
		chip_rv_dm_lc_disabled	9.839m	10.155ms	3	3	100.00
V2	chip_sw_lc_walkthrough	chip_sw_lc_walkthrough_dev	1.771h	48.602ms	3	3	100.00
		chip_sw_lc_walkthrough_prod	1.851h	48.468ms	3	3	100.00
		chip_sw_lc_walkthrough_prodend	15.081m	6.772ms	3	3	100.00
		chip_sw_lc_walkthrough_rma	1.657h	49.373ms	3	3	100.00
		chip_sw_lc_walkthrough_testunlocks	40.802m	34.777ms	3	3	100.00
V2	chip_sw_lc_ctrl_volatile_raw_unlock	chip_sw_lc_ctrl_volatile_raw_unlock	2.070m	2.874ms	3	3	100.00
		chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz	1.977m	2.484ms	3	3	100.00
		rom_volatile_raw_unlock	2.073m	2.218ms	3	3	100.00
V2	chip_otp_ctrl_init	chip_sw_lc_ctrl_transition	20.498m	11.305ms	15	15	100.00
V2	chip_sw_otp_ctrl_keys	chip_sw_flash_init	43.723m	21.247ms	3	3	100.00
		chip_sw_otbn_mem_scramble	10.699m	3.754ms	3	3	100.00
		chip_sw_keymgr_key_derivation	39.994m	11.401ms	3	3	100.00
		chip_sw_sram_ctrl_scrambled_access	8.953m	4.543ms	3	3	100.00
		chip_sw_rv_core_ibex_icache_invalidate	4.979m	2.994ms	3	3	100.00
V2	chip_sw_otp_ctrl_entropy	chip_sw_flash_init	43.723m	21.247ms	3	3	100.00
		chip_sw_otbn_mem_scramble	10.699m	3.754ms	3	3	100.00
		chip_sw_keymgr_key_derivation	39.994m	11.401ms	3	3	100.00
		chip_sw_sram_ctrl_scrambled_access	8.953m	4.543ms	3	3	100.00
		chip_sw_rv_core_ibex_icache_invalidate	4.979m	2.994ms	3	3	100.00
V2	chip_sw_otp_ctrl_program	chip_sw_lc_ctrl_transition	20.498m	11.305ms	15	15	100.00
V2	chip_sw_otp_ctrl_program_error	chip_sw_lc_ctrl_program_error	12.569m	5.444ms	3	3	100.00
V2	chip_sw_otp_ctrl_hw_cfg0	chip_sw_lc_ctrl_otp_hw_cfg0	5.171m	3.187ms	3	3	100.00
V2	chip_sw_otp_ctrl_lc_signals	chip_sw_otp_ctrl_lc_signals_test_unlocked0	12.608m	4.606ms	3	3	100.00
		chip_sw_otp_ctrl_lc_signals_dev	24.204m	8.162ms	3	3	100.00
		chip_sw_otp_ctrl_lc_signals_prod	22.334m	8.722ms	3	3	100.00
		chip_sw_otp_ctrl_lc_signals_rma	25.806m	7.747ms	3	3	100.00
		chip_sw_lc_ctrl_transition	20.498m	11.305ms	15	15	100.00
		chip_prim_tl_access	12.227m	18.809ms	3	3	100.00
V2	chip_sw_otp_prim_tl_access	chip_prim_tl_access	12.227m	18.809ms	3	3	100.00
V2	chip_sw_otp_ctrl_dai_lock	chip_sw_otp_ctrl_dai_lock	1.613h	27.709ms	1	1	100.00
V2	chip_sw_pwrmgr_external_full_reset	chip_sw_pwrmgr_full_aon_reset	8.460m	7.701ms	3	3	100.00
V2	chip_sw_pwrmgr_random_sleep_all_wake_ups	chip_sw_pwrmgr_random_sleep_all_wake_ups	27.245m	20.896ms	3	3	100.00
V2	chip_sw_pwrmgr_normal_sleep_all_wake_ups	chip_sw_pwrmgr_normal_sleep_all_wake_ups	7.776m	6.929ms	3	3	100.00
V2	chip_sw_pwrmgr_deep_sleep_por_reset	chip_sw_pwrmgr_deep_sleep_por_reset	11.734m	9.408ms	3	3	100.00
V2	chip_sw_pwrmgr_normal_sleep_por_reset	chip_sw_pwrmgr_normal_sleep_por_reset	13.865m	5.395ms	3	3	100.00
V2	chip_sw_pwrmgr_deep_sleep_all_wake_ups	chip_sw_pwrmgr_deep_sleep_all_wake_ups	26.220m	24.510ms	3	3	100.00
V2	chip_sw_pwrmgr_deep_sleep_all_reset_reqs	chip_sw_pwrmgr_deep_sleep_all_reset_reqs	28.064m	14.498ms	3	3	100.00
		chip_sw_aon_timer_wdog_bite_reset	15.809m	8.620ms	3	3	100.00
V2	chip_sw_pwrmgr_normal_sleep_all_reset_reqs	chip_sw_pwrmgr_normal_sleep_all_reset_reqs	23.465m	13.428ms	2	3	66.67
V2	chip_sw_pwrmgr_wdog_reset	chip_sw_pwrmgr_wdog_reset	13.929m	5.762ms	3	3	100.00
V2	chip_sw_pwrmgr_aon_power_glitch_reset	chip_sw_pwrmgr_full_aon_reset	8.460m	7.701ms	3	3	100.00
V2	chip_sw_pwrmgr_main_power_glitch_reset	chip_sw_pwrmgr_main_power_glitch_reset	9.471m	4.587ms	3	3	100.00
V2	chip_sw_pwrmgr_random_sleep_power_glitch_reset	chip_sw_pwrmgr_random_sleep_power_glitch_reset	58.183m	37.490ms	3	3	100.00
V2	chip_sw_pwrmgr_deep_sleep_power_glitch_reset	chip_sw_pwrmgr_deep_sleep_power_glitch_reset	9.043m	7.988ms	3	3	100.00
V2	chip_sw_pwrmgr_sleep_power_glitch_reset	chip_sw_pwrmgr_sleep_power_glitch_reset	12.486m	6.507ms	3	3	100.00
V2	chip_sw_pwrmgr_random_sleep_all_reset_reqs	chip_sw_pwrmgr_random_sleep_all_reset_reqs	53.209m	26.758ms	3	3	100.00
V2	chip_sw_pwrmgr_sysrst_ctrl_reset	chip_sw_pwrmgr_sysrst_ctrl_reset	24.320m	8.138ms	3	3	100.00
		chip_sw_pwrmgr_all_reset_reqs	35.239m	12.323ms	3	3	100.00
V2	chip_sw_pwrmgr_b2b_sleep_reset_req	chip_sw_pwrmgr_b2b_sleep_reset_req	55.106m	34.195ms	3	3	100.00
V2	chip_sw_pwrmgr_sleep_disabled	chip_sw_pwrmgr_sleep_disabled	5.458m	3.454ms	3	3	100.00
V2	chip_sw_pwrmgr_escalation_reset	chip_sw_all_escalation_resets	15.921m	6.046ms	97	100	97.00
V2	chip_sw_rom_access	chip_sw_rom_ctrl_integrity_check	8.894m	9.120ms	3	3	100.00
V2	chip_sw_rom_ctrl_integrity_check	chip_sw_rom_ctrl_integrity_check	8.894m	9.120ms	3	3	100.00
V2	chip_sw_rstmgr_non_sys_reset_info	chip_sw_pwrmgr_all_reset_reqs	35.239m	12.323ms	3	3	100.00
		chip_sw_pwrmgr_random_sleep_all_reset_reqs	53.209m	26.758ms	3	3	100.00
		chip_sw_pwrmgr_wdog_reset	13.929m	5.762ms	3	3	100.00
		chip_sw_pwrmgr_smoketest	9.212m	6.411ms	3	3	100.00
V2	chip_sw_rstmgr_sys_reset_info	chip_rv_dm_ndm_reset_req	7.849m	4.876ms	3	3	100.00
V2	chip_sw_rstmgr_cpu_info	chip_sw_rstmgr_cpu_info	17.622m	6.809ms	3	3	100.00
V2	chip_sw_rstmgr_sw_req_reset	chip_sw_rstmgr_sw_req	9.702m	5.395ms	3	3	100.00
V2	chip_sw_rstmgr_alert_info	chip_sw_rstmgr_alert_info	36.156m	11.570ms	3	3	100.00
V2	chip_sw_rstmgr_sw_rst	chip_sw_rstmgr_sw_rst	4.624m	3.325ms	3	3	100.00
V2	chip_sw_rstmgr_escalation_reset	chip_sw_all_escalation_resets	15.921m	6.046ms	97	100	97.00
V2	chip_sw_rstmgr_alert_handler_reset_enables	chip_sw_alert_handler_lpg_reset_toggle	38.437m	8.492ms	3	3	100.00
V2	chip_sw_plic_all_irqs	chip_plic_all_irqs_0	20.428m	6.547ms	3	3	100.00
		chip_plic_all_irqs_10	9.832m	3.537ms	3	3	100.00
		chip_plic_all_irqs_20	13.462m	4.144ms	3	3	100.00
V2	chip_sw_plic_sw_irq	chip_sw_plic_sw_irq	4.505m	2.533ms	3	3	100.00
V2	chip_sw_timer	chip_sw_rv_timer_irq	6.315m	3.516ms	3	3	100.00
V2	chip_sw_spi_device_flash_mode	rom_e2e_smoke	1.065h	14.525ms	3	3	100.00
V2	chip_sw_spi_device_pass_through	chip_sw_spi_device_pass_through	16.062m	8.418ms	3	3	100.00
V2	chip_sw_spi_device_pass_through_collision	chip_sw_spi_device_pass_through_collision	11.155m	5.057ms	3	3	100.00
V2	chip_sw_spi_device_tpm	chip_sw_spi_device_tpm	7.934m	4.080ms	3	3	100.00
V2	chip_sw_spi_host_tx_rx	chip_sw_spi_host_tx_rx	5.252m	2.492ms	3	3	100.00
V2	chip_sw_sram_scrambled_access	chip_sw_sram_ctrl_scrambled_access	8.953m	4.543ms	3	3	100.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en	13.767m	4.648ms	3	3	100.00
V2	chip_sw_sleep_sram_ret_contents	chip_sw_sleep_sram_ret_contents_no_scramble	13.350m	8.531ms	3	3	100.00
		chip_sw_sleep_sram_ret_contents_scramble	15.965m	8.464ms	3	3	100.00
V2	chip_sw_sram_execution	chip_sw_sram_ctrl_execution_main	18.090m	10.158ms	3	3	100.00
V2	chip_sw_sram_lc_escalation	chip_sw_all_escalation_resets	15.921m	6.046ms	97	100	97.00
		chip_sw_data_integrity_escalation	14.023m	5.275ms	6	6	100.00
V2	chip_sw_usbdev_mem	chip_sw_usbdev_mem			0	0	--
V2	chip_sw_usbdev_vbus	chip_sw_usbdev_vbus	4.866m	2.534ms	1	1	100.00
V2	chip_sw_usbdev_pullup	chip_sw_usbdev_pullup	3.731m	2.753ms	1	1	100.00
V2	chip_sw_usbdev_aon_pullup	chip_sw_usbdev_aon_pullup	8.869m	3.641ms	1	1	100.00
V2	chip_sw_usbdev_sof	chip_sw_usbdev_sof			0	0	--
V2	chip_sw_usbdev_setup_rx	chip_sw_usbdev_setuprx	10.217m	3.739ms	1	1	100.00
V2	chip_sw_usbdev_config_host	chip_sw_usbdev_config_host	35.893m	8.441ms	1	1	100.00
V2	chip_sw_usbdev_pincfg	chip_sw_usbdev_pincfg	1.936h	31.134ms	1	1	100.00
V2	chip_sw_usbdev_tx_rx	chip_sw_usbdev_dpi	57.181m	12.151ms	1	1	100.00
V2	chip_sw_alert_handler_alerts	chip_sw_alert_test	6.941m	3.088ms	3	3	100.00
V2	chip_sw_alert_handler_escalations	chip_sw_alert_handler_escalation	10.298m	5.367ms	3	3	100.00
V2	chip_sw_alert_handler_escalation_nmi_reset	chip_sw_alert_handler_escalation_nmi_reset			0	0	--
V2	chip_sw_alert_handler_escalation_methods	chip_sw_alert_handler_escalation_methods			0	0	--
V2	chip_sw_all_escalation_resets	chip_sw_all_escalation_resets	15.921m	6.046ms	97	100	97.00
V2	chip_sw_alert_handler_irqs	chip_plic_all_irqs			0	0	--
V2	chip_sw_alert_handler_entropy	chip_sw_alert_handler_entropy	5.704m	2.797ms	3	3	100.00
V2	chip_sw_alert_handler_crashdump	chip_sw_rstmgr_alert_info	36.156m	11.570ms	3	3	100.00
V2	chip_sw_alert_handler_ping_timeout	chip_sw_alert_handler_ping_timeout	8.396m	5.005ms	3	3	100.00
V2	chip_sw_alert_handler_lpg_sleep_mode_alerts	chip_sw_alert_handler_lpg_sleep_mode_alerts	10.256m	3.740ms	86	90	95.56
V2	chip_sw_alert_handler_lpg_sleep_mode_pings	chip_sw_alert_handler_lpg_sleep_mode_pings	26.611m	12.830ms	3	3	100.00
V2	chip_sw_alert_handler_lpg_clock_off	chip_sw_alert_handler_lpg_clkoff	31.159m	8.243ms	3	3	100.00
V2	chip_sw_alert_handler_lpg_reset_toggle	chip_sw_alert_handler_lpg_reset_toggle	38.437m	8.492ms	3	3	100.00
V2	chip_sw_alert_handler_ping_ok	chip_sw_alert_handler_ping_ok	26.662m	8.518ms	3	3	100.00
V2	chip_sw_alert_handler_reverse_ping_in_deep_sleep	chip_sw_alert_handler_reverse_ping_in_deep_sleep	3.756h	255.379ms	3	3	100.00
V2	chip_jtag_csr_rw	chip_jtag_csr_rw	42.029m	22.848ms	3	3	100.00
V2	chip_jtag_mem_access	chip_jtag_mem_access	25.526m	13.758ms	3	3	100.00
V2	chip_rv_dm_ndm_reset_req	chip_rv_dm_ndm_reset_req	7.849m	4.876ms	3	3	100.00
V2	chip_sw_rv_dm_ndm_reset_req_when_cpu_halted	chip_sw_rv_dm_ndm_reset_req_when_cpu_halted	10.700m	3.502ms	3	3	100.00
V2	chip_rv_dm_access_after_wakeup	chip_sw_rv_dm_access_after_wakeup	11.485m	3.774ms	0	3	0.00
V2	chip_sw_rv_dm_jtag_tap_sel	chip_tap_straps_rma	33.663m	16.794ms	3	5	60.00
V2	chip_rv_dm_lc_disabled	chip_rv_dm_lc_disabled	9.839m	10.155ms	3	3	100.00
V2	chip_rv_dm_jtag	chip_rv_dm_jtag			0	0	--
V2	chip_rv_dm_dtm	chip_rv_dm_dtm			0	0	--
V2	chip_rv_dm_control_status	chip_rv_dm_control_status			0	0	--
V2		TOTAL			2601	2644	98.37
V2S	chip_sw_aes_masking_off	chip_sw_aes_masking_off	6.421m	2.343ms	3	3	100.00
V2S		TOTAL			3	3	100.00
V3	chip_sw_usb_suspend	chip_sw_usb_suspend			0	0	--
V3	chip_usb_wake_debug	chip_usb_wake_debug			0	0	--
V3	chip_sw_coremark	chip_sw_coremark			0	1	0.00
V3	chip_sw_power_max_load	chip_sw_power_virus			0	3	0.00
V3	rom_e2e_debug	rom_e2e_jtag_debug_test_unlocked0	13.637m	7.511ms	0	1	0.00
		rom_e2e_jtag_debug_dev	20.002m	7.842ms	0	1	0.00
		rom_e2e_jtag_debug_rma	15.899m	6.973ms	0	1	0.00
V3	rom_e2e_jtag_inject	rom_e2e_jtag_inject_test_unlocked0	47.692m	31.241ms	1	1	100.00
		rom_e2e_jtag_inject_dev	50.024m	31.093ms	1	1	100.00
		rom_e2e_jtag_inject_rma	55.488m	31.662ms	1	1	100.00
V3	rom_bootstrap_rma	rom_bootstrap_rma			0	0	--
V3	rom_e2e_weak_straps	rom_e2e_weak_straps			0	0	--
V3	rom_e2e_self_hash	rom_e2e_self_hash			0	0	--
V3	manuf_cp_unlock_raw	manuf_cp_unlock_raw			0	0	--
V3	manuf_scrap	manuf_scrap			0	0	--
V3	manuf_cp_yield_test	manuf_cp_yield_test			0	0	--
V3	manuf_cp_ast_test_execution	manuf_cp_ast_test_execution			0	0	--
V3	manuf_cp_device_info_flash_wr	manuf_cp_device_info_flash_wr			0	0	--
V3	manuf_cp_test_lock	manuf_cp_test_lock			0	0	--
V3	manuf_ft_exit_token	manuf_ft_exit_token			0	0	--
V3	manuf_ft_sku_individualization_preop	manuf_ft_sku_individualization_preop			0	0	--
V3	manuf_ft_sku_individualization	manuf_ft_sku_individualization			0	0	--
V3	manuf_ft_provision_rma_token_and_personalization	manuf_ft_provision_rma_token_and_personalization			0	0	--
V3	manuf_ft_load_transport_image	manuf_ft_load_transport_image			0	0	--
V3	manuf_ft_load_certificates	manuf_ft_load_certificates			0	0	--
V3	manuf_ft_eom	manuf_ft_eom			0	0	--
V3	manuf_rma_entry	manuf_rma_entry			0	0	--
V3	manuf_sram_program_crc_functest	manuf_sram_program_crc_functest			0	0	--
V3	chip_sw_adc_ctrl_normal	chip_sw_adc_ctrl_normal			0	0	--
V3	chip_sw_adc_ctrl_oneshot	chip_sw_adc_ctrl_oneshot			0	0	--
V3	chip_sw_clkmgr_jitter_cycle_measurements	chip_sw_clkmgr_jitter_frequency	10.932m	3.718ms	3	3	100.00
V3	chip_sw_edn_boot_mode	chip_sw_edn_boot_mode	12.184m	3.553ms	3	3	100.00
V3	chip_sw_edn_auto_mode	chip_sw_edn_auto_mode	34.631m	6.612ms	3	3	100.00
V3	chip_sw_edn_sw_mode	chip_sw_edn_sw_mode	41.548m	8.596ms	3	3	100.00
V3	chip_sw_edn_kat	chip_sw_edn_kat	12.009m	3.309ms	3	3	100.00
V3	chip_sw_entropy_src_bypass_mode_health_tests	chip_sw_entropy_src_bypass_mode_health_tests			0	0	--
V3	chip_sw_entropy_src_fips_mode_health_tests	chip_sw_entropy_src_fips_mode_health_tests			0	0	--
V3	chip_sw_entropy_src_validation	chip_sw_entropy_src_validation			0	0	--
V3	chip_sw_flash_memory_protection	chip_sw_flash_ctrl_mem_protection	22.362m	5.669ms	3	3	100.00
V3	chip_sw_hmac_sha2_stress	chip_sw_hmac_sha2_stress			0	0	--
V3	chip_sw_hmac_stress	chip_sw_hmac_stress			0	0	--
V3	chip_sw_hmac_endianness	chip_sw_hmac_endianness			0	0	--
V3	chip_sw_hmac_secure_wipe	chip_sw_hmac_secure_wipe			0	0	--
V3	chip_sw_hmac_error_conditions	chip_sw_hmac_error_conditions			0	0	--
V3	chip_sw_i2c_speed	chip_sw_i2c_speed			0	0	--
V3	chip_sw_i2c_override	//sw/device/tests:i2c_host_override_test			0	0	--
V3	chip_sw_i2c_clockstretching	chip_sw_i2c_clockstretching			0	0	--
V3	chip_sw_i2c_nack	chip_sw_i2c_nack			0	0	--
V3	chip_sw_i2c_repeatedstart	chip_sw_i2c_repeatedstart			0	0	--
V3	chip_sw_keymgr_sideload_kmac_error	chip_sw_keymgr_sideload_kmac_error			0	0	--
V3	chip_sw_keymgr_derive_attestation	chip_sw_keymgr_derive_attestation			0	0	--
V3	chip_sw_keymgr_derive_sealing	chip_sw_keymgr_derive_sealing			0	0	--
V3	chip_sw_kmac_sha3_stress	chip_sw_kmac_sha3_stress			0	0	--
V3	chip_sw_kmac_shake_stress	chip_sw_kmac_shake_stress			0	0	--
V3	chip_sw_kmac_cshake_stress	chip_sw_kmac_cshake_stress			0	0	--
V3	chip_sw_kmac_kmac_stress	chip_sw_kmac_kmac_stress			0	0	--
V3	chip_sw_kmac_kmac_key_sideload	chip_sw_kmac_kmac_key_sideload			0	0	--
V3	chip_sw_kmac_endianess	chip_sw_kmac_endianess			0	0	--
V3	chip_sw_kmac_entropy_stress	chip_sw_kmac_entropy_stress			0	0	--
V3	chip_sw_kmac_error_conditions	chip_sw_kmac_error_conditions			0	0	--
V3	chip_sw_lc_ctrl_kmac_error	chip_sw_lc_ctrl_kmac_error			0	0	--
V3	chip_sw_lc_ctrl_debug_access	chip_sw_lc_ctrl_debug_access			0	0	--
V3	chip_sw_otp_ctrl_vendor_test_csr_access	chip_sw_otp_ctrl_vendor_test_csr_access	3.212m	2.688ms	3	3	100.00
V3	chip_sw_otp_ctrl_escalation	chip_sw_otp_ctrl_escalation	10.496m	5.430ms	1	1	100.00
V3	otp_ctrl_calibration	otp_ctrl_calibration			0	0	--
V3	otp_ctrl_partition_access_locked	otp_ctrl_partition_access_locked			0	0	--
V3	otp_ctrl_check_timeout	otp_ctrl_check_timeout			0	0	--
V3	chip_sw_sensor_ctrl_deep_sleep_wake_up	chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up	9.877m	5.514ms	3	3	100.00
V3	chip_sw_pwrmgr_usb_clk_disabled_when_active	chip_sw_pwrmgr_usb_clk_disabled_when_active	12.244m	4.949ms	3	3	100.00
V3	chip_sw_all_resets	chip_sw_pwrmgr_all_reset_reqs	35.239m	12.323ms	3	3	100.00
V3	chip_sw_rom_ctrl_kmac_error	chip_sw_rom_ctrl_kmac_error			0	0	--
V3	chip_sw_rom_ctrl_digests	chip_sw_rom_ctrl_digests			0	0	--
V3	chip_sw_plic_alerts	chip_sw_all_escalation_resets	15.921m	6.046ms	97	100	97.00
V3	tick_configuration	chip_sw_rv_timer_systick_test			0	3	0.00
V3	counter_wrap	chip_sw_rv_timer_systick_test			0	3	0.00
V3	chip_sw_spi_device_pass_through_flash_model	//sw/device/tests:spi_passthru_test			0	0	--
V3	chip_sw_spi_device_output_when_disabled_or_sleeping	chip_sw_spi_device_output_when_disabled_or_sleeping			0	0	--
V3	chip_sw_spi_host_pass_through	//sw/device/tests:spi_passthru_test			0	0	--
V3	chip_sw_spi_host_configuration	chip_sw_spi_host_configuration			0	0	--
V3	chip_sw_spi_host_events	chip_sw_spi_host_events			0	0	--
V3	chip_sw_sram_memset	chip_sw_sram_memset			0	0	--
V3	chip_sw_sram_subword_access	chip_sw_sram_subword_access			0	0	--
V3	chip_sw_uart_parity	chip_sw_uart_parity			0	0	--
V3	chip_sw_uart_line_loopback	chip_sw_uart_line_loopback			0	0	--
V3	chip_sw_uart_system_loopback	chip_sw_uart_system_loopback			0	0	--
V3	chip_sw_uart_line_break	chip_sw_uart_line_break			0	0	--
V3	chip_sw_uart_watermarks	chip_sw_uart_tx_rx	11.488m	3.916ms	5	5	100.00
V3	chip_sw_usbdev_stream	chip_sw_usbdev_stream	1.623h	19.075ms	1	1	100.00
V3	chip_sw_usbdev_iso	chip_sw_usbdev_iso			0	0	--
V3	chip_sw_usbdev_mixed	chip_sw_usbdev_mixed			0	0	--
V3	chip_sw_usbdev_suspend_resume	chip_sw_usbdev_suspend_resume			0	0	--
V3	chip_sw_usbdev_aon_wake_reset	chip_sw_usbdev_aon_wake_reset			0	0	--
V3	chip_sw_usbdev_aon_wake_disconnect	chip_sw_usbdev_aon_wake_disconnect			0	0	--
V3	chip_sw_usbdev_toggle_restore	chip_sw_usbdev_toggle_restore			0	0	--
V3	chip_rv_dm_perform_debug	rom_e2e_jtag_debug_test_unlocked0	13.637m	7.511ms	0	1	0.00
		rom_e2e_jtag_debug_dev	20.002m	7.842ms	0	1	0.00
		rom_e2e_jtag_debug_rma	15.899m	6.973ms	0	1	0.00
V3	chip_sw_rv_dm_access_after_hw_reset	chip_sw_rv_dm_access_after_escalation_reset	10.771m	5.762ms	3	3	100.00
V3		TOTAL			35	45	77.78
	Unmapped tests	chip_sival_flash_info_access	5.518m	3.660ms	3	3	100.00
		chip_sw_rstmgr_rst_cnsty_escalation	10.899m	4.746ms	3	3	100.00
		chip_sw_otp_ctrl_ecc_error_vendor_test	5.824m	3.701ms	3	3	100.00
		chip_sw_otbn_ecdsa_op_irq	1.170h	17.569ms	3	3	100.00
		chip_sw_rv_core_ibex_rnd	20.231m	4.742ms	3	3	100.00
		chip_sw_rv_core_ibex_nmi_irq	15.312m	4.581ms	3	3	100.00
		chip_sw_pwrmgr_lowpower_cancel	8.270m	4.357ms	2	3	66.67
		chip_sw_pwrmgr_sleep_wake_5_bug	10.368m	5.708ms	3	3	100.00
		chip_sw_rv_core_ibex_address_translation	6.503m	3.574ms	3	3	100.00
		chip_sw_rv_core_ibex_lockstep_glitch	5.084m	2.848ms	3	3	100.00
		chip_sw_flash_ctrl_write_clear	7.228m	3.561ms	3	3	100.00
		TOTAL			2871	2945	97.49

Testplan Progress

Items	Total	Written	Passing	Progress
N.A.	11	11	10	90.91
V1	18	18	17	94.44
V2	285	270	243	85.26
V2S	1	1	1	100.00
V3	90	21	15	16.67

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
96.15	95.62	94.06	95.43	--	94.90	97.35	99.53

Failure Buckets

UVM_ERROR @ * us: (cip_base_vseq.sv:828) [chip_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 20 failures:
- Test chip_csr_mem_rw_with_rand_reset has 20 failures.
  - 0.chip_csr_mem_rw_with_rand_reset.62739930006965113827218775247160457515445163624005707554727182772377610632091
    Line 391, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_csr_mem_rw_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 2507.706562 us: (cip_base_vseq.sv:828) [uvm_test_top.env.virtual_sequencer.chip_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 2507.706562 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 1.chip_csr_mem_rw_with_rand_reset.34343223513012228927177423592431506097280152951065501839176510356469816593209
    Line 382, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.chip_csr_mem_rw_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 2195.988413 us: (cip_base_vseq.sv:828) [uvm_test_top.env.virtual_sequencer.chip_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 2195.988413 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 18 more failures.
UVM_ERROR @ * us: (chip_sw_rom_e2e_base_vseq.sv:35) [chip_sw_rom_e2e_sigverify_always_a_bad_b_bad_vseq] Check failed "OpenTitan:*-*-* has 15 failures:
- Test rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0 has 1 failures.
  - 0.rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0.52610654583590743103601260694026039754341718077209724685833953230139348525373
    Line 1008, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0/latest/run.log
```
  UVM_ERROR @ 3526.359245 us: (chip_sw_rom_e2e_base_vseq.sv:35) [uvm_test_top.env.virtual_sequencer.chip_sw_rom_e2e_sigverify_always_a_bad_b_bad_vseq] Check failed "OpenTitan:4001-0002-01
  GIT:" == "BFV:07535603
  LCV:02108421
  "
  UVM_INFO @ 3526.359245 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
```
- Test rom_e2e_sigverify_always_a_bad_b_bad_dev has 1 failures.
  - 0.rom_e2e_sigverify_always_a_bad_b_bad_dev.14131500097122358488462738399539648851487125432940049318563744600643204210462
    Line 1018, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_bad_b_bad_dev/latest/run.log
```
  UVM_ERROR @ 5665.044057 us: (chip_sw_rom_e2e_base_vseq.sv:35) [uvm_test_top.env.virtual_sequencer.chip_sw_rom_e2e_sigverify_always_a_bad_b_bad_vseq] Check failed "OpenTitan:4001-0002-01
  GIT:" == "BFV:07535603
  LCV:21084210
  "
  UVM_INFO @ 5665.044057 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
```
- Test rom_e2e_sigverify_always_a_bad_b_bad_prod has 1 failures.
  - 0.rom_e2e_sigverify_always_a_bad_b_bad_prod.71812544745979617262839769852986172406303080064164938284273212084703826683429
    Line 1059, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_bad_b_bad_prod/latest/run.log
```
  UVM_ERROR @ 5472.235833 us: (chip_sw_rom_e2e_base_vseq.sv:35) [uvm_test_top.env.virtual_sequencer.chip_sw_rom_e2e_sigverify_always_a_bad_b_bad_vseq] Check failed "OpenTitan:4001-0002-01
  GIT:" == "BFV:07535603
  LCV:2318c631
  "
  UVM_INFO @ 5472.235833 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
```
- Test rom_e2e_sigverify_always_a_bad_b_bad_prod_end has 1 failures.
  - 0.rom_e2e_sigverify_always_a_bad_b_bad_prod_end.4346311213360867229678732279653769996213472192207789905407152906138695027645
    Line 1064, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_bad_b_bad_prod_end/latest/run.log
```
  UVM_ERROR @ 5421.275637 us: (chip_sw_rom_e2e_base_vseq.sv:35) [uvm_test_top.env.virtual_sequencer.chip_sw_rom_e2e_sigverify_always_a_bad_b_bad_vseq] Check failed "OpenTitan:4001-0002-01
  GIT:" == "BFV:07535603
  LCV:25294a52
  "
  UVM_INFO @ 5421.275637 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
```
- Test rom_e2e_sigverify_always_a_bad_b_bad_rma has 1 failures.
  - 0.rom_e2e_sigverify_always_a_bad_b_bad_rma.56730160693904929053137483628381608037089214956706374704467428675017623175516
    Line 968, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_bad_b_bad_rma/latest/run.log
```
  UVM_ERROR @ 4641.355917 us: (chip_sw_rom_e2e_base_vseq.sv:35) [uvm_test_top.env.virtual_sequencer.chip_sw_rom_e2e_sigverify_always_a_bad_b_bad_vseq] Check failed "OpenTitan:4001-0002-01
  GIT:" == "BFV:07535603
  LCV:2739ce73
  "
  UVM_INFO @ 4641.355917 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
```
- ... and 10 more tests.
Job chip_earlgrey_asic-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 11 failures:
- Test chip_sw_rv_timer_systick_test has 3 failures.
  - 0.chip_sw_rv_timer_systick_test.77481912522142883324924658012458780023250097908714788243346190365080548729926
    Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_sw_rv_timer_systick_test/latest/run.log
```
  Job ID: smart:ac8135f1-c708-43cc-a062-fde5056cc61e
```
  - 1.chip_sw_rv_timer_systick_test.81501616305320066570450760717766952128309099366269219160668184230215363084410
    Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.chip_sw_rv_timer_systick_test/latest/run.log
```
  Job ID: smart:42b783d6-be22-4370-b595-2328d24950bd
```
  - ... and 1 more failures.
- Test chip_sw_coremark has 1 failures.
  - 0.chip_sw_coremark.29658159053936453646677769097651818643138111358162453312779850676551731246863
    Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_sw_coremark/latest/run.log
```
  Job ID: smart:e26f145b-862b-466b-a693-10717b6519a7
```
- Test chip_sw_csrng_edn_concurrency_reduced_freq has 2 failures.
  - 0.chip_sw_csrng_edn_concurrency_reduced_freq.19692563882165055457515911380159804148548163841943677659216744417671477050157
    Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_sw_csrng_edn_concurrency_reduced_freq/latest/run.log
```
  Job ID: smart:5be64fc7-844b-404c-bcaa-ebaaecf6529b
```
  - 1.chip_sw_csrng_edn_concurrency_reduced_freq.22845424993402037741993606844823336834541270754336590202122534009366073056651
    Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.chip_sw_csrng_edn_concurrency_reduced_freq/latest/run.log
```
  Job ID: smart:b37cba50-474b-4af3-bf98-57fc9f80ade3
```
- Test chip_sw_ast_clk_rst_inputs has 2 failures.
  - 0.chip_sw_ast_clk_rst_inputs.20110251899679150585958504114016155556077334066032954420717139684712945791879
    Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_sw_ast_clk_rst_inputs/latest/run.log
```
  Job ID: smart:934b115d-c29e-432f-b33c-830b107e4431
```
  - 2.chip_sw_ast_clk_rst_inputs.81398261755793846653963206831239879029989304590088184300852762575961983890731
    Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/2.chip_sw_ast_clk_rst_inputs/latest/run.log
```
  Job ID: smart:376e70ef-4698-4114-9e46-f31762031c96
```
- Test chip_sw_power_virus has 3 failures.
  - 0.chip_sw_power_virus.38930782288094186023582788484883635895770148566195586699341073003879412522629
    Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_sw_power_virus/latest/run.log
```
  Job ID: smart:0cfdbce0-d174-4a9e-b932-4e728173be5a
```
  - 1.chip_sw_power_virus.105543679634139655054615942637513116692196275947402611752046830345691079137967
    Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.chip_sw_power_virus/latest/run.log
```
  Job ID: smart:869fb03f-de70-4d82-8c92-1fd89a1ee44c
```
  - ... and 1 more failures.
UVM_FATAL @ * us: (jtag_driver.sv:124) [driver] wait timeout occurred! has 4 failures:
- Test chip_tap_straps_rma has 2 failures.
  - 2.chip_tap_straps_rma.52004451839958855392712294906737912206051118396387817774310530361709356040236
    Line 6000, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/2.chip_tap_straps_rma/latest/run.log
```
  UVM_FATAL @ 16793.785458 us: (jtag_driver.sv:124) [uvm_test_top.env.m_jtag_riscv_agent.m_jtag_agent.driver] wait timeout occurred!
  UVM_INFO @ 16793.785458 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 3.chip_tap_straps_rma.33938422669444714513150593562162398048922136648156864396607272048802657788812
    Line 5960, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/3.chip_tap_straps_rma/latest/run.log
```
  UVM_FATAL @ 13092.741981 us: (jtag_driver.sv:124) [uvm_test_top.env.m_jtag_riscv_agent.m_jtag_agent.driver] wait timeout occurred!
  UVM_INFO @ 13092.741981 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test chip_tap_straps_prod has 1 failures.
  - 3.chip_tap_straps_prod.40312048603128419502938690727951216157915704359300544294418782687643112667075
    Line 5945, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/3.chip_tap_straps_prod/latest/run.log
```
  UVM_FATAL @ 12476.524173 us: (jtag_driver.sv:124) [uvm_test_top.env.m_jtag_riscv_agent.m_jtag_agent.driver] wait timeout occurred!
  UVM_INFO @ 12476.524173 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test chip_tap_straps_testunlock0 has 1 failures.
  - 4.chip_tap_straps_testunlock0.88490965837768796719858150005706015871517778862724240505584105262331736063963
    Line 5961, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/4.chip_tap_straps_testunlock0/latest/run.log
```
  UVM_FATAL @ 14979.434499 us: (jtag_driver.sv:124) [uvm_test_top.env.m_jtag_riscv_agent.m_jtag_agent.driver] wait timeout occurred!
  UVM_INFO @ 14979.434499 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/test_framework/ottf_isrs.c:99)] FAULT: Load Access Fault. MCAUSE=* MEPC=* MTVAL=* has 4 failures:
- Test chip_sw_alert_handler_lpg_sleep_mode_alerts has 4 failures.
  - 41.chip_sw_alert_handler_lpg_sleep_mode_alerts.60125720665749634904581449628621456278536753391689741216369434280362265326760
    Line 832, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/41.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log
```
  UVM_ERROR @ 3739.752972 us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/test_framework/ottf_isrs.c:99)] FAULT: Load Access Fault. MCAUSE=00000005 MEPC=20003720 MTVAL=40600800
  UVM_INFO @ 3739.752972 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 47.chip_sw_alert_handler_lpg_sleep_mode_alerts.49916971236716277765931301717557215927145376872757043264227420005028336873568
    Line 848, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/47.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log
```
  UVM_ERROR @ 3865.332640 us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/test_framework/ottf_isrs.c:99)] FAULT: Load Access Fault. MCAUSE=00000005 MEPC=20003720 MTVAL=40600800
  UVM_INFO @ 3865.332640 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 2 more failures.
UVM_FATAL @ * us: (chip_sw_rv_dm_access_after_wakeup_vseq.sv:56) [chip_sw_rv_dm_access_after_wakeup_vseq] Timed out waiting for device to enter normal sleep. has 3 failures:
- Test chip_sw_rv_dm_access_after_wakeup has 3 failures.
  - 0.chip_sw_rv_dm_access_after_wakeup.9110680016900414065976616340136005030244610964048461007021856672877830083258
    Line 747, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_sw_rv_dm_access_after_wakeup/latest/run.log
```
  UVM_FATAL @ 3487.825645 us: (chip_sw_rv_dm_access_after_wakeup_vseq.sv:56) [uvm_test_top.env.virtual_sequencer.chip_sw_rv_dm_access_after_wakeup_vseq] Timed out waiting for device to enter normal sleep.
  UVM_INFO @ 3487.825645 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 1.chip_sw_rv_dm_access_after_wakeup.104625294896755141411870212167307280143488055058332288285441987944621682810531
    Line 756, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.chip_sw_rv_dm_access_after_wakeup/latest/run.log
```
  UVM_FATAL @ 3773.971542 us: (chip_sw_rv_dm_access_after_wakeup_vseq.sv:56) [uvm_test_top.env.virtual_sequencer.chip_sw_rv_dm_access_after_wakeup_vseq] Timed out waiting for device to enter normal sleep.
  UVM_INFO @ 3773.971542 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 1 more failures.
UVM_ERROR @ * us: (chip_sw_rom_e2e_base_vseq.sv:35) [chip_sw_rom_e2e_shutdown_exception_c_vseq] Check failed "OpenTitan:*-*-* has 3 failures:
- Test rom_e2e_shutdown_exception_c has 3 failures.
  - 0.rom_e2e_shutdown_exception_c.72139691631211326752270397473837049069298690848841639360243676590325665779833
    Line 922, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.rom_e2e_shutdown_exception_c/latest/run.log
```
  UVM_ERROR @ 4476.468073 us: (chip_sw_rom_e2e_base_vseq.sv:35) [uvm_test_top.env.virtual_sequencer.chip_sw_rom_e2e_shutdown_exception_c_vseq] Check failed "OpenTitan:4001-0002-01
  GIT:" == "BFV:01495202
  LCV:2739ce73
  "
  UVM_INFO @ 4476.468073 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
```
  - 1.rom_e2e_shutdown_exception_c.101859047853862346573140858219226719992146356495973684399761468085336121913526
    Line 974, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.rom_e2e_shutdown_exception_c/latest/run.log
```
  UVM_ERROR @ 4844.811345 us: (chip_sw_rom_e2e_base_vseq.sv:35) [uvm_test_top.env.virtual_sequencer.chip_sw_rom_e2e_shutdown_exception_c_vseq] Check failed "OpenTitan:4001-0002-01
  GIT:" == "BFV:01495202
  LCV:2739ce73
  "
  UVM_INFO @ 4844.811345 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
```
  - ... and 1 more failures.
UVM_ERROR @ * us: (chip_sw_rom_e2e_base_vseq.sv:35) [chip_sw_rom_e2e_shutdown_output_vseq] Check failed "OpenTitan:*-*-* has 3 failures:
- Test rom_e2e_shutdown_output has 3 failures.
  - 0.rom_e2e_shutdown_output.50906195542260948105176043103717180385466015480249743918458419506748949333902
    Line 1004, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.rom_e2e_shutdown_output/latest/run.log
```
  UVM_ERROR @ 6483.322461 us: (chip_sw_rom_e2e_base_vseq.sv:35) [uvm_test_top.env.virtual_sequencer.chip_sw_rom_e2e_shutdown_output_vseq] Check failed "OpenTitan:4001-0002-01
  GIT:" == "BFV:0142500d
  LCV:02108421
  "
  UVM_INFO @ 6483.322461 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
```
  - 1.rom_e2e_shutdown_output.7283541157380923148652692968117464569332901268901521786131395096073308627473
    Line 1040, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.rom_e2e_shutdown_output/latest/run.log
```
  UVM_ERROR @ 6382.118898 us: (chip_sw_rom_e2e_base_vseq.sv:35) [uvm_test_top.env.virtual_sequencer.chip_sw_rom_e2e_shutdown_output_vseq] Check failed "OpenTitan:4001-0002-01
  GIT:" == "BFV:0142500d
  LCV:02108421
  "
  UVM_INFO @ 6382.118898 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
```
  - ... and 1 more failures.
UVM_FATAL @ * us: (dv_utils_pkg.sv:269) [sw_symbol_get_addr_size] Check failed (ret) Failed to read line from "uart_putchar.dat" has 3 failures:
- Test rom_e2e_jtag_debug_test_unlocked0 has 1 failures.
  - 0.rom_e2e_jtag_debug_test_unlocked0.40788911420662059287216759793691650031413763360154736018718604895116921555878
    Line 776, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.rom_e2e_jtag_debug_test_unlocked0/latest/run.log
```
  UVM_FATAL @ 7511.052000 us: (dv_utils_pkg.sv:269) [sw_symbol_get_addr_size] Check failed (ret) Failed to read line from "uart_putchar.dat"
  UVM_INFO @ 7511.052000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_jtag_debug_dev has 1 failures.
  - 0.rom_e2e_jtag_debug_dev.34365648617191327516326528649683027979439287173510778009694166372847861937211
    Line 811, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.rom_e2e_jtag_debug_dev/latest/run.log
```
  UVM_FATAL @ 7841.581500 us: (dv_utils_pkg.sv:269) [sw_symbol_get_addr_size] Check failed (ret) Failed to read line from "uart_putchar.dat"
  UVM_INFO @ 7841.581500 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_jtag_debug_rma has 1 failures.
  - 0.rom_e2e_jtag_debug_rma.589325545326546213973814091267169434830047368749381825020453232168478217138
    Line 794, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.rom_e2e_jtag_debug_rma/latest/run.log
```
  UVM_FATAL @ 6973.002000 us: (dv_utils_pkg.sv:269) [sw_symbol_get_addr_size] Check failed (ret) Failed to read line from "uart_putchar.dat"
  UVM_INFO @ 6973.002000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_ERROR @ * us: (chip_sw_base_vseq.sv:306) virtual_sequencer [chip_sw_lc_raw_unlock_vseq] SW TEST TIMED OUT. STATE: SwTestStatusBooted, TIMEOUT = * ns has 3 failures:

Test rom_raw_unlock has 3 failures.

0.rom_raw_unlock.94240963699260194208888026962499731380150509520168793092635059239977433181352
Line 795, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.rom_raw_unlock/latest/run.log

  UVM_ERROR @ 205695.283028 us: (chip_sw_base_vseq.sv:306) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_lc_raw_unlock_vseq] SW TEST TIMED OUT. STATE: SwTestStatusBooted, TIMEOUT = 200000000 ns
  
  UVM_INFO @ 205695.283028 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

1.rom_raw_unlock.49140081974299847097362240935913380644101492867216216421807355515330279144376
Line 768, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.rom_raw_unlock/latest/run.log

  UVM_ERROR @ 205059.488241 us: (chip_sw_base_vseq.sv:306) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_lc_raw_unlock_vseq] SW TEST TIMED OUT. STATE: SwTestStatusBooted, TIMEOUT = 200000000 ns
  
  UVM_INFO @ 205059.488241 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 1 more failures.

UVM_ERROR @ * us: (sw_logger_if.sv:526) [all_escalation_resets_test_sim_dv(w/device/tests/sim_dv/all_escalation_resets_test.c:468)] CHECK-fail: Unexpected mtval: expected *, got * has 3 failures:
- Test chip_sw_all_escalation_resets has 3 failures.
  - 58.chip_sw_all_escalation_resets.69159140453850402025889525359719491464004054411511283843283968698015501575141
    Line 783, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/58.chip_sw_all_escalation_resets/latest/run.log
```
  UVM_ERROR @ 3490.358154 us: (sw_logger_if.sv:526) [all_escalation_resets_test_sim_dv(w/device/tests/sim_dv/all_escalation_resets_test.c:468)] CHECK-fail: Unexpected mtval: expected 0x40600000, got 0x40600804
  UVM_INFO @ 3490.358154 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 60.chip_sw_all_escalation_resets.70899675891679522515327761163177947305819676788260356786795501593270525503834
    Line 795, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/60.chip_sw_all_escalation_resets/latest/run.log
```
  UVM_ERROR @ 2780.249116 us: (sw_logger_if.sv:526) [all_escalation_resets_test_sim_dv(w/device/tests/sim_dv/all_escalation_resets_test.c:468)] CHECK-fail: Unexpected mtval: expected 0x40600000, got 0x40600804
  UVM_INFO @ 2780.249116 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 1 more failures.
Offending '(pend_req[h2d.a_source].pend == *)' has 1 failures:
- Test chip_sw_pwrmgr_normal_sleep_all_reset_reqs has 1 failures.
  - 1.chip_sw_pwrmgr_normal_sleep_all_reset_reqs.92828069928011663590599306434660227570543511035403296950863016325273793699535
    Line 859, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.chip_sw_pwrmgr_normal_sleep_all_reset_reqs/latest/run.log
```
      Offending '(pend_req[h2d.a_source].pend == 0)'
  UVM_ERROR @ 6793.383442 us: (tlul_assert.sv:268) [ASSERT FAILED] pendingReqPerSrc_M
  UVM_INFO @ 6793.383442 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [pwrmgr_lowpower_cancel_test_sim_dv(sw/device/tests/pwrmgr_lowpower_cancel_test.c:84)] CHECK-fail: Timed out after * usec (* CPU cycles) waiting for !get_wakeup_status() has 1 failures:
- Test chip_sw_pwrmgr_lowpower_cancel has 1 failures.
  - 1.chip_sw_pwrmgr_lowpower_cancel.42286392038400136493663404917337920751334311126450355262987845428613982183477
    Line 774, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.chip_sw_pwrmgr_lowpower_cancel/latest/run.log
```
  UVM_ERROR @ 3231.198712 us: (sw_logger_if.sv:526) [pwrmgr_lowpower_cancel_test_sim_dv(sw/device/tests/pwrmgr_lowpower_cancel_test.c:84)] CHECK-fail: Timed out after 100 usec (10000 CPU cycles) waiting for !get_wakeup_status()
  UVM_INFO @ 3231.198712 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```