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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
96.15 95.47 94.09 95.20 94.91 97.71 99.54


Total test records in report: 2885
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T171 /workspace/coverage/default/1.chip_sw_sram_ctrl_execution_main.3925421605 Jun 28 08:08:32 PM PDT 24 Jun 28 08:23:46 PM PDT 24 6813584588 ps
T918 /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_good_prod.3176492939 Jun 28 08:11:46 PM PDT 24 Jun 28 09:17:43 PM PDT 24 14988812932 ps
T163 /workspace/coverage/default/0.chip_sw_lc_ctrl_program_error.670427876 Jun 28 08:04:41 PM PDT 24 Jun 28 08:14:24 PM PDT 24 6004164824 ps
T919 /workspace/coverage/default/0.chip_sw_pwrmgr_deep_sleep_power_glitch_reset.2959034892 Jun 28 08:05:32 PM PDT 24 Jun 28 08:12:40 PM PDT 24 7639163300 ps
T206 /workspace/coverage/default/2.chip_sw_i2c_host_tx_rx.4305167 Jun 28 08:15:17 PM PDT 24 Jun 28 08:30:14 PM PDT 24 5020872740 ps
T920 /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_bad_dev.1658308599 Jun 28 08:07:42 PM PDT 24 Jun 28 09:25:27 PM PDT 24 15171282362 ps
T921 /workspace/coverage/default/1.rom_e2e_asm_init_prod.2772754253 Jun 28 08:15:15 PM PDT 24 Jun 28 09:24:18 PM PDT 24 15607837560 ps
T922 /workspace/coverage/default/13.chip_sw_uart_rand_baudrate.4006708552 Jun 28 08:28:05 PM PDT 24 Jun 28 08:37:25 PM PDT 24 3646470766 ps
T397 /workspace/coverage/default/0.chip_sw_clkmgr_off_peri.1656341967 Jun 28 08:04:15 PM PDT 24 Jun 28 08:34:40 PM PDT 24 12614630916 ps
T923 /workspace/coverage/default/0.chip_sw_example_flash.424272585 Jun 28 08:05:06 PM PDT 24 Jun 28 08:09:03 PM PDT 24 2612908416 ps
T721 /workspace/coverage/default/37.chip_sw_alert_handler_lpg_sleep_mode_alerts.4279395770 Jun 28 08:29:32 PM PDT 24 Jun 28 08:36:42 PM PDT 24 3270231880 ps
T924 /workspace/coverage/default/1.chip_sw_aon_timer_sleep_wdog_sleep_pause.1295262534 Jun 28 08:05:28 PM PDT 24 Jun 28 08:13:43 PM PDT 24 6403275612 ps
T432 /workspace/coverage/default/0.chip_sw_kmac_entropy.1064136398 Jun 28 07:59:51 PM PDT 24 Jun 28 08:05:27 PM PDT 24 2471373700 ps
T636 /workspace/coverage/default/27.chip_sw_all_escalation_resets.1681171896 Jun 28 08:30:21 PM PDT 24 Jun 28 08:42:48 PM PDT 24 6158800926 ps
T717 /workspace/coverage/default/0.chip_sw_ast_clk_outputs.3287297577 Jun 28 08:01:45 PM PDT 24 Jun 28 08:17:47 PM PDT 24 8154600064 ps
T925 /workspace/coverage/default/1.rom_e2e_static_critical.4242417167 Jun 28 08:14:54 PM PDT 24 Jun 28 09:20:45 PM PDT 24 16727523896 ps
T926 /workspace/coverage/default/18.chip_sw_uart_rand_baudrate.357284887 Jun 28 08:27:06 PM PDT 24 Jun 28 08:53:39 PM PDT 24 9100007284 ps
T927 /workspace/coverage/default/1.chip_sw_flash_ctrl_idle_low_power.1691418271 Jun 28 08:06:02 PM PDT 24 Jun 28 08:13:11 PM PDT 24 3383645968 ps
T196 /workspace/coverage/default/2.chip_sw_uart_tx_rx_bootstrap.3889459738 Jun 28 08:17:02 PM PDT 24 Jun 29 12:26:34 AM PDT 24 78897230024 ps
T36 /workspace/coverage/default/0.chip_sw_gpio.2302294467 Jun 28 08:03:51 PM PDT 24 Jun 28 08:13:59 PM PDT 24 3744042024 ps
T166 /workspace/coverage/default/2.chip_sw_flash_init_reduced_freq.3947226210 Jun 28 08:21:42 PM PDT 24 Jun 28 08:56:13 PM PDT 24 24033619846 ps
T928 /workspace/coverage/default/0.rom_e2e_keymgr_init_rom_ext_invalid_meas.3385064608 Jun 28 08:07:44 PM PDT 24 Jun 28 09:24:19 PM PDT 24 14865522498 ps
T67 /workspace/coverage/default/1.chip_tap_straps_testunlock0.1484512299 Jun 28 08:10:34 PM PDT 24 Jun 28 08:28:32 PM PDT 24 9325500237 ps
T773 /workspace/coverage/default/6.chip_sw_alert_handler_lpg_sleep_mode_alerts.3771832249 Jun 28 08:26:01 PM PDT 24 Jun 28 08:32:53 PM PDT 24 4294926470 ps
T168 /workspace/coverage/default/0.chip_sw_lc_ctrl_test_locked0_to_scrap.2154931296 Jun 28 08:05:32 PM PDT 24 Jun 28 08:07:51 PM PDT 24 2721261814 ps
T929 /workspace/coverage/default/0.chip_sw_rv_core_ibex_rnd.1967268685 Jun 28 08:05:07 PM PDT 24 Jun 28 08:22:23 PM PDT 24 5872543912 ps
T930 /workspace/coverage/default/1.chip_sw_edn_sw_mode.1309069019 Jun 28 08:02:49 PM PDT 24 Jun 28 08:24:32 PM PDT 24 8023066440 ps
T931 /workspace/coverage/default/0.chip_sw_aon_timer_smoketest.511509750 Jun 28 08:02:19 PM PDT 24 Jun 28 08:07:46 PM PDT 24 2956690096 ps
T276 /workspace/coverage/default/2.chip_sw_sram_ctrl_scrambled_access_jitter_en.2208226340 Jun 28 08:22:43 PM PDT 24 Jun 28 08:33:40 PM PDT 24 5484704107 ps
T368 /workspace/coverage/default/30.chip_sw_alert_handler_lpg_sleep_mode_alerts.1657823402 Jun 28 08:26:51 PM PDT 24 Jun 28 08:33:15 PM PDT 24 3887567912 ps
T164 /workspace/coverage/default/1.chip_sw_lc_ctrl_program_error.1010593563 Jun 28 08:08:21 PM PDT 24 Jun 28 08:15:05 PM PDT 24 4866313574 ps
T326 /workspace/coverage/default/2.chip_sw_i2c_host_tx_rx_idx1.1322714264 Jun 28 08:16:01 PM PDT 24 Jun 28 08:34:50 PM PDT 24 5137943068 ps
T932 /workspace/coverage/default/0.chip_sw_aon_timer_wdog_bite_reset.1614753585 Jun 28 08:06:53 PM PDT 24 Jun 28 08:19:58 PM PDT 24 8142452784 ps
T10 /workspace/coverage/default/1.chip_sw_pwrmgr_random_sleep_all_wake_ups.1508750249 Jun 28 08:05:33 PM PDT 24 Jun 28 08:34:09 PM PDT 24 25375295552 ps
T83 /workspace/coverage/default/2.chip_sw_alert_handler_lpg_sleep_mode_pings.1778233307 Jun 28 08:20:58 PM PDT 24 Jun 28 08:44:58 PM PDT 24 10692299370 ps
T933 /workspace/coverage/default/2.chip_sw_otp_ctrl_ecc_error_vendor_test.1262358779 Jun 28 08:17:01 PM PDT 24 Jun 28 08:21:28 PM PDT 24 3138517504 ps
T934 /workspace/coverage/default/2.chip_sw_hmac_enc_idle.1718031277 Jun 28 08:19:21 PM PDT 24 Jun 28 08:26:05 PM PDT 24 2881987756 ps
T935 /workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_fast_dev.1640485667 Jun 28 08:20:46 PM PDT 24 Jun 28 08:33:28 PM PDT 24 4074931740 ps
T936 /workspace/coverage/default/1.chip_sw_keymgr_sideload_kmac.3261344809 Jun 28 08:08:23 PM PDT 24 Jun 28 08:37:11 PM PDT 24 8300369004 ps
T937 /workspace/coverage/default/0.chip_sw_otp_ctrl_lc_signals_dev.3379448837 Jun 28 08:04:22 PM PDT 24 Jun 28 08:31:19 PM PDT 24 8822210912 ps
T385 /workspace/coverage/default/1.chip_sw_rv_core_ibex_lockstep_glitch.2306333499 Jun 28 08:07:36 PM PDT 24 Jun 28 08:10:22 PM PDT 24 2805708980 ps
T693 /workspace/coverage/default/4.chip_sw_alert_handler_lpg_sleep_mode_alerts.4185886994 Jun 28 08:26:07 PM PDT 24 Jun 28 08:36:09 PM PDT 24 4297951118 ps
T687 /workspace/coverage/default/16.chip_sw_all_escalation_resets.3515173713 Jun 28 08:25:40 PM PDT 24 Jun 28 08:36:01 PM PDT 24 4610536868 ps
T359 /workspace/coverage/default/1.chip_sw_aon_timer_irq.2169582238 Jun 28 08:05:06 PM PDT 24 Jun 28 08:12:00 PM PDT 24 3594313556 ps
T723 /workspace/coverage/default/43.chip_sw_alert_handler_lpg_sleep_mode_alerts.3170860728 Jun 28 08:33:58 PM PDT 24 Jun 28 08:42:22 PM PDT 24 3503566650 ps
T938 /workspace/coverage/default/2.chip_sw_pwrmgr_normal_sleep_all_reset_reqs.1268997868 Jun 28 08:17:37 PM PDT 24 Jun 28 08:46:20 PM PDT 24 13674414521 ps
T175 /workspace/coverage/default/1.chip_sw_csrng_lc_hw_debug_en_test.406003444 Jun 28 08:02:44 PM PDT 24 Jun 28 08:15:04 PM PDT 24 7879661433 ps
T939 /workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_fast_rma.1232631186 Jun 28 08:12:46 PM PDT 24 Jun 28 08:23:14 PM PDT 24 3311518136 ps
T328 /workspace/coverage/default/2.chip_sw_i2c_host_tx_rx_idx2.2595049798 Jun 28 08:15:58 PM PDT 24 Jun 28 08:31:58 PM PDT 24 5391875476 ps
T319 /workspace/coverage/default/2.chip_plic_all_irqs_20.4167187838 Jun 28 08:21:34 PM PDT 24 Jun 28 08:34:15 PM PDT 24 4539414584 ps
T940 /workspace/coverage/default/9.chip_sw_csrng_edn_concurrency.3813358102 Jun 28 08:29:04 PM PDT 24 Jun 28 09:03:47 PM PDT 24 8851747666 ps
T745 /workspace/coverage/default/51.chip_sw_alert_handler_lpg_sleep_mode_alerts.451379588 Jun 28 08:29:11 PM PDT 24 Jun 28 08:38:31 PM PDT 24 3259021662 ps
T941 /workspace/coverage/default/2.chip_sw_pwrmgr_sleep_wake_5_bug.3161888960 Jun 28 08:21:44 PM PDT 24 Jun 28 08:30:28 PM PDT 24 5616314970 ps
T942 /workspace/coverage/default/0.chip_sw_kmac_mode_cshake.680904980 Jun 28 08:00:42 PM PDT 24 Jun 28 08:05:06 PM PDT 24 3021187964 ps
T218 /workspace/coverage/default/2.chip_sw_keymgr_key_derivation.1101826686 Jun 28 08:20:43 PM PDT 24 Jun 28 09:02:38 PM PDT 24 12753306680 ps
T259 /workspace/coverage/default/0.chip_sw_rstmgr_cpu_info.3367177247 Jun 28 08:05:19 PM PDT 24 Jun 28 08:14:52 PM PDT 24 5681971496 ps
T311 /workspace/coverage/default/65.chip_sw_alert_handler_lpg_sleep_mode_alerts.3539158948 Jun 28 08:31:22 PM PDT 24 Jun 28 08:39:32 PM PDT 24 3658681620 ps
T24 /workspace/coverage/default/1.chip_sw_spi_device_pass_through.1299187409 Jun 28 08:04:38 PM PDT 24 Jun 28 08:16:23 PM PDT 24 6211561457 ps
T943 /workspace/coverage/default/1.chip_sw_kmac_mode_cshake.1086450184 Jun 28 08:04:15 PM PDT 24 Jun 28 08:09:19 PM PDT 24 3564383768 ps
T944 /workspace/coverage/default/0.chip_sw_pwrmgr_random_sleep_power_glitch_reset.262857390 Jun 28 08:05:08 PM PDT 24 Jun 28 09:02:29 PM PDT 24 34799929148 ps
T347 /workspace/coverage/default/54.chip_sw_all_escalation_resets.125798506 Jun 28 08:31:30 PM PDT 24 Jun 28 08:42:31 PM PDT 24 4910583656 ps
T338 /workspace/coverage/default/2.chip_sw_flash_ctrl_ops_jitter_en_reduced_freq.3592212268 Jun 28 08:23:36 PM PDT 24 Jun 28 08:35:56 PM PDT 24 5701765193 ps
T945 /workspace/coverage/default/2.chip_sw_kmac_idle.702175548 Jun 28 08:26:16 PM PDT 24 Jun 28 08:30:40 PM PDT 24 2488375622 ps
T729 /workspace/coverage/default/35.chip_sw_alert_handler_lpg_sleep_mode_alerts.4050068781 Jun 28 08:29:45 PM PDT 24 Jun 28 08:36:52 PM PDT 24 3316761384 ps
T353 /workspace/coverage/default/2.chip_sw_uart_tx_rx_idx3.2081782937 Jun 28 08:15:18 PM PDT 24 Jun 28 08:26:41 PM PDT 24 4936662020 ps
T946 /workspace/coverage/default/0.chip_sw_clkmgr_off_kmac_trans.2929547393 Jun 28 08:01:24 PM PDT 24 Jun 28 08:11:34 PM PDT 24 5886197344 ps
T947 /workspace/coverage/default/0.chip_sw_csrng_fuse_en_sw_app_read_test.1447288197 Jun 28 08:04:59 PM PDT 24 Jun 28 08:11:08 PM PDT 24 3709460578 ps
T948 /workspace/coverage/default/0.chip_sw_csrng_kat_test.4066685810 Jun 28 08:03:54 PM PDT 24 Jun 28 08:08:42 PM PDT 24 2782299320 ps
T369 /workspace/coverage/default/13.chip_sw_alert_handler_lpg_sleep_mode_alerts.2764845837 Jun 28 08:27:19 PM PDT 24 Jun 28 08:34:35 PM PDT 24 3995157368 ps
T949 /workspace/coverage/default/2.chip_sw_rstmgr_smoketest.1611731263 Jun 28 08:23:02 PM PDT 24 Jun 28 08:26:16 PM PDT 24 3078582920 ps
T51 /workspace/coverage/default/1.rom_e2e_shutdown_output.1704709570 Jun 28 08:15:29 PM PDT 24 Jun 28 09:26:42 PM PDT 24 30422348225 ps
T339 /workspace/coverage/default/2.chip_sw_flash_ctrl_ops.3433309091 Jun 28 08:16:28 PM PDT 24 Jun 28 08:29:41 PM PDT 24 3399895668 ps
T950 /workspace/coverage/default/14.chip_sw_lc_ctrl_transition.1238482436 Jun 28 08:28:08 PM PDT 24 Jun 28 08:35:40 PM PDT 24 5287768386 ps
T951 /workspace/coverage/default/1.chip_sw_pwrmgr_sysrst_ctrl_reset.3115892647 Jun 28 08:06:28 PM PDT 24 Jun 28 08:24:27 PM PDT 24 6560431456 ps
T634 /workspace/coverage/default/1.chip_sw_csrng_edn_concurrency_reduced_freq.591782509 Jun 28 08:09:27 PM PDT 24 Jun 28 09:31:02 PM PDT 24 28104945603 ps
T952 /workspace/coverage/default/1.chip_sw_flash_crash_alert.3319532888 Jun 28 08:08:27 PM PDT 24 Jun 28 08:18:36 PM PDT 24 4953479074 ps
T953 /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_bad_prod.566767324 Jun 28 08:09:26 PM PDT 24 Jun 28 09:15:16 PM PDT 24 16025980344 ps
T954 /workspace/coverage/default/2.chip_sw_lc_walkthrough_testunlocks.3882675309 Jun 28 08:17:10 PM PDT 24 Jun 28 08:47:53 PM PDT 24 22303630646 ps
T266 /workspace/coverage/default/2.chip_sw_data_integrity_escalation.982614471 Jun 28 08:14:16 PM PDT 24 Jun 28 08:31:46 PM PDT 24 5346310224 ps
T268 /workspace/coverage/default/33.chip_sw_alert_handler_lpg_sleep_mode_alerts.379499653 Jun 28 08:30:30 PM PDT 24 Jun 28 08:38:48 PM PDT 24 3869114680 ps
T33 /workspace/coverage/default/1.chip_sw_sysrst_ctrl_ec_rst_l.2488899516 Jun 28 08:05:47 PM PDT 24 Jun 28 09:10:03 PM PDT 24 20985648628 ps
T269 /workspace/coverage/default/1.chip_sw_flash_ctrl_ops.60329002 Jun 28 08:05:58 PM PDT 24 Jun 28 08:15:43 PM PDT 24 3744085350 ps
T270 /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_bad_b_good_prod_end.2817986084 Jun 28 08:11:01 PM PDT 24 Jun 28 10:05:40 PM PDT 24 24248851940 ps
T271 /workspace/coverage/default/96.chip_sw_all_escalation_resets.1292037062 Jun 28 08:33:25 PM PDT 24 Jun 28 08:45:55 PM PDT 24 5221567740 ps
T272 /workspace/coverage/default/2.rom_e2e_asm_init_prod_end.3245978456 Jun 28 08:27:21 PM PDT 24 Jun 28 09:29:27 PM PDT 24 15765731830 ps
T273 /workspace/coverage/default/0.chip_sw_all_escalation_resets.3236464802 Jun 28 08:00:56 PM PDT 24 Jun 28 08:16:16 PM PDT 24 5630768052 ps
T96 /workspace/coverage/default/0.chip_sw_pwrmgr_normal_sleep_all_wake_ups.2288998275 Jun 28 08:02:42 PM PDT 24 Jun 28 08:08:54 PM PDT 24 7251595674 ps
T274 /workspace/coverage/default/0.chip_sw_adc_ctrl_sleep_debug_cable_wakeup.3655783957 Jun 28 08:06:41 PM PDT 24 Jun 28 08:15:53 PM PDT 24 18682053736 ps
T199 /workspace/coverage/default/2.chip_sw_sysrst_ctrl_in_irq.1410269448 Jun 28 08:19:17 PM PDT 24 Jun 28 08:30:50 PM PDT 24 3949616318 ps
T955 /workspace/coverage/default/1.chip_sw_rstmgr_smoketest.1448399073 Jun 28 08:14:07 PM PDT 24 Jun 28 08:19:42 PM PDT 24 2580460180 ps
T956 /workspace/coverage/default/3.chip_sw_csrng_edn_concurrency.162524100 Jun 28 08:25:04 PM PDT 24 Jun 28 09:04:03 PM PDT 24 9918959454 ps
T957 /workspace/coverage/default/13.chip_sw_lc_ctrl_transition.524982397 Jun 28 08:26:29 PM PDT 24 Jun 28 08:40:25 PM PDT 24 10264775047 ps
T732 /workspace/coverage/default/99.chip_sw_all_escalation_resets.4043129185 Jun 28 08:34:48 PM PDT 24 Jun 28 08:46:39 PM PDT 24 4372701896 ps
T775 /workspace/coverage/default/3.chip_sw_all_escalation_resets.3275729245 Jun 28 08:24:09 PM PDT 24 Jun 28 08:38:20 PM PDT 24 5896789076 ps
T52 /workspace/coverage/default/2.rom_e2e_shutdown_output.4077817458 Jun 28 08:29:52 PM PDT 24 Jun 28 09:28:03 PM PDT 24 26430747720 ps
T688 /workspace/coverage/default/89.chip_sw_all_escalation_resets.1671686325 Jun 28 08:31:50 PM PDT 24 Jun 28 08:43:57 PM PDT 24 5889514540 ps
T958 /workspace/coverage/default/0.chip_sw_clkmgr_off_aes_trans.2637087793 Jun 28 08:04:40 PM PDT 24 Jun 28 08:13:53 PM PDT 24 5615583066 ps
T959 /workspace/coverage/default/1.chip_sw_example_manufacturer.3500254971 Jun 28 08:06:55 PM PDT 24 Jun 28 08:10:23 PM PDT 24 2896611900 ps
T960 /workspace/coverage/default/2.chip_sw_keymgr_sideload_kmac.2656425352 Jun 28 08:19:25 PM PDT 24 Jun 28 08:59:35 PM PDT 24 9856744996 ps
T718 /workspace/coverage/default/20.chip_sw_alert_handler_lpg_sleep_mode_alerts.3962183323 Jun 28 08:27:07 PM PDT 24 Jun 28 08:33:43 PM PDT 24 3874011192 ps
T703 /workspace/coverage/default/71.chip_sw_all_escalation_resets.1126835270 Jun 28 08:31:05 PM PDT 24 Jun 28 08:41:37 PM PDT 24 5488797600 ps
T360 /workspace/coverage/default/1.chip_sival_flash_info_access.1087864130 Jun 28 08:06:22 PM PDT 24 Jun 28 08:11:58 PM PDT 24 2960175008 ps
T766 /workspace/coverage/default/67.chip_sw_alert_handler_lpg_sleep_mode_alerts.2778926982 Jun 28 08:31:06 PM PDT 24 Jun 28 08:37:38 PM PDT 24 3544243676 ps
T722 /workspace/coverage/default/0.chip_sw_aes_masking_off.2528045621 Jun 28 08:05:39 PM PDT 24 Jun 28 08:12:28 PM PDT 24 3008541131 ps
T961 /workspace/coverage/default/3.chip_sw_uart_tx_rx.391538564 Jun 28 08:24:38 PM PDT 24 Jun 28 08:36:01 PM PDT 24 4439131700 ps
T962 /workspace/coverage/default/1.chip_sw_kmac_mode_kmac_jitter_en_reduced_freq.2575428586 Jun 28 08:08:24 PM PDT 24 Jun 28 08:12:42 PM PDT 24 3741006297 ps
T963 /workspace/coverage/default/6.chip_sw_csrng_edn_concurrency.4100078392 Jun 28 08:25:39 PM PDT 24 Jun 28 09:08:08 PM PDT 24 11446709920 ps
T964 /workspace/coverage/default/2.chip_sw_sram_ctrl_smoketest.2873918349 Jun 28 08:22:53 PM PDT 24 Jun 28 08:27:46 PM PDT 24 2659874644 ps
T965 /workspace/coverage/default/0.chip_sw_sleep_sram_ret_contents_scramble.3913921973 Jun 28 08:01:45 PM PDT 24 Jun 28 08:12:11 PM PDT 24 8747359804 ps
T37 /workspace/coverage/default/2.chip_sw_gpio_smoketest.2190603107 Jun 28 08:24:00 PM PDT 24 Jun 28 08:30:30 PM PDT 24 2810246473 ps
T643 /workspace/coverage/default/1.chip_sw_lc_ctrl_volatile_raw_unlock.132714211 Jun 28 08:05:42 PM PDT 24 Jun 28 08:08:03 PM PDT 24 2831117405 ps
T329 /workspace/coverage/default/4.chip_sw_uart_tx_rx_idx1.3779609548 Jun 28 08:24:54 PM PDT 24 Jun 28 08:34:26 PM PDT 24 4604337812 ps
T704 /workspace/coverage/default/51.chip_sw_all_escalation_resets.1491089377 Jun 28 08:29:15 PM PDT 24 Jun 28 08:39:01 PM PDT 24 5332876364 ps
T641 /workspace/coverage/default/2.chip_sw_rv_dm_access_after_escalation_reset.2166149164 Jun 28 08:27:23 PM PDT 24 Jun 28 08:37:28 PM PDT 24 5299306374 ps
T7 /workspace/coverage/default/1.chip_rv_dm_ndm_reset_req.2945597471 Jun 28 08:07:01 PM PDT 24 Jun 28 08:12:57 PM PDT 24 4214309386 ps
T417 /workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0.624994433 Jun 28 08:00:53 PM PDT 24 Jun 28 08:11:44 PM PDT 24 4202102360 ps
T418 /workspace/coverage/default/4.chip_tap_straps_dev.787360158 Jun 28 08:23:34 PM PDT 24 Jun 28 08:26:18 PM PDT 24 2682257675 ps
T419 /workspace/coverage/default/62.chip_sw_alert_handler_lpg_sleep_mode_alerts.1982213357 Jun 28 08:32:00 PM PDT 24 Jun 28 08:37:48 PM PDT 24 4341787880 ps
T277 /workspace/coverage/default/0.chip_sw_data_integrity_escalation.1416249787 Jun 28 08:01:25 PM PDT 24 Jun 28 08:17:08 PM PDT 24 5689529048 ps
T420 /workspace/coverage/default/52.chip_sw_all_escalation_resets.4121407254 Jun 28 08:29:05 PM PDT 24 Jun 28 08:41:23 PM PDT 24 6106377160 ps
T421 /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_good_rma.2244340218 Jun 28 08:12:03 PM PDT 24 Jun 28 09:18:55 PM PDT 24 14497661000 ps
T422 /workspace/coverage/default/1.chip_sw_rv_core_ibex_rnd.3721952605 Jun 28 08:05:59 PM PDT 24 Jun 28 08:22:50 PM PDT 24 5459904722 ps
T423 /workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_slow_dev.2870734583 Jun 28 08:20:58 PM PDT 24 Jun 28 08:32:58 PM PDT 24 4409942600 ps
T195 /workspace/coverage/default/1.chip_jtag_csr_rw.1313043376 Jun 28 07:59:08 PM PDT 24 Jun 28 08:22:30 PM PDT 24 11205263271 ps
T684 /workspace/coverage/default/89.chip_sw_alert_handler_lpg_sleep_mode_alerts.101143994 Jun 28 08:31:59 PM PDT 24 Jun 28 08:40:06 PM PDT 24 4074301818 ps
T966 /workspace/coverage/default/2.chip_sw_uart_tx_rx.3251789559 Jun 28 08:16:33 PM PDT 24 Jun 28 08:27:56 PM PDT 24 3920791830 ps
T135 /workspace/coverage/default/1.chip_sw_sensor_ctrl_status.1231227667 Jun 28 08:11:21 PM PDT 24 Jun 28 08:15:32 PM PDT 24 2530249237 ps
T967 /workspace/coverage/default/2.chip_sw_flash_ctrl_access.3087841889 Jun 28 08:15:38 PM PDT 24 Jun 28 08:33:22 PM PDT 24 5462373400 ps
T8 /workspace/coverage/default/0.chip_jtag_csr_rw.3541268598 Jun 28 07:52:17 PM PDT 24 Jun 28 08:32:37 PM PDT 24 20569876708 ps
T25 /workspace/coverage/default/0.chip_sw_spi_device_pass_through.3312547105 Jun 28 08:00:45 PM PDT 24 Jun 28 08:15:41 PM PDT 24 7011852581 ps
T411 /workspace/coverage/default/85.chip_sw_alert_handler_lpg_sleep_mode_alerts.2556066250 Jun 28 08:33:46 PM PDT 24 Jun 28 08:39:52 PM PDT 24 3751319458 ps
T412 /workspace/coverage/default/2.chip_sw_kmac_mode_cshake.1111384742 Jun 28 08:19:09 PM PDT 24 Jun 28 08:24:44 PM PDT 24 2403496862 ps
T342 /workspace/coverage/default/2.chip_sw_flash_ctrl_ops_jitter_en.1907150745 Jun 28 08:15:57 PM PDT 24 Jun 28 08:29:13 PM PDT 24 4242510894 ps
T413 /workspace/coverage/default/24.chip_sw_all_escalation_resets.2547149756 Jun 28 08:27:23 PM PDT 24 Jun 28 08:37:37 PM PDT 24 4945677736 ps
T414 /workspace/coverage/default/1.chip_sw_sleep_sram_ret_contents_no_scramble.660429225 Jun 28 08:09:11 PM PDT 24 Jun 28 08:20:07 PM PDT 24 7314409416 ps
T415 /workspace/coverage/default/2.chip_sw_csrng_lc_hw_debug_en_test.1147565426 Jun 28 08:18:28 PM PDT 24 Jun 28 08:32:20 PM PDT 24 6546644750 ps
T351 /workspace/coverage/default/1.chip_sw_flash_ctrl_ops_jitter_en.1288256517 Jun 28 08:06:27 PM PDT 24 Jun 28 08:18:36 PM PDT 24 4254783284 ps
T172 /workspace/coverage/default/1.chip_sw_rv_core_ibex_address_translation.642902374 Jun 28 08:09:49 PM PDT 24 Jun 28 08:15:07 PM PDT 24 3171669482 ps
T390 /workspace/coverage/default/0.chip_sw_lc_walkthrough_prodend.1903862696 Jun 28 08:05:37 PM PDT 24 Jun 28 08:26:43 PM PDT 24 9405139378 ps
T391 /workspace/coverage/default/68.chip_sw_all_escalation_resets.3902067496 Jun 28 08:32:14 PM PDT 24 Jun 28 08:44:14 PM PDT 24 5775503826 ps
T260 /workspace/coverage/default/82.chip_sw_all_escalation_resets.1708084783 Jun 28 08:33:40 PM PDT 24 Jun 28 08:40:34 PM PDT 24 4248116680 ps
T278 /workspace/coverage/default/4.chip_sw_data_integrity_escalation.820925678 Jun 28 08:26:13 PM PDT 24 Jun 28 08:38:41 PM PDT 24 4905573944 ps
T392 /workspace/coverage/default/2.chip_sw_otp_ctrl_smoketest.1787282273 Jun 28 08:23:10 PM PDT 24 Jun 28 08:28:52 PM PDT 24 2912997540 ps
T393 /workspace/coverage/default/66.chip_sw_alert_handler_lpg_sleep_mode_alerts.1778570616 Jun 28 08:33:03 PM PDT 24 Jun 28 08:40:04 PM PDT 24 4314678476 ps
T394 /workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_slow_rma.2580672337 Jun 28 08:14:07 PM PDT 24 Jun 28 08:25:43 PM PDT 24 5279127010 ps
T395 /workspace/coverage/default/10.chip_sw_alert_handler_lpg_sleep_mode_alerts.1885324574 Jun 28 08:28:28 PM PDT 24 Jun 28 08:35:12 PM PDT 24 4149078418 ps
T396 /workspace/coverage/default/77.chip_sw_alert_handler_lpg_sleep_mode_alerts.46308106 Jun 28 08:38:29 PM PDT 24 Jun 28 08:43:53 PM PDT 24 3242880536 ps
T968 /workspace/coverage/default/0.chip_sw_csrng_smoketest.3693762463 Jun 28 08:02:14 PM PDT 24 Jun 28 08:06:53 PM PDT 24 2447882120 ps
T719 /workspace/coverage/default/64.chip_sw_alert_handler_lpg_sleep_mode_alerts.1328068604 Jun 28 08:33:14 PM PDT 24 Jun 28 08:40:15 PM PDT 24 3675719236 ps
T969 /workspace/coverage/default/1.chip_sw_uart_tx_rx_idx2.3050966133 Jun 28 08:04:26 PM PDT 24 Jun 28 08:12:37 PM PDT 24 4279817680 ps
T970 /workspace/coverage/default/2.chip_sw_rstmgr_sw_req.188027856 Jun 28 08:16:23 PM PDT 24 Jun 28 08:23:25 PM PDT 24 3423465800 ps
T971 /workspace/coverage/default/1.chip_sw_entropy_src_ast_rng_req.1988826235 Jun 28 08:03:35 PM PDT 24 Jun 28 08:07:24 PM PDT 24 2311418660 ps
T972 /workspace/coverage/default/0.chip_sw_rstmgr_smoketest.2055260166 Jun 28 08:03:42 PM PDT 24 Jun 28 08:08:14 PM PDT 24 2714834196 ps
T973 /workspace/coverage/default/4.chip_tap_straps_testunlock0.50808419 Jun 28 08:24:31 PM PDT 24 Jun 28 08:29:44 PM PDT 24 3736343795 ps
T974 /workspace/coverage/default/2.chip_sw_alert_handler_lpg_reset_toggle.2656742827 Jun 28 08:18:36 PM PDT 24 Jun 28 08:46:03 PM PDT 24 8383992152 ps
T975 /workspace/coverage/default/19.chip_sw_uart_rand_baudrate.2935942864 Jun 28 08:27:12 PM PDT 24 Jun 28 08:36:13 PM PDT 24 3232889700 ps
T26 /workspace/coverage/default/1.chip_sw_spi_host_tx_rx.2959694241 Jun 28 08:06:14 PM PDT 24 Jun 28 08:09:46 PM PDT 24 3228079550 ps
T236 /workspace/coverage/default/2.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted.1938868769 Jun 28 08:21:15 PM PDT 24 Jun 28 08:29:09 PM PDT 24 4491056664 ps
T97 /workspace/coverage/default/0.chip_sw_pwrmgr_deep_sleep_all_wake_ups.2127232474 Jun 28 08:04:37 PM PDT 24 Jun 28 08:41:56 PM PDT 24 22386880604 ps
T148 /workspace/coverage/default/2.chip_plic_all_irqs_10.496472061 Jun 28 08:20:47 PM PDT 24 Jun 28 08:32:27 PM PDT 24 3529917312 ps
T508 /workspace/coverage/default/2.chip_sw_rv_core_ibex_nmi_irq.2659103665 Jun 28 08:19:14 PM PDT 24 Jun 28 08:35:42 PM PDT 24 4680508888 ps
T976 /workspace/coverage/default/1.chip_sw_rstmgr_sw_rst.3393861351 Jun 28 08:07:22 PM PDT 24 Jun 28 08:11:30 PM PDT 24 2709316500 ps
T197 /workspace/coverage/default/1.chip_sw_inject_scramble_seed.680421618 Jun 28 08:04:29 PM PDT 24 Jun 28 11:37:28 PM PDT 24 64207808094 ps
T977 /workspace/coverage/default/1.chip_sw_flash_ctrl_clock_freqs.2100587939 Jun 28 08:06:37 PM PDT 24 Jun 28 08:26:17 PM PDT 24 5618620725 ps
T978 /workspace/coverage/default/0.chip_sw_pwrmgr_sleep_power_glitch_reset.223223816 Jun 28 08:03:59 PM PDT 24 Jun 28 08:13:09 PM PDT 24 5817638170 ps
T979 /workspace/coverage/default/2.chip_sw_edn_sw_mode.1925962898 Jun 28 08:20:09 PM PDT 24 Jun 28 08:45:47 PM PDT 24 6700661000 ps
T980 /workspace/coverage/default/0.chip_sw_aes_enc_jitter_en_reduced_freq.957838565 Jun 28 08:09:15 PM PDT 24 Jun 28 08:13:24 PM PDT 24 3256097288 ps
T981 /workspace/coverage/default/0.chip_sw_otp_ctrl_ecc_error_vendor_test.1499146130 Jun 28 07:58:46 PM PDT 24 Jun 28 08:03:15 PM PDT 24 2832512828 ps
T695 /workspace/coverage/default/32.chip_sw_alert_handler_lpg_sleep_mode_alerts.2212471899 Jun 28 08:29:42 PM PDT 24 Jun 28 08:36:31 PM PDT 24 3933139156 ps
T982 /workspace/coverage/default/1.chip_sw_otbn_randomness.3726953704 Jun 28 08:11:22 PM PDT 24 Jun 28 08:27:22 PM PDT 24 5449664770 ps
T257 /workspace/coverage/default/2.chip_sw_alert_handler_entropy.1082870194 Jun 28 08:18:30 PM PDT 24 Jun 28 08:25:05 PM PDT 24 3445936272 ps
T983 /workspace/coverage/default/2.chip_sw_hmac_oneshot.3619207639 Jun 28 08:22:30 PM PDT 24 Jun 28 08:28:42 PM PDT 24 2774192502 ps
T362 /workspace/coverage/default/0.chip_sw_flash_ctrl_ops.2257104979 Jun 28 08:06:55 PM PDT 24 Jun 28 08:18:31 PM PDT 24 3698387456 ps
T984 /workspace/coverage/default/2.chip_sw_example_flash.3425284418 Jun 28 08:14:31 PM PDT 24 Jun 28 08:19:27 PM PDT 24 3027351344 ps
T985 /workspace/coverage/default/2.rom_e2e_asm_init_prod.3248034553 Jun 28 08:27:31 PM PDT 24 Jun 28 09:28:45 PM PDT 24 15518223822 ps
T986 /workspace/coverage/default/1.chip_sw_clkmgr_off_peri.3932831344 Jun 28 08:06:33 PM PDT 24 Jun 28 08:35:49 PM PDT 24 13089536164 ps
T333 /workspace/coverage/default/1.chip_sw_i2c_device_tx_rx.4166717314 Jun 28 08:05:49 PM PDT 24 Jun 28 08:15:25 PM PDT 24 4271399546 ps
T690 /workspace/coverage/default/44.chip_sw_all_escalation_resets.1520523476 Jun 28 08:28:52 PM PDT 24 Jun 28 08:41:49 PM PDT 24 5929296808 ps
T737 /workspace/coverage/default/41.chip_sw_all_escalation_resets.2853981799 Jun 28 08:28:38 PM PDT 24 Jun 28 08:40:56 PM PDT 24 5427974658 ps
T336 /workspace/coverage/default/1.chip_sw_pwrmgr_lowpower_cancel.1501483994 Jun 28 08:10:56 PM PDT 24 Jun 28 08:17:14 PM PDT 24 4244254756 ps
T987 /workspace/coverage/default/0.chip_sw_pwrmgr_main_power_glitch_reset.3448473635 Jun 28 08:02:37 PM PDT 24 Jun 28 08:09:20 PM PDT 24 4049313714 ps
T988 /workspace/coverage/default/2.chip_sw_pwrmgr_random_sleep_all_reset_reqs.2407355359 Jun 28 08:17:03 PM PDT 24 Jun 28 08:51:36 PM PDT 24 22610310326 ps
T989 /workspace/coverage/default/2.chip_sw_sleep_sram_ret_contents_scramble.2108508714 Jun 28 08:26:02 PM PDT 24 Jun 28 08:39:53 PM PDT 24 7723273560 ps
T136 /workspace/coverage/default/2.chip_sw_pwrmgr_full_aon_reset.307814516 Jun 28 08:16:30 PM PDT 24 Jun 28 08:26:12 PM PDT 24 8559983762 ps
T370 /workspace/coverage/default/88.chip_sw_all_escalation_resets.3790061952 Jun 28 08:34:34 PM PDT 24 Jun 28 08:43:56 PM PDT 24 4741861090 ps
T990 /workspace/coverage/default/1.chip_sw_aes_entropy.753207889 Jun 28 08:10:45 PM PDT 24 Jun 28 08:14:08 PM PDT 24 3067041182 ps
T991 /workspace/coverage/default/2.chip_sw_pwrmgr_main_power_glitch_reset.611449532 Jun 28 08:17:44 PM PDT 24 Jun 28 08:24:33 PM PDT 24 4797185884 ps
T992 /workspace/coverage/default/0.chip_sw_clkmgr_jitter.2740083005 Jun 28 08:03:21 PM PDT 24 Jun 28 08:07:43 PM PDT 24 2867192671 ps
T698 /workspace/coverage/default/26.chip_sw_alert_handler_lpg_sleep_mode_alerts.3441121490 Jun 28 08:30:22 PM PDT 24 Jun 28 08:38:18 PM PDT 24 4243914120 ps
T744 /workspace/coverage/default/64.chip_sw_all_escalation_resets.1956913101 Jun 28 08:30:46 PM PDT 24 Jun 28 08:39:24 PM PDT 24 4648187744 ps
T219 /workspace/coverage/default/1.chip_sw_keymgr_key_derivation_jitter_en.2939274641 Jun 28 08:04:34 PM PDT 24 Jun 28 08:24:03 PM PDT 24 8838624650 ps
T993 /workspace/coverage/default/1.chip_sw_otp_ctrl_lc_signals_test_unlocked0.1274456771 Jun 28 08:06:19 PM PDT 24 Jun 28 08:17:49 PM PDT 24 4076111960 ps
T994 /workspace/coverage/default/1.chip_sw_clkmgr_jitter.1269250329 Jun 28 08:08:28 PM PDT 24 Jun 28 08:12:03 PM PDT 24 2302403310 ps
T699 /workspace/coverage/default/17.chip_sw_alert_handler_lpg_sleep_mode_alerts.3774956376 Jun 28 08:27:47 PM PDT 24 Jun 28 08:33:56 PM PDT 24 3211732610 ps
T371 /workspace/coverage/default/59.chip_sw_all_escalation_resets.3455328432 Jun 28 08:30:30 PM PDT 24 Jun 28 08:42:24 PM PDT 24 5361723506 ps
T220 /workspace/coverage/default/1.chip_sw_keymgr_key_derivation_prod.516653676 Jun 28 08:05:05 PM PDT 24 Jun 28 08:34:11 PM PDT 24 9369808040 ps
T995 /workspace/coverage/default/1.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.1432012139 Jun 28 08:04:31 PM PDT 24 Jun 28 08:12:44 PM PDT 24 4866148348 ps
T215 /workspace/coverage/default/2.chip_sw_keymgr_sideload_aes.2005645443 Jun 28 08:22:53 PM PDT 24 Jun 28 09:08:07 PM PDT 24 13732426828 ps
T361 /workspace/coverage/default/0.chip_sw_flash_ctrl_ops_jitter_en_reduced_freq.782442407 Jun 28 08:02:33 PM PDT 24 Jun 28 08:16:16 PM PDT 24 5378398238 ps
T996 /workspace/coverage/default/2.chip_sw_uart_tx_rx_idx1.2896081577 Jun 28 08:15:08 PM PDT 24 Jun 28 08:28:11 PM PDT 24 4742889458 ps
T997 /workspace/coverage/default/2.chip_sw_aon_timer_wdog_lc_escalate.236331203 Jun 28 08:19:18 PM PDT 24 Jun 28 08:30:33 PM PDT 24 6075809552 ps
T724 /workspace/coverage/default/38.chip_sw_all_escalation_resets.297749080 Jun 28 08:29:31 PM PDT 24 Jun 28 08:38:29 PM PDT 24 4221638148 ps
T998 /workspace/coverage/default/1.rom_e2e_asm_init_dev.2810408482 Jun 28 08:17:04 PM PDT 24 Jun 28 09:37:34 PM PDT 24 15171841849 ps
T64 /workspace/coverage/default/3.chip_tap_straps_rma.1320197060 Jun 28 08:25:28 PM PDT 24 Jun 28 08:30:20 PM PDT 24 3217614158 ps
T999 /workspace/coverage/default/1.chip_sw_entropy_src_smoketest.1074184197 Jun 28 08:13:35 PM PDT 24 Jun 28 08:22:49 PM PDT 24 4091953510 ps
T1000 /workspace/coverage/default/1.chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq.3622579181 Jun 28 08:08:14 PM PDT 24 Jun 28 09:11:26 PM PDT 24 24519262183 ps
T223 /workspace/coverage/default/1.chip_sw_lc_walkthrough_rma.1468070143 Jun 28 08:06:55 PM PDT 24 Jun 28 09:38:38 PM PDT 24 48846406289 ps
T1001 /workspace/coverage/default/2.chip_sw_uart_smoketest.1432860077 Jun 28 08:25:22 PM PDT 24 Jun 28 08:28:48 PM PDT 24 2759922964 ps
T1002 /workspace/coverage/default/1.chip_sw_clkmgr_sleep_frequency.4242858699 Jun 28 08:09:16 PM PDT 24 Jun 28 08:19:07 PM PDT 24 4157533634 ps
T1003 /workspace/coverage/default/37.chip_sw_all_escalation_resets.4148647303 Jun 28 08:27:20 PM PDT 24 Jun 28 08:38:16 PM PDT 24 5715637320 ps
T1004 /workspace/coverage/default/2.chip_sw_otp_ctrl_lc_signals_test_unlocked0.1394424577 Jun 28 08:16:56 PM PDT 24 Jun 28 08:29:19 PM PDT 24 4314694096 ps
T1005 /workspace/coverage/default/1.chip_sw_uart_smoketest.2683482819 Jun 28 08:13:53 PM PDT 24 Jun 28 08:18:39 PM PDT 24 2985227792 ps
T1006 /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_bad_b_good_dev.3214132452 Jun 28 08:10:36 PM PDT 24 Jun 28 10:10:16 PM PDT 24 24081937190 ps
T279 /workspace/coverage/default/1.chip_sw_sram_ctrl_scrambled_access.702826290 Jun 28 08:03:55 PM PDT 24 Jun 28 08:15:54 PM PDT 24 5975278900 ps
T720 /workspace/coverage/default/23.chip_sw_alert_handler_lpg_sleep_mode_alerts.4089926510 Jun 28 08:28:25 PM PDT 24 Jun 28 08:35:09 PM PDT 24 4053952816 ps
T741 /workspace/coverage/default/72.chip_sw_alert_handler_lpg_sleep_mode_alerts.347028553 Jun 28 08:32:39 PM PDT 24 Jun 28 08:39:57 PM PDT 24 3775732792 ps
T1007 /workspace/coverage/default/1.chip_sw_csrng_smoketest.1385394887 Jun 28 08:13:33 PM PDT 24 Jun 28 08:17:31 PM PDT 24 3387844376 ps
T1008 /workspace/coverage/default/0.chip_sw_pwrmgr_b2b_sleep_reset_req.2127056698 Jun 28 08:00:55 PM PDT 24 Jun 28 08:40:55 PM PDT 24 27093458400 ps
T1009 /workspace/coverage/default/2.chip_sw_kmac_mode_kmac_jitter_en_reduced_freq.1045062605 Jun 28 08:23:01 PM PDT 24 Jun 28 08:27:56 PM PDT 24 3079707509 ps
T668 /workspace/coverage/default/2.chip_sw_power_idle_load.3647591953 Jun 28 08:23:11 PM PDT 24 Jun 28 08:35:27 PM PDT 24 4783797128 ps
T1010 /workspace/coverage/default/1.chip_sw_entropy_src_kat_test.1517423196 Jun 28 08:07:59 PM PDT 24 Jun 28 08:11:02 PM PDT 24 2669191252 ps
T35 /workspace/coverage/default/0.chip_sw_usbdev_config_host.1602901083 Jun 28 08:03:29 PM PDT 24 Jun 28 08:41:18 PM PDT 24 8232510190 ps
T510 /workspace/coverage/default/1.chip_sw_pwrmgr_all_reset_reqs.1145867487 Jun 28 08:05:48 PM PDT 24 Jun 28 08:30:00 PM PDT 24 8918154904 ps
T125 /workspace/coverage/default/0.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup.1880395165 Jun 28 08:01:21 PM PDT 24 Jun 28 08:10:47 PM PDT 24 5578799256 ps
T1011 /workspace/coverage/default/0.chip_sw_aes_enc.1522566787 Jun 28 08:06:56 PM PDT 24 Jun 28 08:10:46 PM PDT 24 2792556768 ps
T1012 /workspace/coverage/default/2.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.4034701349 Jun 28 08:19:14 PM PDT 24 Jun 28 08:27:55 PM PDT 24 4178170208 ps
T774 /workspace/coverage/default/25.chip_sw_all_escalation_resets.398339698 Jun 28 08:30:19 PM PDT 24 Jun 28 08:43:52 PM PDT 24 6209755208 ps
T1013 /workspace/coverage/default/0.rom_keymgr_functest.3293791740 Jun 28 08:01:38 PM PDT 24 Jun 28 08:10:33 PM PDT 24 4610807416 ps
T711 /workspace/coverage/default/8.chip_sw_all_escalation_resets.3111883022 Jun 28 08:25:50 PM PDT 24 Jun 28 08:38:26 PM PDT 24 4932034296 ps
T1014 /workspace/coverage/default/0.chip_sw_sleep_pwm_pulses.276698295 Jun 28 08:06:38 PM PDT 24 Jun 28 08:32:11 PM PDT 24 8132153596 ps
T1015 /workspace/coverage/default/0.chip_sw_keymgr_key_derivation_prod.204584471 Jun 28 07:59:39 PM PDT 24 Jun 28 08:27:31 PM PDT 24 9632315586 ps
T1016 /workspace/coverage/default/4.chip_sw_uart_tx_rx_idx2.543630675 Jun 28 08:23:27 PM PDT 24 Jun 28 08:34:24 PM PDT 24 4086870152 ps
T410 /workspace/coverage/default/0.chip_rv_dm_ndm_reset_req.524157693 Jun 28 08:01:48 PM PDT 24 Jun 28 08:09:16 PM PDT 24 4777200472 ps
T1017 /workspace/coverage/default/0.chip_sw_hmac_enc_idle.182900094 Jun 28 08:01:46 PM PDT 24 Jun 28 08:06:24 PM PDT 24 2646192692 ps
T406 /workspace/coverage/default/0.chip_sw_rom_ctrl_integrity_check.3023178445 Jun 28 08:01:13 PM PDT 24 Jun 28 08:13:34 PM PDT 24 8094833173 ps
T1018 /workspace/coverage/default/0.chip_sw_kmac_mode_kmac.1391788322 Jun 28 07:59:33 PM PDT 24 Jun 28 08:03:58 PM PDT 24 2941028180 ps
T352 /workspace/coverage/default/1.chip_sw_hmac_enc.1887740447 Jun 28 08:04:25 PM PDT 24 Jun 28 08:09:37 PM PDT 24 3759217774 ps
T1019 /workspace/coverage/default/80.chip_sw_all_escalation_resets.4091957846 Jun 28 08:32:58 PM PDT 24 Jun 28 08:43:53 PM PDT 24 5882180176 ps
T1020 /workspace/coverage/default/1.chip_sw_uart_tx_rx.2018149743 Jun 28 08:04:31 PM PDT 24 Jun 28 08:14:35 PM PDT 24 4302428696 ps
T137 /workspace/coverage/default/1.chip_sw_pwrmgr_full_aon_reset.2725011708 Jun 28 08:05:25 PM PDT 24 Jun 28 08:13:38 PM PDT 24 6251605128 ps
T1021 /workspace/coverage/default/1.chip_sw_flash_ctrl_access.1711456034 Jun 28 08:03:06 PM PDT 24 Jun 28 08:21:23 PM PDT 24 5700354250 ps
T1022 /workspace/coverage/default/3.chip_sw_uart_tx_rx_idx2.2468958235 Jun 28 08:24:18 PM PDT 24 Jun 28 08:33:58 PM PDT 24 4944495020 ps
T343 /workspace/coverage/default/1.chip_sw_i2c_host_tx_rx.4290590596 Jun 28 08:07:26 PM PDT 24 Jun 28 08:19:35 PM PDT 24 5066410904 ps
T98 /workspace/coverage/default/1.chip_sw_pwrmgr_deep_sleep_all_wake_ups.2577538039 Jun 28 08:10:22 PM PDT 24 Jun 28 08:40:37 PM PDT 24 24208780264 ps
T1023 /workspace/coverage/default/0.chip_sw_edn_kat.2205978889 Jun 28 08:04:06 PM PDT 24 Jun 28 08:16:39 PM PDT 24 3064015416 ps
T1024 /workspace/coverage/default/1.chip_sw_pwrmgr_deep_sleep_power_glitch_reset.62742484 Jun 28 08:05:51 PM PDT 24 Jun 28 08:14:37 PM PDT 24 7822675560 ps
T344 /workspace/coverage/default/2.chip_sw_pattgen_ios.3899833014 Jun 28 08:15:09 PM PDT 24 Jun 28 08:19:47 PM PDT 24 3488736356 ps
T696 /workspace/coverage/default/15.chip_sw_alert_handler_lpg_sleep_mode_alerts.2138922231 Jun 28 08:26:30 PM PDT 24 Jun 28 08:32:19 PM PDT 24 4030744152 ps
T1025 /workspace/coverage/default/0.rom_e2e_jtag_inject_dev.3293593424 Jun 28 08:07:37 PM PDT 24 Jun 28 08:55:08 PM PDT 24 32094346509 ps
T11 /workspace/coverage/default/0.chip_sw_sleep_pin_retention.120444937 Jun 28 08:03:36 PM PDT 24 Jun 28 08:07:11 PM PDT 24 3182338460 ps
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