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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
96.15 95.47 94.09 95.20 94.91 97.71 99.54


Total test records in report: 2885
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T330 /workspace/coverage/default/0.chip_sw_i2c_host_tx_rx_idx1.1851041722 Jun 28 08:04:30 PM PDT 24 Jun 28 08:16:44 PM PDT 24 4761805680 ps
T1026 /workspace/coverage/default/2.chip_sw_uart_tx_rx_alt_clk_freq.1271216471 Jun 28 08:15:54 PM PDT 24 Jun 28 08:28:01 PM PDT 24 4652906597 ps
T1027 /workspace/coverage/default/1.chip_sw_alert_handler_ping_ok.2340130395 Jun 28 08:09:14 PM PDT 24 Jun 28 08:37:11 PM PDT 24 7634237920 ps
T221 /workspace/coverage/default/0.chip_sw_keymgr_sideload_otbn.4095576664 Jun 28 08:01:31 PM PDT 24 Jun 28 09:19:39 PM PDT 24 18006867084 ps
T280 /workspace/coverage/default/1.chip_sw_sram_ctrl_scrambled_access_jitter_en.4177771753 Jun 28 08:11:08 PM PDT 24 Jun 28 08:24:12 PM PDT 24 5560901429 ps
T730 /workspace/coverage/default/24.chip_sw_alert_handler_lpg_sleep_mode_alerts.3062349413 Jun 28 08:27:02 PM PDT 24 Jun 28 08:34:59 PM PDT 24 3829330226 ps
T256 /workspace/coverage/default/0.chip_sw_alert_handler_lpg_sleep_mode_pings.2334562676 Jun 28 08:03:40 PM PDT 24 Jun 28 08:25:09 PM PDT 24 9795649832 ps
T1028 /workspace/coverage/default/0.chip_sw_clkmgr_off_otbn_trans.3515691201 Jun 28 08:04:29 PM PDT 24 Jun 28 08:12:21 PM PDT 24 4588955800 ps
T654 /workspace/coverage/default/1.chip_sw_pwrmgr_sleep_disabled.3025282771 Jun 28 08:05:02 PM PDT 24 Jun 28 08:08:24 PM PDT 24 2972050152 ps
T691 /workspace/coverage/default/60.chip_sw_all_escalation_resets.3596280018 Jun 28 08:30:41 PM PDT 24 Jun 28 08:43:09 PM PDT 24 5175476492 ps
T509 /workspace/coverage/default/1.chip_sw_rv_core_ibex_nmi_irq.1780604051 Jun 28 08:07:20 PM PDT 24 Jun 28 08:20:33 PM PDT 24 5345325572 ps
T757 /workspace/coverage/default/84.chip_sw_all_escalation_resets.150176406 Jun 28 08:33:06 PM PDT 24 Jun 28 08:43:22 PM PDT 24 5655768120 ps
T407 /workspace/coverage/default/2.chip_sw_kmac_app_rom.2554271190 Jun 28 08:20:17 PM PDT 24 Jun 28 08:23:08 PM PDT 24 2192444176 ps
T1029 /workspace/coverage/default/2.chip_sw_clkmgr_off_kmac_trans.330225880 Jun 28 08:25:43 PM PDT 24 Jun 28 08:34:13 PM PDT 24 4174144264 ps
T709 /workspace/coverage/default/63.chip_sw_all_escalation_resets.564578044 Jun 28 08:31:30 PM PDT 24 Jun 28 08:40:00 PM PDT 24 4788126000 ps
T708 /workspace/coverage/default/5.chip_sw_alert_handler_lpg_sleep_mode_alerts.846716196 Jun 28 08:24:26 PM PDT 24 Jun 28 08:32:21 PM PDT 24 3843523562 ps
T644 /workspace/coverage/default/2.chip_sw_lc_ctrl_rand_to_scrap.4040966718 Jun 28 08:16:58 PM PDT 24 Jun 28 08:19:40 PM PDT 24 3461864652 ps
T354 /workspace/coverage/default/1.chip_sw_uart_tx_rx_idx3.492013518 Jun 28 08:03:44 PM PDT 24 Jun 28 08:14:05 PM PDT 24 4642208292 ps
T1030 /workspace/coverage/default/0.rom_e2e_static_critical.2880818393 Jun 28 08:06:58 PM PDT 24 Jun 28 09:21:19 PM PDT 24 16894389916 ps
T1031 /workspace/coverage/default/2.chip_sw_example_concurrency.2394619652 Jun 28 08:13:41 PM PDT 24 Jun 28 08:18:51 PM PDT 24 3362141248 ps
T372 /workspace/coverage/default/76.chip_sw_alert_handler_lpg_sleep_mode_alerts.555241165 Jun 28 08:31:48 PM PDT 24 Jun 28 08:39:10 PM PDT 24 3368660270 ps
T224 /workspace/coverage/default/0.chip_sw_flash_init.2297411870 Jun 28 08:02:05 PM PDT 24 Jun 28 08:39:21 PM PDT 24 25416797200 ps
T742 /workspace/coverage/default/44.chip_sw_alert_handler_lpg_sleep_mode_alerts.2306817318 Jun 28 08:33:30 PM PDT 24 Jun 28 08:41:06 PM PDT 24 3426345910 ps
T155 /workspace/coverage/default/1.chip_sw_otp_ctrl_vendor_test_csr_access.2194944309 Jun 28 08:06:05 PM PDT 24 Jun 28 08:07:47 PM PDT 24 1883278217 ps
T1032 /workspace/coverage/default/1.chip_sw_lc_walkthrough_testunlocks.2457857448 Jun 28 08:07:54 PM PDT 24 Jun 28 08:43:48 PM PDT 24 31179584744 ps
T1033 /workspace/coverage/default/8.chip_sw_csrng_edn_concurrency.650064616 Jun 28 08:25:30 PM PDT 24 Jun 28 09:53:12 PM PDT 24 22180935488 ps
T1034 /workspace/coverage/default/2.chip_sw_pwrmgr_sleep_power_glitch_reset.4097966955 Jun 28 08:18:18 PM PDT 24 Jun 28 08:29:56 PM PDT 24 6102505800 ps
T702 /workspace/coverage/default/50.chip_sw_all_escalation_resets.4163658714 Jun 28 08:29:12 PM PDT 24 Jun 28 08:43:20 PM PDT 24 6444767194 ps
T1035 /workspace/coverage/default/21.chip_sw_all_escalation_resets.1901039950 Jun 28 08:26:56 PM PDT 24 Jun 28 08:41:41 PM PDT 24 6457063750 ps
T1036 /workspace/coverage/default/0.chip_sw_sram_ctrl_smoketest.4031599981 Jun 28 08:03:11 PM PDT 24 Jun 28 08:08:00 PM PDT 24 3471559076 ps
T1037 /workspace/coverage/default/2.rom_e2e_shutdown_exception_c.1976590687 Jun 28 08:28:14 PM PDT 24 Jun 28 09:31:09 PM PDT 24 15077692654 ps
T1038 /workspace/coverage/default/1.chip_sw_lc_ctrl_otp_hw_cfg0.406891445 Jun 28 08:04:31 PM PDT 24 Jun 28 08:10:20 PM PDT 24 3348158370 ps
T1039 /workspace/coverage/default/0.chip_sw_alert_handler_escalation.1112277523 Jun 28 08:06:56 PM PDT 24 Jun 28 08:15:19 PM PDT 24 4852470440 ps
T1040 /workspace/coverage/default/1.chip_tap_straps_rma.1167666931 Jun 28 08:10:05 PM PDT 24 Jun 28 08:15:32 PM PDT 24 4279632485 ps
T767 /workspace/coverage/default/2.chip_sw_alert_handler_lpg_sleep_mode_alerts.594159122 Jun 28 08:19:55 PM PDT 24 Jun 28 08:28:17 PM PDT 24 4025654598 ps
T226 /workspace/coverage/default/1.chip_sw_flash_init.524333441 Jun 28 08:05:09 PM PDT 24 Jun 28 08:47:34 PM PDT 24 21960306778 ps
T1041 /workspace/coverage/default/2.chip_sw_pwrmgr_deep_sleep_all_reset_reqs.2888080868 Jun 28 08:17:19 PM PDT 24 Jun 28 08:39:34 PM PDT 24 12184992880 ps
T198 /workspace/coverage/default/2.chip_sw_inject_scramble_seed.2893264023 Jun 28 08:16:57 PM PDT 24 Jun 28 11:40:24 PM PDT 24 64564722095 ps
T1042 /workspace/coverage/default/1.chip_sw_otbn_smoketest.2144235333 Jun 28 08:13:04 PM PDT 24 Jun 28 08:31:45 PM PDT 24 5710608480 ps
T317 /workspace/coverage/default/2.chip_plic_all_irqs_0.309948751 Jun 28 08:21:42 PM PDT 24 Jun 28 08:41:25 PM PDT 24 6331833396 ps
T1043 /workspace/coverage/default/1.chip_sw_hmac_enc_jitter_en_reduced_freq.4272369150 Jun 28 08:08:22 PM PDT 24 Jun 28 08:12:26 PM PDT 24 2991513935 ps
T1044 /workspace/coverage/default/2.chip_sw_pwrmgr_wdog_reset.1809561189 Jun 28 08:18:15 PM PDT 24 Jun 28 08:30:36 PM PDT 24 4993667882 ps
T1045 /workspace/coverage/default/1.chip_sw_pwrmgr_wdog_reset.688840469 Jun 28 08:06:05 PM PDT 24 Jun 28 08:17:01 PM PDT 24 5201504440 ps
T1046 /workspace/coverage/default/2.rom_e2e_keymgr_init_rom_ext_invalid_meas.2314557150 Jun 28 08:28:39 PM PDT 24 Jun 28 09:24:00 PM PDT 24 15069930464 ps
T23 /workspace/coverage/default/2.chip_sw_sleep_pin_mio_dio_val.4170653254 Jun 28 08:15:11 PM PDT 24 Jun 28 08:20:05 PM PDT 24 2694834150 ps
T697 /workspace/coverage/default/48.chip_sw_alert_handler_lpg_sleep_mode_alerts.541676990 Jun 28 08:29:55 PM PDT 24 Jun 28 08:36:59 PM PDT 24 3401005438 ps
T1047 /workspace/coverage/default/2.chip_sival_flash_info_access.1941682035 Jun 28 08:14:03 PM PDT 24 Jun 28 08:20:03 PM PDT 24 3074476704 ps
T778 /workspace/coverage/default/70.chip_sw_alert_handler_lpg_sleep_mode_alerts.2325823289 Jun 28 08:31:39 PM PDT 24 Jun 28 08:39:25 PM PDT 24 3988621898 ps
T1048 /workspace/coverage/default/2.chip_sw_kmac_mode_kmac_jitter_en.1973884533 Jun 28 08:22:34 PM PDT 24 Jun 28 08:28:18 PM PDT 24 2912661259 ps
T752 /workspace/coverage/default/45.chip_sw_alert_handler_lpg_sleep_mode_alerts.3505190621 Jun 28 08:29:08 PM PDT 24 Jun 28 08:37:30 PM PDT 24 4429825788 ps
T714 /workspace/coverage/default/18.chip_sw_alert_handler_lpg_sleep_mode_alerts.2361295527 Jun 28 08:29:29 PM PDT 24 Jun 28 08:35:28 PM PDT 24 3510669840 ps
T705 /workspace/coverage/default/47.chip_sw_alert_handler_lpg_sleep_mode_alerts.3986948721 Jun 28 08:29:11 PM PDT 24 Jun 28 08:36:53 PM PDT 24 3496356856 ps
T1049 /workspace/coverage/default/2.rom_e2e_keymgr_init_rom_ext_no_meas.2967043622 Jun 28 08:28:45 PM PDT 24 Jun 28 09:35:23 PM PDT 24 14424924200 ps
T322 /workspace/coverage/default/0.chip_plic_all_irqs_0.1743715798 Jun 28 08:01:59 PM PDT 24 Jun 28 08:20:31 PM PDT 24 6829940980 ps
T1050 /workspace/coverage/default/3.chip_sw_uart_tx_rx_alt_clk_freq.3108945756 Jun 28 08:27:10 PM PDT 24 Jun 28 08:35:50 PM PDT 24 3530375261 ps
T1051 /workspace/coverage/default/0.chip_sw_inject_scramble_seed.3658354876 Jun 28 08:01:55 PM PDT 24 Jun 28 11:41:14 PM PDT 24 64636283491 ps
T743 /workspace/coverage/default/60.chip_sw_alert_handler_lpg_sleep_mode_alerts.699895420 Jun 28 08:30:18 PM PDT 24 Jun 28 08:37:47 PM PDT 24 4069404730 ps
T1052 /workspace/coverage/default/0.chip_sw_uart_rand_baudrate.1001166756 Jun 28 08:04:10 PM PDT 24 Jun 28 08:13:01 PM PDT 24 3814906968 ps
T225 /workspace/coverage/default/2.chip_sw_lc_walkthrough_dev.1657478650 Jun 28 08:17:18 PM PDT 24 Jun 28 09:55:02 PM PDT 24 49820556912 ps
T712 /workspace/coverage/default/74.chip_sw_all_escalation_resets.3261953661 Jun 28 08:31:19 PM PDT 24 Jun 28 08:41:47 PM PDT 24 6136580200 ps
T768 /workspace/coverage/default/71.chip_sw_alert_handler_lpg_sleep_mode_alerts.4050278434 Jun 28 08:31:15 PM PDT 24 Jun 28 08:37:50 PM PDT 24 3299054772 ps
T173 /workspace/coverage/default/0.chip_sw_rv_core_ibex_icache_invalidate.200146263 Jun 28 08:00:38 PM PDT 24 Jun 28 08:04:58 PM PDT 24 2874939748 ps
T689 /workspace/coverage/default/22.chip_sw_all_escalation_resets.1655405011 Jun 28 08:27:21 PM PDT 24 Jun 28 08:38:43 PM PDT 24 4644526440 ps
T1053 /workspace/coverage/default/1.chip_sw_clkmgr_jitter_frequency.1731758646 Jun 28 08:09:46 PM PDT 24 Jun 28 08:16:24 PM PDT 24 3919182482 ps
T1054 /workspace/coverage/default/34.chip_sw_alert_handler_lpg_sleep_mode_alerts.1661982426 Jun 28 08:29:55 PM PDT 24 Jun 28 08:37:45 PM PDT 24 3946370342 ps
T301 /workspace/coverage/default/1.chip_sw_rv_core_ibex_icache_invalidate.1032432771 Jun 28 08:07:26 PM PDT 24 Jun 28 08:10:49 PM PDT 24 2780466433 ps
T1055 /workspace/coverage/default/1.chip_sw_uart_rand_baudrate.1409447676 Jun 28 08:06:26 PM PDT 24 Jun 28 08:14:17 PM PDT 24 3313821542 ps
T65 /workspace/coverage/default/3.chip_tap_straps_testunlock0.795328974 Jun 28 08:23:10 PM PDT 24 Jun 28 08:29:11 PM PDT 24 4350535533 ps
T405 /workspace/coverage/default/0.chip_sw_usb_ast_clk_calib.2196181059 Jun 28 08:02:51 PM PDT 24 Jun 28 08:08:57 PM PDT 24 3252651028 ps
T713 /workspace/coverage/default/13.chip_sw_all_escalation_resets.2038504591 Jun 28 08:29:05 PM PDT 24 Jun 28 08:38:46 PM PDT 24 4532104560 ps
T227 /workspace/coverage/default/1.chip_sw_lc_walkthrough_dev.545076711 Jun 28 08:04:57 PM PDT 24 Jun 28 09:33:16 PM PDT 24 48026838840 ps
T1056 /workspace/coverage/default/1.chip_sw_hmac_enc_idle.2816076405 Jun 28 08:05:44 PM PDT 24 Jun 28 08:10:22 PM PDT 24 3619087608 ps
T629 /workspace/coverage/default/2.chip_sw_edn_boot_mode.641143871 Jun 28 08:19:57 PM PDT 24 Jun 28 08:30:59 PM PDT 24 3276639800 ps
T685 /workspace/coverage/default/25.chip_sw_alert_handler_lpg_sleep_mode_alerts.1115404265 Jun 28 08:27:22 PM PDT 24 Jun 28 08:34:18 PM PDT 24 3621113600 ps
T632 /workspace/coverage/default/2.chip_sw_csrng_edn_concurrency_reduced_freq.1255756506 Jun 28 08:22:17 PM PDT 24 Jun 28 09:50:26 PM PDT 24 35643698919 ps
T1057 /workspace/coverage/default/0.chip_sw_otbn_mem_scramble.1188821123 Jun 28 08:06:40 PM PDT 24 Jun 28 08:14:08 PM PDT 24 3997212616 ps
T1058 /workspace/coverage/default/0.chip_sw_hmac_enc.3809053969 Jun 28 08:02:54 PM PDT 24 Jun 28 08:06:18 PM PDT 24 2346383900 ps
T1059 /workspace/coverage/default/2.chip_sw_flash_ctrl_write_clear.4280292126 Jun 28 08:22:01 PM PDT 24 Jun 28 08:29:14 PM PDT 24 3179494580 ps
T710 /workspace/coverage/default/91.chip_sw_all_escalation_resets.3400499240 Jun 28 08:34:43 PM PDT 24 Jun 28 08:46:26 PM PDT 24 5950360166 ps
T304 /workspace/coverage/default/2.chip_sw_sram_ctrl_execution_main.3445361442 Jun 28 08:27:04 PM PDT 24 Jun 28 08:44:01 PM PDT 24 7611137428 ps
T1060 /workspace/coverage/default/5.chip_sw_data_integrity_escalation.506527952 Jun 28 08:25:12 PM PDT 24 Jun 28 08:36:37 PM PDT 24 5873153920 ps
T323 /workspace/coverage/default/0.chip_sw_entropy_src_csrng.2900069483 Jun 28 08:01:32 PM PDT 24 Jun 28 08:28:35 PM PDT 24 6582782790 ps
T1061 /workspace/coverage/default/1.chip_sw_pwrmgr_main_power_glitch_reset.197473929 Jun 28 08:05:47 PM PDT 24 Jun 28 08:11:55 PM PDT 24 5333407165 ps
T1062 /workspace/coverage/default/97.chip_sw_all_escalation_resets.1394873472 Jun 28 08:32:47 PM PDT 24 Jun 28 08:42:58 PM PDT 24 4981945464 ps
T748 /workspace/coverage/default/81.chip_sw_alert_handler_lpg_sleep_mode_alerts.3347281779 Jun 28 08:33:26 PM PDT 24 Jun 28 08:40:13 PM PDT 24 3651644096 ps
T1063 /workspace/coverage/default/1.chip_sw_edn_kat.3728346734 Jun 28 08:03:48 PM PDT 24 Jun 28 08:13:48 PM PDT 24 2968535896 ps
T1064 /workspace/coverage/default/0.chip_sw_alert_handler_ping_ok.1636840415 Jun 28 08:07:34 PM PDT 24 Jun 28 08:36:24 PM PDT 24 7356771416 ps
T230 /workspace/coverage/default/0.chip_sw_lc_walkthrough_rma.2392977636 Jun 28 08:08:25 PM PDT 24 Jun 28 09:31:54 PM PDT 24 47573057630 ps
T1065 /workspace/coverage/default/3.chip_sw_data_integrity_escalation.2201022696 Jun 28 08:23:14 PM PDT 24 Jun 28 08:33:48 PM PDT 24 5605846614 ps
T1066 /workspace/coverage/default/2.chip_sw_keymgr_key_derivation_prod.2933872264 Jun 28 08:19:39 PM PDT 24 Jun 28 08:59:03 PM PDT 24 12305755080 ps
T1067 /workspace/coverage/default/2.chip_sw_flash_crash_alert.884849735 Jun 28 08:21:09 PM PDT 24 Jun 28 08:34:43 PM PDT 24 5731581008 ps
T1068 /workspace/coverage/default/0.chip_sw_flash_ctrl_access.2664545305 Jun 28 07:59:49 PM PDT 24 Jun 28 08:21:14 PM PDT 24 6186591048 ps
T645 /workspace/coverage/default/0.chip_sw_lc_ctrl_raw_to_scrap.1523444847 Jun 28 08:05:36 PM PDT 24 Jun 28 08:08:04 PM PDT 24 3507847059 ps
T1069 /workspace/coverage/default/0.chip_sw_i2c_host_tx_rx_idx2.2775587911 Jun 28 08:05:43 PM PDT 24 Jun 28 08:18:49 PM PDT 24 4615630860 ps
T1070 /workspace/coverage/default/0.rom_e2e_keymgr_init_rom_ext_meas.2892512350 Jun 28 08:07:43 PM PDT 24 Jun 28 09:22:12 PM PDT 24 14973820028 ps
T1071 /workspace/coverage/default/1.rom_e2e_asm_init_test_unlocked0.1707939598 Jun 28 08:14:20 PM PDT 24 Jun 28 09:08:24 PM PDT 24 11372782069 ps
T1072 /workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0.1276556241 Jun 28 08:07:23 PM PDT 24 Jun 28 08:16:58 PM PDT 24 5207655672 ps
T726 /workspace/coverage/default/17.chip_sw_all_escalation_resets.1465204225 Jun 28 08:25:54 PM PDT 24 Jun 28 08:36:06 PM PDT 24 5079717312 ps
T1073 /workspace/coverage/default/0.chip_sival_flash_info_access.2744544630 Jun 28 07:59:54 PM PDT 24 Jun 28 08:05:54 PM PDT 24 3944000278 ps
T229 /workspace/coverage/default/0.chip_sw_flash_init_reduced_freq.3529266978 Jun 28 08:08:08 PM PDT 24 Jun 28 08:45:07 PM PDT 24 18789759048 ps
T736 /workspace/coverage/default/72.chip_sw_all_escalation_resets.2390736733 Jun 28 08:30:32 PM PDT 24 Jun 28 08:40:27 PM PDT 24 4336818312 ps
T1074 /workspace/coverage/default/1.chip_tap_straps_dev.2064552803 Jun 28 08:05:37 PM PDT 24 Jun 28 08:08:52 PM PDT 24 3343116278 ps
T754 /workspace/coverage/default/20.chip_sw_all_escalation_resets.326538491 Jun 28 08:29:24 PM PDT 24 Jun 28 08:39:03 PM PDT 24 5563746480 ps
T1075 /workspace/coverage/default/0.chip_sw_otbn_randomness.3739476437 Jun 28 08:06:20 PM PDT 24 Jun 28 08:23:19 PM PDT 24 5953321628 ps
T1076 /workspace/coverage/default/0.chip_sw_otp_ctrl_dai_lock.456952078 Jun 28 08:00:32 PM PDT 24 Jun 28 09:43:29 PM PDT 24 27351793880 ps
T751 /workspace/coverage/default/83.chip_sw_alert_handler_lpg_sleep_mode_alerts.1823792242 Jun 28 08:31:50 PM PDT 24 Jun 28 08:38:23 PM PDT 24 3512823708 ps
T200 /workspace/coverage/default/0.chip_sw_sysrst_ctrl_in_irq.4049793181 Jun 28 08:05:52 PM PDT 24 Jun 28 08:16:13 PM PDT 24 5062948404 ps
T694 /workspace/coverage/default/39.chip_sw_alert_handler_lpg_sleep_mode_alerts.2072404056 Jun 28 08:28:26 PM PDT 24 Jun 28 08:35:01 PM PDT 24 4170878168 ps
T1077 /workspace/coverage/default/2.chip_sw_aon_timer_sleep_wdog_sleep_pause.4081848973 Jun 28 08:19:25 PM PDT 24 Jun 28 08:25:10 PM PDT 24 6807090096 ps
T1078 /workspace/coverage/default/82.chip_sw_alert_handler_lpg_sleep_mode_alerts.3150988386 Jun 28 08:31:59 PM PDT 24 Jun 28 08:39:36 PM PDT 24 3966798400 ps
T1079 /workspace/coverage/default/2.chip_sw_lc_ctrl_otp_hw_cfg0.689214050 Jun 28 08:17:00 PM PDT 24 Jun 28 08:23:29 PM PDT 24 2766812168 ps
T646 /workspace/coverage/default/2.rom_volatile_raw_unlock.3186616232 Jun 28 08:30:17 PM PDT 24 Jun 28 08:32:21 PM PDT 24 2677670533 ps
T1080 /workspace/coverage/default/0.chip_sw_otp_ctrl_smoketest.2199624831 Jun 28 08:04:17 PM PDT 24 Jun 28 08:10:22 PM PDT 24 3515949194 ps
T1081 /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0.1516286109 Jun 28 08:08:10 PM PDT 24 Jun 28 09:12:28 PM PDT 24 11069515792 ps
T1082 /workspace/coverage/default/2.chip_sw_example_rom.4256907733 Jun 28 08:15:59 PM PDT 24 Jun 28 08:18:07 PM PDT 24 2506421528 ps
T1083 /workspace/coverage/default/0.chip_sw_usbdev_vbus.4205145849 Jun 28 08:02:47 PM PDT 24 Jun 28 08:08:01 PM PDT 24 3261567792 ps
T190 /workspace/coverage/default/0.chip_sw_spi_device_pass_through_collision.1637225833 Jun 28 08:02:36 PM PDT 24 Jun 28 08:09:39 PM PDT 24 4441929608 ps
T251 /workspace/coverage/default/2.chip_sw_rv_timer_irq.3958123769 Jun 28 08:17:57 PM PDT 24 Jun 28 08:21:50 PM PDT 24 3140531572 ps
T765 /workspace/coverage/default/45.chip_sw_all_escalation_resets.2752085232 Jun 28 08:30:46 PM PDT 24 Jun 28 08:44:56 PM PDT 24 4989594680 ps
T728 /workspace/coverage/default/3.chip_sw_alert_handler_lpg_sleep_mode_alerts.2179561093 Jun 28 08:24:56 PM PDT 24 Jun 28 08:33:06 PM PDT 24 3996059064 ps
T734 /workspace/coverage/default/88.chip_sw_alert_handler_lpg_sleep_mode_alerts.3333100174 Jun 28 08:32:57 PM PDT 24 Jun 28 08:39:53 PM PDT 24 3042733640 ps
T1084 /workspace/coverage/default/1.chip_sw_sleep_pwm_pulses.2923329123 Jun 28 08:06:07 PM PDT 24 Jun 28 08:28:55 PM PDT 24 9497682620 ps
T142 /workspace/coverage/default/0.chip_sw_usbdev_dpi.3427462482 Jun 28 07:59:51 PM PDT 24 Jun 28 08:51:25 PM PDT 24 12377386242 ps
T324 /workspace/coverage/default/2.chip_sw_entropy_src_csrng.2143564779 Jun 28 08:20:24 PM PDT 24 Jun 28 08:39:10 PM PDT 24 6005631720 ps
T284 /workspace/coverage/default/2.chip_sw_rv_core_ibex_lockstep_glitch.1502160235 Jun 28 08:22:39 PM PDT 24 Jun 28 08:28:02 PM PDT 24 2504755608 ps
T285 /workspace/coverage/default/0.chip_sw_lc_ctrl_volatile_raw_unlock.1152846488 Jun 28 08:06:33 PM PDT 24 Jun 28 08:08:21 PM PDT 24 2579566376 ps
T286 /workspace/coverage/default/48.chip_sw_all_escalation_resets.338449172 Jun 28 08:30:21 PM PDT 24 Jun 28 08:38:30 PM PDT 24 4752160616 ps
T287 /workspace/coverage/default/1.rom_e2e_asm_init_rma.2677311317 Jun 28 08:20:34 PM PDT 24 Jun 28 09:18:05 PM PDT 24 14841134586 ps
T288 /workspace/coverage/default/58.chip_sw_alert_handler_lpg_sleep_mode_alerts.2118015060 Jun 28 08:33:39 PM PDT 24 Jun 28 08:38:52 PM PDT 24 3816270482 ps
T289 /workspace/coverage/default/1.rom_keymgr_functest.3836433993 Jun 28 08:11:47 PM PDT 24 Jun 28 08:23:16 PM PDT 24 5508137592 ps
T290 /workspace/coverage/default/29.chip_sw_all_escalation_resets.3488699745 Jun 28 08:28:05 PM PDT 24 Jun 28 08:38:52 PM PDT 24 5542890430 ps
T237 /workspace/coverage/default/1.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted.2891346163 Jun 28 08:06:42 PM PDT 24 Jun 28 08:16:46 PM PDT 24 3935313050 ps
T291 /workspace/coverage/default/28.chip_sw_all_escalation_resets.4031752012 Jun 28 08:28:24 PM PDT 24 Jun 28 08:38:00 PM PDT 24 4875431480 ps
T292 /workspace/coverage/default/2.chip_sw_aes_idle.166021938 Jun 28 08:18:57 PM PDT 24 Jun 28 08:23:36 PM PDT 24 2802655674 ps
T363 /workspace/coverage/default/1.chip_sw_flash_ctrl_ops_jitter_en_reduced_freq.985145175 Jun 28 08:08:07 PM PDT 24 Jun 28 08:18:42 PM PDT 24 4986437811 ps
T1085 /workspace/coverage/default/1.chip_sw_pwrmgr_sleep_power_glitch_reset.3043804508 Jun 28 08:05:45 PM PDT 24 Jun 28 08:15:27 PM PDT 24 5975780055 ps
T1086 /workspace/coverage/default/2.rom_keymgr_functest.2722908599 Jun 28 08:22:39 PM PDT 24 Jun 28 08:30:35 PM PDT 24 3994237164 ps
T772 /workspace/coverage/default/94.chip_sw_all_escalation_resets.3202881875 Jun 28 08:32:27 PM PDT 24 Jun 28 08:42:34 PM PDT 24 4480705534 ps
T1087 /workspace/coverage/default/1.chip_sw_example_concurrency.2734816008 Jun 28 08:03:14 PM PDT 24 Jun 28 08:08:13 PM PDT 24 2722569700 ps
T57 /workspace/coverage/default/1.chip_sw_alert_test.1502629883 Jun 28 08:11:20 PM PDT 24 Jun 28 08:16:55 PM PDT 24 3567648952 ps
T655 /workspace/coverage/default/1.chip_sw_plic_sw_irq.4199358550 Jun 28 08:06:57 PM PDT 24 Jun 28 08:12:59 PM PDT 24 3195934352 ps
T404 /workspace/coverage/default/2.chip_sw_pwrmgr_usbdev_smoketest.1163701333 Jun 28 08:24:16 PM PDT 24 Jun 28 08:31:54 PM PDT 24 5783258524 ps
T50 /workspace/coverage/default/0.chip_sw_spi_device_tpm.713163161 Jun 28 07:59:51 PM PDT 24 Jun 28 08:06:45 PM PDT 24 3250084878 ps
T740 /workspace/coverage/default/86.chip_sw_alert_handler_lpg_sleep_mode_alerts.304769779 Jun 28 08:31:39 PM PDT 24 Jun 28 08:39:46 PM PDT 24 4180922050 ps
T43 /workspace/coverage/default/2.chip_sw_spi_host_tx_rx.1004977820 Jun 28 08:15:25 PM PDT 24 Jun 28 08:19:30 PM PDT 24 2843749240 ps
T1088 /workspace/coverage/default/1.chip_sw_aes_enc_jitter_en.1606209688 Jun 28 08:11:18 PM PDT 24 Jun 28 08:15:42 PM PDT 24 2991917223 ps
T1089 /workspace/coverage/default/1.chip_sw_hmac_enc_jitter_en.4040715047 Jun 28 08:04:11 PM PDT 24 Jun 28 08:08:29 PM PDT 24 2592287717 ps
T1090 /workspace/coverage/default/2.chip_sw_csrng_edn_concurrency.3325152479 Jun 28 08:19:46 PM PDT 24 Jun 28 08:55:56 PM PDT 24 9234785314 ps
T1091 /workspace/coverage/default/1.chip_sw_power_idle_load.3497068881 Jun 28 08:09:07 PM PDT 24 Jun 28 08:23:48 PM PDT 24 5034752984 ps
T1092 /workspace/coverage/default/2.chip_sw_keymgr_key_derivation_jitter_en.3527759047 Jun 28 08:21:53 PM PDT 24 Jun 28 08:58:37 PM PDT 24 12792791100 ps
T1093 /workspace/coverage/default/0.chip_sw_kmac_mode_kmac_jitter_en_reduced_freq.2778184846 Jun 28 08:03:19 PM PDT 24 Jun 28 08:07:54 PM PDT 24 3089421764 ps
T165 /workspace/coverage/default/2.chip_sw_lc_ctrl_program_error.1559447736 Jun 28 08:27:15 PM PDT 24 Jun 28 08:35:04 PM PDT 24 4691168240 ps
T364 /workspace/coverage/default/2.chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up.3417391806 Jun 28 08:21:02 PM PDT 24 Jun 28 08:28:35 PM PDT 24 6461603550 ps
T244 /workspace/coverage/default/87.chip_sw_alert_handler_lpg_sleep_mode_alerts.4023450837 Jun 28 08:31:49 PM PDT 24 Jun 28 08:39:03 PM PDT 24 4158267716 ps
T293 /workspace/coverage/default/6.chip_sw_all_escalation_resets.3742127744 Jun 28 08:26:27 PM PDT 24 Jun 28 08:37:47 PM PDT 24 5635317832 ps
T294 /workspace/coverage/default/9.chip_sw_uart_rand_baudrate.3418855431 Jun 28 08:31:34 PM PDT 24 Jun 28 09:02:38 PM PDT 24 8464484500 ps
T295 /workspace/coverage/default/41.chip_sw_alert_handler_lpg_sleep_mode_alerts.2622466827 Jun 28 08:29:31 PM PDT 24 Jun 28 08:36:18 PM PDT 24 3728936126 ps
T296 /workspace/coverage/default/7.chip_sw_all_escalation_resets.1432711855 Jun 28 08:26:03 PM PDT 24 Jun 28 08:35:54 PM PDT 24 5946894184 ps
T297 /workspace/coverage/default/2.chip_sw_hmac_enc.2133219398 Jun 28 08:19:11 PM PDT 24 Jun 28 08:24:17 PM PDT 24 3805426232 ps
T298 /workspace/coverage/default/2.chip_sw_clkmgr_reset_frequency.34921753 Jun 28 08:22:25 PM PDT 24 Jun 28 08:32:16 PM PDT 24 3778114968 ps
T69 /workspace/coverage/default/0.chip_sw_usbdev_pullup.1483032765 Jun 28 08:03:07 PM PDT 24 Jun 28 08:08:11 PM PDT 24 3490214464 ps
T299 /workspace/coverage/default/70.chip_sw_all_escalation_resets.4171889169 Jun 28 08:33:58 PM PDT 24 Jun 28 08:43:48 PM PDT 24 5725695220 ps
T300 /workspace/coverage/default/85.chip_sw_all_escalation_resets.398219833 Jun 28 08:32:30 PM PDT 24 Jun 28 08:44:57 PM PDT 24 5368865932 ps
T1094 /workspace/coverage/default/3.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.2728214514 Jun 28 08:27:22 PM PDT 24 Jun 28 08:35:38 PM PDT 24 3817783946 ps
T1095 /workspace/coverage/default/0.chip_sw_example_concurrency.1771439987 Jun 28 08:04:19 PM PDT 24 Jun 28 08:09:17 PM PDT 24 3102644458 ps
T1096 /workspace/coverage/default/1.chip_sw_aon_timer_smoketest.3812802386 Jun 28 08:13:05 PM PDT 24 Jun 28 08:18:28 PM PDT 24 2980274130 ps
T759 /workspace/coverage/default/12.chip_sw_alert_handler_lpg_sleep_mode_alerts.2686768594 Jun 28 08:27:50 PM PDT 24 Jun 28 08:35:54 PM PDT 24 4141052840 ps
T58 /workspace/coverage/default/0.chip_sw_alert_test.2478829960 Jun 28 08:06:39 PM PDT 24 Jun 28 08:12:33 PM PDT 24 3339302740 ps
T1097 /workspace/coverage/default/2.chip_sw_rv_timer_smoketest.1954745879 Jun 28 08:23:38 PM PDT 24 Jun 28 08:27:50 PM PDT 24 2571617658 ps
T1098 /workspace/coverage/default/0.chip_sw_alert_handler_lpg_clkoff.3287028739 Jun 28 08:01:40 PM PDT 24 Jun 28 08:33:18 PM PDT 24 8182896776 ps
T245 /workspace/coverage/default/53.chip_sw_all_escalation_resets.1454916819 Jun 28 08:34:47 PM PDT 24 Jun 28 08:47:28 PM PDT 24 5808874216 ps
T1099 /workspace/coverage/default/4.chip_sw_uart_rand_baudrate.2877971973 Jun 28 08:25:55 PM PDT 24 Jun 28 09:08:38 PM PDT 24 13013605010 ps
T1100 /workspace/coverage/default/2.chip_sw_otbn_ecdsa_op_irq_jitter_en.3673713277 Jun 28 08:17:41 PM PDT 24 Jun 28 09:16:56 PM PDT 24 19122959313 ps
T1101 /workspace/coverage/default/1.chip_sw_hmac_multistream.2417180803 Jun 28 08:05:43 PM PDT 24 Jun 28 08:35:07 PM PDT 24 6956275324 ps
T1102 /workspace/coverage/default/1.chip_sw_pwrmgr_normal_sleep_all_reset_reqs.826568280 Jun 28 08:04:39 PM PDT 24 Jun 28 08:34:49 PM PDT 24 13090834952 ps
T1103 /workspace/coverage/default/5.chip_sw_csrng_edn_concurrency.2314003549 Jun 28 08:25:41 PM PDT 24 Jun 28 09:34:51 PM PDT 24 19781791628 ps
T1104 /workspace/coverage/default/0.chip_sw_pwrmgr_sleep_wake_5_bug.4139503208 Jun 28 08:01:32 PM PDT 24 Jun 28 08:10:43 PM PDT 24 5438460006 ps
T1105 /workspace/coverage/default/0.chip_sw_entropy_src_ast_rng_req.590170990 Jun 28 08:02:02 PM PDT 24 Jun 28 08:05:46 PM PDT 24 2502027156 ps
T755 /workspace/coverage/default/52.chip_sw_alert_handler_lpg_sleep_mode_alerts.3358243325 Jun 28 08:29:49 PM PDT 24 Jun 28 08:37:40 PM PDT 24 4612629954 ps
T1106 /workspace/coverage/default/1.rom_e2e_keymgr_init_rom_ext_invalid_meas.1137907664 Jun 28 08:16:27 PM PDT 24 Jun 28 09:19:54 PM PDT 24 14452350296 ps
T1107 /workspace/coverage/default/1.chip_sw_sram_ctrl_smoketest.3912682200 Jun 28 08:14:05 PM PDT 24 Jun 28 08:18:14 PM PDT 24 2499755532 ps
T749 /workspace/coverage/default/31.chip_sw_all_escalation_resets.1209692598 Jun 28 08:28:21 PM PDT 24 Jun 28 08:39:22 PM PDT 24 4761339960 ps
T1108 /workspace/coverage/default/0.chip_sw_example_manufacturer.4126010672 Jun 28 08:03:03 PM PDT 24 Jun 28 08:06:10 PM PDT 24 2574834312 ps
T1109 /workspace/coverage/default/39.chip_sw_all_escalation_resets.1764668031 Jun 28 08:30:30 PM PDT 24 Jun 28 08:41:43 PM PDT 24 6135045892 ps
T1110 /workspace/coverage/default/2.chip_sw_alert_handler_reverse_ping_in_deep_sleep.4010763651 Jun 28 08:19:51 PM PDT 24 Jun 29 12:05:27 AM PDT 24 254517261744 ps
T1111 /workspace/coverage/default/0.chip_sw_flash_ctrl_access_jitter_en_reduced_freq.3759374275 Jun 28 08:08:47 PM PDT 24 Jun 28 08:30:21 PM PDT 24 7025718842 ps
T1112 /workspace/coverage/default/2.chip_sw_lc_ctrl_volatile_raw_unlock.1335372959 Jun 28 08:16:35 PM PDT 24 Jun 28 08:18:46 PM PDT 24 2802136865 ps
T1113 /workspace/coverage/default/1.chip_sw_clkmgr_jitter_reduced_freq.1841426578 Jun 28 08:07:26 PM PDT 24 Jun 28 08:10:32 PM PDT 24 3031661011 ps
T1114 /workspace/coverage/default/2.chip_sw_flash_ctrl_access_jitter_en_reduced_freq.3893708173 Jun 28 08:27:48 PM PDT 24 Jun 28 08:44:56 PM PDT 24 6964498262 ps
T1115 /workspace/coverage/default/1.chip_sw_rstmgr_rst_cnsty_escalation.2295173795 Jun 28 08:06:10 PM PDT 24 Jun 28 08:18:15 PM PDT 24 6535230096 ps
T408 /workspace/coverage/default/0.chip_sw_kmac_app_rom.2034961208 Jun 28 08:03:50 PM PDT 24 Jun 28 08:08:29 PM PDT 24 2879707704 ps
T1116 /workspace/coverage/default/1.chip_sw_lc_ctrl_rand_to_scrap.2433866647 Jun 28 08:05:58 PM PDT 24 Jun 28 08:08:37 PM PDT 24 3414051436 ps
T665 /workspace/coverage/default/0.chip_sw_power_sleep_load.2959816063 Jun 28 08:02:42 PM PDT 24 Jun 28 08:08:47 PM PDT 24 4112952112 ps
T1117 /workspace/coverage/default/6.chip_sw_uart_rand_baudrate.2483292999 Jun 28 08:26:08 PM PDT 24 Jun 28 08:35:56 PM PDT 24 3960513534 ps
T305 /workspace/coverage/default/0.chip_sw_sram_ctrl_execution_main.3766784375 Jun 28 08:04:13 PM PDT 24 Jun 28 08:20:15 PM PDT 24 7857805138 ps
T1118 /workspace/coverage/default/1.chip_sw_alert_handler_ping_timeout.3486845339 Jun 28 08:11:15 PM PDT 24 Jun 28 08:15:26 PM PDT 24 2516015352 ps
T1119 /workspace/coverage/default/1.chip_sw_gpio_smoketest.1860528825 Jun 28 08:13:30 PM PDT 24 Jun 28 08:18:10 PM PDT 24 3242605169 ps
T201 /workspace/coverage/default/1.chip_sw_sysrst_ctrl_in_irq.1455924996 Jun 28 08:10:39 PM PDT 24 Jun 28 08:20:26 PM PDT 24 5058621040 ps
T231 /workspace/coverage/default/2.chip_sw_lc_walkthrough_rma.4240400539 Jun 28 08:16:37 PM PDT 24 Jun 28 09:47:06 PM PDT 24 49013041450 ps
T1120 /workspace/coverage/default/2.chip_sw_otp_ctrl_lc_signals_dev.3423896417 Jun 28 08:15:39 PM PDT 24 Jun 28 08:38:26 PM PDT 24 9162928422 ps
T1121 /workspace/coverage/default/0.chip_tap_straps_prod.1376750408 Jun 28 08:01:00 PM PDT 24 Jun 28 08:03:58 PM PDT 24 3336820939 ps
T1122 /workspace/coverage/default/43.chip_sw_all_escalation_resets.498260857 Jun 28 08:29:10 PM PDT 24 Jun 28 08:43:11 PM PDT 24 5728074372 ps
T1123 /workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_fast_rma.2932832925 Jun 28 08:00:23 PM PDT 24 Jun 28 08:11:16 PM PDT 24 4628126510 ps
T1124 /workspace/coverage/default/2.chip_sw_aes_masking_off.4260577622 Jun 28 08:20:00 PM PDT 24 Jun 28 08:26:56 PM PDT 24 3192055960 ps
T1125 /workspace/coverage/default/0.rom_e2e_keymgr_init_rom_ext_no_meas.862623097 Jun 28 08:07:39 PM PDT 24 Jun 28 09:13:28 PM PDT 24 14876231952 ps
T1126 /workspace/coverage/default/1.chip_sw_otbn_ecdsa_op_irq_jitter_en.4227309004 Jun 28 08:07:08 PM PDT 24 Jun 28 09:13:50 PM PDT 24 18766594940 ps
T191 /workspace/coverage/default/1.chip_sw_spi_device_pass_through_collision.885385558 Jun 28 08:05:06 PM PDT 24 Jun 28 08:14:52 PM PDT 24 4836899595 ps
T409 /workspace/coverage/default/2.chip_sw_rom_ctrl_integrity_check.2210646420 Jun 28 08:19:57 PM PDT 24 Jun 28 08:29:49 PM PDT 24 9982898637 ps
T345 /workspace/coverage/default/1.chip_sw_pattgen_ios.2440982089 Jun 28 08:06:28 PM PDT 24 Jun 28 08:11:22 PM PDT 24 2474135996 ps
T1127 /workspace/coverage/default/1.chip_sw_all_escalation_resets.2155473266 Jun 28 08:05:56 PM PDT 24 Jun 28 08:18:24 PM PDT 24 4341237198 ps
T222 /workspace/coverage/default/2.chip_sw_keymgr_sideload_otbn.2694216550 Jun 28 08:21:09 PM PDT 24 Jun 28 09:31:57 PM PDT 24 15281705856 ps
T1128 /workspace/coverage/default/2.chip_sw_alert_handler_ping_ok.1034616877 Jun 28 08:19:43 PM PDT 24 Jun 28 08:42:56 PM PDT 24 7749623580 ps
T760 /workspace/coverage/default/11.chip_sw_all_escalation_resets.4200113804 Jun 28 08:31:47 PM PDT 24 Jun 28 08:42:36 PM PDT 24 5427330946 ps
T1129 /workspace/coverage/default/0.chip_sw_edn_auto_mode.650019590 Jun 28 08:05:53 PM PDT 24 Jun 28 08:17:04 PM PDT 24 3709664240 ps
T1130 /workspace/coverage/default/4.chip_sw_uart_tx_rx_alt_clk_freq.834938706 Jun 28 08:23:35 PM PDT 24 Jun 28 08:35:49 PM PDT 24 4238599652 ps
T1131 /workspace/coverage/default/2.chip_sw_flash_rma_unlocked.3051481120 Jun 28 08:19:27 PM PDT 24 Jun 28 09:39:38 PM PDT 24 43792511696 ps
T302 /workspace/coverage/default/0.chip_sw_rv_core_ibex_address_translation.1641065444 Jun 28 08:02:47 PM PDT 24 Jun 28 08:07:38 PM PDT 24 3490917966 ps
T192 /workspace/coverage/default/2.chip_sw_spi_device_pass_through_collision.52990052 Jun 28 08:16:36 PM PDT 24 Jun 28 08:26:52 PM PDT 24 4882125918 ps
T1132 /workspace/coverage/default/0.chip_sw_otp_ctrl_lc_signals_test_unlocked0.1145914270 Jun 28 08:06:38 PM PDT 24 Jun 28 08:19:00 PM PDT 24 4808720240 ps
T614 /workspace/coverage/default/0.chip_sw_sram_ctrl_scrambled_access.2157747241 Jun 28 08:01:50 PM PDT 24 Jun 28 08:12:04 PM PDT 24 4192831922 ps
T1133 /workspace/coverage/default/0.chip_sw_sysrst_ctrl_ec_rst_l.2220509508 Jun 28 08:05:59 PM PDT 24 Jun 28 09:03:04 PM PDT 24 20851509800 ps
T1134 /workspace/coverage/default/1.chip_sw_keymgr_key_derivation_jitter_en_reduced_freq.1971700503 Jun 28 08:11:16 PM PDT 24 Jun 28 08:48:03 PM PDT 24 11785890413 ps
T1135 /workspace/coverage/default/4.chip_sw_uart_tx_rx_idx3.3479411425 Jun 28 08:24:59 PM PDT 24 Jun 28 08:35:33 PM PDT 24 4674505716 ps
T1136 /workspace/coverage/default/3.chip_sw_uart_tx_rx_idx1.1718923934 Jun 28 08:22:57 PM PDT 24 Jun 28 08:34:28 PM PDT 24 4454548136 ps
T1137 /workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_lc.3601205426 Jun 28 08:21:01 PM PDT 24 Jun 28 08:28:16 PM PDT 24 6114132224 ps
T733 /workspace/coverage/default/54.chip_sw_alert_handler_lpg_sleep_mode_alerts.3290059718 Jun 28 08:28:28 PM PDT 24 Jun 28 08:33:54 PM PDT 24 3015129228 ps
T1138 /workspace/coverage/default/0.chip_sw_uart_smoketest.297442420 Jun 28 08:03:43 PM PDT 24 Jun 28 08:07:38 PM PDT 24 3343277000 ps
T9 /workspace/coverage/default/2.chip_rv_dm_ndm_reset_req.1433531735 Jun 28 08:20:34 PM PDT 24 Jun 28 08:26:29 PM PDT 24 3650709370 ps
T686 /workspace/coverage/default/11.chip_sw_alert_handler_lpg_sleep_mode_alerts.1429744312 Jun 28 08:26:36 PM PDT 24 Jun 28 08:33:26 PM PDT 24 3141967946 ps
T1139 /workspace/coverage/default/7.chip_sw_uart_rand_baudrate.1583174532 Jun 28 08:26:00 PM PDT 24 Jun 28 08:36:49 PM PDT 24 3796872760 ps
T1140 /workspace/coverage/default/2.rom_e2e_asm_init_dev.3274739581 Jun 28 08:26:53 PM PDT 24 Jun 28 09:20:12 PM PDT 24 15726653279 ps
T202 /workspace/coverage/default/0.chip_sw_sysrst_ctrl_reset.2895257351 Jun 28 08:06:30 PM PDT 24 Jun 28 08:38:40 PM PDT 24 24810342992 ps
T1141 /workspace/coverage/default/4.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.191675543 Jun 28 08:24:43 PM PDT 24 Jun 28 08:51:44 PM PDT 24 13285472283 ps
T1142 /workspace/coverage/default/2.chip_sw_clkmgr_smoketest.2353571014 Jun 28 08:25:09 PM PDT 24 Jun 28 08:28:44 PM PDT 24 2772871792 ps
T1143 /workspace/coverage/default/1.chip_sw_pwrmgr_normal_sleep_por_reset.3299152864 Jun 28 08:06:06 PM PDT 24 Jun 28 08:13:45 PM PDT 24 6190824840 ps
T1144 /workspace/coverage/default/1.chip_sw_pwrmgr_b2b_sleep_reset_req.844585343 Jun 28 08:11:18 PM PDT 24 Jun 28 08:53:22 PM PDT 24 27034316395 ps
T1145 /workspace/coverage/default/0.chip_sw_aes_entropy.973671789 Jun 28 08:04:09 PM PDT 24 Jun 28 08:07:16 PM PDT 24 2358427070 ps
T1146 /workspace/coverage/default/2.chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq.886208913 Jun 28 08:21:43 PM PDT 24 Jun 28 08:34:29 PM PDT 24 4466677277 ps
T1147 /workspace/coverage/default/0.chip_sw_csrng_lc_hw_debug_en_test.3426914617 Jun 28 08:05:53 PM PDT 24 Jun 28 08:17:24 PM PDT 24 5669666299 ps
T1148 /workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_slow_rma.363009092 Jun 28 08:02:13 PM PDT 24 Jun 28 08:10:50 PM PDT 24 4810867634 ps
T735 /workspace/coverage/default/1.chip_sw_alert_handler_lpg_sleep_mode_alerts.1191183310 Jun 28 08:08:40 PM PDT 24 Jun 28 08:15:02 PM PDT 24 3191338410 ps
T1149 /workspace/coverage/default/2.chip_tap_straps_prod.685789304 Jun 28 08:20:29 PM PDT 24 Jun 28 08:23:21 PM PDT 24 3101486627 ps
T1150 /workspace/coverage/default/3.chip_tap_straps_dev.1001356656 Jun 28 08:23:12 PM PDT 24 Jun 28 08:54:58 PM PDT 24 17993730702 ps
T1151 /workspace/coverage/default/12.chip_sw_lc_ctrl_transition.763967115 Jun 28 08:28:14 PM PDT 24 Jun 28 08:35:43 PM PDT 24 6070756850 ps
T1152 /workspace/coverage/default/1.chip_sw_flash_ctrl_mem_protection.332510918 Jun 28 08:11:44 PM PDT 24 Jun 28 08:32:23 PM PDT 24 5647285736 ps
T1153 /workspace/coverage/default/2.chip_sw_rv_core_ibex_rnd.251209253 Jun 28 08:18:12 PM PDT 24 Jun 28 08:34:33 PM PDT 24 6104921100 ps
T1154 /workspace/coverage/default/0.chip_sw_lc_ctrl_transition.3975100404 Jun 28 08:04:15 PM PDT 24 Jun 28 08:22:26 PM PDT 24 12728269549 ps
T1155 /workspace/coverage/default/84.chip_sw_alert_handler_lpg_sleep_mode_alerts.3959215233 Jun 28 08:31:58 PM PDT 24 Jun 28 08:38:47 PM PDT 24 4070217256 ps
T1156 /workspace/coverage/default/0.chip_sw_uart_tx_rx_idx1.2288454334 Jun 28 07:59:03 PM PDT 24 Jun 28 08:08:36 PM PDT 24 4149168040 ps
T320 /workspace/coverage/default/1.chip_plic_all_irqs_20.2668276323 Jun 28 08:09:17 PM PDT 24 Jun 28 08:22:29 PM PDT 24 4307371384 ps
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