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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
96.15 95.47 94.09 95.20 94.91 97.71 99.54


Total test records in report: 2885
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T1157 /workspace/coverage/default/0.rom_e2e_shutdown_exception_c.2892519762 Jun 28 08:07:43 PM PDT 24 Jun 28 09:04:02 PM PDT 24 14704983373 ps
T1158 /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0.3984446509 Jun 28 08:09:06 PM PDT 24 Jun 28 09:37:07 PM PDT 24 17870432082 ps
T228 /workspace/coverage/default/0.chip_sw_lc_walkthrough_prod.2525705131 Jun 28 08:04:06 PM PDT 24 Jun 28 09:41:29 PM PDT 24 49100050200 ps
T1159 /workspace/coverage/default/0.chip_sw_pwrmgr_usbdev_smoketest.3900837231 Jun 28 08:04:22 PM PDT 24 Jun 28 08:11:28 PM PDT 24 5359311628 ps
T203 /workspace/coverage/default/1.chip_sw_sysrst_ctrl_outputs.157285449 Jun 28 08:07:33 PM PDT 24 Jun 28 08:14:42 PM PDT 24 4318759240 ps
T204 /workspace/coverage/default/2.chip_sw_sysrst_ctrl_outputs.1006672580 Jun 28 08:18:45 PM PDT 24 Jun 28 08:25:57 PM PDT 24 3852076800 ps
T762 /workspace/coverage/default/46.chip_sw_all_escalation_resets.96419946 Jun 28 08:33:52 PM PDT 24 Jun 28 08:43:02 PM PDT 24 4714335478 ps
T1160 /workspace/coverage/default/0.chip_sw_pwrmgr_normal_sleep_por_reset.3188151807 Jun 28 08:04:15 PM PDT 24 Jun 28 08:14:00 PM PDT 24 5311515787 ps
T216 /workspace/coverage/default/0.chip_sw_keymgr_sideload_aes.2200109995 Jun 28 08:01:41 PM PDT 24 Jun 28 08:47:43 PM PDT 24 11715435576 ps
T1161 /workspace/coverage/default/0.chip_sw_clkmgr_off_hmac_trans.681065740 Jun 28 08:00:54 PM PDT 24 Jun 28 08:09:08 PM PDT 24 5438225050 ps
T1162 /workspace/coverage/default/1.chip_sw_pwrmgr_sleep_wake_5_bug.3076080162 Jun 28 08:08:55 PM PDT 24 Jun 28 08:15:55 PM PDT 24 5687411320 ps
T1163 /workspace/coverage/default/2.chip_sw_clkmgr_off_otbn_trans.666721171 Jun 28 08:26:31 PM PDT 24 Jun 28 08:33:26 PM PDT 24 5055062032 ps
T217 /workspace/coverage/default/1.chip_sw_keymgr_sideload_aes.648984308 Jun 28 08:05:35 PM PDT 24 Jun 28 08:37:51 PM PDT 24 7815419660 ps
T12 /workspace/coverage/default/1.chip_sw_sleep_pin_retention.1534342110 Jun 28 08:03:38 PM PDT 24 Jun 28 08:09:18 PM PDT 24 4418173472 ps
T1164 /workspace/coverage/default/0.chip_sw_keymgr_key_derivation_jitter_en_reduced_freq.3137696747 Jun 28 08:09:46 PM PDT 24 Jun 28 08:36:28 PM PDT 24 9011652173 ps
T750 /workspace/coverage/default/21.chip_sw_alert_handler_lpg_sleep_mode_alerts.1593346971 Jun 28 08:32:27 PM PDT 24 Jun 28 08:41:59 PM PDT 24 4312717816 ps
T159 /workspace/coverage/default/0.chip_sw_otp_ctrl_escalation.2026025443 Jun 28 08:03:45 PM PDT 24 Jun 28 08:13:31 PM PDT 24 5079776110 ps
T1165 /workspace/coverage/default/0.chip_sw_keymgr_key_derivation_jitter_en.943304939 Jun 28 08:03:44 PM PDT 24 Jun 28 08:24:54 PM PDT 24 6744395199 ps
T1166 /workspace/coverage/default/0.chip_sw_keymgr_key_derivation.3141469472 Jun 28 08:00:49 PM PDT 24 Jun 28 08:17:45 PM PDT 24 6501941712 ps
T1167 /workspace/coverage/default/2.chip_sw_alert_handler_ping_timeout.86793016 Jun 28 08:21:45 PM PDT 24 Jun 28 08:28:50 PM PDT 24 4565262600 ps
T1168 /workspace/coverage/default/16.chip_sw_uart_rand_baudrate.3927461476 Jun 28 08:28:07 PM PDT 24 Jun 28 08:50:43 PM PDT 24 8148825070 ps
T334 /workspace/coverage/default/2.chip_sw_pwrmgr_lowpower_cancel.1358162220 Jun 28 08:21:45 PM PDT 24 Jun 28 08:27:40 PM PDT 24 3841262866 ps
T1169 /workspace/coverage/default/14.chip_sw_all_escalation_resets.720798641 Jun 28 08:27:35 PM PDT 24 Jun 28 08:40:08 PM PDT 24 5508245240 ps
T1170 /workspace/coverage/default/2.chip_sw_ast_clk_outputs.843409188 Jun 28 08:21:48 PM PDT 24 Jun 28 08:38:32 PM PDT 24 7992892410 ps
T160 /workspace/coverage/default/83.chip_sw_all_escalation_resets.3825610711 Jun 28 08:33:55 PM PDT 24 Jun 28 08:46:20 PM PDT 24 4772930484 ps
T346 /workspace/coverage/default/0.chip_sw_pattgen_ios.1360372996 Jun 28 07:58:59 PM PDT 24 Jun 28 08:04:55 PM PDT 24 2679117430 ps
T1171 /workspace/coverage/default/2.chip_sw_flash_ctrl_clock_freqs.3003271840 Jun 28 08:17:57 PM PDT 24 Jun 28 08:41:53 PM PDT 24 5493739905 ps
T1172 /workspace/coverage/default/0.chip_sw_flash_ctrl_mem_protection.2075180865 Jun 28 08:03:27 PM PDT 24 Jun 28 08:21:44 PM PDT 24 5572249292 ps
T1173 /workspace/coverage/default/0.chip_sw_aes_smoketest.3396265106 Jun 28 08:01:40 PM PDT 24 Jun 28 08:08:27 PM PDT 24 3429415172 ps
T1174 /workspace/coverage/default/2.chip_sw_uart_rand_baudrate.2889356586 Jun 28 08:14:48 PM PDT 24 Jun 28 09:01:56 PM PDT 24 12942532380 ps
T146 /workspace/coverage/default/2.chip_sw_exit_test_unlocked_bootstrap.3390114577 Jun 28 08:18:29 PM PDT 24 Jun 28 11:17:02 PM PDT 24 58440510250 ps
T1175 /workspace/coverage/default/0.chip_sw_clkmgr_jitter_reduced_freq.4139550535 Jun 28 08:02:23 PM PDT 24 Jun 28 08:05:12 PM PDT 24 3140141683 ps
T1176 /workspace/coverage/default/3.chip_sw_lc_ctrl_transition.2773421521 Jun 28 08:25:16 PM PDT 24 Jun 28 08:33:36 PM PDT 24 6813570068 ps
T161 /workspace/coverage/default/66.chip_sw_all_escalation_resets.2287565228 Jun 28 08:30:45 PM PDT 24 Jun 28 08:40:38 PM PDT 24 4579955828 ps
T1177 /workspace/coverage/default/0.chip_sw_pwrmgr_smoketest.3132906675 Jun 28 08:03:40 PM PDT 24 Jun 28 08:10:16 PM PDT 24 4874420398 ps
T1178 /workspace/coverage/default/0.chip_sw_flash_ctrl_clock_freqs.2557700001 Jun 28 08:01:12 PM PDT 24 Jun 28 08:21:22 PM PDT 24 5770807127 ps
T1179 /workspace/coverage/default/1.rom_volatile_raw_unlock.1560028074 Jun 28 08:12:13 PM PDT 24 Jun 28 08:14:16 PM PDT 24 2331234402 ps
T1180 /workspace/coverage/default/2.chip_sw_entropy_src_smoketest.995426026 Jun 28 08:30:41 PM PDT 24 Jun 28 08:38:15 PM PDT 24 3351597336 ps
T1181 /workspace/coverage/default/2.chip_sw_aes_enc_jitter_en.4043516843 Jun 28 08:19:49 PM PDT 24 Jun 28 08:24:53 PM PDT 24 2901060684 ps
T1182 /workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0.2158690105 Jun 28 08:21:57 PM PDT 24 Jun 28 08:36:13 PM PDT 24 4780511384 ps
T739 /workspace/coverage/default/5.chip_sw_all_escalation_resets.2637200047 Jun 28 08:24:44 PM PDT 24 Jun 28 08:35:30 PM PDT 24 5042032280 ps
T84 /workspace/coverage/default/42.chip_sw_all_escalation_resets.1352936444 Jun 28 08:28:35 PM PDT 24 Jun 28 08:44:33 PM PDT 24 5088712076 ps
T87 /workspace/coverage/default/0.chip_sw_sysrst_ctrl_outputs.3939270584 Jun 28 08:06:55 PM PDT 24 Jun 28 08:12:47 PM PDT 24 3289323588 ps
T88 /workspace/coverage/default/2.chip_sw_alert_handler_lpg_clkoff.2705578950 Jun 28 08:18:09 PM PDT 24 Jun 28 08:39:33 PM PDT 24 6185556188 ps
T89 /workspace/coverage/default/1.chip_sw_pwrmgr_random_sleep_all_reset_reqs.1828750099 Jun 28 08:07:37 PM PDT 24 Jun 28 08:52:31 PM PDT 24 24233418943 ps
T90 /workspace/coverage/default/2.chip_sw_keymgr_key_derivation_jitter_en_reduced_freq.1940971253 Jun 28 08:22:38 PM PDT 24 Jun 28 08:50:26 PM PDT 24 9849403270 ps
T91 /workspace/coverage/default/2.chip_sw_pwrmgr_random_sleep_all_wake_ups.106522242 Jun 28 08:21:59 PM PDT 24 Jun 28 08:53:48 PM PDT 24 23745749688 ps
T92 /workspace/coverage/default/0.chip_sw_hmac_enc_jitter_en.3057480979 Jun 28 08:00:32 PM PDT 24 Jun 28 08:04:23 PM PDT 24 2642267132 ps
T93 /workspace/coverage/default/2.chip_sw_edn_auto_mode.3020061759 Jun 28 08:19:51 PM PDT 24 Jun 28 08:35:55 PM PDT 24 4465855354 ps
T94 /workspace/coverage/default/2.chip_tap_straps_dev.3007430613 Jun 28 08:21:30 PM PDT 24 Jun 28 08:41:36 PM PDT 24 10503271211 ps
T95 /workspace/coverage/default/0.chip_sw_rv_timer_irq.1974005878 Jun 28 08:08:29 PM PDT 24 Jun 28 08:13:00 PM PDT 24 3407791186 ps
T1183 /workspace/coverage/default/0.chip_sw_hmac_enc_jitter_en_reduced_freq.2317289295 Jun 28 08:09:33 PM PDT 24 Jun 28 08:13:50 PM PDT 24 3488972801 ps
T1184 /workspace/coverage/default/0.chip_sw_aes_enc_jitter_en.309904953 Jun 28 08:01:42 PM PDT 24 Jun 28 08:05:57 PM PDT 24 3411634049 ps
T193 /workspace/coverage/default/2.chip_sw_spi_device_pass_through.539460755 Jun 28 08:16:19 PM PDT 24 Jun 28 08:32:48 PM PDT 24 7619185503 ps
T157 /workspace/coverage/default/2.chip_sw_otp_ctrl_vendor_test_csr_access.1097476014 Jun 28 08:20:53 PM PDT 24 Jun 28 08:22:42 PM PDT 24 2004322481 ps
T1185 /workspace/coverage/default/2.chip_sw_clkmgr_sleep_frequency.620421844 Jun 28 08:26:41 PM PDT 24 Jun 28 08:40:00 PM PDT 24 4729105524 ps
T1186 /workspace/coverage/default/0.chip_sw_pwrmgr_sleep_disabled.2584781784 Jun 28 08:05:30 PM PDT 24 Jun 28 08:09:29 PM PDT 24 3109281752 ps
T14 /workspace/coverage/default/1.chip_sw_sleep_pin_wake.1291627885 Jun 28 08:05:14 PM PDT 24 Jun 28 08:09:41 PM PDT 24 3097303992 ps
T1187 /workspace/coverage/default/2.rom_e2e_smoke.1605099745 Jun 28 08:26:08 PM PDT 24 Jun 28 09:43:41 PM PDT 24 14519760328 ps
T1188 /workspace/coverage/default/77.chip_sw_all_escalation_resets.3875740785 Jun 28 08:37:10 PM PDT 24 Jun 28 08:46:10 PM PDT 24 4457237052 ps
T47 /workspace/coverage/default/0.chip_sw_sysrst_ctrl_ulp_z3_wakeup.2180243083 Jun 28 08:08:07 PM PDT 24 Jun 28 08:15:07 PM PDT 24 6142919128 ps
T16 /workspace/coverage/default/2.chip_sw_sleep_pin_wake.3052433278 Jun 28 08:17:01 PM PDT 24 Jun 28 08:23:06 PM PDT 24 3078401744 ps
T1189 /workspace/coverage/default/2.chip_sw_pwrmgr_deep_sleep_por_reset.3207805687 Jun 28 08:17:25 PM PDT 24 Jun 28 08:30:27 PM PDT 24 8860922376 ps
T763 /workspace/coverage/default/55.chip_sw_alert_handler_lpg_sleep_mode_alerts.429565799 Jun 28 08:29:04 PM PDT 24 Jun 28 08:35:55 PM PDT 24 3674021796 ps
T1190 /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_bad_rma.1906567768 Jun 28 08:08:38 PM PDT 24 Jun 28 09:15:09 PM PDT 24 14714948120 ps
T1191 /workspace/coverage/default/1.chip_sw_otp_ctrl_lc_signals_rma.2716320890 Jun 28 08:05:43 PM PDT 24 Jun 28 08:27:04 PM PDT 24 7649530786 ps
T1192 /workspace/coverage/default/2.chip_sw_plic_sw_irq.3940603942 Jun 28 08:20:13 PM PDT 24 Jun 28 08:25:49 PM PDT 24 3525415600 ps
T1193 /workspace/coverage/default/2.chip_sw_clkmgr_jitter.2478205067 Jun 28 08:20:29 PM PDT 24 Jun 28 08:23:52 PM PDT 24 3340294478 ps
T331 /workspace/coverage/default/0.chip_sw_i2c_device_tx_rx.1610728558 Jun 28 08:04:29 PM PDT 24 Jun 28 08:14:45 PM PDT 24 3661705908 ps
T232 /workspace/coverage/default/1.chip_sw_lc_walkthrough_prod.3356642554 Jun 28 08:06:44 PM PDT 24 Jun 28 09:35:51 PM PDT 24 48331076782 ps
T350 /workspace/coverage/default/2.chip_sw_sensor_ctrl_status.3156442694 Jun 28 08:20:16 PM PDT 24 Jun 28 08:26:18 PM PDT 24 3351120728 ps
T1194 /workspace/coverage/default/2.chip_sw_sysrst_ctrl_inputs.801661510 Jun 28 08:17:36 PM PDT 24 Jun 28 08:22:52 PM PDT 24 3209769156 ps
T1195 /workspace/coverage/default/0.chip_sw_kmac_idle.2776452493 Jun 28 08:02:30 PM PDT 24 Jun 28 08:05:35 PM PDT 24 3161204800 ps
T1196 /workspace/coverage/default/2.chip_sw_sleep_pwm_pulses.3668448138 Jun 28 08:18:31 PM PDT 24 Jun 28 08:41:38 PM PDT 24 8552124108 ps
T1197 /workspace/coverage/default/2.chip_sw_clkmgr_off_hmac_trans.438850963 Jun 28 08:22:38 PM PDT 24 Jun 28 08:31:10 PM PDT 24 5468169516 ps
T1198 /workspace/coverage/default/0.chip_sw_gpio_smoketest.2351342836 Jun 28 08:05:05 PM PDT 24 Jun 28 08:10:54 PM PDT 24 3114502957 ps
T1199 /workspace/coverage/default/81.chip_sw_all_escalation_resets.1873469126 Jun 28 08:31:28 PM PDT 24 Jun 28 08:43:01 PM PDT 24 5868441258 ps
T1200 /workspace/coverage/default/2.chip_sw_aon_timer_smoketest.1859219119 Jun 28 08:22:48 PM PDT 24 Jun 28 08:27:26 PM PDT 24 2380675312 ps
T1201 /workspace/coverage/default/2.chip_sw_clkmgr_off_peri.3140212416 Jun 28 08:25:45 PM PDT 24 Jun 28 08:46:07 PM PDT 24 9761186088 ps
T433 /workspace/coverage/default/2.chip_sw_edn_entropy_reqs.2122207754 Jun 28 08:21:14 PM PDT 24 Jun 28 08:39:23 PM PDT 24 6587047980 ps
T1202 /workspace/coverage/default/0.chip_sw_kmac_smoketest.4279772807 Jun 28 08:06:42 PM PDT 24 Jun 28 08:11:55 PM PDT 24 2545334890 ps
T434 /workspace/coverage/default/1.chip_sw_edn_entropy_reqs_jitter.129960052 Jun 28 08:05:46 PM PDT 24 Jun 28 08:26:50 PM PDT 24 6786561538 ps
T70 /workspace/coverage/default/0.chip_sw_usbdev_aon_pullup.4241973835 Jun 28 08:01:53 PM PDT 24 Jun 28 08:10:09 PM PDT 24 4307890000 ps
T1203 /workspace/coverage/default/2.chip_sw_pwrmgr_usb_clk_disabled_when_active.1314807643 Jun 28 08:17:16 PM PDT 24 Jun 28 08:24:11 PM PDT 24 5354525240 ps
T246 /workspace/coverage/default/40.chip_sw_alert_handler_lpg_sleep_mode_alerts.3699741967 Jun 28 08:28:41 PM PDT 24 Jun 28 08:36:10 PM PDT 24 3242866766 ps
T1204 /workspace/coverage/default/1.chip_sw_otp_ctrl_smoketest.2503721246 Jun 28 08:14:06 PM PDT 24 Jun 28 08:18:24 PM PDT 24 3206004720 ps
T1205 /workspace/coverage/default/0.chip_sw_pwrmgr_normal_sleep_all_reset_reqs.984245452 Jun 28 08:06:03 PM PDT 24 Jun 28 08:34:47 PM PDT 24 12813070336 ps
T1206 /workspace/coverage/default/1.chip_tap_straps_prod.953852897 Jun 28 08:08:53 PM PDT 24 Jun 28 08:34:04 PM PDT 24 14239617748 ps
T234 /workspace/coverage/default/1.chip_sw_flash_init_reduced_freq.2868418750 Jun 28 08:09:46 PM PDT 24 Jun 28 08:49:42 PM PDT 24 26972560770 ps
T1207 /workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0.3697656341 Jun 28 08:04:32 PM PDT 24 Jun 28 08:16:16 PM PDT 24 4801450314 ps
T1208 /workspace/coverage/default/0.chip_sw_pwrmgr_full_aon_reset.3206464959 Jun 28 08:04:52 PM PDT 24 Jun 28 08:14:14 PM PDT 24 7127327146 ps
T1209 /workspace/coverage/default/0.chip_sw_sensor_ctrl_status.1245820715 Jun 28 08:02:16 PM PDT 24 Jun 28 08:05:09 PM PDT 24 2355115400 ps
T1210 /workspace/coverage/default/1.chip_sw_example_rom.3654150109 Jun 28 08:03:58 PM PDT 24 Jun 28 08:06:08 PM PDT 24 2306711720 ps
T1211 /workspace/coverage/default/0.chip_sw_uart_tx_rx_alt_clk_freq.4221715152 Jun 28 08:03:56 PM PDT 24 Jun 28 08:13:35 PM PDT 24 3990414305 ps
T771 /workspace/coverage/default/36.chip_sw_alert_handler_lpg_sleep_mode_alerts.2122396574 Jun 28 08:29:38 PM PDT 24 Jun 28 08:35:57 PM PDT 24 3462942192 ps
T1212 /workspace/coverage/default/2.chip_sw_clkmgr_jitter_frequency.2164261472 Jun 28 08:20:51 PM PDT 24 Jun 28 08:28:20 PM PDT 24 3348119080 ps
T1213 /workspace/coverage/default/0.chip_sw_coremark.756058088 Jun 28 08:01:56 PM PDT 24 Jun 28 11:37:59 PM PDT 24 71446574120 ps
T1214 /workspace/coverage/default/1.chip_sw_sysrst_ctrl_inputs.157830258 Jun 28 08:07:03 PM PDT 24 Jun 28 08:11:57 PM PDT 24 2621361660 ps
T1215 /workspace/coverage/default/1.chip_sw_keymgr_key_derivation.2091936392 Jun 28 08:08:15 PM PDT 24 Jun 28 08:36:49 PM PDT 24 8788805466 ps
T1216 /workspace/coverage/default/2.chip_sw_flash_ctrl_access_jitter_en.4156299436 Jun 28 08:16:42 PM PDT 24 Jun 28 08:34:39 PM PDT 24 6288105938 ps
T647 /workspace/coverage/default/15.chip_sw_all_escalation_resets.3743338603 Jun 28 08:27:20 PM PDT 24 Jun 28 08:37:11 PM PDT 24 4607983704 ps
T194 /workspace/coverage/default/0.chip_jtag_mem_access.332995562 Jun 28 07:52:11 PM PDT 24 Jun 28 08:19:40 PM PDT 24 13775035272 ps
T176 /workspace/coverage/default/0.chip_sw_flash_rma_unlocked.1315794785 Jun 28 08:04:34 PM PDT 24 Jun 28 09:32:18 PM PDT 24 43693080168 ps
T642 /workspace/coverage/default/0.chip_tap_straps_dev.4286491602 Jun 28 08:01:33 PM PDT 24 Jun 28 08:22:54 PM PDT 24 11478278428 ps
T1217 /workspace/coverage/default/8.chip_sw_uart_rand_baudrate.658662805 Jun 28 08:25:48 PM PDT 24 Jun 28 08:37:32 PM PDT 24 4131727208 ps
T365 /workspace/coverage/default/1.chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up.3911690878 Jun 28 08:10:59 PM PDT 24 Jun 28 08:19:21 PM PDT 24 5820224884 ps
T303 /workspace/coverage/default/2.chip_sw_rv_core_ibex_address_translation.3184278564 Jun 28 08:23:40 PM PDT 24 Jun 28 08:28:53 PM PDT 24 2922318120 ps
T59 /workspace/coverage/default/2.chip_sw_alert_test.3048746062 Jun 28 08:19:48 PM PDT 24 Jun 28 08:26:15 PM PDT 24 3800553344 ps
T675 /workspace/coverage/default/0.chip_sw_rv_core_ibex_nmi_irq.2925763891 Jun 28 08:06:10 PM PDT 24 Jun 28 08:19:02 PM PDT 24 4859630902 ps
T1218 /workspace/coverage/default/0.rom_e2e_asm_init_rma.3119599089 Jun 28 08:06:31 PM PDT 24 Jun 28 09:13:58 PM PDT 24 14911942578 ps
T1219 /workspace/coverage/default/1.chip_sw_aes_smoketest.1043586261 Jun 28 08:11:51 PM PDT 24 Jun 28 08:16:36 PM PDT 24 3295655720 ps
T1220 /workspace/coverage/default/1.chip_sw_edn_entropy_reqs.3210207238 Jun 28 08:09:01 PM PDT 24 Jun 28 08:26:29 PM PDT 24 4998544252 ps
T1221 /workspace/coverage/default/2.chip_sw_csrng_kat_test.1343743972 Jun 28 08:19:54 PM PDT 24 Jun 28 08:24:22 PM PDT 24 2629216730 ps
T769 /workspace/coverage/default/86.chip_sw_all_escalation_resets.3731876717 Jun 28 08:33:40 PM PDT 24 Jun 28 08:42:32 PM PDT 24 5236358924 ps
T1222 /workspace/coverage/default/1.chip_sw_kmac_entropy.3258450570 Jun 28 08:04:28 PM PDT 24 Jun 28 08:08:16 PM PDT 24 2689743054 ps
T1223 /workspace/coverage/default/2.chip_sw_aon_timer_wdog_bite_reset.1439182152 Jun 28 08:19:00 PM PDT 24 Jun 28 08:28:58 PM PDT 24 8323954956 ps
T1224 /workspace/coverage/default/57.chip_sw_all_escalation_resets.3497089236 Jun 28 08:29:21 PM PDT 24 Jun 28 08:39:17 PM PDT 24 4316094560 ps
T1225 /workspace/coverage/default/63.chip_sw_alert_handler_lpg_sleep_mode_alerts.2650565779 Jun 28 08:31:18 PM PDT 24 Jun 28 08:40:44 PM PDT 24 4175091840 ps
T321 /workspace/coverage/default/0.chip_plic_all_irqs_20.2532708970 Jun 28 08:00:52 PM PDT 24 Jun 28 08:14:10 PM PDT 24 4222516688 ps
T1226 /workspace/coverage/default/0.chip_sw_uart_tx_rx.1433766415 Jun 28 07:59:16 PM PDT 24 Jun 28 08:09:10 PM PDT 24 4035742308 ps
T1227 /workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_fast_dev.3374603571 Jun 28 08:07:41 PM PDT 24 Jun 28 08:19:49 PM PDT 24 3689608176 ps
T727 /workspace/coverage/default/28.chip_sw_alert_handler_lpg_sleep_mode_alerts.656987623 Jun 28 08:28:10 PM PDT 24 Jun 28 08:35:27 PM PDT 24 3621708022 ps
T1228 /workspace/coverage/default/1.chip_sw_lc_walkthrough_prodend.1475230851 Jun 28 08:05:21 PM PDT 24 Jun 28 08:21:04 PM PDT 24 10665512768 ps
T1229 /workspace/coverage/default/9.chip_sw_alert_handler_lpg_sleep_mode_alerts.66231888 Jun 28 08:26:34 PM PDT 24 Jun 28 08:34:17 PM PDT 24 3669014548 ps
T1230 /workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_lc.3422711278 Jun 28 08:01:32 PM PDT 24 Jun 28 08:17:06 PM PDT 24 12340363664 ps
T1231 /workspace/coverage/default/2.chip_sw_hmac_multistream.4065592737 Jun 28 08:20:03 PM PDT 24 Jun 28 08:48:50 PM PDT 24 6589358650 ps
T126 /workspace/coverage/default/1.chip_sw_sensor_ctrl_alert.1530754408 Jun 28 08:05:29 PM PDT 24 Jun 28 08:19:58 PM PDT 24 6872032462 ps
T233 /workspace/coverage/default/0.chip_sw_flash_ctrl_lc_rw_en.1152382280 Jun 28 08:02:43 PM PDT 24 Jun 28 08:09:14 PM PDT 24 5314047496 ps
T1232 /workspace/coverage/default/1.chip_sw_alert_handler_lpg_sleep_mode_pings.289317447 Jun 28 08:02:49 PM PDT 24 Jun 28 08:32:03 PM PDT 24 13003603082 ps
T1233 /workspace/coverage/default/1.chip_sw_pwrmgr_smoketest.1855210578 Jun 28 08:14:54 PM PDT 24 Jun 28 08:21:12 PM PDT 24 5324420400 ps
T746 /workspace/coverage/default/74.chip_sw_alert_handler_lpg_sleep_mode_alerts.742345032 Jun 28 08:30:57 PM PDT 24 Jun 28 08:40:10 PM PDT 24 3689464216 ps
T1234 /workspace/coverage/default/2.chip_sw_hmac_smoketest.3408695146 Jun 28 08:23:22 PM PDT 24 Jun 28 08:29:52 PM PDT 24 3471835284 ps
T1235 /workspace/coverage/default/0.chip_sw_flash_scrambling_smoketest.2516288326 Jun 28 08:05:24 PM PDT 24 Jun 28 08:08:58 PM PDT 24 2668119216 ps
T416 /workspace/coverage/default/1.chip_sw_pwrmgr_normal_sleep_all_wake_ups.4280149669 Jun 28 08:08:28 PM PDT 24 Jun 28 08:16:43 PM PDT 24 7269727144 ps
T1236 /workspace/coverage/default/1.chip_sw_rv_timer_smoketest.2822300874 Jun 28 08:13:44 PM PDT 24 Jun 28 08:18:10 PM PDT 24 3222488584 ps
T1237 /workspace/coverage/default/1.chip_sw_rv_timer_irq.2966123120 Jun 28 08:05:21 PM PDT 24 Jun 28 08:09:19 PM PDT 24 2748373368 ps
T1238 /workspace/coverage/default/0.chip_sw_power_idle_load.2362173916 Jun 28 08:02:03 PM PDT 24 Jun 28 08:13:28 PM PDT 24 4774897206 ps
T332 /workspace/coverage/default/2.chip_sw_i2c_device_tx_rx.306905686 Jun 28 08:15:12 PM PDT 24 Jun 28 08:25:24 PM PDT 24 3836077860 ps
T1239 /workspace/coverage/default/0.chip_sw_rv_plic_smoketest.828578841 Jun 28 08:02:27 PM PDT 24 Jun 28 08:07:00 PM PDT 24 2822506812 ps
T1240 /workspace/coverage/default/0.chip_sw_flash_ctrl_write_clear.1431411466 Jun 28 08:01:57 PM PDT 24 Jun 28 08:06:11 PM PDT 24 3472385286 ps
T1241 /workspace/coverage/default/2.chip_sw_pwrmgr_sysrst_ctrl_reset.144465129 Jun 28 08:17:52 PM PDT 24 Jun 28 08:32:39 PM PDT 24 6913425496 ps
T366 /workspace/coverage/default/0.chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up.807800448 Jun 28 08:02:03 PM PDT 24 Jun 28 08:06:59 PM PDT 24 4910091476 ps
T1242 /workspace/coverage/default/0.chip_sw_pwrmgr_all_reset_reqs.1271256595 Jun 28 08:04:19 PM PDT 24 Jun 28 08:29:26 PM PDT 24 9155729569 ps
T761 /workspace/coverage/default/50.chip_sw_alert_handler_lpg_sleep_mode_alerts.1848408507 Jun 28 08:29:17 PM PDT 24 Jun 28 08:35:49 PM PDT 24 3684245946 ps
T44 /workspace/coverage/default/0.chip_sw_spi_host_tx_rx.1798969969 Jun 28 08:03:01 PM PDT 24 Jun 28 08:07:35 PM PDT 24 3347069664 ps
T738 /workspace/coverage/default/49.chip_sw_alert_handler_lpg_sleep_mode_alerts.3010408832 Jun 28 08:29:51 PM PDT 24 Jun 28 08:36:08 PM PDT 24 3351468050 ps
T1243 /workspace/coverage/default/2.chip_sw_otbn_ecdsa_op_irq.909602465 Jun 28 08:19:15 PM PDT 24 Jun 28 09:21:32 PM PDT 24 17127594998 ps
T1244 /workspace/coverage/default/1.chip_sw_pwrmgr_random_sleep_power_glitch_reset.3555894433 Jun 28 08:05:44 PM PDT 24 Jun 28 08:53:52 PM PDT 24 31520037507 ps
T1245 /workspace/coverage/default/1.chip_sw_ast_clk_outputs.1052753196 Jun 28 08:11:56 PM PDT 24 Jun 28 08:26:58 PM PDT 24 6619121886 ps
T770 /workspace/coverage/default/67.chip_sw_all_escalation_resets.4046381713 Jun 28 08:31:14 PM PDT 24 Jun 28 08:41:52 PM PDT 24 5644072720 ps
T1246 /workspace/coverage/default/78.chip_sw_alert_handler_lpg_sleep_mode_alerts.1919560452 Jun 28 08:31:31 PM PDT 24 Jun 28 08:38:25 PM PDT 24 3658508968 ps
T1247 /workspace/coverage/default/2.chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq.1406368996 Jun 28 08:21:26 PM PDT 24 Jun 28 09:32:24 PM PDT 24 24461670818 ps
T1248 /workspace/coverage/default/1.chip_sw_rom_ctrl_integrity_check.788579283 Jun 28 08:08:07 PM PDT 24 Jun 28 08:20:04 PM PDT 24 8217470796 ps
T1249 /workspace/coverage/default/1.chip_sw_csrng_fuse_en_sw_app_read_test.934290766 Jun 28 08:04:43 PM PDT 24 Jun 28 08:10:37 PM PDT 24 4498135208 ps
T1250 /workspace/coverage/default/1.chip_sw_flash_rma_unlocked.4059088092 Jun 28 08:05:53 PM PDT 24 Jun 28 09:40:13 PM PDT 24 43695656139 ps
T85 /workspace/coverage/default/9.chip_sw_all_escalation_resets.1704068829 Jun 28 08:28:49 PM PDT 24 Jun 28 08:40:12 PM PDT 24 5583910984 ps
T1251 /workspace/coverage/default/2.chip_sw_edn_kat.2185148412 Jun 28 08:20:46 PM PDT 24 Jun 28 08:30:07 PM PDT 24 3557865900 ps
T1252 /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_good_prod_end.2553749177 Jun 28 08:09:24 PM PDT 24 Jun 28 09:17:44 PM PDT 24 15498375640 ps
T1253 /workspace/coverage/default/0.chip_sw_edn_entropy_reqs.4091722933 Jun 28 08:02:18 PM PDT 24 Jun 28 08:20:58 PM PDT 24 6209836248 ps
T776 /workspace/coverage/default/26.chip_sw_all_escalation_resets.3439628811 Jun 28 08:29:57 PM PDT 24 Jun 28 08:42:07 PM PDT 24 4462412600 ps
T683 /workspace/coverage/default/56.chip_sw_all_escalation_resets.3112455378 Jun 28 08:34:19 PM PDT 24 Jun 28 08:44:27 PM PDT 24 5792478696 ps
T1254 /workspace/coverage/default/1.chip_sw_sleep_sram_ret_contents_scramble.857352575 Jun 28 08:12:50 PM PDT 24 Jun 28 08:24:45 PM PDT 24 9028361760 ps
T15 /workspace/coverage/default/0.chip_sw_sleep_pin_wake.2541067219 Jun 28 08:01:39 PM PDT 24 Jun 28 08:07:35 PM PDT 24 2866655098 ps
T1255 /workspace/coverage/default/0.chip_sw_uart_tx_rx_idx3.3051713029 Jun 28 08:04:10 PM PDT 24 Jun 28 08:14:56 PM PDT 24 3871900824 ps
T1256 /workspace/coverage/default/1.chip_sw_clkmgr_off_hmac_trans.3330575077 Jun 28 08:08:36 PM PDT 24 Jun 28 08:16:59 PM PDT 24 4028253464 ps
T1257 /workspace/coverage/default/2.chip_sw_pwrmgr_b2b_sleep_reset_req.3265194111 Jun 28 08:26:59 PM PDT 24 Jun 28 09:05:04 PM PDT 24 25878315217 ps
T1258 /workspace/coverage/default/0.chip_sw_entropy_src_smoketest.1130075157 Jun 28 08:06:46 PM PDT 24 Jun 28 08:17:21 PM PDT 24 3876309788 ps
T86 /workspace/coverage/default/76.chip_sw_all_escalation_resets.2717093730 Jun 28 08:31:52 PM PDT 24 Jun 28 08:39:41 PM PDT 24 4863242100 ps
T1259 /workspace/coverage/default/2.chip_sw_flash_ctrl_idle_low_power.903524411 Jun 28 08:17:23 PM PDT 24 Jun 28 08:22:57 PM PDT 24 3390905880 ps
T1260 /workspace/coverage/default/1.chip_sw_alert_handler_escalation.1442014493 Jun 28 08:07:25 PM PDT 24 Jun 28 08:15:57 PM PDT 24 4792954280 ps
T756 /workspace/coverage/default/69.chip_sw_alert_handler_lpg_sleep_mode_alerts.2172182477 Jun 28 08:31:45 PM PDT 24 Jun 28 08:40:36 PM PDT 24 4368100888 ps
T1261 /workspace/coverage/default/1.chip_sw_adc_ctrl_sleep_debug_cable_wakeup.3427295794 Jun 28 08:06:27 PM PDT 24 Jun 28 08:18:13 PM PDT 24 19961328840 ps
T1262 /workspace/coverage/default/1.chip_sw_flash_ctrl_lc_rw_en.3257868311 Jun 28 08:02:27 PM PDT 24 Jun 28 08:13:31 PM PDT 24 5080041160 ps
T779 /workspace/coverage/default/33.chip_sw_all_escalation_resets.2577061249 Jun 28 08:27:39 PM PDT 24 Jun 28 08:41:04 PM PDT 24 6009376492 ps
T1263 /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_good_dev.3574142547 Jun 28 08:08:14 PM PDT 24 Jun 28 09:34:48 PM PDT 24 15406784680 ps
T1264 /workspace/coverage/default/2.rom_e2e_asm_init_test_unlocked0.3125412994 Jun 28 08:26:58 PM PDT 24 Jun 28 09:11:11 PM PDT 24 10999196669 ps
T1265 /workspace/coverage/default/2.chip_sw_lc_ctrl_transition.3844750829 Jun 28 08:16:51 PM PDT 24 Jun 28 08:36:49 PM PDT 24 11246029548 ps
T1266 /workspace/coverage/default/0.rom_volatile_raw_unlock.1452334033 Jun 28 08:02:51 PM PDT 24 Jun 28 08:04:50 PM PDT 24 2672524425 ps
T1267 /workspace/coverage/default/8.chip_sw_lc_ctrl_transition.314355593 Jun 28 08:26:30 PM PDT 24 Jun 28 08:37:23 PM PDT 24 5255177762 ps
T1268 /workspace/coverage/default/0.chip_sw_rstmgr_sw_rst.4225890882 Jun 28 08:07:19 PM PDT 24 Jun 28 08:11:22 PM PDT 24 2478087688 ps
T1269 /workspace/coverage/default/65.chip_sw_all_escalation_resets.1771801247 Jun 28 08:30:52 PM PDT 24 Jun 28 08:41:16 PM PDT 24 5597913946 ps
T1270 /workspace/coverage/default/0.chip_tap_straps_rma.2217734018 Jun 28 08:05:12 PM PDT 24 Jun 28 08:18:30 PM PDT 24 7149827059 ps
T1271 /workspace/coverage/default/11.chip_sw_lc_ctrl_transition.1116905361 Jun 28 08:25:43 PM PDT 24 Jun 28 08:43:27 PM PDT 24 9564289458 ps
T71 /workspace/coverage/default/0.chip_sw_usbdev_pincfg.4243842022 Jun 28 08:00:24 PM PDT 24 Jun 28 10:08:42 PM PDT 24 31821483092 ps
T1272 /workspace/coverage/default/2.chip_sw_sysrst_ctrl_reset.324178661 Jun 28 08:16:55 PM PDT 24 Jun 28 08:46:47 PM PDT 24 24392304808 ps
T1273 /workspace/coverage/default/0.chip_sw_aon_timer_sleep_wdog_sleep_pause.3402227692 Jun 28 08:07:02 PM PDT 24 Jun 28 08:13:49 PM PDT 24 6881187256 ps
T630 /workspace/coverage/default/0.chip_sw_edn_boot_mode.293855638 Jun 28 08:07:22 PM PDT 24 Jun 28 08:17:48 PM PDT 24 3137559912 ps
T1274 /workspace/coverage/default/2.chip_sw_kmac_mode_kmac.3031753807 Jun 28 08:20:09 PM PDT 24 Jun 28 08:23:59 PM PDT 24 2815578392 ps
T130 /workspace/coverage/default/1.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup.2652429133 Jun 28 08:04:29 PM PDT 24 Jun 28 08:11:11 PM PDT 24 5100727560 ps
T1275 /workspace/coverage/default/2.chip_sw_clkmgr_off_aes_trans.70744297 Jun 28 08:27:01 PM PDT 24 Jun 28 08:37:16 PM PDT 24 4235319870 ps
T1276 /workspace/coverage/default/2.chip_sw_flash_ctrl_lc_rw_en.4110071998 Jun 28 08:16:13 PM PDT 24 Jun 28 08:23:17 PM PDT 24 3600691400 ps
T1277 /workspace/coverage/default/2.chip_sw_lc_walkthrough_prod.362154746 Jun 28 08:16:39 PM PDT 24 Jun 28 09:50:32 PM PDT 24 50063856664 ps
T38 /workspace/coverage/default/2.chip_sw_gpio.1791974755 Jun 28 08:16:46 PM PDT 24 Jun 28 08:26:43 PM PDT 24 4359847151 ps
T1278 /workspace/coverage/default/1.chip_sw_edn_auto_mode.3912129630 Jun 28 08:07:35 PM PDT 24 Jun 28 08:24:47 PM PDT 24 4735320280 ps
T129 /workspace/coverage/default/2.chip_sw_sensor_ctrl_alert.3624216548 Jun 28 08:21:33 PM PDT 24 Jun 28 08:41:59 PM PDT 24 9065490440 ps
T1279 /workspace/coverage/default/1.chip_sw_otp_ctrl_ecc_error_vendor_test.1556538451 Jun 28 08:06:01 PM PDT 24 Jun 28 08:09:07 PM PDT 24 2779731107 ps
T1280 /workspace/coverage/default/1.rom_e2e_shutdown_exception_c.3023302921 Jun 28 08:16:56 PM PDT 24 Jun 28 09:17:32 PM PDT 24 14827291436 ps
T1281 /workspace/coverage/default/0.chip_sw_sram_ctrl_scrambled_access_jitter_en.2665170656 Jun 28 08:01:57 PM PDT 24 Jun 28 08:08:53 PM PDT 24 3941506938 ps
T1282 /workspace/coverage/default/0.chip_sw_pwrmgr_sysrst_ctrl_reset.3221734107 Jun 28 08:04:19 PM PDT 24 Jun 28 08:24:50 PM PDT 24 8160469238 ps
T1283 /workspace/coverage/default/1.chip_sw_kmac_app_rom.3789153453 Jun 28 08:03:47 PM PDT 24 Jun 28 08:07:38 PM PDT 24 3044410500 ps
T1284 /workspace/coverage/default/0.chip_sw_otp_ctrl_lc_signals_prod.3108265813 Jun 28 08:04:16 PM PDT 24 Jun 28 08:27:07 PM PDT 24 7963715136 ps
T747 /workspace/coverage/default/27.chip_sw_alert_handler_lpg_sleep_mode_alerts.4051008983 Jun 28 08:27:24 PM PDT 24 Jun 28 08:34:42 PM PDT 24 4076033776 ps
T1285 /workspace/coverage/default/1.chip_sw_power_sleep_load.2712266282 Jun 28 08:10:24 PM PDT 24 Jun 28 08:18:27 PM PDT 24 9616151250 ps
T13 /workspace/coverage/default/2.chip_sw_sleep_pin_retention.1584293017 Jun 28 08:15:25 PM PDT 24 Jun 28 08:21:15 PM PDT 24 3079610200 ps
T1286 /workspace/coverage/default/4.chip_sw_aon_timer_sleep_wdog_sleep_pause.1763793072 Jun 28 08:23:48 PM PDT 24 Jun 28 08:34:06 PM PDT 24 7182701396 ps
T149 /workspace/coverage/default/1.chip_plic_all_irqs_10.3984785500 Jun 28 08:11:15 PM PDT 24 Jun 28 08:22:04 PM PDT 24 3790694200 ps
T1287 /workspace/coverage/default/2.chip_sw_pwrmgr_deep_sleep_power_glitch_reset.1401042690 Jun 28 08:17:25 PM PDT 24 Jun 28 08:26:08 PM PDT 24 6300784224 ps
T1288 /workspace/coverage/default/1.chip_sw_pwrmgr_usbdev_smoketest.232237216 Jun 28 08:13:17 PM PDT 24 Jun 28 08:20:54 PM PDT 24 5849601906 ps
T1289 /workspace/coverage/default/0.chip_sw_clkmgr_reset_frequency.2502439524 Jun 28 08:00:14 PM PDT 24 Jun 28 08:07:13 PM PDT 24 3623954780 ps
T1290 /workspace/coverage/default/1.chip_sw_clkmgr_off_kmac_trans.437896880 Jun 28 08:05:17 PM PDT 24 Jun 28 08:14:10 PM PDT 24 5237609106 ps
T1291 /workspace/coverage/default/1.chip_sw_flash_ctrl_write_clear.4123140168 Jun 28 08:11:00 PM PDT 24 Jun 28 08:18:00 PM PDT 24 3135948184 ps
T1292 /workspace/coverage/default/0.chip_sw_clkmgr_sleep_frequency.2669639601 Jun 28 08:02:21 PM PDT 24 Jun 28 08:13:40 PM PDT 24 4880704000 ps
T1293 /workspace/coverage/default/0.chip_sw_aon_timer_irq.1309822599 Jun 28 08:05:47 PM PDT 24 Jun 28 08:12:45 PM PDT 24 3845547120 ps
T1294 /workspace/coverage/default/2.chip_sw_pwrmgr_all_reset_reqs.2980896272 Jun 28 08:16:46 PM PDT 24 Jun 28 08:41:22 PM PDT 24 10675769516 ps
T1295 /workspace/coverage/default/2.chip_sw_hmac_enc_jitter_en_reduced_freq.2033254413 Jun 28 08:22:23 PM PDT 24 Jun 28 08:27:00 PM PDT 24 3510889039 ps
T150 /workspace/coverage/default/0.chip_plic_all_irqs_10.1860591453 Jun 28 08:02:05 PM PDT 24 Jun 28 08:11:45 PM PDT 24 4132161704 ps
T758 /workspace/coverage/default/93.chip_sw_all_escalation_resets.2049009559 Jun 28 08:32:00 PM PDT 24 Jun 28 08:43:50 PM PDT 24 6160442640 ps
T267 /workspace/coverage/default/1.chip_sw_data_integrity_escalation.2181326246 Jun 28 08:06:47 PM PDT 24 Jun 28 08:21:14 PM PDT 24 4704843910 ps
T1296 /workspace/coverage/default/98.chip_sw_all_escalation_resets.2519151808 Jun 28 08:32:30 PM PDT 24 Jun 28 08:43:33 PM PDT 24 5109550928 ps
T1297 /workspace/coverage/default/34.chip_sw_all_escalation_resets.2393304124 Jun 28 08:29:15 PM PDT 24 Jun 28 08:39:58 PM PDT 24 4991424068 ps
T1298 /workspace/coverage/default/3.chip_sw_uart_tx_rx_idx3.3636744622 Jun 28 08:23:51 PM PDT 24 Jun 28 08:33:51 PM PDT 24 3815986910 ps
T1299 /workspace/coverage/default/1.chip_sw_otp_ctrl_lc_signals_dev.158313442 Jun 28 08:03:47 PM PDT 24 Jun 28 08:24:27 PM PDT 24 7101114680 ps
T312 /workspace/coverage/default/49.chip_sw_all_escalation_resets.1521282607 Jun 28 08:29:05 PM PDT 24 Jun 28 08:41:47 PM PDT 24 5267630088 ps
T1300 /workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_slow_dev.195110657 Jun 28 08:01:19 PM PDT 24 Jun 28 08:11:40 PM PDT 24 4644159070 ps
T1301 /workspace/coverage/default/0.chip_sw_alert_handler_reverse_ping_in_deep_sleep.1780320149 Jun 28 08:06:40 PM PDT 24 Jun 28 11:43:38 PM PDT 24 255484399790 ps
T777 /workspace/coverage/default/73.chip_sw_alert_handler_lpg_sleep_mode_alerts.3348703761 Jun 28 08:31:49 PM PDT 24 Jun 28 08:38:33 PM PDT 24 3841799152 ps
T1302 /workspace/coverage/default/2.chip_sw_aes_enc.4186486162 Jun 28 08:18:15 PM PDT 24 Jun 28 08:23:33 PM PDT 24 3212319000 ps
T1303 /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0.1882292226 Jun 28 08:11:29 PM PDT 24 Jun 28 09:09:26 PM PDT 24 11178785326 ps
T1304 /workspace/coverage/default/2.chip_sw_edn_entropy_reqs_jitter.1059610653 Jun 28 08:22:41 PM PDT 24 Jun 28 08:43:00 PM PDT 24 6436311223 ps
T1305 /workspace/coverage/default/0.chip_sw_uart_tx_rx_bootstrap.928782164 Jun 28 07:58:55 PM PDT 24 Jun 28 11:41:49 PM PDT 24 78275369720 ps
T1306 /workspace/coverage/default/55.chip_sw_all_escalation_resets.3325170819 Jun 28 08:29:46 PM PDT 24 Jun 28 08:41:38 PM PDT 24 5585874040 ps
T1307 /workspace/coverage/default/0.chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq.1002678145 Jun 28 08:09:08 PM PDT 24 Jun 28 09:22:38 PM PDT 24 25117098733 ps
T1308 /workspace/coverage/default/0.chip_sw_example_rom.568750640 Jun 28 07:59:29 PM PDT 24 Jun 28 08:02:01 PM PDT 24 2428486680 ps
T1309 /workspace/coverage/default/2.chip_sw_pwrmgr_smoketest.1567355369 Jun 28 08:29:00 PM PDT 24 Jun 28 08:37:28 PM PDT 24 5668392930 ps
T72 /workspace/coverage/cover_reg_top/95.xbar_stress_all.99193960 Jun 28 08:52:11 PM PDT 24 Jun 28 08:53:31 PM PDT 24 906718185 ps
T73 /workspace/coverage/cover_reg_top/34.xbar_smoke.619574926 Jun 28 08:40:45 PM PDT 24 Jun 28 08:41:07 PM PDT 24 207784534 ps
T74 /workspace/coverage/cover_reg_top/25.xbar_smoke_slow_rsp.3536673991 Jun 28 08:38:40 PM PDT 24 Jun 28 08:40:31 PM PDT 24 5871757307 ps
T80 /workspace/coverage/cover_reg_top/69.xbar_stress_all_with_rand_reset.1043812193 Jun 28 08:47:22 PM PDT 24 Jun 28 08:48:37 PM PDT 24 233208496 ps
T79 /workspace/coverage/cover_reg_top/88.xbar_error_random.3206991564 Jun 28 08:50:24 PM PDT 24 Jun 28 08:51:33 PM PDT 24 451431956 ps
T235 /workspace/coverage/cover_reg_top/31.xbar_random_zero_delays.1588732013 Jun 28 08:39:49 PM PDT 24 Jun 28 08:40:03 PM PDT 24 73371293 ps
T530 /workspace/coverage/cover_reg_top/69.xbar_smoke_zero_delays.1752033577 Jun 28 08:46:59 PM PDT 24 Jun 28 08:47:36 PM PDT 24 53164641 ps
T247 /workspace/coverage/cover_reg_top/17.xbar_stress_all_with_reset_error.716457461 Jun 28 08:36:50 PM PDT 24 Jun 28 08:40:22 PM PDT 24 936716676 ps
T522 /workspace/coverage/cover_reg_top/19.xbar_random.3960077749 Jun 28 08:37:03 PM PDT 24 Jun 28 08:37:45 PM PDT 24 246809061 ps
T248 /workspace/coverage/cover_reg_top/99.xbar_stress_all_with_error.117021631 Jun 28 08:53:16 PM PDT 24 Jun 28 08:56:28 PM PDT 24 1802629823 ps
T725 /workspace/coverage/cover_reg_top/13.xbar_access_same_device.3073360700 Jun 28 08:35:10 PM PDT 24 Jun 28 08:35:51 PM PDT 24 546318052 ps
T377 /workspace/coverage/cover_reg_top/4.chip_csr_rw.20175261 Jun 28 08:30:50 PM PDT 24 Jun 28 08:38:37 PM PDT 24 4811459938 ps
T527 /workspace/coverage/cover_reg_top/74.xbar_smoke_zero_delays.1405573818 Jun 28 08:48:00 PM PDT 24 Jun 28 08:48:29 PM PDT 24 54248896 ps
T538 /workspace/coverage/cover_reg_top/9.xbar_smoke_slow_rsp.3464725338 Jun 28 08:34:00 PM PDT 24 Jun 28 08:36:01 PM PDT 24 6773544783 ps
T515 /workspace/coverage/cover_reg_top/47.xbar_error_random.1015618537 Jun 28 08:42:59 PM PDT 24 Jun 28 08:44:11 PM PDT 24 591004799 ps
T534 /workspace/coverage/cover_reg_top/68.xbar_smoke_large_delays.3516964932 Jun 28 08:46:56 PM PDT 24 Jun 28 08:49:18 PM PDT 24 10979381709 ps
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