| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
| 96.15 | 95.47 | 94.09 | 95.20 | 94.91 | 97.71 | 99.54 |
| T2764 | /workspace/coverage/cover_reg_top/50.xbar_stress_all_with_error.3044130463 | Jun 28 08:43:15 PM PDT 24 | Jun 28 08:47:35 PM PDT 24 | 7135544786 ps | ||
| T2765 | /workspace/coverage/cover_reg_top/57.xbar_stress_all_with_reset_error.2200893446 | Jun 28 08:45:19 PM PDT 24 | Jun 28 08:59:13 PM PDT 24 | 8898235478 ps | ||
| T2766 | /workspace/coverage/cover_reg_top/11.xbar_smoke_slow_rsp.45987367 | Jun 28 08:34:27 PM PDT 24 | Jun 28 08:36:08 PM PDT 24 | 4698951332 ps | ||
| T663 | /workspace/coverage/cover_reg_top/12.chip_tl_errors.2331225516 | Jun 28 08:34:40 PM PDT 24 | Jun 28 08:40:34 PM PDT 24 | 4030487184 ps | ||
| T2767 | /workspace/coverage/cover_reg_top/35.xbar_unmapped_addr.1797591988 | Jun 28 08:40:41 PM PDT 24 | Jun 28 08:41:34 PM PDT 24 | 827150628 ps | ||
| T2768 | /workspace/coverage/cover_reg_top/89.xbar_same_source.216169808 | Jun 28 08:50:40 PM PDT 24 | Jun 28 08:52:05 PM PDT 24 | 1853714051 ps | ||
| T2769 | /workspace/coverage/cover_reg_top/72.xbar_stress_all_with_reset_error.1882972283 | Jun 28 08:47:59 PM PDT 24 | Jun 28 08:52:26 PM PDT 24 | 5695878409 ps | ||
| T2770 | /workspace/coverage/cover_reg_top/65.xbar_error_random.521164595 | Jun 28 08:46:01 PM PDT 24 | Jun 28 08:47:08 PM PDT 24 | 1511864534 ps | ||
| T2771 | /workspace/coverage/cover_reg_top/94.xbar_random_large_delays.1488184639 | Jun 28 08:51:45 PM PDT 24 | Jun 28 09:04:17 PM PDT 24 | 74680742234 ps | ||
| T2772 | /workspace/coverage/cover_reg_top/34.xbar_unmapped_addr.1371408013 | Jun 28 08:40:24 PM PDT 24 | Jun 28 08:41:10 PM PDT 24 | 858158804 ps | ||
| T2773 | /workspace/coverage/cover_reg_top/37.xbar_access_same_device.2464185523 | Jun 28 08:41:06 PM PDT 24 | Jun 28 08:43:01 PM PDT 24 | 2593211296 ps | ||
| T2774 | /workspace/coverage/cover_reg_top/76.xbar_access_same_device.2759408280 | Jun 28 08:48:19 PM PDT 24 | Jun 28 08:49:52 PM PDT 24 | 1861349461 ps | ||
| T2775 | /workspace/coverage/cover_reg_top/7.xbar_stress_all_with_reset_error.3080163857 | Jun 28 08:32:45 PM PDT 24 | Jun 28 08:33:09 PM PDT 24 | 20626393 ps | ||
| T2776 | /workspace/coverage/cover_reg_top/94.xbar_smoke.2261226268 | Jun 28 08:51:26 PM PDT 24 | Jun 28 08:51:56 PM PDT 24 | 212045351 ps | ||
| T2777 | /workspace/coverage/cover_reg_top/75.xbar_same_source.1641034682 | Jun 28 08:48:23 PM PDT 24 | Jun 28 08:49:02 PM PDT 24 | 277174637 ps | ||
| T2778 | /workspace/coverage/cover_reg_top/49.xbar_access_same_device_slow_rsp.891937619 | Jun 28 08:43:13 PM PDT 24 | Jun 28 08:55:38 PM PDT 24 | 41457612059 ps | ||
| T2779 | /workspace/coverage/cover_reg_top/51.xbar_smoke.994576002 | Jun 28 08:43:32 PM PDT 24 | Jun 28 08:43:45 PM PDT 24 | 247743651 ps | ||
| T2780 | /workspace/coverage/cover_reg_top/27.xbar_stress_all_with_rand_reset.4220861504 | Jun 28 08:39:29 PM PDT 24 | Jun 28 08:42:58 PM PDT 24 | 591832782 ps | ||
| T2781 | /workspace/coverage/cover_reg_top/73.xbar_stress_all_with_reset_error.3890416219 | Jun 28 08:48:02 PM PDT 24 | Jun 28 08:51:46 PM PDT 24 | 1374456452 ps | ||
| T2782 | /workspace/coverage/cover_reg_top/18.xbar_smoke.1393660894 | Jun 28 08:36:49 PM PDT 24 | Jun 28 08:37:23 PM PDT 24 | 204714135 ps | ||
| T2783 | /workspace/coverage/cover_reg_top/35.xbar_random_large_delays.2382241037 | Jun 28 08:40:45 PM PDT 24 | Jun 28 08:45:44 PM PDT 24 | 27830893147 ps | ||
| T2784 | /workspace/coverage/cover_reg_top/31.xbar_stress_all_with_rand_reset.1971694456 | Jun 28 08:40:06 PM PDT 24 | Jun 28 08:50:42 PM PDT 24 | 8813880580 ps | ||
| T2785 | /workspace/coverage/cover_reg_top/1.xbar_error_and_unmapped_addr.41899869 | Jun 28 08:28:47 PM PDT 24 | Jun 28 08:29:24 PM PDT 24 | 96772934 ps | ||
| T2786 | /workspace/coverage/cover_reg_top/93.xbar_smoke.714231472 | Jun 28 08:51:32 PM PDT 24 | Jun 28 08:51:58 PM PDT 24 | 49123232 ps | ||
| T2787 | /workspace/coverage/cover_reg_top/80.xbar_error_and_unmapped_addr.2992516556 | Jun 28 08:49:46 PM PDT 24 | Jun 28 08:50:24 PM PDT 24 | 305425734 ps | ||
| T2788 | /workspace/coverage/cover_reg_top/89.xbar_stress_all_with_error.716559824 | Jun 28 08:50:43 PM PDT 24 | Jun 28 08:51:57 PM PDT 24 | 620640036 ps | ||
| T2789 | /workspace/coverage/cover_reg_top/26.xbar_error_and_unmapped_addr.287851366 | Jun 28 08:39:09 PM PDT 24 | Jun 28 08:40:07 PM PDT 24 | 920541395 ps | ||
| T2790 | /workspace/coverage/cover_reg_top/1.chip_csr_aliasing.3015433762 | Jun 28 08:28:10 PM PDT 24 | Jun 28 09:53:05 PM PDT 24 | 38638983875 ps | ||
| T2791 | /workspace/coverage/cover_reg_top/57.xbar_same_source.379954575 | Jun 28 08:45:19 PM PDT 24 | Jun 28 08:45:58 PM PDT 24 | 242561618 ps | ||
| T2792 | /workspace/coverage/cover_reg_top/92.xbar_random.872735668 | Jun 28 08:51:02 PM PDT 24 | Jun 28 08:52:00 PM PDT 24 | 785538603 ps | ||
| T2793 | /workspace/coverage/cover_reg_top/4.xbar_random_zero_delays.2339904254 | Jun 28 08:30:32 PM PDT 24 | Jun 28 08:31:29 PM PDT 24 | 604634612 ps | ||
| T2794 | /workspace/coverage/cover_reg_top/17.xbar_access_same_device_slow_rsp.3878498049 | Jun 28 08:36:50 PM PDT 24 | Jun 28 08:47:10 PM PDT 24 | 32819952055 ps | ||
| T2795 | /workspace/coverage/cover_reg_top/25.xbar_smoke_large_delays.3682639613 | Jun 28 08:38:41 PM PDT 24 | Jun 28 08:40:25 PM PDT 24 | 9317817187 ps | ||
| T2796 | /workspace/coverage/cover_reg_top/59.xbar_stress_all.1497348190 | Jun 28 08:45:30 PM PDT 24 | Jun 28 08:48:19 PM PDT 24 | 3963501500 ps | ||
| T2797 | /workspace/coverage/cover_reg_top/44.xbar_access_same_device_slow_rsp.941422490 | Jun 28 08:42:54 PM PDT 24 | Jun 28 08:51:31 PM PDT 24 | 28411834190 ps | ||
| T2798 | /workspace/coverage/cover_reg_top/81.xbar_smoke.1901014749 | Jun 28 08:49:50 PM PDT 24 | Jun 28 08:50:23 PM PDT 24 | 163504290 ps | ||
| T2799 | /workspace/coverage/cover_reg_top/43.xbar_smoke_slow_rsp.804255015 | Jun 28 08:42:19 PM PDT 24 | Jun 28 08:44:07 PM PDT 24 | 5335903718 ps | ||
| T2800 | /workspace/coverage/cover_reg_top/11.xbar_smoke_zero_delays.2221676470 | Jun 28 08:34:25 PM PDT 24 | Jun 28 08:34:48 PM PDT 24 | 41683034 ps | ||
| T2801 | /workspace/coverage/cover_reg_top/73.xbar_stress_all.1684484423 | Jun 28 08:47:59 PM PDT 24 | Jun 28 08:51:03 PM PDT 24 | 3791827211 ps | ||
| T2802 | /workspace/coverage/cover_reg_top/26.xbar_stress_all_with_error.508038699 | Jun 28 08:39:10 PM PDT 24 | Jun 28 08:42:37 PM PDT 24 | 2129127459 ps | ||
| T2803 | /workspace/coverage/cover_reg_top/36.xbar_smoke_large_delays.361188821 | Jun 28 08:40:42 PM PDT 24 | Jun 28 08:42:12 PM PDT 24 | 7337897742 ps | ||
| T2804 | /workspace/coverage/cover_reg_top/78.xbar_stress_all_with_error.2294817759 | Jun 28 08:49:03 PM PDT 24 | Jun 28 08:51:46 PM PDT 24 | 4603892337 ps | ||
| T2805 | /workspace/coverage/cover_reg_top/53.xbar_stress_all.2470941838 | Jun 28 08:44:47 PM PDT 24 | Jun 28 08:51:10 PM PDT 24 | 4056586762 ps | ||
| T2806 | /workspace/coverage/cover_reg_top/98.xbar_smoke_zero_delays.1170382635 | Jun 28 08:52:40 PM PDT 24 | Jun 28 08:52:50 PM PDT 24 | 50821253 ps | ||
| T2807 | /workspace/coverage/cover_reg_top/78.xbar_random_zero_delays.4135741354 | Jun 28 08:48:24 PM PDT 24 | Jun 28 08:49:09 PM PDT 24 | 329003191 ps | ||
| T2808 | /workspace/coverage/cover_reg_top/86.xbar_random_slow_rsp.2201344542 | Jun 28 08:50:03 PM PDT 24 | Jun 28 08:53:41 PM PDT 24 | 9861079777 ps | ||
| T2809 | /workspace/coverage/cover_reg_top/85.xbar_access_same_device_slow_rsp.784401515 | Jun 28 08:50:14 PM PDT 24 | Jun 28 09:25:51 PM PDT 24 | 131954780433 ps | ||
| T2810 | /workspace/coverage/cover_reg_top/4.xbar_access_same_device_slow_rsp.1300171640 | Jun 28 08:30:34 PM PDT 24 | Jun 28 08:55:38 PM PDT 24 | 85329179599 ps | ||
| T2811 | /workspace/coverage/cover_reg_top/66.xbar_random_large_delays.2337161778 | Jun 28 08:46:08 PM PDT 24 | Jun 28 09:04:50 PM PDT 24 | 106224951426 ps | ||
| T843 | /workspace/coverage/cover_reg_top/81.xbar_stress_all_with_reset_error.4064209342 | Jun 28 08:49:50 PM PDT 24 | Jun 28 08:52:59 PM PDT 24 | 601625768 ps | ||
| T2812 | /workspace/coverage/cover_reg_top/26.xbar_smoke.1843343249 | Jun 28 08:38:41 PM PDT 24 | Jun 28 08:38:51 PM PDT 24 | 41093256 ps | ||
| T2813 | /workspace/coverage/cover_reg_top/41.xbar_error_and_unmapped_addr.231648833 | Jun 28 08:42:12 PM PDT 24 | Jun 28 08:42:38 PM PDT 24 | 119953884 ps | ||
| T2814 | /workspace/coverage/cover_reg_top/89.xbar_access_same_device.1453055467 | Jun 28 08:50:38 PM PDT 24 | Jun 28 08:53:33 PM PDT 24 | 3528652728 ps | ||
| T2815 | /workspace/coverage/cover_reg_top/80.xbar_smoke_large_delays.3780132281 | Jun 28 08:49:07 PM PDT 24 | Jun 28 08:50:54 PM PDT 24 | 10152574201 ps | ||
| T2816 | /workspace/coverage/cover_reg_top/33.xbar_stress_all_with_error.3748718233 | Jun 28 08:40:48 PM PDT 24 | Jun 28 08:44:35 PM PDT 24 | 2921496697 ps | ||
| T2817 | /workspace/coverage/cover_reg_top/53.xbar_same_source.2149538899 | Jun 28 08:44:45 PM PDT 24 | Jun 28 08:45:37 PM PDT 24 | 973071843 ps | ||
| T2818 | /workspace/coverage/cover_reg_top/8.xbar_access_same_device_slow_rsp.2240437554 | Jun 28 08:33:32 PM PDT 24 | Jun 28 08:42:43 PM PDT 24 | 31786944218 ps | ||
| T2819 | /workspace/coverage/cover_reg_top/6.xbar_stress_all_with_error.3684547286 | Jun 28 08:31:57 PM PDT 24 | Jun 28 08:36:58 PM PDT 24 | 3406527050 ps | ||
| T2820 | /workspace/coverage/cover_reg_top/65.xbar_stress_all_with_rand_reset.1351776733 | Jun 28 08:46:01 PM PDT 24 | Jun 28 08:51:43 PM PDT 24 | 3460793568 ps | ||
| T2821 | /workspace/coverage/cover_reg_top/78.xbar_stress_all_with_reset_error.3697807626 | Jun 28 08:49:06 PM PDT 24 | Jun 28 08:57:33 PM PDT 24 | 12216397055 ps | ||
| T2822 | /workspace/coverage/cover_reg_top/33.xbar_stress_all.1194084162 | Jun 28 08:40:25 PM PDT 24 | Jun 28 08:46:36 PM PDT 24 | 9068411716 ps | ||
| T2823 | /workspace/coverage/cover_reg_top/28.xbar_random_zero_delays.151949629 | Jun 28 08:39:28 PM PDT 24 | Jun 28 08:40:16 PM PDT 24 | 408913726 ps | ||
| T2824 | /workspace/coverage/cover_reg_top/7.chip_same_csr_outstanding.2609762172 | Jun 28 08:31:56 PM PDT 24 | Jun 28 09:05:54 PM PDT 24 | 16766927261 ps | ||
| T2825 | /workspace/coverage/cover_reg_top/72.xbar_same_source.893894484 | Jun 28 08:47:58 PM PDT 24 | Jun 28 08:48:52 PM PDT 24 | 435814348 ps | ||
| T2826 | /workspace/coverage/cover_reg_top/41.xbar_smoke_zero_delays.1415587674 | Jun 28 08:42:14 PM PDT 24 | Jun 28 08:42:38 PM PDT 24 | 44010555 ps | ||
| T2827 | /workspace/coverage/cover_reg_top/13.xbar_stress_all_with_rand_reset.2812930931 | Jun 28 08:35:39 PM PDT 24 | Jun 28 08:41:26 PM PDT 24 | 1689362189 ps | ||
| T2828 | /workspace/coverage/cover_reg_top/43.xbar_access_same_device_slow_rsp.1689310938 | Jun 28 08:42:19 PM PDT 24 | Jun 28 09:14:07 PM PDT 24 | 108108442767 ps | ||
| T2829 | /workspace/coverage/cover_reg_top/81.xbar_random_slow_rsp.4184207871 | Jun 28 08:49:50 PM PDT 24 | Jun 28 09:03:59 PM PDT 24 | 46314554808 ps | ||
| T2830 | /workspace/coverage/cover_reg_top/68.xbar_error_random.804615528 | Jun 28 08:46:59 PM PDT 24 | Jun 28 08:48:34 PM PDT 24 | 1761423838 ps | ||
| T2831 | /workspace/coverage/cover_reg_top/0.chip_rv_dm_lc_disabled.3116428619 | Jun 28 08:26:59 PM PDT 24 | Jun 28 08:35:21 PM PDT 24 | 12052346634 ps | ||
| T2832 | /workspace/coverage/cover_reg_top/99.xbar_random_slow_rsp.3574140670 | Jun 28 08:52:42 PM PDT 24 | Jun 28 08:58:00 PM PDT 24 | 18584260315 ps | ||
| T2833 | /workspace/coverage/cover_reg_top/37.xbar_smoke_slow_rsp.3624204989 | Jun 28 08:41:07 PM PDT 24 | Jun 28 08:42:25 PM PDT 24 | 4195370394 ps | ||
| T2834 | /workspace/coverage/cover_reg_top/90.xbar_random_slow_rsp.253954211 | Jun 28 08:50:43 PM PDT 24 | Jun 28 08:55:35 PM PDT 24 | 14690399134 ps | ||
| T2835 | /workspace/coverage/cover_reg_top/97.xbar_error_random.4249164856 | Jun 28 08:52:42 PM PDT 24 | Jun 28 08:53:19 PM PDT 24 | 436481608 ps | ||
| T2836 | /workspace/coverage/cover_reg_top/58.xbar_smoke_zero_delays.2924875028 | Jun 28 08:45:17 PM PDT 24 | Jun 28 08:45:51 PM PDT 24 | 47167581 ps | ||
| T2837 | /workspace/coverage/cover_reg_top/24.xbar_random.3728177721 | Jun 28 08:38:39 PM PDT 24 | Jun 28 08:39:28 PM PDT 24 | 417766482 ps | ||
| T2838 | /workspace/coverage/cover_reg_top/3.xbar_access_same_device.2802547762 | Jun 28 08:29:49 PM PDT 24 | Jun 28 08:31:16 PM PDT 24 | 1586796056 ps | ||
| T2839 | /workspace/coverage/cover_reg_top/90.xbar_random_zero_delays.1217962088 | Jun 28 08:50:42 PM PDT 24 | Jun 28 08:51:35 PM PDT 24 | 275558034 ps | ||
| T2840 | /workspace/coverage/cover_reg_top/73.xbar_smoke_large_delays.4219304528 | Jun 28 08:47:58 PM PDT 24 | Jun 28 08:49:33 PM PDT 24 | 7300286836 ps | ||
| T2841 | /workspace/coverage/cover_reg_top/59.xbar_access_same_device_slow_rsp.3267861331 | Jun 28 08:45:30 PM PDT 24 | Jun 28 09:11:57 PM PDT 24 | 97304032674 ps | ||
| T2842 | /workspace/coverage/cover_reg_top/35.xbar_smoke_zero_delays.2932670853 | Jun 28 08:40:24 PM PDT 24 | Jun 28 08:40:35 PM PDT 24 | 45603332 ps | ||
| T2843 | /workspace/coverage/cover_reg_top/63.xbar_stress_all_with_error.2986538190 | Jun 28 08:45:38 PM PDT 24 | Jun 28 08:50:47 PM PDT 24 | 8432200894 ps | ||
| T2844 | /workspace/coverage/cover_reg_top/71.xbar_access_same_device_slow_rsp.1816027373 | Jun 28 08:47:58 PM PDT 24 | Jun 28 09:25:41 PM PDT 24 | 125842805029 ps | ||
| T2845 | /workspace/coverage/cover_reg_top/42.xbar_error_random.2529701634 | Jun 28 08:42:15 PM PDT 24 | Jun 28 08:42:49 PM PDT 24 | 174848098 ps | ||
| T2846 | /workspace/coverage/cover_reg_top/46.xbar_stress_all_with_reset_error.4091009467 | Jun 28 08:42:59 PM PDT 24 | Jun 28 08:48:15 PM PDT 24 | 6477841822 ps | ||
| T2847 | /workspace/coverage/cover_reg_top/53.xbar_stress_all_with_reset_error.2831514447 | Jun 28 08:44:45 PM PDT 24 | Jun 28 08:50:26 PM PDT 24 | 2752792261 ps | ||
| T2848 | /workspace/coverage/cover_reg_top/20.xbar_error_and_unmapped_addr.4187565015 | Jun 28 08:37:29 PM PDT 24 | Jun 28 08:37:49 PM PDT 24 | 70627163 ps | ||
| T2849 | /workspace/coverage/cover_reg_top/90.xbar_smoke_slow_rsp.3563035272 | Jun 28 08:50:43 PM PDT 24 | Jun 28 08:52:41 PM PDT 24 | 5117998314 ps | ||
| T2850 | /workspace/coverage/cover_reg_top/52.xbar_stress_all_with_error.787099776 | Jun 28 08:44:46 PM PDT 24 | Jun 28 08:46:18 PM PDT 24 | 2082057137 ps | ||
| T2851 | /workspace/coverage/cover_reg_top/98.xbar_smoke_slow_rsp.3507623022 | Jun 28 08:52:41 PM PDT 24 | Jun 28 08:54:33 PM PDT 24 | 6339478851 ps | ||
| T2852 | /workspace/coverage/cover_reg_top/54.xbar_stress_all_with_error.63111041 | Jun 28 08:44:47 PM PDT 24 | Jun 28 08:47:04 PM PDT 24 | 1540136405 ps | ||
| T2853 | /workspace/coverage/cover_reg_top/20.xbar_smoke_slow_rsp.937805162 | Jun 28 08:37:28 PM PDT 24 | Jun 28 08:38:59 PM PDT 24 | 4683214278 ps | ||
| T2854 | /workspace/coverage/cover_reg_top/85.xbar_random_zero_delays.1950700856 | Jun 28 08:50:01 PM PDT 24 | Jun 28 08:51:12 PM PDT 24 | 312947628 ps | ||
| T2855 | /workspace/coverage/cover_reg_top/44.xbar_error_random.874029358 | Jun 28 08:42:54 PM PDT 24 | Jun 28 08:44:01 PM PDT 24 | 1336348970 ps | ||
| T2856 | /workspace/coverage/cover_reg_top/83.xbar_same_source.1702560121 | Jun 28 08:49:53 PM PDT 24 | Jun 28 08:51:10 PM PDT 24 | 1637495719 ps | ||
| T2857 | /workspace/coverage/cover_reg_top/31.xbar_random_slow_rsp.1656240647 | Jun 28 08:39:50 PM PDT 24 | Jun 28 08:54:57 PM PDT 24 | 52884968017 ps | ||
| T2858 | /workspace/coverage/cover_reg_top/46.xbar_stress_all_with_rand_reset.1129884980 | Jun 28 08:42:52 PM PDT 24 | Jun 28 08:44:44 PM PDT 24 | 815578872 ps | ||
| T2859 | /workspace/coverage/cover_reg_top/35.xbar_smoke.1479922582 | Jun 28 08:40:29 PM PDT 24 | Jun 28 08:40:41 PM PDT 24 | 242531087 ps | ||
| T2860 | /workspace/coverage/cover_reg_top/57.xbar_smoke.3326668224 | Jun 28 08:45:22 PM PDT 24 | Jun 28 08:45:56 PM PDT 24 | 52028755 ps | ||
| T2861 | /workspace/coverage/cover_reg_top/37.xbar_stress_all_with_error.2403983518 | Jun 28 08:41:06 PM PDT 24 | Jun 28 08:48:39 PM PDT 24 | 11984274406 ps | ||
| T2862 | /workspace/coverage/cover_reg_top/95.xbar_random_slow_rsp.1890499739 | Jun 28 08:51:49 PM PDT 24 | Jun 28 08:53:16 PM PDT 24 | 3985160541 ps | ||
| T2863 | /workspace/coverage/cover_reg_top/20.xbar_random_zero_delays.900883148 | Jun 28 08:37:27 PM PDT 24 | Jun 28 08:38:13 PM PDT 24 | 388794073 ps | ||
| T2864 | /workspace/coverage/cover_reg_top/82.xbar_stress_all_with_error.1499666536 | Jun 28 08:49:45 PM PDT 24 | Jun 28 08:56:29 PM PDT 24 | 9952903388 ps | ||
| T2865 | /workspace/coverage/cover_reg_top/93.xbar_access_same_device_slow_rsp.3725830958 | Jun 28 08:51:27 PM PDT 24 | Jun 28 08:56:01 PM PDT 24 | 14406959895 ps | ||
| T2866 | /workspace/coverage/cover_reg_top/0.chip_csr_aliasing.3493251072 | Jun 28 08:26:17 PM PDT 24 | Jun 28 10:55:16 PM PDT 24 | 69551069822 ps | ||
| T2867 | /workspace/coverage/cover_reg_top/66.xbar_smoke_zero_delays.1853703605 | Jun 28 08:46:03 PM PDT 24 | Jun 28 08:46:24 PM PDT 24 | 35256302 ps | ||
| T2868 | /workspace/coverage/cover_reg_top/26.xbar_access_same_device.3836474894 | Jun 28 08:39:12 PM PDT 24 | Jun 28 08:41:52 PM PDT 24 | 3106392484 ps | ||
| T2869 | /workspace/coverage/cover_reg_top/96.xbar_access_same_device.1025704750 | Jun 28 08:52:11 PM PDT 24 | Jun 28 08:53:46 PM PDT 24 | 1274241350 ps | ||
| T2870 | /workspace/coverage/cover_reg_top/82.xbar_smoke_zero_delays.818477112 | Jun 28 08:49:46 PM PDT 24 | Jun 28 08:50:14 PM PDT 24 | 45986760 ps | ||
| T2871 | /workspace/coverage/cover_reg_top/32.xbar_smoke_slow_rsp.460415871 | Jun 28 08:40:08 PM PDT 24 | Jun 28 08:41:39 PM PDT 24 | 4628681042 ps | ||
| T2872 | /workspace/coverage/cover_reg_top/47.xbar_smoke_slow_rsp.3246815468 | Jun 28 08:42:57 PM PDT 24 | Jun 28 08:44:15 PM PDT 24 | 3492716226 ps | ||
| T2873 | /workspace/coverage/cover_reg_top/93.xbar_random_large_delays.288516853 | Jun 28 08:51:29 PM PDT 24 | Jun 28 08:56:39 PM PDT 24 | 29866165071 ps | ||
| T2874 | /workspace/coverage/cover_reg_top/37.xbar_access_same_device_slow_rsp.2127778422 | Jun 28 08:41:08 PM PDT 24 | Jun 28 09:15:00 PM PDT 24 | 110044671610 ps | ||
| T2875 | /workspace/coverage/cover_reg_top/19.xbar_error_and_unmapped_addr.2306922165 | Jun 28 08:37:07 PM PDT 24 | Jun 28 08:37:31 PM PDT 24 | 86842728 ps | ||
| T2876 | /workspace/coverage/cover_reg_top/89.xbar_random_zero_delays.202660834 | Jun 28 08:50:43 PM PDT 24 | Jun 28 08:51:20 PM PDT 24 | 127291280 ps | ||
| T2877 | /workspace/coverage/cover_reg_top/57.xbar_unmapped_addr.8332566 | Jun 28 08:45:25 PM PDT 24 | Jun 28 08:46:00 PM PDT 24 | 59506548 ps | ||
| T2878 | /workspace/coverage/cover_reg_top/49.xbar_error_random.3584209358 | Jun 28 08:43:15 PM PDT 24 | Jun 28 08:44:15 PM PDT 24 | 1414076799 ps | ||
| T2879 | /workspace/coverage/cover_reg_top/72.xbar_smoke_zero_delays.1495227093 | Jun 28 08:47:58 PM PDT 24 | Jun 28 08:48:26 PM PDT 24 | 46852070 ps | ||
| T2880 | /workspace/coverage/cover_reg_top/60.xbar_access_same_device_slow_rsp.1481318107 | Jun 28 08:45:34 PM PDT 24 | Jun 28 08:50:20 PM PDT 24 | 15468085216 ps | ||
| T2881 | /workspace/coverage/cover_reg_top/21.xbar_access_same_device.2924276970 | Jun 28 08:37:53 PM PDT 24 | Jun 28 08:39:19 PM PDT 24 | 1721710358 ps | ||
| T2882 | /workspace/coverage/cover_reg_top/94.xbar_stress_all_with_reset_error.607846133 | Jun 28 08:51:50 PM PDT 24 | Jun 28 08:52:40 PM PDT 24 | 127969068 ps | ||
| T2883 | /workspace/coverage/cover_reg_top/89.xbar_access_same_device_slow_rsp.3860452130 | Jun 28 08:50:40 PM PDT 24 | Jun 28 09:17:04 PM PDT 24 | 86618119232 ps | ||
| T2884 | /workspace/coverage/cover_reg_top/91.xbar_smoke_zero_delays.1755191525 | Jun 28 08:51:06 PM PDT 24 | Jun 28 08:51:40 PM PDT 24 | 44242975 ps | ||
| T2885 | /workspace/coverage/cover_reg_top/2.chip_rv_dm_lc_disabled.4240113463 | Jun 28 08:28:38 PM PDT 24 | Jun 28 08:38:29 PM PDT 24 | 15938012613 ps | ||
| T652 | /workspace/coverage/cover_reg_top/73.xbar_stress_all_with_error.2123363990 | Jun 28 08:48:01 PM PDT 24 | Jun 28 08:53:28 PM PDT 24 | 8861267887 ps | ||
| T39 | /workspace/coverage/pad_ctrl_test_mode/3.chip_padctrl_attributes.3975077905 | Jun 28 08:53:18 PM PDT 24 | Jun 28 08:58:09 PM PDT 24 | 5465836936 ps | ||
| T40 | /workspace/coverage/pad_ctrl_test_mode/5.chip_padctrl_attributes.3646409706 | Jun 28 08:53:19 PM PDT 24 | Jun 28 08:57:57 PM PDT 24 | 4724322208 ps | ||
| T41 | /workspace/coverage/pad_ctrl_test_mode/2.chip_padctrl_attributes.218621436 | Jun 28 08:53:17 PM PDT 24 | Jun 28 08:58:13 PM PDT 24 | 4537187110 ps | ||
| T181 | /workspace/coverage/pad_ctrl_test_mode/1.chip_padctrl_attributes.499330735 | Jun 28 08:53:16 PM PDT 24 | Jun 28 08:58:11 PM PDT 24 | 5663487548 ps | ||
| T182 | /workspace/coverage/pad_ctrl_test_mode/6.chip_padctrl_attributes.2142305716 | Jun 28 08:53:18 PM PDT 24 | Jun 28 08:58:05 PM PDT 24 | 5763266333 ps | ||
| T183 | /workspace/coverage/pad_ctrl_test_mode/0.chip_padctrl_attributes.361199848 | Jun 28 08:53:16 PM PDT 24 | Jun 28 08:57:10 PM PDT 24 | 5622563814 ps | ||
| T184 | /workspace/coverage/pad_ctrl_test_mode/9.chip_padctrl_attributes.10551965 | Jun 28 08:53:19 PM PDT 24 | Jun 28 08:57:36 PM PDT 24 | 4530934680 ps | ||
| T185 | /workspace/coverage/pad_ctrl_test_mode/4.chip_padctrl_attributes.824620571 | Jun 28 08:53:16 PM PDT 24 | Jun 28 08:58:30 PM PDT 24 | 4564047046 ps | ||
| T186 | /workspace/coverage/pad_ctrl_test_mode/8.chip_padctrl_attributes.2779484947 | Jun 28 08:53:17 PM PDT 24 | Jun 28 08:57:44 PM PDT 24 | 4530074138 ps | ||
| T187 | /workspace/coverage/pad_ctrl_test_mode/7.chip_padctrl_attributes.1831059956 | Jun 28 08:53:17 PM PDT 24 | Jun 28 08:58:05 PM PDT 24 | 5322256407 ps |
| Test location | /workspace/coverage/default/40.chip_sw_all_escalation_resets.4002988025 |
| Short name | T17 |
| Test name | |
| Test status | |
| Simulation time | 4983392680 ps |
| CPU time | 694.41 seconds |
| Started | Jun 28 08:31:46 PM PDT 24 |
| Finished | Jun 28 08:43:31 PM PDT 24 |
| Peak memory | 643368 kb |
| Host | smart-b3d39168-928f-426c-b9af-fbfdec052943 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 4002988025 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.chip_sw_all_escalation_resets.4002988025 |
| Directory | /workspace/40.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/0.chip_jtag_csr_rw.3541268598 |
| Short name | T8 |
| Test name | |
| Test status | |
| Simulation time | 20569876708 ps |
| CPU time | 2418.23 seconds |
| Started | Jun 28 07:52:17 PM PDT 24 |
| Finished | Jun 28 08:32:37 PM PDT 24 |
| Peak memory | 601852 kb |
| Host | smart-74b1916b-6572-483b-aee7-da20cf1035e1 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +csr_rw +create_jtag_riscv_map=1 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3541268598 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_T EST_SEQ=chip_jtag_csr_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.c hip_jtag_csr_rw.3541268598 |
| Directory | /workspace/0.chip_jtag_csr_rw/latest |
| Test location | /workspace/coverage/default/1.chip_plic_all_irqs_0.2233226304 |
| Short name | T253 |
| Test name | |
| Test status | |
| Simulation time | 5626297720 ps |
| CPU time | 1263.24 seconds |
| Started | Jun 28 08:06:41 PM PDT 24 |
| Finished | Jun 28 08:27:46 PM PDT 24 |
| Peak memory | 607136 kb |
| Host | smart-1a332364-08f4-4191-a60a-4d71c4a38f83 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=plic_all_irqs_test_0:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2233226304 -assert nopostproc +UVM_TESTNA ME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 1.chip_plic_all_irqs_0.2233226304 |
| Directory | /workspace/1.chip_plic_all_irqs_0/latest |
| Test location | /workspace/coverage/cover_reg_top/95.xbar_stress_all.99193960 |
| Short name | T72 |
| Test name | |
| Test status | |
| Simulation time | 906718185 ps |
| CPU time | 74.35 seconds |
| Started | Jun 28 08:52:11 PM PDT 24 |
| Finished | Jun 28 08:53:31 PM PDT 24 |
| Peak memory | 575356 kb |
| Host | smart-479f19a2-5496-4ba8-bec3-b3d04f6df3c2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99193960 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 95.xbar_stress_all.99193960 |
| Directory | /workspace/95.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/75.xbar_access_same_device_slow_rsp.765417749 |
| Short name | T791 |
| Test name | |
| Test status | |
| Simulation time | 153577641711 ps |
| CPU time | 2787.7 seconds |
| Started | Jun 28 08:48:21 PM PDT 24 |
| Finished | Jun 28 09:35:07 PM PDT 24 |
| Peak memory | 575428 kb |
| Host | smart-8b32f35b-ce13-44d5-b527-deb46bab098b |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=765417749 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 75.xbar_access_same_d evice_slow_rsp.765417749 |
| Directory | /workspace/75.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/pad_ctrl_test_mode/3.chip_padctrl_attributes.3975077905 |
| Short name | T39 |
| Test name | |
| Test status | |
| Simulation time | 5465836936 ps |
| CPU time | 280.27 seconds |
| Started | Jun 28 08:53:18 PM PDT 24 |
| Finished | Jun 28 08:58:09 PM PDT 24 |
| Peak memory | 640244 kb |
| Host | smart-91a377b3-b34c-41bd-b39b-414336156539 |
| User | root |
| Command | /workspace/pad_ctrl_test_mode/simv +use_otp_image=OtpTypeLcStProd +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3975077905 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TE ST_SEQ=chip_padctrl_attributes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/pad_ctrl_test_mode.vdb -cm_log /dev/ null -cm_name 3.chip_padctrl_attributes.3975077905 |
| Directory | /workspace/3.chip_padctrl_attributes/latest |
| Test location | /workspace/coverage/cover_reg_top/35.xbar_access_same_device_slow_rsp.949683552 |
| Short name | T447 |
| Test name | |
| Test status | |
| Simulation time | 125018797288 ps |
| CPU time | 2080.62 seconds |
| Started | Jun 28 08:40:43 PM PDT 24 |
| Finished | Jun 28 09:15:37 PM PDT 24 |
| Peak memory | 574340 kb |
| Host | smart-5ebe6366-ca5b-4fc0-93fe-946eebb93a19 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=949683552 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.xbar_access_same_d evice_slow_rsp.949683552 |
| Directory | /workspace/35.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/default/1.chip_sw_keymgr_sideload_otbn.3815675801 |
| Short name | T121 |
| Test name | |
| Test status | |
| Simulation time | 15739205140 ps |
| CPU time | 5188.22 seconds |
| Started | Jun 28 08:05:09 PM PDT 24 |
| Finished | Jun 28 09:31:38 PM PDT 24 |
| Peak memory | 609292 kb |
| Host | smart-4f290c94-8f55-4c71-b755-a62d08eb948c |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=20_000_000 +sw_build_device=sim_dv +sw_images=keymgr_sideload_otbn_test:1:new_rules,test_rom:0 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38156 75801 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_keymgr_sideload_otbn.3815675801 |
| Directory | /workspace/1.chip_sw_keymgr_sideload_otbn/latest |
| Test location | /workspace/coverage/cover_reg_top/4.chip_csr_rw.20175261 |
| Short name | T377 |
| Test name | |
| Test status | |
| Simulation time | 4811459938 ps |
| CPU time | 465.33 seconds |
| Started | Jun 28 08:30:50 PM PDT 24 |
| Finished | Jun 28 08:38:37 PM PDT 24 |
| Peak memory | 595124 kb |
| Host | smart-c2967d18-9e52-4c54-8251-fea38c1cecbd |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20175261 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.chip_csr_rw.20175261 |
| Directory | /workspace/4.chip_csr_rw/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_asm_init_prod_end.761080570 |
| Short name | T54 |
| Test name | |
| Test status | |
| Simulation time | 15810237009 ps |
| CPU time | 3617.4 seconds |
| Started | Jun 28 08:12:26 PM PDT 24 |
| Finished | Jun 28 09:12:48 PM PDT 24 |
| Peak memory | 607896 kb |
| Host | smart-08979e89-f1e2-486f-9be2-8e9de3a413cb |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeCustom +sw_test_timeout_ns=20000000 +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_prod _key_0:1:ot_flash_binary,otp_img_e2e_bootstrap_entry_prod_end:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=761080570 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TE ST_SEQ=chip_sw_rom_e2e_asm_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n ame 0.rom_e2e_asm_init_prod_end.761080570 |
| Directory | /workspace/0.rom_e2e_asm_init_prod_end/latest |
| Test location | /workspace/coverage/cover_reg_top/2.xbar_access_same_device_slow_rsp.2074183521 |
| Short name | T563 |
| Test name | |
| Test status | |
| Simulation time | 121825923549 ps |
| CPU time | 2087.86 seconds |
| Started | Jun 28 08:29:11 PM PDT 24 |
| Finished | Jun 28 09:04:17 PM PDT 24 |
| Peak memory | 574376 kb |
| Host | smart-53a71809-c57a-4841-96d6-d6c9c0da459c |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2074183521 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.xbar_access_same_d evice_slow_rsp.2074183521 |
| Directory | /workspace/2.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/11.xbar_access_same_device_slow_rsp.3779107350 |
| Short name | T532 |
| Test name | |
| Test status | |
| Simulation time | 97124513418 ps |
| CPU time | 1684.82 seconds |
| Started | Jun 28 08:34:29 PM PDT 24 |
| Finished | Jun 28 09:02:51 PM PDT 24 |
| Peak memory | 575416 kb |
| Host | smart-3d971656-152c-4698-83ef-baff16b0db6a |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3779107350 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.xbar_access_same_ device_slow_rsp.3779107350 |
| Directory | /workspace/11.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/default/2.chip_sw_lc_walkthrough_prodend.3267113822 |
| Short name | T113 |
| Test name | |
| Test status | |
| Simulation time | 11241944640 ps |
| CPU time | 1227.8 seconds |
| Started | Jun 28 08:17:53 PM PDT 24 |
| Finished | Jun 28 08:38:22 PM PDT 24 |
| Peak memory | 623576 kb |
| Host | smart-596144c6-53d8-43f3-bbe9-e585eab249f7 |
| User | root |
| Command | /workspace/default/simv +flash_program_latency=5 +use_otp_image=OtpTypeLcStRaw +dest_dec_state=DecLcStProdEnd +sw_build_device=sim_dv +sw_images=lc_wa lkthrough_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3267113822 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_walkthrough_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_lc_walkthrough_prodend.3267113822 |
| Directory | /workspace/2.chip_sw_lc_walkthrough_prodend/latest |
| Test location | /workspace/coverage/default/0.chip_sw_sleep_pin_mio_dio_val.2301892530 |
| Short name | T21 |
| Test name | |
| Test status | |
| Simulation time | 2894767306 ps |
| CPU time | 221.76 seconds |
| Started | Jun 28 08:04:02 PM PDT 24 |
| Finished | Jun 28 08:07:46 PM PDT 24 |
| Peak memory | 607244 kb |
| Host | smart-e637e591-7c32-4474-b3ee-115f8f00cee0 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStProd +sw_build_device=sim_dv +sw_images=sleep_pin_mio_dio_val_test:1:new_rules,test_rom:0 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2301 892530 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sleep_pin_mio_dio_val_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_sleep_pin_mio_dio_val.2301892530 |
| Directory | /workspace/0.chip_sw_sleep_pin_mio_dio_val/latest |
| Test location | /workspace/coverage/cover_reg_top/63.xbar_access_same_device_slow_rsp.4024885681 |
| Short name | T784 |
| Test name | |
| Test status | |
| Simulation time | 103674490831 ps |
| CPU time | 1836.72 seconds |
| Started | Jun 28 08:45:38 PM PDT 24 |
| Finished | Jun 28 09:16:42 PM PDT 24 |
| Peak memory | 574368 kb |
| Host | smart-b5c1c4b3-557a-413d-a8e2-57c8db1cdfbd |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4024885681 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 63.xbar_access_same_ device_slow_rsp.4024885681 |
| Directory | /workspace/63.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/18.xbar_access_same_device_slow_rsp.2906961315 |
| Short name | T537 |
| Test name | |
| Test status | |
| Simulation time | 115781882314 ps |
| CPU time | 2158.43 seconds |
| Started | Jun 28 08:37:08 PM PDT 24 |
| Finished | Jun 28 09:13:18 PM PDT 24 |
| Peak memory | 574360 kb |
| Host | smart-f90c4cdb-1c02-455d-9350-22b918ec1c5d |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2906961315 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.xbar_access_same_ device_slow_rsp.2906961315 |
| Directory | /workspace/18.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/default/2.chip_plic_all_irqs_20.4167187838 |
| Short name | T319 |
| Test name | |
| Test status | |
| Simulation time | 4539414584 ps |
| CPU time | 760.24 seconds |
| Started | Jun 28 08:21:34 PM PDT 24 |
| Finished | Jun 28 08:34:15 PM PDT 24 |
| Peak memory | 609172 kb |
| Host | smart-c44c935f-716c-49a0-bbea-f04932d0f194 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=plic_all_irqs_test_20:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4167187838 -assert nopostproc +UVM_TESTN AME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log / dev/null -cm_name 2.chip_plic_all_irqs_20.4167187838 |
| Directory | /workspace/2.chip_plic_all_irqs_20/latest |
| Test location | /workspace/coverage/default/0.chip_sw_rv_core_ibex_address_translation.1641065444 |
| Short name | T302 |
| Test name | |
| Test status | |
| Simulation time | 3490917966 ps |
| CPU time | 289.9 seconds |
| Started | Jun 28 08:02:47 PM PDT 24 |
| Finished | Jun 28 08:07:38 PM PDT 24 |
| Peak memory | 609184 kb |
| Host | smart-b4b86b2c-da05-42ec-9b87-24ef94cf840a |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=7_000_000 +sw_build_device=sim_dv +sw_images=rv_core_ibex_address_translation_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=1641065444 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_rv_core_ibex_address_translation.1641065444 |
| Directory | /workspace/0.chip_sw_rv_core_ibex_address_translation/latest |
| Test location | /workspace/coverage/default/2.chip_sw_pwrmgr_deep_sleep_all_wake_ups.3677851898 |
| Short name | T1 |
| Test name | |
| Test status | |
| Simulation time | 25217200872 ps |
| CPU time | 1460.81 seconds |
| Started | Jun 28 08:22:59 PM PDT 24 |
| Finished | Jun 28 08:47:24 PM PDT 24 |
| Peak memory | 608712 kb |
| Host | smart-dac9b769-8fc1-4217-976e-a4668896067e |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=pwrmgr_deep_sleep_all_wake_ups:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 3677851898 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_pwrmgr_deep_sleep_all_wake_ups_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_deep_sleep_all_wake_ups.3677851898 |
| Directory | /workspace/2.chip_sw_pwrmgr_deep_sleep_all_wake_ups/latest |
| Test location | /workspace/coverage/cover_reg_top/17.xbar_stress_all_with_reset_error.716457461 |
| Short name | T247 |
| Test name | |
| Test status | |
| Simulation time | 936716676 ps |
| CPU time | 188.03 seconds |
| Started | Jun 28 08:36:50 PM PDT 24 |
| Finished | Jun 28 08:40:22 PM PDT 24 |
| Peak memory | 577404 kb |
| Host | smart-4dab4447-b90c-4a6d-b903-2ddacfa0977a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=716457461 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.xbar_stress_all _with_reset_error.716457461 |
| Directory | /workspace/17.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/default/1.chip_sw_gpio.633080103 |
| Short name | T27 |
| Test name | |
| Test status | |
| Simulation time | 3285951970 ps |
| CPU time | 453.08 seconds |
| Started | Jun 28 08:06:42 PM PDT 24 |
| Finished | Jun 28 08:14:18 PM PDT 24 |
| Peak memory | 606992 kb |
| Host | smart-aa678152-c198-4ade-ad4f-646ccedfb7d2 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=gpio_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=633080103 -assert nopostproc +UVM_TESTNAME=chip_base _test +UVM_TEST_SEQ=chip_sw_gpio_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 1.chip_sw_gpio.633080103 |
| Directory | /workspace/1.chip_sw_gpio/latest |
| Test location | /workspace/coverage/cover_reg_top/6.chip_tl_errors.3219242488 |
| Short name | T543 |
| Test name | |
| Test status | |
| Simulation time | 4787097510 ps |
| CPU time | 681.15 seconds |
| Started | Jun 28 08:31:36 PM PDT 24 |
| Finished | Jun 28 08:43:10 PM PDT 24 |
| Peak memory | 597444 kb |
| Host | smart-96214701-0222-462e-80fa-04e796aa51ea |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3219242488 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.chip_tl_errors.3219242488 |
| Directory | /workspace/6.chip_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/9.xbar_access_same_device_slow_rsp.1178779485 |
| Short name | T588 |
| Test name | |
| Test status | |
| Simulation time | 158110857489 ps |
| CPU time | 2605.08 seconds |
| Started | Jun 28 08:34:07 PM PDT 24 |
| Finished | Jun 28 09:17:43 PM PDT 24 |
| Peak memory | 574392 kb |
| Host | smart-c23f787d-1a8b-4ae3-8865-3527f7ad05e6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1178779485 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.xbar_access_same_d evice_slow_rsp.1178779485 |
| Directory | /workspace/9.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/default/2.chip_jtag_csr_rw.2828157847 |
| Short name | T78 |
| Test name | |
| Test status | |
| Simulation time | 12545935714 ps |
| CPU time | 1600.86 seconds |
| Started | Jun 28 08:13:34 PM PDT 24 |
| Finished | Jun 28 08:40:21 PM PDT 24 |
| Peak memory | 605332 kb |
| Host | smart-2a684e86-b14e-4a86-8adf-f6578b14ee42 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +csr_rw +create_jtag_riscv_map=1 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2828157847 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_T EST_SEQ=chip_jtag_csr_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.c hip_jtag_csr_rw.2828157847 |
| Directory | /workspace/2.chip_jtag_csr_rw/latest |
| Test location | /workspace/coverage/default/56.chip_sw_alert_handler_lpg_sleep_mode_alerts.3718709422 |
| Short name | T18 |
| Test name | |
| Test status | |
| Simulation time | 4439531102 ps |
| CPU time | 458.76 seconds |
| Started | Jun 28 08:29:17 PM PDT 24 |
| Finished | Jun 28 08:37:09 PM PDT 24 |
| Peak memory | 647220 kb |
| Host | smart-0becf001-75f0-44b9-87d0-ea7e752690cb |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3718709422 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.chip_ sw_alert_handler_lpg_sleep_mode_alerts.3718709422 |
| Directory | /workspace/56.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/cover_reg_top/50.xbar_access_same_device_slow_rsp.2318706377 |
| Short name | T559 |
| Test name | |
| Test status | |
| Simulation time | 140282481560 ps |
| CPU time | 2482.22 seconds |
| Started | Jun 28 08:43:14 PM PDT 24 |
| Finished | Jun 28 09:24:43 PM PDT 24 |
| Peak memory | 575448 kb |
| Host | smart-dfd76c2d-6370-440c-9462-c342ffa7c413 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2318706377 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 50.xbar_access_same_ device_slow_rsp.2318706377 |
| Directory | /workspace/50.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/10.chip_same_csr_outstanding.365354823 |
| Short name | T378 |
| Test name | |
| Test status | |
| Simulation time | 28574422527 ps |
| CPU time | 4666.6 seconds |
| Started | Jun 28 08:34:00 PM PDT 24 |
| Finished | Jun 28 09:51:55 PM PDT 24 |
| Peak memory | 592100 kb |
| Host | smart-22e6dc8e-2ab4-44dd-a178-2a2c5f9301aa |
| User | root |
| Command | /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +run_same_csr_outstanding +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=365354823 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c m_log /dev/null -cm_name 10.chip_same_csr_outstanding.365354823 |
| Directory | /workspace/10.chip_same_csr_outstanding/latest |
| Test location | /workspace/coverage/default/0.chip_sw_edn_entropy_reqs_jitter.977952737 |
| Short name | T110 |
| Test name | |
| Test status | |
| Simulation time | 7204855135 ps |
| CPU time | 1270.9 seconds |
| Started | Jun 28 07:59:51 PM PDT 24 |
| Finished | Jun 28 08:21:04 PM PDT 24 |
| Peak memory | 609328 kb |
| Host | smart-04b5f823-2ef2-406f-b9b0-aae86e585dbd |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=15000000 +rng_srate_value_min=15 +rng_srate_value_max=30 +en_jitter=1 +sw_build_device=sim_dv +sw_images=e ntropy_src_edn_reqs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=977952737 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_edn_entropy_reqs_jitter.977952737 |
| Directory | /workspace/0.chip_sw_edn_entropy_reqs_jitter/latest |
| Test location | /workspace/coverage/default/2.chip_sw_alert_handler_lpg_sleep_mode_pings.1778233307 |
| Short name | T83 |
| Test name | |
| Test status | |
| Simulation time | 10692299370 ps |
| CPU time | 1427.31 seconds |
| Started | Jun 28 08:20:58 PM PDT 24 |
| Finished | Jun 28 08:44:58 PM PDT 24 |
| Peak memory | 608864 kb |
| Host | smart-c818b5e7-0d13-4667-ba12-4c1d751c00a1 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=alert_handler _lpg_sleep_mode_pings_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1778233307 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_alert_han dler_shorten_ping_wait_cycle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_alert_handler_lpg_sleep_mode_pings.1778233307 |
| Directory | /workspace/2.chip_sw_alert_handler_lpg_sleep_mode_pings/latest |
| Test location | /workspace/coverage/default/2.chip_plic_all_irqs_10.496472061 |
| Short name | T148 |
| Test name | |
| Test status | |
| Simulation time | 3529917312 ps |
| CPU time | 693.08 seconds |
| Started | Jun 28 08:20:47 PM PDT 24 |
| Finished | Jun 28 08:32:27 PM PDT 24 |
| Peak memory | 607132 kb |
| Host | smart-bfcbf8e7-936b-456b-aa26-12ae7e6f5695 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=plic_all_irqs_test_10:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=496472061 -assert nopostproc +UVM_TESTNA ME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 2.chip_plic_all_irqs_10.496472061 |
| Directory | /workspace/2.chip_plic_all_irqs_10/latest |
| Test location | /workspace/coverage/cover_reg_top/29.xbar_stress_all_with_error.269158479 |
| Short name | T516 |
| Test name | |
| Test status | |
| Simulation time | 9613043366 ps |
| CPU time | 338.75 seconds |
| Started | Jun 28 08:39:40 PM PDT 24 |
| Finished | Jun 28 08:45:24 PM PDT 24 |
| Peak memory | 574664 kb |
| Host | smart-f9680c64-c80a-4803-9111-777c774972bd |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=269158479 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.xbar_stress_all_with_error.269158479 |
| Directory | /workspace/29.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/default/0.chip_sw_exit_test_unlocked_bootstrap.188756077 |
| Short name | T75 |
| Test name | |
| Test status | |
| Simulation time | 58160032883 ps |
| CPU time | 11271.3 seconds |
| Started | Jun 28 08:00:58 PM PDT 24 |
| Finished | Jun 28 11:08:52 PM PDT 24 |
| Peak memory | 623468 kb |
| Host | smart-b899e244-c947-4861-b003-0bee5a128fbd |
| User | root |
| Command | /workspace/default/simv +flash_program_latency=5 +sw_test_timeout_ns=150_000_000 +sw_build_device=sim_dv +sw_images=exit_test_unlocked_bootstrap:1:new _rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/s im.tcl +ntb_random_seed=188756077 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_exit_test_unlocked_bootstrap_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_exit_test_unlocked_bootstrap.188756077 |
| Directory | /workspace/0.chip_sw_exit_test_unlocked_bootstrap/latest |
| Test location | /workspace/coverage/cover_reg_top/72.xbar_stress_all.2359783142 |
| Short name | T440 |
| Test name | |
| Test status | |
| Simulation time | 4561763787 ps |
| CPU time | 418.75 seconds |
| Started | Jun 28 08:47:58 PM PDT 24 |
| Finished | Jun 28 08:55:18 PM PDT 24 |
| Peak memory | 575444 kb |
| Host | smart-f6a1afeb-2044-468f-a430-776998c3aabf |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2359783142 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 72.xbar_stress_all.2359783142 |
| Directory | /workspace/72.xbar_stress_all/latest |
| Test location | /workspace/coverage/default/0.chip_sw_lc_walkthrough_dev.1819739911 |
| Short name | T162 |
| Test name | |
| Test status | |
| Simulation time | 50109119732 ps |
| CPU time | 5866.68 seconds |
| Started | Jun 28 08:05:29 PM PDT 24 |
| Finished | Jun 28 09:43:18 PM PDT 24 |
| Peak memory | 617336 kb |
| Host | smart-7f713675-26b0-47e6-874f-e343705f2168 |
| User | root |
| Command | /workspace/default/simv +flash_program_latency=5 +use_otp_image=OtpTypeLcStRaw +dest_dec_state=DecLcStDev +sw_test_timeout_ns=200_000_000 +sw_build_de vice=sim_dv +sw_images=lc_walkthrough_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1819739911 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=c hip_sw_lc_walkthrough_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip _sw_lc_walkthrough_dev.1819739911 |
| Directory | /workspace/0.chip_sw_lc_walkthrough_dev/latest |
| Test location | /workspace/coverage/default/1.chip_sw_sysrst_ctrl_reset.1647424547 |
| Short name | T31 |
| Test name | |
| Test status | |
| Simulation time | 24141462536 ps |
| CPU time | 2289.43 seconds |
| Started | Jun 28 08:04:40 PM PDT 24 |
| Finished | Jun 28 08:42:52 PM PDT 24 |
| Peak memory | 611588 kb |
| Host | smart-d8ba56c8-71f1-4089-b514-1fb0a2aa7e9a |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=36_000_000 +sw_build_device=sim_dv +sw_images=sysrst_ctrl_reset_test:1:new_rules,test_rom:0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16474245 47 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_sysrst_ctrl_reset.1647424547 |
| Directory | /workspace/1.chip_sw_sysrst_ctrl_reset/latest |
| Test location | /workspace/coverage/default/0.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup.1880395165 |
| Short name | T125 |
| Test name | |
| Test status | |
| Simulation time | 5578799256 ps |
| CPU time | 564.04 seconds |
| Started | Jun 28 08:01:21 PM PDT 24 |
| Finished | Jun 28 08:10:47 PM PDT 24 |
| Peak memory | 609236 kb |
| Host | smart-3c215c06-c118-42fa-9924-bd932cc853cc |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=8_000_000 +sw_build_device=sim_dv +sw_images=sensor_ctrl_wakeup_test:1:new_rules,test_rom:0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18803951 65 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac e/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup.1880395165 |
| Directory | /workspace/0.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup/latest |
| Test location | /workspace/coverage/default/2.chip_sw_rstmgr_alert_info.3788223067 |
| Short name | T147 |
| Test name | |
| Test status | |
| Simulation time | 12544769412 ps |
| CPU time | 1807.18 seconds |
| Started | Jun 28 08:16:34 PM PDT 24 |
| Finished | Jun 28 08:46:43 PM PDT 24 |
| Peak memory | 608616 kb |
| Host | smart-87052bc5-995a-4eb3-9b53-633bcc8da7f6 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=30_000_000 +en_scb_tl_err_chk=0 +sw_build_device=sim_dv +sw_images=rstmgr_alert_info_test:1:new_rules,test _rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb _random_seed=3788223067 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_rstmgr_alert_info.3788223067 |
| Directory | /workspace/2.chip_sw_rstmgr_alert_info/latest |
| Test location | /workspace/coverage/default/2.chip_sw_sleep_pin_mio_dio_val.4170653254 |
| Short name | T23 |
| Test name | |
| Test status | |
| Simulation time | 2694834150 ps |
| CPU time | 293.42 seconds |
| Started | Jun 28 08:15:11 PM PDT 24 |
| Finished | Jun 28 08:20:05 PM PDT 24 |
| Peak memory | 607252 kb |
| Host | smart-26a0665f-b9a5-4ef3-b348-d7e4e620122c |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStProd +sw_build_device=sim_dv +sw_images=sleep_pin_mio_dio_val_test:1:new_rules,test_rom:0 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4170 653254 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sleep_pin_mio_dio_val_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_sleep_pin_mio_dio_val.4170653254 |
| Directory | /workspace/2.chip_sw_sleep_pin_mio_dio_val/latest |
| Test location | /workspace/coverage/cover_reg_top/53.xbar_random_large_delays.165654302 |
| Short name | T491 |
| Test name | |
| Test status | |
| Simulation time | 84203515694 ps |
| CPU time | 835.62 seconds |
| Started | Jun 28 08:44:49 PM PDT 24 |
| Finished | Jun 28 08:59:04 PM PDT 24 |
| Peak memory | 574252 kb |
| Host | smart-3576347b-a267-418d-93f9-5925428ad3d8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=165654302 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 53.xbar_random_large_delays.165654302 |
| Directory | /workspace/53.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/31.xbar_access_same_device.204667033 |
| Short name | T449 |
| Test name | |
| Test status | |
| Simulation time | 2786447997 ps |
| CPU time | 147.84 seconds |
| Started | Jun 28 08:40:08 PM PDT 24 |
| Finished | Jun 28 08:42:47 PM PDT 24 |
| Peak memory | 575228 kb |
| Host | smart-65f95c6f-495d-4dfb-99ef-8481defbc2e1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=204667033 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.xbar_access_same_device. 204667033 |
| Directory | /workspace/31.xbar_access_same_device/latest |
| Test location | /workspace/coverage/default/2.chip_sw_flash_init.1539136625 |
| Short name | T19 |
| Test name | |
| Test status | |
| Simulation time | 19324603388 ps |
| CPU time | 2011.4 seconds |
| Started | Jun 28 08:15:59 PM PDT 24 |
| Finished | Jun 28 08:49:34 PM PDT 24 |
| Peak memory | 611732 kb |
| Host | smart-aae3e530-387c-464c-bd12-f426957210ae |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=25_000_000 +sw_build_device=sim_dv +sw_images=flash_init_test:0:test_in_rom:new_rules +cdc_instrumentation _enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1539136625 -as sert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_flash_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac e/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_flash_init.1539136625 |
| Directory | /workspace/2.chip_sw_flash_init/latest |
| Test location | /workspace/coverage/default/0.chip_sw_otp_ctrl_escalation.2026025443 |
| Short name | T159 |
| Test name | |
| Test status | |
| Simulation time | 5079776110 ps |
| CPU time | 583.82 seconds |
| Started | Jun 28 08:03:45 PM PDT 24 |
| Finished | Jun 28 08:13:31 PM PDT 24 |
| Peak memory | 608864 kb |
| Host | smart-d726675a-4832-400b-9c52-82927e846f9e |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 2026025443 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_otp_ctrl_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_otp_ctrl_escalation.2026025443 |
| Directory | /workspace/0.chip_sw_otp_ctrl_escalation/latest |
| Test location | /workspace/coverage/cover_reg_top/59.xbar_stress_all_with_reset_error.3217681818 |
| Short name | T818 |
| Test name | |
| Test status | |
| Simulation time | 6351853285 ps |
| CPU time | 290.81 seconds |
| Started | Jun 28 08:45:31 PM PDT 24 |
| Finished | Jun 28 08:50:50 PM PDT 24 |
| Peak memory | 576432 kb |
| Host | smart-1af0c595-854b-4ce5-a7bf-5d80c76cd68d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3217681818 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 59.xbar_stress_al l_with_reset_error.3217681818 |
| Directory | /workspace/59.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/default/1.chip_sw_sleep_pin_mio_dio_val.3562434069 |
| Short name | T22 |
| Test name | |
| Test status | |
| Simulation time | 3357826885 ps |
| CPU time | 298.57 seconds |
| Started | Jun 28 08:05:56 PM PDT 24 |
| Finished | Jun 28 08:10:57 PM PDT 24 |
| Peak memory | 608404 kb |
| Host | smart-39d39ae6-f92a-4822-bf18-7a542abe5d8b |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStProd +sw_build_device=sim_dv +sw_images=sleep_pin_mio_dio_val_test:1:new_rules,test_rom:0 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3562 434069 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sleep_pin_mio_dio_val_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_sleep_pin_mio_dio_val.3562434069 |
| Directory | /workspace/1.chip_sw_sleep_pin_mio_dio_val/latest |
| Test location | /workspace/coverage/cover_reg_top/29.chip_tl_errors.3970417420 |
| Short name | T542 |
| Test name | |
| Test status | |
| Simulation time | 3803887448 ps |
| CPU time | 363.14 seconds |
| Started | Jun 28 08:39:32 PM PDT 24 |
| Finished | Jun 28 08:45:44 PM PDT 24 |
| Peak memory | 603492 kb |
| Host | smart-26cc8c48-8c61-4b54-813d-9fa63699991c |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3970417420 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.chip_tl_errors.3970417420 |
| Directory | /workspace/29.chip_tl_errors/latest |
| Test location | /workspace/coverage/default/1.chip_sw_csrng_lc_hw_debug_en_test.406003444 |
| Short name | T175 |
| Test name | |
| Test status | |
| Simulation time | 7879661433 ps |
| CPU time | 738.9 seconds |
| Started | Jun 28 08:02:44 PM PDT 24 |
| Finished | Jun 28 08:15:04 PM PDT 24 |
| Peak memory | 608920 kb |
| Host | smart-2490d5dd-a5f0-4bd0-8eac-68e4bab57e1b |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=15_000_000 +rng_srate_value_min=15 +use_otp_image=OtpTypeLcStTestUnlocked0 +sw_build_device=sim_dv +sw_ima ges=csrng_lc_hw_debug_en_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=406003444 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_csrng_l c_hw_debug_en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_csrn g_lc_hw_debug_en_test.406003444 |
| Directory | /workspace/1.chip_sw_csrng_lc_hw_debug_en_test/latest |
| Test location | /workspace/coverage/default/0.chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq.4141305799 |
| Short name | T170 |
| Test name | |
| Test status | |
| Simulation time | 5598700464 ps |
| CPU time | 847.51 seconds |
| Started | Jun 28 08:08:29 PM PDT 24 |
| Finished | Jun 28 08:22:38 PM PDT 24 |
| Peak memory | 608888 kb |
| Host | smart-60120c9e-bd6b-4ca0-ab1b-aa11b247b472 |
| User | root |
| Command | /workspace/default/simv +mem_sel=main +sw_test_timeout_ns=12_000_000 +bypass_alert_ready_to_end_check=1 +en_jitter=1 +en_scb_tl_err_chk=0 +cal_sys_clk _70mhz=1 +sw_build_device=sim_dv +sw_images=sram_ctrl_scrambled_access_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4141305799 -assert nopostproc +UVM_TESTNA ME=chip_base_test +UVM_TEST_SEQ=chip_sw_sram_ctrl_scrambled_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/ default.vdb -cm_log /dev/null -cm_name 0.chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq.4141305799 |
| Directory | /workspace/0.chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq/latest |
| Test location | /workspace/coverage/default/17.chip_sw_uart_rand_baudrate.2502969167 |
| Short name | T177 |
| Test name | |
| Test status | |
| Simulation time | 3980277300 ps |
| CPU time | 695.53 seconds |
| Started | Jun 28 08:26:10 PM PDT 24 |
| Finished | Jun 28 08:37:56 PM PDT 24 |
| Peak memory | 618572 kb |
| Host | smart-8d475b86-24e2-44f5-9355-23ddb010b338 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=2502969167 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.chip_sw_uart_rand_baudrate.2502969167 |
| Directory | /workspace/17.chip_sw_uart_rand_baudrate/latest |
| Test location | /workspace/coverage/default/0.chip_sw_spi_host_tx_rx.1798969969 |
| Short name | T44 |
| Test name | |
| Test status | |
| Simulation time | 3347069664 ps |
| CPU time | 273.13 seconds |
| Started | Jun 28 08:03:01 PM PDT 24 |
| Finished | Jun 28 08:07:35 PM PDT 24 |
| Peak memory | 607992 kb |
| Host | smart-1d0d847e-dded-4477-ac4d-6f3281490c23 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=spi_host_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1798969969 -assert nopostproc +UVM_TESTNAM E=chip_base_test +UVM_TEST_SEQ=chip_sw_spi_host_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb - cm_log /dev/null -cm_name 0.chip_sw_spi_host_tx_rx.1798969969 |
| Directory | /workspace/0.chip_sw_spi_host_tx_rx/latest |
| Test location | /workspace/coverage/default/0.chip_sw_alert_test.2478829960 |
| Short name | T58 |
| Test name | |
| Test status | |
| Simulation time | 3339302740 ps |
| CPU time | 351.85 seconds |
| Started | Jun 28 08:06:39 PM PDT 24 |
| Finished | Jun 28 08:12:33 PM PDT 24 |
| Peak memory | 607148 kb |
| Host | smart-bd64304d-2ec7-4b8c-a106-fcca14d0acbf |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=alert_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2478829960 -assert nopostproc +UVM_TESTNAME=chip_ba se_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 0.chip_sw_alert_test.2478829960 |
| Directory | /workspace/0.chip_sw_alert_test/latest |
| Test location | /workspace/coverage/default/1.chip_sw_entropy_src_csrng.3266660231 |
| Short name | T117 |
| Test name | |
| Test status | |
| Simulation time | 6252465760 ps |
| CPU time | 1256.81 seconds |
| Started | Jun 28 08:07:46 PM PDT 24 |
| Finished | Jun 28 08:28:43 PM PDT 24 |
| Peak memory | 608104 kb |
| Host | smart-8158c435-0e69-4067-98bc-2749a2c8b733 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=50_000_000 +rng_srate_value_min=15 +rng_srate_value_max=30 +sw_build_device=sim_dv +sw_images=entropy_src_ csrng_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3266660231 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_entropy_src_csrng.3266660231 |
| Directory | /workspace/1.chip_sw_entropy_src_csrng/latest |
| Test location | /workspace/coverage/default/35.chip_sw_all_escalation_resets.1650678314 |
| Short name | T309 |
| Test name | |
| Test status | |
| Simulation time | 4874235072 ps |
| CPU time | 774.63 seconds |
| Started | Jun 28 08:29:27 PM PDT 24 |
| Finished | Jun 28 08:42:28 PM PDT 24 |
| Peak memory | 643636 kb |
| Host | smart-953648eb-e403-42fa-b4ce-cd4ce0e96f44 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 1650678314 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.chip_sw_all_escalation_resets.1650678314 |
| Directory | /workspace/35.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/1.chip_sw_sleep_pin_retention.1534342110 |
| Short name | T12 |
| Test name | |
| Test status | |
| Simulation time | 4418173472 ps |
| CPU time | 337.78 seconds |
| Started | Jun 28 08:03:38 PM PDT 24 |
| Finished | Jun 28 08:09:18 PM PDT 24 |
| Peak memory | 608208 kb |
| Host | smart-68b62e9d-9472-43a9-b677-9e2498479bb2 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=sleep_pin_retention_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1534342110 -assert nopostproc +UVM_TE STNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sleep_pin_retention_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def ault.vdb -cm_log /dev/null -cm_name 1.chip_sw_sleep_pin_retention.1534342110 |
| Directory | /workspace/1.chip_sw_sleep_pin_retention/latest |
| Test location | /workspace/coverage/default/19.chip_sw_all_escalation_resets.4228220083 |
| Short name | T241 |
| Test name | |
| Test status | |
| Simulation time | 4985630522 ps |
| CPU time | 553.15 seconds |
| Started | Jun 28 08:26:24 PM PDT 24 |
| Finished | Jun 28 08:35:41 PM PDT 24 |
| Peak memory | 643732 kb |
| Host | smart-f9e0040a-e1d7-4853-8cb4-5e03b40d1207 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 4228220083 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.chip_sw_all_escalation_resets.4228220083 |
| Directory | /workspace/19.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/cover_reg_top/37.xbar_stress_all_with_rand_reset.4272571254 |
| Short name | T470 |
| Test name | |
| Test status | |
| Simulation time | 11910127271 ps |
| CPU time | 638.81 seconds |
| Started | Jun 28 08:41:08 PM PDT 24 |
| Finished | Jun 28 08:51:50 PM PDT 24 |
| Peak memory | 575444 kb |
| Host | smart-7cd74f0e-84a1-414f-81f9-004c128ec31e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4272571254 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.xbar_stress_all _with_rand_reset.4272571254 |
| Directory | /workspace/37.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/1.chip_sw_kmac_idle.4099374180 |
| Short name | T862 |
| Test name | |
| Test status | |
| Simulation time | 2670686184 ps |
| CPU time | 284.08 seconds |
| Started | Jun 28 08:09:24 PM PDT 24 |
| Finished | Jun 28 08:14:10 PM PDT 24 |
| Peak memory | 606368 kb |
| Host | smart-e72c8fa8-06d4-427a-b045-0d8b5350e728 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=kmac_idle_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4099374180 -assert nopostproc +UVM_TESTNAME=chi p_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul l -cm_name 1.chip_sw_kmac_idle.4099374180 |
| Directory | /workspace/1.chip_sw_kmac_idle/latest |
| Test location | /workspace/coverage/default/2.chip_sw_data_integrity_escalation.982614471 |
| Short name | T266 |
| Test name | |
| Test status | |
| Simulation time | 5346310224 ps |
| CPU time | 1049.19 seconds |
| Started | Jun 28 08:14:16 PM PDT 24 |
| Finished | Jun 28 08:31:46 PM PDT 24 |
| Peak memory | 609272 kb |
| Host | smart-2d4e543d-cafa-4c53-856e-b6ef082d0095 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=data_integrity_escalation_reset_test:1:new_rules,test_ro m:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=982614471 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_data_integrity_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_data_integrity_escalation.982614471 |
| Directory | /workspace/2.chip_sw_data_integrity_escalation/latest |
| Test location | /workspace/coverage/default/42.chip_sw_all_escalation_resets.1352936444 |
| Short name | T84 |
| Test name | |
| Test status | |
| Simulation time | 5088712076 ps |
| CPU time | 950.51 seconds |
| Started | Jun 28 08:28:35 PM PDT 24 |
| Finished | Jun 28 08:44:33 PM PDT 24 |
| Peak memory | 643976 kb |
| Host | smart-be8b407f-0bef-4d19-a78c-30c27d82283f |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 1352936444 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.chip_sw_all_escalation_resets.1352936444 |
| Directory | /workspace/42.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/40.chip_sw_alert_handler_lpg_sleep_mode_alerts.3699741967 |
| Short name | T246 |
| Test name | |
| Test status | |
| Simulation time | 3242866766 ps |
| CPU time | 430.03 seconds |
| Started | Jun 28 08:28:41 PM PDT 24 |
| Finished | Jun 28 08:36:10 PM PDT 24 |
| Peak memory | 642224 kb |
| Host | smart-e2bdb253-e04d-4052-bcd3-f07e8fca479c |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3699741967 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.chip_ sw_alert_handler_lpg_sleep_mode_alerts.3699741967 |
| Directory | /workspace/40.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/0.chip_sw_lc_ctrl_rma_to_scrap.2589586624 |
| Short name | T60 |
| Test name | |
| Test status | |
| Simulation time | 3162758724 ps |
| CPU time | 300.87 seconds |
| Started | Jun 28 08:03:14 PM PDT 24 |
| Finished | Jun 28 08:08:18 PM PDT 24 |
| Peak memory | 617808 kb |
| Host | smart-8eb48f87-f6b2-4015-8e17-8588b239688d |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +src_dec_state=DecLcStRma +sw_build_device=sim_dv +sw_images=lc_ctrl_scrap_test:1:new_rules ,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2589586624 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_scrap_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_lc_ctrl_rma_to_scrap.2589586624 |
| Directory | /workspace/0.chip_sw_lc_ctrl_rma_to_scrap/latest |
| Test location | /workspace/coverage/default/0.chip_plic_all_irqs_0.1743715798 |
| Short name | T322 |
| Test name | |
| Test status | |
| Simulation time | 6829940980 ps |
| CPU time | 1111.5 seconds |
| Started | Jun 28 08:01:59 PM PDT 24 |
| Finished | Jun 28 08:20:31 PM PDT 24 |
| Peak memory | 607132 kb |
| Host | smart-553e1c86-3bd1-4f44-83fa-a2357a5336ca |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=plic_all_irqs_test_0:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1743715798 -assert nopostproc +UVM_TESTNA ME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 0.chip_plic_all_irqs_0.1743715798 |
| Directory | /workspace/0.chip_plic_all_irqs_0/latest |
| Test location | /workspace/coverage/cover_reg_top/1.chip_csr_hw_reset.2755343568 |
| Short name | T127 |
| Test name | |
| Test status | |
| Simulation time | 7289196712 ps |
| CPU time | 532.82 seconds |
| Started | Jun 28 08:28:41 PM PDT 24 |
| Finished | Jun 28 08:37:52 PM PDT 24 |
| Peak memory | 660496 kb |
| Host | smart-bef4ce64-03b0-4ed6-9889-49d55aa24cba |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2755343568 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.chip_csr_hw_r eset.2755343568 |
| Directory | /workspace/1.chip_csr_hw_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/67.xbar_stress_all_with_rand_reset.1295897858 |
| Short name | T454 |
| Test name | |
| Test status | |
| Simulation time | 2775836401 ps |
| CPU time | 401.66 seconds |
| Started | Jun 28 08:46:57 PM PDT 24 |
| Finished | Jun 28 08:54:10 PM PDT 24 |
| Peak memory | 575544 kb |
| Host | smart-46ca9668-ab4b-431f-85c5-02111cf5f939 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1295897858 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 67.xbar_stress_all _with_rand_reset.1295897858 |
| Directory | /workspace/67.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/2.chip_sw_rv_core_ibex_lockstep_glitch.1502160235 |
| Short name | T284 |
| Test name | |
| Test status | |
| Simulation time | 2504755608 ps |
| CPU time | 320.79 seconds |
| Started | Jun 28 08:22:39 PM PDT 24 |
| Finished | Jun 28 08:28:02 PM PDT 24 |
| Peak memory | 613464 kb |
| Host | smart-384cd30b-0b5f-4953-9fd1-93221e95c446 |
| User | root |
| Command | /workspace/default/simv +disable_assert_final_checks +sw_build_device=sim_dv +sw_images=aes_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1502160235 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rv_core_ibex_lockstep_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_rv_core_ibex_lockstep_glitch.1502160235 |
| Directory | /workspace/2.chip_sw_rv_core_ibex_lockstep_glitch/latest |
| Test location | /workspace/coverage/default/0.chip_sw_flash_rma_unlocked.1315794785 |
| Short name | T176 |
| Test name | |
| Test status | |
| Simulation time | 43693080168 ps |
| CPU time | 5262.29 seconds |
| Started | Jun 28 08:04:34 PM PDT 24 |
| Finished | Jun 28 09:32:18 PM PDT 24 |
| Peak memory | 617700 kb |
| Host | smart-0ead249a-f6d6-4c28-98df-10529366401b |
| User | root |
| Command | /workspace/default/simv +flash_program_latency=5 +sw_test_timeout_ns=150_000_000 +sw_build_device=sim_dv +sw_images=flash_rma_unlocked_test:0:test_in_ rom:new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t cl +ntb_random_seed=1315794785 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_flash_rma_unlocked_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_flash_rma_unlocked.1315794785 |
| Directory | /workspace/0.chip_sw_flash_rma_unlocked/latest |
| Test location | /workspace/coverage/cover_reg_top/16.chip_tl_errors.2013221824 |
| Short name | T556 |
| Test name | |
| Test status | |
| Simulation time | 4005542350 ps |
| CPU time | 361.78 seconds |
| Started | Jun 28 08:36:16 PM PDT 24 |
| Finished | Jun 28 08:42:25 PM PDT 24 |
| Peak memory | 597444 kb |
| Host | smart-b5f5a30e-a59b-4a2b-a12f-52e9d5663b6e |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2013221824 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.chip_tl_errors.2013221824 |
| Directory | /workspace/16.chip_tl_errors/latest |
| Test location | /workspace/coverage/default/2.chip_sw_aes_entropy.1041886468 |
| Short name | T373 |
| Test name | |
| Test status | |
| Simulation time | 2732700118 ps |
| CPU time | 245.56 seconds |
| Started | Jun 28 08:18:01 PM PDT 24 |
| Finished | Jun 28 08:22:08 PM PDT 24 |
| Peak memory | 609164 kb |
| Host | smart-af6f9cf4-ada1-4261-8af0-e66b8599e6d6 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=15_000_000 +sw_build_device=sim_dv +sw_images=aes_entropy_test:1:new_rules,test_rom:0 +cdc_instrumentation _enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1041886468 -as sert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove rage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_aes_entropy.1041886468 |
| Directory | /workspace/2.chip_sw_aes_entropy/latest |
| Test location | /workspace/coverage/default/0.chip_sw_sensor_ctrl_alert.3176758421 |
| Short name | T128 |
| Test name | |
| Test status | |
| Simulation time | 5683530712 ps |
| CPU time | 997.74 seconds |
| Started | Jun 28 08:04:43 PM PDT 24 |
| Finished | Jun 28 08:21:22 PM PDT 24 |
| Peak memory | 608196 kb |
| Host | smart-74819022-66c6-430b-beb5-c22436768a82 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=40_000_000 +sw_build_device=sim_dv +sw_images=sensor_ctrl_alert_test:1:new_rules,test_rom:0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31767584 21 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac e/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_sensor_ctrl_alert.3176758421 |
| Directory | /workspace/0.chip_sw_sensor_ctrl_alert/latest |
| Test location | /workspace/coverage/default/0.chip_sw_sleep_pin_wake.2541067219 |
| Short name | T15 |
| Test name | |
| Test status | |
| Simulation time | 2866655098 ps |
| CPU time | 354.48 seconds |
| Started | Jun 28 08:01:39 PM PDT 24 |
| Finished | Jun 28 08:07:35 PM PDT 24 |
| Peak memory | 607728 kb |
| Host | smart-4f054c88-6e1e-4a13-aad6-2516c43da5a8 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStProd +sw_build_device=sim_dv +sw_images=sleep_pin_wake_test:1:new_rules,test_rom:0 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2541067219 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sleep_pin_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_sleep_pin_wake.2541067219 |
| Directory | /workspace/0.chip_sw_sleep_pin_wake/latest |
| Test location | /workspace/coverage/default/3.chip_tap_straps_rma.1320197060 |
| Short name | T64 |
| Test name | |
| Test status | |
| Simulation time | 3217614158 ps |
| CPU time | 289.43 seconds |
| Started | Jun 28 08:25:28 PM PDT 24 |
| Finished | Jun 28 08:30:20 PM PDT 24 |
| Peak memory | 620044 kb |
| Host | smart-8d0beeb3-7115-46ba-89bd-0f3eeef9173d |
| User | root |
| Command | /workspace/default/simv +create_jtag_riscv_map=1 +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:test_in_rom:new_rules +cdc_instrumentation _enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1320197060 -as sert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_tap_straps_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/c overage/default.vdb -cm_log /dev/null -cm_name 3.chip_tap_straps_rma.1320197060 |
| Directory | /workspace/3.chip_tap_straps_rma/latest |
| Test location | /workspace/coverage/default/2.chip_sw_sleep_pin_wake.3052433278 |
| Short name | T16 |
| Test name | |
| Test status | |
| Simulation time | 3078401744 ps |
| CPU time | 359.7 seconds |
| Started | Jun 28 08:17:01 PM PDT 24 |
| Finished | Jun 28 08:23:06 PM PDT 24 |
| Peak memory | 608316 kb |
| Host | smart-98100e98-02e5-4b4e-b961-0ff2dab2c15f |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStProd +sw_build_device=sim_dv +sw_images=sleep_pin_wake_test:1:new_rules,test_rom:0 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3052433278 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sleep_pin_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_sleep_pin_wake.3052433278 |
| Directory | /workspace/2.chip_sw_sleep_pin_wake/latest |
| Test location | /workspace/coverage/default/1.chip_sw_flash_ctrl_lc_rw_en.3257868311 |
| Short name | T1262 |
| Test name | |
| Test status | |
| Simulation time | 5080041160 ps |
| CPU time | 661.42 seconds |
| Started | Jun 28 08:02:27 PM PDT 24 |
| Finished | Jun 28 08:13:31 PM PDT 24 |
| Peak memory | 609168 kb |
| Host | smart-2c6e92c4-a6d5-4699-92f1-723775d68c1b |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=flash_ctrl_lc_rw_en_test:1:new_rules,test_rom:0 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32 57868311 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_flash_ctrl_lc_rw_en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_flash_ctrl_lc_rw_en.3257868311 |
| Directory | /workspace/1.chip_sw_flash_ctrl_lc_rw_en/latest |
| Test location | /workspace/coverage/default/1.chip_sw_uart_tx_rx_idx3.492013518 |
| Short name | T354 |
| Test name | |
| Test status | |
| Simulation time | 4642208292 ps |
| CPU time | 618.61 seconds |
| Started | Jun 28 08:03:44 PM PDT 24 |
| Finished | Jun 28 08:14:05 PM PDT 24 |
| Peak memory | 615828 kb |
| Host | smart-45f3d174-85f3-4cdc-945c-8e18e8c11094 |
| User | root |
| Command | /workspace/default/simv +uart_idx=3 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=492013518 -as sert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac e/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_uart_tx_rx_idx3.492013518 |
| Directory | /workspace/1.chip_sw_uart_tx_rx_idx3/latest |
| Test location | /workspace/coverage/cover_reg_top/26.xbar_stress_all_with_rand_reset.1350356364 |
| Short name | T1585 |
| Test name | |
| Test status | |
| Simulation time | 12666433273 ps |
| CPU time | 1489.75 seconds |
| Started | Jun 28 08:39:10 PM PDT 24 |
| Finished | Jun 28 09:04:16 PM PDT 24 |
| Peak memory | 582836 kb |
| Host | smart-5d79d7f9-6165-4ac7-94b5-a0fc8031f752 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1350356364 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.xbar_stress_all _with_rand_reset.1350356364 |
| Directory | /workspace/26.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/1.chip_sw_flash_rma_unlocked.4059088092 |
| Short name | T1250 |
| Test name | |
| Test status | |
| Simulation time | 43695656139 ps |
| CPU time | 5657.49 seconds |
| Started | Jun 28 08:05:53 PM PDT 24 |
| Finished | Jun 28 09:40:13 PM PDT 24 |
| Peak memory | 623552 kb |
| Host | smart-4733cbcc-3069-4ca3-8df4-e05811a5c5be |
| User | root |
| Command | /workspace/default/simv +flash_program_latency=5 +sw_test_timeout_ns=150_000_000 +sw_build_device=sim_dv +sw_images=flash_rma_unlocked_test:0:test_in_ rom:new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t cl +ntb_random_seed=4059088092 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_flash_rma_unlocked_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_flash_rma_unlocked.4059088092 |
| Directory | /workspace/1.chip_sw_flash_rma_unlocked/latest |
| Test location | /workspace/coverage/default/0.chip_sw_usbdev_aon_pullup.4241973835 |
| Short name | T70 |
| Test name | |
| Test status | |
| Simulation time | 4307890000 ps |
| CPU time | 495.4 seconds |
| Started | Jun 28 08:01:53 PM PDT 24 |
| Finished | Jun 28 08:10:09 PM PDT 24 |
| Peak memory | 609108 kb |
| Host | smart-02163d67-db93-4486-a19b-5fa862efe40b |
| User | root |
| Command | /workspace/default/simv +uart_idx=0 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=usbdev_aon_pullup_test:1:new_rules,test_rom:0 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=424197 3835 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_usbdev_dpi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_usbdev_aon_pullup.4241973835 |
| Directory | /workspace/0.chip_sw_usbdev_aon_pullup/latest |
| Test location | /workspace/coverage/cover_reg_top/77.xbar_stress_all.3504491866 |
| Short name | T441 |
| Test name | |
| Test status | |
| Simulation time | 4462861854 ps |
| CPU time | 385.72 seconds |
| Started | Jun 28 08:48:29 PM PDT 24 |
| Finished | Jun 28 08:55:10 PM PDT 24 |
| Peak memory | 575444 kb |
| Host | smart-92458f39-3d6a-49b9-b3d4-b74d164aeaba |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3504491866 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 77.xbar_stress_all.3504491866 |
| Directory | /workspace/77.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/54.xbar_stress_all_with_rand_reset.35259400 |
| Short name | T845 |
| Test name | |
| Test status | |
| Simulation time | 1180015979 ps |
| CPU time | 311.33 seconds |
| Started | Jun 28 08:44:43 PM PDT 24 |
| Finished | Jun 28 08:50:13 PM PDT 24 |
| Peak memory | 575388 kb |
| Host | smart-3a7556c1-a26a-4e90-be20-369b133c452e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35259400 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_rese t_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 54.xbar_stress_all_w ith_rand_reset.35259400 |
| Directory | /workspace/54.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/28.chip_tl_errors.737158730 |
| Short name | T517 |
| Test name | |
| Test status | |
| Simulation time | 4317479528 ps |
| CPU time | 355.63 seconds |
| Started | Jun 28 08:39:29 PM PDT 24 |
| Finished | Jun 28 08:45:34 PM PDT 24 |
| Peak memory | 603568 kb |
| Host | smart-3ab84d07-e59f-4466-866d-9ebee5ecc6ac |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=737158730 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.chip_tl_errors.737158730 |
| Directory | /workspace/28.chip_tl_errors/latest |
| Test location | /workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_lc.1448523358 |
| Short name | T860 |
| Test name | |
| Test status | |
| Simulation time | 5542702302 ps |
| CPU time | 632.57 seconds |
| Started | Jun 28 08:12:06 PM PDT 24 |
| Finished | Jun 28 08:22:40 PM PDT 24 |
| Peak memory | 618576 kb |
| Host | smart-547c12a1-3933-4f6b-bffb-ad18bfbc7feb |
| User | root |
| Command | /workspace/default/simv +chip_clock_source=ChipClockSourceExternal48Mhz +sw_build_device=sim_dv +sw_images=clkmgr_external_clk_src_for_lc_test:1:new_r ules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim .tcl +ntb_random_seed=1448523358 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_transition_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_clkmgr_external_clk_src_for_lc.1448523358 |
| Directory | /workspace/1.chip_sw_clkmgr_external_clk_src_for_lc/latest |
| Test location | /workspace/coverage/default/1.chip_plic_all_irqs_20.2668276323 |
| Short name | T320 |
| Test name | |
| Test status | |
| Simulation time | 4307371384 ps |
| CPU time | 791.34 seconds |
| Started | Jun 28 08:09:17 PM PDT 24 |
| Finished | Jun 28 08:22:29 PM PDT 24 |
| Peak memory | 609176 kb |
| Host | smart-eed91594-6d8a-423b-ac43-5f30ca03a6c9 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=plic_all_irqs_test_20:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2668276323 -assert nopostproc +UVM_TESTN AME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log / dev/null -cm_name 1.chip_plic_all_irqs_20.2668276323 |
| Directory | /workspace/1.chip_plic_all_irqs_20/latest |
| Test location | /workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_fast_dev.4164978065 |
| Short name | T867 |
| Test name | |
| Test status | |
| Simulation time | 3783737288 ps |
| CPU time | 707.14 seconds |
| Started | Jun 28 08:05:23 PM PDT 24 |
| Finished | Jun 28 08:17:13 PM PDT 24 |
| Peak memory | 610748 kb |
| Host | smart-3ab2df7a-1ab6-4930-bf62-b9c50055648b |
| User | root |
| Command | /workspace/default/simv +chip_clock_source=ChipClockSourceExternal96Mhz +calibrate_usb_clk=1 +src_dec_state=DecLcStDev +sw_build_device=sim_dv +sw_ima ges=clkmgr_external_clk_src_for_sw_fast_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4164978065 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ =chip_sw_lc_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_c lkmgr_external_clk_src_for_sw_fast_dev.4164978065 |
| Directory | /workspace/1.chip_sw_clkmgr_external_clk_src_for_sw_fast_dev/latest |
| Test location | /workspace/coverage/default/2.chip_plic_all_irqs_0.309948751 |
| Short name | T317 |
| Test name | |
| Test status | |
| Simulation time | 6331833396 ps |
| CPU time | 1181.65 seconds |
| Started | Jun 28 08:21:42 PM PDT 24 |
| Finished | Jun 28 08:41:25 PM PDT 24 |
| Peak memory | 607124 kb |
| Host | smart-45df2910-9a3c-4ca1-843c-bbea6c1bd824 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=plic_all_irqs_test_0:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=309948751 -assert nopostproc +UVM_TESTNAM E=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 2.chip_plic_all_irqs_0.309948751 |
| Directory | /workspace/2.chip_plic_all_irqs_0/latest |
| Test location | /workspace/coverage/default/1.chip_rv_dm_ndm_reset_req.2945597471 |
| Short name | T7 |
| Test name | |
| Test status | |
| Simulation time | 4214309386 ps |
| CPU time | 354.7 seconds |
| Started | Jun 28 08:07:01 PM PDT 24 |
| Finished | Jun 28 08:12:57 PM PDT 24 |
| Peak memory | 616700 kb |
| Host | smart-09a3c101-dcc6-4edf-8436-9bfc9c109b07 |
| User | root |
| Command | /workspace/default/simv +en_scb_tl_err_chk=0 +use_jtag_dmi=1 +sw_build_device=sim_dv +sw_images=rv_dm_ndm_reset_req_rma:1:new_rules,test_rom:0 +cdc_in strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2 945597471 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_rv_dm_ndm_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_rv_dm_ndm_reset_req.2945597471 |
| Directory | /workspace/1.chip_rv_dm_ndm_reset_req/latest |
| Test location | /workspace/coverage/default/1.chip_sw_sensor_ctrl_alert.1530754408 |
| Short name | T126 |
| Test name | |
| Test status | |
| Simulation time | 6872032462 ps |
| CPU time | 867.69 seconds |
| Started | Jun 28 08:05:29 PM PDT 24 |
| Finished | Jun 28 08:19:58 PM PDT 24 |
| Peak memory | 609188 kb |
| Host | smart-00880761-e02c-4050-8239-833712d0038c |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=40_000_000 +sw_build_device=sim_dv +sw_images=sensor_ctrl_alert_test:1:new_rules,test_rom:0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15307544 08 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac e/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_sensor_ctrl_alert.1530754408 |
| Directory | /workspace/1.chip_sw_sensor_ctrl_alert/latest |
| Test location | /workspace/coverage/cover_reg_top/12.xbar_stress_all_with_reset_error.789169014 |
| Short name | T826 |
| Test name | |
| Test status | |
| Simulation time | 4377768590 ps |
| CPU time | 573.18 seconds |
| Started | Jun 28 08:34:53 PM PDT 24 |
| Finished | Jun 28 08:44:46 PM PDT 24 |
| Peak memory | 574676 kb |
| Host | smart-36eb6f45-9add-4e1b-abde-bf35d54a3234 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=789169014 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.xbar_stress_all _with_reset_error.789169014 |
| Directory | /workspace/12.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/27.chip_tl_errors.931706362 |
| Short name | T658 |
| Test name | |
| Test status | |
| Simulation time | 4503361176 ps |
| CPU time | 448.78 seconds |
| Started | Jun 28 08:39:11 PM PDT 24 |
| Finished | Jun 28 08:46:56 PM PDT 24 |
| Peak memory | 597628 kb |
| Host | smart-426290bf-6002-4194-8e12-48da3ab4243c |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=931706362 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.chip_tl_errors.931706362 |
| Directory | /workspace/27.chip_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/3.chip_csr_aliasing.2870769579 |
| Short name | T139 |
| Test name | |
| Test status | |
| Simulation time | 30216254700 ps |
| CPU time | 4898.78 seconds |
| Started | Jun 28 08:29:35 PM PDT 24 |
| Finished | Jun 28 09:51:23 PM PDT 24 |
| Peak memory | 592360 kb |
| Host | smart-a6df355a-d8e6-4e8a-9c30-b4434b0176c3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +csr_aliasing +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2870769579 -assert nopostproc +UVM_TESTNAME=chip_ base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/ null -cm_name 3.chip_csr_aliasing.2870769579 |
| Directory | /workspace/3.chip_csr_aliasing/latest |
| Test location | /workspace/coverage/cover_reg_top/55.xbar_stress_all.3595990329 |
| Short name | T479 |
| Test name | |
| Test status | |
| Simulation time | 16352303775 ps |
| CPU time | 595.68 seconds |
| Started | Jun 28 08:44:49 PM PDT 24 |
| Finished | Jun 28 08:55:04 PM PDT 24 |
| Peak memory | 575440 kb |
| Host | smart-1e4daf71-cadc-4518-92b6-34d6c2cd7f3b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3595990329 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 55.xbar_stress_all.3595990329 |
| Directory | /workspace/55.xbar_stress_all/latest |
| Test location | /workspace/coverage/default/2.chip_sw_flash_rma_unlocked.3051481120 |
| Short name | T1131 |
| Test name | |
| Test status | |
| Simulation time | 43792511696 ps |
| CPU time | 4808.82 seconds |
| Started | Jun 28 08:19:27 PM PDT 24 |
| Finished | Jun 28 09:39:38 PM PDT 24 |
| Peak memory | 623092 kb |
| Host | smart-1006f17b-d30c-4666-b6c9-77745ce53394 |
| User | root |
| Command | /workspace/default/simv +flash_program_latency=5 +sw_test_timeout_ns=150_000_000 +sw_build_device=sim_dv +sw_images=flash_rma_unlocked_test:0:test_in_ rom:new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t cl +ntb_random_seed=3051481120 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_flash_rma_unlocked_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_flash_rma_unlocked.3051481120 |
| Directory | /workspace/2.chip_sw_flash_rma_unlocked/latest |
| Test location | /workspace/coverage/default/0.chip_sw_spi_device_pass_through_collision.1637225833 |
| Short name | T190 |
| Test name | |
| Test status | |
| Simulation time | 4441929608 ps |
| CPU time | 421.12 seconds |
| Started | Jun 28 08:02:36 PM PDT 24 |
| Finished | Jun 28 08:09:39 PM PDT 24 |
| Peak memory | 624212 kb |
| Host | smart-e4892d84-1eb4-4b01-84a8-cd8a7e62507e |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=spi_passthrough_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1637225833 -assert nopostproc +UVM_TESTNA ME=chip_base_test +UVM_TEST_SEQ=chip_sw_spi_passthrough_collision_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/d efault.vdb -cm_log /dev/null -cm_name 0.chip_sw_spi_device_pass_through_collision.1637225833 |
| Directory | /workspace/0.chip_sw_spi_device_pass_through_collision/latest |
| Test location | /workspace/coverage/default/2.chip_sw_spi_host_tx_rx.1004977820 |
| Short name | T43 |
| Test name | |
| Test status | |
| Simulation time | 2843749240 ps |
| CPU time | 242.97 seconds |
| Started | Jun 28 08:15:25 PM PDT 24 |
| Finished | Jun 28 08:19:30 PM PDT 24 |
| Peak memory | 607960 kb |
| Host | smart-f62f3f92-15f6-4942-901a-1e9d93d840d0 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=spi_host_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1004977820 -assert nopostproc +UVM_TESTNAM E=chip_base_test +UVM_TEST_SEQ=chip_sw_spi_host_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb - cm_log /dev/null -cm_name 2.chip_sw_spi_host_tx_rx.1004977820 |
| Directory | /workspace/2.chip_sw_spi_host_tx_rx/latest |
| Test location | /workspace/coverage/default/0.chip_sw_ast_clk_rst_inputs.2747899893 |
| Short name | T109 |
| Test name | |
| Test status | |
| Simulation time | 16404045446 ps |
| CPU time | 2714.14 seconds |
| Started | Jun 28 08:02:48 PM PDT 24 |
| Finished | Jun 28 08:48:04 PM PDT 24 |
| Peak memory | 608784 kb |
| Host | smart-6a30fb6e-4744-464b-880c-455511515080 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=200_000_000 +sw_build_device=sim_dv +sw_images=ast_clk_rst_inputs:1:new_rules,test_rom:0 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2747899893 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_ast_clk_rst_inputs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_ast_clk_rst_inputs.2747899893 |
| Directory | /workspace/0.chip_sw_ast_clk_rst_inputs/latest |
| Test location | /workspace/coverage/default/0.chip_sw_flash_ctrl_ops_jitter_en.2505034395 |
| Short name | T340 |
| Test name | |
| Test status | |
| Simulation time | 3867947804 ps |
| CPU time | 678.1 seconds |
| Started | Jun 28 08:04:26 PM PDT 24 |
| Finished | Jun 28 08:15:46 PM PDT 24 |
| Peak memory | 607740 kb |
| Host | smart-a48fe0a3-6a38-4e72-8ce0-b81e33252f71 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=50_000_000 +en_jitter=1 +sw_build_device=sim_dv +sw_images=flash_ctrl_ops_test:1:new_rules,test_rom:0 +cdc _instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see d=2505034395 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_flash_ctrl_ops_jitter_en.2505034395 |
| Directory | /workspace/0.chip_sw_flash_ctrl_ops_jitter_en/latest |
| Test location | /workspace/coverage/cover_reg_top/34.xbar_stress_all_with_reset_error.3054660185 |
| Short name | T811 |
| Test name | |
| Test status | |
| Simulation time | 458412172 ps |
| CPU time | 152.49 seconds |
| Started | Jun 28 08:40:25 PM PDT 24 |
| Finished | Jun 28 08:43:02 PM PDT 24 |
| Peak memory | 574608 kb |
| Host | smart-2d5c46cd-026c-4992-bf54-01c575538371 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3054660185 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.xbar_stress_al l_with_reset_error.3054660185 |
| Directory | /workspace/34.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/default/0.chip_sw_otp_ctrl_vendor_test_csr_access.375108869 |
| Short name | T156 |
| Test name | |
| Test status | |
| Simulation time | 2060067852 ps |
| CPU time | 125.06 seconds |
| Started | Jun 28 08:05:33 PM PDT 24 |
| Finished | Jun 28 08:07:40 PM PDT 24 |
| Peak memory | 615640 kb |
| Host | smart-93104be1-7f73-4916-a2f3-f245ba6ef7c5 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=otp_ctrl_vendor_test_csr_access_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=375108869 -assert nopostp roc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_otp_ctrl_vendor_test_csr_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_otp_ctrl_vendor_test_csr_access.375108869 |
| Directory | /workspace/0.chip_sw_otp_ctrl_vendor_test_csr_access/latest |
| Test location | /workspace/coverage/cover_reg_top/64.xbar_access_same_device_slow_rsp.324542757 |
| Short name | T445 |
| Test name | |
| Test status | |
| Simulation time | 86868748542 ps |
| CPU time | 1594.15 seconds |
| Started | Jun 28 08:45:56 PM PDT 24 |
| Finished | Jun 28 09:12:49 PM PDT 24 |
| Peak memory | 575380 kb |
| Host | smart-565ec3ad-1b72-4833-b5ac-5b680115ccf8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=324542757 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 64.xbar_access_same_d evice_slow_rsp.324542757 |
| Directory | /workspace/64.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/3.chip_csr_hw_reset.3310974781 |
| Short name | T131 |
| Test name | |
| Test status | |
| Simulation time | 7152271608 ps |
| CPU time | 342.68 seconds |
| Started | Jun 28 08:30:16 PM PDT 24 |
| Finished | Jun 28 08:36:03 PM PDT 24 |
| Peak memory | 661352 kb |
| Host | smart-7fd20c12-8a84-4600-907c-5c38e0e0c654 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3310974781 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.chip_csr_hw_r eset.3310974781 |
| Directory | /workspace/3.chip_csr_hw_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/6.chip_same_csr_outstanding.2308340696 |
| Short name | T400 |
| Test name | |
| Test status | |
| Simulation time | 30931142873 ps |
| CPU time | 3863.77 seconds |
| Started | Jun 28 08:31:36 PM PDT 24 |
| Finished | Jun 28 09:36:13 PM PDT 24 |
| Peak memory | 591964 kb |
| Host | smart-52268d23-9e22-414a-9dfb-b0d877f1ed46 |
| User | root |
| Command | /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +run_same_csr_outstanding +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2308340696 -assert nopostproc +UVM_TE STNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb - cm_log /dev/null -cm_name 6.chip_same_csr_outstanding.2308340696 |
| Directory | /workspace/6.chip_same_csr_outstanding/latest |
| Test location | /workspace/coverage/default/0.chip_plic_all_irqs_20.2532708970 |
| Short name | T321 |
| Test name | |
| Test status | |
| Simulation time | 4222516688 ps |
| CPU time | 797.96 seconds |
| Started | Jun 28 08:00:52 PM PDT 24 |
| Finished | Jun 28 08:14:10 PM PDT 24 |
| Peak memory | 609176 kb |
| Host | smart-b6327562-26c2-4a1f-975f-786b5842a0b8 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=plic_all_irqs_test_20:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2532708970 -assert nopostproc +UVM_TESTN AME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log / dev/null -cm_name 0.chip_plic_all_irqs_20.2532708970 |
| Directory | /workspace/0.chip_plic_all_irqs_20/latest |
| Test location | /workspace/coverage/pad_ctrl_test_mode/0.chip_padctrl_attributes.361199848 |
| Short name | T183 |
| Test name | |
| Test status | |
| Simulation time | 5622563814 ps |
| CPU time | 222.93 seconds |
| Started | Jun 28 08:53:16 PM PDT 24 |
| Finished | Jun 28 08:57:10 PM PDT 24 |
| Peak memory | 640324 kb |
| Host | smart-eb1a2075-c894-4677-a643-a3e29566d9fb |
| User | root |
| Command | /workspace/pad_ctrl_test_mode/simv +use_otp_image=OtpTypeLcStProd +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=361199848 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TES T_SEQ=chip_padctrl_attributes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/pad_ctrl_test_mode.vdb -cm_log /dev/n ull -cm_name 0.chip_padctrl_attributes.361199848 |
| Directory | /workspace/0.chip_padctrl_attributes/latest |
| Test location | /workspace/coverage/default/2.chip_sw_pattgen_ios.3899833014 |
| Short name | T344 |
| Test name | |
| Test status | |
| Simulation time | 3488736356 ps |
| CPU time | 277.11 seconds |
| Started | Jun 28 08:15:09 PM PDT 24 |
| Finished | Jun 28 08:19:47 PM PDT 24 |
| Peak memory | 609284 kb |
| Host | smart-a2fe3396-f6d7-4e93-a47c-d75038cd755f |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=5_000_000 +sw_build_device=sim_dv +sw_images=pattgen_ios_test:1:new_rules,test_rom:0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3899833014 -ass ert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_patt_ios_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/c overage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pattgen_ios.3899833014 |
| Directory | /workspace/2.chip_sw_pattgen_ios/latest |
| Test location | /workspace/coverage/cover_reg_top/13.xbar_stress_all_with_reset_error.928402881 |
| Short name | T1466 |
| Test name | |
| Test status | |
| Simulation time | 1097895930 ps |
| CPU time | 232.17 seconds |
| Started | Jun 28 08:35:36 PM PDT 24 |
| Finished | Jun 28 08:39:55 PM PDT 24 |
| Peak memory | 574352 kb |
| Host | smart-3a6cb431-d12e-4fad-b7b5-4338cf1184b5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=928402881 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.xbar_stress_all _with_reset_error.928402881 |
| Directory | /workspace/13.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/22.xbar_stress_all_with_rand_reset.2764936379 |
| Short name | T851 |
| Test name | |
| Test status | |
| Simulation time | 5595371303 ps |
| CPU time | 462.71 seconds |
| Started | Jun 28 08:38:21 PM PDT 24 |
| Finished | Jun 28 08:46:15 PM PDT 24 |
| Peak memory | 575460 kb |
| Host | smart-b979e8b1-6295-44ed-ac5c-a85a9408b301 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2764936379 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.xbar_stress_all _with_rand_reset.2764936379 |
| Directory | /workspace/22.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/3.xbar_stress_all_with_rand_reset.2360584918 |
| Short name | T2083 |
| Test name | |
| Test status | |
| Simulation time | 485852835 ps |
| CPU time | 216.6 seconds |
| Started | Jun 28 08:30:10 PM PDT 24 |
| Finished | Jun 28 08:33:53 PM PDT 24 |
| Peak memory | 575368 kb |
| Host | smart-1e1a366a-9d95-4b0a-a51b-960566b7ccd1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2360584918 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.xbar_stress_all_ with_rand_reset.2360584918 |
| Directory | /workspace/3.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/47.xbar_stress_all_with_rand_reset.2576474111 |
| Short name | T831 |
| Test name | |
| Test status | |
| Simulation time | 6109798824 ps |
| CPU time | 318.41 seconds |
| Started | Jun 28 08:42:48 PM PDT 24 |
| Finished | Jun 28 08:48:14 PM PDT 24 |
| Peak memory | 575448 kb |
| Host | smart-4f2f9533-93f6-49fa-881e-5b8ffc2e5d7a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2576474111 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.xbar_stress_all _with_rand_reset.2576474111 |
| Directory | /workspace/47.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/0.chip_sw_uart_tx_rx_alt_clk_freq.4221715152 |
| Short name | T1211 |
| Test name | |
| Test status | |
| Simulation time | 3990414305 ps |
| CPU time | 574.95 seconds |
| Started | Jun 28 08:03:56 PM PDT 24 |
| Finished | Jun 28 08:13:35 PM PDT 24 |
| Peak memory | 617628 kb |
| Host | smart-b6eb1f76-7de2-44d2-9211-223fb8b9bcc3 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=80_000_000 +chip_clock_source=ChipClockSourceExternal96Mhz +calibrate_usb_clk=1 +sw_build_device=sim_dv +s w_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4221715152 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_b audrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_uart_tx_rx _alt_clk_freq.4221715152 |
| Directory | /workspace/0.chip_sw_uart_tx_rx_alt_clk_freq/latest |
| Test location | /workspace/coverage/cover_reg_top/47.xbar_stress_all.775517797 |
| Short name | T1842 |
| Test name | |
| Test status | |
| Simulation time | 3355787067 ps |
| CPU time | 284.94 seconds |
| Started | Jun 28 08:42:57 PM PDT 24 |
| Finished | Jun 28 08:47:58 PM PDT 24 |
| Peak memory | 574396 kb |
| Host | smart-583c9587-7c83-4361-b70e-f6c4eac7130a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=775517797 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.xbar_stress_all.775517797 |
| Directory | /workspace/47.xbar_stress_all/latest |
| Test location | /workspace/coverage/default/0.chip_plic_all_irqs_10.1860591453 |
| Short name | T150 |
| Test name | |
| Test status | |
| Simulation time | 4132161704 ps |
| CPU time | 579.4 seconds |
| Started | Jun 28 08:02:05 PM PDT 24 |
| Finished | Jun 28 08:11:45 PM PDT 24 |
| Peak memory | 609180 kb |
| Host | smart-d9881d1c-724f-4247-86b9-7341de950fd9 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=plic_all_irqs_test_10:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1860591453 -assert nopostproc +UVM_TESTN AME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log / dev/null -cm_name 0.chip_plic_all_irqs_10.1860591453 |
| Directory | /workspace/0.chip_plic_all_irqs_10/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_shutdown_output.471233466 |
| Short name | T6 |
| Test name | |
| Test status | |
| Simulation time | 27165423859 ps |
| CPU time | 3960.29 seconds |
| Started | Jun 28 08:06:15 PM PDT 24 |
| Finished | Jun 28 09:12:17 PM PDT 24 |
| Peak memory | 609520 kb |
| Host | smart-354fc932-acc7-4428-8c6c-1662c91cfd43 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=20000000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_unsigned:1:ot_f lash_binary,otp_img_shutdown_output_test_unlocked0:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=471233466 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip _sw_rom_e2e_shutdown_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_shutdown_output.471233466 |
| Directory | /workspace/0.rom_e2e_shutdown_output/latest |
| Test location | /workspace/coverage/cover_reg_top/2.xbar_stress_all_with_rand_reset.2893505411 |
| Short name | T482 |
| Test name | |
| Test status | |
| Simulation time | 7324118170 ps |
| CPU time | 496.86 seconds |
| Started | Jun 28 08:29:48 PM PDT 24 |
| Finished | Jun 28 08:38:17 PM PDT 24 |
| Peak memory | 575432 kb |
| Host | smart-c2a834ea-816c-49b4-8807-3d91c5794657 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2893505411 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.xbar_stress_all_ with_rand_reset.2893505411 |
| Directory | /workspace/2.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/0.chip_sw_csrng_edn_concurrency_reduced_freq.3939785441 |
| Short name | T108 |
| Test name | |
| Test status | |
| Simulation time | 32500616304 ps |
| CPU time | 6037.52 seconds |
| Started | Jun 28 08:02:38 PM PDT 24 |
| Finished | Jun 28 09:43:17 PM PDT 24 |
| Peak memory | 609320 kb |
| Host | smart-b1d39409-2c18-4942-9e67-1b8be88c587e |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=360_000_000 +rng_srate_value_min=15 +rng_srate_value_max=20 +cal_sys_clk_70mhz=1 +en_jitter=1 +accelerate_ cold_power_up_time=3 +accelerate_regulators_power_up_time=2 +sw_build_device=sim_dv +sw_images=csrng_edn_concurrency_test:1:new_rules,test_rom:0 + cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_ seed=3939785441 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_csrng_edn_concurrency_reduced_freq.3939785441 |
| Directory | /workspace/0.chip_sw_csrng_edn_concurrency_reduced_freq/latest |
| Test location | /workspace/coverage/default/1.chip_sw_otp_ctrl_vendor_test_csr_access.2194944309 |
| Short name | T155 |
| Test name | |
| Test status | |
| Simulation time | 1883278217 ps |
| CPU time | 101.34 seconds |
| Started | Jun 28 08:06:05 PM PDT 24 |
| Finished | Jun 28 08:07:47 PM PDT 24 |
| Peak memory | 615632 kb |
| Host | smart-311c8501-8228-44fb-9849-166a773edf81 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=otp_ctrl_vendor_test_csr_access_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2194944309 -assert nopost proc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_otp_ctrl_vendor_test_csr_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_otp_ctrl_vendor_test_csr_access.2194944309 |
| Directory | /workspace/1.chip_sw_otp_ctrl_vendor_test_csr_access/latest |
| Test location | /workspace/coverage/default/0.chip_sw_gpio.2302294467 |
| Short name | T36 |
| Test name | |
| Test status | |
| Simulation time | 3744042024 ps |
| CPU time | 606.32 seconds |
| Started | Jun 28 08:03:51 PM PDT 24 |
| Finished | Jun 28 08:13:59 PM PDT 24 |
| Peak memory | 607100 kb |
| Host | smart-3817037b-934c-432c-93e6-83b6b790eca0 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=gpio_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2302294467 -assert nopostproc +UVM_TESTNAME=chip_bas e_test +UVM_TEST_SEQ=chip_sw_gpio_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm _name 0.chip_sw_gpio.2302294467 |
| Directory | /workspace/0.chip_sw_gpio/latest |
| Test location | /workspace/coverage/default/1.chip_sw_uart_tx_rx.2018149743 |
| Short name | T1020 |
| Test name | |
| Test status | |
| Simulation time | 4302428696 ps |
| CPU time | 603.6 seconds |
| Started | Jun 28 08:04:31 PM PDT 24 |
| Finished | Jun 28 08:14:35 PM PDT 24 |
| Peak memory | 615828 kb |
| Host | smart-6cc9d45d-7b19-4e56-8b65-1789381621f8 |
| User | root |
| Command | /workspace/default/simv +uart_idx=0 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2018149743 -a ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_uart_tx_rx.2018149743 |
| Directory | /workspace/1.chip_sw_uart_tx_rx/latest |
| Test location | /workspace/coverage/default/92.chip_sw_all_escalation_resets.2029994338 |
| Short name | T513 |
| Test name | |
| Test status | |
| Simulation time | 5645931580 ps |
| CPU time | 750.72 seconds |
| Started | Jun 28 08:32:56 PM PDT 24 |
| Finished | Jun 28 08:45:29 PM PDT 24 |
| Peak memory | 643452 kb |
| Host | smart-8d2ae0a4-685c-4095-92a1-497f096e3037 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 2029994338 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 92.chip_sw_all_escalation_resets.2029994338 |
| Directory | /workspace/92.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/cover_reg_top/23.chip_tl_errors.111915116 |
| Short name | T700 |
| Test name | |
| Test status | |
| Simulation time | 3005599249 ps |
| CPU time | 180.3 seconds |
| Started | Jun 28 08:38:26 PM PDT 24 |
| Finished | Jun 28 08:41:36 PM PDT 24 |
| Peak memory | 603564 kb |
| Host | smart-717fe326-6043-4a7d-a297-e2e1390d8e17 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=111915116 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.chip_tl_errors.111915116 |
| Directory | /workspace/23.chip_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/28.xbar_stress_all_with_rand_reset.192173674 |
| Short name | T464 |
| Test name | |
| Test status | |
| Simulation time | 7642003240 ps |
| CPU time | 348.14 seconds |
| Started | Jun 28 08:39:39 PM PDT 24 |
| Finished | Jun 28 08:45:33 PM PDT 24 |
| Peak memory | 574384 kb |
| Host | smart-3b3aeb0e-d4df-42bf-bf18-29387fa6c640 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=192173674 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_res et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.xbar_stress_all_ with_rand_reset.192173674 |
| Directory | /workspace/28.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/1.chip_sw_flash_ctrl_ops_jitter_en.1288256517 |
| Short name | T351 |
| Test name | |
| Test status | |
| Simulation time | 4254783284 ps |
| CPU time | 728.25 seconds |
| Started | Jun 28 08:06:27 PM PDT 24 |
| Finished | Jun 28 08:18:36 PM PDT 24 |
| Peak memory | 609192 kb |
| Host | smart-956e8189-5b8f-4fde-b956-cd0890fbc2dc |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=50_000_000 +en_jitter=1 +sw_build_device=sim_dv +sw_images=flash_ctrl_ops_test:1:new_rules,test_rom:0 +cdc _instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see d=1288256517 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_flash_ctrl_ops_jitter_en.1288256517 |
| Directory | /workspace/1.chip_sw_flash_ctrl_ops_jitter_en/latest |
| Test location | /workspace/coverage/default/0.chip_sw_usbdev_config_host.1602901083 |
| Short name | T35 |
| Test name | |
| Test status | |
| Simulation time | 8232510190 ps |
| CPU time | 2267.05 seconds |
| Started | Jun 28 08:03:29 PM PDT 24 |
| Finished | Jun 28 08:41:18 PM PDT 24 |
| Peak memory | 607780 kb |
| Host | smart-9e11f9d6-cb97-40be-9270-3d5a9e61a2ac |
| User | root |
| Command | /workspace/default/simv +uart_idx=0 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=usbdev_config_host_test:1:new_rules,test_rom:0 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16029 01083 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_usbdev_dpi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_usbdev_config_host.1602901083 |
| Directory | /workspace/0.chip_sw_usbdev_config_host/latest |
| Test location | /workspace/coverage/cover_reg_top/4.xbar_stress_all_with_rand_reset.2234348431 |
| Short name | T842 |
| Test name | |
| Test status | |
| Simulation time | 4499535096 ps |
| CPU time | 441.13 seconds |
| Started | Jun 28 08:30:54 PM PDT 24 |
| Finished | Jun 28 08:38:17 PM PDT 24 |
| Peak memory | 575432 kb |
| Host | smart-15eddb09-5f2e-4807-b53c-17007cd019b6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2234348431 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.xbar_stress_all_ with_rand_reset.2234348431 |
| Directory | /workspace/4.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/0.chip_sw_alert_handler_lpg_sleep_mode_alerts.3030961395 |
| Short name | T692 |
| Test name | |
| Test status | |
| Simulation time | 3889196040 ps |
| CPU time | 487.57 seconds |
| Started | Jun 28 08:08:59 PM PDT 24 |
| Finished | Jun 28 08:17:09 PM PDT 24 |
| Peak memory | 647012 kb |
| Host | smart-8ffc7654-d389-4d2e-acae-745055f2ebfd |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3030961395 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_s w_alert_handler_lpg_sleep_mode_alerts.3030961395 |
| Directory | /workspace/0.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/0.chip_sw_all_escalation_resets.3236464802 |
| Short name | T273 |
| Test name | |
| Test status | |
| Simulation time | 5630768052 ps |
| CPU time | 917.29 seconds |
| Started | Jun 28 08:00:56 PM PDT 24 |
| Finished | Jun 28 08:16:16 PM PDT 24 |
| Peak memory | 643456 kb |
| Host | smart-be760c93-7c82-48d2-9370-953167f9e7a2 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 3236464802 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_all_escalation_resets.3236464802 |
| Directory | /workspace/0.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/1.chip_sw_alert_handler_lpg_sleep_mode_alerts.1191183310 |
| Short name | T735 |
| Test name | |
| Test status | |
| Simulation time | 3191338410 ps |
| CPU time | 381.21 seconds |
| Started | Jun 28 08:08:40 PM PDT 24 |
| Finished | Jun 28 08:15:02 PM PDT 24 |
| Peak memory | 646948 kb |
| Host | smart-7843f2c5-4114-432f-866d-f71f23cb2d80 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1191183310 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_s w_alert_handler_lpg_sleep_mode_alerts.1191183310 |
| Directory | /workspace/1.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/1.chip_sw_all_escalation_resets.2155473266 |
| Short name | T1127 |
| Test name | |
| Test status | |
| Simulation time | 4341237198 ps |
| CPU time | 745.71 seconds |
| Started | Jun 28 08:05:56 PM PDT 24 |
| Finished | Jun 28 08:18:24 PM PDT 24 |
| Peak memory | 643336 kb |
| Host | smart-42d991a3-0b12-4ab8-825d-01c0f1748ed1 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 2155473266 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_all_escalation_resets.2155473266 |
| Directory | /workspace/1.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/10.chip_sw_alert_handler_lpg_sleep_mode_alerts.1885324574 |
| Short name | T395 |
| Test name | |
| Test status | |
| Simulation time | 4149078418 ps |
| CPU time | 402.65 seconds |
| Started | Jun 28 08:28:28 PM PDT 24 |
| Finished | Jun 28 08:35:12 PM PDT 24 |
| Peak memory | 647012 kb |
| Host | smart-621519a7-d0da-47d4-92d6-f297951e3206 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1885324574 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.chip_ sw_alert_handler_lpg_sleep_mode_alerts.1885324574 |
| Directory | /workspace/10.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/10.chip_sw_all_escalation_resets.181505027 |
| Short name | T680 |
| Test name | |
| Test status | |
| Simulation time | 6251171596 ps |
| CPU time | 697.94 seconds |
| Started | Jun 28 08:28:44 PM PDT 24 |
| Finished | Jun 28 08:40:42 PM PDT 24 |
| Peak memory | 643324 kb |
| Host | smart-d81739ff-ccc6-4a25-96e5-9ea49d6a4fa9 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 181505027 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.chip_sw_all_escalation_resets.181505027 |
| Directory | /workspace/10.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/11.chip_sw_alert_handler_lpg_sleep_mode_alerts.1429744312 |
| Short name | T686 |
| Test name | |
| Test status | |
| Simulation time | 3141967946 ps |
| CPU time | 407.69 seconds |
| Started | Jun 28 08:26:36 PM PDT 24 |
| Finished | Jun 28 08:33:26 PM PDT 24 |
| Peak memory | 647432 kb |
| Host | smart-1f6fa784-048a-4437-a01a-a67522618844 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1429744312 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.chip_ sw_alert_handler_lpg_sleep_mode_alerts.1429744312 |
| Directory | /workspace/11.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/11.chip_sw_all_escalation_resets.4200113804 |
| Short name | T760 |
| Test name | |
| Test status | |
| Simulation time | 5427330946 ps |
| CPU time | 638.38 seconds |
| Started | Jun 28 08:31:47 PM PDT 24 |
| Finished | Jun 28 08:42:36 PM PDT 24 |
| Peak memory | 647780 kb |
| Host | smart-a96ab6d5-04c4-4a2a-9fc6-c083a9fe0616 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 4200113804 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.chip_sw_all_escalation_resets.4200113804 |
| Directory | /workspace/11.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/12.chip_sw_alert_handler_lpg_sleep_mode_alerts.2686768594 |
| Short name | T759 |
| Test name | |
| Test status | |
| Simulation time | 4141052840 ps |
| CPU time | 476.45 seconds |
| Started | Jun 28 08:27:50 PM PDT 24 |
| Finished | Jun 28 08:35:54 PM PDT 24 |
| Peak memory | 646880 kb |
| Host | smart-3659401a-2ea0-478a-a4cb-1f158d633d1e |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2686768594 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.chip_ sw_alert_handler_lpg_sleep_mode_alerts.2686768594 |
| Directory | /workspace/12.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/13.chip_sw_all_escalation_resets.2038504591 |
| Short name | T713 |
| Test name | |
| Test status | |
| Simulation time | 4532104560 ps |
| CPU time | 559.18 seconds |
| Started | Jun 28 08:29:05 PM PDT 24 |
| Finished | Jun 28 08:38:46 PM PDT 24 |
| Peak memory | 643476 kb |
| Host | smart-73a3473f-7d17-4cc5-b241-1b6c52637b77 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 2038504591 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.chip_sw_all_escalation_resets.2038504591 |
| Directory | /workspace/13.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/15.chip_sw_alert_handler_lpg_sleep_mode_alerts.2138922231 |
| Short name | T696 |
| Test name | |
| Test status | |
| Simulation time | 4030744152 ps |
| CPU time | 347.01 seconds |
| Started | Jun 28 08:26:30 PM PDT 24 |
| Finished | Jun 28 08:32:19 PM PDT 24 |
| Peak memory | 647332 kb |
| Host | smart-a3b41a49-559e-44b7-b10a-1c1ec1dc0dff |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2138922231 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.chip_ sw_alert_handler_lpg_sleep_mode_alerts.2138922231 |
| Directory | /workspace/15.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/16.chip_sw_alert_handler_lpg_sleep_mode_alerts.1733803937 |
| Short name | T151 |
| Test name | |
| Test status | |
| Simulation time | 4088681672 ps |
| CPU time | 408.55 seconds |
| Started | Jun 28 08:28:38 PM PDT 24 |
| Finished | Jun 28 08:35:41 PM PDT 24 |
| Peak memory | 647040 kb |
| Host | smart-e4d9256d-5452-4bff-8b7a-887d44fb332a |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1733803937 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.chip_ sw_alert_handler_lpg_sleep_mode_alerts.1733803937 |
| Directory | /workspace/16.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/16.chip_sw_all_escalation_resets.3515173713 |
| Short name | T687 |
| Test name | |
| Test status | |
| Simulation time | 4610536868 ps |
| CPU time | 619.72 seconds |
| Started | Jun 28 08:25:40 PM PDT 24 |
| Finished | Jun 28 08:36:01 PM PDT 24 |
| Peak memory | 643400 kb |
| Host | smart-d4253f06-c282-45d6-bf23-01209a2041bf |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 3515173713 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.chip_sw_all_escalation_resets.3515173713 |
| Directory | /workspace/16.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/17.chip_sw_all_escalation_resets.1465204225 |
| Short name | T726 |
| Test name | |
| Test status | |
| Simulation time | 5079717312 ps |
| CPU time | 609.94 seconds |
| Started | Jun 28 08:25:54 PM PDT 24 |
| Finished | Jun 28 08:36:06 PM PDT 24 |
| Peak memory | 643644 kb |
| Host | smart-28dabd34-74a0-42f2-b231-b8d4d5f4ae85 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 1465204225 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.chip_sw_all_escalation_resets.1465204225 |
| Directory | /workspace/17.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/18.chip_sw_alert_handler_lpg_sleep_mode_alerts.2361295527 |
| Short name | T714 |
| Test name | |
| Test status | |
| Simulation time | 3510669840 ps |
| CPU time | 352.64 seconds |
| Started | Jun 28 08:29:29 PM PDT 24 |
| Finished | Jun 28 08:35:28 PM PDT 24 |
| Peak memory | 642168 kb |
| Host | smart-8fc3a1ed-4c1a-4362-9359-20a67118d209 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2361295527 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.chip_ sw_alert_handler_lpg_sleep_mode_alerts.2361295527 |
| Directory | /workspace/18.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/18.chip_sw_all_escalation_resets.3240639321 |
| Short name | T348 |
| Test name | |
| Test status | |
| Simulation time | 5614296138 ps |
| CPU time | 496.06 seconds |
| Started | Jun 28 08:28:49 PM PDT 24 |
| Finished | Jun 28 08:37:27 PM PDT 24 |
| Peak memory | 647788 kb |
| Host | smart-537ef973-8537-434d-a7dc-d2957cb94150 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 3240639321 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.chip_sw_all_escalation_resets.3240639321 |
| Directory | /workspace/18.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/2.chip_sw_alert_handler_lpg_sleep_mode_alerts.594159122 |
| Short name | T767 |
| Test name | |
| Test status | |
| Simulation time | 4025654598 ps |
| CPU time | 501.01 seconds |
| Started | Jun 28 08:19:55 PM PDT 24 |
| Finished | Jun 28 08:28:17 PM PDT 24 |
| Peak memory | 642320 kb |
| Host | smart-49f40660-9d1a-4160-801f-afc3ffb2e14c |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=594159122 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all _escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw _alert_handler_lpg_sleep_mode_alerts.594159122 |
| Directory | /workspace/2.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/21.chip_sw_alert_handler_lpg_sleep_mode_alerts.1593346971 |
| Short name | T750 |
| Test name | |
| Test status | |
| Simulation time | 4312717816 ps |
| CPU time | 570.56 seconds |
| Started | Jun 28 08:32:27 PM PDT 24 |
| Finished | Jun 28 08:41:59 PM PDT 24 |
| Peak memory | 642828 kb |
| Host | smart-90a4e7a4-962a-4778-8c6e-735c04e7dec7 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1593346971 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.chip_ sw_alert_handler_lpg_sleep_mode_alerts.1593346971 |
| Directory | /workspace/21.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/22.chip_sw_alert_handler_lpg_sleep_mode_alerts.3825313695 |
| Short name | T764 |
| Test name | |
| Test status | |
| Simulation time | 3447223344 ps |
| CPU time | 506.75 seconds |
| Started | Jun 28 08:29:31 PM PDT 24 |
| Finished | Jun 28 08:38:04 PM PDT 24 |
| Peak memory | 647092 kb |
| Host | smart-3b64d46d-3a9f-4253-91d4-9eb267dd59a2 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3825313695 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.chip_ sw_alert_handler_lpg_sleep_mode_alerts.3825313695 |
| Directory | /workspace/22.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/22.chip_sw_all_escalation_resets.1655405011 |
| Short name | T689 |
| Test name | |
| Test status | |
| Simulation time | 4644526440 ps |
| CPU time | 681 seconds |
| Started | Jun 28 08:27:21 PM PDT 24 |
| Finished | Jun 28 08:38:43 PM PDT 24 |
| Peak memory | 643464 kb |
| Host | smart-4d5b1da5-6ff7-4aae-ad39-889195ed6bf2 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 1655405011 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.chip_sw_all_escalation_resets.1655405011 |
| Directory | /workspace/22.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/23.chip_sw_alert_handler_lpg_sleep_mode_alerts.4089926510 |
| Short name | T720 |
| Test name | |
| Test status | |
| Simulation time | 4053952816 ps |
| CPU time | 402.06 seconds |
| Started | Jun 28 08:28:25 PM PDT 24 |
| Finished | Jun 28 08:35:09 PM PDT 24 |
| Peak memory | 647096 kb |
| Host | smart-fabe0959-8266-4663-84e7-6945ffae5d07 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4089926510 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.chip_ sw_alert_handler_lpg_sleep_mode_alerts.4089926510 |
| Directory | /workspace/23.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/24.chip_sw_alert_handler_lpg_sleep_mode_alerts.3062349413 |
| Short name | T730 |
| Test name | |
| Test status | |
| Simulation time | 3829330226 ps |
| CPU time | 476.18 seconds |
| Started | Jun 28 08:27:02 PM PDT 24 |
| Finished | Jun 28 08:34:59 PM PDT 24 |
| Peak memory | 647036 kb |
| Host | smart-a035f139-5295-4414-967a-368129f7df16 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3062349413 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.chip_ sw_alert_handler_lpg_sleep_mode_alerts.3062349413 |
| Directory | /workspace/24.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/24.chip_sw_all_escalation_resets.2547149756 |
| Short name | T413 |
| Test name | |
| Test status | |
| Simulation time | 4945677736 ps |
| CPU time | 612.6 seconds |
| Started | Jun 28 08:27:23 PM PDT 24 |
| Finished | Jun 28 08:37:37 PM PDT 24 |
| Peak memory | 643584 kb |
| Host | smart-c8f26f6b-b872-4e2e-9c11-c30eeb53d5da |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 2547149756 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.chip_sw_all_escalation_resets.2547149756 |
| Directory | /workspace/24.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/25.chip_sw_all_escalation_resets.398339698 |
| Short name | T774 |
| Test name | |
| Test status | |
| Simulation time | 6209755208 ps |
| CPU time | 807.01 seconds |
| Started | Jun 28 08:30:19 PM PDT 24 |
| Finished | Jun 28 08:43:52 PM PDT 24 |
| Peak memory | 643148 kb |
| Host | smart-eee971b1-19a3-408f-b727-b02253fbab5c |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 398339698 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.chip_sw_all_escalation_resets.398339698 |
| Directory | /workspace/25.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/26.chip_sw_all_escalation_resets.3439628811 |
| Short name | T776 |
| Test name | |
| Test status | |
| Simulation time | 4462412600 ps |
| CPU time | 717.77 seconds |
| Started | Jun 28 08:29:57 PM PDT 24 |
| Finished | Jun 28 08:42:07 PM PDT 24 |
| Peak memory | 643368 kb |
| Host | smart-45e487f8-9f53-402c-b164-8bfccace259e |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 3439628811 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.chip_sw_all_escalation_resets.3439628811 |
| Directory | /workspace/26.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/27.chip_sw_alert_handler_lpg_sleep_mode_alerts.4051008983 |
| Short name | T747 |
| Test name | |
| Test status | |
| Simulation time | 4076033776 ps |
| CPU time | 436.02 seconds |
| Started | Jun 28 08:27:24 PM PDT 24 |
| Finished | Jun 28 08:34:42 PM PDT 24 |
| Peak memory | 647004 kb |
| Host | smart-b72a32d7-45f4-4463-8823-583abcb3f160 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4051008983 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.chip_ sw_alert_handler_lpg_sleep_mode_alerts.4051008983 |
| Directory | /workspace/27.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/27.chip_sw_all_escalation_resets.1681171896 |
| Short name | T636 |
| Test name | |
| Test status | |
| Simulation time | 6158800926 ps |
| CPU time | 741.44 seconds |
| Started | Jun 28 08:30:21 PM PDT 24 |
| Finished | Jun 28 08:42:48 PM PDT 24 |
| Peak memory | 643776 kb |
| Host | smart-3ef27503-556a-4f5b-afb3-df0b0eefe94a |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 1681171896 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.chip_sw_all_escalation_resets.1681171896 |
| Directory | /workspace/27.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/28.chip_sw_all_escalation_resets.4031752012 |
| Short name | T291 |
| Test name | |
| Test status | |
| Simulation time | 4875431480 ps |
| CPU time | 575.64 seconds |
| Started | Jun 28 08:28:24 PM PDT 24 |
| Finished | Jun 28 08:38:00 PM PDT 24 |
| Peak memory | 648004 kb |
| Host | smart-ec668e6e-9532-42d8-bc31-27b0a4fbce0d |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 4031752012 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.chip_sw_all_escalation_resets.4031752012 |
| Directory | /workspace/28.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/29.chip_sw_all_escalation_resets.3488699745 |
| Short name | T290 |
| Test name | |
| Test status | |
| Simulation time | 5542890430 ps |
| CPU time | 645.86 seconds |
| Started | Jun 28 08:28:05 PM PDT 24 |
| Finished | Jun 28 08:38:52 PM PDT 24 |
| Peak memory | 643332 kb |
| Host | smart-4ceb0aca-f754-4be5-85e4-ab7c6dc517af |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 3488699745 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.chip_sw_all_escalation_resets.3488699745 |
| Directory | /workspace/29.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/3.chip_sw_alert_handler_lpg_sleep_mode_alerts.2179561093 |
| Short name | T728 |
| Test name | |
| Test status | |
| Simulation time | 3996059064 ps |
| CPU time | 488.46 seconds |
| Started | Jun 28 08:24:56 PM PDT 24 |
| Finished | Jun 28 08:33:06 PM PDT 24 |
| Peak memory | 647144 kb |
| Host | smart-f7e17ebe-ab69-48e1-9581-0243d8636b7f |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2179561093 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.chip_s w_alert_handler_lpg_sleep_mode_alerts.2179561093 |
| Directory | /workspace/3.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/30.chip_sw_all_escalation_resets.692535470 |
| Short name | T258 |
| Test name | |
| Test status | |
| Simulation time | 5068343688 ps |
| CPU time | 609 seconds |
| Started | Jun 28 08:30:21 PM PDT 24 |
| Finished | Jun 28 08:40:35 PM PDT 24 |
| Peak memory | 648092 kb |
| Host | smart-f2aa99f7-cbea-4413-b8c0-7d968403c6df |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 692535470 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.chip_sw_all_escalation_resets.692535470 |
| Directory | /workspace/30.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/31.chip_sw_alert_handler_lpg_sleep_mode_alerts.3218262528 |
| Short name | T682 |
| Test name | |
| Test status | |
| Simulation time | 4324030440 ps |
| CPU time | 528.94 seconds |
| Started | Jun 28 08:30:22 PM PDT 24 |
| Finished | Jun 28 08:39:17 PM PDT 24 |
| Peak memory | 642600 kb |
| Host | smart-9c2c59a8-9fb6-4ffa-9479-0a713167de5b |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3218262528 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.chip_ sw_alert_handler_lpg_sleep_mode_alerts.3218262528 |
| Directory | /workspace/31.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/32.chip_sw_all_escalation_resets.2600932671 |
| Short name | T512 |
| Test name | |
| Test status | |
| Simulation time | 6608753204 ps |
| CPU time | 740.7 seconds |
| Started | Jun 28 08:28:37 PM PDT 24 |
| Finished | Jun 28 08:41:08 PM PDT 24 |
| Peak memory | 642368 kb |
| Host | smart-365aae7a-1264-4b53-a419-5edcb994ac2e |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 2600932671 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.chip_sw_all_escalation_resets.2600932671 |
| Directory | /workspace/32.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/33.chip_sw_alert_handler_lpg_sleep_mode_alerts.379499653 |
| Short name | T268 |
| Test name | |
| Test status | |
| Simulation time | 3869114680 ps |
| CPU time | 490.57 seconds |
| Started | Jun 28 08:30:30 PM PDT 24 |
| Finished | Jun 28 08:38:48 PM PDT 24 |
| Peak memory | 646932 kb |
| Host | smart-2d54848b-c7bb-4c81-b6e6-1b266472b520 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=379499653 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all _escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.chip_s w_alert_handler_lpg_sleep_mode_alerts.379499653 |
| Directory | /workspace/33.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/33.chip_sw_all_escalation_resets.2577061249 |
| Short name | T779 |
| Test name | |
| Test status | |
| Simulation time | 6009376492 ps |
| CPU time | 795.65 seconds |
| Started | Jun 28 08:27:39 PM PDT 24 |
| Finished | Jun 28 08:41:04 PM PDT 24 |
| Peak memory | 643584 kb |
| Host | smart-51c8cd76-48d4-4546-bbf9-5794a85fe33c |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 2577061249 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.chip_sw_all_escalation_resets.2577061249 |
| Directory | /workspace/33.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/34.chip_sw_alert_handler_lpg_sleep_mode_alerts.1661982426 |
| Short name | T1054 |
| Test name | |
| Test status | |
| Simulation time | 3946370342 ps |
| CPU time | 457.62 seconds |
| Started | Jun 28 08:29:55 PM PDT 24 |
| Finished | Jun 28 08:37:45 PM PDT 24 |
| Peak memory | 642208 kb |
| Host | smart-159dc138-5851-407a-abd3-9911ed5fcde9 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1661982426 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.chip_ sw_alert_handler_lpg_sleep_mode_alerts.1661982426 |
| Directory | /workspace/34.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/36.chip_sw_all_escalation_resets.2222365653 |
| Short name | T511 |
| Test name | |
| Test status | |
| Simulation time | 5564814636 ps |
| CPU time | 732.97 seconds |
| Started | Jun 28 08:27:55 PM PDT 24 |
| Finished | Jun 28 08:40:11 PM PDT 24 |
| Peak memory | 647916 kb |
| Host | smart-e29aaa35-e9c2-4086-808b-8e446230b7ed |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 2222365653 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.chip_sw_all_escalation_resets.2222365653 |
| Directory | /workspace/36.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/37.chip_sw_alert_handler_lpg_sleep_mode_alerts.4279395770 |
| Short name | T721 |
| Test name | |
| Test status | |
| Simulation time | 3270231880 ps |
| CPU time | 423.47 seconds |
| Started | Jun 28 08:29:32 PM PDT 24 |
| Finished | Jun 28 08:36:42 PM PDT 24 |
| Peak memory | 642300 kb |
| Host | smart-3d3d95b5-9bf6-46c8-9baf-f9bf6f2dc07a |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4279395770 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.chip_ sw_alert_handler_lpg_sleep_mode_alerts.4279395770 |
| Directory | /workspace/37.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/38.chip_sw_all_escalation_resets.297749080 |
| Short name | T724 |
| Test name | |
| Test status | |
| Simulation time | 4221638148 ps |
| CPU time | 531.07 seconds |
| Started | Jun 28 08:29:31 PM PDT 24 |
| Finished | Jun 28 08:38:29 PM PDT 24 |
| Peak memory | 643204 kb |
| Host | smart-ce4c7882-2beb-440c-9850-479fbb582844 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 297749080 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.chip_sw_all_escalation_resets.297749080 |
| Directory | /workspace/38.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/4.chip_sw_all_escalation_resets.1505340526 |
| Short name | T355 |
| Test name | |
| Test status | |
| Simulation time | 4993436328 ps |
| CPU time | 740.16 seconds |
| Started | Jun 28 08:25:17 PM PDT 24 |
| Finished | Jun 28 08:37:44 PM PDT 24 |
| Peak memory | 643376 kb |
| Host | smart-6c4f2a3e-4e00-4cc9-b634-a3e4cfb78bdb |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 1505340526 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.chip_sw_all_escalation_resets.1505340526 |
| Directory | /workspace/4.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/41.chip_sw_alert_handler_lpg_sleep_mode_alerts.2622466827 |
| Short name | T295 |
| Test name | |
| Test status | |
| Simulation time | 3728936126 ps |
| CPU time | 400.33 seconds |
| Started | Jun 28 08:29:31 PM PDT 24 |
| Finished | Jun 28 08:36:18 PM PDT 24 |
| Peak memory | 642124 kb |
| Host | smart-15a8c11a-1b27-4e31-ae85-d04019f37086 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2622466827 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.chip_ sw_alert_handler_lpg_sleep_mode_alerts.2622466827 |
| Directory | /workspace/41.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/41.chip_sw_all_escalation_resets.2853981799 |
| Short name | T737 |
| Test name | |
| Test status | |
| Simulation time | 5427974658 ps |
| CPU time | 725.05 seconds |
| Started | Jun 28 08:28:38 PM PDT 24 |
| Finished | Jun 28 08:40:56 PM PDT 24 |
| Peak memory | 643776 kb |
| Host | smart-a2956490-c71d-42d8-aaa0-0d709bf6bdf0 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 2853981799 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.chip_sw_all_escalation_resets.2853981799 |
| Directory | /workspace/41.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/42.chip_sw_alert_handler_lpg_sleep_mode_alerts.1652103233 |
| Short name | T672 |
| Test name | |
| Test status | |
| Simulation time | 3594522844 ps |
| CPU time | 458.78 seconds |
| Started | Jun 28 08:33:51 PM PDT 24 |
| Finished | Jun 28 08:41:39 PM PDT 24 |
| Peak memory | 646992 kb |
| Host | smart-0c7f971c-b89c-42c0-a546-d0cca38f6b55 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1652103233 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.chip_ sw_alert_handler_lpg_sleep_mode_alerts.1652103233 |
| Directory | /workspace/42.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/46.chip_sw_all_escalation_resets.96419946 |
| Short name | T762 |
| Test name | |
| Test status | |
| Simulation time | 4714335478 ps |
| CPU time | 540.63 seconds |
| Started | Jun 28 08:33:52 PM PDT 24 |
| Finished | Jun 28 08:43:02 PM PDT 24 |
| Peak memory | 643460 kb |
| Host | smart-1c1a3824-a30a-4e74-a7fb-e85a601664ce |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 96419946 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.chip_sw_all_escalation_resets.96419946 |
| Directory | /workspace/46.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/47.chip_sw_alert_handler_lpg_sleep_mode_alerts.3986948721 |
| Short name | T705 |
| Test name | |
| Test status | |
| Simulation time | 3496356856 ps |
| CPU time | 444.17 seconds |
| Started | Jun 28 08:29:11 PM PDT 24 |
| Finished | Jun 28 08:36:53 PM PDT 24 |
| Peak memory | 646996 kb |
| Host | smart-7152fb55-5858-4a2c-9847-518e715048d9 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3986948721 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.chip_ sw_alert_handler_lpg_sleep_mode_alerts.3986948721 |
| Directory | /workspace/47.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/48.chip_sw_all_escalation_resets.338449172 |
| Short name | T286 |
| Test name | |
| Test status | |
| Simulation time | 4752160616 ps |
| CPU time | 483.3 seconds |
| Started | Jun 28 08:30:21 PM PDT 24 |
| Finished | Jun 28 08:38:30 PM PDT 24 |
| Peak memory | 647752 kb |
| Host | smart-3f0fe6b0-c6c0-4cd3-9678-d1a6412c00c5 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 338449172 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.chip_sw_all_escalation_resets.338449172 |
| Directory | /workspace/48.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/49.chip_sw_all_escalation_resets.1521282607 |
| Short name | T312 |
| Test name | |
| Test status | |
| Simulation time | 5267630088 ps |
| CPU time | 740.07 seconds |
| Started | Jun 28 08:29:05 PM PDT 24 |
| Finished | Jun 28 08:41:47 PM PDT 24 |
| Peak memory | 648060 kb |
| Host | smart-c6b29fea-f14a-497d-b3b7-66cb57e475b1 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 1521282607 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.chip_sw_all_escalation_resets.1521282607 |
| Directory | /workspace/49.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/5.chip_sw_alert_handler_lpg_sleep_mode_alerts.846716196 |
| Short name | T708 |
| Test name | |
| Test status | |
| Simulation time | 3843523562 ps |
| CPU time | 469.16 seconds |
| Started | Jun 28 08:24:26 PM PDT 24 |
| Finished | Jun 28 08:32:21 PM PDT 24 |
| Peak memory | 646924 kb |
| Host | smart-aadeee3c-a433-48dc-8b03-1c4ce5ddf6f2 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=846716196 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all _escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.chip_sw _alert_handler_lpg_sleep_mode_alerts.846716196 |
| Directory | /workspace/5.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/51.chip_sw_alert_handler_lpg_sleep_mode_alerts.451379588 |
| Short name | T745 |
| Test name | |
| Test status | |
| Simulation time | 3259021662 ps |
| CPU time | 542.25 seconds |
| Started | Jun 28 08:29:11 PM PDT 24 |
| Finished | Jun 28 08:38:31 PM PDT 24 |
| Peak memory | 642020 kb |
| Host | smart-e694a68f-eab8-40a8-ac61-db8c01e2886f |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=451379588 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all _escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.chip_s w_alert_handler_lpg_sleep_mode_alerts.451379588 |
| Directory | /workspace/51.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/52.chip_sw_alert_handler_lpg_sleep_mode_alerts.3358243325 |
| Short name | T755 |
| Test name | |
| Test status | |
| Simulation time | 4612629954 ps |
| CPU time | 459.03 seconds |
| Started | Jun 28 08:29:49 PM PDT 24 |
| Finished | Jun 28 08:37:40 PM PDT 24 |
| Peak memory | 647236 kb |
| Host | smart-64df2053-db84-4002-95ca-86520efd2868 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3358243325 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.chip_ sw_alert_handler_lpg_sleep_mode_alerts.3358243325 |
| Directory | /workspace/52.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/52.chip_sw_all_escalation_resets.4121407254 |
| Short name | T420 |
| Test name | |
| Test status | |
| Simulation time | 6106377160 ps |
| CPU time | 716.86 seconds |
| Started | Jun 28 08:29:05 PM PDT 24 |
| Finished | Jun 28 08:41:23 PM PDT 24 |
| Peak memory | 647952 kb |
| Host | smart-7abfd650-b718-4313-b749-488f5732b6b3 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 4121407254 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.chip_sw_all_escalation_resets.4121407254 |
| Directory | /workspace/52.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/53.chip_sw_all_escalation_resets.1454916819 |
| Short name | T245 |
| Test name | |
| Test status | |
| Simulation time | 5808874216 ps |
| CPU time | 739.38 seconds |
| Started | Jun 28 08:34:47 PM PDT 24 |
| Finished | Jun 28 08:47:28 PM PDT 24 |
| Peak memory | 647904 kb |
| Host | smart-c23aec99-ab79-4de7-9f0f-89a71a2bf07e |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 1454916819 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.chip_sw_all_escalation_resets.1454916819 |
| Directory | /workspace/53.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/54.chip_sw_all_escalation_resets.125798506 |
| Short name | T347 |
| Test name | |
| Test status | |
| Simulation time | 4910583656 ps |
| CPU time | 645.67 seconds |
| Started | Jun 28 08:31:30 PM PDT 24 |
| Finished | Jun 28 08:42:31 PM PDT 24 |
| Peak memory | 643812 kb |
| Host | smart-4c3fbb08-d9ed-457c-8448-49a6826c9f92 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 125798506 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.chip_sw_all_escalation_resets.125798506 |
| Directory | /workspace/54.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/55.chip_sw_alert_handler_lpg_sleep_mode_alerts.429565799 |
| Short name | T763 |
| Test name | |
| Test status | |
| Simulation time | 3674021796 ps |
| CPU time | 388.44 seconds |
| Started | Jun 28 08:29:04 PM PDT 24 |
| Finished | Jun 28 08:35:55 PM PDT 24 |
| Peak memory | 647008 kb |
| Host | smart-2fdf95dd-ff94-4ee6-afce-052f4fc7a3d7 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=429565799 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all _escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.chip_s w_alert_handler_lpg_sleep_mode_alerts.429565799 |
| Directory | /workspace/55.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/56.chip_sw_all_escalation_resets.3112455378 |
| Short name | T683 |
| Test name | |
| Test status | |
| Simulation time | 5792478696 ps |
| CPU time | 592.42 seconds |
| Started | Jun 28 08:34:19 PM PDT 24 |
| Finished | Jun 28 08:44:27 PM PDT 24 |
| Peak memory | 643688 kb |
| Host | smart-08e341de-1c98-4c38-8d3f-97f8bd17dd73 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 3112455378 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.chip_sw_all_escalation_resets.3112455378 |
| Directory | /workspace/56.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/57.chip_sw_alert_handler_lpg_sleep_mode_alerts.304262374 |
| Short name | T707 |
| Test name | |
| Test status | |
| Simulation time | 3825831064 ps |
| CPU time | 537.05 seconds |
| Started | Jun 28 08:30:15 PM PDT 24 |
| Finished | Jun 28 08:39:16 PM PDT 24 |
| Peak memory | 647036 kb |
| Host | smart-f9c54760-f4d2-4493-a1df-da22cb757e66 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=304262374 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all _escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.chip_s w_alert_handler_lpg_sleep_mode_alerts.304262374 |
| Directory | /workspace/57.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/58.chip_sw_alert_handler_lpg_sleep_mode_alerts.2118015060 |
| Short name | T288 |
| Test name | |
| Test status | |
| Simulation time | 3816270482 ps |
| CPU time | 306.33 seconds |
| Started | Jun 28 08:33:39 PM PDT 24 |
| Finished | Jun 28 08:38:52 PM PDT 24 |
| Peak memory | 647112 kb |
| Host | smart-53d6546e-7fd4-48e6-86e3-11e01e3cc624 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2118015060 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.chip_ sw_alert_handler_lpg_sleep_mode_alerts.2118015060 |
| Directory | /workspace/58.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/58.chip_sw_all_escalation_resets.1313496145 |
| Short name | T706 |
| Test name | |
| Test status | |
| Simulation time | 5461340538 ps |
| CPU time | 692.63 seconds |
| Started | Jun 28 08:31:28 PM PDT 24 |
| Finished | Jun 28 08:43:17 PM PDT 24 |
| Peak memory | 643496 kb |
| Host | smart-73f57e07-a099-417b-9438-5a09cf6563d9 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 1313496145 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.chip_sw_all_escalation_resets.1313496145 |
| Directory | /workspace/58.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/68.chip_sw_alert_handler_lpg_sleep_mode_alerts.4250747768 |
| Short name | T506 |
| Test name | |
| Test status | |
| Simulation time | 3505614274 ps |
| CPU time | 270.93 seconds |
| Started | Jun 28 08:30:08 PM PDT 24 |
| Finished | Jun 28 08:34:46 PM PDT 24 |
| Peak memory | 646996 kb |
| Host | smart-12857e21-e15e-4f7f-9921-3e7bc0fc7391 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4250747768 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.chip_ sw_alert_handler_lpg_sleep_mode_alerts.4250747768 |
| Directory | /workspace/68.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/71.chip_sw_all_escalation_resets.1126835270 |
| Short name | T703 |
| Test name | |
| Test status | |
| Simulation time | 5488797600 ps |
| CPU time | 627.05 seconds |
| Started | Jun 28 08:31:05 PM PDT 24 |
| Finished | Jun 28 08:41:37 PM PDT 24 |
| Peak memory | 647932 kb |
| Host | smart-4ee48021-f14e-46b8-b3f0-b081a4baa817 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 1126835270 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.chip_sw_all_escalation_resets.1126835270 |
| Directory | /workspace/71.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/76.chip_sw_all_escalation_resets.2717093730 |
| Short name | T86 |
| Test name | |
| Test status | |
| Simulation time | 4863242100 ps |
| CPU time | 458.79 seconds |
| Started | Jun 28 08:31:52 PM PDT 24 |
| Finished | Jun 28 08:39:41 PM PDT 24 |
| Peak memory | 644064 kb |
| Host | smart-a0290417-5665-46fa-9a49-d10433afd2c9 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 2717093730 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.chip_sw_all_escalation_resets.2717093730 |
| Directory | /workspace/76.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/78.chip_sw_all_escalation_resets.2509815939 |
| Short name | T679 |
| Test name | |
| Test status | |
| Simulation time | 4715168000 ps |
| CPU time | 766.41 seconds |
| Started | Jun 28 08:32:59 PM PDT 24 |
| Finished | Jun 28 08:45:48 PM PDT 24 |
| Peak memory | 643632 kb |
| Host | smart-7a313045-f1cb-44a9-a7f5-7341ae48f528 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 2509815939 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.chip_sw_all_escalation_resets.2509815939 |
| Directory | /workspace/78.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/84.chip_sw_all_escalation_resets.150176406 |
| Short name | T757 |
| Test name | |
| Test status | |
| Simulation time | 5655768120 ps |
| CPU time | 606.11 seconds |
| Started | Jun 28 08:33:06 PM PDT 24 |
| Finished | Jun 28 08:43:22 PM PDT 24 |
| Peak memory | 643448 kb |
| Host | smart-d7d82e59-c032-446a-b13b-cacd7047f195 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 150176406 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 84.chip_sw_all_escalation_resets.150176406 |
| Directory | /workspace/84.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/cover_reg_top/25.xbar_stress_all_with_rand_reset.220212259 |
| Short name | T848 |
| Test name | |
| Test status | |
| Simulation time | 10680035694 ps |
| CPU time | 1057.74 seconds |
| Started | Jun 28 08:38:40 PM PDT 24 |
| Finished | Jun 28 08:56:21 PM PDT 24 |
| Peak memory | 576444 kb |
| Host | smart-8d92d6b9-99a7-4ccf-a550-37df9d515949 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=220212259 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_res et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.xbar_stress_all_ with_rand_reset.220212259 |
| Directory | /workspace/25.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/87.xbar_stress_all_with_rand_reset.3772117383 |
| Short name | T1869 |
| Test name | |
| Test status | |
| Simulation time | 6292244483 ps |
| CPU time | 659.03 seconds |
| Started | Jun 28 08:50:27 PM PDT 24 |
| Finished | Jun 28 09:01:57 PM PDT 24 |
| Peak memory | 575468 kb |
| Host | smart-53a1bad7-a078-4a1d-80bb-90877fc8a4ae |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3772117383 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 87.xbar_stress_all _with_rand_reset.3772117383 |
| Directory | /workspace/87.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/0.chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up.807800448 |
| Short name | T366 |
| Test name | |
| Test status | |
| Simulation time | 4910091476 ps |
| CPU time | 295.07 seconds |
| Started | Jun 28 08:02:03 PM PDT 24 |
| Finished | Jun 28 08:06:59 PM PDT 24 |
| Peak memory | 609328 kb |
| Host | smart-e8a30493-51ec-492d-9d1f-96d0c66f44d8 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +do_random=1 +sw_build_device=sim_dv +sw_images=pwrmgr_sensor_ctrl_deep_sleep_wake_up:1:new_rul es,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t cl +ntb_random_seed=807800448 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_sensor_ctrl_deep_sl eep_wake_up.807800448 |
| Directory | /workspace/0.chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up/latest |
| Test location | /workspace/coverage/default/2.chip_sw_pwrmgr_lowpower_cancel.1358162220 |
| Short name | T334 |
| Test name | |
| Test status | |
| Simulation time | 3841262866 ps |
| CPU time | 355.02 seconds |
| Started | Jun 28 08:21:45 PM PDT 24 |
| Finished | Jun 28 08:27:40 PM PDT 24 |
| Peak memory | 609244 kb |
| Host | smart-4e6d8a28-197d-4e8c-b504-22b34824dc4d |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_lowpower_cancel_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1358162220 -assert nopostproc +UVM _TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm _log /dev/null -cm_name 2.chip_sw_pwrmgr_lowpower_cancel.1358162220 |
| Directory | /workspace/2.chip_sw_pwrmgr_lowpower_cancel/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_jtag_inject_rma.3727983329 |
| Short name | T106 |
| Test name | |
| Test status | |
| Simulation time | 25742403491 ps |
| CPU time | 3350.88 seconds |
| Started | Jun 28 08:02:55 PM PDT 24 |
| Finished | Jun 28 08:58:48 PM PDT 24 |
| Peak memory | 617668 kb |
| Host | smart-21a8d03d-e19a-45f7-9ce2-b77ae2f850e7 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=40_000_000 +use_jtag_dmi=1 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=img_rma_exec_di sabled:4,sram_program:5,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3727983329 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_e2e_jtag_inject_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_jtag_inject_rma.3727983329 |
| Directory | /workspace/0.rom_e2e_jtag_inject_rma/latest |
| Test location | /workspace/coverage/default/15.chip_sw_all_escalation_resets.3743338603 |
| Short name | T647 |
| Test name | |
| Test status | |
| Simulation time | 4607983704 ps |
| CPU time | 588.89 seconds |
| Started | Jun 28 08:27:20 PM PDT 24 |
| Finished | Jun 28 08:37:11 PM PDT 24 |
| Peak memory | 608416 kb |
| Host | smart-cefd650d-5c35-4296-be1e-df6411c01999 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 3743338603 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.chip_sw_all_escalation_resets.3743338603 |
| Directory | /workspace/15.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/0.chip_sw_i2c_host_tx_rx_idx1.1851041722 |
| Short name | T330 |
| Test name | |
| Test status | |
| Simulation time | 4761805680 ps |
| CPU time | 732.1 seconds |
| Started | Jun 28 08:04:30 PM PDT 24 |
| Finished | Jun 28 08:16:44 PM PDT 24 |
| Peak memory | 608264 kb |
| Host | smart-65f36c62-bda9-4c31-a4fc-345994609ddd |
| User | root |
| Command | /workspace/default/simv +i2c_idx=1 +sw_build_device=sim_dv +sw_images=i2c_host_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1851041722 -assert nopostproc + UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_i2c_host_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de fault.vdb -cm_log /dev/null -cm_name 0.chip_sw_i2c_host_tx_rx_idx1.1851041722 |
| Directory | /workspace/0.chip_sw_i2c_host_tx_rx_idx1/latest |
| Test location | /workspace/coverage/default/0.chip_sw_power_idle_load.2362173916 |
| Short name | T1238 |
| Test name | |
| Test status | |
| Simulation time | 4774897206 ps |
| CPU time | 683.63 seconds |
| Started | Jun 28 08:02:03 PM PDT 24 |
| Finished | Jun 28 08:13:28 PM PDT 24 |
| Peak memory | 606980 kb |
| Host | smart-b3b99e8b-18fb-4f7b-8006-5165840be14c |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=chip_power_idle_load:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2362173916 -assert nopostproc +UVM_TESTNA ME=chip_base_test +UVM_TEST_SEQ=chip_sw_power_idle_load_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_power_idle_load.2362173916 |
| Directory | /workspace/0.chip_sw_power_idle_load/latest |
| Test location | /workspace/coverage/default/0.chip_sw_flash_init.2297411870 |
| Short name | T224 |
| Test name | |
| Test status | |
| Simulation time | 25416797200 ps |
| CPU time | 2234.71 seconds |
| Started | Jun 28 08:02:05 PM PDT 24 |
| Finished | Jun 28 08:39:21 PM PDT 24 |
| Peak memory | 612072 kb |
| Host | smart-7d9bce1a-4373-468e-9da4-64cade956b07 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=25_000_000 +sw_build_device=sim_dv +sw_images=flash_init_test:0:test_in_rom:new_rules +cdc_instrumentation _enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2297411870 -as sert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_flash_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac e/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_flash_init.2297411870 |
| Directory | /workspace/0.chip_sw_flash_init/latest |
| Test location | /workspace/coverage/default/0.chip_sw_pwrmgr_full_aon_reset.3206464959 |
| Short name | T1208 |
| Test name | |
| Test status | |
| Simulation time | 7127327146 ps |
| CPU time | 560.93 seconds |
| Started | Jun 28 08:04:52 PM PDT 24 |
| Finished | Jun 28 08:14:14 PM PDT 24 |
| Peak memory | 609188 kb |
| Host | smart-c4a88324-afd8-435f-9916-c39ab650fa96 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=rstmgr_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3206464959 -assert nopostproc +UVM_TESTNAME=c hip_base_test +UVM_TEST_SEQ=chip_sw_full_aon_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_ log /dev/null -cm_name 0.chip_sw_pwrmgr_full_aon_reset.3206464959 |
| Directory | /workspace/0.chip_sw_pwrmgr_full_aon_reset/latest |
| Test location | /workspace/coverage/default/1.chip_sw_exit_test_unlocked_bootstrap.4200589009 |
| Short name | T145 |
| Test name | |
| Test status | |
| Simulation time | 58075515272 ps |
| CPU time | 10203.7 seconds |
| Started | Jun 28 08:05:47 PM PDT 24 |
| Finished | Jun 28 10:55:53 PM PDT 24 |
| Peak memory | 623468 kb |
| Host | smart-0ed23638-d348-42ff-9c3c-38ce73f5078d |
| User | root |
| Command | /workspace/default/simv +flash_program_latency=5 +sw_test_timeout_ns=150_000_000 +sw_build_device=sim_dv +sw_images=exit_test_unlocked_bootstrap:1:new _rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/s im.tcl +ntb_random_seed=4200589009 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_exit_test_unlocked_bootstrap_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_exit_test_unlocked_bootstrap.4200589009 |
| Directory | /workspace/1.chip_sw_exit_test_unlocked_bootstrap/latest |
| Test location | /workspace/coverage/default/0.chip_sw_rv_dm_access_after_escalation_reset.44362205 |
| Short name | T212 |
| Test name | |
| Test status | |
| Simulation time | 5742005871 ps |
| CPU time | 699.76 seconds |
| Started | Jun 28 08:01:36 PM PDT 24 |
| Finished | Jun 28 08:13:17 PM PDT 24 |
| Peak memory | 618304 kb |
| Host | smart-97424560-86a5-471c-9a33-8ff208544624 |
| User | root |
| Command | /workspace/default/simv +use_jtag_dmi=1 +sw_build_device=sim_dv +sw_images=alert_handler_escalation_test:1:new_rules,test_rom:0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44362205 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rv_dm_access_after_escalation_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_rv_dm_access_after_escalation_reset.44362205 |
| Directory | /workspace/0.chip_sw_rv_dm_access_after_escalation_reset/latest |
| Test location | /workspace/coverage/default/0.chip_tap_straps_dev.4286491602 |
| Short name | T642 |
| Test name | |
| Test status | |
| Simulation time | 11478278428 ps |
| CPU time | 1279.84 seconds |
| Started | Jun 28 08:01:33 PM PDT 24 |
| Finished | Jun 28 08:22:54 PM PDT 24 |
| Peak memory | 618224 kb |
| Host | smart-53ec9980-7a0a-4b92-9372-9962209a207d |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStDev +create_jtag_riscv_map=1 +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:test_in_rom: new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=4286491602 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_tap_straps_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_tap_straps_dev.4286491602 |
| Directory | /workspace/0.chip_tap_straps_dev/latest |
| Test location | /workspace/coverage/cover_reg_top/0.xbar_access_same_device_slow_rsp.2078923362 |
| Short name | T611 |
| Test name | |
| Test status | |
| Simulation time | 35155976339 ps |
| CPU time | 600.53 seconds |
| Started | Jun 28 08:26:36 PM PDT 24 |
| Finished | Jun 28 08:36:39 PM PDT 24 |
| Peak memory | 575376 kb |
| Host | smart-01946b99-068a-4d96-83bd-94d4898fcf07 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2078923362 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.xbar_access_same_d evice_slow_rsp.2078923362 |
| Directory | /workspace/0.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/4.chip_tl_errors.444067876 |
| Short name | T638 |
| Test name | |
| Test status | |
| Simulation time | 4338626188 ps |
| CPU time | 277.14 seconds |
| Started | Jun 28 08:30:26 PM PDT 24 |
| Finished | Jun 28 08:35:10 PM PDT 24 |
| Peak memory | 603548 kb |
| Host | smart-2ffdaa8b-4762-4f12-8537-78ac716f38c0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=444067876 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.chip_tl_errors.444067876 |
| Directory | /workspace/4.chip_tl_errors/latest |
| Test location | /workspace/coverage/default/1.chip_plic_all_irqs_10.3984785500 |
| Short name | T149 |
| Test name | |
| Test status | |
| Simulation time | 3790694200 ps |
| CPU time | 647.69 seconds |
| Started | Jun 28 08:11:15 PM PDT 24 |
| Finished | Jun 28 08:22:04 PM PDT 24 |
| Peak memory | 609124 kb |
| Host | smart-4b95a24e-79db-4a31-9866-b77a05bc8819 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=plic_all_irqs_test_10:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3984785500 -assert nopostproc +UVM_TESTN AME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log / dev/null -cm_name 1.chip_plic_all_irqs_10.3984785500 |
| Directory | /workspace/1.chip_plic_all_irqs_10/latest |
| Test location | /workspace/coverage/default/2.chip_sw_gpio.1791974755 |
| Short name | T38 |
| Test name | |
| Test status | |
| Simulation time | 4359847151 ps |
| CPU time | 595.28 seconds |
| Started | Jun 28 08:16:46 PM PDT 24 |
| Finished | Jun 28 08:26:43 PM PDT 24 |
| Peak memory | 606624 kb |
| Host | smart-3278c8d5-d248-4004-8b99-73563dc81a20 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=gpio_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1791974755 -assert nopostproc +UVM_TESTNAME=chip_bas e_test +UVM_TEST_SEQ=chip_sw_gpio_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm _name 2.chip_sw_gpio.1791974755 |
| Directory | /workspace/2.chip_sw_gpio/latest |
| Test location | /workspace/coverage/default/0.chip_sw_adc_ctrl_sleep_debug_cable_wakeup.3655783957 |
| Short name | T274 |
| Test name | |
| Test status | |
| Simulation time | 18682053736 ps |
| CPU time | 549.87 seconds |
| Started | Jun 28 08:06:41 PM PDT 24 |
| Finished | Jun 28 08:15:53 PM PDT 24 |
| Peak memory | 616544 kb |
| Host | smart-3250397b-c415-43d0-b543-cdf964fcf30d |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=adc_ctrl_sleep_debug_cable_wakeup_test:1:new_rules,test_rom: 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand om_seed=3655783957 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_adc_ctrl_sleep_debug_cable_wakeup_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_adc_ctrl_sleep_debug_cable_wakeup.3655783957 |
| Directory | /workspace/0.chip_sw_adc_ctrl_sleep_debug_cable_wakeup/latest |
| Test location | /workspace/coverage/default/0.chip_sw_edn_entropy_reqs.4091722933 |
| Short name | T1253 |
| Test name | |
| Test status | |
| Simulation time | 6209836248 ps |
| CPU time | 1118.92 seconds |
| Started | Jun 28 08:02:18 PM PDT 24 |
| Finished | Jun 28 08:20:58 PM PDT 24 |
| Peak memory | 609232 kb |
| Host | smart-f985c0d5-3598-43f8-97cf-7869cf2ecc41 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=15000000 +rng_srate_value_min=15 +rng_srate_value_max=30 +sw_build_device=sim_dv +sw_images=entropy_src_ed n_reqs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=4091722933 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_edn_entropy_reqs.4091722933 |
| Directory | /workspace/0.chip_sw_edn_entropy_reqs/latest |
| Test location | /workspace/coverage/default/2.chip_sw_otp_ctrl_vendor_test_csr_access.1097476014 |
| Short name | T157 |
| Test name | |
| Test status | |
| Simulation time | 2004322481 ps |
| CPU time | 100.12 seconds |
| Started | Jun 28 08:20:53 PM PDT 24 |
| Finished | Jun 28 08:22:42 PM PDT 24 |
| Peak memory | 615628 kb |
| Host | smart-92b1ae74-e234-40c4-99ec-49729a76f5a5 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=otp_ctrl_vendor_test_csr_access_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1097476014 -assert nopost proc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_otp_ctrl_vendor_test_csr_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_otp_ctrl_vendor_test_csr_access.1097476014 |
| Directory | /workspace/2.chip_sw_otp_ctrl_vendor_test_csr_access/latest |
| Test location | /workspace/coverage/default/0.chip_sw_i2c_host_tx_rx.465038478 |
| Short name | T99 |
| Test name | |
| Test status | |
| Simulation time | 4457401464 ps |
| CPU time | 923.19 seconds |
| Started | Jun 28 08:06:58 PM PDT 24 |
| Finished | Jun 28 08:22:23 PM PDT 24 |
| Peak memory | 607920 kb |
| Host | smart-f839a902-6dd7-45a2-988a-75a7f56ec879 |
| User | root |
| Command | /workspace/default/simv +i2c_idx=0 +sw_build_device=sim_dv +sw_images=i2c_host_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=465038478 -assert nopostproc +U VM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_i2c_host_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def ault.vdb -cm_log /dev/null -cm_name 0.chip_sw_i2c_host_tx_rx.465038478 |
| Directory | /workspace/0.chip_sw_i2c_host_tx_rx/latest |
| Test location | /workspace/coverage/default/0.chip_sw_plic_sw_irq.2381434015 |
| Short name | T249 |
| Test name | |
| Test status | |
| Simulation time | 2991948940 ps |
| CPU time | 282.72 seconds |
| Started | Jun 28 08:03:06 PM PDT 24 |
| Finished | Jun 28 08:07:51 PM PDT 24 |
| Peak memory | 607124 kb |
| Host | smart-8b629b57-6e0b-42e2-9c17-acb93c818dea |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=plic_sw_irq_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2381434015 -assert nopostproc +UVM_TESTNAME=c hip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n ull -cm_name 0.chip_sw_plic_sw_irq.2381434015 |
| Directory | /workspace/0.chip_sw_plic_sw_irq/latest |
| Test location | /workspace/coverage/cover_reg_top/2.chip_csr_hw_reset.1689416153 |
| Short name | T134 |
| Test name | |
| Test status | |
| Simulation time | 5144094511 ps |
| CPU time | 208.59 seconds |
| Started | Jun 28 08:29:34 PM PDT 24 |
| Finished | Jun 28 08:33:10 PM PDT 24 |
| Peak memory | 662260 kb |
| Host | smart-bbf2a332-8faa-47ea-a3b5-c0e03310d5eb |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1689416153 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.chip_csr_hw_r eset.1689416153 |
| Directory | /workspace/2.chip_csr_hw_reset/latest |
| Test location | /workspace/coverage/default/0.chip_sw_hmac_enc_idle.182900094 |
| Short name | T1017 |
| Test name | |
| Test status | |
| Simulation time | 2646192692 ps |
| CPU time | 276.24 seconds |
| Started | Jun 28 08:01:46 PM PDT 24 |
| Finished | Jun 28 08:06:24 PM PDT 24 |
| Peak memory | 607272 kb |
| Host | smart-96a67793-8257-404c-9020-bf699d91e4cf |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=hmac_enc_idle_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=182900094 -assert nopostproc +UVM_TESTNAME= chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/ null -cm_name 0.chip_sw_hmac_enc_idle.182900094 |
| Directory | /workspace/0.chip_sw_hmac_enc_idle/latest |
| Test location | /workspace/coverage/default/0.chip_sw_keymgr_sideload_aes.2200109995 |
| Short name | T216 |
| Test name | |
| Test status | |
| Simulation time | 11715435576 ps |
| CPU time | 2760.82 seconds |
| Started | Jun 28 08:01:41 PM PDT 24 |
| Finished | Jun 28 08:47:43 PM PDT 24 |
| Peak memory | 609356 kb |
| Host | smart-31835767-1c7e-487c-9c44-c596f61e6fd0 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=20_000_000 +sw_build_device=sim_dv +sw_images=keymgr_sideload_aes_test:1:new_rules,test_rom:0 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=220010 9995 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_keymgr_sideload_aes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_keymgr_sideload_aes.2200109995 |
| Directory | /workspace/0.chip_sw_keymgr_sideload_aes/latest |
| Test location | /workspace/coverage/default/0.chip_sw_lc_ctrl_program_error.670427876 |
| Short name | T163 |
| Test name | |
| Test status | |
| Simulation time | 6004164824 ps |
| CPU time | 581.84 seconds |
| Started | Jun 28 08:04:41 PM PDT 24 |
| Finished | Jun 28 08:14:24 PM PDT 24 |
| Peak memory | 608724 kb |
| Host | smart-a5ffdf96-9337-40c4-9b23-94d238f677b5 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=lc_ctrl_program_error:1:new_rules,test_rom:0 + cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_ seed=670427876 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_program_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_lc_ctrl_program_error.670427876 |
| Directory | /workspace/0.chip_sw_lc_ctrl_program_error/latest |
| Test location | /workspace/coverage/default/0.chip_sw_pwrmgr_deep_sleep_power_glitch_reset.2959034892 |
| Short name | T919 |
| Test name | |
| Test status | |
| Simulation time | 7639163300 ps |
| CPU time | 427.46 seconds |
| Started | Jun 28 08:05:32 PM PDT 24 |
| Finished | Jun 28 08:12:40 PM PDT 24 |
| Peak memory | 615396 kb |
| Host | smart-65027cbc-f4ce-410d-92b2-841d57d323da |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=pwrmgr_deep_sleep_power_glitch_test:1:new_rules,test_rom :0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=2959034892 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_deep_power_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_deep_sleep_power_glitch_reset.2959034892 |
| Directory | /workspace/0.chip_sw_pwrmgr_deep_sleep_power_glitch_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/0.chip_tl_errors.1054156144 |
| Short name | T640 |
| Test name | |
| Test status | |
| Simulation time | 3859027500 ps |
| CPU time | 189.17 seconds |
| Started | Jun 28 08:26:14 PM PDT 24 |
| Finished | Jun 28 08:29:33 PM PDT 24 |
| Peak memory | 597436 kb |
| Host | smart-7d27dd26-ad14-4648-a720-66c1f7d8fe68 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1054156144 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.chip_tl_errors.1054156144 |
| Directory | /workspace/0.chip_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/1.xbar_stress_all_with_error.4086957116 |
| Short name | T2437 |
| Test name | |
| Test status | |
| Simulation time | 4396804964 ps |
| CPU time | 383.64 seconds |
| Started | Jun 28 08:28:39 PM PDT 24 |
| Finished | Jun 28 08:35:17 PM PDT 24 |
| Peak memory | 574424 kb |
| Host | smart-a3493204-8cb8-4992-97b0-aee7795c0849 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4086957116 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.xbar_stress_all_with_error.4086957116 |
| Directory | /workspace/1.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/10.chip_tl_errors.2456134662 |
| Short name | T546 |
| Test name | |
| Test status | |
| Simulation time | 2890569650 ps |
| CPU time | 214.42 seconds |
| Started | Jun 28 08:34:07 PM PDT 24 |
| Finished | Jun 28 08:37:52 PM PDT 24 |
| Peak memory | 597432 kb |
| Host | smart-2a79406a-bbf4-448f-baa0-0aec80bdac55 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2456134662 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.chip_tl_errors.2456134662 |
| Directory | /workspace/10.chip_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/2.xbar_stress_all_with_reset_error.3933101547 |
| Short name | T602 |
| Test name | |
| Test status | |
| Simulation time | 2595089725 ps |
| CPU time | 322.83 seconds |
| Started | Jun 28 08:29:41 PM PDT 24 |
| Finished | Jun 28 08:35:14 PM PDT 24 |
| Peak memory | 574432 kb |
| Host | smart-f10762de-c5e9-4737-8e18-b7bf3a8f3b4a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3933101547 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.xbar_stress_all _with_reset_error.3933101547 |
| Directory | /workspace/2.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/25.xbar_stress_all_with_error.4104655908 |
| Short name | T606 |
| Test name | |
| Test status | |
| Simulation time | 3339411068 ps |
| CPU time | 279.22 seconds |
| Started | Jun 28 08:38:42 PM PDT 24 |
| Finished | Jun 28 08:43:24 PM PDT 24 |
| Peak memory | 574424 kb |
| Host | smart-1fc44073-2f1f-46e9-98ca-f65e0f9699ce |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4104655908 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.xbar_stress_all_with_error.4104655908 |
| Directory | /workspace/25.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/73.xbar_stress_all_with_error.2123363990 |
| Short name | T652 |
| Test name | |
| Test status | |
| Simulation time | 8861267887 ps |
| CPU time | 305.65 seconds |
| Started | Jun 28 08:48:01 PM PDT 24 |
| Finished | Jun 28 08:53:28 PM PDT 24 |
| Peak memory | 574368 kb |
| Host | smart-6331c06b-baf3-4784-a61d-8513e86700d1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2123363990 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 73.xbar_stress_all_with_error.2123363990 |
| Directory | /workspace/73.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/77.xbar_stress_all_with_error.3719905561 |
| Short name | T648 |
| Test name | |
| Test status | |
| Simulation time | 14620509081 ps |
| CPU time | 470.15 seconds |
| Started | Jun 28 08:48:30 PM PDT 24 |
| Finished | Jun 28 08:56:35 PM PDT 24 |
| Peak memory | 574648 kb |
| Host | smart-be7ab1ca-2b89-4464-b74c-44dd2253a88b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3719905561 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 77.xbar_stress_all_with_error.3719905561 |
| Directory | /workspace/77.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/88.xbar_stress_all_with_reset_error.2399181790 |
| Short name | T597 |
| Test name | |
| Test status | |
| Simulation time | 903298762 ps |
| CPU time | 272.57 seconds |
| Started | Jun 28 08:50:22 PM PDT 24 |
| Finished | Jun 28 08:55:30 PM PDT 24 |
| Peak memory | 574372 kb |
| Host | smart-50ecd0cc-4848-4154-9f4a-e572dcf7726d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2399181790 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 88.xbar_stress_al l_with_reset_error.2399181790 |
| Directory | /workspace/88.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/default/0.chip_sw_pwrmgr_lowpower_cancel.1831505113 |
| Short name | T335 |
| Test name | |
| Test status | |
| Simulation time | 4485461780 ps |
| CPU time | 437.76 seconds |
| Started | Jun 28 08:01:47 PM PDT 24 |
| Finished | Jun 28 08:09:05 PM PDT 24 |
| Peak memory | 609252 kb |
| Host | smart-d5b969fe-68af-4553-a0fb-b126a51b1183 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_lowpower_cancel_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1831505113 -assert nopostproc +UVM _TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm _log /dev/null -cm_name 0.chip_sw_pwrmgr_lowpower_cancel.1831505113 |
| Directory | /workspace/0.chip_sw_pwrmgr_lowpower_cancel/latest |
| Test location | /workspace/coverage/default/0.chip_sw_rv_core_ibex_nmi_irq.2925763891 |
| Short name | T675 |
| Test name | |
| Test status | |
| Simulation time | 4859630902 ps |
| CPU time | 770.41 seconds |
| Started | Jun 28 08:06:10 PM PDT 24 |
| Finished | Jun 28 08:19:02 PM PDT 24 |
| Peak memory | 607116 kb |
| Host | smart-bafd07ee-c70a-4c04-a8ff-de3ad02ebc6c |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=10_000_000 +sw_build_device=sim_dv +sw_images=rv_core_ibex_nmi_irq_test:1:new_rules,test_rom:0 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29257 63891 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_rv_core_ibex_nmi_irq.2925763891 |
| Directory | /workspace/0.chip_sw_rv_core_ibex_nmi_irq/latest |
| Test location | /workspace/coverage/default/1.chip_sw_rstmgr_alert_info.1252153652 |
| Short name | T153 |
| Test name | |
| Test status | |
| Simulation time | 13011869380 ps |
| CPU time | 2373.33 seconds |
| Started | Jun 28 08:05:04 PM PDT 24 |
| Finished | Jun 28 08:44:39 PM PDT 24 |
| Peak memory | 609192 kb |
| Host | smart-605b68fa-78f4-491d-bdce-c4751003c304 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=30_000_000 +en_scb_tl_err_chk=0 +sw_build_device=sim_dv +sw_images=rstmgr_alert_info_test:1:new_rules,test _rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb _random_seed=1252153652 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_rstmgr_alert_info.1252153652 |
| Directory | /workspace/1.chip_sw_rstmgr_alert_info/latest |
| Test location | /workspace/coverage/cover_reg_top/0.chip_rv_dm_lc_disabled.3116428619 |
| Short name | T2831 |
| Test name | |
| Test status | |
| Simulation time | 12052346634 ps |
| CPU time | 500.12 seconds |
| Started | Jun 28 08:26:59 PM PDT 24 |
| Finished | Jun 28 08:35:21 PM PDT 24 |
| Peak memory | 590132 kb |
| Host | smart-731ba0c3-7a41-4dff-a371-0260d85992af |
| User | root |
| Command | /workspace/cover_reg_top/simv +en_scb=0 +en_scb_tl_err_chk=0 +use_jtag_dmi=1 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3116428619 -assert nopostproc +UVM_TESTNAME=chip_base_t est +UVM_TEST_SEQ=chip_rv_dm_lc_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.chip_rv_dm_lc_disabled.3116428619 |
| Directory | /workspace/0.chip_rv_dm_lc_disabled/latest |
| Test location | /workspace/coverage/cover_reg_top/4.chip_csr_hw_reset.2395463013 |
| Short name | T132 |
| Test name | |
| Test status | |
| Simulation time | 4872608860 ps |
| CPU time | 275.18 seconds |
| Started | Jun 28 08:30:51 PM PDT 24 |
| Finished | Jun 28 08:35:27 PM PDT 24 |
| Peak memory | 661396 kb |
| Host | smart-992f279d-ecea-48ab-8f72-734830da3150 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2395463013 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.chip_csr_hw_r eset.2395463013 |
| Directory | /workspace/4.chip_csr_hw_reset/latest |
| Test location | /workspace/coverage/default/0.chip_sw_edn_boot_mode.293855638 |
| Short name | T630 |
| Test name | |
| Test status | |
| Simulation time | 3137559912 ps |
| CPU time | 624.37 seconds |
| Started | Jun 28 08:07:22 PM PDT 24 |
| Finished | Jun 28 08:17:48 PM PDT 24 |
| Peak memory | 609312 kb |
| Host | smart-095e6ecc-132f-44d0-b96a-4f6ca971da9a |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +rng_srate_value=5 +accelerate_cold_power_up_time=3 +accelerate_regulators_power_up_time=2 +sw_ build_device=sim_dv +sw_images=edn_boot_mode:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=293855638 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ= chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_edn_b oot_mode.293855638 |
| Directory | /workspace/0.chip_sw_edn_boot_mode/latest |
| Test location | /workspace/coverage/default/0.chip_sw_otbn_ecdsa_op_irq.1245547282 |
| Short name | T435 |
| Test name | |
| Test status | |
| Simulation time | 17062255520 ps |
| CPU time | 3792.06 seconds |
| Started | Jun 28 08:06:14 PM PDT 24 |
| Finished | Jun 28 09:09:28 PM PDT 24 |
| Peak memory | 609328 kb |
| Host | smart-07a49e93-0258-4e82-bab5-44c1ac731fdc |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=28_000_000 +rng_srate_value=30 +sw_build_device=sim_dv +sw_images=otbn_ecdsa_op_irq_test:1:new_rules,test_ rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ random_seed=1245547282 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_otbn_ecdsa_op_irq.1245547282 |
| Directory | /workspace/0.chip_sw_otbn_ecdsa_op_irq/latest |
| Test location | /workspace/coverage/default/2.chip_sw_csrng_edn_concurrency_reduced_freq.1255756506 |
| Short name | T632 |
| Test name | |
| Test status | |
| Simulation time | 35643698919 ps |
| CPU time | 5284.16 seconds |
| Started | Jun 28 08:22:17 PM PDT 24 |
| Finished | Jun 28 09:50:26 PM PDT 24 |
| Peak memory | 609316 kb |
| Host | smart-c2dd8288-6388-41a5-a284-ee26efa11426 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=360_000_000 +rng_srate_value_min=15 +rng_srate_value_max=20 +cal_sys_clk_70mhz=1 +en_jitter=1 +accelerate_ cold_power_up_time=3 +accelerate_regulators_power_up_time=2 +sw_build_device=sim_dv +sw_images=csrng_edn_concurrency_test:1:new_rules,test_rom:0 + cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_ seed=1255756506 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_csrng_edn_concurrency_reduced_freq.1255756506 |
| Directory | /workspace/2.chip_sw_csrng_edn_concurrency_reduced_freq/latest |
| Test location | /workspace/coverage/default/0.chip_sw_rv_core_ibex_lockstep_glitch.2394880458 |
| Short name | T384 |
| Test name | |
| Test status | |
| Simulation time | 2745237780 ps |
| CPU time | 224.65 seconds |
| Started | Jun 28 08:01:41 PM PDT 24 |
| Finished | Jun 28 08:05:27 PM PDT 24 |
| Peak memory | 636308 kb |
| Host | smart-32361cb2-13c1-4c9a-ae1a-617db25698c9 |
| User | root |
| Command | /workspace/default/simv +disable_assert_final_checks +sw_build_device=sim_dv +sw_images=aes_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2394880458 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rv_core_ibex_lockstep_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_rv_core_ibex_lockstep_glitch.2394880458 |
| Directory | /workspace/0.chip_sw_rv_core_ibex_lockstep_glitch/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_bad_b_good_dev.3214132452 |
| Short name | T1006 |
| Test name | |
| Test status | |
| Simulation time | 24081937190 ps |
| CPU time | 7179.32 seconds |
| Started | Jun 28 08:10:36 PM PDT 24 |
| Finished | Jun 28 10:10:16 PM PDT 24 |
| Peak memory | 608364 kb |
| Host | smart-e7f5c6ac-ba86-445b-867e-31f90a041520 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_corrupted:1: ot_flash_binary:signed:fake_ecdsa_prod_key_0,empty_test_slot_b_fake_ecdsa_prod_key_0:2:ot_flash_binary,otp_img_boot_policy_valid_dev:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=3214132452 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_boot_policy_valid_a_bad_b_good_dev.3214132452 |
| Directory | /workspace/0.rom_e2e_boot_policy_valid_a_bad_b_good_dev/latest |
| Test location | /workspace/coverage/cover_reg_top/0.chip_csr_aliasing.3493251072 |
| Short name | T2866 |
| Test name | |
| Test status | |
| Simulation time | 69551069822 ps |
| CPU time | 8929.5 seconds |
| Started | Jun 28 08:26:17 PM PDT 24 |
| Finished | Jun 28 10:55:16 PM PDT 24 |
| Peak memory | 637108 kb |
| Host | smart-130e2a3c-ded5-4227-8f32-89f2c891c6b5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +csr_aliasing +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3493251072 -assert nopostproc +UVM_TESTNAME=chip_ base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/ null -cm_name 0.chip_csr_aliasing.3493251072 |
| Directory | /workspace/0.chip_csr_aliasing/latest |
| Test location | /workspace/coverage/cover_reg_top/0.chip_csr_bit_bash.2649811649 |
| Short name | T1451 |
| Test name | |
| Test status | |
| Simulation time | 6324521570 ps |
| CPU time | 693.09 seconds |
| Started | Jun 28 08:26:26 PM PDT 24 |
| Finished | Jun 28 08:38:02 PM PDT 24 |
| Peak memory | 588992 kb |
| Host | smart-bafdbeda-0b97-4631-a7a8-95e93a9413de |
| User | root |
| Command | /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +num_test_csrs=200 +csr_bit_bash +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2649811649 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to p.vdb -cm_log /dev/null -cm_name 0.chip_csr_bit_bash.2649811649 |
| Directory | /workspace/0.chip_csr_bit_bash/latest |
| Test location | /workspace/coverage/cover_reg_top/0.chip_csr_hw_reset.3383229695 |
| Short name | T133 |
| Test name | |
| Test status | |
| Simulation time | 6202111120 ps |
| CPU time | 438.18 seconds |
| Started | Jun 28 08:27:45 PM PDT 24 |
| Finished | Jun 28 08:35:13 PM PDT 24 |
| Peak memory | 662788 kb |
| Host | smart-4957ff24-b8c8-46dd-a25d-8668948fa709 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3383229695 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.chip_csr_hw_r eset.3383229695 |
| Directory | /workspace/0.chip_csr_hw_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/0.chip_csr_rw.745522662 |
| Short name | T1883 |
| Test name | |
| Test status | |
| Simulation time | 5533963260 ps |
| CPU time | 785.73 seconds |
| Started | Jun 28 08:27:36 PM PDT 24 |
| Finished | Jun 28 08:40:47 PM PDT 24 |
| Peak memory | 597740 kb |
| Host | smart-b25989ce-c16b-45e3-b3be-39b916d8e40e |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=745522662 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.chip_csr_rw.745522662 |
| Directory | /workspace/0.chip_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/0.chip_prim_tl_access.626879305 |
| Short name | T2450 |
| Test name | |
| Test status | |
| Simulation time | 11272887522 ps |
| CPU time | 556.39 seconds |
| Started | Jun 28 08:26:20 PM PDT 24 |
| Finished | Jun 28 08:35:44 PM PDT 24 |
| Peak memory | 589084 kb |
| Host | smart-e92d4e98-0150-4193-b5c4-d3c5d3a4c8d7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +en_scb=0 +en_scb_tl_err_chk=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=626879305 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ =chip_prim_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0 .chip_prim_tl_access.626879305 |
| Directory | /workspace/0.chip_prim_tl_access/latest |
| Test location | /workspace/coverage/cover_reg_top/0.chip_same_csr_outstanding.3167095674 |
| Short name | T141 |
| Test name | |
| Test status | |
| Simulation time | 15490047959 ps |
| CPU time | 2062.52 seconds |
| Started | Jun 28 08:26:11 PM PDT 24 |
| Finished | Jun 28 09:00:45 PM PDT 24 |
| Peak memory | 591844 kb |
| Host | smart-d627950e-4466-4a63-bd23-2beb6ef20897 |
| User | root |
| Command | /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +run_same_csr_outstanding +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3167095674 -assert nopostproc +UVM_TE STNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb - cm_log /dev/null -cm_name 0.chip_same_csr_outstanding.3167095674 |
| Directory | /workspace/0.chip_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/0.xbar_access_same_device.1248958441 |
| Short name | T801 |
| Test name | |
| Test status | |
| Simulation time | 2002385413 ps |
| CPU time | 98.66 seconds |
| Started | Jun 28 08:26:34 PM PDT 24 |
| Finished | Jun 28 08:28:15 PM PDT 24 |
| Peak memory | 575236 kb |
| Host | smart-ac2e3d7a-9c26-4278-86e8-3d3a00f680ef |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1248958441 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.xbar_access_same_device. 1248958441 |
| Directory | /workspace/0.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/0.xbar_error_and_unmapped_addr.1654338936 |
| Short name | T1652 |
| Test name | |
| Test status | |
| Simulation time | 41516961 ps |
| CPU time | 8.7 seconds |
| Started | Jun 28 08:26:41 PM PDT 24 |
| Finished | Jun 28 08:26:51 PM PDT 24 |
| Peak memory | 574184 kb |
| Host | smart-af0720cb-4674-4b7c-a95e-9ab36e4b106a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1654338936 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.xbar_error_and_unmapped_addr .1654338936 |
| Directory | /workspace/0.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/0.xbar_error_random.1153071537 |
| Short name | T2158 |
| Test name | |
| Test status | |
| Simulation time | 105844811 ps |
| CPU time | 12.52 seconds |
| Started | Jun 28 08:26:36 PM PDT 24 |
| Finished | Jun 28 08:26:50 PM PDT 24 |
| Peak memory | 574356 kb |
| Host | smart-23cf45dc-9a98-4553-ae13-9e7ef4aa99d6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1153071537 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.xbar_error_random.1153071537 |
| Directory | /workspace/0.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/0.xbar_random.2499022522 |
| Short name | T595 |
| Test name | |
| Test status | |
| Simulation time | 2051975406 ps |
| CPU time | 85.81 seconds |
| Started | Jun 28 08:26:36 PM PDT 24 |
| Finished | Jun 28 08:28:04 PM PDT 24 |
| Peak memory | 574232 kb |
| Host | smart-2c9bf5a4-e4fd-4161-9ebb-3d1e073d8d44 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2499022522 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.xbar_random.2499022522 |
| Directory | /workspace/0.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/0.xbar_random_large_delays.2703675049 |
| Short name | T2086 |
| Test name | |
| Test status | |
| Simulation time | 50277479510 ps |
| CPU time | 497.83 seconds |
| Started | Jun 28 08:26:36 PM PDT 24 |
| Finished | Jun 28 08:34:56 PM PDT 24 |
| Peak memory | 575316 kb |
| Host | smart-199fae55-6a90-445f-8f15-0ead97226284 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2703675049 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.xbar_random_large_delays.2703675049 |
| Directory | /workspace/0.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/0.xbar_random_slow_rsp.313315454 |
| Short name | T2148 |
| Test name | |
| Test status | |
| Simulation time | 3186799497 ps |
| CPU time | 59.83 seconds |
| Started | Jun 28 08:26:46 PM PDT 24 |
| Finished | Jun 28 08:27:48 PM PDT 24 |
| Peak memory | 574064 kb |
| Host | smart-cfaaf9f1-fea7-43c2-ae64-3f4786b73fc8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=313315454 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.xbar_random_slow_rsp.313315454 |
| Directory | /workspace/0.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/0.xbar_random_zero_delays.3460542396 |
| Short name | T2120 |
| Test name | |
| Test status | |
| Simulation time | 541655517 ps |
| CPU time | 56.23 seconds |
| Started | Jun 28 08:26:34 PM PDT 24 |
| Finished | Jun 28 08:27:32 PM PDT 24 |
| Peak memory | 575252 kb |
| Host | smart-8fe7c1c4-fbcb-449d-bc07-701363529024 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3460542396 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.xbar_random_zero_dela ys.3460542396 |
| Directory | /workspace/0.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/0.xbar_same_source.2774896433 |
| Short name | T2110 |
| Test name | |
| Test status | |
| Simulation time | 96078400 ps |
| CPU time | 12.06 seconds |
| Started | Jun 28 08:27:11 PM PDT 24 |
| Finished | Jun 28 08:27:24 PM PDT 24 |
| Peak memory | 575216 kb |
| Host | smart-be669a00-7202-49a5-a462-a24b8929867c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2774896433 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.xbar_same_source.2774896433 |
| Directory | /workspace/0.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/0.xbar_smoke.4024625664 |
| Short name | T2684 |
| Test name | |
| Test status | |
| Simulation time | 230711231 ps |
| CPU time | 10.83 seconds |
| Started | Jun 28 08:26:13 PM PDT 24 |
| Finished | Jun 28 08:26:34 PM PDT 24 |
| Peak memory | 574160 kb |
| Host | smart-409ba5cc-0672-455f-8dae-487b322b5461 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4024625664 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.xbar_smoke.4024625664 |
| Directory | /workspace/0.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/0.xbar_smoke_large_delays.164056824 |
| Short name | T2136 |
| Test name | |
| Test status | |
| Simulation time | 5987470666 ps |
| CPU time | 58.83 seconds |
| Started | Jun 28 08:26:48 PM PDT 24 |
| Finished | Jun 28 08:27:48 PM PDT 24 |
| Peak memory | 574240 kb |
| Host | smart-a1745ed1-85bb-418f-8c87-c7bec3290fae |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=164056824 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.xbar_smoke_large_delays.164056824 |
| Directory | /workspace/0.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/0.xbar_smoke_slow_rsp.1141767743 |
| Short name | T2447 |
| Test name | |
| Test status | |
| Simulation time | 5257149909 ps |
| CPU time | 96.46 seconds |
| Started | Jun 28 08:26:42 PM PDT 24 |
| Finished | Jun 28 08:28:20 PM PDT 24 |
| Peak memory | 574184 kb |
| Host | smart-2bf03eac-4163-4bb7-a03d-cc25232fa457 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1141767743 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.xbar_smoke_slow_rsp.1141767743 |
| Directory | /workspace/0.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/0.xbar_smoke_zero_delays.2758567278 |
| Short name | T1680 |
| Test name | |
| Test status | |
| Simulation time | 54051300 ps |
| CPU time | 8.09 seconds |
| Started | Jun 28 08:26:34 PM PDT 24 |
| Finished | Jun 28 08:26:45 PM PDT 24 |
| Peak memory | 574132 kb |
| Host | smart-5664957b-ca0b-4363-854b-9af13a1fa065 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2758567278 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.xbar_smoke_zero_delays .2758567278 |
| Directory | /workspace/0.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/0.xbar_stress_all.1047692055 |
| Short name | T465 |
| Test name | |
| Test status | |
| Simulation time | 4050837833 ps |
| CPU time | 366.81 seconds |
| Started | Jun 28 08:26:33 PM PDT 24 |
| Finished | Jun 28 08:32:42 PM PDT 24 |
| Peak memory | 575444 kb |
| Host | smart-303ac2cc-82ae-4d5f-9e8a-d74c3748f7af |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1047692055 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.xbar_stress_all.1047692055 |
| Directory | /workspace/0.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/0.xbar_stress_all_with_error.1525465470 |
| Short name | T2090 |
| Test name | |
| Test status | |
| Simulation time | 16413845378 ps |
| CPU time | 728.57 seconds |
| Started | Jun 28 08:27:16 PM PDT 24 |
| Finished | Jun 28 08:39:25 PM PDT 24 |
| Peak memory | 574664 kb |
| Host | smart-5f2faeda-febb-4492-91c5-3402a7fc0573 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1525465470 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.xbar_stress_all_with_error.1525465470 |
| Directory | /workspace/0.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/0.xbar_stress_all_with_rand_reset.3203031322 |
| Short name | T1487 |
| Test name | |
| Test status | |
| Simulation time | 219807170 ps |
| CPU time | 159.08 seconds |
| Started | Jun 28 08:27:25 PM PDT 24 |
| Finished | Jun 28 08:30:07 PM PDT 24 |
| Peak memory | 576372 kb |
| Host | smart-73eeb50b-baf6-4bc9-a875-2ac3e8e37310 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3203031322 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.xbar_stress_all_ with_rand_reset.3203031322 |
| Directory | /workspace/0.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/0.xbar_stress_all_with_reset_error.1890441178 |
| Short name | T1837 |
| Test name | |
| Test status | |
| Simulation time | 4092223289 ps |
| CPU time | 326.77 seconds |
| Started | Jun 28 08:27:38 PM PDT 24 |
| Finished | Jun 28 08:33:12 PM PDT 24 |
| Peak memory | 574656 kb |
| Host | smart-3847a3fc-9417-4dc1-bcb9-28d7592161fd |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1890441178 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.xbar_stress_all _with_reset_error.1890441178 |
| Directory | /workspace/0.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/0.xbar_unmapped_addr.1683384956 |
| Short name | T2353 |
| Test name | |
| Test status | |
| Simulation time | 791023475 ps |
| CPU time | 45.12 seconds |
| Started | Jun 28 08:26:41 PM PDT 24 |
| Finished | Jun 28 08:27:28 PM PDT 24 |
| Peak memory | 575260 kb |
| Host | smart-d8c080cb-aa63-4669-8316-969be8456e13 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1683384956 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.xbar_unmapped_addr.1683384956 |
| Directory | /workspace/0.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/1.chip_csr_aliasing.3015433762 |
| Short name | T2790 |
| Test name | |
| Test status | |
| Simulation time | 38638983875 ps |
| CPU time | 5092.34 seconds |
| Started | Jun 28 08:28:10 PM PDT 24 |
| Finished | Jun 28 09:53:05 PM PDT 24 |
| Peak memory | 592188 kb |
| Host | smart-f7bc7368-64f8-4048-ab7d-df120c7dcc11 |
| User | root |
| Command | /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +csr_aliasing +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3015433762 -assert nopostproc +UVM_TESTNAME=chip_ base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/ null -cm_name 1.chip_csr_aliasing.3015433762 |
| Directory | /workspace/1.chip_csr_aliasing/latest |
| Test location | /workspace/coverage/cover_reg_top/1.chip_csr_bit_bash.66436979 |
| Short name | T2153 |
| Test name | |
| Test status | |
| Simulation time | 36245434986 ps |
| CPU time | 3420.94 seconds |
| Started | Jun 28 08:27:35 PM PDT 24 |
| Finished | Jun 28 09:24:41 PM PDT 24 |
| Peak memory | 589152 kb |
| Host | smart-209479f6-aa05-4bc3-9034-b48ad936a7ec |
| User | root |
| Command | /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +num_test_csrs=200 +csr_bit_bash +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66436979 -assert nopostproc +U VM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top. vdb -cm_log /dev/null -cm_name 1.chip_csr_bit_bash.66436979 |
| Directory | /workspace/1.chip_csr_bit_bash/latest |
| Test location | /workspace/coverage/cover_reg_top/1.chip_csr_rw.32979784 |
| Short name | T425 |
| Test name | |
| Test status | |
| Simulation time | 5726339000 ps |
| CPU time | 611.4 seconds |
| Started | Jun 28 08:28:40 PM PDT 24 |
| Finished | Jun 28 08:39:09 PM PDT 24 |
| Peak memory | 597528 kb |
| Host | smart-1d871b8a-69c7-49da-aa1b-755e385db2b8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32979784 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.chip_csr_rw.32979784 |
| Directory | /workspace/1.chip_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/1.chip_prim_tl_access.2934800356 |
| Short name | T1354 |
| Test name | |
| Test status | |
| Simulation time | 5687209040 ps |
| CPU time | 292.93 seconds |
| Started | Jun 28 08:28:09 PM PDT 24 |
| Finished | Jun 28 08:33:04 PM PDT 24 |
| Peak memory | 589108 kb |
| Host | smart-d1af8c20-6173-494f-a0a2-a0c1c887e7ae |
| User | root |
| Command | /workspace/cover_reg_top/simv +en_scb=0 +en_scb_tl_err_chk=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2934800356 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SE Q=chip_prim_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.chip_prim_tl_access.2934800356 |
| Directory | /workspace/1.chip_prim_tl_access/latest |
| Test location | /workspace/coverage/cover_reg_top/1.chip_rv_dm_lc_disabled.1497376221 |
| Short name | T2475 |
| Test name | |
| Test status | |
| Simulation time | 16236553379 ps |
| CPU time | 551.38 seconds |
| Started | Jun 28 08:28:13 PM PDT 24 |
| Finished | Jun 28 08:37:28 PM PDT 24 |
| Peak memory | 589948 kb |
| Host | smart-4e1d1ef7-ae79-4e21-8ae4-e36b4c2dea9e |
| User | root |
| Command | /workspace/cover_reg_top/simv +en_scb=0 +en_scb_tl_err_chk=0 +use_jtag_dmi=1 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1497376221 -assert nopostproc +UVM_TESTNAME=chip_base_t est +UVM_TEST_SEQ=chip_rv_dm_lc_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.chip_rv_dm_lc_disabled.1497376221 |
| Directory | /workspace/1.chip_rv_dm_lc_disabled/latest |
| Test location | /workspace/coverage/cover_reg_top/1.chip_same_csr_outstanding.2197173512 |
| Short name | T426 |
| Test name | |
| Test status | |
| Simulation time | 29787238285 ps |
| CPU time | 3859.41 seconds |
| Started | Jun 28 08:28:04 PM PDT 24 |
| Finished | Jun 28 09:32:24 PM PDT 24 |
| Peak memory | 591972 kb |
| Host | smart-7efffe99-a3c8-4ba2-bd73-3cc06e42fcab |
| User | root |
| Command | /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +run_same_csr_outstanding +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2197173512 -assert nopostproc +UVM_TE STNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb - cm_log /dev/null -cm_name 1.chip_same_csr_outstanding.2197173512 |
| Directory | /workspace/1.chip_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/1.chip_tl_errors.776157816 |
| Short name | T637 |
| Test name | |
| Test status | |
| Simulation time | 2714694691 ps |
| CPU time | 79.27 seconds |
| Started | Jun 28 08:28:10 PM PDT 24 |
| Finished | Jun 28 08:29:32 PM PDT 24 |
| Peak memory | 597372 kb |
| Host | smart-e15005fd-7596-46c8-a675-c95b10b148cd |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=776157816 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.chip_tl_errors.776157816 |
| Directory | /workspace/1.chip_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/1.xbar_access_same_device.3893342488 |
| Short name | T1441 |
| Test name | |
| Test status | |
| Simulation time | 2222423432 ps |
| CPU time | 107.78 seconds |
| Started | Jun 28 08:28:12 PM PDT 24 |
| Finished | Jun 28 08:30:03 PM PDT 24 |
| Peak memory | 574244 kb |
| Host | smart-69d43a7c-b84b-4b4c-9b24-f0104e9090c8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3893342488 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.xbar_access_same_device. 3893342488 |
| Directory | /workspace/1.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/1.xbar_access_same_device_slow_rsp.1273654573 |
| Short name | T2369 |
| Test name | |
| Test status | |
| Simulation time | 103914072696 ps |
| CPU time | 1777.62 seconds |
| Started | Jun 28 08:28:29 PM PDT 24 |
| Finished | Jun 28 08:58:08 PM PDT 24 |
| Peak memory | 575436 kb |
| Host | smart-0ea7bb78-2dba-4044-9e4d-ded8e67285bf |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1273654573 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.xbar_access_same_d evice_slow_rsp.1273654573 |
| Directory | /workspace/1.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/1.xbar_error_and_unmapped_addr.41899869 |
| Short name | T2785 |
| Test name | |
| Test status | |
| Simulation time | 96772934 ps |
| CPU time | 16.4 seconds |
| Started | Jun 28 08:28:47 PM PDT 24 |
| Finished | Jun 28 08:29:24 PM PDT 24 |
| Peak memory | 573828 kb |
| Host | smart-cd816318-8b17-427f-b66a-f3a7dab7514e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41899869 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.xbar_error_and_unmapped_addr.41899869 |
| Directory | /workspace/1.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/1.xbar_error_random.57302729 |
| Short name | T1353 |
| Test name | |
| Test status | |
| Simulation time | 1968307791 ps |
| CPU time | 84.63 seconds |
| Started | Jun 28 08:28:07 PM PDT 24 |
| Finished | Jun 28 08:29:33 PM PDT 24 |
| Peak memory | 573860 kb |
| Host | smart-084d0474-5999-4d0d-baf1-0a8885cd3758 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57302729 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.xbar_error_random.57302729 |
| Directory | /workspace/1.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/1.xbar_random.687105698 |
| Short name | T2134 |
| Test name | |
| Test status | |
| Simulation time | 181788836 ps |
| CPU time | 20.47 seconds |
| Started | Jun 28 08:28:12 PM PDT 24 |
| Finished | Jun 28 08:28:36 PM PDT 24 |
| Peak memory | 575212 kb |
| Host | smart-484ce9f5-5120-4b4f-ac40-93f14c627423 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=687105698 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.xbar_random.687105698 |
| Directory | /workspace/1.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/1.xbar_random_large_delays.4053662487 |
| Short name | T521 |
| Test name | |
| Test status | |
| Simulation time | 34296816627 ps |
| CPU time | 374.66 seconds |
| Started | Jun 28 08:28:06 PM PDT 24 |
| Finished | Jun 28 08:34:22 PM PDT 24 |
| Peak memory | 575320 kb |
| Host | smart-dcc2f4bc-f44a-4f7e-a46a-c7b5fc5885e2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4053662487 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.xbar_random_large_delays.4053662487 |
| Directory | /workspace/1.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/1.xbar_random_slow_rsp.472916169 |
| Short name | T2249 |
| Test name | |
| Test status | |
| Simulation time | 35247163957 ps |
| CPU time | 619.46 seconds |
| Started | Jun 28 08:28:13 PM PDT 24 |
| Finished | Jun 28 08:38:36 PM PDT 24 |
| Peak memory | 575324 kb |
| Host | smart-963bc7a7-c1ea-4ac6-8399-73e3e58738eb |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=472916169 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.xbar_random_slow_rsp.472916169 |
| Directory | /workspace/1.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/1.xbar_random_zero_delays.253099037 |
| Short name | T1804 |
| Test name | |
| Test status | |
| Simulation time | 279712629 ps |
| CPU time | 29.23 seconds |
| Started | Jun 28 08:28:03 PM PDT 24 |
| Finished | Jun 28 08:28:33 PM PDT 24 |
| Peak memory | 574172 kb |
| Host | smart-1467aba2-4d9b-4486-91b4-3646fb772759 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=253099037 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.xbar_random_zero_delay s.253099037 |
| Directory | /workspace/1.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/1.xbar_same_source.1823228928 |
| Short name | T1790 |
| Test name | |
| Test status | |
| Simulation time | 1546699022 ps |
| CPU time | 52.11 seconds |
| Started | Jun 28 08:28:08 PM PDT 24 |
| Finished | Jun 28 08:29:02 PM PDT 24 |
| Peak memory | 574168 kb |
| Host | smart-277af393-3f5e-404e-ad6a-5054544a2dcf |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1823228928 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.xbar_same_source.1823228928 |
| Directory | /workspace/1.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/1.xbar_smoke.1341642057 |
| Short name | T1711 |
| Test name | |
| Test status | |
| Simulation time | 224489781 ps |
| CPU time | 10.9 seconds |
| Started | Jun 28 08:28:07 PM PDT 24 |
| Finished | Jun 28 08:28:19 PM PDT 24 |
| Peak memory | 574176 kb |
| Host | smart-c803ece0-73be-43ba-adb3-71e935a8f808 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1341642057 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.xbar_smoke.1341642057 |
| Directory | /workspace/1.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/1.xbar_smoke_large_delays.3169805625 |
| Short name | T1467 |
| Test name | |
| Test status | |
| Simulation time | 9489032559 ps |
| CPU time | 102.51 seconds |
| Started | Jun 28 08:28:06 PM PDT 24 |
| Finished | Jun 28 08:29:49 PM PDT 24 |
| Peak memory | 574256 kb |
| Host | smart-760b7784-851d-48da-8faa-f0e8237de9b0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3169805625 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.xbar_smoke_large_delays.3169805625 |
| Directory | /workspace/1.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/1.xbar_smoke_slow_rsp.455884130 |
| Short name | T1510 |
| Test name | |
| Test status | |
| Simulation time | 6493650620 ps |
| CPU time | 114.1 seconds |
| Started | Jun 28 08:28:07 PM PDT 24 |
| Finished | Jun 28 08:30:02 PM PDT 24 |
| Peak memory | 574224 kb |
| Host | smart-94e0e3fe-19f9-47a3-a1c1-2afae70d4d22 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=455884130 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.xbar_smoke_slow_rsp.455884130 |
| Directory | /workspace/1.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/1.xbar_smoke_zero_delays.1258618518 |
| Short name | T1507 |
| Test name | |
| Test status | |
| Simulation time | 43319702 ps |
| CPU time | 7.24 seconds |
| Started | Jun 28 08:28:20 PM PDT 24 |
| Finished | Jun 28 08:28:30 PM PDT 24 |
| Peak memory | 565896 kb |
| Host | smart-4d371d0d-98cf-49e0-9d69-f6bc54f4b585 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1258618518 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.xbar_smoke_zero_delays .1258618518 |
| Directory | /workspace/1.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/1.xbar_stress_all.2042399323 |
| Short name | T1621 |
| Test name | |
| Test status | |
| Simulation time | 7066123318 ps |
| CPU time | 317.14 seconds |
| Started | Jun 28 08:28:39 PM PDT 24 |
| Finished | Jun 28 08:34:11 PM PDT 24 |
| Peak memory | 575460 kb |
| Host | smart-d6aa62dd-6346-463b-b6ed-0b908abb5f16 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2042399323 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.xbar_stress_all.2042399323 |
| Directory | /workspace/1.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/1.xbar_stress_all_with_rand_reset.2094812081 |
| Short name | T492 |
| Test name | |
| Test status | |
| Simulation time | 1192735222 ps |
| CPU time | 357.55 seconds |
| Started | Jun 28 08:28:41 PM PDT 24 |
| Finished | Jun 28 08:34:57 PM PDT 24 |
| Peak memory | 575392 kb |
| Host | smart-31fa087f-1ef2-4278-a1b7-094511019760 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2094812081 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.xbar_stress_all_ with_rand_reset.2094812081 |
| Directory | /workspace/1.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/1.xbar_stress_all_with_reset_error.643948024 |
| Short name | T2140 |
| Test name | |
| Test status | |
| Simulation time | 56706744 ps |
| CPU time | 22.08 seconds |
| Started | Jun 28 08:28:39 PM PDT 24 |
| Finished | Jun 28 08:29:16 PM PDT 24 |
| Peak memory | 574340 kb |
| Host | smart-296caf4e-ff3a-4e7a-80fb-bee9ea86906d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=643948024 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.xbar_stress_all_ with_reset_error.643948024 |
| Directory | /workspace/1.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/1.xbar_unmapped_addr.1967485969 |
| Short name | T2713 |
| Test name | |
| Test status | |
| Simulation time | 41682036 ps |
| CPU time | 8.55 seconds |
| Started | Jun 28 08:28:52 PM PDT 24 |
| Finished | Jun 28 08:29:25 PM PDT 24 |
| Peak memory | 566000 kb |
| Host | smart-0584b673-1d67-4c76-a371-df0ad04304d2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1967485969 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.xbar_unmapped_addr.1967485969 |
| Directory | /workspace/1.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/10.chip_csr_rw.3675564672 |
| Short name | T2461 |
| Test name | |
| Test status | |
| Simulation time | 5291189505 ps |
| CPU time | 570.7 seconds |
| Started | Jun 28 08:34:26 PM PDT 24 |
| Finished | Jun 28 08:44:12 PM PDT 24 |
| Peak memory | 597056 kb |
| Host | smart-bda29f13-b327-48ce-b92a-a66ad3e51f42 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3675564672 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.chip_csr_rw.3675564672 |
| Directory | /workspace/10.chip_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/10.xbar_access_same_device.3890009824 |
| Short name | T2240 |
| Test name | |
| Test status | |
| Simulation time | 874161697 ps |
| CPU time | 40.98 seconds |
| Started | Jun 28 08:34:33 PM PDT 24 |
| Finished | Jun 28 08:35:32 PM PDT 24 |
| Peak memory | 574192 kb |
| Host | smart-3127f58e-e3f3-4d52-aa83-29e22ec87ec8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3890009824 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.xbar_access_same_device .3890009824 |
| Directory | /workspace/10.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/10.xbar_access_same_device_slow_rsp.4006862679 |
| Short name | T1723 |
| Test name | |
| Test status | |
| Simulation time | 58500694450 ps |
| CPU time | 1009.54 seconds |
| Started | Jun 28 08:34:28 PM PDT 24 |
| Finished | Jun 28 08:51:36 PM PDT 24 |
| Peak memory | 575384 kb |
| Host | smart-3505bc70-4896-4f54-a1f4-f09ea6004e99 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4006862679 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.xbar_access_same_ device_slow_rsp.4006862679 |
| Directory | /workspace/10.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/10.xbar_error_and_unmapped_addr.2920545297 |
| Short name | T2309 |
| Test name | |
| Test status | |
| Simulation time | 23935561 ps |
| CPU time | 5.77 seconds |
| Started | Jun 28 08:34:25 PM PDT 24 |
| Finished | Jun 28 08:34:47 PM PDT 24 |
| Peak memory | 574120 kb |
| Host | smart-a64a5ca8-cd63-4153-a188-11ab4dc9f41e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2920545297 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.xbar_error_and_unmapped_add r.2920545297 |
| Directory | /workspace/10.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/10.xbar_error_random.3911174560 |
| Short name | T2644 |
| Test name | |
| Test status | |
| Simulation time | 570149353 ps |
| CPU time | 51.9 seconds |
| Started | Jun 28 08:34:28 PM PDT 24 |
| Finished | Jun 28 08:35:38 PM PDT 24 |
| Peak memory | 574224 kb |
| Host | smart-081a765c-fbfb-4329-bf25-a6008998762b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3911174560 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.xbar_error_random.3911174560 |
| Directory | /workspace/10.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/10.xbar_random.1732559629 |
| Short name | T2670 |
| Test name | |
| Test status | |
| Simulation time | 451912475 ps |
| CPU time | 42.7 seconds |
| Started | Jun 28 08:34:00 PM PDT 24 |
| Finished | Jun 28 08:34:51 PM PDT 24 |
| Peak memory | 574164 kb |
| Host | smart-ac193e21-2867-49a5-a053-5111f602e52e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1732559629 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.xbar_random.1732559629 |
| Directory | /workspace/10.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/10.xbar_random_large_delays.1383658272 |
| Short name | T1655 |
| Test name | |
| Test status | |
| Simulation time | 78044811277 ps |
| CPU time | 769.06 seconds |
| Started | Jun 28 08:34:25 PM PDT 24 |
| Finished | Jun 28 08:47:29 PM PDT 24 |
| Peak memory | 574244 kb |
| Host | smart-ee91065d-27d3-4c70-bc4a-0bdcdd7dba8f |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1383658272 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.xbar_random_large_delays.1383658272 |
| Directory | /workspace/10.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/10.xbar_random_slow_rsp.1687121261 |
| Short name | T2097 |
| Test name | |
| Test status | |
| Simulation time | 56236526091 ps |
| CPU time | 916.23 seconds |
| Started | Jun 28 08:34:29 PM PDT 24 |
| Finished | Jun 28 08:50:03 PM PDT 24 |
| Peak memory | 575344 kb |
| Host | smart-bbac78ab-c678-4fb6-90c8-6d133997b7f7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1687121261 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.xbar_random_slow_rsp.1687121261 |
| Directory | /workspace/10.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/10.xbar_random_zero_delays.1660233848 |
| Short name | T505 |
| Test name | |
| Test status | |
| Simulation time | 484689339 ps |
| CPU time | 51.44 seconds |
| Started | Jun 28 08:34:00 PM PDT 24 |
| Finished | Jun 28 08:35:00 PM PDT 24 |
| Peak memory | 575248 kb |
| Host | smart-b745a1f6-c1ca-43ba-aa7c-11247001c920 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1660233848 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.xbar_random_zero_del ays.1660233848 |
| Directory | /workspace/10.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/10.xbar_same_source.2447611634 |
| Short name | T2560 |
| Test name | |
| Test status | |
| Simulation time | 120398532 ps |
| CPU time | 13.23 seconds |
| Started | Jun 28 08:34:25 PM PDT 24 |
| Finished | Jun 28 08:34:55 PM PDT 24 |
| Peak memory | 575220 kb |
| Host | smart-6d90b116-b022-4b2a-8690-b22e61c62e52 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2447611634 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.xbar_same_source.2447611634 |
| Directory | /workspace/10.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/10.xbar_smoke.1808599884 |
| Short name | T2535 |
| Test name | |
| Test status | |
| Simulation time | 49747008 ps |
| CPU time | 6.72 seconds |
| Started | Jun 28 08:34:07 PM PDT 24 |
| Finished | Jun 28 08:34:25 PM PDT 24 |
| Peak memory | 574192 kb |
| Host | smart-51e9789d-caf7-41a1-921f-a9fb02cc1835 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1808599884 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.xbar_smoke.1808599884 |
| Directory | /workspace/10.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/10.xbar_smoke_large_delays.2494041750 |
| Short name | T1967 |
| Test name | |
| Test status | |
| Simulation time | 8804919548 ps |
| CPU time | 94 seconds |
| Started | Jun 28 08:34:00 PM PDT 24 |
| Finished | Jun 28 08:35:42 PM PDT 24 |
| Peak memory | 574256 kb |
| Host | smart-0d5f3d61-9829-4c26-aaaf-b94b406bcebd |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2494041750 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.xbar_smoke_large_delays.2494041750 |
| Directory | /workspace/10.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/10.xbar_smoke_slow_rsp.2247609742 |
| Short name | T1887 |
| Test name | |
| Test status | |
| Simulation time | 6515274067 ps |
| CPU time | 115.86 seconds |
| Started | Jun 28 08:33:59 PM PDT 24 |
| Finished | Jun 28 08:36:04 PM PDT 24 |
| Peak memory | 574260 kb |
| Host | smart-5ff2554c-4596-4cbf-9061-a1b9fefc47e7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2247609742 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.xbar_smoke_slow_rsp.2247609742 |
| Directory | /workspace/10.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/10.xbar_smoke_zero_delays.513859441 |
| Short name | T2106 |
| Test name | |
| Test status | |
| Simulation time | 56953154 ps |
| CPU time | 7.07 seconds |
| Started | Jun 28 08:33:58 PM PDT 24 |
| Finished | Jun 28 08:34:14 PM PDT 24 |
| Peak memory | 574200 kb |
| Host | smart-ca8a82ad-8378-4877-8c58-aad9360cc745 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=513859441 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.xbar_smoke_zero_delays .513859441 |
| Directory | /workspace/10.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/10.xbar_stress_all.4162932508 |
| Short name | T443 |
| Test name | |
| Test status | |
| Simulation time | 334769067 ps |
| CPU time | 30.2 seconds |
| Started | Jun 28 08:34:28 PM PDT 24 |
| Finished | Jun 28 08:35:16 PM PDT 24 |
| Peak memory | 575296 kb |
| Host | smart-9f4ece0d-02f8-4681-bccd-1a00bb6f6a43 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4162932508 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.xbar_stress_all.4162932508 |
| Directory | /workspace/10.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/10.xbar_stress_all_with_error.384065848 |
| Short name | T1948 |
| Test name | |
| Test status | |
| Simulation time | 1769397974 ps |
| CPU time | 134.02 seconds |
| Started | Jun 28 08:34:24 PM PDT 24 |
| Finished | Jun 28 08:36:53 PM PDT 24 |
| Peak memory | 574500 kb |
| Host | smart-c05028cc-d336-45f2-990c-58d503e50037 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=384065848 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.xbar_stress_all_with_error.384065848 |
| Directory | /workspace/10.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/10.xbar_stress_all_with_rand_reset.186315433 |
| Short name | T1774 |
| Test name | |
| Test status | |
| Simulation time | 3676529956 ps |
| CPU time | 487.53 seconds |
| Started | Jun 28 08:34:33 PM PDT 24 |
| Finished | Jun 28 08:42:59 PM PDT 24 |
| Peak memory | 575452 kb |
| Host | smart-30c0e5b2-bf17-4adb-92f0-f9c1ecf42cac |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=186315433 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_res et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.xbar_stress_all_ with_rand_reset.186315433 |
| Directory | /workspace/10.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/10.xbar_stress_all_with_reset_error.29315162 |
| Short name | T1973 |
| Test name | |
| Test status | |
| Simulation time | 112274294 ps |
| CPU time | 34.27 seconds |
| Started | Jun 28 08:34:27 PM PDT 24 |
| Finished | Jun 28 08:35:19 PM PDT 24 |
| Peak memory | 574604 kb |
| Host | smart-d8938db4-26ec-4b07-83be-27bf845329d5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29315162 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_res et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.xbar_stress_all_ with_reset_error.29315162 |
| Directory | /workspace/10.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/10.xbar_unmapped_addr.1495569063 |
| Short name | T1325 |
| Test name | |
| Test status | |
| Simulation time | 609955579 ps |
| CPU time | 27.65 seconds |
| Started | Jun 28 08:34:32 PM PDT 24 |
| Finished | Jun 28 08:35:17 PM PDT 24 |
| Peak memory | 575304 kb |
| Host | smart-49f2aede-3b36-4dbb-8a9b-a405fe604d6b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1495569063 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.xbar_unmapped_addr.1495569063 |
| Directory | /workspace/10.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/11.chip_csr_rw.2290361243 |
| Short name | T398 |
| Test name | |
| Test status | |
| Simulation time | 5674382191 ps |
| CPU time | 578.82 seconds |
| Started | Jun 28 08:34:40 PM PDT 24 |
| Finished | Jun 28 08:44:40 PM PDT 24 |
| Peak memory | 597400 kb |
| Host | smart-e22911fe-5314-4f57-9688-40a127af1ff2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2290361243 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.chip_csr_rw.2290361243 |
| Directory | /workspace/11.chip_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/11.chip_same_csr_outstanding.414169772 |
| Short name | T402 |
| Test name | |
| Test status | |
| Simulation time | 16691660890 ps |
| CPU time | 1952.95 seconds |
| Started | Jun 28 08:34:24 PM PDT 24 |
| Finished | Jun 28 09:07:12 PM PDT 24 |
| Peak memory | 591456 kb |
| Host | smart-36aba796-026e-4f78-b933-28e239971030 |
| User | root |
| Command | /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +run_same_csr_outstanding +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=414169772 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c m_log /dev/null -cm_name 11.chip_same_csr_outstanding.414169772 |
| Directory | /workspace/11.chip_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/11.chip_tl_errors.1246805228 |
| Short name | T2588 |
| Test name | |
| Test status | |
| Simulation time | 3281713775 ps |
| CPU time | 308.29 seconds |
| Started | Jun 28 08:34:25 PM PDT 24 |
| Finished | Jun 28 08:39:50 PM PDT 24 |
| Peak memory | 597340 kb |
| Host | smart-554c9f7a-1640-4aa6-a957-ad407f882c54 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1246805228 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.chip_tl_errors.1246805228 |
| Directory | /workspace/11.chip_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/11.xbar_access_same_device.1733310591 |
| Short name | T2615 |
| Test name | |
| Test status | |
| Simulation time | 931574477 ps |
| CPU time | 48.53 seconds |
| Started | Jun 28 08:34:24 PM PDT 24 |
| Finished | Jun 28 08:35:28 PM PDT 24 |
| Peak memory | 575268 kb |
| Host | smart-8d62fde0-e760-4a38-9668-ffeb07b023f2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1733310591 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.xbar_access_same_device .1733310591 |
| Directory | /workspace/11.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/11.xbar_error_and_unmapped_addr.3856540823 |
| Short name | T651 |
| Test name | |
| Test status | |
| Simulation time | 372894373 ps |
| CPU time | 17.24 seconds |
| Started | Jun 28 08:34:39 PM PDT 24 |
| Finished | Jun 28 08:35:18 PM PDT 24 |
| Peak memory | 574436 kb |
| Host | smart-a6c93df8-27c9-4be5-8dc5-bb8acf94ed0a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3856540823 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.xbar_error_and_unmapped_add r.3856540823 |
| Directory | /workspace/11.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/11.xbar_error_random.1843483296 |
| Short name | T1492 |
| Test name | |
| Test status | |
| Simulation time | 33858524 ps |
| CPU time | 6.72 seconds |
| Started | Jun 28 08:34:24 PM PDT 24 |
| Finished | Jun 28 08:34:46 PM PDT 24 |
| Peak memory | 573760 kb |
| Host | smart-048c1e69-da32-41bd-aaf1-90294a2bd8f4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1843483296 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.xbar_error_random.1843483296 |
| Directory | /workspace/11.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/11.xbar_random.3840292896 |
| Short name | T557 |
| Test name | |
| Test status | |
| Simulation time | 1413375320 ps |
| CPU time | 50.1 seconds |
| Started | Jun 28 08:34:24 PM PDT 24 |
| Finished | Jun 28 08:35:29 PM PDT 24 |
| Peak memory | 575236 kb |
| Host | smart-8950e436-e83b-46fe-91f9-d45c8dc887e6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3840292896 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.xbar_random.3840292896 |
| Directory | /workspace/11.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/11.xbar_random_large_delays.3329651441 |
| Short name | T2481 |
| Test name | |
| Test status | |
| Simulation time | 3051767784 ps |
| CPU time | 35.46 seconds |
| Started | Jun 28 08:34:29 PM PDT 24 |
| Finished | Jun 28 08:35:22 PM PDT 24 |
| Peak memory | 574136 kb |
| Host | smart-67abaf8b-c580-43ea-8630-3f34938c7b3a |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3329651441 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.xbar_random_large_delays.3329651441 |
| Directory | /workspace/11.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/11.xbar_random_slow_rsp.1949515390 |
| Short name | T459 |
| Test name | |
| Test status | |
| Simulation time | 64788168706 ps |
| CPU time | 1161.68 seconds |
| Started | Jun 28 08:34:33 PM PDT 24 |
| Finished | Jun 28 08:54:13 PM PDT 24 |
| Peak memory | 575316 kb |
| Host | smart-d60dcfb5-40c3-4c35-9a43-7c2bbcf6c23c |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1949515390 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.xbar_random_slow_rsp.1949515390 |
| Directory | /workspace/11.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/11.xbar_random_zero_delays.1097440696 |
| Short name | T1395 |
| Test name | |
| Test status | |
| Simulation time | 102697126 ps |
| CPU time | 12.21 seconds |
| Started | Jun 28 08:34:23 PM PDT 24 |
| Finished | Jun 28 08:34:50 PM PDT 24 |
| Peak memory | 574316 kb |
| Host | smart-92507e85-8b97-4289-9f1e-c3d037d3d0bf |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1097440696 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.xbar_random_zero_del ays.1097440696 |
| Directory | /workspace/11.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/11.xbar_same_source.713510977 |
| Short name | T1839 |
| Test name | |
| Test status | |
| Simulation time | 1276057190 ps |
| CPU time | 38.2 seconds |
| Started | Jun 28 08:34:26 PM PDT 24 |
| Finished | Jun 28 08:35:23 PM PDT 24 |
| Peak memory | 575224 kb |
| Host | smart-f2985105-163f-413f-8160-fbf0ce906a68 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=713510977 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.xbar_same_source.713510977 |
| Directory | /workspace/11.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/11.xbar_smoke.50384022 |
| Short name | T1954 |
| Test name | |
| Test status | |
| Simulation time | 236115055 ps |
| CPU time | 9.76 seconds |
| Started | Jun 28 08:34:27 PM PDT 24 |
| Finished | Jun 28 08:34:54 PM PDT 24 |
| Peak memory | 574172 kb |
| Host | smart-b05988b2-cfc6-418d-a85e-3cda7e2bd045 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50384022 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.xbar_smoke.50384022 |
| Directory | /workspace/11.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/11.xbar_smoke_large_delays.384252470 |
| Short name | T2138 |
| Test name | |
| Test status | |
| Simulation time | 9683688710 ps |
| CPU time | 98.85 seconds |
| Started | Jun 28 08:34:26 PM PDT 24 |
| Finished | Jun 28 08:36:21 PM PDT 24 |
| Peak memory | 574256 kb |
| Host | smart-d1eb1454-e9ad-45e9-b8f3-19438bd3354b |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=384252470 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.xbar_smoke_large_delays.384252470 |
| Directory | /workspace/11.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/11.xbar_smoke_slow_rsp.45987367 |
| Short name | T2766 |
| Test name | |
| Test status | |
| Simulation time | 4698951332 ps |
| CPU time | 83.3 seconds |
| Started | Jun 28 08:34:27 PM PDT 24 |
| Finished | Jun 28 08:36:08 PM PDT 24 |
| Peak memory | 574244 kb |
| Host | smart-6b253805-2664-4758-80c0-1d124fc44281 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45987367 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.xbar_smoke_slow_rsp.45987367 |
| Directory | /workspace/11.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/11.xbar_smoke_zero_delays.2221676470 |
| Short name | T2800 |
| Test name | |
| Test status | |
| Simulation time | 41683034 ps |
| CPU time | 6.57 seconds |
| Started | Jun 28 08:34:25 PM PDT 24 |
| Finished | Jun 28 08:34:48 PM PDT 24 |
| Peak memory | 574180 kb |
| Host | smart-e58ad356-5752-4a68-b1de-b1006061b4cc |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2221676470 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.xbar_smoke_zero_delay s.2221676470 |
| Directory | /workspace/11.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/11.xbar_stress_all.222500901 |
| Short name | T475 |
| Test name | |
| Test status | |
| Simulation time | 6671703894 ps |
| CPU time | 236.42 seconds |
| Started | Jun 28 08:34:42 PM PDT 24 |
| Finished | Jun 28 08:38:59 PM PDT 24 |
| Peak memory | 575444 kb |
| Host | smart-3db6b498-cda5-413c-b5b0-6fefec1fd84d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=222500901 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.xbar_stress_all.222500901 |
| Directory | /workspace/11.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/11.xbar_stress_all_with_error.3535787033 |
| Short name | T526 |
| Test name | |
| Test status | |
| Simulation time | 161919663 ps |
| CPU time | 17.67 seconds |
| Started | Jun 28 08:34:38 PM PDT 24 |
| Finished | Jun 28 08:35:17 PM PDT 24 |
| Peak memory | 574468 kb |
| Host | smart-f498c519-fbcb-4cb1-9c90-314cd4f6cb47 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3535787033 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.xbar_stress_all_with_error.3535787033 |
| Directory | /workspace/11.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/11.xbar_stress_all_with_rand_reset.2577689886 |
| Short name | T2642 |
| Test name | |
| Test status | |
| Simulation time | 1295057638 ps |
| CPU time | 235.16 seconds |
| Started | Jun 28 08:34:40 PM PDT 24 |
| Finished | Jun 28 08:38:56 PM PDT 24 |
| Peak memory | 575328 kb |
| Host | smart-4ced08bf-2410-4520-8507-8dfc8a02cf3e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2577689886 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.xbar_stress_all _with_rand_reset.2577689886 |
| Directory | /workspace/11.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/11.xbar_stress_all_with_reset_error.1300261204 |
| Short name | T2040 |
| Test name | |
| Test status | |
| Simulation time | 14836923868 ps |
| CPU time | 702.26 seconds |
| Started | Jun 28 08:34:39 PM PDT 24 |
| Finished | Jun 28 08:46:42 PM PDT 24 |
| Peak memory | 575448 kb |
| Host | smart-98bc263b-f52b-493a-8d35-fbb3064cf3be |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1300261204 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.xbar_stress_al l_with_reset_error.1300261204 |
| Directory | /workspace/11.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/11.xbar_unmapped_addr.4280356446 |
| Short name | T2740 |
| Test name | |
| Test status | |
| Simulation time | 72117549 ps |
| CPU time | 12.1 seconds |
| Started | Jun 28 08:34:41 PM PDT 24 |
| Finished | Jun 28 08:35:15 PM PDT 24 |
| Peak memory | 575288 kb |
| Host | smart-76327ab5-3763-4479-864b-12c130dcdf4c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4280356446 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.xbar_unmapped_addr.4280356446 |
| Directory | /workspace/11.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/12.chip_csr_rw.817783700 |
| Short name | T2523 |
| Test name | |
| Test status | |
| Simulation time | 4270397423 ps |
| CPU time | 325.04 seconds |
| Started | Jun 28 08:34:58 PM PDT 24 |
| Finished | Jun 28 08:40:41 PM PDT 24 |
| Peak memory | 595888 kb |
| Host | smart-179aa83a-867d-49f8-9a37-f4b888655872 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=817783700 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.chip_csr_rw.817783700 |
| Directory | /workspace/12.chip_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/12.chip_same_csr_outstanding.1104570266 |
| Short name | T428 |
| Test name | |
| Test status | |
| Simulation time | 29884514373 ps |
| CPU time | 2927.73 seconds |
| Started | Jun 28 08:34:39 PM PDT 24 |
| Finished | Jun 28 09:23:49 PM PDT 24 |
| Peak memory | 591828 kb |
| Host | smart-3a3d9847-8344-44f0-b9ed-c980cb9a29f0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +run_same_csr_outstanding +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1104570266 -assert nopostproc +UVM_TE STNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb - cm_log /dev/null -cm_name 12.chip_same_csr_outstanding.1104570266 |
| Directory | /workspace/12.chip_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/12.chip_tl_errors.2331225516 |
| Short name | T663 |
| Test name | |
| Test status | |
| Simulation time | 4030487184 ps |
| CPU time | 332.98 seconds |
| Started | Jun 28 08:34:40 PM PDT 24 |
| Finished | Jun 28 08:40:34 PM PDT 24 |
| Peak memory | 597444 kb |
| Host | smart-99c30713-9bc6-47e3-88c3-42a3cc3c6495 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2331225516 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.chip_tl_errors.2331225516 |
| Directory | /workspace/12.chip_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/12.xbar_access_same_device.3422834082 |
| Short name | T2693 |
| Test name | |
| Test status | |
| Simulation time | 105680358 ps |
| CPU time | 16.85 seconds |
| Started | Jun 28 08:34:40 PM PDT 24 |
| Finished | Jun 28 08:35:18 PM PDT 24 |
| Peak memory | 575224 kb |
| Host | smart-1b5a4d04-f89b-4e28-990c-8e68cc42ee2c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3422834082 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.xbar_access_same_device .3422834082 |
| Directory | /workspace/12.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/12.xbar_access_same_device_slow_rsp.1648561487 |
| Short name | T1633 |
| Test name | |
| Test status | |
| Simulation time | 8699756661 ps |
| CPU time | 157.2 seconds |
| Started | Jun 28 08:34:54 PM PDT 24 |
| Finished | Jun 28 08:37:51 PM PDT 24 |
| Peak memory | 566028 kb |
| Host | smart-519f75ee-3f84-4296-b9d0-f8f1cdd0669a |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1648561487 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.xbar_access_same_ device_slow_rsp.1648561487 |
| Directory | /workspace/12.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/12.xbar_error_and_unmapped_addr.3721601434 |
| Short name | T1738 |
| Test name | |
| Test status | |
| Simulation time | 187265875 ps |
| CPU time | 20.96 seconds |
| Started | Jun 28 08:34:59 PM PDT 24 |
| Finished | Jun 28 08:35:37 PM PDT 24 |
| Peak memory | 574200 kb |
| Host | smart-bbf03926-c74c-483c-855f-dbac3d7a0bf8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3721601434 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.xbar_error_and_unmapped_add r.3721601434 |
| Directory | /workspace/12.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/12.xbar_error_random.515405392 |
| Short name | T2613 |
| Test name | |
| Test status | |
| Simulation time | 2310215917 ps |
| CPU time | 85.38 seconds |
| Started | Jun 28 08:34:55 PM PDT 24 |
| Finished | Jun 28 08:36:40 PM PDT 24 |
| Peak memory | 573896 kb |
| Host | smart-7afcb388-cd39-4bea-874f-71b8ad821fde |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=515405392 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.xbar_error_random.515405392 |
| Directory | /workspace/12.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/12.xbar_random.945526274 |
| Short name | T1618 |
| Test name | |
| Test status | |
| Simulation time | 251195378 ps |
| CPU time | 24.64 seconds |
| Started | Jun 28 08:34:43 PM PDT 24 |
| Finished | Jun 28 08:35:29 PM PDT 24 |
| Peak memory | 574180 kb |
| Host | smart-7e66befb-3cf5-4b77-87c1-dabf8b81762a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=945526274 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.xbar_random.945526274 |
| Directory | /workspace/12.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/12.xbar_random_large_delays.3284159544 |
| Short name | T2061 |
| Test name | |
| Test status | |
| Simulation time | 19999546289 ps |
| CPU time | 210.3 seconds |
| Started | Jun 28 08:34:40 PM PDT 24 |
| Finished | Jun 28 08:38:32 PM PDT 24 |
| Peak memory | 575316 kb |
| Host | smart-9a515288-a2cf-4035-b468-d2d3818620e0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3284159544 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.xbar_random_large_delays.3284159544 |
| Directory | /workspace/12.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/12.xbar_random_slow_rsp.1965582415 |
| Short name | T1782 |
| Test name | |
| Test status | |
| Simulation time | 42122701610 ps |
| CPU time | 740.51 seconds |
| Started | Jun 28 08:34:43 PM PDT 24 |
| Finished | Jun 28 08:47:25 PM PDT 24 |
| Peak memory | 575292 kb |
| Host | smart-62dc6920-11b6-4a08-9955-4a0bee3b078f |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1965582415 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.xbar_random_slow_rsp.1965582415 |
| Directory | /workspace/12.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/12.xbar_random_zero_delays.3354087436 |
| Short name | T474 |
| Test name | |
| Test status | |
| Simulation time | 439491195 ps |
| CPU time | 41.72 seconds |
| Started | Jun 28 08:34:45 PM PDT 24 |
| Finished | Jun 28 08:35:49 PM PDT 24 |
| Peak memory | 575260 kb |
| Host | smart-7f4ee658-0d46-47de-9969-b437246efca0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3354087436 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.xbar_random_zero_del ays.3354087436 |
| Directory | /workspace/12.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/12.xbar_same_source.3007168173 |
| Short name | T2300 |
| Test name | |
| Test status | |
| Simulation time | 167299019 ps |
| CPU time | 16.25 seconds |
| Started | Jun 28 08:34:55 PM PDT 24 |
| Finished | Jun 28 08:35:31 PM PDT 24 |
| Peak memory | 575220 kb |
| Host | smart-2d0d2c71-3a8a-47a3-98a5-69a55181ac17 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3007168173 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.xbar_same_source.3007168173 |
| Directory | /workspace/12.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/12.xbar_smoke.182627075 |
| Short name | T1329 |
| Test name | |
| Test status | |
| Simulation time | 197416576 ps |
| CPU time | 9.97 seconds |
| Started | Jun 28 08:34:40 PM PDT 24 |
| Finished | Jun 28 08:35:11 PM PDT 24 |
| Peak memory | 565880 kb |
| Host | smart-63b9b899-6505-4ad1-a243-489981fb6f04 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=182627075 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.xbar_smoke.182627075 |
| Directory | /workspace/12.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/12.xbar_smoke_large_delays.2191145588 |
| Short name | T1351 |
| Test name | |
| Test status | |
| Simulation time | 5243368518 ps |
| CPU time | 54.64 seconds |
| Started | Jun 28 08:34:43 PM PDT 24 |
| Finished | Jun 28 08:35:59 PM PDT 24 |
| Peak memory | 566000 kb |
| Host | smart-46c52064-4c24-4114-805f-f5f71bf67664 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2191145588 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.xbar_smoke_large_delays.2191145588 |
| Directory | /workspace/12.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/12.xbar_smoke_slow_rsp.2650228689 |
| Short name | T2634 |
| Test name | |
| Test status | |
| Simulation time | 6088743745 ps |
| CPU time | 107.13 seconds |
| Started | Jun 28 08:34:45 PM PDT 24 |
| Finished | Jun 28 08:36:54 PM PDT 24 |
| Peak memory | 574272 kb |
| Host | smart-eee1ef7b-7b10-4283-b68f-6a33409c45bf |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2650228689 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.xbar_smoke_slow_rsp.2650228689 |
| Directory | /workspace/12.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/12.xbar_smoke_zero_delays.2445703327 |
| Short name | T1781 |
| Test name | |
| Test status | |
| Simulation time | 47913512 ps |
| CPU time | 6.32 seconds |
| Started | Jun 28 08:34:42 PM PDT 24 |
| Finished | Jun 28 08:35:10 PM PDT 24 |
| Peak memory | 574184 kb |
| Host | smart-80a36775-e4e7-4f21-96ea-6f29138e03f1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2445703327 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.xbar_smoke_zero_delay s.2445703327 |
| Directory | /workspace/12.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/12.xbar_stress_all.3190738196 |
| Short name | T2596 |
| Test name | |
| Test status | |
| Simulation time | 15688547351 ps |
| CPU time | 551.84 seconds |
| Started | Jun 28 08:34:57 PM PDT 24 |
| Finished | Jun 28 08:44:27 PM PDT 24 |
| Peak memory | 575352 kb |
| Host | smart-a5c49910-b1bd-47a6-9940-0a114e698c67 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3190738196 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.xbar_stress_all.3190738196 |
| Directory | /workspace/12.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/12.xbar_stress_all_with_error.1730389647 |
| Short name | T2735 |
| Test name | |
| Test status | |
| Simulation time | 3236638115 ps |
| CPU time | 284.98 seconds |
| Started | Jun 28 08:34:52 PM PDT 24 |
| Finished | Jun 28 08:39:57 PM PDT 24 |
| Peak memory | 574676 kb |
| Host | smart-02666b83-59e8-44d5-a03b-bcd633b0f240 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1730389647 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.xbar_stress_all_with_error.1730389647 |
| Directory | /workspace/12.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/12.xbar_stress_all_with_rand_reset.2994380351 |
| Short name | T2311 |
| Test name | |
| Test status | |
| Simulation time | 2922339475 ps |
| CPU time | 513.7 seconds |
| Started | Jun 28 08:34:53 PM PDT 24 |
| Finished | Jun 28 08:43:46 PM PDT 24 |
| Peak memory | 576576 kb |
| Host | smart-e98f681c-3bbc-4ebf-b875-3f02dab758cf |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2994380351 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.xbar_stress_all _with_rand_reset.2994380351 |
| Directory | /workspace/12.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/12.xbar_unmapped_addr.2850890283 |
| Short name | T1932 |
| Test name | |
| Test status | |
| Simulation time | 391153875 ps |
| CPU time | 22.04 seconds |
| Started | Jun 28 08:34:55 PM PDT 24 |
| Finished | Jun 28 08:35:37 PM PDT 24 |
| Peak memory | 575300 kb |
| Host | smart-9dfecc56-79dc-4cad-8f37-18a65086c57c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2850890283 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.xbar_unmapped_addr.2850890283 |
| Directory | /workspace/12.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/13.chip_csr_rw.984108630 |
| Short name | T2386 |
| Test name | |
| Test status | |
| Simulation time | 4208498884 ps |
| CPU time | 384.34 seconds |
| Started | Jun 28 08:35:37 PM PDT 24 |
| Finished | Jun 28 08:42:28 PM PDT 24 |
| Peak memory | 596232 kb |
| Host | smart-3951285e-00dc-4469-bc9a-858fe278ca12 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=984108630 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.chip_csr_rw.984108630 |
| Directory | /workspace/13.chip_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/13.chip_same_csr_outstanding.2424913883 |
| Short name | T1964 |
| Test name | |
| Test status | |
| Simulation time | 28101874195 ps |
| CPU time | 3675.75 seconds |
| Started | Jun 28 08:34:54 PM PDT 24 |
| Finished | Jun 28 09:36:30 PM PDT 24 |
| Peak memory | 591544 kb |
| Host | smart-ba020028-7749-4479-9798-a2b9bf91cf10 |
| User | root |
| Command | /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +run_same_csr_outstanding +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2424913883 -assert nopostproc +UVM_TE STNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb - cm_log /dev/null -cm_name 13.chip_same_csr_outstanding.2424913883 |
| Directory | /workspace/13.chip_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/13.chip_tl_errors.3807809291 |
| Short name | T541 |
| Test name | |
| Test status | |
| Simulation time | 3190502253 ps |
| CPU time | 200.32 seconds |
| Started | Jun 28 08:34:56 PM PDT 24 |
| Finished | Jun 28 08:38:36 PM PDT 24 |
| Peak memory | 597348 kb |
| Host | smart-be3519a9-5162-4763-bad5-9de76c34729b |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3807809291 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.chip_tl_errors.3807809291 |
| Directory | /workspace/13.chip_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/13.xbar_access_same_device.3073360700 |
| Short name | T725 |
| Test name | |
| Test status | |
| Simulation time | 546318052 ps |
| CPU time | 26.56 seconds |
| Started | Jun 28 08:35:10 PM PDT 24 |
| Finished | Jun 28 08:35:51 PM PDT 24 |
| Peak memory | 574164 kb |
| Host | smart-22bfdad5-d2dd-4a4a-af21-f501a66a87c3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3073360700 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.xbar_access_same_device .3073360700 |
| Directory | /workspace/13.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/13.xbar_access_same_device_slow_rsp.2593615924 |
| Short name | T1873 |
| Test name | |
| Test status | |
| Simulation time | 54920175354 ps |
| CPU time | 943.28 seconds |
| Started | Jun 28 08:35:11 PM PDT 24 |
| Finished | Jun 28 08:51:09 PM PDT 24 |
| Peak memory | 575352 kb |
| Host | smart-6d27c40f-5648-4576-b530-8fb0b456cc58 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2593615924 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.xbar_access_same_ device_slow_rsp.2593615924 |
| Directory | /workspace/13.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/13.xbar_error_and_unmapped_addr.3812049031 |
| Short name | T2589 |
| Test name | |
| Test status | |
| Simulation time | 712113826 ps |
| CPU time | 31.13 seconds |
| Started | Jun 28 08:35:09 PM PDT 24 |
| Finished | Jun 28 08:35:55 PM PDT 24 |
| Peak memory | 574444 kb |
| Host | smart-897dd27d-8bcc-4df3-a01f-01e0730e3454 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3812049031 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.xbar_error_and_unmapped_add r.3812049031 |
| Directory | /workspace/13.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/13.xbar_error_random.4113721802 |
| Short name | T1666 |
| Test name | |
| Test status | |
| Simulation time | 477797883 ps |
| CPU time | 21.27 seconds |
| Started | Jun 28 08:35:11 PM PDT 24 |
| Finished | Jun 28 08:35:46 PM PDT 24 |
| Peak memory | 574192 kb |
| Host | smart-4848a0ed-c497-43de-aa6b-378fad52fb63 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4113721802 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.xbar_error_random.4113721802 |
| Directory | /workspace/13.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/13.xbar_random.1583974345 |
| Short name | T480 |
| Test name | |
| Test status | |
| Simulation time | 1986757550 ps |
| CPU time | 83.39 seconds |
| Started | Jun 28 08:35:14 PM PDT 24 |
| Finished | Jun 28 08:36:52 PM PDT 24 |
| Peak memory | 575176 kb |
| Host | smart-22677bb1-f2bc-41d5-98b9-406314446506 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1583974345 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.xbar_random.1583974345 |
| Directory | /workspace/13.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/13.xbar_random_large_delays.4213288647 |
| Short name | T2039 |
| Test name | |
| Test status | |
| Simulation time | 105632891216 ps |
| CPU time | 1111.01 seconds |
| Started | Jun 28 08:35:10 PM PDT 24 |
| Finished | Jun 28 08:53:55 PM PDT 24 |
| Peak memory | 574268 kb |
| Host | smart-5efb5d10-284b-4765-98e0-887f2e3b0bee |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4213288647 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.xbar_random_large_delays.4213288647 |
| Directory | /workspace/13.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/13.xbar_random_slow_rsp.354626399 |
| Short name | T2515 |
| Test name | |
| Test status | |
| Simulation time | 7492107236 ps |
| CPU time | 136.33 seconds |
| Started | Jun 28 08:35:13 PM PDT 24 |
| Finished | Jun 28 08:37:43 PM PDT 24 |
| Peak memory | 574296 kb |
| Host | smart-3ba5e3ef-cfc4-4928-90a9-a348b3cf9786 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=354626399 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.xbar_random_slow_rsp.354626399 |
| Directory | /workspace/13.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/13.xbar_random_zero_delays.2746573315 |
| Short name | T2760 |
| Test name | |
| Test status | |
| Simulation time | 436274299 ps |
| CPU time | 51.5 seconds |
| Started | Jun 28 08:35:09 PM PDT 24 |
| Finished | Jun 28 08:36:15 PM PDT 24 |
| Peak memory | 574228 kb |
| Host | smart-6ddb5d31-32a6-41e5-ac25-af81347f2b0d |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2746573315 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.xbar_random_zero_del ays.2746573315 |
| Directory | /workspace/13.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/13.xbar_same_source.2295966833 |
| Short name | T2651 |
| Test name | |
| Test status | |
| Simulation time | 2214138065 ps |
| CPU time | 71.81 seconds |
| Started | Jun 28 08:35:11 PM PDT 24 |
| Finished | Jun 28 08:36:38 PM PDT 24 |
| Peak memory | 575284 kb |
| Host | smart-e9ce4a3d-ffdb-4f2d-a2ff-19d869675b1f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2295966833 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.xbar_same_source.2295966833 |
| Directory | /workspace/13.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/13.xbar_smoke.587039308 |
| Short name | T601 |
| Test name | |
| Test status | |
| Simulation time | 203206690 ps |
| CPU time | 9.3 seconds |
| Started | Jun 28 08:34:59 PM PDT 24 |
| Finished | Jun 28 08:35:26 PM PDT 24 |
| Peak memory | 573388 kb |
| Host | smart-df50a7ef-4610-417e-a2f4-dfadb55543d1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=587039308 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.xbar_smoke.587039308 |
| Directory | /workspace/13.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/13.xbar_smoke_large_delays.3973875753 |
| Short name | T1968 |
| Test name | |
| Test status | |
| Simulation time | 5894937111 ps |
| CPU time | 65.97 seconds |
| Started | Jun 28 08:35:14 PM PDT 24 |
| Finished | Jun 28 08:36:34 PM PDT 24 |
| Peak memory | 565924 kb |
| Host | smart-2d0ed2af-4ad0-41d3-8d24-ad9c52742c2a |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3973875753 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.xbar_smoke_large_delays.3973875753 |
| Directory | /workspace/13.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/13.xbar_smoke_slow_rsp.3915992440 |
| Short name | T1761 |
| Test name | |
| Test status | |
| Simulation time | 7186505531 ps |
| CPU time | 127.62 seconds |
| Started | Jun 28 08:35:11 PM PDT 24 |
| Finished | Jun 28 08:37:34 PM PDT 24 |
| Peak memory | 574204 kb |
| Host | smart-88892c43-5cd1-48c7-b27f-ad64ef33b26b |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3915992440 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.xbar_smoke_slow_rsp.3915992440 |
| Directory | /workspace/13.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/13.xbar_smoke_zero_delays.4063946290 |
| Short name | T1375 |
| Test name | |
| Test status | |
| Simulation time | 59899193 ps |
| CPU time | 8.1 seconds |
| Started | Jun 28 08:34:55 PM PDT 24 |
| Finished | Jun 28 08:35:23 PM PDT 24 |
| Peak memory | 574200 kb |
| Host | smart-67c2fdf2-4ad2-44cf-8911-ee6b87e1dbdb |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4063946290 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.xbar_smoke_zero_delay s.4063946290 |
| Directory | /workspace/13.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/13.xbar_stress_all.1463046262 |
| Short name | T1709 |
| Test name | |
| Test status | |
| Simulation time | 3557369811 ps |
| CPU time | 138.19 seconds |
| Started | Jun 28 08:35:11 PM PDT 24 |
| Finished | Jun 28 08:37:44 PM PDT 24 |
| Peak memory | 575420 kb |
| Host | smart-54875de8-3770-442d-bede-352a6d4644cd |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1463046262 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.xbar_stress_all.1463046262 |
| Directory | /workspace/13.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/13.xbar_stress_all_with_error.1231911440 |
| Short name | T1334 |
| Test name | |
| Test status | |
| Simulation time | 1580175039 ps |
| CPU time | 130.78 seconds |
| Started | Jun 28 08:35:36 PM PDT 24 |
| Finished | Jun 28 08:38:13 PM PDT 24 |
| Peak memory | 574352 kb |
| Host | smart-21084cac-cc70-40ee-9e49-dac3c6c35e49 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1231911440 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.xbar_stress_all_with_error.1231911440 |
| Directory | /workspace/13.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/13.xbar_stress_all_with_rand_reset.2812930931 |
| Short name | T2827 |
| Test name | |
| Test status | |
| Simulation time | 1689362189 ps |
| CPU time | 321.18 seconds |
| Started | Jun 28 08:35:39 PM PDT 24 |
| Finished | Jun 28 08:41:26 PM PDT 24 |
| Peak memory | 575380 kb |
| Host | smart-833030d2-59a5-4532-9cfd-bf2a968badbd |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2812930931 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.xbar_stress_all _with_rand_reset.2812930931 |
| Directory | /workspace/13.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/13.xbar_unmapped_addr.1437792854 |
| Short name | T2483 |
| Test name | |
| Test status | |
| Simulation time | 1183371281 ps |
| CPU time | 60.49 seconds |
| Started | Jun 28 08:35:10 PM PDT 24 |
| Finished | Jun 28 08:36:25 PM PDT 24 |
| Peak memory | 575288 kb |
| Host | smart-ea64c43a-4086-4b4a-a281-06aca53d0e54 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1437792854 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.xbar_unmapped_addr.1437792854 |
| Directory | /workspace/13.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/14.chip_csr_rw.3689168501 |
| Short name | T376 |
| Test name | |
| Test status | |
| Simulation time | 5071027860 ps |
| CPU time | 366.25 seconds |
| Started | Jun 28 08:35:57 PM PDT 24 |
| Finished | Jun 28 08:42:20 PM PDT 24 |
| Peak memory | 596068 kb |
| Host | smart-cdf2228a-f617-45a9-94bf-4596903fbf8f |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3689168501 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.chip_csr_rw.3689168501 |
| Directory | /workspace/14.chip_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/14.chip_same_csr_outstanding.800111487 |
| Short name | T437 |
| Test name | |
| Test status | |
| Simulation time | 16702328944 ps |
| CPU time | 2170.76 seconds |
| Started | Jun 28 08:35:36 PM PDT 24 |
| Finished | Jun 28 09:12:14 PM PDT 24 |
| Peak memory | 591804 kb |
| Host | smart-8f92d3fd-aef5-4c68-9121-eb429b1e5df5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +run_same_csr_outstanding +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=800111487 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c m_log /dev/null -cm_name 14.chip_same_csr_outstanding.800111487 |
| Directory | /workspace/14.chip_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/14.chip_tl_errors.2531995920 |
| Short name | T2342 |
| Test name | |
| Test status | |
| Simulation time | 3537553516 ps |
| CPU time | 294.97 seconds |
| Started | Jun 28 08:35:36 PM PDT 24 |
| Finished | Jun 28 08:40:57 PM PDT 24 |
| Peak memory | 603524 kb |
| Host | smart-8113fe84-636f-48ac-b176-bec080959fec |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2531995920 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.chip_tl_errors.2531995920 |
| Directory | /workspace/14.chip_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/14.xbar_access_same_device.1908411822 |
| Short name | T2448 |
| Test name | |
| Test status | |
| Simulation time | 1531463976 ps |
| CPU time | 67.45 seconds |
| Started | Jun 28 08:35:38 PM PDT 24 |
| Finished | Jun 28 08:37:11 PM PDT 24 |
| Peak memory | 574156 kb |
| Host | smart-d4d341ce-27e5-4233-8f57-6681a2cc059c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1908411822 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.xbar_access_same_device .1908411822 |
| Directory | /workspace/14.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/14.xbar_access_same_device_slow_rsp.3013196341 |
| Short name | T478 |
| Test name | |
| Test status | |
| Simulation time | 73331752595 ps |
| CPU time | 1306.54 seconds |
| Started | Jun 28 08:35:37 PM PDT 24 |
| Finished | Jun 28 08:57:51 PM PDT 24 |
| Peak memory | 575328 kb |
| Host | smart-0505afc7-e896-461e-9dac-07cb37009555 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3013196341 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.xbar_access_same_ device_slow_rsp.3013196341 |
| Directory | /workspace/14.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/14.xbar_error_and_unmapped_addr.913099337 |
| Short name | T2419 |
| Test name | |
| Test status | |
| Simulation time | 1341734006 ps |
| CPU time | 51.25 seconds |
| Started | Jun 28 08:35:53 PM PDT 24 |
| Finished | Jun 28 08:37:03 PM PDT 24 |
| Peak memory | 574408 kb |
| Host | smart-53c31afd-4b57-473f-938d-ce208247cc58 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=913099337 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.xbar_error_and_unmapped_addr .913099337 |
| Directory | /workspace/14.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/14.xbar_error_random.3007682722 |
| Short name | T1567 |
| Test name | |
| Test status | |
| Simulation time | 1589832081 ps |
| CPU time | 58.89 seconds |
| Started | Jun 28 08:35:54 PM PDT 24 |
| Finished | Jun 28 08:37:12 PM PDT 24 |
| Peak memory | 573848 kb |
| Host | smart-eae310b9-a513-41eb-a180-8bb7a25abe5d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3007682722 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.xbar_error_random.3007682722 |
| Directory | /workspace/14.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/14.xbar_random.421828822 |
| Short name | T1759 |
| Test name | |
| Test status | |
| Simulation time | 1981591741 ps |
| CPU time | 78.07 seconds |
| Started | Jun 28 08:35:34 PM PDT 24 |
| Finished | Jun 28 08:37:18 PM PDT 24 |
| Peak memory | 575220 kb |
| Host | smart-ddd27e48-1f51-48bc-a1ee-126d74b75b51 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=421828822 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.xbar_random.421828822 |
| Directory | /workspace/14.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/14.xbar_random_large_delays.3855447759 |
| Short name | T2699 |
| Test name | |
| Test status | |
| Simulation time | 93128736223 ps |
| CPU time | 1031.91 seconds |
| Started | Jun 28 08:35:39 PM PDT 24 |
| Finished | Jun 28 08:53:17 PM PDT 24 |
| Peak memory | 575364 kb |
| Host | smart-2190cae7-6f60-4144-b7ef-9704e90ddf6e |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3855447759 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.xbar_random_large_delays.3855447759 |
| Directory | /workspace/14.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/14.xbar_random_slow_rsp.1327237909 |
| Short name | T2503 |
| Test name | |
| Test status | |
| Simulation time | 15080139017 ps |
| CPU time | 271.75 seconds |
| Started | Jun 28 08:35:33 PM PDT 24 |
| Finished | Jun 28 08:40:32 PM PDT 24 |
| Peak memory | 575344 kb |
| Host | smart-3971f2a2-1385-4394-b19a-87122c2ae8f4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1327237909 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.xbar_random_slow_rsp.1327237909 |
| Directory | /workspace/14.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/14.xbar_random_zero_delays.482635226 |
| Short name | T1643 |
| Test name | |
| Test status | |
| Simulation time | 308020027 ps |
| CPU time | 29.03 seconds |
| Started | Jun 28 08:35:36 PM PDT 24 |
| Finished | Jun 28 08:36:31 PM PDT 24 |
| Peak memory | 575244 kb |
| Host | smart-5075bbeb-7284-40db-aada-2b5cc7eb58ef |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=482635226 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.xbar_random_zero_dela ys.482635226 |
| Directory | /workspace/14.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/14.xbar_same_source.3805260379 |
| Short name | T1896 |
| Test name | |
| Test status | |
| Simulation time | 388197619 ps |
| CPU time | 27.62 seconds |
| Started | Jun 28 08:35:36 PM PDT 24 |
| Finished | Jun 28 08:36:30 PM PDT 24 |
| Peak memory | 575228 kb |
| Host | smart-55f7a4be-9c4e-413e-b5d0-f5d025d42c84 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3805260379 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.xbar_same_source.3805260379 |
| Directory | /workspace/14.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/14.xbar_smoke.4111568680 |
| Short name | T1678 |
| Test name | |
| Test status | |
| Simulation time | 180684052 ps |
| CPU time | 8.91 seconds |
| Started | Jun 28 08:35:37 PM PDT 24 |
| Finished | Jun 28 08:36:13 PM PDT 24 |
| Peak memory | 574160 kb |
| Host | smart-ffaef069-275c-4195-84b5-379bf6d41174 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4111568680 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.xbar_smoke.4111568680 |
| Directory | /workspace/14.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/14.xbar_smoke_large_delays.1007945762 |
| Short name | T1614 |
| Test name | |
| Test status | |
| Simulation time | 8965415074 ps |
| CPU time | 95.49 seconds |
| Started | Jun 28 08:35:36 PM PDT 24 |
| Finished | Jun 28 08:37:38 PM PDT 24 |
| Peak memory | 574276 kb |
| Host | smart-9cfeff55-0ba2-420e-b755-2eeef55a8a11 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1007945762 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.xbar_smoke_large_delays.1007945762 |
| Directory | /workspace/14.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/14.xbar_smoke_slow_rsp.2026323952 |
| Short name | T1601 |
| Test name | |
| Test status | |
| Simulation time | 5993834137 ps |
| CPU time | 102.2 seconds |
| Started | Jun 28 08:35:36 PM PDT 24 |
| Finished | Jun 28 08:37:45 PM PDT 24 |
| Peak memory | 566024 kb |
| Host | smart-0a42c3af-209e-40f5-991e-62a2248abcf8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2026323952 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.xbar_smoke_slow_rsp.2026323952 |
| Directory | /workspace/14.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/14.xbar_smoke_zero_delays.2959996285 |
| Short name | T2015 |
| Test name | |
| Test status | |
| Simulation time | 47273944 ps |
| CPU time | 6.43 seconds |
| Started | Jun 28 08:35:37 PM PDT 24 |
| Finished | Jun 28 08:36:10 PM PDT 24 |
| Peak memory | 574188 kb |
| Host | smart-5d20cb64-9a7c-48e6-8179-b0db01007352 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2959996285 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.xbar_smoke_zero_delay s.2959996285 |
| Directory | /workspace/14.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/14.xbar_stress_all.939209216 |
| Short name | T1724 |
| Test name | |
| Test status | |
| Simulation time | 935085544 ps |
| CPU time | 84.79 seconds |
| Started | Jun 28 08:35:53 PM PDT 24 |
| Finished | Jun 28 08:37:37 PM PDT 24 |
| Peak memory | 575332 kb |
| Host | smart-a63d5cfe-89e9-46fa-9c1d-25c11c3c793e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=939209216 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.xbar_stress_all.939209216 |
| Directory | /workspace/14.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/14.xbar_stress_all_with_error.3711486633 |
| Short name | T2193 |
| Test name | |
| Test status | |
| Simulation time | 13900087657 ps |
| CPU time | 609.42 seconds |
| Started | Jun 28 08:35:53 PM PDT 24 |
| Finished | Jun 28 08:46:21 PM PDT 24 |
| Peak memory | 574312 kb |
| Host | smart-1aca0ec0-b416-4999-bcd5-c17d38c349d9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3711486633 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.xbar_stress_all_with_error.3711486633 |
| Directory | /workspace/14.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/14.xbar_stress_all_with_rand_reset.1126249113 |
| Short name | T1530 |
| Test name | |
| Test status | |
| Simulation time | 215559361 ps |
| CPU time | 98.22 seconds |
| Started | Jun 28 08:35:58 PM PDT 24 |
| Finished | Jun 28 08:37:52 PM PDT 24 |
| Peak memory | 575316 kb |
| Host | smart-b75a1135-0fac-4cad-b0be-37a91f6f0b75 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1126249113 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.xbar_stress_all _with_rand_reset.1126249113 |
| Directory | /workspace/14.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/14.xbar_stress_all_with_reset_error.2839106323 |
| Short name | T1671 |
| Test name | |
| Test status | |
| Simulation time | 5296813864 ps |
| CPU time | 279.12 seconds |
| Started | Jun 28 08:35:53 PM PDT 24 |
| Finished | Jun 28 08:40:51 PM PDT 24 |
| Peak memory | 574656 kb |
| Host | smart-efa6c0f3-3b6f-457c-8549-88eb20256f01 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2839106323 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.xbar_stress_al l_with_reset_error.2839106323 |
| Directory | /workspace/14.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/14.xbar_unmapped_addr.3085394298 |
| Short name | T2581 |
| Test name | |
| Test status | |
| Simulation time | 970336062 ps |
| CPU time | 41.56 seconds |
| Started | Jun 28 08:35:55 PM PDT 24 |
| Finished | Jun 28 08:36:54 PM PDT 24 |
| Peak memory | 575264 kb |
| Host | smart-de8107d3-2671-4333-9d85-e1be5aa3a36c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3085394298 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.xbar_unmapped_addr.3085394298 |
| Directory | /workspace/14.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/15.chip_csr_rw.1874590194 |
| Short name | T403 |
| Test name | |
| Test status | |
| Simulation time | 4079514728 ps |
| CPU time | 425.2 seconds |
| Started | Jun 28 08:36:12 PM PDT 24 |
| Finished | Jun 28 08:43:24 PM PDT 24 |
| Peak memory | 597236 kb |
| Host | smart-af542eb1-e913-4336-82fc-a59d1d3de489 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1874590194 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.chip_csr_rw.1874590194 |
| Directory | /workspace/15.chip_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/15.chip_same_csr_outstanding.1818030045 |
| Short name | T1756 |
| Test name | |
| Test status | |
| Simulation time | 15678571926 ps |
| CPU time | 1541.13 seconds |
| Started | Jun 28 08:35:54 PM PDT 24 |
| Finished | Jun 28 09:01:53 PM PDT 24 |
| Peak memory | 591940 kb |
| Host | smart-5d7df68b-dcc2-4fef-9d4b-2868a3984f27 |
| User | root |
| Command | /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +run_same_csr_outstanding +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1818030045 -assert nopostproc +UVM_TE STNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb - cm_log /dev/null -cm_name 15.chip_same_csr_outstanding.1818030045 |
| Directory | /workspace/15.chip_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/15.chip_tl_errors.1367457531 |
| Short name | T664 |
| Test name | |
| Test status | |
| Simulation time | 4787298800 ps |
| CPU time | 531.42 seconds |
| Started | Jun 28 08:35:52 PM PDT 24 |
| Finished | Jun 28 08:45:03 PM PDT 24 |
| Peak memory | 603496 kb |
| Host | smart-9e61406c-9ff1-4e9d-a413-e2326e933385 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1367457531 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.chip_tl_errors.1367457531 |
| Directory | /workspace/15.chip_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/15.xbar_access_same_device.1317261970 |
| Short name | T2539 |
| Test name | |
| Test status | |
| Simulation time | 1759673312 ps |
| CPU time | 75.03 seconds |
| Started | Jun 28 08:35:55 PM PDT 24 |
| Finished | Jun 28 08:37:28 PM PDT 24 |
| Peak memory | 574168 kb |
| Host | smart-0909230f-e92c-4a3e-9f71-53b2a5cabe95 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1317261970 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.xbar_access_same_device .1317261970 |
| Directory | /workspace/15.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/15.xbar_access_same_device_slow_rsp.639030689 |
| Short name | T1622 |
| Test name | |
| Test status | |
| Simulation time | 55531282816 ps |
| CPU time | 986.34 seconds |
| Started | Jun 28 08:35:55 PM PDT 24 |
| Finished | Jun 28 08:52:39 PM PDT 24 |
| Peak memory | 575424 kb |
| Host | smart-4c26dd63-ecdf-43a1-9146-2aea9c0c4fc3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=639030689 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.xbar_access_same_d evice_slow_rsp.639030689 |
| Directory | /workspace/15.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/15.xbar_error_and_unmapped_addr.2838865021 |
| Short name | T1557 |
| Test name | |
| Test status | |
| Simulation time | 199840519 ps |
| CPU time | 23.31 seconds |
| Started | Jun 28 08:36:12 PM PDT 24 |
| Finished | Jun 28 08:36:42 PM PDT 24 |
| Peak memory | 574412 kb |
| Host | smart-f5f91948-b1fc-462f-8032-c5210039e94e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2838865021 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.xbar_error_and_unmapped_add r.2838865021 |
| Directory | /workspace/15.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/15.xbar_error_random.4268855370 |
| Short name | T2116 |
| Test name | |
| Test status | |
| Simulation time | 441805142 ps |
| CPU time | 41.61 seconds |
| Started | Jun 28 08:35:54 PM PDT 24 |
| Finished | Jun 28 08:36:54 PM PDT 24 |
| Peak memory | 573820 kb |
| Host | smart-c0704f5a-8bb2-4396-b845-d2828b35367f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4268855370 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.xbar_error_random.4268855370 |
| Directory | /workspace/15.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/15.xbar_random.3673474724 |
| Short name | T2725 |
| Test name | |
| Test status | |
| Simulation time | 553997844 ps |
| CPU time | 25.2 seconds |
| Started | Jun 28 08:35:59 PM PDT 24 |
| Finished | Jun 28 08:36:39 PM PDT 24 |
| Peak memory | 575252 kb |
| Host | smart-f99ea0b4-041e-49e7-9dd4-0f5a4ef437d4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3673474724 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.xbar_random.3673474724 |
| Directory | /workspace/15.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/15.xbar_random_large_delays.4211413745 |
| Short name | T1519 |
| Test name | |
| Test status | |
| Simulation time | 71015619218 ps |
| CPU time | 805.65 seconds |
| Started | Jun 28 08:35:58 PM PDT 24 |
| Finished | Jun 28 08:49:40 PM PDT 24 |
| Peak memory | 575296 kb |
| Host | smart-163e2e0c-c481-452b-8fae-e2fbeb0dda35 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4211413745 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.xbar_random_large_delays.4211413745 |
| Directory | /workspace/15.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/15.xbar_random_slow_rsp.1412851997 |
| Short name | T2671 |
| Test name | |
| Test status | |
| Simulation time | 65395696092 ps |
| CPU time | 1197.35 seconds |
| Started | Jun 28 08:35:56 PM PDT 24 |
| Finished | Jun 28 08:56:11 PM PDT 24 |
| Peak memory | 574264 kb |
| Host | smart-16da857d-7290-44b2-8083-2894b42c151c |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1412851997 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.xbar_random_slow_rsp.1412851997 |
| Directory | /workspace/15.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/15.xbar_random_zero_delays.1873021200 |
| Short name | T2160 |
| Test name | |
| Test status | |
| Simulation time | 393317209 ps |
| CPU time | 36.73 seconds |
| Started | Jun 28 08:35:56 PM PDT 24 |
| Finished | Jun 28 08:36:49 PM PDT 24 |
| Peak memory | 575284 kb |
| Host | smart-1abdec2b-6acf-4b7f-a23d-4cd731e727ee |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1873021200 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.xbar_random_zero_del ays.1873021200 |
| Directory | /workspace/15.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/15.xbar_same_source.2502225901 |
| Short name | T1748 |
| Test name | |
| Test status | |
| Simulation time | 576817942 ps |
| CPU time | 47.29 seconds |
| Started | Jun 28 08:35:55 PM PDT 24 |
| Finished | Jun 28 08:37:00 PM PDT 24 |
| Peak memory | 574176 kb |
| Host | smart-dfb16dbd-ad4e-4021-bc8f-5a318979198b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2502225901 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.xbar_same_source.2502225901 |
| Directory | /workspace/15.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/15.xbar_smoke.161505831 |
| Short name | T1871 |
| Test name | |
| Test status | |
| Simulation time | 207637466 ps |
| CPU time | 10.05 seconds |
| Started | Jun 28 08:35:52 PM PDT 24 |
| Finished | Jun 28 08:36:22 PM PDT 24 |
| Peak memory | 574176 kb |
| Host | smart-b52ec9b6-0189-4b3f-ae09-deba61cc0932 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=161505831 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.xbar_smoke.161505831 |
| Directory | /workspace/15.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/15.xbar_smoke_large_delays.1282129300 |
| Short name | T2616 |
| Test name | |
| Test status | |
| Simulation time | 7072055034 ps |
| CPU time | 77.56 seconds |
| Started | Jun 28 08:35:55 PM PDT 24 |
| Finished | Jun 28 08:37:30 PM PDT 24 |
| Peak memory | 574264 kb |
| Host | smart-e666b1be-7cbc-425e-bcea-8762d56b896e |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1282129300 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.xbar_smoke_large_delays.1282129300 |
| Directory | /workspace/15.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/15.xbar_smoke_slow_rsp.2946336297 |
| Short name | T1442 |
| Test name | |
| Test status | |
| Simulation time | 4625906378 ps |
| CPU time | 80.81 seconds |
| Started | Jun 28 08:35:58 PM PDT 24 |
| Finished | Jun 28 08:37:35 PM PDT 24 |
| Peak memory | 566016 kb |
| Host | smart-4416b774-2ba8-466f-8236-8b17c4b78823 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2946336297 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.xbar_smoke_slow_rsp.2946336297 |
| Directory | /workspace/15.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/15.xbar_smoke_zero_delays.1270960745 |
| Short name | T2360 |
| Test name | |
| Test status | |
| Simulation time | 48289524 ps |
| CPU time | 7.24 seconds |
| Started | Jun 28 08:35:58 PM PDT 24 |
| Finished | Jun 28 08:36:21 PM PDT 24 |
| Peak memory | 574164 kb |
| Host | smart-ad78f9ff-7a34-4edb-829a-1922da55bbd9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1270960745 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.xbar_smoke_zero_delay s.1270960745 |
| Directory | /workspace/15.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/15.xbar_stress_all.2861747002 |
| Short name | T446 |
| Test name | |
| Test status | |
| Simulation time | 2147219941 ps |
| CPU time | 180.31 seconds |
| Started | Jun 28 08:36:13 PM PDT 24 |
| Finished | Jun 28 08:39:20 PM PDT 24 |
| Peak memory | 575300 kb |
| Host | smart-1fe7ff3f-df6b-475c-a9eb-18cfc55655b8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2861747002 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.xbar_stress_all.2861747002 |
| Directory | /workspace/15.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/15.xbar_stress_all_with_error.510824038 |
| Short name | T1974 |
| Test name | |
| Test status | |
| Simulation time | 1947191671 ps |
| CPU time | 186.47 seconds |
| Started | Jun 28 08:36:13 PM PDT 24 |
| Finished | Jun 28 08:39:26 PM PDT 24 |
| Peak memory | 574588 kb |
| Host | smart-25f614be-40d1-4388-a22a-d073492f0280 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=510824038 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.xbar_stress_all_with_error.510824038 |
| Directory | /workspace/15.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/15.xbar_stress_all_with_rand_reset.2169572413 |
| Short name | T2414 |
| Test name | |
| Test status | |
| Simulation time | 28076763557 ps |
| CPU time | 1315.33 seconds |
| Started | Jun 28 08:36:11 PM PDT 24 |
| Finished | Jun 28 08:58:14 PM PDT 24 |
| Peak memory | 575460 kb |
| Host | smart-a2714d6a-32f5-460f-ac60-ac0cc5bad1a2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2169572413 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.xbar_stress_all _with_rand_reset.2169572413 |
| Directory | /workspace/15.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/15.xbar_stress_all_with_reset_error.3248101759 |
| Short name | T2324 |
| Test name | |
| Test status | |
| Simulation time | 3738654422 ps |
| CPU time | 374.22 seconds |
| Started | Jun 28 08:36:12 PM PDT 24 |
| Finished | Jun 28 08:42:33 PM PDT 24 |
| Peak memory | 574676 kb |
| Host | smart-1117c17a-6892-4a69-a97f-99f50e3cf9ab |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3248101759 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.xbar_stress_al l_with_reset_error.3248101759 |
| Directory | /workspace/15.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/15.xbar_unmapped_addr.701975774 |
| Short name | T2152 |
| Test name | |
| Test status | |
| Simulation time | 381859771 ps |
| CPU time | 16.99 seconds |
| Started | Jun 28 08:36:18 PM PDT 24 |
| Finished | Jun 28 08:36:43 PM PDT 24 |
| Peak memory | 575264 kb |
| Host | smart-e7454952-9baf-402d-81ba-a470604d5533 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=701975774 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.xbar_unmapped_addr.701975774 |
| Directory | /workspace/15.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/16.chip_csr_rw.1968818309 |
| Short name | T2284 |
| Test name | |
| Test status | |
| Simulation time | 4741222375 ps |
| CPU time | 407.11 seconds |
| Started | Jun 28 08:36:28 PM PDT 24 |
| Finished | Jun 28 08:43:27 PM PDT 24 |
| Peak memory | 595740 kb |
| Host | smart-86507d61-4fde-40c1-8b2c-d9a0a0cfc28d |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1968818309 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.chip_csr_rw.1968818309 |
| Directory | /workspace/16.chip_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/16.chip_same_csr_outstanding.3825567220 |
| Short name | T140 |
| Test name | |
| Test status | |
| Simulation time | 15766688231 ps |
| CPU time | 1755.09 seconds |
| Started | Jun 28 08:36:13 PM PDT 24 |
| Finished | Jun 28 09:05:35 PM PDT 24 |
| Peak memory | 591804 kb |
| Host | smart-fe6ec67e-51a9-4330-9a20-2719c3aabd65 |
| User | root |
| Command | /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +run_same_csr_outstanding +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3825567220 -assert nopostproc +UVM_TE STNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb - cm_log /dev/null -cm_name 16.chip_same_csr_outstanding.3825567220 |
| Directory | /workspace/16.chip_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/16.xbar_access_same_device.2221523523 |
| Short name | T1630 |
| Test name | |
| Test status | |
| Simulation time | 897007960 ps |
| CPU time | 83.15 seconds |
| Started | Jun 28 08:36:13 PM PDT 24 |
| Finished | Jun 28 08:37:43 PM PDT 24 |
| Peak memory | 575260 kb |
| Host | smart-7479aeca-6412-4b75-94d0-61b5d61bc981 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2221523523 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.xbar_access_same_device .2221523523 |
| Directory | /workspace/16.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/16.xbar_access_same_device_slow_rsp.2115166448 |
| Short name | T2430 |
| Test name | |
| Test status | |
| Simulation time | 2542000279 ps |
| CPU time | 46.24 seconds |
| Started | Jun 28 08:36:13 PM PDT 24 |
| Finished | Jun 28 08:37:07 PM PDT 24 |
| Peak memory | 566032 kb |
| Host | smart-651a38e0-3eb5-4212-823f-1637285d02a0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2115166448 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.xbar_access_same_ device_slow_rsp.2115166448 |
| Directory | /workspace/16.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/16.xbar_error_and_unmapped_addr.1969330 |
| Short name | T2265 |
| Test name | |
| Test status | |
| Simulation time | 335499540 ps |
| CPU time | 31.13 seconds |
| Started | Jun 28 08:36:28 PM PDT 24 |
| Finished | Jun 28 08:37:11 PM PDT 24 |
| Peak memory | 574424 kb |
| Host | smart-3e496552-2ce9-4bbb-ac05-711abdfc9d10 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1969330 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.xbar_error_and_unmapped_addr.1969330 |
| Directory | /workspace/16.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/16.xbar_error_random.3489265047 |
| Short name | T1710 |
| Test name | |
| Test status | |
| Simulation time | 621907732 ps |
| CPU time | 58.45 seconds |
| Started | Jun 28 08:36:14 PM PDT 24 |
| Finished | Jun 28 08:37:20 PM PDT 24 |
| Peak memory | 574564 kb |
| Host | smart-fb10d727-dd44-4109-8e7a-3acd96886147 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3489265047 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.xbar_error_random.3489265047 |
| Directory | /workspace/16.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/16.xbar_random.452808389 |
| Short name | T577 |
| Test name | |
| Test status | |
| Simulation time | 619398555 ps |
| CPU time | 59.18 seconds |
| Started | Jun 28 08:36:13 PM PDT 24 |
| Finished | Jun 28 08:37:19 PM PDT 24 |
| Peak memory | 575280 kb |
| Host | smart-03ca6efa-0829-4e40-94c0-820c1af9612a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=452808389 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.xbar_random.452808389 |
| Directory | /workspace/16.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/16.xbar_random_large_delays.313677347 |
| Short name | T1444 |
| Test name | |
| Test status | |
| Simulation time | 46696004760 ps |
| CPU time | 506.77 seconds |
| Started | Jun 28 08:36:16 PM PDT 24 |
| Finished | Jun 28 08:44:51 PM PDT 24 |
| Peak memory | 574260 kb |
| Host | smart-c6aa3638-1048-48b4-9139-77fba67ae4f9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=313677347 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.xbar_random_large_delays.313677347 |
| Directory | /workspace/16.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/16.xbar_random_slow_rsp.3226271364 |
| Short name | T1583 |
| Test name | |
| Test status | |
| Simulation time | 9048876006 ps |
| CPU time | 165.19 seconds |
| Started | Jun 28 08:36:13 PM PDT 24 |
| Finished | Jun 28 08:39:05 PM PDT 24 |
| Peak memory | 574260 kb |
| Host | smart-3fb60dd9-8b5f-44f9-be82-35b4115b947f |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3226271364 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.xbar_random_slow_rsp.3226271364 |
| Directory | /workspace/16.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/16.xbar_random_zero_delays.1694070658 |
| Short name | T1326 |
| Test name | |
| Test status | |
| Simulation time | 122208678 ps |
| CPU time | 15.45 seconds |
| Started | Jun 28 08:36:12 PM PDT 24 |
| Finished | Jun 28 08:36:34 PM PDT 24 |
| Peak memory | 575248 kb |
| Host | smart-a71c0901-1448-4431-8b92-f8134ce1a21e |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1694070658 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.xbar_random_zero_del ays.1694070658 |
| Directory | /workspace/16.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/16.xbar_same_source.791372481 |
| Short name | T1740 |
| Test name | |
| Test status | |
| Simulation time | 440467312 ps |
| CPU time | 39.14 seconds |
| Started | Jun 28 08:36:14 PM PDT 24 |
| Finished | Jun 28 08:37:01 PM PDT 24 |
| Peak memory | 575352 kb |
| Host | smart-c0055bf5-bbb2-4a02-bc99-604ce33ec897 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=791372481 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.xbar_same_source.791372481 |
| Directory | /workspace/16.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/16.xbar_smoke.2343210502 |
| Short name | T2538 |
| Test name | |
| Test status | |
| Simulation time | 196954146 ps |
| CPU time | 9.47 seconds |
| Started | Jun 28 08:36:12 PM PDT 24 |
| Finished | Jun 28 08:36:28 PM PDT 24 |
| Peak memory | 574196 kb |
| Host | smart-da4a7e77-f8c2-45ec-8c65-f2d8703ff1a9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2343210502 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.xbar_smoke.2343210502 |
| Directory | /workspace/16.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/16.xbar_smoke_large_delays.770131930 |
| Short name | T1347 |
| Test name | |
| Test status | |
| Simulation time | 8602485563 ps |
| CPU time | 94.74 seconds |
| Started | Jun 28 08:36:12 PM PDT 24 |
| Finished | Jun 28 08:37:54 PM PDT 24 |
| Peak memory | 574264 kb |
| Host | smart-e5f3f94c-9da0-488a-9781-5e201e7cf0d5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=770131930 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.xbar_smoke_large_delays.770131930 |
| Directory | /workspace/16.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/16.xbar_smoke_slow_rsp.740710100 |
| Short name | T2320 |
| Test name | |
| Test status | |
| Simulation time | 5099236641 ps |
| CPU time | 87.93 seconds |
| Started | Jun 28 08:36:12 PM PDT 24 |
| Finished | Jun 28 08:37:47 PM PDT 24 |
| Peak memory | 566028 kb |
| Host | smart-4fa24c6f-d939-49ee-beb0-3b878b17b0d2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=740710100 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.xbar_smoke_slow_rsp.740710100 |
| Directory | /workspace/16.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/16.xbar_smoke_zero_delays.515032912 |
| Short name | T2199 |
| Test name | |
| Test status | |
| Simulation time | 49367243 ps |
| CPU time | 6.4 seconds |
| Started | Jun 28 08:36:15 PM PDT 24 |
| Finished | Jun 28 08:36:29 PM PDT 24 |
| Peak memory | 574192 kb |
| Host | smart-558f2fcb-58f3-4122-9efe-05db2c8fb061 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=515032912 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.xbar_smoke_zero_delays .515032912 |
| Directory | /workspace/16.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/16.xbar_stress_all.1853534667 |
| Short name | T476 |
| Test name | |
| Test status | |
| Simulation time | 1154355559 ps |
| CPU time | 112.95 seconds |
| Started | Jun 28 08:36:29 PM PDT 24 |
| Finished | Jun 28 08:38:35 PM PDT 24 |
| Peak memory | 574324 kb |
| Host | smart-629001b2-7a0e-412e-97c4-5cb72ecee832 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1853534667 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.xbar_stress_all.1853534667 |
| Directory | /workspace/16.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/16.xbar_stress_all_with_error.1016586105 |
| Short name | T2720 |
| Test name | |
| Test status | |
| Simulation time | 2160585369 ps |
| CPU time | 76.66 seconds |
| Started | Jun 28 08:36:28 PM PDT 24 |
| Finished | Jun 28 08:37:56 PM PDT 24 |
| Peak memory | 573984 kb |
| Host | smart-bdd93ae7-f58b-4cb4-a6c0-d8008e53ae3b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1016586105 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.xbar_stress_all_with_error.1016586105 |
| Directory | /workspace/16.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/16.xbar_stress_all_with_rand_reset.2683012670 |
| Short name | T2036 |
| Test name | |
| Test status | |
| Simulation time | 147880228 ps |
| CPU time | 53.98 seconds |
| Started | Jun 28 08:36:28 PM PDT 24 |
| Finished | Jun 28 08:37:33 PM PDT 24 |
| Peak memory | 575344 kb |
| Host | smart-a6a24a1d-6ea8-47bc-b05f-cfb240a77349 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2683012670 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.xbar_stress_all _with_rand_reset.2683012670 |
| Directory | /workspace/16.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/16.xbar_stress_all_with_reset_error.1154785816 |
| Short name | T836 |
| Test name | |
| Test status | |
| Simulation time | 4459429388 ps |
| CPU time | 301.94 seconds |
| Started | Jun 28 08:36:28 PM PDT 24 |
| Finished | Jun 28 08:41:41 PM PDT 24 |
| Peak memory | 576436 kb |
| Host | smart-aa9390ce-2578-4c94-9145-dfa1105a78a3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1154785816 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.xbar_stress_al l_with_reset_error.1154785816 |
| Directory | /workspace/16.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/16.xbar_unmapped_addr.1445819738 |
| Short name | T1459 |
| Test name | |
| Test status | |
| Simulation time | 417457073 ps |
| CPU time | 19.98 seconds |
| Started | Jun 28 08:36:30 PM PDT 24 |
| Finished | Jun 28 08:37:04 PM PDT 24 |
| Peak memory | 574256 kb |
| Host | smart-419be8b8-cb5b-4502-87b4-886480bcc5c2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1445819738 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.xbar_unmapped_addr.1445819738 |
| Directory | /workspace/16.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/17.chip_csr_rw.4189256060 |
| Short name | T375 |
| Test name | |
| Test status | |
| Simulation time | 3786181390 ps |
| CPU time | 315.46 seconds |
| Started | Jun 28 08:36:51 PM PDT 24 |
| Finished | Jun 28 08:42:29 PM PDT 24 |
| Peak memory | 596152 kb |
| Host | smart-1c1d28fb-2dc4-411c-bf55-3e8912d3db0e |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4189256060 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.chip_csr_rw.4189256060 |
| Directory | /workspace/17.chip_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/17.chip_same_csr_outstanding.997886013 |
| Short name | T2604 |
| Test name | |
| Test status | |
| Simulation time | 16117805287 ps |
| CPU time | 1755.32 seconds |
| Started | Jun 28 08:36:28 PM PDT 24 |
| Finished | Jun 28 09:05:55 PM PDT 24 |
| Peak memory | 591740 kb |
| Host | smart-d7be06d1-2b06-4789-9122-d046fa7f9791 |
| User | root |
| Command | /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +run_same_csr_outstanding +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=997886013 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c m_log /dev/null -cm_name 17.chip_same_csr_outstanding.997886013 |
| Directory | /workspace/17.chip_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/17.chip_tl_errors.2740889902 |
| Short name | T639 |
| Test name | |
| Test status | |
| Simulation time | 3820599043 ps |
| CPU time | 351.23 seconds |
| Started | Jun 28 08:36:33 PM PDT 24 |
| Finished | Jun 28 08:42:40 PM PDT 24 |
| Peak memory | 597440 kb |
| Host | smart-b37f65cb-0279-41c8-aacf-f25d18f5faf5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2740889902 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.chip_tl_errors.2740889902 |
| Directory | /workspace/17.chip_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/17.xbar_access_same_device.1462602450 |
| Short name | T810 |
| Test name | |
| Test status | |
| Simulation time | 1392586661 ps |
| CPU time | 57.63 seconds |
| Started | Jun 28 08:36:29 PM PDT 24 |
| Finished | Jun 28 08:37:41 PM PDT 24 |
| Peak memory | 574164 kb |
| Host | smart-addb8098-d78e-45da-8fde-fd845ffd90c1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1462602450 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.xbar_access_same_device .1462602450 |
| Directory | /workspace/17.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/17.xbar_access_same_device_slow_rsp.3878498049 |
| Short name | T2794 |
| Test name | |
| Test status | |
| Simulation time | 32819952055 ps |
| CPU time | 596.42 seconds |
| Started | Jun 28 08:36:50 PM PDT 24 |
| Finished | Jun 28 08:47:10 PM PDT 24 |
| Peak memory | 575344 kb |
| Host | smart-f201c72e-6e36-4fbf-b861-725c6182ea07 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3878498049 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.xbar_access_same_ device_slow_rsp.3878498049 |
| Directory | /workspace/17.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/17.xbar_error_and_unmapped_addr.3910368233 |
| Short name | T1632 |
| Test name | |
| Test status | |
| Simulation time | 539894606 ps |
| CPU time | 25.36 seconds |
| Started | Jun 28 08:36:50 PM PDT 24 |
| Finished | Jun 28 08:37:38 PM PDT 24 |
| Peak memory | 574456 kb |
| Host | smart-8494fda4-70d0-4bfd-8f0e-1524d1643167 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3910368233 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.xbar_error_and_unmapped_add r.3910368233 |
| Directory | /workspace/17.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/17.xbar_error_random.3106297474 |
| Short name | T2628 |
| Test name | |
| Test status | |
| Simulation time | 261680612 ps |
| CPU time | 26.6 seconds |
| Started | Jun 28 08:36:57 PM PDT 24 |
| Finished | Jun 28 08:37:43 PM PDT 24 |
| Peak memory | 574412 kb |
| Host | smart-b4b4fefb-d901-4682-b35c-cfddd72f09b4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3106297474 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.xbar_error_random.3106297474 |
| Directory | /workspace/17.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/17.xbar_random.1620370028 |
| Short name | T2454 |
| Test name | |
| Test status | |
| Simulation time | 316999797 ps |
| CPU time | 16.22 seconds |
| Started | Jun 28 08:36:29 PM PDT 24 |
| Finished | Jun 28 08:36:58 PM PDT 24 |
| Peak memory | 575244 kb |
| Host | smart-53443d25-6d39-48f9-a8da-26c3b5416411 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1620370028 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.xbar_random.1620370028 |
| Directory | /workspace/17.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/17.xbar_random_large_delays.4279723 |
| Short name | T2224 |
| Test name | |
| Test status | |
| Simulation time | 32876375466 ps |
| CPU time | 382.98 seconds |
| Started | Jun 28 08:36:33 PM PDT 24 |
| Finished | Jun 28 08:43:14 PM PDT 24 |
| Peak memory | 574248 kb |
| Host | smart-864b30c1-1e32-4963-92d3-e86544dfa600 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4279723 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.xbar_random_large_delays.4279723 |
| Directory | /workspace/17.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/17.xbar_random_slow_rsp.3266939989 |
| Short name | T2409 |
| Test name | |
| Test status | |
| Simulation time | 67123613402 ps |
| CPU time | 1164.32 seconds |
| Started | Jun 28 08:36:28 PM PDT 24 |
| Finished | Jun 28 08:56:04 PM PDT 24 |
| Peak memory | 575476 kb |
| Host | smart-01c1dc41-209d-4112-af56-a9f184f9cc79 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3266939989 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.xbar_random_slow_rsp.3266939989 |
| Directory | /workspace/17.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/17.xbar_random_zero_delays.1684221955 |
| Short name | T1983 |
| Test name | |
| Test status | |
| Simulation time | 217969023 ps |
| CPU time | 25.88 seconds |
| Started | Jun 28 08:36:30 PM PDT 24 |
| Finished | Jun 28 08:37:10 PM PDT 24 |
| Peak memory | 575228 kb |
| Host | smart-84147381-ccfd-4c51-91d9-3306eabbf6a8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1684221955 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.xbar_random_zero_del ays.1684221955 |
| Directory | /workspace/17.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/17.xbar_same_source.989421552 |
| Short name | T2584 |
| Test name | |
| Test status | |
| Simulation time | 2476560639 ps |
| CPU time | 77.58 seconds |
| Started | Jun 28 08:36:49 PM PDT 24 |
| Finished | Jun 28 08:38:31 PM PDT 24 |
| Peak memory | 574232 kb |
| Host | smart-11f87d49-6eb8-4d93-9174-a75af6080ea6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=989421552 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.xbar_same_source.989421552 |
| Directory | /workspace/17.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/17.xbar_smoke.1899127647 |
| Short name | T2439 |
| Test name | |
| Test status | |
| Simulation time | 46381600 ps |
| CPU time | 6.09 seconds |
| Started | Jun 28 08:36:28 PM PDT 24 |
| Finished | Jun 28 08:36:45 PM PDT 24 |
| Peak memory | 565956 kb |
| Host | smart-2b51307a-76e6-4ccd-a751-c366c29f7baa |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1899127647 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.xbar_smoke.1899127647 |
| Directory | /workspace/17.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/17.xbar_smoke_large_delays.2815809957 |
| Short name | T2087 |
| Test name | |
| Test status | |
| Simulation time | 10625697175 ps |
| CPU time | 110.03 seconds |
| Started | Jun 28 08:36:27 PM PDT 24 |
| Finished | Jun 28 08:38:28 PM PDT 24 |
| Peak memory | 574264 kb |
| Host | smart-9a4fe191-5f3d-4dc3-8210-0daba1ed5bd4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2815809957 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.xbar_smoke_large_delays.2815809957 |
| Directory | /workspace/17.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/17.xbar_smoke_slow_rsp.1124980511 |
| Short name | T780 |
| Test name | |
| Test status | |
| Simulation time | 5204617525 ps |
| CPU time | 86.33 seconds |
| Started | Jun 28 08:36:29 PM PDT 24 |
| Finished | Jun 28 08:38:09 PM PDT 24 |
| Peak memory | 574260 kb |
| Host | smart-7f77a8d8-1620-46e0-91b4-3b543dc6d421 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1124980511 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.xbar_smoke_slow_rsp.1124980511 |
| Directory | /workspace/17.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/17.xbar_smoke_zero_delays.3463508620 |
| Short name | T1899 |
| Test name | |
| Test status | |
| Simulation time | 40236525 ps |
| CPU time | 6.7 seconds |
| Started | Jun 28 08:36:29 PM PDT 24 |
| Finished | Jun 28 08:36:49 PM PDT 24 |
| Peak memory | 574132 kb |
| Host | smart-401ed959-5526-4a18-94c6-217f9fc8ddd5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3463508620 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.xbar_smoke_zero_delay s.3463508620 |
| Directory | /workspace/17.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/17.xbar_stress_all.1443751582 |
| Short name | T485 |
| Test name | |
| Test status | |
| Simulation time | 4675677694 ps |
| CPU time | 193.13 seconds |
| Started | Jun 28 08:36:50 PM PDT 24 |
| Finished | Jun 28 08:40:27 PM PDT 24 |
| Peak memory | 575388 kb |
| Host | smart-6ff44e12-6286-46ab-a8fd-4c3abdbcf94c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1443751582 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.xbar_stress_all.1443751582 |
| Directory | /workspace/17.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/17.xbar_stress_all_with_error.3072096546 |
| Short name | T1508 |
| Test name | |
| Test status | |
| Simulation time | 4562044872 ps |
| CPU time | 359.71 seconds |
| Started | Jun 28 08:36:56 PM PDT 24 |
| Finished | Jun 28 08:43:16 PM PDT 24 |
| Peak memory | 574396 kb |
| Host | smart-04f91093-682b-4383-b96f-690a3f1fcf12 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3072096546 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.xbar_stress_all_with_error.3072096546 |
| Directory | /workspace/17.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/17.xbar_stress_all_with_rand_reset.1763867825 |
| Short name | T2747 |
| Test name | |
| Test status | |
| Simulation time | 6128683051 ps |
| CPU time | 378.05 seconds |
| Started | Jun 28 08:36:57 PM PDT 24 |
| Finished | Jun 28 08:43:35 PM PDT 24 |
| Peak memory | 575344 kb |
| Host | smart-fa741b50-1e49-4120-8804-eb513005b31f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1763867825 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.xbar_stress_all _with_rand_reset.1763867825 |
| Directory | /workspace/17.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/17.xbar_unmapped_addr.2446431286 |
| Short name | T2348 |
| Test name | |
| Test status | |
| Simulation time | 164656804 ps |
| CPU time | 10.5 seconds |
| Started | Jun 28 08:36:50 PM PDT 24 |
| Finished | Jun 28 08:37:23 PM PDT 24 |
| Peak memory | 574168 kb |
| Host | smart-6adbf6e1-8a67-4d49-ac45-225db034ab6f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2446431286 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.xbar_unmapped_addr.2446431286 |
| Directory | /workspace/17.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/18.chip_csr_rw.2047190770 |
| Short name | T2745 |
| Test name | |
| Test status | |
| Simulation time | 5253010995 ps |
| CPU time | 649.54 seconds |
| Started | Jun 28 08:37:03 PM PDT 24 |
| Finished | Jun 28 08:48:07 PM PDT 24 |
| Peak memory | 596260 kb |
| Host | smart-d5cf39d9-15dd-405e-9ddd-f08b9be31ece |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2047190770 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.chip_csr_rw.2047190770 |
| Directory | /workspace/18.chip_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/18.chip_same_csr_outstanding.2347504923 |
| Short name | T427 |
| Test name | |
| Test status | |
| Simulation time | 33920927115 ps |
| CPU time | 3716.06 seconds |
| Started | Jun 28 08:36:57 PM PDT 24 |
| Finished | Jun 28 09:39:13 PM PDT 24 |
| Peak memory | 592080 kb |
| Host | smart-14b0a5f6-9798-4f2a-bacb-a6031bccafdc |
| User | root |
| Command | /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +run_same_csr_outstanding +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2347504923 -assert nopostproc +UVM_TE STNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb - cm_log /dev/null -cm_name 18.chip_same_csr_outstanding.2347504923 |
| Directory | /workspace/18.chip_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/18.chip_tl_errors.825419027 |
| Short name | T660 |
| Test name | |
| Test status | |
| Simulation time | 3786717804 ps |
| CPU time | 261.69 seconds |
| Started | Jun 28 08:36:52 PM PDT 24 |
| Finished | Jun 28 08:41:35 PM PDT 24 |
| Peak memory | 597736 kb |
| Host | smart-da3ef76d-a5d1-4001-b612-6003b74ade33 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=825419027 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.chip_tl_errors.825419027 |
| Directory | /workspace/18.chip_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/18.xbar_access_same_device.1249856782 |
| Short name | T1875 |
| Test name | |
| Test status | |
| Simulation time | 1809832681 ps |
| CPU time | 75.01 seconds |
| Started | Jun 28 08:37:11 PM PDT 24 |
| Finished | Jun 28 08:38:36 PM PDT 24 |
| Peak memory | 575236 kb |
| Host | smart-ded48c73-cd75-4808-b9b5-501a0c01359d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1249856782 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.xbar_access_same_device .1249856782 |
| Directory | /workspace/18.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/18.xbar_error_and_unmapped_addr.3386018599 |
| Short name | T1673 |
| Test name | |
| Test status | |
| Simulation time | 332139240 ps |
| CPU time | 34.52 seconds |
| Started | Jun 28 08:37:05 PM PDT 24 |
| Finished | Jun 28 08:37:53 PM PDT 24 |
| Peak memory | 574452 kb |
| Host | smart-da914a28-e209-4b5a-98c2-724878e7e395 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3386018599 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.xbar_error_and_unmapped_add r.3386018599 |
| Directory | /workspace/18.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/18.xbar_error_random.2896844798 |
| Short name | T2244 |
| Test name | |
| Test status | |
| Simulation time | 346244176 ps |
| CPU time | 31.22 seconds |
| Started | Jun 28 08:37:06 PM PDT 24 |
| Finished | Jun 28 08:37:50 PM PDT 24 |
| Peak memory | 574444 kb |
| Host | smart-bc7f46c4-0194-4dc1-94d4-b85facbc6140 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2896844798 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.xbar_error_random.2896844798 |
| Directory | /workspace/18.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/18.xbar_random.2239450802 |
| Short name | T1960 |
| Test name | |
| Test status | |
| Simulation time | 2516987404 ps |
| CPU time | 114.79 seconds |
| Started | Jun 28 08:36:50 PM PDT 24 |
| Finished | Jun 28 08:39:08 PM PDT 24 |
| Peak memory | 574272 kb |
| Host | smart-52050910-26ed-4e63-af2d-fbe2433ebed1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2239450802 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.xbar_random.2239450802 |
| Directory | /workspace/18.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/18.xbar_random_large_delays.3466901676 |
| Short name | T1513 |
| Test name | |
| Test status | |
| Simulation time | 15850881115 ps |
| CPU time | 178.08 seconds |
| Started | Jun 28 08:36:52 PM PDT 24 |
| Finished | Jun 28 08:40:12 PM PDT 24 |
| Peak memory | 575324 kb |
| Host | smart-8074ae8f-cfa5-4299-acc1-2168a5164cc0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3466901676 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.xbar_random_large_delays.3466901676 |
| Directory | /workspace/18.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/18.xbar_random_slow_rsp.1757568947 |
| Short name | T1907 |
| Test name | |
| Test status | |
| Simulation time | 36415836338 ps |
| CPU time | 663.1 seconds |
| Started | Jun 28 08:36:50 PM PDT 24 |
| Finished | Jun 28 08:48:16 PM PDT 24 |
| Peak memory | 575336 kb |
| Host | smart-e3fc6353-58b0-4428-921d-3c7c41a5910c |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1757568947 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.xbar_random_slow_rsp.1757568947 |
| Directory | /workspace/18.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/18.xbar_random_zero_delays.2868078881 |
| Short name | T1669 |
| Test name | |
| Test status | |
| Simulation time | 163386368 ps |
| CPU time | 19.08 seconds |
| Started | Jun 28 08:36:50 PM PDT 24 |
| Finished | Jun 28 08:37:33 PM PDT 24 |
| Peak memory | 575244 kb |
| Host | smart-1fc0bdec-ff4e-4120-a51e-502082dd0ca0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2868078881 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.xbar_random_zero_del ays.2868078881 |
| Directory | /workspace/18.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/18.xbar_same_source.484689112 |
| Short name | T2529 |
| Test name | |
| Test status | |
| Simulation time | 2376284448 ps |
| CPU time | 87.01 seconds |
| Started | Jun 28 08:37:05 PM PDT 24 |
| Finished | Jun 28 08:38:46 PM PDT 24 |
| Peak memory | 575296 kb |
| Host | smart-e90f8076-6dfe-4bb6-92f4-b4af1f46b75f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=484689112 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.xbar_same_source.484689112 |
| Directory | /workspace/18.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/18.xbar_smoke.1393660894 |
| Short name | T2782 |
| Test name | |
| Test status | |
| Simulation time | 204714135 ps |
| CPU time | 9.83 seconds |
| Started | Jun 28 08:36:49 PM PDT 24 |
| Finished | Jun 28 08:37:23 PM PDT 24 |
| Peak memory | 574140 kb |
| Host | smart-3853e840-c3ff-4d43-9c57-8d1cd3d32819 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1393660894 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.xbar_smoke.1393660894 |
| Directory | /workspace/18.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/18.xbar_smoke_large_delays.411584054 |
| Short name | T1998 |
| Test name | |
| Test status | |
| Simulation time | 7473916031 ps |
| CPU time | 76.43 seconds |
| Started | Jun 28 08:36:51 PM PDT 24 |
| Finished | Jun 28 08:38:30 PM PDT 24 |
| Peak memory | 574232 kb |
| Host | smart-97ed3e4e-4845-431b-8a42-e44875e0bd5c |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=411584054 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.xbar_smoke_large_delays.411584054 |
| Directory | /workspace/18.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/18.xbar_smoke_slow_rsp.1978437131 |
| Short name | T1479 |
| Test name | |
| Test status | |
| Simulation time | 6971763617 ps |
| CPU time | 122.04 seconds |
| Started | Jun 28 08:36:52 PM PDT 24 |
| Finished | Jun 28 08:39:16 PM PDT 24 |
| Peak memory | 574256 kb |
| Host | smart-1c28c4fe-3d25-41b0-903a-e0c8f2b1b8e9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1978437131 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.xbar_smoke_slow_rsp.1978437131 |
| Directory | /workspace/18.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/18.xbar_smoke_zero_delays.1481258058 |
| Short name | T2556 |
| Test name | |
| Test status | |
| Simulation time | 54695400 ps |
| CPU time | 8.08 seconds |
| Started | Jun 28 08:36:49 PM PDT 24 |
| Finished | Jun 28 08:37:21 PM PDT 24 |
| Peak memory | 574100 kb |
| Host | smart-905164ec-9f95-43d9-9504-33b228b09192 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1481258058 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.xbar_smoke_zero_delay s.1481258058 |
| Directory | /workspace/18.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/18.xbar_stress_all.2317627424 |
| Short name | T450 |
| Test name | |
| Test status | |
| Simulation time | 4664076338 ps |
| CPU time | 439.98 seconds |
| Started | Jun 28 08:37:07 PM PDT 24 |
| Finished | Jun 28 08:44:40 PM PDT 24 |
| Peak memory | 575436 kb |
| Host | smart-9dd7ba81-8c2a-46ee-9444-97f581486917 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2317627424 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.xbar_stress_all.2317627424 |
| Directory | /workspace/18.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/18.xbar_stress_all_with_error.3949497176 |
| Short name | T2263 |
| Test name | |
| Test status | |
| Simulation time | 7040518268 ps |
| CPU time | 233.61 seconds |
| Started | Jun 28 08:37:10 PM PDT 24 |
| Finished | Jun 28 08:41:15 PM PDT 24 |
| Peak memory | 574300 kb |
| Host | smart-ddcc0e21-84aa-476d-b4f8-24267ffe7903 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3949497176 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.xbar_stress_all_with_error.3949497176 |
| Directory | /workspace/18.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/18.xbar_stress_all_with_rand_reset.3067681849 |
| Short name | T1605 |
| Test name | |
| Test status | |
| Simulation time | 572930018 ps |
| CPU time | 169.5 seconds |
| Started | Jun 28 08:37:05 PM PDT 24 |
| Finished | Jun 28 08:40:08 PM PDT 24 |
| Peak memory | 576288 kb |
| Host | smart-a70259d1-f9f2-442a-850b-1f17600a37a2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3067681849 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.xbar_stress_all _with_rand_reset.3067681849 |
| Directory | /workspace/18.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/18.xbar_stress_all_with_reset_error.2952879472 |
| Short name | T1844 |
| Test name | |
| Test status | |
| Simulation time | 655993637 ps |
| CPU time | 147.14 seconds |
| Started | Jun 28 08:37:08 PM PDT 24 |
| Finished | Jun 28 08:39:47 PM PDT 24 |
| Peak memory | 575296 kb |
| Host | smart-3feb0097-bb4e-46b0-973f-22b6e746092d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2952879472 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.xbar_stress_al l_with_reset_error.2952879472 |
| Directory | /workspace/18.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/18.xbar_unmapped_addr.1000316549 |
| Short name | T590 |
| Test name | |
| Test status | |
| Simulation time | 220074190 ps |
| CPU time | 12.26 seconds |
| Started | Jun 28 08:37:06 PM PDT 24 |
| Finished | Jun 28 08:37:31 PM PDT 24 |
| Peak memory | 574300 kb |
| Host | smart-af4b71c7-07ba-411b-8051-da05948d85e2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1000316549 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.xbar_unmapped_addr.1000316549 |
| Directory | /workspace/18.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/19.chip_csr_rw.1197986763 |
| Short name | T1676 |
| Test name | |
| Test status | |
| Simulation time | 5343628299 ps |
| CPU time | 560.44 seconds |
| Started | Jun 28 08:37:09 PM PDT 24 |
| Finished | Jun 28 08:46:41 PM PDT 24 |
| Peak memory | 596584 kb |
| Host | smart-03c5725b-1004-4ed9-b2b5-2d76cee6dc9d |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1197986763 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.chip_csr_rw.1197986763 |
| Directory | /workspace/19.chip_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/19.chip_same_csr_outstanding.1478221295 |
| Short name | T1961 |
| Test name | |
| Test status | |
| Simulation time | 16114083215 ps |
| CPU time | 1699.3 seconds |
| Started | Jun 28 08:37:09 PM PDT 24 |
| Finished | Jun 28 09:05:40 PM PDT 24 |
| Peak memory | 591828 kb |
| Host | smart-3176227f-b85e-49b3-9433-30f13e365f14 |
| User | root |
| Command | /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +run_same_csr_outstanding +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1478221295 -assert nopostproc +UVM_TE STNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb - cm_log /dev/null -cm_name 19.chip_same_csr_outstanding.1478221295 |
| Directory | /workspace/19.chip_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/19.chip_tl_errors.1786162610 |
| Short name | T549 |
| Test name | |
| Test status | |
| Simulation time | 3450059037 ps |
| CPU time | 265.42 seconds |
| Started | Jun 28 08:37:09 PM PDT 24 |
| Finished | Jun 28 08:41:46 PM PDT 24 |
| Peak memory | 597348 kb |
| Host | smart-5a570465-5b84-45c4-a1cc-6afa3cc72e04 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1786162610 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.chip_tl_errors.1786162610 |
| Directory | /workspace/19.chip_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/19.xbar_access_same_device.3375363365 |
| Short name | T2489 |
| Test name | |
| Test status | |
| Simulation time | 893035208 ps |
| CPU time | 59.44 seconds |
| Started | Jun 28 08:37:12 PM PDT 24 |
| Finished | Jun 28 08:38:21 PM PDT 24 |
| Peak memory | 574212 kb |
| Host | smart-d65641bf-15c3-4709-ae49-84066c57f340 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3375363365 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.xbar_access_same_device .3375363365 |
| Directory | /workspace/19.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/19.xbar_access_same_device_slow_rsp.3005266093 |
| Short name | T2583 |
| Test name | |
| Test status | |
| Simulation time | 146786996997 ps |
| CPU time | 2482.08 seconds |
| Started | Jun 28 08:37:07 PM PDT 24 |
| Finished | Jun 28 09:18:42 PM PDT 24 |
| Peak memory | 575372 kb |
| Host | smart-691d91b0-e65b-4ca1-85a2-f4e745e6473e |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3005266093 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.xbar_access_same_ device_slow_rsp.3005266093 |
| Directory | /workspace/19.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/19.xbar_error_and_unmapped_addr.2306922165 |
| Short name | T2875 |
| Test name | |
| Test status | |
| Simulation time | 86842728 ps |
| CPU time | 11.93 seconds |
| Started | Jun 28 08:37:07 PM PDT 24 |
| Finished | Jun 28 08:37:31 PM PDT 24 |
| Peak memory | 574188 kb |
| Host | smart-c610800b-86a7-42f9-9367-2514556dd4f6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2306922165 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.xbar_error_and_unmapped_add r.2306922165 |
| Directory | /workspace/19.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/19.xbar_error_random.667298761 |
| Short name | T2597 |
| Test name | |
| Test status | |
| Simulation time | 853390965 ps |
| CPU time | 33.28 seconds |
| Started | Jun 28 08:37:05 PM PDT 24 |
| Finished | Jun 28 08:37:52 PM PDT 24 |
| Peak memory | 573864 kb |
| Host | smart-9b785d81-5c72-4d09-9783-6b4ac115885a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=667298761 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.xbar_error_random.667298761 |
| Directory | /workspace/19.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/19.xbar_random.3960077749 |
| Short name | T522 |
| Test name | |
| Test status | |
| Simulation time | 246809061 ps |
| CPU time | 26.82 seconds |
| Started | Jun 28 08:37:03 PM PDT 24 |
| Finished | Jun 28 08:37:45 PM PDT 24 |
| Peak memory | 575260 kb |
| Host | smart-5fef492b-749c-46d1-94a4-daffbb1a9b04 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3960077749 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.xbar_random.3960077749 |
| Directory | /workspace/19.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/19.xbar_random_large_delays.1883943186 |
| Short name | T1791 |
| Test name | |
| Test status | |
| Simulation time | 114234718761 ps |
| CPU time | 1162.76 seconds |
| Started | Jun 28 08:37:05 PM PDT 24 |
| Finished | Jun 28 08:56:42 PM PDT 24 |
| Peak memory | 575332 kb |
| Host | smart-4f1a54df-a27f-4de4-ab35-a7a8a8180a8e |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1883943186 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.xbar_random_large_delays.1883943186 |
| Directory | /workspace/19.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/19.xbar_random_slow_rsp.869906142 |
| Short name | T2702 |
| Test name | |
| Test status | |
| Simulation time | 63754413037 ps |
| CPU time | 1199.77 seconds |
| Started | Jun 28 08:37:08 PM PDT 24 |
| Finished | Jun 28 08:57:19 PM PDT 24 |
| Peak memory | 575332 kb |
| Host | smart-066d3192-931b-42b1-b792-7be0fc05fb08 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=869906142 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.xbar_random_slow_rsp.869906142 |
| Directory | /workspace/19.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/19.xbar_random_zero_delays.1928930609 |
| Short name | T2384 |
| Test name | |
| Test status | |
| Simulation time | 114444799 ps |
| CPU time | 13.18 seconds |
| Started | Jun 28 08:37:09 PM PDT 24 |
| Finished | Jun 28 08:37:33 PM PDT 24 |
| Peak memory | 574164 kb |
| Host | smart-b3741b2e-ec8c-434c-b971-7b4212046d69 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1928930609 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.xbar_random_zero_del ays.1928930609 |
| Directory | /workspace/19.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/19.xbar_same_source.826553835 |
| Short name | T1746 |
| Test name | |
| Test status | |
| Simulation time | 1081823647 ps |
| CPU time | 36.19 seconds |
| Started | Jun 28 08:37:05 PM PDT 24 |
| Finished | Jun 28 08:37:55 PM PDT 24 |
| Peak memory | 575208 kb |
| Host | smart-df7f79c7-971f-4195-8748-da64d57002ee |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=826553835 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.xbar_same_source.826553835 |
| Directory | /workspace/19.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/19.xbar_smoke.3591777778 |
| Short name | T2569 |
| Test name | |
| Test status | |
| Simulation time | 202630566 ps |
| CPU time | 9.32 seconds |
| Started | Jun 28 08:37:06 PM PDT 24 |
| Finished | Jun 28 08:37:28 PM PDT 24 |
| Peak memory | 574156 kb |
| Host | smart-abf04b0e-353a-4e2c-a5dc-6d32c3287e38 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3591777778 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.xbar_smoke.3591777778 |
| Directory | /workspace/19.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/19.xbar_smoke_large_delays.2331302018 |
| Short name | T1668 |
| Test name | |
| Test status | |
| Simulation time | 7771109678 ps |
| CPU time | 80.03 seconds |
| Started | Jun 28 08:37:12 PM PDT 24 |
| Finished | Jun 28 08:38:42 PM PDT 24 |
| Peak memory | 574268 kb |
| Host | smart-354a2657-b55a-461d-bc34-e01ab55ee4ac |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2331302018 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.xbar_smoke_large_delays.2331302018 |
| Directory | /workspace/19.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/19.xbar_smoke_slow_rsp.2086871500 |
| Short name | T1355 |
| Test name | |
| Test status | |
| Simulation time | 4364737179 ps |
| CPU time | 74.62 seconds |
| Started | Jun 28 08:37:05 PM PDT 24 |
| Finished | Jun 28 08:38:34 PM PDT 24 |
| Peak memory | 566016 kb |
| Host | smart-bbd3d832-6d9b-4bcb-9fff-103d785f5f88 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2086871500 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.xbar_smoke_slow_rsp.2086871500 |
| Directory | /workspace/19.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/19.xbar_smoke_zero_delays.682393370 |
| Short name | T2519 |
| Test name | |
| Test status | |
| Simulation time | 49820235 ps |
| CPU time | 7.19 seconds |
| Started | Jun 28 08:37:08 PM PDT 24 |
| Finished | Jun 28 08:37:27 PM PDT 24 |
| Peak memory | 565868 kb |
| Host | smart-819c4882-176e-4bab-a373-a1f2a7065d3c |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=682393370 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.xbar_smoke_zero_delays .682393370 |
| Directory | /workspace/19.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/19.xbar_stress_all.652889279 |
| Short name | T1608 |
| Test name | |
| Test status | |
| Simulation time | 18469275300 ps |
| CPU time | 706.8 seconds |
| Started | Jun 28 08:37:03 PM PDT 24 |
| Finished | Jun 28 08:49:05 PM PDT 24 |
| Peak memory | 574396 kb |
| Host | smart-a882eadf-05ae-442b-ad33-195b62deb9aa |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=652889279 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.xbar_stress_all.652889279 |
| Directory | /workspace/19.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/19.xbar_stress_all_with_error.1441080675 |
| Short name | T2128 |
| Test name | |
| Test status | |
| Simulation time | 1534464854 ps |
| CPU time | 112.04 seconds |
| Started | Jun 28 08:37:12 PM PDT 24 |
| Finished | Jun 28 08:39:14 PM PDT 24 |
| Peak memory | 574312 kb |
| Host | smart-53fc3893-434b-4732-80fd-5fbdc8e4603a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1441080675 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.xbar_stress_all_with_error.1441080675 |
| Directory | /workspace/19.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/19.xbar_stress_all_with_rand_reset.2626410483 |
| Short name | T2587 |
| Test name | |
| Test status | |
| Simulation time | 2586645827 ps |
| CPU time | 523.02 seconds |
| Started | Jun 28 08:37:07 PM PDT 24 |
| Finished | Jun 28 08:46:02 PM PDT 24 |
| Peak memory | 575428 kb |
| Host | smart-346faf14-3935-4b39-a142-22c7bdb519c4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2626410483 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.xbar_stress_all _with_rand_reset.2626410483 |
| Directory | /workspace/19.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/19.xbar_stress_all_with_reset_error.3607429407 |
| Short name | T2469 |
| Test name | |
| Test status | |
| Simulation time | 2231119044 ps |
| CPU time | 234.38 seconds |
| Started | Jun 28 08:37:08 PM PDT 24 |
| Finished | Jun 28 08:41:14 PM PDT 24 |
| Peak memory | 574580 kb |
| Host | smart-23e7b086-002a-49e7-8230-a91e4a0495c2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3607429407 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.xbar_stress_al l_with_reset_error.3607429407 |
| Directory | /workspace/19.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/19.xbar_unmapped_addr.2270499254 |
| Short name | T477 |
| Test name | |
| Test status | |
| Simulation time | 853878868 ps |
| CPU time | 38.12 seconds |
| Started | Jun 28 08:37:05 PM PDT 24 |
| Finished | Jun 28 08:37:57 PM PDT 24 |
| Peak memory | 575300 kb |
| Host | smart-b494e658-9bb0-482b-b2c4-a1f376478666 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2270499254 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.xbar_unmapped_addr.2270499254 |
| Directory | /workspace/19.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/2.chip_csr_aliasing.3547114279 |
| Short name | T379 |
| Test name | |
| Test status | |
| Simulation time | 34626191784 ps |
| CPU time | 4819.81 seconds |
| Started | Jun 28 08:28:45 PM PDT 24 |
| Finished | Jun 28 09:49:25 PM PDT 24 |
| Peak memory | 592532 kb |
| Host | smart-a46b3479-150f-47b7-a17c-87a1c3ec7278 |
| User | root |
| Command | /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +csr_aliasing +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3547114279 -assert nopostproc +UVM_TESTNAME=chip_ base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/ null -cm_name 2.chip_csr_aliasing.3547114279 |
| Directory | /workspace/2.chip_csr_aliasing/latest |
| Test location | /workspace/coverage/cover_reg_top/2.chip_csr_bit_bash.847762926 |
| Short name | T374 |
| Test name | |
| Test status | |
| Simulation time | 59032274557 ps |
| CPU time | 5760.8 seconds |
| Started | Jun 28 08:28:37 PM PDT 24 |
| Finished | Jun 28 10:04:50 PM PDT 24 |
| Peak memory | 589156 kb |
| Host | smart-26ce9184-dcdc-4481-ba53-764a4aea0b9d |
| User | root |
| Command | /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +num_test_csrs=200 +csr_bit_bash +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=847762926 -assert nopostproc + UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top .vdb -cm_log /dev/null -cm_name 2.chip_csr_bit_bash.847762926 |
| Directory | /workspace/2.chip_csr_bit_bash/latest |
| Test location | /workspace/coverage/cover_reg_top/2.chip_csr_rw.3536760527 |
| Short name | T1848 |
| Test name | |
| Test status | |
| Simulation time | 5718410970 ps |
| CPU time | 596.97 seconds |
| Started | Jun 28 08:29:35 PM PDT 24 |
| Finished | Jun 28 08:39:41 PM PDT 24 |
| Peak memory | 597648 kb |
| Host | smart-f0a1167e-e586-4eda-9b98-e56269503bfd |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3536760527 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.chip_csr_rw.3536760527 |
| Directory | /workspace/2.chip_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/2.chip_prim_tl_access.2105565092 |
| Short name | T2738 |
| Test name | |
| Test status | |
| Simulation time | 11499751786 ps |
| CPU time | 473.8 seconds |
| Started | Jun 28 08:28:45 PM PDT 24 |
| Finished | Jun 28 08:36:59 PM PDT 24 |
| Peak memory | 589256 kb |
| Host | smart-36a4a345-1b90-4690-9d9f-30d8c20692a3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +en_scb=0 +en_scb_tl_err_chk=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2105565092 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SE Q=chip_prim_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.chip_prim_tl_access.2105565092 |
| Directory | /workspace/2.chip_prim_tl_access/latest |
| Test location | /workspace/coverage/cover_reg_top/2.chip_rv_dm_lc_disabled.4240113463 |
| Short name | T2885 |
| Test name | |
| Test status | |
| Simulation time | 15938012613 ps |
| CPU time | 577.19 seconds |
| Started | Jun 28 08:28:38 PM PDT 24 |
| Finished | Jun 28 08:38:29 PM PDT 24 |
| Peak memory | 589004 kb |
| Host | smart-67f7030f-e409-4b15-a8fe-a82d8ce732c6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +en_scb=0 +en_scb_tl_err_chk=0 +use_jtag_dmi=1 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4240113463 -assert nopostproc +UVM_TESTNAME=chip_base_t est +UVM_TEST_SEQ=chip_rv_dm_lc_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.chip_rv_dm_lc_disabled.4240113463 |
| Directory | /workspace/2.chip_rv_dm_lc_disabled/latest |
| Test location | /workspace/coverage/cover_reg_top/2.chip_same_csr_outstanding.3532645847 |
| Short name | T436 |
| Test name | |
| Test status | |
| Simulation time | 14622479118 ps |
| CPU time | 2007.65 seconds |
| Started | Jun 28 08:28:43 PM PDT 24 |
| Finished | Jun 28 09:02:30 PM PDT 24 |
| Peak memory | 591464 kb |
| Host | smart-5b817005-1e39-4c29-a041-9975d1fc2548 |
| User | root |
| Command | /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +run_same_csr_outstanding +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3532645847 -assert nopostproc +UVM_TE STNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb - cm_log /dev/null -cm_name 2.chip_same_csr_outstanding.3532645847 |
| Directory | /workspace/2.chip_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/2.chip_tl_errors.2217220441 |
| Short name | T657 |
| Test name | |
| Test status | |
| Simulation time | 3802017910 ps |
| CPU time | 183.27 seconds |
| Started | Jun 28 08:28:43 PM PDT 24 |
| Finished | Jun 28 08:32:05 PM PDT 24 |
| Peak memory | 597440 kb |
| Host | smart-6f696752-a5fe-4933-b80f-a47f72e13973 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2217220441 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.chip_tl_errors.2217220441 |
| Directory | /workspace/2.chip_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/2.xbar_access_same_device.724990859 |
| Short name | T2203 |
| Test name | |
| Test status | |
| Simulation time | 508006119 ps |
| CPU time | 51.67 seconds |
| Started | Jun 28 08:29:09 PM PDT 24 |
| Finished | Jun 28 08:30:20 PM PDT 24 |
| Peak memory | 575244 kb |
| Host | smart-adefa8a1-f241-4048-a5de-b4410d0d865f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=724990859 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.xbar_access_same_device.724990859 |
| Directory | /workspace/2.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/2.xbar_error_and_unmapped_addr.1486407692 |
| Short name | T2749 |
| Test name | |
| Test status | |
| Simulation time | 74662433 ps |
| CPU time | 7.1 seconds |
| Started | Jun 28 08:29:48 PM PDT 24 |
| Finished | Jun 28 08:30:06 PM PDT 24 |
| Peak memory | 565628 kb |
| Host | smart-4c24a607-8b94-40cc-92d1-48baf2244d79 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1486407692 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.xbar_error_and_unmapped_addr .1486407692 |
| Directory | /workspace/2.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/2.xbar_error_random.3661071217 |
| Short name | T2288 |
| Test name | |
| Test status | |
| Simulation time | 1016299003 ps |
| CPU time | 42.57 seconds |
| Started | Jun 28 08:29:14 PM PDT 24 |
| Finished | Jun 28 08:30:12 PM PDT 24 |
| Peak memory | 573868 kb |
| Host | smart-5c134aca-13c1-4f45-a3f2-51690beb13f9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3661071217 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.xbar_error_random.3661071217 |
| Directory | /workspace/2.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/2.xbar_random.3818363555 |
| Short name | T2062 |
| Test name | |
| Test status | |
| Simulation time | 140494388 ps |
| CPU time | 8.86 seconds |
| Started | Jun 28 08:29:09 PM PDT 24 |
| Finished | Jun 28 08:29:37 PM PDT 24 |
| Peak memory | 574096 kb |
| Host | smart-a7caed18-50cd-49c5-9cbd-626fdae34794 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3818363555 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.xbar_random.3818363555 |
| Directory | /workspace/2.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/2.xbar_random_large_delays.4284619349 |
| Short name | T1581 |
| Test name | |
| Test status | |
| Simulation time | 19869412006 ps |
| CPU time | 229.06 seconds |
| Started | Jun 28 08:29:19 PM PDT 24 |
| Finished | Jun 28 08:33:20 PM PDT 24 |
| Peak memory | 574228 kb |
| Host | smart-2ed87daa-2485-4e10-8a05-7b5fc125f83d |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4284619349 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.xbar_random_large_delays.4284619349 |
| Directory | /workspace/2.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/2.xbar_random_slow_rsp.3387316647 |
| Short name | T1715 |
| Test name | |
| Test status | |
| Simulation time | 21574104484 ps |
| CPU time | 375.43 seconds |
| Started | Jun 28 08:29:10 PM PDT 24 |
| Finished | Jun 28 08:35:44 PM PDT 24 |
| Peak memory | 574264 kb |
| Host | smart-2b71614a-32a8-4aa5-9267-221cea9ab516 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3387316647 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.xbar_random_slow_rsp.3387316647 |
| Directory | /workspace/2.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/2.xbar_random_zero_delays.4211578301 |
| Short name | T1429 |
| Test name | |
| Test status | |
| Simulation time | 511227929 ps |
| CPU time | 47.53 seconds |
| Started | Jun 28 08:29:11 PM PDT 24 |
| Finished | Jun 28 08:30:16 PM PDT 24 |
| Peak memory | 575232 kb |
| Host | smart-a7ff6f7a-4e74-4d1c-ad6f-1a36368b0869 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4211578301 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.xbar_random_zero_dela ys.4211578301 |
| Directory | /workspace/2.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/2.xbar_same_source.4152504481 |
| Short name | T2476 |
| Test name | |
| Test status | |
| Simulation time | 426061499 ps |
| CPU time | 17.63 seconds |
| Started | Jun 28 08:29:10 PM PDT 24 |
| Finished | Jun 28 08:29:46 PM PDT 24 |
| Peak memory | 575220 kb |
| Host | smart-eb18bdd8-a266-4ec7-a230-f06cc3cb85ca |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4152504481 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.xbar_same_source.4152504481 |
| Directory | /workspace/2.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/2.xbar_smoke.358805443 |
| Short name | T1538 |
| Test name | |
| Test status | |
| Simulation time | 51957893 ps |
| CPU time | 6.62 seconds |
| Started | Jun 28 08:28:43 PM PDT 24 |
| Finished | Jun 28 08:29:09 PM PDT 24 |
| Peak memory | 574184 kb |
| Host | smart-532a3e8a-2f95-49f6-a821-c048c56744e7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=358805443 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.xbar_smoke.358805443 |
| Directory | /workspace/2.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/2.xbar_smoke_large_delays.1818095757 |
| Short name | T1579 |
| Test name | |
| Test status | |
| Simulation time | 10134443104 ps |
| CPU time | 122.23 seconds |
| Started | Jun 28 08:29:10 PM PDT 24 |
| Finished | Jun 28 08:31:30 PM PDT 24 |
| Peak memory | 566028 kb |
| Host | smart-7d88c047-1e52-466e-aebe-fe55e6b48c6b |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1818095757 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.xbar_smoke_large_delays.1818095757 |
| Directory | /workspace/2.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/2.xbar_smoke_slow_rsp.2158694645 |
| Short name | T2131 |
| Test name | |
| Test status | |
| Simulation time | 6687531783 ps |
| CPU time | 130.8 seconds |
| Started | Jun 28 08:29:29 PM PDT 24 |
| Finished | Jun 28 08:31:47 PM PDT 24 |
| Peak memory | 566008 kb |
| Host | smart-e5883f7a-a941-4cc0-af19-f8a953b43c0e |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2158694645 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.xbar_smoke_slow_rsp.2158694645 |
| Directory | /workspace/2.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/2.xbar_smoke_zero_delays.214188879 |
| Short name | T2334 |
| Test name | |
| Test status | |
| Simulation time | 44049444 ps |
| CPU time | 6.72 seconds |
| Started | Jun 28 08:28:42 PM PDT 24 |
| Finished | Jun 28 08:29:07 PM PDT 24 |
| Peak memory | 574176 kb |
| Host | smart-53746109-076b-40d3-b68f-4e28b430b352 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=214188879 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.xbar_smoke_zero_delays. 214188879 |
| Directory | /workspace/2.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/2.xbar_stress_all.3841267979 |
| Short name | T2459 |
| Test name | |
| Test status | |
| Simulation time | 1399053757 ps |
| CPU time | 128.87 seconds |
| Started | Jun 28 08:29:42 PM PDT 24 |
| Finished | Jun 28 08:32:01 PM PDT 24 |
| Peak memory | 575384 kb |
| Host | smart-3e3abbdf-9496-41e0-8392-fad10937d143 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3841267979 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.xbar_stress_all.3841267979 |
| Directory | /workspace/2.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/2.xbar_stress_all_with_error.4145078410 |
| Short name | T1474 |
| Test name | |
| Test status | |
| Simulation time | 4567574960 ps |
| CPU time | 177.78 seconds |
| Started | Jun 28 08:29:36 PM PDT 24 |
| Finished | Jun 28 08:32:42 PM PDT 24 |
| Peak memory | 574596 kb |
| Host | smart-f343a0ae-eb71-4abd-b072-0d5de183e466 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4145078410 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.xbar_stress_all_with_error.4145078410 |
| Directory | /workspace/2.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/2.xbar_unmapped_addr.2578015937 |
| Short name | T1743 |
| Test name | |
| Test status | |
| Simulation time | 759559571 ps |
| CPU time | 33.85 seconds |
| Started | Jun 28 08:29:37 PM PDT 24 |
| Finished | Jun 28 08:30:21 PM PDT 24 |
| Peak memory | 574232 kb |
| Host | smart-c94b363f-ac4d-4a8b-9cbe-a69b74bbdef0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2578015937 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.xbar_unmapped_addr.2578015937 |
| Directory | /workspace/2.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/20.chip_tl_errors.3784538437 |
| Short name | T661 |
| Test name | |
| Test status | |
| Simulation time | 4117643014 ps |
| CPU time | 301.43 seconds |
| Started | Jun 28 08:37:28 PM PDT 24 |
| Finished | Jun 28 08:42:38 PM PDT 24 |
| Peak memory | 603492 kb |
| Host | smart-018526a3-ad29-4057-be30-ef8b4a9cdb2e |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3784538437 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.chip_tl_errors.3784538437 |
| Directory | /workspace/20.chip_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/20.xbar_access_same_device.2829764898 |
| Short name | T2137 |
| Test name | |
| Test status | |
| Simulation time | 1231432251 ps |
| CPU time | 101.05 seconds |
| Started | Jun 28 08:37:33 PM PDT 24 |
| Finished | Jun 28 08:39:24 PM PDT 24 |
| Peak memory | 575296 kb |
| Host | smart-7bffc528-c702-44b5-95bc-404fa5683af1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2829764898 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.xbar_access_same_device .2829764898 |
| Directory | /workspace/20.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/20.xbar_access_same_device_slow_rsp.14913344 |
| Short name | T803 |
| Test name | |
| Test status | |
| Simulation time | 10668945964 ps |
| CPU time | 207.56 seconds |
| Started | Jun 28 08:37:27 PM PDT 24 |
| Finished | Jun 28 08:41:03 PM PDT 24 |
| Peak memory | 575284 kb |
| Host | smart-cc8ee6b1-d0d3-4ba4-aa56-2933dc0084ec |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14913344 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.xbar_access_same_de vice_slow_rsp.14913344 |
| Directory | /workspace/20.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/20.xbar_error_and_unmapped_addr.4187565015 |
| Short name | T2848 |
| Test name | |
| Test status | |
| Simulation time | 70627163 ps |
| CPU time | 10.82 seconds |
| Started | Jun 28 08:37:29 PM PDT 24 |
| Finished | Jun 28 08:37:49 PM PDT 24 |
| Peak memory | 573832 kb |
| Host | smart-cd3b800b-e24f-49c3-952f-bfeb27027802 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4187565015 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.xbar_error_and_unmapped_add r.4187565015 |
| Directory | /workspace/20.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/20.xbar_error_random.1383973289 |
| Short name | T2287 |
| Test name | |
| Test status | |
| Simulation time | 2253791500 ps |
| CPU time | 82.34 seconds |
| Started | Jun 28 08:37:28 PM PDT 24 |
| Finished | Jun 28 08:39:00 PM PDT 24 |
| Peak memory | 574260 kb |
| Host | smart-b070d44a-e6fd-4927-89a7-c7470b4c8d7a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1383973289 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.xbar_error_random.1383973289 |
| Directory | /workspace/20.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/20.xbar_random.915262654 |
| Short name | T1692 |
| Test name | |
| Test status | |
| Simulation time | 31830006 ps |
| CPU time | 6.21 seconds |
| Started | Jun 28 08:37:31 PM PDT 24 |
| Finished | Jun 28 08:37:47 PM PDT 24 |
| Peak memory | 565904 kb |
| Host | smart-fe40724b-8417-45d8-aeab-705bbeaf993a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=915262654 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.xbar_random.915262654 |
| Directory | /workspace/20.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/20.xbar_random_large_delays.1355119672 |
| Short name | T1980 |
| Test name | |
| Test status | |
| Simulation time | 104668582599 ps |
| CPU time | 1114.8 seconds |
| Started | Jun 28 08:37:28 PM PDT 24 |
| Finished | Jun 28 08:56:12 PM PDT 24 |
| Peak memory | 575304 kb |
| Host | smart-884392e1-a1f8-4573-8877-dd4b88e9d03b |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1355119672 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.xbar_random_large_delays.1355119672 |
| Directory | /workspace/20.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/20.xbar_random_slow_rsp.3225959924 |
| Short name | T1636 |
| Test name | |
| Test status | |
| Simulation time | 45028573569 ps |
| CPU time | 782.72 seconds |
| Started | Jun 28 08:37:29 PM PDT 24 |
| Finished | Jun 28 08:50:41 PM PDT 24 |
| Peak memory | 575328 kb |
| Host | smart-df67c1ec-9dad-470d-bb73-fa06bccda5c9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3225959924 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.xbar_random_slow_rsp.3225959924 |
| Directory | /workspace/20.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/20.xbar_random_zero_delays.900883148 |
| Short name | T2863 |
| Test name | |
| Test status | |
| Simulation time | 388794073 ps |
| CPU time | 37.98 seconds |
| Started | Jun 28 08:37:27 PM PDT 24 |
| Finished | Jun 28 08:38:13 PM PDT 24 |
| Peak memory | 574172 kb |
| Host | smart-aa513f2a-ebef-4b95-8fc8-11b08c583d1b |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=900883148 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.xbar_random_zero_dela ys.900883148 |
| Directory | /workspace/20.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/20.xbar_same_source.3217073025 |
| Short name | T1575 |
| Test name | |
| Test status | |
| Simulation time | 102938457 ps |
| CPU time | 11.59 seconds |
| Started | Jun 28 08:37:31 PM PDT 24 |
| Finished | Jun 28 08:37:52 PM PDT 24 |
| Peak memory | 574120 kb |
| Host | smart-49874618-25df-4e0b-aa74-b186f98eae78 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3217073025 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.xbar_same_source.3217073025 |
| Directory | /workspace/20.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/20.xbar_smoke.4269917738 |
| Short name | T1385 |
| Test name | |
| Test status | |
| Simulation time | 51821969 ps |
| CPU time | 6.86 seconds |
| Started | Jun 28 08:37:33 PM PDT 24 |
| Finished | Jun 28 08:37:50 PM PDT 24 |
| Peak memory | 565932 kb |
| Host | smart-0125ddd4-3e83-4fad-bdcf-13563d2d7dad |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4269917738 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.xbar_smoke.4269917738 |
| Directory | /workspace/20.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/20.xbar_smoke_large_delays.1732769696 |
| Short name | T1627 |
| Test name | |
| Test status | |
| Simulation time | 6968167286 ps |
| CPU time | 72.51 seconds |
| Started | Jun 28 08:37:28 PM PDT 24 |
| Finished | Jun 28 08:38:49 PM PDT 24 |
| Peak memory | 566016 kb |
| Host | smart-db01ed58-b372-4db7-8188-c4a4d93db7c6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1732769696 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.xbar_smoke_large_delays.1732769696 |
| Directory | /workspace/20.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/20.xbar_smoke_slow_rsp.937805162 |
| Short name | T2853 |
| Test name | |
| Test status | |
| Simulation time | 4683214278 ps |
| CPU time | 81.44 seconds |
| Started | Jun 28 08:37:28 PM PDT 24 |
| Finished | Jun 28 08:38:59 PM PDT 24 |
| Peak memory | 566024 kb |
| Host | smart-ff2eef12-871d-4317-9cff-147bd64d8156 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=937805162 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.xbar_smoke_slow_rsp.937805162 |
| Directory | /workspace/20.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/20.xbar_smoke_zero_delays.2461443450 |
| Short name | T1525 |
| Test name | |
| Test status | |
| Simulation time | 46708460 ps |
| CPU time | 6.1 seconds |
| Started | Jun 28 08:37:27 PM PDT 24 |
| Finished | Jun 28 08:37:41 PM PDT 24 |
| Peak memory | 574192 kb |
| Host | smart-93bfd896-4c26-4770-be77-de5a8e0b413c |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2461443450 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.xbar_smoke_zero_delay s.2461443450 |
| Directory | /workspace/20.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/20.xbar_stress_all.1777868163 |
| Short name | T2057 |
| Test name | |
| Test status | |
| Simulation time | 5025340334 ps |
| CPU time | 202.7 seconds |
| Started | Jun 28 08:37:27 PM PDT 24 |
| Finished | Jun 28 08:40:58 PM PDT 24 |
| Peak memory | 575436 kb |
| Host | smart-0ab329e5-353d-4f2e-a2a7-ce2918ef03d9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1777868163 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.xbar_stress_all.1777868163 |
| Directory | /workspace/20.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/20.xbar_stress_all_with_error.732681374 |
| Short name | T2077 |
| Test name | |
| Test status | |
| Simulation time | 1556582284 ps |
| CPU time | 129.93 seconds |
| Started | Jun 28 08:37:28 PM PDT 24 |
| Finished | Jun 28 08:39:47 PM PDT 24 |
| Peak memory | 574236 kb |
| Host | smart-c3f2907f-7bb1-4480-a1b9-6c1e05656b66 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=732681374 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.xbar_stress_all_with_error.732681374 |
| Directory | /workspace/20.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/20.xbar_stress_all_with_rand_reset.1503730047 |
| Short name | T1701 |
| Test name | |
| Test status | |
| Simulation time | 462827084 ps |
| CPU time | 164.34 seconds |
| Started | Jun 28 08:37:27 PM PDT 24 |
| Finished | Jun 28 08:40:20 PM PDT 24 |
| Peak memory | 575384 kb |
| Host | smart-b258ebae-cd15-4a97-a71f-addbe44dc43c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1503730047 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.xbar_stress_all _with_rand_reset.1503730047 |
| Directory | /workspace/20.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/20.xbar_stress_all_with_reset_error.630939435 |
| Short name | T1824 |
| Test name | |
| Test status | |
| Simulation time | 3506347685 ps |
| CPU time | 483.32 seconds |
| Started | Jun 28 08:37:27 PM PDT 24 |
| Finished | Jun 28 08:45:38 PM PDT 24 |
| Peak memory | 576484 kb |
| Host | smart-ed3f867a-18da-48d9-b84a-0f7ab29d357c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=630939435 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.xbar_stress_all _with_reset_error.630939435 |
| Directory | /workspace/20.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/20.xbar_unmapped_addr.2367821546 |
| Short name | T1938 |
| Test name | |
| Test status | |
| Simulation time | 312299198 ps |
| CPU time | 34.24 seconds |
| Started | Jun 28 08:37:27 PM PDT 24 |
| Finished | Jun 28 08:38:09 PM PDT 24 |
| Peak memory | 574200 kb |
| Host | smart-84666200-b0bb-400a-a33f-6df3d5aeaf96 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2367821546 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.xbar_unmapped_addr.2367821546 |
| Directory | /workspace/20.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/21.chip_tl_errors.2358336842 |
| Short name | T2253 |
| Test name | |
| Test status | |
| Simulation time | 4734093938 ps |
| CPU time | 543.28 seconds |
| Started | Jun 28 08:37:28 PM PDT 24 |
| Finished | Jun 28 08:46:41 PM PDT 24 |
| Peak memory | 603576 kb |
| Host | smart-9aee37fc-f8c0-45d8-9915-690c8e1323b5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2358336842 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.chip_tl_errors.2358336842 |
| Directory | /workspace/21.chip_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/21.xbar_access_same_device.2924276970 |
| Short name | T2881 |
| Test name | |
| Test status | |
| Simulation time | 1721710358 ps |
| CPU time | 84.05 seconds |
| Started | Jun 28 08:37:53 PM PDT 24 |
| Finished | Jun 28 08:39:19 PM PDT 24 |
| Peak memory | 575160 kb |
| Host | smart-95f121f0-69c9-4b65-87fa-e2b631178a35 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2924276970 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.xbar_access_same_device .2924276970 |
| Directory | /workspace/21.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/21.xbar_access_same_device_slow_rsp.1273422188 |
| Short name | T2664 |
| Test name | |
| Test status | |
| Simulation time | 13996101890 ps |
| CPU time | 278.24 seconds |
| Started | Jun 28 08:37:53 PM PDT 24 |
| Finished | Jun 28 08:42:34 PM PDT 24 |
| Peak memory | 575384 kb |
| Host | smart-168029af-c70d-45f1-90ad-728c4dcc2856 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1273422188 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.xbar_access_same_ device_slow_rsp.1273422188 |
| Directory | /workspace/21.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/21.xbar_error_and_unmapped_addr.1013328797 |
| Short name | T1340 |
| Test name | |
| Test status | |
| Simulation time | 55164938 ps |
| CPU time | 8.78 seconds |
| Started | Jun 28 08:37:53 PM PDT 24 |
| Finished | Jun 28 08:38:05 PM PDT 24 |
| Peak memory | 573816 kb |
| Host | smart-e6b21a33-2ce1-4ab9-815b-fdbe6c5146c4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1013328797 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.xbar_error_and_unmapped_add r.1013328797 |
| Directory | /workspace/21.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/21.xbar_error_random.2218256176 |
| Short name | T1941 |
| Test name | |
| Test status | |
| Simulation time | 1772946471 ps |
| CPU time | 68.21 seconds |
| Started | Jun 28 08:37:53 PM PDT 24 |
| Finished | Jun 28 08:39:04 PM PDT 24 |
| Peak memory | 574448 kb |
| Host | smart-cd231ed6-3dc2-457b-a980-93a7ed308c2a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2218256176 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.xbar_error_random.2218256176 |
| Directory | /workspace/21.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/21.xbar_random.656226199 |
| Short name | T456 |
| Test name | |
| Test status | |
| Simulation time | 437225401 ps |
| CPU time | 42.85 seconds |
| Started | Jun 28 08:37:54 PM PDT 24 |
| Finished | Jun 28 08:38:39 PM PDT 24 |
| Peak memory | 574196 kb |
| Host | smart-3279482b-6853-49cc-966e-1a6b3df07690 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=656226199 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.xbar_random.656226199 |
| Directory | /workspace/21.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/21.xbar_random_large_delays.1040722039 |
| Short name | T2691 |
| Test name | |
| Test status | |
| Simulation time | 65873265795 ps |
| CPU time | 661.54 seconds |
| Started | Jun 28 08:37:54 PM PDT 24 |
| Finished | Jun 28 08:48:58 PM PDT 24 |
| Peak memory | 575324 kb |
| Host | smart-499da07b-471a-4053-bfcf-fdd7d3f248fd |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1040722039 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.xbar_random_large_delays.1040722039 |
| Directory | /workspace/21.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/21.xbar_random_slow_rsp.2357454883 |
| Short name | T2484 |
| Test name | |
| Test status | |
| Simulation time | 5451387130 ps |
| CPU time | 99.61 seconds |
| Started | Jun 28 08:37:55 PM PDT 24 |
| Finished | Jun 28 08:39:38 PM PDT 24 |
| Peak memory | 574192 kb |
| Host | smart-71c60608-8652-481c-9952-386e6cb8faa4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2357454883 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.xbar_random_slow_rsp.2357454883 |
| Directory | /workspace/21.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/21.xbar_random_zero_delays.4145185976 |
| Short name | T1773 |
| Test name | |
| Test status | |
| Simulation time | 383902742 ps |
| CPU time | 35.38 seconds |
| Started | Jun 28 08:37:52 PM PDT 24 |
| Finished | Jun 28 08:38:31 PM PDT 24 |
| Peak memory | 574176 kb |
| Host | smart-539c750e-3812-42ce-b402-fbc5e6be160b |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4145185976 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.xbar_random_zero_del ays.4145185976 |
| Directory | /workspace/21.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/21.xbar_same_source.589265733 |
| Short name | T2467 |
| Test name | |
| Test status | |
| Simulation time | 83715793 ps |
| CPU time | 9.57 seconds |
| Started | Jun 28 08:37:55 PM PDT 24 |
| Finished | Jun 28 08:38:07 PM PDT 24 |
| Peak memory | 575228 kb |
| Host | smart-54a1e26c-bcfd-4cae-892c-1c066f7f54a8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=589265733 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.xbar_same_source.589265733 |
| Directory | /workspace/21.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/21.xbar_smoke.3481746331 |
| Short name | T2177 |
| Test name | |
| Test status | |
| Simulation time | 171315193 ps |
| CPU time | 9.11 seconds |
| Started | Jun 28 08:37:28 PM PDT 24 |
| Finished | Jun 28 08:37:46 PM PDT 24 |
| Peak memory | 574192 kb |
| Host | smart-c7dc3710-f90c-42cb-8730-a0d1973a4292 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3481746331 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.xbar_smoke.3481746331 |
| Directory | /workspace/21.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/21.xbar_smoke_large_delays.731167336 |
| Short name | T1565 |
| Test name | |
| Test status | |
| Simulation time | 7670507006 ps |
| CPU time | 85.47 seconds |
| Started | Jun 28 08:37:54 PM PDT 24 |
| Finished | Jun 28 08:39:23 PM PDT 24 |
| Peak memory | 574268 kb |
| Host | smart-e6d7efc0-843c-4038-8463-e50d6563b76d |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=731167336 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.xbar_smoke_large_delays.731167336 |
| Directory | /workspace/21.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/21.xbar_smoke_slow_rsp.1232916572 |
| Short name | T1937 |
| Test name | |
| Test status | |
| Simulation time | 6321732741 ps |
| CPU time | 112.39 seconds |
| Started | Jun 28 08:37:52 PM PDT 24 |
| Finished | Jun 28 08:39:48 PM PDT 24 |
| Peak memory | 574252 kb |
| Host | smart-5e27612a-5351-4630-a1ff-f783b2acdb42 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1232916572 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.xbar_smoke_slow_rsp.1232916572 |
| Directory | /workspace/21.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/21.xbar_smoke_zero_delays.2764508507 |
| Short name | T2463 |
| Test name | |
| Test status | |
| Simulation time | 54716353 ps |
| CPU time | 7.34 seconds |
| Started | Jun 28 08:37:54 PM PDT 24 |
| Finished | Jun 28 08:38:04 PM PDT 24 |
| Peak memory | 574184 kb |
| Host | smart-2948ef57-f54f-4ba9-ae2f-b2a467f19d45 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2764508507 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.xbar_smoke_zero_delay s.2764508507 |
| Directory | /workspace/21.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/21.xbar_stress_all.2529352160 |
| Short name | T1679 |
| Test name | |
| Test status | |
| Simulation time | 2398076285 ps |
| CPU time | 108.77 seconds |
| Started | Jun 28 08:37:56 PM PDT 24 |
| Finished | Jun 28 08:39:47 PM PDT 24 |
| Peak memory | 574392 kb |
| Host | smart-636cc480-1207-4d18-b1de-d1e8bab5aac1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2529352160 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.xbar_stress_all.2529352160 |
| Directory | /workspace/21.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/21.xbar_stress_all_with_error.2462980918 |
| Short name | T1719 |
| Test name | |
| Test status | |
| Simulation time | 4703496664 ps |
| CPU time | 167.43 seconds |
| Started | Jun 28 08:37:56 PM PDT 24 |
| Finished | Jun 28 08:40:46 PM PDT 24 |
| Peak memory | 574376 kb |
| Host | smart-3034d443-c27e-4ad4-b00b-426a86b0cf98 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2462980918 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.xbar_stress_all_with_error.2462980918 |
| Directory | /workspace/21.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/21.xbar_stress_all_with_rand_reset.1350390436 |
| Short name | T2102 |
| Test name | |
| Test status | |
| Simulation time | 882490615 ps |
| CPU time | 167.49 seconds |
| Started | Jun 28 08:37:53 PM PDT 24 |
| Finished | Jun 28 08:40:43 PM PDT 24 |
| Peak memory | 575372 kb |
| Host | smart-1a7ed95f-938b-4d9b-b318-22dfb4e6fb8d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1350390436 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.xbar_stress_all _with_rand_reset.1350390436 |
| Directory | /workspace/21.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/21.xbar_stress_all_with_reset_error.303361325 |
| Short name | T1874 |
| Test name | |
| Test status | |
| Simulation time | 224334323 ps |
| CPU time | 109.15 seconds |
| Started | Jun 28 08:37:53 PM PDT 24 |
| Finished | Jun 28 08:39:46 PM PDT 24 |
| Peak memory | 574616 kb |
| Host | smart-43777e5a-f191-4544-8144-93a87e4a1259 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=303361325 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.xbar_stress_all _with_reset_error.303361325 |
| Directory | /workspace/21.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/21.xbar_unmapped_addr.1112583645 |
| Short name | T1402 |
| Test name | |
| Test status | |
| Simulation time | 937569766 ps |
| CPU time | 45.24 seconds |
| Started | Jun 28 08:37:54 PM PDT 24 |
| Finished | Jun 28 08:38:42 PM PDT 24 |
| Peak memory | 575328 kb |
| Host | smart-601c56e1-6f9d-4383-b732-32d685d73c86 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1112583645 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.xbar_unmapped_addr.1112583645 |
| Directory | /workspace/21.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/22.chip_tl_errors.999524797 |
| Short name | T2743 |
| Test name | |
| Test status | |
| Simulation time | 3077443128 ps |
| CPU time | 265.48 seconds |
| Started | Jun 28 08:37:53 PM PDT 24 |
| Finished | Jun 28 08:42:22 PM PDT 24 |
| Peak memory | 597412 kb |
| Host | smart-1365e077-0c96-4ab0-81c1-cfb6093e6c43 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=999524797 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.chip_tl_errors.999524797 |
| Directory | /workspace/22.chip_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/22.xbar_access_same_device.4204267232 |
| Short name | T2404 |
| Test name | |
| Test status | |
| Simulation time | 3368328651 ps |
| CPU time | 145.82 seconds |
| Started | Jun 28 08:37:53 PM PDT 24 |
| Finished | Jun 28 08:40:22 PM PDT 24 |
| Peak memory | 575284 kb |
| Host | smart-019e2458-ab80-4499-8036-598bcb398d8a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4204267232 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.xbar_access_same_device .4204267232 |
| Directory | /workspace/22.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/22.xbar_access_same_device_slow_rsp.3582942310 |
| Short name | T797 |
| Test name | |
| Test status | |
| Simulation time | 63427934807 ps |
| CPU time | 1086.17 seconds |
| Started | Jun 28 08:37:54 PM PDT 24 |
| Finished | Jun 28 08:56:03 PM PDT 24 |
| Peak memory | 575384 kb |
| Host | smart-2792b716-94e9-427b-9a7b-2e268710c227 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3582942310 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.xbar_access_same_ device_slow_rsp.3582942310 |
| Directory | /workspace/22.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/22.xbar_error_and_unmapped_addr.1565464801 |
| Short name | T2315 |
| Test name | |
| Test status | |
| Simulation time | 202987165 ps |
| CPU time | 28.76 seconds |
| Started | Jun 28 08:38:23 PM PDT 24 |
| Finished | Jun 28 08:39:02 PM PDT 24 |
| Peak memory | 574112 kb |
| Host | smart-ac22ad5b-ef42-4311-8f85-54b6cd8415cd |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1565464801 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.xbar_error_and_unmapped_add r.1565464801 |
| Directory | /workspace/22.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/22.xbar_error_random.2635130312 |
| Short name | T1477 |
| Test name | |
| Test status | |
| Simulation time | 876651307 ps |
| CPU time | 30.4 seconds |
| Started | Jun 28 08:38:33 PM PDT 24 |
| Finished | Jun 28 08:39:08 PM PDT 24 |
| Peak memory | 574432 kb |
| Host | smart-f49b9903-77e6-428a-ad4c-32f82d9711b2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2635130312 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.xbar_error_random.2635130312 |
| Directory | /workspace/22.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/22.xbar_random.2856552702 |
| Short name | T2525 |
| Test name | |
| Test status | |
| Simulation time | 1847166251 ps |
| CPU time | 69.67 seconds |
| Started | Jun 28 08:37:55 PM PDT 24 |
| Finished | Jun 28 08:39:08 PM PDT 24 |
| Peak memory | 574176 kb |
| Host | smart-13d97f6c-c06f-4430-8858-da17b6df5ec8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2856552702 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.xbar_random.2856552702 |
| Directory | /workspace/22.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/22.xbar_random_large_delays.159500333 |
| Short name | T2723 |
| Test name | |
| Test status | |
| Simulation time | 81815688825 ps |
| CPU time | 889.64 seconds |
| Started | Jun 28 08:37:52 PM PDT 24 |
| Finished | Jun 28 08:52:45 PM PDT 24 |
| Peak memory | 575320 kb |
| Host | smart-9ba40113-3688-454d-a1e6-d808ddacbc54 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=159500333 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.xbar_random_large_delays.159500333 |
| Directory | /workspace/22.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/22.xbar_random_slow_rsp.37309765 |
| Short name | T2554 |
| Test name | |
| Test status | |
| Simulation time | 7489162786 ps |
| CPU time | 130.27 seconds |
| Started | Jun 28 08:37:54 PM PDT 24 |
| Finished | Jun 28 08:40:08 PM PDT 24 |
| Peak memory | 575304 kb |
| Host | smart-23780482-c057-4d9c-b61b-e106cf0f2062 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37309765 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.xbar_random_slow_rsp.37309765 |
| Directory | /workspace/22.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/22.xbar_random_zero_delays.4079297397 |
| Short name | T2534 |
| Test name | |
| Test status | |
| Simulation time | 156503036 ps |
| CPU time | 18.09 seconds |
| Started | Jun 28 08:37:54 PM PDT 24 |
| Finished | Jun 28 08:38:15 PM PDT 24 |
| Peak memory | 575212 kb |
| Host | smart-decaba99-da7c-46a9-9e81-680b5f6c946f |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4079297397 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.xbar_random_zero_del ays.4079297397 |
| Directory | /workspace/22.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/22.xbar_same_source.2212405133 |
| Short name | T2286 |
| Test name | |
| Test status | |
| Simulation time | 123515033 ps |
| CPU time | 12.35 seconds |
| Started | Jun 28 08:38:20 PM PDT 24 |
| Finished | Jun 28 08:38:44 PM PDT 24 |
| Peak memory | 575244 kb |
| Host | smart-a97da38c-0ef4-4ae4-ac3e-db0549a9069f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2212405133 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.xbar_same_source.2212405133 |
| Directory | /workspace/22.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/22.xbar_smoke.3218792141 |
| Short name | T1337 |
| Test name | |
| Test status | |
| Simulation time | 148813920 ps |
| CPU time | 8.87 seconds |
| Started | Jun 28 08:37:53 PM PDT 24 |
| Finished | Jun 28 08:38:05 PM PDT 24 |
| Peak memory | 574068 kb |
| Host | smart-03ce3d86-baa3-4495-983c-cdfb50342712 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3218792141 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.xbar_smoke.3218792141 |
| Directory | /workspace/22.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/22.xbar_smoke_large_delays.319168739 |
| Short name | T1623 |
| Test name | |
| Test status | |
| Simulation time | 6165266915 ps |
| CPU time | 67.16 seconds |
| Started | Jun 28 08:37:52 PM PDT 24 |
| Finished | Jun 28 08:39:02 PM PDT 24 |
| Peak memory | 574076 kb |
| Host | smart-7f4d77b2-78dd-42e2-ad8e-a37a39c59889 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=319168739 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.xbar_smoke_large_delays.319168739 |
| Directory | /workspace/22.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/22.xbar_smoke_slow_rsp.3929363098 |
| Short name | T2708 |
| Test name | |
| Test status | |
| Simulation time | 4617436156 ps |
| CPU time | 82.26 seconds |
| Started | Jun 28 08:37:55 PM PDT 24 |
| Finished | Jun 28 08:39:20 PM PDT 24 |
| Peak memory | 566036 kb |
| Host | smart-2f758d2c-f4b9-4631-8d88-3c7bcd2d6a29 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3929363098 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.xbar_smoke_slow_rsp.3929363098 |
| Directory | /workspace/22.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/22.xbar_smoke_zero_delays.1237251189 |
| Short name | T1894 |
| Test name | |
| Test status | |
| Simulation time | 49879457 ps |
| CPU time | 7.39 seconds |
| Started | Jun 28 08:37:56 PM PDT 24 |
| Finished | Jun 28 08:38:06 PM PDT 24 |
| Peak memory | 574180 kb |
| Host | smart-4630d484-a3af-4e27-a05f-1c772bfd5700 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1237251189 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.xbar_smoke_zero_delay s.1237251189 |
| Directory | /workspace/22.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/22.xbar_stress_all.891689338 |
| Short name | T2214 |
| Test name | |
| Test status | |
| Simulation time | 10091702550 ps |
| CPU time | 411.86 seconds |
| Started | Jun 28 08:38:21 PM PDT 24 |
| Finished | Jun 28 08:45:24 PM PDT 24 |
| Peak memory | 575464 kb |
| Host | smart-11e4cc0d-7ae8-47a9-a7ef-34ecd6dbadaa |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=891689338 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.xbar_stress_all.891689338 |
| Directory | /workspace/22.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/22.xbar_stress_all_with_error.4014397384 |
| Short name | T2436 |
| Test name | |
| Test status | |
| Simulation time | 4599403239 ps |
| CPU time | 187.76 seconds |
| Started | Jun 28 08:38:22 PM PDT 24 |
| Finished | Jun 28 08:41:40 PM PDT 24 |
| Peak memory | 574588 kb |
| Host | smart-f605ce26-3d15-4f74-bc80-6f2e2294efd1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4014397384 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.xbar_stress_all_with_error.4014397384 |
| Directory | /workspace/22.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/22.xbar_stress_all_with_reset_error.2485867023 |
| Short name | T837 |
| Test name | |
| Test status | |
| Simulation time | 455321876 ps |
| CPU time | 144.57 seconds |
| Started | Jun 28 08:38:22 PM PDT 24 |
| Finished | Jun 28 08:40:57 PM PDT 24 |
| Peak memory | 574372 kb |
| Host | smart-f8f1f595-e2ec-4dbe-a15a-9a6a1d88e6ea |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2485867023 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.xbar_stress_al l_with_reset_error.2485867023 |
| Directory | /workspace/22.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/22.xbar_unmapped_addr.3336590120 |
| Short name | T2563 |
| Test name | |
| Test status | |
| Simulation time | 232213635 ps |
| CPU time | 13.69 seconds |
| Started | Jun 28 08:38:22 PM PDT 24 |
| Finished | Jun 28 08:38:46 PM PDT 24 |
| Peak memory | 574420 kb |
| Host | smart-bdabbf4f-d918-438e-8f59-4b60481751df |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3336590120 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.xbar_unmapped_addr.3336590120 |
| Directory | /workspace/22.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/23.xbar_access_same_device.4057124811 |
| Short name | T2391 |
| Test name | |
| Test status | |
| Simulation time | 332130238 ps |
| CPU time | 33.91 seconds |
| Started | Jun 28 08:38:20 PM PDT 24 |
| Finished | Jun 28 08:39:05 PM PDT 24 |
| Peak memory | 575236 kb |
| Host | smart-7687d5f4-0518-44b4-a74f-0859bb326626 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4057124811 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.xbar_access_same_device .4057124811 |
| Directory | /workspace/23.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/23.xbar_access_same_device_slow_rsp.652805419 |
| Short name | T2517 |
| Test name | |
| Test status | |
| Simulation time | 127487028834 ps |
| CPU time | 2235.69 seconds |
| Started | Jun 28 08:38:22 PM PDT 24 |
| Finished | Jun 28 09:15:48 PM PDT 24 |
| Peak memory | 574304 kb |
| Host | smart-f930eb43-4f67-4075-94fa-7b61efddb371 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=652805419 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.xbar_access_same_d evice_slow_rsp.652805419 |
| Directory | /workspace/23.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/23.xbar_error_and_unmapped_addr.1439798604 |
| Short name | T2755 |
| Test name | |
| Test status | |
| Simulation time | 226968269 ps |
| CPU time | 24.39 seconds |
| Started | Jun 28 08:38:28 PM PDT 24 |
| Finished | Jun 28 08:39:01 PM PDT 24 |
| Peak memory | 574420 kb |
| Host | smart-b67d571d-032a-4489-af93-749e864712cf |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1439798604 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.xbar_error_and_unmapped_add r.1439798604 |
| Directory | /workspace/23.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/23.xbar_error_random.480907322 |
| Short name | T1684 |
| Test name | |
| Test status | |
| Simulation time | 566439520 ps |
| CPU time | 49.02 seconds |
| Started | Jun 28 08:38:22 PM PDT 24 |
| Finished | Jun 28 08:39:22 PM PDT 24 |
| Peak memory | 573880 kb |
| Host | smart-8b0b4c17-d99d-4798-90f3-c57dcaafdafa |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=480907322 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.xbar_error_random.480907322 |
| Directory | /workspace/23.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/23.xbar_random.1090830817 |
| Short name | T625 |
| Test name | |
| Test status | |
| Simulation time | 1860463518 ps |
| CPU time | 74.61 seconds |
| Started | Jun 28 08:38:26 PM PDT 24 |
| Finished | Jun 28 08:39:50 PM PDT 24 |
| Peak memory | 575236 kb |
| Host | smart-c847c90c-c492-4887-9ca5-b18e3d86229a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1090830817 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.xbar_random.1090830817 |
| Directory | /workspace/23.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/23.xbar_random_large_delays.1386124064 |
| Short name | T2714 |
| Test name | |
| Test status | |
| Simulation time | 29414186214 ps |
| CPU time | 317.52 seconds |
| Started | Jun 28 08:38:23 PM PDT 24 |
| Finished | Jun 28 08:43:51 PM PDT 24 |
| Peak memory | 575228 kb |
| Host | smart-ac09f417-c4b5-47c9-9101-06bb00c813d4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1386124064 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.xbar_random_large_delays.1386124064 |
| Directory | /workspace/23.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/23.xbar_random_slow_rsp.803207825 |
| Short name | T2069 |
| Test name | |
| Test status | |
| Simulation time | 18356118758 ps |
| CPU time | 308.39 seconds |
| Started | Jun 28 08:38:23 PM PDT 24 |
| Finished | Jun 28 08:43:42 PM PDT 24 |
| Peak memory | 574240 kb |
| Host | smart-645efae2-891b-4f95-bc5e-5bcf8d1e6316 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=803207825 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.xbar_random_slow_rsp.803207825 |
| Directory | /workspace/23.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/23.xbar_random_zero_delays.2216612464 |
| Short name | T584 |
| Test name | |
| Test status | |
| Simulation time | 144189637 ps |
| CPU time | 15.73 seconds |
| Started | Jun 28 08:38:23 PM PDT 24 |
| Finished | Jun 28 08:38:49 PM PDT 24 |
| Peak memory | 575244 kb |
| Host | smart-235c4e02-5d0b-4c53-9c5e-b1aabf483f33 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2216612464 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.xbar_random_zero_del ays.2216612464 |
| Directory | /workspace/23.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/23.xbar_same_source.1948032117 |
| Short name | T674 |
| Test name | |
| Test status | |
| Simulation time | 1386819721 ps |
| CPU time | 40.07 seconds |
| Started | Jun 28 08:38:20 PM PDT 24 |
| Finished | Jun 28 08:39:12 PM PDT 24 |
| Peak memory | 575112 kb |
| Host | smart-f230aae2-9186-4ca0-a896-b912f34518a6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1948032117 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.xbar_same_source.1948032117 |
| Directory | /workspace/23.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/23.xbar_smoke.1187432554 |
| Short name | T1367 |
| Test name | |
| Test status | |
| Simulation time | 49704108 ps |
| CPU time | 7.17 seconds |
| Started | Jun 28 08:38:21 PM PDT 24 |
| Finished | Jun 28 08:38:39 PM PDT 24 |
| Peak memory | 565892 kb |
| Host | smart-25fdb807-fa37-4021-a12d-879fa7e867e5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1187432554 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.xbar_smoke.1187432554 |
| Directory | /workspace/23.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/23.xbar_smoke_large_delays.818897897 |
| Short name | T1688 |
| Test name | |
| Test status | |
| Simulation time | 7346181443 ps |
| CPU time | 74.75 seconds |
| Started | Jun 28 08:38:28 PM PDT 24 |
| Finished | Jun 28 08:39:51 PM PDT 24 |
| Peak memory | 565976 kb |
| Host | smart-368390e2-6d98-45d5-af95-98a2c1587197 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=818897897 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.xbar_smoke_large_delays.818897897 |
| Directory | /workspace/23.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/23.xbar_smoke_slow_rsp.1650749917 |
| Short name | T1549 |
| Test name | |
| Test status | |
| Simulation time | 4957580968 ps |
| CPU time | 86.06 seconds |
| Started | Jun 28 08:38:22 PM PDT 24 |
| Finished | Jun 28 08:39:59 PM PDT 24 |
| Peak memory | 574256 kb |
| Host | smart-da3d2088-63a3-4c18-8278-4e92a6dde578 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1650749917 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.xbar_smoke_slow_rsp.1650749917 |
| Directory | /workspace/23.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/23.xbar_smoke_zero_delays.3977070506 |
| Short name | T1545 |
| Test name | |
| Test status | |
| Simulation time | 48012528 ps |
| CPU time | 7.15 seconds |
| Started | Jun 28 08:38:21 PM PDT 24 |
| Finished | Jun 28 08:38:39 PM PDT 24 |
| Peak memory | 565952 kb |
| Host | smart-13372515-82e2-459c-a1a7-474533ecc68d |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3977070506 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.xbar_smoke_zero_delay s.3977070506 |
| Directory | /workspace/23.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/23.xbar_stress_all.3204680873 |
| Short name | T2035 |
| Test name | |
| Test status | |
| Simulation time | 15759338783 ps |
| CPU time | 623.25 seconds |
| Started | Jun 28 08:38:21 PM PDT 24 |
| Finished | Jun 28 08:48:55 PM PDT 24 |
| Peak memory | 575436 kb |
| Host | smart-16e29198-d19c-4626-9205-6744f9f6a37b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3204680873 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.xbar_stress_all.3204680873 |
| Directory | /workspace/23.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/23.xbar_stress_all_with_error.2488371913 |
| Short name | T1404 |
| Test name | |
| Test status | |
| Simulation time | 10447216158 ps |
| CPU time | 377.39 seconds |
| Started | Jun 28 08:38:21 PM PDT 24 |
| Finished | Jun 28 08:44:49 PM PDT 24 |
| Peak memory | 574576 kb |
| Host | smart-f813e14b-5120-422b-809a-2428231bc4f7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2488371913 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.xbar_stress_all_with_error.2488371913 |
| Directory | /workspace/23.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/23.xbar_stress_all_with_rand_reset.1543987642 |
| Short name | T1857 |
| Test name | |
| Test status | |
| Simulation time | 221415160 ps |
| CPU time | 84.25 seconds |
| Started | Jun 28 08:38:34 PM PDT 24 |
| Finished | Jun 28 08:40:02 PM PDT 24 |
| Peak memory | 575344 kb |
| Host | smart-dfa8b147-86d7-4f62-ac71-643f852e3e97 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1543987642 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.xbar_stress_all _with_rand_reset.1543987642 |
| Directory | /workspace/23.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/23.xbar_stress_all_with_reset_error.873399765 |
| Short name | T840 |
| Test name | |
| Test status | |
| Simulation time | 2915662341 ps |
| CPU time | 246.72 seconds |
| Started | Jun 28 08:38:32 PM PDT 24 |
| Finished | Jun 28 08:42:44 PM PDT 24 |
| Peak memory | 577476 kb |
| Host | smart-fee29f3c-2a09-4d63-bb11-00d4de00b514 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=873399765 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.xbar_stress_all _with_reset_error.873399765 |
| Directory | /workspace/23.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/23.xbar_unmapped_addr.3880588463 |
| Short name | T1925 |
| Test name | |
| Test status | |
| Simulation time | 346257371 ps |
| CPU time | 16.41 seconds |
| Started | Jun 28 08:38:34 PM PDT 24 |
| Finished | Jun 28 08:38:54 PM PDT 24 |
| Peak memory | 574176 kb |
| Host | smart-85f97c4b-3577-4bb4-b79a-0b5d664fa789 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3880588463 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.xbar_unmapped_addr.3880588463 |
| Directory | /workspace/23.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/24.chip_tl_errors.3908784746 |
| Short name | T662 |
| Test name | |
| Test status | |
| Simulation time | 3038783700 ps |
| CPU time | 154.61 seconds |
| Started | Jun 28 08:38:20 PM PDT 24 |
| Finished | Jun 28 08:41:05 PM PDT 24 |
| Peak memory | 597420 kb |
| Host | smart-9bbf8e90-be1a-474c-b59f-03a94a35188a |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3908784746 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.chip_tl_errors.3908784746 |
| Directory | /workspace/24.chip_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/24.xbar_access_same_device.3837747763 |
| Short name | T2299 |
| Test name | |
| Test status | |
| Simulation time | 975893957 ps |
| CPU time | 43.02 seconds |
| Started | Jun 28 08:38:39 PM PDT 24 |
| Finished | Jun 28 08:39:26 PM PDT 24 |
| Peak memory | 575232 kb |
| Host | smart-848aa9c9-e534-492c-8a37-7ab116eb4c81 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3837747763 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.xbar_access_same_device .3837747763 |
| Directory | /workspace/24.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/24.xbar_access_same_device_slow_rsp.490274812 |
| Short name | T782 |
| Test name | |
| Test status | |
| Simulation time | 135788522258 ps |
| CPU time | 2282.7 seconds |
| Started | Jun 28 08:38:40 PM PDT 24 |
| Finished | Jun 28 09:16:47 PM PDT 24 |
| Peak memory | 575420 kb |
| Host | smart-91fcd2f8-471c-4a06-88c3-dee88cf4ee30 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=490274812 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.xbar_access_same_d evice_slow_rsp.490274812 |
| Directory | /workspace/24.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/24.xbar_error_and_unmapped_addr.778128765 |
| Short name | T2377 |
| Test name | |
| Test status | |
| Simulation time | 75074883 ps |
| CPU time | 12.94 seconds |
| Started | Jun 28 08:38:41 PM PDT 24 |
| Finished | Jun 28 08:38:58 PM PDT 24 |
| Peak memory | 574436 kb |
| Host | smart-c6711d59-bfcd-4c9a-a2b4-e51731cded0b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=778128765 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.xbar_error_and_unmapped_addr .778128765 |
| Directory | /workspace/24.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/24.xbar_error_random.2641529754 |
| Short name | T2392 |
| Test name | |
| Test status | |
| Simulation time | 199986438 ps |
| CPU time | 20.14 seconds |
| Started | Jun 28 08:38:39 PM PDT 24 |
| Finished | Jun 28 08:39:03 PM PDT 24 |
| Peak memory | 574440 kb |
| Host | smart-67a74679-fd32-414f-8dc3-5cefbefe61b7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2641529754 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.xbar_error_random.2641529754 |
| Directory | /workspace/24.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/24.xbar_random.3728177721 |
| Short name | T2837 |
| Test name | |
| Test status | |
| Simulation time | 417766482 ps |
| CPU time | 45.09 seconds |
| Started | Jun 28 08:38:39 PM PDT 24 |
| Finished | Jun 28 08:39:28 PM PDT 24 |
| Peak memory | 575236 kb |
| Host | smart-5cf964b6-6bde-47af-a684-e52eb6a2d14d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3728177721 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.xbar_random.3728177721 |
| Directory | /workspace/24.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/24.xbar_random_large_delays.2661625179 |
| Short name | T2531 |
| Test name | |
| Test status | |
| Simulation time | 98956417455 ps |
| CPU time | 1075.95 seconds |
| Started | Jun 28 08:38:40 PM PDT 24 |
| Finished | Jun 28 08:56:40 PM PDT 24 |
| Peak memory | 574292 kb |
| Host | smart-5ae39b66-1343-42c1-b182-374698a81ffb |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2661625179 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.xbar_random_large_delays.2661625179 |
| Directory | /workspace/24.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/24.xbar_random_slow_rsp.1292520412 |
| Short name | T2744 |
| Test name | |
| Test status | |
| Simulation time | 62190344735 ps |
| CPU time | 1149.54 seconds |
| Started | Jun 28 08:38:39 PM PDT 24 |
| Finished | Jun 28 08:57:53 PM PDT 24 |
| Peak memory | 575312 kb |
| Host | smart-daa85af1-747b-4997-86c5-a22e0f058caa |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1292520412 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.xbar_random_slow_rsp.1292520412 |
| Directory | /workspace/24.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/24.xbar_random_zero_delays.3302908652 |
| Short name | T2594 |
| Test name | |
| Test status | |
| Simulation time | 196741469 ps |
| CPU time | 23.34 seconds |
| Started | Jun 28 08:38:40 PM PDT 24 |
| Finished | Jun 28 08:39:07 PM PDT 24 |
| Peak memory | 575280 kb |
| Host | smart-68a3541e-107a-4e43-af40-b6bb5f198366 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3302908652 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.xbar_random_zero_del ays.3302908652 |
| Directory | /workspace/24.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/24.xbar_same_source.3634943598 |
| Short name | T2550 |
| Test name | |
| Test status | |
| Simulation time | 1189133542 ps |
| CPU time | 41.5 seconds |
| Started | Jun 28 08:38:39 PM PDT 24 |
| Finished | Jun 28 08:39:24 PM PDT 24 |
| Peak memory | 575140 kb |
| Host | smart-4a4ddf28-70b0-4e0b-8ada-6bc56d6dafba |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3634943598 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.xbar_same_source.3634943598 |
| Directory | /workspace/24.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/24.xbar_smoke.901549181 |
| Short name | T2729 |
| Test name | |
| Test status | |
| Simulation time | 47472672 ps |
| CPU time | 7.08 seconds |
| Started | Jun 28 08:38:23 PM PDT 24 |
| Finished | Jun 28 08:38:41 PM PDT 24 |
| Peak memory | 574188 kb |
| Host | smart-fdaa148a-775e-47e0-9c6c-6fcb05d43936 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=901549181 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.xbar_smoke.901549181 |
| Directory | /workspace/24.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/24.xbar_smoke_large_delays.1623826689 |
| Short name | T2438 |
| Test name | |
| Test status | |
| Simulation time | 8348548666 ps |
| CPU time | 94.99 seconds |
| Started | Jun 28 08:38:26 PM PDT 24 |
| Finished | Jun 28 08:40:10 PM PDT 24 |
| Peak memory | 574256 kb |
| Host | smart-ebd03f3d-e39c-4dda-9dc9-fdfee8bfea6b |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1623826689 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.xbar_smoke_large_delays.1623826689 |
| Directory | /workspace/24.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/24.xbar_smoke_slow_rsp.2847209708 |
| Short name | T2425 |
| Test name | |
| Test status | |
| Simulation time | 4567151218 ps |
| CPU time | 77.26 seconds |
| Started | Jun 28 08:38:33 PM PDT 24 |
| Finished | Jun 28 08:39:55 PM PDT 24 |
| Peak memory | 574088 kb |
| Host | smart-d630de4d-c0eb-431b-812c-7dc9034b6370 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2847209708 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.xbar_smoke_slow_rsp.2847209708 |
| Directory | /workspace/24.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/24.xbar_smoke_zero_delays.3449070058 |
| Short name | T2511 |
| Test name | |
| Test status | |
| Simulation time | 36333375 ps |
| CPU time | 6.04 seconds |
| Started | Jun 28 08:38:21 PM PDT 24 |
| Finished | Jun 28 08:38:38 PM PDT 24 |
| Peak memory | 574184 kb |
| Host | smart-c5be2d86-757b-46b7-9da0-3051b35b774d |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3449070058 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.xbar_smoke_zero_delay s.3449070058 |
| Directory | /workspace/24.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/24.xbar_stress_all.3261575158 |
| Short name | T599 |
| Test name | |
| Test status | |
| Simulation time | 719776089 ps |
| CPU time | 28.09 seconds |
| Started | Jun 28 08:38:40 PM PDT 24 |
| Finished | Jun 28 08:39:12 PM PDT 24 |
| Peak memory | 575248 kb |
| Host | smart-3c477693-927d-42a1-b1a2-464071c1f5d9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3261575158 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.xbar_stress_all.3261575158 |
| Directory | /workspace/24.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/24.xbar_stress_all_with_error.3191536323 |
| Short name | T1749 |
| Test name | |
| Test status | |
| Simulation time | 4030521930 ps |
| CPU time | 305.96 seconds |
| Started | Jun 28 08:38:44 PM PDT 24 |
| Finished | Jun 28 08:43:53 PM PDT 24 |
| Peak memory | 574368 kb |
| Host | smart-630ff301-c82e-4e16-b504-c80dd7ebd2fd |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3191536323 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.xbar_stress_all_with_error.3191536323 |
| Directory | /workspace/24.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/24.xbar_stress_all_with_rand_reset.379832442 |
| Short name | T2442 |
| Test name | |
| Test status | |
| Simulation time | 1314621425 ps |
| CPU time | 347.45 seconds |
| Started | Jun 28 08:38:39 PM PDT 24 |
| Finished | Jun 28 08:44:30 PM PDT 24 |
| Peak memory | 575396 kb |
| Host | smart-8998a284-4b80-42dd-ac46-77ee4b18c40b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=379832442 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_res et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.xbar_stress_all_ with_rand_reset.379832442 |
| Directory | /workspace/24.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/24.xbar_stress_all_with_reset_error.843455032 |
| Short name | T1458 |
| Test name | |
| Test status | |
| Simulation time | 190432126 ps |
| CPU time | 55.18 seconds |
| Started | Jun 28 08:38:40 PM PDT 24 |
| Finished | Jun 28 08:39:38 PM PDT 24 |
| Peak memory | 574344 kb |
| Host | smart-3a3c96ce-3ac7-479c-873c-25493fe5c4ca |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=843455032 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.xbar_stress_all _with_reset_error.843455032 |
| Directory | /workspace/24.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/24.xbar_unmapped_addr.3013391111 |
| Short name | T2082 |
| Test name | |
| Test status | |
| Simulation time | 980486955 ps |
| CPU time | 48.65 seconds |
| Started | Jun 28 08:38:40 PM PDT 24 |
| Finished | Jun 28 08:39:32 PM PDT 24 |
| Peak memory | 575252 kb |
| Host | smart-a425706c-0073-4d7d-97ce-b96373748a6b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3013391111 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.xbar_unmapped_addr.3013391111 |
| Directory | /workspace/24.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/25.chip_tl_errors.1323460181 |
| Short name | T659 |
| Test name | |
| Test status | |
| Simulation time | 3737310356 ps |
| CPU time | 202.52 seconds |
| Started | Jun 28 08:38:41 PM PDT 24 |
| Finished | Jun 28 08:42:07 PM PDT 24 |
| Peak memory | 597440 kb |
| Host | smart-28b4da99-fe5b-4276-9a90-77564f66fcee |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1323460181 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.chip_tl_errors.1323460181 |
| Directory | /workspace/25.chip_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/25.xbar_access_same_device.3021841226 |
| Short name | T2509 |
| Test name | |
| Test status | |
| Simulation time | 3170368514 ps |
| CPU time | 138.9 seconds |
| Started | Jun 28 08:38:43 PM PDT 24 |
| Finished | Jun 28 08:41:05 PM PDT 24 |
| Peak memory | 575296 kb |
| Host | smart-c6df6b3a-30ae-4e12-9e75-c6fe60734d55 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3021841226 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.xbar_access_same_device .3021841226 |
| Directory | /workspace/25.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/25.xbar_access_same_device_slow_rsp.911220830 |
| Short name | T781 |
| Test name | |
| Test status | |
| Simulation time | 102113543655 ps |
| CPU time | 1854.02 seconds |
| Started | Jun 28 08:38:43 PM PDT 24 |
| Finished | Jun 28 09:09:40 PM PDT 24 |
| Peak memory | 575408 kb |
| Host | smart-e5b821f9-78cd-4fbe-b939-75d2b0c806bd |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=911220830 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.xbar_access_same_d evice_slow_rsp.911220830 |
| Directory | /workspace/25.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/25.xbar_error_and_unmapped_addr.3328912365 |
| Short name | T2564 |
| Test name | |
| Test status | |
| Simulation time | 554916032 ps |
| CPU time | 27.78 seconds |
| Started | Jun 28 08:38:46 PM PDT 24 |
| Finished | Jun 28 08:39:16 PM PDT 24 |
| Peak memory | 573940 kb |
| Host | smart-65902774-5331-4c31-ba63-558771feb7bc |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3328912365 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.xbar_error_and_unmapped_add r.3328912365 |
| Directory | /workspace/25.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/25.xbar_error_random.3065263338 |
| Short name | T2081 |
| Test name | |
| Test status | |
| Simulation time | 242648347 ps |
| CPU time | 13.17 seconds |
| Started | Jun 28 08:38:47 PM PDT 24 |
| Finished | Jun 28 08:39:01 PM PDT 24 |
| Peak memory | 573940 kb |
| Host | smart-8559d8bc-eb95-4890-81b4-33a013a0198d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3065263338 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.xbar_error_random.3065263338 |
| Directory | /workspace/25.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/25.xbar_random.1274241717 |
| Short name | T2255 |
| Test name | |
| Test status | |
| Simulation time | 530642844 ps |
| CPU time | 23.59 seconds |
| Started | Jun 28 08:38:45 PM PDT 24 |
| Finished | Jun 28 08:39:11 PM PDT 24 |
| Peak memory | 575220 kb |
| Host | smart-e26adbc6-48b8-4e1f-ba8d-ea7e1f439223 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1274241717 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.xbar_random.1274241717 |
| Directory | /workspace/25.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/25.xbar_random_large_delays.2114559247 |
| Short name | T565 |
| Test name | |
| Test status | |
| Simulation time | 36426916191 ps |
| CPU time | 406.82 seconds |
| Started | Jun 28 08:38:44 PM PDT 24 |
| Finished | Jun 28 08:45:34 PM PDT 24 |
| Peak memory | 575452 kb |
| Host | smart-8c166ae8-975b-4efe-8888-af393feda426 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2114559247 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.xbar_random_large_delays.2114559247 |
| Directory | /workspace/25.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/25.xbar_random_slow_rsp.1692271866 |
| Short name | T1386 |
| Test name | |
| Test status | |
| Simulation time | 14876165605 ps |
| CPU time | 260.76 seconds |
| Started | Jun 28 08:38:42 PM PDT 24 |
| Finished | Jun 28 08:43:06 PM PDT 24 |
| Peak memory | 575348 kb |
| Host | smart-3a30b03d-2427-453a-a53d-9d9652ed3133 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1692271866 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.xbar_random_slow_rsp.1692271866 |
| Directory | /workspace/25.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/25.xbar_random_zero_delays.2224333130 |
| Short name | T1975 |
| Test name | |
| Test status | |
| Simulation time | 201183973 ps |
| CPU time | 22.17 seconds |
| Started | Jun 28 08:38:44 PM PDT 24 |
| Finished | Jun 28 08:39:09 PM PDT 24 |
| Peak memory | 575364 kb |
| Host | smart-767a6a83-b64a-466e-92a8-5e0431f273c3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2224333130 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.xbar_random_zero_del ays.2224333130 |
| Directory | /workspace/25.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/25.xbar_same_source.1407183700 |
| Short name | T1461 |
| Test name | |
| Test status | |
| Simulation time | 1351929990 ps |
| CPU time | 41.1 seconds |
| Started | Jun 28 08:38:42 PM PDT 24 |
| Finished | Jun 28 08:39:26 PM PDT 24 |
| Peak memory | 574176 kb |
| Host | smart-355031cd-c9a1-4e1a-a7b3-4a76f701dec5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1407183700 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.xbar_same_source.1407183700 |
| Directory | /workspace/25.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/25.xbar_smoke.3685645676 |
| Short name | T2273 |
| Test name | |
| Test status | |
| Simulation time | 205683902 ps |
| CPU time | 9.93 seconds |
| Started | Jun 28 08:38:40 PM PDT 24 |
| Finished | Jun 28 08:38:53 PM PDT 24 |
| Peak memory | 574192 kb |
| Host | smart-2b8b62b0-1203-48c1-bbc5-02a047852208 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3685645676 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.xbar_smoke.3685645676 |
| Directory | /workspace/25.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/25.xbar_smoke_large_delays.3682639613 |
| Short name | T2795 |
| Test name | |
| Test status | |
| Simulation time | 9317817187 ps |
| CPU time | 100.99 seconds |
| Started | Jun 28 08:38:41 PM PDT 24 |
| Finished | Jun 28 08:40:25 PM PDT 24 |
| Peak memory | 574256 kb |
| Host | smart-c0a6ef82-eeb1-40de-9fed-96818326873e |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3682639613 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.xbar_smoke_large_delays.3682639613 |
| Directory | /workspace/25.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/25.xbar_smoke_slow_rsp.3536673991 |
| Short name | T74 |
| Test name | |
| Test status | |
| Simulation time | 5871757307 ps |
| CPU time | 106.67 seconds |
| Started | Jun 28 08:38:40 PM PDT 24 |
| Finished | Jun 28 08:40:31 PM PDT 24 |
| Peak memory | 566016 kb |
| Host | smart-b4973618-0e32-4115-8749-1f7298ab67db |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3536673991 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.xbar_smoke_slow_rsp.3536673991 |
| Directory | /workspace/25.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/25.xbar_smoke_zero_delays.1249099052 |
| Short name | T529 |
| Test name | |
| Test status | |
| Simulation time | 47502256 ps |
| CPU time | 7.09 seconds |
| Started | Jun 28 08:38:40 PM PDT 24 |
| Finished | Jun 28 08:38:51 PM PDT 24 |
| Peak memory | 574184 kb |
| Host | smart-e68ebec1-3c18-42d2-a333-2a15f9459ec5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1249099052 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.xbar_smoke_zero_delay s.1249099052 |
| Directory | /workspace/25.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/25.xbar_stress_all.2223053494 |
| Short name | T1729 |
| Test name | |
| Test status | |
| Simulation time | 1387222678 ps |
| CPU time | 120.83 seconds |
| Started | Jun 28 08:38:43 PM PDT 24 |
| Finished | Jun 28 08:40:47 PM PDT 24 |
| Peak memory | 575348 kb |
| Host | smart-1140db55-6083-40e3-9bb3-4c1795e1aed9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2223053494 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.xbar_stress_all.2223053494 |
| Directory | /workspace/25.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/25.xbar_stress_all_with_reset_error.3227904521 |
| Short name | T2716 |
| Test name | |
| Test status | |
| Simulation time | 1301871955 ps |
| CPU time | 84.25 seconds |
| Started | Jun 28 08:38:43 PM PDT 24 |
| Finished | Jun 28 08:40:10 PM PDT 24 |
| Peak memory | 577428 kb |
| Host | smart-405d95be-b664-41d3-934d-a0397fe0d0c7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3227904521 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.xbar_stress_al l_with_reset_error.3227904521 |
| Directory | /workspace/25.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/25.xbar_unmapped_addr.248532941 |
| Short name | T2355 |
| Test name | |
| Test status | |
| Simulation time | 1252993524 ps |
| CPU time | 59.2 seconds |
| Started | Jun 28 08:38:46 PM PDT 24 |
| Finished | Jun 28 08:39:47 PM PDT 24 |
| Peak memory | 575404 kb |
| Host | smart-f9f434a3-3746-4ff0-8978-123dfd0d6411 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=248532941 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.xbar_unmapped_addr.248532941 |
| Directory | /workspace/25.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/26.chip_tl_errors.4284664765 |
| Short name | T544 |
| Test name | |
| Test status | |
| Simulation time | 3940681298 ps |
| CPU time | 304.49 seconds |
| Started | Jun 28 08:38:41 PM PDT 24 |
| Finished | Jun 28 08:43:49 PM PDT 24 |
| Peak memory | 597440 kb |
| Host | smart-a9022507-9a41-479d-b811-6de38b8b958b |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4284664765 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.chip_tl_errors.4284664765 |
| Directory | /workspace/26.chip_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/26.xbar_access_same_device.3836474894 |
| Short name | T2868 |
| Test name | |
| Test status | |
| Simulation time | 3106392484 ps |
| CPU time | 143.98 seconds |
| Started | Jun 28 08:39:12 PM PDT 24 |
| Finished | Jun 28 08:41:52 PM PDT 24 |
| Peak memory | 574344 kb |
| Host | smart-291c19c7-11d3-45b6-b521-df7fe17d5b48 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3836474894 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.xbar_access_same_device .3836474894 |
| Directory | /workspace/26.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/26.xbar_access_same_device_slow_rsp.3040081673 |
| Short name | T500 |
| Test name | |
| Test status | |
| Simulation time | 120138561230 ps |
| CPU time | 2165.41 seconds |
| Started | Jun 28 08:39:12 PM PDT 24 |
| Finished | Jun 28 09:15:34 PM PDT 24 |
| Peak memory | 574236 kb |
| Host | smart-c957461b-fdb9-46a5-8ee9-6a1f50087280 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3040081673 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.xbar_access_same_ device_slow_rsp.3040081673 |
| Directory | /workspace/26.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/26.xbar_error_and_unmapped_addr.287851366 |
| Short name | T2789 |
| Test name | |
| Test status | |
| Simulation time | 920541395 ps |
| CPU time | 41.97 seconds |
| Started | Jun 28 08:39:09 PM PDT 24 |
| Finished | Jun 28 08:40:07 PM PDT 24 |
| Peak memory | 574224 kb |
| Host | smart-9d3cbbab-a651-42ac-b5b5-79f40ee9b4f5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=287851366 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.xbar_error_and_unmapped_addr .287851366 |
| Directory | /workspace/26.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/26.xbar_error_random.808065906 |
| Short name | T2229 |
| Test name | |
| Test status | |
| Simulation time | 416808102 ps |
| CPU time | 37.78 seconds |
| Started | Jun 28 08:39:10 PM PDT 24 |
| Finished | Jun 28 08:40:04 PM PDT 24 |
| Peak memory | 573824 kb |
| Host | smart-5c25306d-50f7-4039-b4f2-167383a909a1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=808065906 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.xbar_error_random.808065906 |
| Directory | /workspace/26.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/26.xbar_random.611043799 |
| Short name | T2145 |
| Test name | |
| Test status | |
| Simulation time | 579938594 ps |
| CPU time | 52.86 seconds |
| Started | Jun 28 08:39:09 PM PDT 24 |
| Finished | Jun 28 08:40:17 PM PDT 24 |
| Peak memory | 575248 kb |
| Host | smart-8cfc4485-2aa9-49cc-ae7d-38cf579cfedf |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=611043799 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.xbar_random.611043799 |
| Directory | /workspace/26.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/26.xbar_random_large_delays.1501982654 |
| Short name | T1745 |
| Test name | |
| Test status | |
| Simulation time | 84114445766 ps |
| CPU time | 952.06 seconds |
| Started | Jun 28 08:39:11 PM PDT 24 |
| Finished | Jun 28 08:55:18 PM PDT 24 |
| Peak memory | 574276 kb |
| Host | smart-350295b2-7029-4a87-aca8-4edd1c86489c |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1501982654 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.xbar_random_large_delays.1501982654 |
| Directory | /workspace/26.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/26.xbar_random_slow_rsp.4105433304 |
| Short name | T1878 |
| Test name | |
| Test status | |
| Simulation time | 60897896164 ps |
| CPU time | 1112.08 seconds |
| Started | Jun 28 08:39:09 PM PDT 24 |
| Finished | Jun 28 08:57:57 PM PDT 24 |
| Peak memory | 575332 kb |
| Host | smart-f859640a-73bc-4e4c-ae31-b371f88dda29 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4105433304 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.xbar_random_slow_rsp.4105433304 |
| Directory | /workspace/26.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/26.xbar_random_zero_delays.3089420923 |
| Short name | T2185 |
| Test name | |
| Test status | |
| Simulation time | 268816999 ps |
| CPU time | 26.5 seconds |
| Started | Jun 28 08:39:10 PM PDT 24 |
| Finished | Jun 28 08:39:53 PM PDT 24 |
| Peak memory | 575244 kb |
| Host | smart-f919c295-4722-45c9-a12f-8485c292aa98 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3089420923 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.xbar_random_zero_del ays.3089420923 |
| Directory | /workspace/26.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/26.xbar_same_source.83926459 |
| Short name | T2362 |
| Test name | |
| Test status | |
| Simulation time | 1474313334 ps |
| CPU time | 50.19 seconds |
| Started | Jun 28 08:39:11 PM PDT 24 |
| Finished | Jun 28 08:40:17 PM PDT 24 |
| Peak memory | 574148 kb |
| Host | smart-f69f8e6c-2fe0-476b-aa55-9647a05a8f27 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83926459 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.xbar_same_source.83926459 |
| Directory | /workspace/26.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/26.xbar_smoke.1843343249 |
| Short name | T2812 |
| Test name | |
| Test status | |
| Simulation time | 41093256 ps |
| CPU time | 6.08 seconds |
| Started | Jun 28 08:38:41 PM PDT 24 |
| Finished | Jun 28 08:38:51 PM PDT 24 |
| Peak memory | 574180 kb |
| Host | smart-d9e420c3-19a7-4fd7-a64a-f5c8097a1d2b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1843343249 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.xbar_smoke.1843343249 |
| Directory | /workspace/26.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/26.xbar_smoke_large_delays.3182653652 |
| Short name | T2038 |
| Test name | |
| Test status | |
| Simulation time | 7644907761 ps |
| CPU time | 79.58 seconds |
| Started | Jun 28 08:39:11 PM PDT 24 |
| Finished | Jun 28 08:40:46 PM PDT 24 |
| Peak memory | 574188 kb |
| Host | smart-5785a274-d4ca-4215-9d1e-f648bb0986c0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3182653652 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.xbar_smoke_large_delays.3182653652 |
| Directory | /workspace/26.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/26.xbar_smoke_slow_rsp.831973131 |
| Short name | T2540 |
| Test name | |
| Test status | |
| Simulation time | 3291506215 ps |
| CPU time | 58.72 seconds |
| Started | Jun 28 08:39:11 PM PDT 24 |
| Finished | Jun 28 08:40:26 PM PDT 24 |
| Peak memory | 574068 kb |
| Host | smart-c95e8d15-82c8-4632-b2cf-84eddf4d6971 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=831973131 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.xbar_smoke_slow_rsp.831973131 |
| Directory | /workspace/26.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/26.xbar_smoke_zero_delays.1564701809 |
| Short name | T2341 |
| Test name | |
| Test status | |
| Simulation time | 44462393 ps |
| CPU time | 6.36 seconds |
| Started | Jun 28 08:38:40 PM PDT 24 |
| Finished | Jun 28 08:38:50 PM PDT 24 |
| Peak memory | 574132 kb |
| Host | smart-d00e3444-7901-421e-8f85-44a71c83c5b0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1564701809 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.xbar_smoke_zero_delay s.1564701809 |
| Directory | /workspace/26.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/26.xbar_stress_all.3407464309 |
| Short name | T1490 |
| Test name | |
| Test status | |
| Simulation time | 12340517209 ps |
| CPU time | 450.44 seconds |
| Started | Jun 28 08:39:09 PM PDT 24 |
| Finished | Jun 28 08:46:55 PM PDT 24 |
| Peak memory | 574368 kb |
| Host | smart-c7e5569c-b06a-4c9c-b94d-aa53f5ce95c2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3407464309 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.xbar_stress_all.3407464309 |
| Directory | /workspace/26.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/26.xbar_stress_all_with_error.508038699 |
| Short name | T2802 |
| Test name | |
| Test status | |
| Simulation time | 2129127459 ps |
| CPU time | 191.2 seconds |
| Started | Jun 28 08:39:10 PM PDT 24 |
| Finished | Jun 28 08:42:37 PM PDT 24 |
| Peak memory | 574608 kb |
| Host | smart-a8eaf3e9-151b-4328-8f39-d765623c5d15 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=508038699 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.xbar_stress_all_with_error.508038699 |
| Directory | /workspace/26.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/26.xbar_stress_all_with_reset_error.2205656309 |
| Short name | T2123 |
| Test name | |
| Test status | |
| Simulation time | 307682799 ps |
| CPU time | 64.58 seconds |
| Started | Jun 28 08:39:15 PM PDT 24 |
| Finished | Jun 28 08:40:34 PM PDT 24 |
| Peak memory | 574324 kb |
| Host | smart-6130deda-07c3-4ccd-a38f-27757d84161c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2205656309 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.xbar_stress_al l_with_reset_error.2205656309 |
| Directory | /workspace/26.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/26.xbar_unmapped_addr.4236901880 |
| Short name | T2246 |
| Test name | |
| Test status | |
| Simulation time | 364901455 ps |
| CPU time | 18.53 seconds |
| Started | Jun 28 08:39:08 PM PDT 24 |
| Finished | Jun 28 08:39:42 PM PDT 24 |
| Peak memory | 575280 kb |
| Host | smart-7390ad5b-6ed1-4a46-ad3b-291933a91235 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4236901880 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.xbar_unmapped_addr.4236901880 |
| Directory | /workspace/26.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/27.xbar_access_same_device.782868646 |
| Short name | T2647 |
| Test name | |
| Test status | |
| Simulation time | 112481367 ps |
| CPU time | 17.26 seconds |
| Started | Jun 28 08:39:10 PM PDT 24 |
| Finished | Jun 28 08:39:43 PM PDT 24 |
| Peak memory | 575200 kb |
| Host | smart-1f55626e-ef0d-447b-b210-a037226d8078 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=782868646 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.xbar_access_same_device. 782868646 |
| Directory | /workspace/27.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/27.xbar_access_same_device_slow_rsp.2289391515 |
| Short name | T2718 |
| Test name | |
| Test status | |
| Simulation time | 68998603471 ps |
| CPU time | 1183.93 seconds |
| Started | Jun 28 08:39:13 PM PDT 24 |
| Finished | Jun 28 08:59:12 PM PDT 24 |
| Peak memory | 574244 kb |
| Host | smart-9008304a-8acc-49a2-8841-175bbb0565b8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2289391515 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.xbar_access_same_ device_slow_rsp.2289391515 |
| Directory | /workspace/27.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/27.xbar_error_and_unmapped_addr.1655402416 |
| Short name | T2172 |
| Test name | |
| Test status | |
| Simulation time | 1127772339 ps |
| CPU time | 48.5 seconds |
| Started | Jun 28 08:39:28 PM PDT 24 |
| Finished | Jun 28 08:40:26 PM PDT 24 |
| Peak memory | 573956 kb |
| Host | smart-aabf11eb-c4a5-46c5-b101-ae6b65c919c1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1655402416 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.xbar_error_and_unmapped_add r.1655402416 |
| Directory | /workspace/27.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/27.xbar_error_random.1740875265 |
| Short name | T520 |
| Test name | |
| Test status | |
| Simulation time | 2242308382 ps |
| CPU time | 95.1 seconds |
| Started | Jun 28 08:39:11 PM PDT 24 |
| Finished | Jun 28 08:41:01 PM PDT 24 |
| Peak memory | 574268 kb |
| Host | smart-1af9cc57-90a1-4599-a499-2da0eeff6696 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1740875265 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.xbar_error_random.1740875265 |
| Directory | /workspace/27.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/27.xbar_random.1893096345 |
| Short name | T1384 |
| Test name | |
| Test status | |
| Simulation time | 792921006 ps |
| CPU time | 37.61 seconds |
| Started | Jun 28 08:39:15 PM PDT 24 |
| Finished | Jun 28 08:40:07 PM PDT 24 |
| Peak memory | 575264 kb |
| Host | smart-e74cc5fd-30c2-4c77-8b63-f77f673da193 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1893096345 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.xbar_random.1893096345 |
| Directory | /workspace/27.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/27.xbar_random_large_delays.788274523 |
| Short name | T1698 |
| Test name | |
| Test status | |
| Simulation time | 60237143666 ps |
| CPU time | 627.5 seconds |
| Started | Jun 28 08:39:13 PM PDT 24 |
| Finished | Jun 28 08:49:56 PM PDT 24 |
| Peak memory | 575368 kb |
| Host | smart-579c4acc-a5ad-4f4c-9605-066db2cf148c |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=788274523 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.xbar_random_large_delays.788274523 |
| Directory | /workspace/27.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/27.xbar_random_slow_rsp.3599520975 |
| Short name | T2003 |
| Test name | |
| Test status | |
| Simulation time | 2426487701 ps |
| CPU time | 45.26 seconds |
| Started | Jun 28 08:39:10 PM PDT 24 |
| Finished | Jun 28 08:40:11 PM PDT 24 |
| Peak memory | 574140 kb |
| Host | smart-eb4fefab-4139-4323-a360-16d8021bc1cb |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3599520975 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.xbar_random_slow_rsp.3599520975 |
| Directory | /workspace/27.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/27.xbar_random_zero_delays.2928660802 |
| Short name | T2545 |
| Test name | |
| Test status | |
| Simulation time | 499594391 ps |
| CPU time | 42.36 seconds |
| Started | Jun 28 08:39:14 PM PDT 24 |
| Finished | Jun 28 08:40:12 PM PDT 24 |
| Peak memory | 575280 kb |
| Host | smart-fdfbeff3-f106-43ce-bd7e-22b418ab91a4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2928660802 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.xbar_random_zero_del ays.2928660802 |
| Directory | /workspace/27.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/27.xbar_same_source.3710076241 |
| Short name | T2084 |
| Test name | |
| Test status | |
| Simulation time | 1632592430 ps |
| CPU time | 56.21 seconds |
| Started | Jun 28 08:39:10 PM PDT 24 |
| Finished | Jun 28 08:40:21 PM PDT 24 |
| Peak memory | 575240 kb |
| Host | smart-cf419fcc-55c3-4d5f-a62c-ead8c0b8680b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3710076241 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.xbar_same_source.3710076241 |
| Directory | /workspace/27.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/27.xbar_smoke.438452097 |
| Short name | T1396 |
| Test name | |
| Test status | |
| Simulation time | 197792523 ps |
| CPU time | 9.83 seconds |
| Started | Jun 28 08:39:10 PM PDT 24 |
| Finished | Jun 28 08:39:35 PM PDT 24 |
| Peak memory | 574188 kb |
| Host | smart-08968a71-efbc-4022-be74-6fa0cec47a6a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=438452097 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.xbar_smoke.438452097 |
| Directory | /workspace/27.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/27.xbar_smoke_large_delays.3532578461 |
| Short name | T2444 |
| Test name | |
| Test status | |
| Simulation time | 7395861547 ps |
| CPU time | 78.23 seconds |
| Started | Jun 28 08:39:08 PM PDT 24 |
| Finished | Jun 28 08:40:42 PM PDT 24 |
| Peak memory | 574240 kb |
| Host | smart-2ca6f269-d573-4b33-b7d5-f7a23a8a0ff4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3532578461 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.xbar_smoke_large_delays.3532578461 |
| Directory | /workspace/27.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/27.xbar_smoke_slow_rsp.284844999 |
| Short name | T2507 |
| Test name | |
| Test status | |
| Simulation time | 4734696738 ps |
| CPU time | 81.15 seconds |
| Started | Jun 28 08:39:11 PM PDT 24 |
| Finished | Jun 28 08:40:47 PM PDT 24 |
| Peak memory | 574020 kb |
| Host | smart-1c4ea67b-2e80-4190-b511-59f78b4a8581 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=284844999 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.xbar_smoke_slow_rsp.284844999 |
| Directory | /workspace/27.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/27.xbar_smoke_zero_delays.3640306210 |
| Short name | T1526 |
| Test name | |
| Test status | |
| Simulation time | 49612848 ps |
| CPU time | 7.09 seconds |
| Started | Jun 28 08:39:10 PM PDT 24 |
| Finished | Jun 28 08:39:33 PM PDT 24 |
| Peak memory | 574184 kb |
| Host | smart-f6868130-0f17-4ef4-8a45-eebace3a140d |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3640306210 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.xbar_smoke_zero_delay s.3640306210 |
| Directory | /workspace/27.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/27.xbar_stress_all.2795514717 |
| Short name | T1453 |
| Test name | |
| Test status | |
| Simulation time | 2107170459 ps |
| CPU time | 76.66 seconds |
| Started | Jun 28 08:39:29 PM PDT 24 |
| Finished | Jun 28 08:40:55 PM PDT 24 |
| Peak memory | 575292 kb |
| Host | smart-005e5243-cb51-4dfa-a977-03a492fcf384 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2795514717 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.xbar_stress_all.2795514717 |
| Directory | /workspace/27.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/27.xbar_stress_all_with_error.615747383 |
| Short name | T1757 |
| Test name | |
| Test status | |
| Simulation time | 1873040522 ps |
| CPU time | 85.23 seconds |
| Started | Jun 28 08:39:29 PM PDT 24 |
| Finished | Jun 28 08:41:03 PM PDT 24 |
| Peak memory | 574200 kb |
| Host | smart-fad0e872-b64c-41b3-8a1f-f5c351505026 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=615747383 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.xbar_stress_all_with_error.615747383 |
| Directory | /workspace/27.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/27.xbar_stress_all_with_rand_reset.4220861504 |
| Short name | T2780 |
| Test name | |
| Test status | |
| Simulation time | 591832782 ps |
| CPU time | 199.46 seconds |
| Started | Jun 28 08:39:29 PM PDT 24 |
| Finished | Jun 28 08:42:58 PM PDT 24 |
| Peak memory | 575388 kb |
| Host | smart-e85bf5b1-5ed1-4481-9822-8019a2c38e26 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4220861504 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.xbar_stress_all _with_rand_reset.4220861504 |
| Directory | /workspace/27.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/27.xbar_stress_all_with_reset_error.2894551050 |
| Short name | T545 |
| Test name | |
| Test status | |
| Simulation time | 4989708683 ps |
| CPU time | 607.55 seconds |
| Started | Jun 28 08:39:30 PM PDT 24 |
| Finished | Jun 28 08:49:46 PM PDT 24 |
| Peak memory | 574668 kb |
| Host | smart-844f0c4f-5868-4aac-a308-3746b55f7905 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2894551050 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.xbar_stress_al l_with_reset_error.2894551050 |
| Directory | /workspace/27.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/27.xbar_unmapped_addr.3453994815 |
| Short name | T2667 |
| Test name | |
| Test status | |
| Simulation time | 242986793 ps |
| CPU time | 14.1 seconds |
| Started | Jun 28 08:39:12 PM PDT 24 |
| Finished | Jun 28 08:39:42 PM PDT 24 |
| Peak memory | 575320 kb |
| Host | smart-f8f7581c-78b4-46f9-80b5-69e1cd6eba6e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3453994815 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.xbar_unmapped_addr.3453994815 |
| Directory | /workspace/27.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/28.xbar_access_same_device.349166514 |
| Short name | T2408 |
| Test name | |
| Test status | |
| Simulation time | 3116742393 ps |
| CPU time | 133.53 seconds |
| Started | Jun 28 08:39:31 PM PDT 24 |
| Finished | Jun 28 08:41:53 PM PDT 24 |
| Peak memory | 575292 kb |
| Host | smart-5637d180-1bb4-4869-bc95-664395fb76eb |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=349166514 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.xbar_access_same_device. 349166514 |
| Directory | /workspace/28.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/28.xbar_access_same_device_slow_rsp.1707206913 |
| Short name | T1895 |
| Test name | |
| Test status | |
| Simulation time | 81585799789 ps |
| CPU time | 1426.22 seconds |
| Started | Jun 28 08:39:31 PM PDT 24 |
| Finished | Jun 28 09:03:26 PM PDT 24 |
| Peak memory | 575320 kb |
| Host | smart-2ecaf523-5c14-4038-8e10-cb2744e090cb |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1707206913 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.xbar_access_same_ device_slow_rsp.1707206913 |
| Directory | /workspace/28.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/28.xbar_error_and_unmapped_addr.3503134746 |
| Short name | T1454 |
| Test name | |
| Test status | |
| Simulation time | 209951227 ps |
| CPU time | 11.57 seconds |
| Started | Jun 28 08:39:34 PM PDT 24 |
| Finished | Jun 28 08:39:53 PM PDT 24 |
| Peak memory | 574432 kb |
| Host | smart-5a906528-91cb-4206-9289-2da97c4cc583 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3503134746 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.xbar_error_and_unmapped_add r.3503134746 |
| Directory | /workspace/28.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/28.xbar_error_random.3319788172 |
| Short name | T1706 |
| Test name | |
| Test status | |
| Simulation time | 251596605 ps |
| CPU time | 24.24 seconds |
| Started | Jun 28 08:39:26 PM PDT 24 |
| Finished | Jun 28 08:40:00 PM PDT 24 |
| Peak memory | 574428 kb |
| Host | smart-395a2419-d8fa-4f65-9c70-58ef616d615f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3319788172 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.xbar_error_random.3319788172 |
| Directory | /workspace/28.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/28.xbar_random.3988811897 |
| Short name | T587 |
| Test name | |
| Test status | |
| Simulation time | 1710218848 ps |
| CPU time | 68.8 seconds |
| Started | Jun 28 08:39:29 PM PDT 24 |
| Finished | Jun 28 08:40:47 PM PDT 24 |
| Peak memory | 575288 kb |
| Host | smart-37515ff2-e09d-4c79-a7a0-35f79f31e952 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3988811897 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.xbar_random.3988811897 |
| Directory | /workspace/28.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/28.xbar_random_large_delays.2215209584 |
| Short name | T2590 |
| Test name | |
| Test status | |
| Simulation time | 64226042840 ps |
| CPU time | 624.58 seconds |
| Started | Jun 28 08:39:30 PM PDT 24 |
| Finished | Jun 28 08:50:03 PM PDT 24 |
| Peak memory | 574260 kb |
| Host | smart-419eca87-c8f7-489e-ab66-7e7d3c3218b2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2215209584 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.xbar_random_large_delays.2215209584 |
| Directory | /workspace/28.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/28.xbar_random_slow_rsp.4028121756 |
| Short name | T1435 |
| Test name | |
| Test status | |
| Simulation time | 26123397360 ps |
| CPU time | 493.27 seconds |
| Started | Jun 28 08:39:30 PM PDT 24 |
| Finished | Jun 28 08:47:52 PM PDT 24 |
| Peak memory | 575320 kb |
| Host | smart-471e86b9-e5a1-43fc-8be2-7f6aa64ccee1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4028121756 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.xbar_random_slow_rsp.4028121756 |
| Directory | /workspace/28.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/28.xbar_random_zero_delays.151949629 |
| Short name | T2823 |
| Test name | |
| Test status | |
| Simulation time | 408913726 ps |
| CPU time | 39.01 seconds |
| Started | Jun 28 08:39:28 PM PDT 24 |
| Finished | Jun 28 08:40:16 PM PDT 24 |
| Peak memory | 575372 kb |
| Host | smart-25f846a1-16b3-4d5e-9147-62eed40d3063 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=151949629 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.xbar_random_zero_dela ys.151949629 |
| Directory | /workspace/28.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/28.xbar_same_source.2407678556 |
| Short name | T1734 |
| Test name | |
| Test status | |
| Simulation time | 2010908582 ps |
| CPU time | 69.02 seconds |
| Started | Jun 28 08:39:31 PM PDT 24 |
| Finished | Jun 28 08:40:49 PM PDT 24 |
| Peak memory | 574132 kb |
| Host | smart-d53ba006-50e6-4489-be44-a4d61ed05092 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2407678556 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.xbar_same_source.2407678556 |
| Directory | /workspace/28.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/28.xbar_smoke.774362525 |
| Short name | T1330 |
| Test name | |
| Test status | |
| Simulation time | 195162260 ps |
| CPU time | 9.82 seconds |
| Started | Jun 28 08:39:28 PM PDT 24 |
| Finished | Jun 28 08:39:47 PM PDT 24 |
| Peak memory | 574192 kb |
| Host | smart-d3ba3a28-f9ea-4484-a2ad-4100731cb14c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=774362525 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.xbar_smoke.774362525 |
| Directory | /workspace/28.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/28.xbar_smoke_large_delays.3005292918 |
| Short name | T2103 |
| Test name | |
| Test status | |
| Simulation time | 6342244078 ps |
| CPU time | 65.76 seconds |
| Started | Jun 28 08:39:28 PM PDT 24 |
| Finished | Jun 28 08:40:42 PM PDT 24 |
| Peak memory | 566024 kb |
| Host | smart-5b136560-e1fa-46fa-a5e0-02da1a7ec3e3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3005292918 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.xbar_smoke_large_delays.3005292918 |
| Directory | /workspace/28.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/28.xbar_smoke_slow_rsp.3766925942 |
| Short name | T1553 |
| Test name | |
| Test status | |
| Simulation time | 5265833497 ps |
| CPU time | 89.79 seconds |
| Started | Jun 28 08:39:31 PM PDT 24 |
| Finished | Jun 28 08:41:10 PM PDT 24 |
| Peak memory | 574256 kb |
| Host | smart-838e6c0f-6769-4b58-b2b4-04381451d5c1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3766925942 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.xbar_smoke_slow_rsp.3766925942 |
| Directory | /workspace/28.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/28.xbar_smoke_zero_delays.2371525008 |
| Short name | T2562 |
| Test name | |
| Test status | |
| Simulation time | 50392393 ps |
| CPU time | 6.97 seconds |
| Started | Jun 28 08:39:28 PM PDT 24 |
| Finished | Jun 28 08:39:44 PM PDT 24 |
| Peak memory | 574184 kb |
| Host | smart-7f0ac6b3-e969-4e7d-b587-bbe71e18c9cc |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2371525008 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.xbar_smoke_zero_delay s.2371525008 |
| Directory | /workspace/28.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/28.xbar_stress_all.3745882442 |
| Short name | T2241 |
| Test name | |
| Test status | |
| Simulation time | 19221055005 ps |
| CPU time | 752.99 seconds |
| Started | Jun 28 08:39:33 PM PDT 24 |
| Finished | Jun 28 08:52:15 PM PDT 24 |
| Peak memory | 574332 kb |
| Host | smart-75125e68-12f3-4176-a914-14536821a348 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3745882442 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.xbar_stress_all.3745882442 |
| Directory | /workspace/28.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/28.xbar_stress_all_with_error.4106541136 |
| Short name | T1379 |
| Test name | |
| Test status | |
| Simulation time | 5317940769 ps |
| CPU time | 212.21 seconds |
| Started | Jun 28 08:39:38 PM PDT 24 |
| Finished | Jun 28 08:43:17 PM PDT 24 |
| Peak memory | 574424 kb |
| Host | smart-f1dc5757-d33d-4fd8-8a27-e4caa18a0a3c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4106541136 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.xbar_stress_all_with_error.4106541136 |
| Directory | /workspace/28.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/28.xbar_stress_all_with_reset_error.614402673 |
| Short name | T2445 |
| Test name | |
| Test status | |
| Simulation time | 21241938837 ps |
| CPU time | 889.67 seconds |
| Started | Jun 28 08:39:31 PM PDT 24 |
| Finished | Jun 28 08:54:29 PM PDT 24 |
| Peak memory | 576448 kb |
| Host | smart-7aa97493-c1f2-43e1-9343-ead89a20e7e2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=614402673 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.xbar_stress_all _with_reset_error.614402673 |
| Directory | /workspace/28.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/28.xbar_unmapped_addr.1080163036 |
| Short name | T2093 |
| Test name | |
| Test status | |
| Simulation time | 902026100 ps |
| CPU time | 39.86 seconds |
| Started | Jun 28 08:39:34 PM PDT 24 |
| Finished | Jun 28 08:40:22 PM PDT 24 |
| Peak memory | 575300 kb |
| Host | smart-263ce372-6125-447c-ac67-43df583aaeb2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1080163036 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.xbar_unmapped_addr.1080163036 |
| Directory | /workspace/28.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/29.xbar_access_same_device.3336229372 |
| Short name | T2591 |
| Test name | |
| Test status | |
| Simulation time | 151854085 ps |
| CPU time | 10.42 seconds |
| Started | Jun 28 08:39:42 PM PDT 24 |
| Finished | Jun 28 08:39:57 PM PDT 24 |
| Peak memory | 565864 kb |
| Host | smart-04c1e1a2-90b5-4f02-8f8e-3638cbe034df |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3336229372 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.xbar_access_same_device .3336229372 |
| Directory | /workspace/29.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/29.xbar_access_same_device_slow_rsp.372864321 |
| Short name | T2512 |
| Test name | |
| Test status | |
| Simulation time | 84924127617 ps |
| CPU time | 1431.95 seconds |
| Started | Jun 28 08:39:35 PM PDT 24 |
| Finished | Jun 28 09:03:35 PM PDT 24 |
| Peak memory | 574364 kb |
| Host | smart-a6c04f50-9e3f-4182-9ad2-933e5ff90979 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=372864321 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.xbar_access_same_d evice_slow_rsp.372864321 |
| Directory | /workspace/29.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/29.xbar_error_and_unmapped_addr.2145608307 |
| Short name | T2232 |
| Test name | |
| Test status | |
| Simulation time | 228362200 ps |
| CPU time | 26.52 seconds |
| Started | Jun 28 08:39:42 PM PDT 24 |
| Finished | Jun 28 08:40:13 PM PDT 24 |
| Peak memory | 574412 kb |
| Host | smart-dbc377d3-a626-4225-bfc1-87961fb18d76 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2145608307 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.xbar_error_and_unmapped_add r.2145608307 |
| Directory | /workspace/29.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/29.xbar_error_random.2982111166 |
| Short name | T2422 |
| Test name | |
| Test status | |
| Simulation time | 65656522 ps |
| CPU time | 8.99 seconds |
| Started | Jun 28 08:39:41 PM PDT 24 |
| Finished | Jun 28 08:39:55 PM PDT 24 |
| Peak memory | 573860 kb |
| Host | smart-29c01bfc-e347-4e63-b71e-c48452e4f4c0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2982111166 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.xbar_error_random.2982111166 |
| Directory | /workspace/29.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/29.xbar_random.319484714 |
| Short name | T2167 |
| Test name | |
| Test status | |
| Simulation time | 820904084 ps |
| CPU time | 36.03 seconds |
| Started | Jun 28 08:39:31 PM PDT 24 |
| Finished | Jun 28 08:40:16 PM PDT 24 |
| Peak memory | 574180 kb |
| Host | smart-5d373514-c7ff-48bc-bce2-c99ae2393eba |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=319484714 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.xbar_random.319484714 |
| Directory | /workspace/29.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/29.xbar_random_large_delays.1880333409 |
| Short name | T1339 |
| Test name | |
| Test status | |
| Simulation time | 21258095200 ps |
| CPU time | 234 seconds |
| Started | Jun 28 08:39:35 PM PDT 24 |
| Finished | Jun 28 08:43:37 PM PDT 24 |
| Peak memory | 575316 kb |
| Host | smart-a694f394-806b-4465-adcc-88ea178c9527 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1880333409 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.xbar_random_large_delays.1880333409 |
| Directory | /workspace/29.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/29.xbar_random_slow_rsp.3925130391 |
| Short name | T1846 |
| Test name | |
| Test status | |
| Simulation time | 17701443598 ps |
| CPU time | 313.21 seconds |
| Started | Jun 28 08:39:32 PM PDT 24 |
| Finished | Jun 28 08:44:54 PM PDT 24 |
| Peak memory | 575304 kb |
| Host | smart-a9990e0c-e750-4f0c-bb0f-d41868350922 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3925130391 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.xbar_random_slow_rsp.3925130391 |
| Directory | /workspace/29.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/29.xbar_random_zero_delays.1286374785 |
| Short name | T2170 |
| Test name | |
| Test status | |
| Simulation time | 99553461 ps |
| CPU time | 11.85 seconds |
| Started | Jun 28 08:39:42 PM PDT 24 |
| Finished | Jun 28 08:39:59 PM PDT 24 |
| Peak memory | 575232 kb |
| Host | smart-0e5189fb-7999-4f0c-918a-e1bbb44584db |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1286374785 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.xbar_random_zero_del ays.1286374785 |
| Directory | /workspace/29.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/29.xbar_same_source.3244418496 |
| Short name | T2660 |
| Test name | |
| Test status | |
| Simulation time | 513690062 ps |
| CPU time | 42.86 seconds |
| Started | Jun 28 08:39:36 PM PDT 24 |
| Finished | Jun 28 08:40:26 PM PDT 24 |
| Peak memory | 575224 kb |
| Host | smart-c48b38b8-1e9d-4139-bc7f-9d4e715f6794 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3244418496 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.xbar_same_source.3244418496 |
| Directory | /workspace/29.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/29.xbar_smoke.4016572423 |
| Short name | T2350 |
| Test name | |
| Test status | |
| Simulation time | 193573882 ps |
| CPU time | 8.85 seconds |
| Started | Jun 28 08:39:31 PM PDT 24 |
| Finished | Jun 28 08:39:49 PM PDT 24 |
| Peak memory | 574192 kb |
| Host | smart-f164b3ac-6054-44ec-ad5d-a904a29b88f4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4016572423 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.xbar_smoke.4016572423 |
| Directory | /workspace/29.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/29.xbar_smoke_large_delays.3798728667 |
| Short name | T1356 |
| Test name | |
| Test status | |
| Simulation time | 8717612004 ps |
| CPU time | 87.83 seconds |
| Started | Jun 28 08:39:39 PM PDT 24 |
| Finished | Jun 28 08:41:13 PM PDT 24 |
| Peak memory | 566016 kb |
| Host | smart-751fbd2d-3f38-434c-a507-1ef7139248ff |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3798728667 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.xbar_smoke_large_delays.3798728667 |
| Directory | /workspace/29.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/29.xbar_smoke_slow_rsp.3007982185 |
| Short name | T1455 |
| Test name | |
| Test status | |
| Simulation time | 4524427508 ps |
| CPU time | 78.45 seconds |
| Started | Jun 28 08:39:33 PM PDT 24 |
| Finished | Jun 28 08:40:59 PM PDT 24 |
| Peak memory | 574072 kb |
| Host | smart-6f1f378c-245a-4b7d-a016-74de055fc6ca |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3007982185 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.xbar_smoke_slow_rsp.3007982185 |
| Directory | /workspace/29.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/29.xbar_smoke_zero_delays.3670838973 |
| Short name | T2230 |
| Test name | |
| Test status | |
| Simulation time | 54509612 ps |
| CPU time | 7.08 seconds |
| Started | Jun 28 08:39:37 PM PDT 24 |
| Finished | Jun 28 08:39:51 PM PDT 24 |
| Peak memory | 574176 kb |
| Host | smart-150c0e60-2252-4167-98b0-c082607ba1b5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3670838973 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.xbar_smoke_zero_delay s.3670838973 |
| Directory | /workspace/29.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/29.xbar_stress_all.1928568168 |
| Short name | T2006 |
| Test name | |
| Test status | |
| Simulation time | 5641458943 ps |
| CPU time | 217.49 seconds |
| Started | Jun 28 08:39:40 PM PDT 24 |
| Finished | Jun 28 08:43:23 PM PDT 24 |
| Peak memory | 574380 kb |
| Host | smart-7772c925-cf2e-4cf6-a2a7-53880dccf272 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1928568168 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.xbar_stress_all.1928568168 |
| Directory | /workspace/29.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/29.xbar_stress_all_with_rand_reset.279692475 |
| Short name | T1653 |
| Test name | |
| Test status | |
| Simulation time | 248568135 ps |
| CPU time | 84.2 seconds |
| Started | Jun 28 08:39:40 PM PDT 24 |
| Finished | Jun 28 08:41:10 PM PDT 24 |
| Peak memory | 575380 kb |
| Host | smart-6ce24ab1-2868-4a0f-a707-0e284db742e6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=279692475 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_res et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.xbar_stress_all_ with_rand_reset.279692475 |
| Directory | /workspace/29.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/29.xbar_stress_all_with_reset_error.1715639363 |
| Short name | T2402 |
| Test name | |
| Test status | |
| Simulation time | 159306904 ps |
| CPU time | 45.71 seconds |
| Started | Jun 28 08:39:36 PM PDT 24 |
| Finished | Jun 28 08:40:29 PM PDT 24 |
| Peak memory | 576324 kb |
| Host | smart-9fc9c12b-e04c-4daf-a712-31320c3c405a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1715639363 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.xbar_stress_al l_with_reset_error.1715639363 |
| Directory | /workspace/29.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/29.xbar_unmapped_addr.3675901934 |
| Short name | T2598 |
| Test name | |
| Test status | |
| Simulation time | 299307770 ps |
| CPU time | 15.7 seconds |
| Started | Jun 28 08:39:42 PM PDT 24 |
| Finished | Jun 28 08:40:03 PM PDT 24 |
| Peak memory | 575288 kb |
| Host | smart-912b5b4f-7af1-4cb1-bcf3-424698adf424 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3675901934 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.xbar_unmapped_addr.3675901934 |
| Directory | /workspace/29.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/3.chip_csr_bit_bash.200715597 |
| Short name | T389 |
| Test name | |
| Test status | |
| Simulation time | 8136979947 ps |
| CPU time | 1022.18 seconds |
| Started | Jun 28 08:29:36 PM PDT 24 |
| Finished | Jun 28 08:46:49 PM PDT 24 |
| Peak memory | 591068 kb |
| Host | smart-e41e0d11-134d-40b0-97c5-f2260d931765 |
| User | root |
| Command | /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +num_test_csrs=200 +csr_bit_bash +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=200715597 -assert nopostproc + UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top .vdb -cm_log /dev/null -cm_name 3.chip_csr_bit_bash.200715597 |
| Directory | /workspace/3.chip_csr_bit_bash/latest |
| Test location | /workspace/coverage/cover_reg_top/3.chip_csr_rw.2478436844 |
| Short name | T439 |
| Test name | |
| Test status | |
| Simulation time | 3727310982 ps |
| CPU time | 378.33 seconds |
| Started | Jun 28 08:30:15 PM PDT 24 |
| Finished | Jun 28 08:36:37 PM PDT 24 |
| Peak memory | 596252 kb |
| Host | smart-433b776e-0098-4904-8e1d-1bc6aef12073 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2478436844 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.chip_csr_rw.2478436844 |
| Directory | /workspace/3.chip_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/3.chip_same_csr_outstanding.2943456748 |
| Short name | T1943 |
| Test name | |
| Test status | |
| Simulation time | 15021982509 ps |
| CPU time | 1905.78 seconds |
| Started | Jun 28 08:29:43 PM PDT 24 |
| Finished | Jun 28 09:01:40 PM PDT 24 |
| Peak memory | 590856 kb |
| Host | smart-115a9f59-fff6-4104-b5eb-cf83c7d2e4f6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +run_same_csr_outstanding +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2943456748 -assert nopostproc +UVM_TE STNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb - cm_log /dev/null -cm_name 3.chip_same_csr_outstanding.2943456748 |
| Directory | /workspace/3.chip_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/3.chip_tl_errors.98659049 |
| Short name | T2399 |
| Test name | |
| Test status | |
| Simulation time | 2735516443 ps |
| CPU time | 96.28 seconds |
| Started | Jun 28 08:29:37 PM PDT 24 |
| Finished | Jun 28 08:31:24 PM PDT 24 |
| Peak memory | 603368 kb |
| Host | smart-8a64af41-6f4a-442e-b424-eca629dcd047 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98659049 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.chip_tl_errors.98659049 |
| Directory | /workspace/3.chip_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/3.xbar_access_same_device.2802547762 |
| Short name | T2838 |
| Test name | |
| Test status | |
| Simulation time | 1586796056 ps |
| CPU time | 76.97 seconds |
| Started | Jun 28 08:29:49 PM PDT 24 |
| Finished | Jun 28 08:31:16 PM PDT 24 |
| Peak memory | 574176 kb |
| Host | smart-49bd53de-85b6-4dee-99da-1dac87ffb5ce |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2802547762 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.xbar_access_same_device. 2802547762 |
| Directory | /workspace/3.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/3.xbar_access_same_device_slow_rsp.533660306 |
| Short name | T1576 |
| Test name | |
| Test status | |
| Simulation time | 4604620196 ps |
| CPU time | 88.81 seconds |
| Started | Jun 28 08:29:55 PM PDT 24 |
| Finished | Jun 28 08:31:36 PM PDT 24 |
| Peak memory | 574164 kb |
| Host | smart-d3d51a55-9ed6-4be6-9e56-3e8cda61e214 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=533660306 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.xbar_access_same_de vice_slow_rsp.533660306 |
| Directory | /workspace/3.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/3.xbar_error_and_unmapped_addr.1850504632 |
| Short name | T2635 |
| Test name | |
| Test status | |
| Simulation time | 257291657 ps |
| CPU time | 27.22 seconds |
| Started | Jun 28 08:30:07 PM PDT 24 |
| Finished | Jun 28 08:30:42 PM PDT 24 |
| Peak memory | 574440 kb |
| Host | smart-4659966d-22c0-42be-ad11-7e304bd36066 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1850504632 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.xbar_error_and_unmapped_addr .1850504632 |
| Directory | /workspace/3.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/3.xbar_error_random.264455002 |
| Short name | T1397 |
| Test name | |
| Test status | |
| Simulation time | 369396149 ps |
| CPU time | 16.41 seconds |
| Started | Jun 28 08:30:08 PM PDT 24 |
| Finished | Jun 28 08:30:31 PM PDT 24 |
| Peak memory | 573940 kb |
| Host | smart-7c0dc3cf-644d-49e1-b8c2-4493b8bc6252 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=264455002 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.xbar_error_random.264455002 |
| Directory | /workspace/3.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/3.xbar_random.1504497483 |
| Short name | T2389 |
| Test name | |
| Test status | |
| Simulation time | 546475731 ps |
| CPU time | 61.33 seconds |
| Started | Jun 28 08:29:59 PM PDT 24 |
| Finished | Jun 28 08:31:12 PM PDT 24 |
| Peak memory | 575280 kb |
| Host | smart-cab50056-1067-4dfb-a474-a3d9eb1e35e2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1504497483 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.xbar_random.1504497483 |
| Directory | /workspace/3.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/3.xbar_random_large_delays.3088812523 |
| Short name | T2609 |
| Test name | |
| Test status | |
| Simulation time | 15155180712 ps |
| CPU time | 168.35 seconds |
| Started | Jun 28 08:29:49 PM PDT 24 |
| Finished | Jun 28 08:32:49 PM PDT 24 |
| Peak memory | 574252 kb |
| Host | smart-7080e17d-1626-4874-91f7-2219995ae8e6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3088812523 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.xbar_random_large_delays.3088812523 |
| Directory | /workspace/3.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/3.xbar_random_slow_rsp.1442986404 |
| Short name | T1881 |
| Test name | |
| Test status | |
| Simulation time | 12575418636 ps |
| CPU time | 232.91 seconds |
| Started | Jun 28 08:30:10 PM PDT 24 |
| Finished | Jun 28 08:34:10 PM PDT 24 |
| Peak memory | 575296 kb |
| Host | smart-b49c9471-5c61-4fb0-ae86-992ba48aedf2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1442986404 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.xbar_random_slow_rsp.1442986404 |
| Directory | /workspace/3.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/3.xbar_random_zero_delays.2924281373 |
| Short name | T1977 |
| Test name | |
| Test status | |
| Simulation time | 594911058 ps |
| CPU time | 62.55 seconds |
| Started | Jun 28 08:29:51 PM PDT 24 |
| Finished | Jun 28 08:31:06 PM PDT 24 |
| Peak memory | 575288 kb |
| Host | smart-b186ec3c-0f4c-4213-afac-0a051b2c70ab |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2924281373 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.xbar_random_zero_dela ys.2924281373 |
| Directory | /workspace/3.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/3.xbar_same_source.2245128893 |
| Short name | T2434 |
| Test name | |
| Test status | |
| Simulation time | 564578693 ps |
| CPU time | 45.01 seconds |
| Started | Jun 28 08:30:16 PM PDT 24 |
| Finished | Jun 28 08:31:05 PM PDT 24 |
| Peak memory | 575228 kb |
| Host | smart-69862a53-1b46-482d-80a2-bde968c99e54 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2245128893 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.xbar_same_source.2245128893 |
| Directory | /workspace/3.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/3.xbar_smoke.3008227875 |
| Short name | T1449 |
| Test name | |
| Test status | |
| Simulation time | 213048412 ps |
| CPU time | 9.82 seconds |
| Started | Jun 28 08:29:50 PM PDT 24 |
| Finished | Jun 28 08:30:12 PM PDT 24 |
| Peak memory | 565860 kb |
| Host | smart-f06de6b7-2858-4d40-b295-5827c1acda25 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3008227875 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.xbar_smoke.3008227875 |
| Directory | /workspace/3.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/3.xbar_smoke_large_delays.2802283745 |
| Short name | T1640 |
| Test name | |
| Test status | |
| Simulation time | 7635566978 ps |
| CPU time | 82.4 seconds |
| Started | Jun 28 08:29:51 PM PDT 24 |
| Finished | Jun 28 08:31:26 PM PDT 24 |
| Peak memory | 574232 kb |
| Host | smart-58ea0180-9d2d-4980-9906-eacfd3b38922 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2802283745 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.xbar_smoke_large_delays.2802283745 |
| Directory | /workspace/3.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/3.xbar_smoke_slow_rsp.2014694831 |
| Short name | T1806 |
| Test name | |
| Test status | |
| Simulation time | 5255396030 ps |
| CPU time | 86.75 seconds |
| Started | Jun 28 08:30:05 PM PDT 24 |
| Finished | Jun 28 08:31:40 PM PDT 24 |
| Peak memory | 574240 kb |
| Host | smart-41402e87-7d6d-47d0-bb91-77a083385df7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2014694831 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.xbar_smoke_slow_rsp.2014694831 |
| Directory | /workspace/3.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/3.xbar_smoke_zero_delays.1713148889 |
| Short name | T1393 |
| Test name | |
| Test status | |
| Simulation time | 58892915 ps |
| CPU time | 8.27 seconds |
| Started | Jun 28 08:29:51 PM PDT 24 |
| Finished | Jun 28 08:30:11 PM PDT 24 |
| Peak memory | 574092 kb |
| Host | smart-aaebd11a-36a5-47de-825d-637fd82b44fd |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1713148889 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.xbar_smoke_zero_delays .1713148889 |
| Directory | /workspace/3.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/3.xbar_stress_all.473110554 |
| Short name | T1999 |
| Test name | |
| Test status | |
| Simulation time | 15756475331 ps |
| CPU time | 630.43 seconds |
| Started | Jun 28 08:30:15 PM PDT 24 |
| Finished | Jun 28 08:40:50 PM PDT 24 |
| Peak memory | 575448 kb |
| Host | smart-1931f5fd-841b-4e7e-b55e-25da9c29dcb9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=473110554 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.xbar_stress_all.473110554 |
| Directory | /workspace/3.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/3.xbar_stress_all_with_error.545748664 |
| Short name | T794 |
| Test name | |
| Test status | |
| Simulation time | 12778935468 ps |
| CPU time | 460.15 seconds |
| Started | Jun 28 08:30:04 PM PDT 24 |
| Finished | Jun 28 08:37:53 PM PDT 24 |
| Peak memory | 574648 kb |
| Host | smart-9a2763e7-04a7-446e-ad7a-df526c48259a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=545748664 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.xbar_stress_all_with_error.545748664 |
| Directory | /workspace/3.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/3.xbar_stress_all_with_reset_error.1119558564 |
| Short name | T2135 |
| Test name | |
| Test status | |
| Simulation time | 7564831 ps |
| CPU time | 4.05 seconds |
| Started | Jun 28 08:30:04 PM PDT 24 |
| Finished | Jun 28 08:30:17 PM PDT 24 |
| Peak memory | 565740 kb |
| Host | smart-02b32557-c4cf-4e2b-9988-818653603e9a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1119558564 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.xbar_stress_all _with_reset_error.1119558564 |
| Directory | /workspace/3.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/3.xbar_unmapped_addr.3558556849 |
| Short name | T2681 |
| Test name | |
| Test status | |
| Simulation time | 86717580 ps |
| CPU time | 7.08 seconds |
| Started | Jun 28 08:30:06 PM PDT 24 |
| Finished | Jun 28 08:30:21 PM PDT 24 |
| Peak memory | 574084 kb |
| Host | smart-99f2a1df-8fee-4166-aaea-588378cd0304 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3558556849 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.xbar_unmapped_addr.3558556849 |
| Directory | /workspace/3.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/30.xbar_access_same_device.1939492590 |
| Short name | T1780 |
| Test name | |
| Test status | |
| Simulation time | 391604066 ps |
| CPU time | 42.52 seconds |
| Started | Jun 28 08:39:47 PM PDT 24 |
| Finished | Jun 28 08:40:33 PM PDT 24 |
| Peak memory | 575220 kb |
| Host | smart-0a554216-057e-474d-a91e-cef5b60b730c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1939492590 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.xbar_access_same_device .1939492590 |
| Directory | /workspace/30.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/30.xbar_access_same_device_slow_rsp.347424944 |
| Short name | T792 |
| Test name | |
| Test status | |
| Simulation time | 62514412376 ps |
| CPU time | 1178.58 seconds |
| Started | Jun 28 08:39:45 PM PDT 24 |
| Finished | Jun 28 08:59:28 PM PDT 24 |
| Peak memory | 575408 kb |
| Host | smart-c2d887a8-41ca-4fe6-86b4-5a279b77ad21 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=347424944 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.xbar_access_same_d evice_slow_rsp.347424944 |
| Directory | /workspace/30.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/30.xbar_error_and_unmapped_addr.1531691656 |
| Short name | T1532 |
| Test name | |
| Test status | |
| Simulation time | 826955466 ps |
| CPU time | 34.99 seconds |
| Started | Jun 28 08:39:47 PM PDT 24 |
| Finished | Jun 28 08:40:26 PM PDT 24 |
| Peak memory | 573852 kb |
| Host | smart-5883a5c8-7a1c-4515-805d-0c633462773c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1531691656 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.xbar_error_and_unmapped_add r.1531691656 |
| Directory | /workspace/30.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/30.xbar_error_random.2639147061 |
| Short name | T2455 |
| Test name | |
| Test status | |
| Simulation time | 2256296399 ps |
| CPU time | 91.21 seconds |
| Started | Jun 28 08:39:45 PM PDT 24 |
| Finished | Jun 28 08:41:21 PM PDT 24 |
| Peak memory | 574472 kb |
| Host | smart-efd62ce3-4087-4886-8300-7bc73e7b0bfd |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2639147061 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.xbar_error_random.2639147061 |
| Directory | /workspace/30.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/30.xbar_random.4076734903 |
| Short name | T2212 |
| Test name | |
| Test status | |
| Simulation time | 1305139866 ps |
| CPU time | 50.72 seconds |
| Started | Jun 28 08:39:46 PM PDT 24 |
| Finished | Jun 28 08:40:40 PM PDT 24 |
| Peak memory | 575232 kb |
| Host | smart-f156d15b-0432-4bd5-987d-69a9afca7e36 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4076734903 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.xbar_random.4076734903 |
| Directory | /workspace/30.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/30.xbar_random_large_delays.1567586149 |
| Short name | T2118 |
| Test name | |
| Test status | |
| Simulation time | 26374353407 ps |
| CPU time | 294.3 seconds |
| Started | Jun 28 08:39:50 PM PDT 24 |
| Finished | Jun 28 08:44:47 PM PDT 24 |
| Peak memory | 574236 kb |
| Host | smart-cc4024fd-5ea3-4956-8c0f-04fd6228bf79 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1567586149 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.xbar_random_large_delays.1567586149 |
| Directory | /workspace/30.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/30.xbar_random_slow_rsp.2834310158 |
| Short name | T2413 |
| Test name | |
| Test status | |
| Simulation time | 32754061658 ps |
| CPU time | 596.36 seconds |
| Started | Jun 28 08:39:45 PM PDT 24 |
| Finished | Jun 28 08:49:45 PM PDT 24 |
| Peak memory | 574240 kb |
| Host | smart-61f8492d-3791-4d6d-b558-5e4b999f61fd |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2834310158 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.xbar_random_slow_rsp.2834310158 |
| Directory | /workspace/30.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/30.xbar_random_zero_delays.3451587482 |
| Short name | T523 |
| Test name | |
| Test status | |
| Simulation time | 287453131 ps |
| CPU time | 31.03 seconds |
| Started | Jun 28 08:39:46 PM PDT 24 |
| Finished | Jun 28 08:40:21 PM PDT 24 |
| Peak memory | 575228 kb |
| Host | smart-d0daf01d-4fc0-43c7-8eba-74b9aa8a1bb5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3451587482 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.xbar_random_zero_del ays.3451587482 |
| Directory | /workspace/30.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/30.xbar_same_source.3044988505 |
| Short name | T2262 |
| Test name | |
| Test status | |
| Simulation time | 586708756 ps |
| CPU time | 20.25 seconds |
| Started | Jun 28 08:39:50 PM PDT 24 |
| Finished | Jun 28 08:40:14 PM PDT 24 |
| Peak memory | 575228 kb |
| Host | smart-98a2741d-201c-4eeb-84e1-7d7135ef3d54 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3044988505 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.xbar_same_source.3044988505 |
| Directory | /workspace/30.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/30.xbar_smoke.2908493810 |
| Short name | T1457 |
| Test name | |
| Test status | |
| Simulation time | 213102726 ps |
| CPU time | 9.55 seconds |
| Started | Jun 28 08:39:36 PM PDT 24 |
| Finished | Jun 28 08:39:53 PM PDT 24 |
| Peak memory | 565872 kb |
| Host | smart-a26122d3-51c0-4f3c-a555-3da83407ad30 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2908493810 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.xbar_smoke.2908493810 |
| Directory | /workspace/30.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/30.xbar_smoke_large_delays.1441218494 |
| Short name | T578 |
| Test name | |
| Test status | |
| Simulation time | 9086583625 ps |
| CPU time | 92.02 seconds |
| Started | Jun 28 08:39:40 PM PDT 24 |
| Finished | Jun 28 08:41:18 PM PDT 24 |
| Peak memory | 566016 kb |
| Host | smart-e0b8caa9-38e7-4518-941c-5bbf1515fcea |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1441218494 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.xbar_smoke_large_delays.1441218494 |
| Directory | /workspace/30.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/30.xbar_smoke_slow_rsp.2985709523 |
| Short name | T2573 |
| Test name | |
| Test status | |
| Simulation time | 5665432874 ps |
| CPU time | 90.21 seconds |
| Started | Jun 28 08:39:41 PM PDT 24 |
| Finished | Jun 28 08:41:16 PM PDT 24 |
| Peak memory | 574076 kb |
| Host | smart-be56eac7-df6b-4265-ad12-eb0b1b9e1f78 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2985709523 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.xbar_smoke_slow_rsp.2985709523 |
| Directory | /workspace/30.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/30.xbar_smoke_zero_delays.9244856 |
| Short name | T1966 |
| Test name | |
| Test status | |
| Simulation time | 45223899 ps |
| CPU time | 7.08 seconds |
| Started | Jun 28 08:39:38 PM PDT 24 |
| Finished | Jun 28 08:39:52 PM PDT 24 |
| Peak memory | 574188 kb |
| Host | smart-235e7ad4-ed81-489b-9d1b-c7d9acfc462d |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=9244856 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.xbar_smoke_zero_delays.9244856 |
| Directory | /workspace/30.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/30.xbar_stress_all.2222726039 |
| Short name | T2449 |
| Test name | |
| Test status | |
| Simulation time | 1664045612 ps |
| CPU time | 121.67 seconds |
| Started | Jun 28 08:39:49 PM PDT 24 |
| Finished | Jun 28 08:41:54 PM PDT 24 |
| Peak memory | 575364 kb |
| Host | smart-53e4859e-2b97-4ae0-9b08-2a5e4c9913f9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2222726039 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.xbar_stress_all.2222726039 |
| Directory | /workspace/30.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/30.xbar_stress_all_with_error.3763950632 |
| Short name | T1970 |
| Test name | |
| Test status | |
| Simulation time | 141013236 ps |
| CPU time | 12.07 seconds |
| Started | Jun 28 08:39:46 PM PDT 24 |
| Finished | Jun 28 08:40:02 PM PDT 24 |
| Peak memory | 573748 kb |
| Host | smart-0de0222e-d722-4d49-899b-e1bf30a5d448 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3763950632 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.xbar_stress_all_with_error.3763950632 |
| Directory | /workspace/30.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/30.xbar_stress_all_with_rand_reset.3775919521 |
| Short name | T467 |
| Test name | |
| Test status | |
| Simulation time | 3585850882 ps |
| CPU time | 576.14 seconds |
| Started | Jun 28 08:39:44 PM PDT 24 |
| Finished | Jun 28 08:49:25 PM PDT 24 |
| Peak memory | 574316 kb |
| Host | smart-0ef67d68-85cb-456d-a606-785e6a48ebae |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3775919521 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.xbar_stress_all _with_rand_reset.3775919521 |
| Directory | /workspace/30.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/30.xbar_stress_all_with_reset_error.3777102955 |
| Short name | T1888 |
| Test name | |
| Test status | |
| Simulation time | 525833908 ps |
| CPU time | 170.8 seconds |
| Started | Jun 28 08:39:47 PM PDT 24 |
| Finished | Jun 28 08:42:41 PM PDT 24 |
| Peak memory | 574620 kb |
| Host | smart-37447d05-ada9-47b5-8467-165b9eca18a3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3777102955 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.xbar_stress_al l_with_reset_error.3777102955 |
| Directory | /workspace/30.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/30.xbar_unmapped_addr.998593095 |
| Short name | T619 |
| Test name | |
| Test status | |
| Simulation time | 1265343951 ps |
| CPU time | 54.3 seconds |
| Started | Jun 28 08:39:49 PM PDT 24 |
| Finished | Jun 28 08:40:47 PM PDT 24 |
| Peak memory | 575288 kb |
| Host | smart-3524e9dd-4bc4-4465-b31d-2a11ff61ea27 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=998593095 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.xbar_unmapped_addr.998593095 |
| Directory | /workspace/30.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/31.xbar_access_same_device_slow_rsp.190642572 |
| Short name | T2279 |
| Test name | |
| Test status | |
| Simulation time | 19350850015 ps |
| CPU time | 340.86 seconds |
| Started | Jun 28 08:40:08 PM PDT 24 |
| Finished | Jun 28 08:46:00 PM PDT 24 |
| Peak memory | 575288 kb |
| Host | smart-e3566c27-1d7a-490f-84e5-a0745893c973 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=190642572 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.xbar_access_same_d evice_slow_rsp.190642572 |
| Directory | /workspace/31.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/31.xbar_error_and_unmapped_addr.1368859901 |
| Short name | T1906 |
| Test name | |
| Test status | |
| Simulation time | 337082457 ps |
| CPU time | 36.54 seconds |
| Started | Jun 28 08:40:08 PM PDT 24 |
| Finished | Jun 28 08:40:55 PM PDT 24 |
| Peak memory | 574132 kb |
| Host | smart-e5dc8d9b-fab7-4fb5-a56a-d63f11efde60 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1368859901 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.xbar_error_and_unmapped_add r.1368859901 |
| Directory | /workspace/31.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/31.xbar_error_random.536472905 |
| Short name | T2282 |
| Test name | |
| Test status | |
| Simulation time | 1911786540 ps |
| CPU time | 70.86 seconds |
| Started | Jun 28 08:40:08 PM PDT 24 |
| Finished | Jun 28 08:41:30 PM PDT 24 |
| Peak memory | 574208 kb |
| Host | smart-cf25af8f-5be1-44b1-b4ce-f507e03f0e32 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=536472905 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.xbar_error_random.536472905 |
| Directory | /workspace/31.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/31.xbar_random.727563030 |
| Short name | T2645 |
| Test name | |
| Test status | |
| Simulation time | 1171438869 ps |
| CPU time | 45.28 seconds |
| Started | Jun 28 08:39:48 PM PDT 24 |
| Finished | Jun 28 08:40:37 PM PDT 24 |
| Peak memory | 575224 kb |
| Host | smart-23499bdd-5db3-4b60-a403-e32e281cd350 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=727563030 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.xbar_random.727563030 |
| Directory | /workspace/31.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/31.xbar_random_large_delays.1346555679 |
| Short name | T1808 |
| Test name | |
| Test status | |
| Simulation time | 99867771516 ps |
| CPU time | 990.21 seconds |
| Started | Jun 28 08:39:47 PM PDT 24 |
| Finished | Jun 28 08:56:21 PM PDT 24 |
| Peak memory | 574292 kb |
| Host | smart-dc585ee8-ea62-4e6b-aedd-01e448ddbb41 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1346555679 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.xbar_random_large_delays.1346555679 |
| Directory | /workspace/31.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/31.xbar_random_slow_rsp.1656240647 |
| Short name | T2857 |
| Test name | |
| Test status | |
| Simulation time | 52884968017 ps |
| CPU time | 903.71 seconds |
| Started | Jun 28 08:39:50 PM PDT 24 |
| Finished | Jun 28 08:54:57 PM PDT 24 |
| Peak memory | 575308 kb |
| Host | smart-56021173-be6f-4808-8df5-5f2cea0f968c |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1656240647 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.xbar_random_slow_rsp.1656240647 |
| Directory | /workspace/31.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/31.xbar_random_zero_delays.1588732013 |
| Short name | T235 |
| Test name | |
| Test status | |
| Simulation time | 73371293 ps |
| CPU time | 10.3 seconds |
| Started | Jun 28 08:39:49 PM PDT 24 |
| Finished | Jun 28 08:40:03 PM PDT 24 |
| Peak memory | 575228 kb |
| Host | smart-9ff9f9b8-9a4d-4afe-b77d-2a6c4a0a5fe7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1588732013 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.xbar_random_zero_del ays.1588732013 |
| Directory | /workspace/31.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/31.xbar_same_source.792405917 |
| Short name | T2351 |
| Test name | |
| Test status | |
| Simulation time | 2752273643 ps |
| CPU time | 82.99 seconds |
| Started | Jun 28 08:40:05 PM PDT 24 |
| Finished | Jun 28 08:41:39 PM PDT 24 |
| Peak memory | 574244 kb |
| Host | smart-9484bdaa-c03c-4753-84ef-69d31a3508cd |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=792405917 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.xbar_same_source.792405917 |
| Directory | /workspace/31.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/31.xbar_smoke.3904021640 |
| Short name | T2179 |
| Test name | |
| Test status | |
| Simulation time | 37835104 ps |
| CPU time | 6.2 seconds |
| Started | Jun 28 08:39:43 PM PDT 24 |
| Finished | Jun 28 08:39:54 PM PDT 24 |
| Peak memory | 565760 kb |
| Host | smart-946de93d-bf15-4a41-9d80-e728f129a303 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3904021640 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.xbar_smoke.3904021640 |
| Directory | /workspace/31.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/31.xbar_smoke_large_delays.951140637 |
| Short name | T1363 |
| Test name | |
| Test status | |
| Simulation time | 8769277873 ps |
| CPU time | 98.14 seconds |
| Started | Jun 28 08:39:45 PM PDT 24 |
| Finished | Jun 28 08:41:28 PM PDT 24 |
| Peak memory | 574252 kb |
| Host | smart-0234083f-85c2-4fc7-9831-6f024121eae4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=951140637 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.xbar_smoke_large_delays.951140637 |
| Directory | /workspace/31.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/31.xbar_smoke_slow_rsp.1232078009 |
| Short name | T1570 |
| Test name | |
| Test status | |
| Simulation time | 5155411208 ps |
| CPU time | 90.58 seconds |
| Started | Jun 28 08:39:48 PM PDT 24 |
| Finished | Jun 28 08:41:22 PM PDT 24 |
| Peak memory | 566012 kb |
| Host | smart-72b348b3-d824-48a3-8b82-da74a4935108 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1232078009 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.xbar_smoke_slow_rsp.1232078009 |
| Directory | /workspace/31.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/31.xbar_smoke_zero_delays.1503490570 |
| Short name | T605 |
| Test name | |
| Test status | |
| Simulation time | 46293422 ps |
| CPU time | 6.37 seconds |
| Started | Jun 28 08:39:49 PM PDT 24 |
| Finished | Jun 28 08:39:59 PM PDT 24 |
| Peak memory | 574180 kb |
| Host | smart-5764ed80-554e-48b4-84df-38662eed918d |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1503490570 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.xbar_smoke_zero_delay s.1503490570 |
| Directory | /workspace/31.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/31.xbar_stress_all.627621567 |
| Short name | T2175 |
| Test name | |
| Test status | |
| Simulation time | 5801713625 ps |
| CPU time | 214.68 seconds |
| Started | Jun 28 08:40:09 PM PDT 24 |
| Finished | Jun 28 08:43:54 PM PDT 24 |
| Peak memory | 575440 kb |
| Host | smart-eed37e51-c0c6-4863-904b-8007bc5c31fc |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=627621567 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.xbar_stress_all.627621567 |
| Directory | /workspace/31.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/31.xbar_stress_all_with_error.3555168324 |
| Short name | T1638 |
| Test name | |
| Test status | |
| Simulation time | 18502510020 ps |
| CPU time | 632.76 seconds |
| Started | Jun 28 08:40:09 PM PDT 24 |
| Finished | Jun 28 08:50:53 PM PDT 24 |
| Peak memory | 574416 kb |
| Host | smart-e0c38117-1642-4d43-b7d2-5291ccd54725 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3555168324 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.xbar_stress_all_with_error.3555168324 |
| Directory | /workspace/31.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/31.xbar_stress_all_with_rand_reset.1971694456 |
| Short name | T2784 |
| Test name | |
| Test status | |
| Simulation time | 8813880580 ps |
| CPU time | 625.88 seconds |
| Started | Jun 28 08:40:06 PM PDT 24 |
| Finished | Jun 28 08:50:42 PM PDT 24 |
| Peak memory | 575424 kb |
| Host | smart-0fcc79a0-253d-435f-a10e-68615cc87e69 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1971694456 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.xbar_stress_all _with_rand_reset.1971694456 |
| Directory | /workspace/31.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/31.xbar_stress_all_with_reset_error.2815858067 |
| Short name | T2619 |
| Test name | |
| Test status | |
| Simulation time | 5705788590 ps |
| CPU time | 292.88 seconds |
| Started | Jun 28 08:40:08 PM PDT 24 |
| Finished | Jun 28 08:45:12 PM PDT 24 |
| Peak memory | 576428 kb |
| Host | smart-ea747c30-f26b-4b14-bc76-fe4e2486c3b4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2815858067 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.xbar_stress_al l_with_reset_error.2815858067 |
| Directory | /workspace/31.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/31.xbar_unmapped_addr.1785178139 |
| Short name | T1499 |
| Test name | |
| Test status | |
| Simulation time | 241060533 ps |
| CPU time | 35.25 seconds |
| Started | Jun 28 08:40:04 PM PDT 24 |
| Finished | Jun 28 08:40:50 PM PDT 24 |
| Peak memory | 574256 kb |
| Host | smart-6b22fefd-6110-4fd3-9851-3c62ac04a216 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1785178139 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.xbar_unmapped_addr.1785178139 |
| Directory | /workspace/31.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/32.xbar_access_same_device.3498579939 |
| Short name | T2700 |
| Test name | |
| Test status | |
| Simulation time | 3191419597 ps |
| CPU time | 155.51 seconds |
| Started | Jun 28 08:40:13 PM PDT 24 |
| Finished | Jun 28 08:42:58 PM PDT 24 |
| Peak memory | 575360 kb |
| Host | smart-5bf21cb2-7ede-49ae-9aa9-714c6dc8726e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3498579939 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.xbar_access_same_device .3498579939 |
| Directory | /workspace/32.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/32.xbar_access_same_device_slow_rsp.3447646914 |
| Short name | T1933 |
| Test name | |
| Test status | |
| Simulation time | 38874300279 ps |
| CPU time | 727.62 seconds |
| Started | Jun 28 08:40:04 PM PDT 24 |
| Finished | Jun 28 08:52:23 PM PDT 24 |
| Peak memory | 574280 kb |
| Host | smart-ddc49c56-0fdd-4eda-9c68-e3be5299fec0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3447646914 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.xbar_access_same_ device_slow_rsp.3447646914 |
| Directory | /workspace/32.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/32.xbar_error_and_unmapped_addr.529875535 |
| Short name | T2582 |
| Test name | |
| Test status | |
| Simulation time | 64582116 ps |
| CPU time | 9.96 seconds |
| Started | Jun 28 08:40:08 PM PDT 24 |
| Finished | Jun 28 08:40:29 PM PDT 24 |
| Peak memory | 573856 kb |
| Host | smart-4f36d7f5-7d24-49e5-876b-1f80faa8d59f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=529875535 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.xbar_error_and_unmapped_addr .529875535 |
| Directory | /workspace/32.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/32.xbar_error_random.2466787274 |
| Short name | T2600 |
| Test name | |
| Test status | |
| Simulation time | 2176124783 ps |
| CPU time | 88.19 seconds |
| Started | Jun 28 08:40:05 PM PDT 24 |
| Finished | Jun 28 08:41:44 PM PDT 24 |
| Peak memory | 573880 kb |
| Host | smart-9986b218-2383-45ed-90e0-a680b6da7959 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2466787274 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.xbar_error_random.2466787274 |
| Directory | /workspace/32.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/32.xbar_random.398532382 |
| Short name | T1802 |
| Test name | |
| Test status | |
| Simulation time | 461460037 ps |
| CPU time | 19.6 seconds |
| Started | Jun 28 08:40:10 PM PDT 24 |
| Finished | Jun 28 08:40:40 PM PDT 24 |
| Peak memory | 575244 kb |
| Host | smart-278facf0-e14f-48bc-92f8-76b655ba2355 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=398532382 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.xbar_random.398532382 |
| Directory | /workspace/32.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/32.xbar_random_large_delays.401942641 |
| Short name | T1408 |
| Test name | |
| Test status | |
| Simulation time | 35867297955 ps |
| CPU time | 377.49 seconds |
| Started | Jun 28 08:40:05 PM PDT 24 |
| Finished | Jun 28 08:46:33 PM PDT 24 |
| Peak memory | 575308 kb |
| Host | smart-cf1a41a4-d6a0-46da-a3a2-c7e4f777d44c |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=401942641 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.xbar_random_large_delays.401942641 |
| Directory | /workspace/32.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/32.xbar_random_slow_rsp.2098783922 |
| Short name | T2016 |
| Test name | |
| Test status | |
| Simulation time | 20616914311 ps |
| CPU time | 342.04 seconds |
| Started | Jun 28 08:40:05 PM PDT 24 |
| Finished | Jun 28 08:45:58 PM PDT 24 |
| Peak memory | 574268 kb |
| Host | smart-4d3ab89c-0842-4b9a-bf17-adc04720b2ec |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2098783922 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.xbar_random_slow_rsp.2098783922 |
| Directory | /workspace/32.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/32.xbar_random_zero_delays.3825877856 |
| Short name | T1374 |
| Test name | |
| Test status | |
| Simulation time | 234366602 ps |
| CPU time | 26.73 seconds |
| Started | Jun 28 08:40:06 PM PDT 24 |
| Finished | Jun 28 08:40:44 PM PDT 24 |
| Peak memory | 574160 kb |
| Host | smart-470c5d85-ccc8-4c33-a60b-4210f366d3a5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3825877856 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.xbar_random_zero_del ays.3825877856 |
| Directory | /workspace/32.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/32.xbar_same_source.750090051 |
| Short name | T1591 |
| Test name | |
| Test status | |
| Simulation time | 2193310954 ps |
| CPU time | 71.99 seconds |
| Started | Jun 28 08:40:08 PM PDT 24 |
| Finished | Jun 28 08:41:31 PM PDT 24 |
| Peak memory | 574176 kb |
| Host | smart-58afa088-4db6-4081-96be-625f74d09484 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=750090051 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.xbar_same_source.750090051 |
| Directory | /workspace/32.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/32.xbar_smoke.965727533 |
| Short name | T2537 |
| Test name | |
| Test status | |
| Simulation time | 176034265 ps |
| CPU time | 8.74 seconds |
| Started | Jun 28 08:40:13 PM PDT 24 |
| Finished | Jun 28 08:40:31 PM PDT 24 |
| Peak memory | 574184 kb |
| Host | smart-8405167d-9ab0-4d2e-b7a7-73a7485a99a6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=965727533 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.xbar_smoke.965727533 |
| Directory | /workspace/32.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/32.xbar_smoke_large_delays.1284346281 |
| Short name | T1493 |
| Test name | |
| Test status | |
| Simulation time | 7078145594 ps |
| CPU time | 75.44 seconds |
| Started | Jun 28 08:40:06 PM PDT 24 |
| Finished | Jun 28 08:41:33 PM PDT 24 |
| Peak memory | 574260 kb |
| Host | smart-a432ccf3-0626-4466-a9bd-31d2c5ee5ad4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1284346281 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.xbar_smoke_large_delays.1284346281 |
| Directory | /workspace/32.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/32.xbar_smoke_slow_rsp.460415871 |
| Short name | T2871 |
| Test name | |
| Test status | |
| Simulation time | 4628681042 ps |
| CPU time | 79.94 seconds |
| Started | Jun 28 08:40:08 PM PDT 24 |
| Finished | Jun 28 08:41:39 PM PDT 24 |
| Peak memory | 574068 kb |
| Host | smart-132649aa-b74e-4081-86b6-d8c4c8b253ac |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=460415871 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.xbar_smoke_slow_rsp.460415871 |
| Directory | /workspace/32.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/32.xbar_smoke_zero_delays.3313294916 |
| Short name | T2460 |
| Test name | |
| Test status | |
| Simulation time | 44034206 ps |
| CPU time | 6.32 seconds |
| Started | Jun 28 08:40:06 PM PDT 24 |
| Finished | Jun 28 08:40:24 PM PDT 24 |
| Peak memory | 574180 kb |
| Host | smart-9d99d616-3d06-4648-8142-5756a869f642 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3313294916 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.xbar_smoke_zero_delay s.3313294916 |
| Directory | /workspace/32.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/32.xbar_stress_all.2954894252 |
| Short name | T2060 |
| Test name | |
| Test status | |
| Simulation time | 1074704825 ps |
| CPU time | 43.29 seconds |
| Started | Jun 28 08:40:07 PM PDT 24 |
| Finished | Jun 28 08:41:01 PM PDT 24 |
| Peak memory | 574216 kb |
| Host | smart-59adeae9-0b9b-4830-bf57-a9cd0ae35051 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2954894252 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.xbar_stress_all.2954894252 |
| Directory | /workspace/32.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/32.xbar_stress_all_with_error.4140490691 |
| Short name | T2543 |
| Test name | |
| Test status | |
| Simulation time | 8222863936 ps |
| CPU time | 329.41 seconds |
| Started | Jun 28 08:40:09 PM PDT 24 |
| Finished | Jun 28 08:45:49 PM PDT 24 |
| Peak memory | 574668 kb |
| Host | smart-4332f491-57c5-4883-b4cf-5de158b8acdd |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4140490691 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.xbar_stress_all_with_error.4140490691 |
| Directory | /workspace/32.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/32.xbar_stress_all_with_rand_reset.686233258 |
| Short name | T1924 |
| Test name | |
| Test status | |
| Simulation time | 13876093019 ps |
| CPU time | 884.19 seconds |
| Started | Jun 28 08:40:08 PM PDT 24 |
| Finished | Jun 28 08:55:03 PM PDT 24 |
| Peak memory | 575388 kb |
| Host | smart-38b49499-ddc7-4618-bf73-4d0181616c70 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=686233258 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_res et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.xbar_stress_all_ with_rand_reset.686233258 |
| Directory | /workspace/32.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/32.xbar_stress_all_with_reset_error.3476324758 |
| Short name | T2752 |
| Test name | |
| Test status | |
| Simulation time | 5861652503 ps |
| CPU time | 454.88 seconds |
| Started | Jun 28 08:40:06 PM PDT 24 |
| Finished | Jun 28 08:47:51 PM PDT 24 |
| Peak memory | 576452 kb |
| Host | smart-38dea390-85e0-49ab-91be-54a1ce1fa8ac |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3476324758 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.xbar_stress_al l_with_reset_error.3476324758 |
| Directory | /workspace/32.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/32.xbar_unmapped_addr.343539329 |
| Short name | T624 |
| Test name | |
| Test status | |
| Simulation time | 346426633 ps |
| CPU time | 44.27 seconds |
| Started | Jun 28 08:40:08 PM PDT 24 |
| Finished | Jun 28 08:41:03 PM PDT 24 |
| Peak memory | 575268 kb |
| Host | smart-fe5d215b-bb11-40f3-9470-b4bd66a0432d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=343539329 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.xbar_unmapped_addr.343539329 |
| Directory | /workspace/32.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/33.xbar_access_same_device.2987172825 |
| Short name | T2665 |
| Test name | |
| Test status | |
| Simulation time | 678997060 ps |
| CPU time | 47.6 seconds |
| Started | Jun 28 08:40:06 PM PDT 24 |
| Finished | Jun 28 08:41:04 PM PDT 24 |
| Peak memory | 574196 kb |
| Host | smart-7a86c54f-cb84-4534-807c-7d694d770ff6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2987172825 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.xbar_access_same_device .2987172825 |
| Directory | /workspace/33.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/33.xbar_access_same_device_slow_rsp.2111086809 |
| Short name | T2759 |
| Test name | |
| Test status | |
| Simulation time | 44047676889 ps |
| CPU time | 755.77 seconds |
| Started | Jun 28 08:40:13 PM PDT 24 |
| Finished | Jun 28 08:52:58 PM PDT 24 |
| Peak memory | 575356 kb |
| Host | smart-e2bd0b0e-c485-49f5-8890-6e1ec40e5aa9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2111086809 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.xbar_access_same_ device_slow_rsp.2111086809 |
| Directory | /workspace/33.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/33.xbar_error_and_unmapped_addr.3260130353 |
| Short name | T1504 |
| Test name | |
| Test status | |
| Simulation time | 330312215 ps |
| CPU time | 37.03 seconds |
| Started | Jun 28 08:40:24 PM PDT 24 |
| Finished | Jun 28 08:41:05 PM PDT 24 |
| Peak memory | 574216 kb |
| Host | smart-c76a383d-1a16-477a-ab78-2b601e352271 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3260130353 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.xbar_error_and_unmapped_add r.3260130353 |
| Directory | /workspace/33.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/33.xbar_error_random.3250230946 |
| Short name | T2688 |
| Test name | |
| Test status | |
| Simulation time | 1367695112 ps |
| CPU time | 47.39 seconds |
| Started | Jun 28 08:40:21 PM PDT 24 |
| Finished | Jun 28 08:41:13 PM PDT 24 |
| Peak memory | 574424 kb |
| Host | smart-13da2817-d727-43c6-9964-4d922af5fdfd |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3250230946 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.xbar_error_random.3250230946 |
| Directory | /workspace/33.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/33.xbar_random.512761477 |
| Short name | T1682 |
| Test name | |
| Test status | |
| Simulation time | 2214469731 ps |
| CPU time | 79.94 seconds |
| Started | Jun 28 08:40:07 PM PDT 24 |
| Finished | Jun 28 08:41:37 PM PDT 24 |
| Peak memory | 572720 kb |
| Host | smart-02d42dae-026d-4b59-8057-1c6f4da61466 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=512761477 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.xbar_random.512761477 |
| Directory | /workspace/33.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/33.xbar_random_large_delays.136864327 |
| Short name | T1399 |
| Test name | |
| Test status | |
| Simulation time | 27494778197 ps |
| CPU time | 310.51 seconds |
| Started | Jun 28 08:40:07 PM PDT 24 |
| Finished | Jun 28 08:45:28 PM PDT 24 |
| Peak memory | 575468 kb |
| Host | smart-918b0541-5dab-4b47-9603-c60cdbfbc26e |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=136864327 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.xbar_random_large_delays.136864327 |
| Directory | /workspace/33.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/33.xbar_random_slow_rsp.2870980317 |
| Short name | T574 |
| Test name | |
| Test status | |
| Simulation time | 74168166887 ps |
| CPU time | 1228.55 seconds |
| Started | Jun 28 08:40:07 PM PDT 24 |
| Finished | Jun 28 09:00:47 PM PDT 24 |
| Peak memory | 574300 kb |
| Host | smart-9cc7a58c-7a59-449d-b1d8-38eec7cc5cd6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2870980317 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.xbar_random_slow_rsp.2870980317 |
| Directory | /workspace/33.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/33.xbar_random_zero_delays.2352848019 |
| Short name | T2007 |
| Test name | |
| Test status | |
| Simulation time | 221959091 ps |
| CPU time | 25.86 seconds |
| Started | Jun 28 08:40:04 PM PDT 24 |
| Finished | Jun 28 08:40:41 PM PDT 24 |
| Peak memory | 574176 kb |
| Host | smart-44e440f8-7541-447a-8e32-da80944533c5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2352848019 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.xbar_random_zero_del ays.2352848019 |
| Directory | /workspace/33.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/33.xbar_same_source.322806244 |
| Short name | T1369 |
| Test name | |
| Test status | |
| Simulation time | 611614961 ps |
| CPU time | 19.17 seconds |
| Started | Jun 28 08:40:07 PM PDT 24 |
| Finished | Jun 28 08:40:37 PM PDT 24 |
| Peak memory | 573764 kb |
| Host | smart-f8c27b41-1788-4526-867d-f0334a395d03 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=322806244 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.xbar_same_source.322806244 |
| Directory | /workspace/33.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/33.xbar_smoke.2399332115 |
| Short name | T1986 |
| Test name | |
| Test status | |
| Simulation time | 195205306 ps |
| CPU time | 9.22 seconds |
| Started | Jun 28 08:40:10 PM PDT 24 |
| Finished | Jun 28 08:40:30 PM PDT 24 |
| Peak memory | 565936 kb |
| Host | smart-6ccd0927-4d36-4b73-8244-4c325854bd06 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2399332115 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.xbar_smoke.2399332115 |
| Directory | /workspace/33.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/33.xbar_smoke_large_delays.4141319494 |
| Short name | T493 |
| Test name | |
| Test status | |
| Simulation time | 8628799927 ps |
| CPU time | 85.46 seconds |
| Started | Jun 28 08:40:09 PM PDT 24 |
| Finished | Jun 28 08:41:45 PM PDT 24 |
| Peak memory | 566016 kb |
| Host | smart-014b5111-2aa5-4c4e-98d1-551db34a4bf3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4141319494 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.xbar_smoke_large_delays.4141319494 |
| Directory | /workspace/33.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/33.xbar_smoke_slow_rsp.768497043 |
| Short name | T1360 |
| Test name | |
| Test status | |
| Simulation time | 4546483649 ps |
| CPU time | 80.27 seconds |
| Started | Jun 28 08:40:14 PM PDT 24 |
| Finished | Jun 28 08:41:42 PM PDT 24 |
| Peak memory | 574256 kb |
| Host | smart-35c987b0-285c-42ff-98c7-2ba6b50a1ce6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=768497043 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.xbar_smoke_slow_rsp.768497043 |
| Directory | /workspace/33.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/33.xbar_smoke_zero_delays.2175394007 |
| Short name | T519 |
| Test name | |
| Test status | |
| Simulation time | 49049046 ps |
| CPU time | 7.25 seconds |
| Started | Jun 28 08:40:06 PM PDT 24 |
| Finished | Jun 28 08:40:24 PM PDT 24 |
| Peak memory | 565944 kb |
| Host | smart-7d6523ea-0901-40b3-bc1c-9ef03e4c2f67 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2175394007 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.xbar_smoke_zero_delay s.2175394007 |
| Directory | /workspace/33.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/33.xbar_stress_all.1194084162 |
| Short name | T2822 |
| Test name | |
| Test status | |
| Simulation time | 9068411716 ps |
| CPU time | 367.28 seconds |
| Started | Jun 28 08:40:25 PM PDT 24 |
| Finished | Jun 28 08:46:36 PM PDT 24 |
| Peak memory | 575440 kb |
| Host | smart-6ecce6a3-18fb-46df-8549-1cb06be3505d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1194084162 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.xbar_stress_all.1194084162 |
| Directory | /workspace/33.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/33.xbar_stress_all_with_error.3748718233 |
| Short name | T2816 |
| Test name | |
| Test status | |
| Simulation time | 2921496697 ps |
| CPU time | 213.75 seconds |
| Started | Jun 28 08:40:48 PM PDT 24 |
| Finished | Jun 28 08:44:35 PM PDT 24 |
| Peak memory | 574392 kb |
| Host | smart-8e15751a-9632-49ff-8520-7a0350a11f6d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3748718233 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.xbar_stress_all_with_error.3748718233 |
| Directory | /workspace/33.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/33.xbar_stress_all_with_rand_reset.3882056352 |
| Short name | T2004 |
| Test name | |
| Test status | |
| Simulation time | 75698267 ps |
| CPU time | 30.6 seconds |
| Started | Jun 28 08:40:27 PM PDT 24 |
| Finished | Jun 28 08:41:00 PM PDT 24 |
| Peak memory | 574356 kb |
| Host | smart-896646e1-6d89-45e9-991b-29cda7a7e783 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3882056352 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.xbar_stress_all _with_rand_reset.3882056352 |
| Directory | /workspace/33.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/33.xbar_stress_all_with_reset_error.1207292752 |
| Short name | T2332 |
| Test name | |
| Test status | |
| Simulation time | 6676609699 ps |
| CPU time | 674.26 seconds |
| Started | Jun 28 08:40:29 PM PDT 24 |
| Finished | Jun 28 08:51:45 PM PDT 24 |
| Peak memory | 576448 kb |
| Host | smart-05b0f11d-98cb-475a-842a-7d1bab882515 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1207292752 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.xbar_stress_al l_with_reset_error.1207292752 |
| Directory | /workspace/33.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/33.xbar_unmapped_addr.2995449474 |
| Short name | T1702 |
| Test name | |
| Test status | |
| Simulation time | 119210037 ps |
| CPU time | 17.2 seconds |
| Started | Jun 28 08:40:22 PM PDT 24 |
| Finished | Jun 28 08:40:43 PM PDT 24 |
| Peak memory | 574340 kb |
| Host | smart-287a38b0-d8d2-4ef4-a636-16babbac5039 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2995449474 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.xbar_unmapped_addr.2995449474 |
| Directory | /workspace/33.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/34.xbar_access_same_device.1396212853 |
| Short name | T2354 |
| Test name | |
| Test status | |
| Simulation time | 3477198119 ps |
| CPU time | 159 seconds |
| Started | Jun 28 08:40:29 PM PDT 24 |
| Finished | Jun 28 08:43:10 PM PDT 24 |
| Peak memory | 575348 kb |
| Host | smart-2a46e5c8-48b1-49cd-9b00-8ebd511ef28a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1396212853 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.xbar_access_same_device .1396212853 |
| Directory | /workspace/34.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/34.xbar_access_same_device_slow_rsp.3604278189 |
| Short name | T2050 |
| Test name | |
| Test status | |
| Simulation time | 6864922939 ps |
| CPU time | 121.42 seconds |
| Started | Jun 28 08:40:23 PM PDT 24 |
| Finished | Jun 28 08:42:28 PM PDT 24 |
| Peak memory | 575312 kb |
| Host | smart-24c59e00-7afb-4575-9c88-5092d47eafc1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3604278189 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.xbar_access_same_ device_slow_rsp.3604278189 |
| Directory | /workspace/34.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/34.xbar_error_and_unmapped_addr.3302221871 |
| Short name | T2533 |
| Test name | |
| Test status | |
| Simulation time | 795515871 ps |
| CPU time | 34.08 seconds |
| Started | Jun 28 08:40:23 PM PDT 24 |
| Finished | Jun 28 08:41:01 PM PDT 24 |
| Peak memory | 574184 kb |
| Host | smart-f7b54cf7-8aee-45f2-9b2c-c64afbcdd557 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3302221871 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.xbar_error_and_unmapped_add r.3302221871 |
| Directory | /workspace/34.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/34.xbar_error_random.4259098901 |
| Short name | T2385 |
| Test name | |
| Test status | |
| Simulation time | 27892996 ps |
| CPU time | 5.18 seconds |
| Started | Jun 28 08:40:42 PM PDT 24 |
| Finished | Jun 28 08:41:00 PM PDT 24 |
| Peak memory | 574120 kb |
| Host | smart-29c43405-b028-4fa6-8144-29953589c5e9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4259098901 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.xbar_error_random.4259098901 |
| Directory | /workspace/34.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/34.xbar_random.65173042 |
| Short name | T2226 |
| Test name | |
| Test status | |
| Simulation time | 2524564860 ps |
| CPU time | 94.05 seconds |
| Started | Jun 28 08:40:22 PM PDT 24 |
| Finished | Jun 28 08:42:00 PM PDT 24 |
| Peak memory | 574236 kb |
| Host | smart-c81e7452-450e-4259-8fbd-56b04a6ea0f2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65173042 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.xbar_random.65173042 |
| Directory | /workspace/34.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/34.xbar_random_large_delays.27423625 |
| Short name | T499 |
| Test name | |
| Test status | |
| Simulation time | 42781242291 ps |
| CPU time | 451.61 seconds |
| Started | Jun 28 08:40:43 PM PDT 24 |
| Finished | Jun 28 08:48:26 PM PDT 24 |
| Peak memory | 575320 kb |
| Host | smart-eb209264-b25f-44bd-bdf4-860bb90c7fc4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27423625 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.xbar_random_large_delays.27423625 |
| Directory | /workspace/34.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/34.xbar_random_slow_rsp.28220606 |
| Short name | T1364 |
| Test name | |
| Test status | |
| Simulation time | 24766206281 ps |
| CPU time | 434.15 seconds |
| Started | Jun 28 08:40:22 PM PDT 24 |
| Finished | Jun 28 08:47:40 PM PDT 24 |
| Peak memory | 574224 kb |
| Host | smart-bfffca3c-9fe7-4668-ade2-c1174df1119a |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28220606 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.xbar_random_slow_rsp.28220606 |
| Directory | /workspace/34.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/34.xbar_random_zero_delays.2580041628 |
| Short name | T533 |
| Test name | |
| Test status | |
| Simulation time | 611572453 ps |
| CPU time | 64.82 seconds |
| Started | Jun 28 08:40:23 PM PDT 24 |
| Finished | Jun 28 08:41:31 PM PDT 24 |
| Peak memory | 575316 kb |
| Host | smart-cc8d53e6-e966-4909-bd40-e822801fabaf |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2580041628 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.xbar_random_zero_del ays.2580041628 |
| Directory | /workspace/34.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/34.xbar_same_source.3250560556 |
| Short name | T2009 |
| Test name | |
| Test status | |
| Simulation time | 442168944 ps |
| CPU time | 37.87 seconds |
| Started | Jun 28 08:40:24 PM PDT 24 |
| Finished | Jun 28 08:41:06 PM PDT 24 |
| Peak memory | 575100 kb |
| Host | smart-1ee53776-55fc-4f38-b5be-802b3780a9e4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3250560556 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.xbar_same_source.3250560556 |
| Directory | /workspace/34.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/34.xbar_smoke.619574926 |
| Short name | T73 |
| Test name | |
| Test status | |
| Simulation time | 207784534 ps |
| CPU time | 9.17 seconds |
| Started | Jun 28 08:40:45 PM PDT 24 |
| Finished | Jun 28 08:41:07 PM PDT 24 |
| Peak memory | 574168 kb |
| Host | smart-73de85eb-c9d6-4486-91f7-950c7fd7a791 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=619574926 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.xbar_smoke.619574926 |
| Directory | /workspace/34.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/34.xbar_smoke_large_delays.2128689121 |
| Short name | T1661 |
| Test name | |
| Test status | |
| Simulation time | 8066298173 ps |
| CPU time | 81.71 seconds |
| Started | Jun 28 08:40:43 PM PDT 24 |
| Finished | Jun 28 08:42:16 PM PDT 24 |
| Peak memory | 566008 kb |
| Host | smart-49c9d356-21be-4d6c-822d-8f0b3869c0ba |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2128689121 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.xbar_smoke_large_delays.2128689121 |
| Directory | /workspace/34.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/34.xbar_smoke_slow_rsp.587180545 |
| Short name | T1359 |
| Test name | |
| Test status | |
| Simulation time | 5408852812 ps |
| CPU time | 94.54 seconds |
| Started | Jun 28 08:40:26 PM PDT 24 |
| Finished | Jun 28 08:42:04 PM PDT 24 |
| Peak memory | 574344 kb |
| Host | smart-d9a27ea6-2acb-40ba-8cde-db0b4c3d0c78 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=587180545 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.xbar_smoke_slow_rsp.587180545 |
| Directory | /workspace/34.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/34.xbar_smoke_zero_delays.2916246232 |
| Short name | T2243 |
| Test name | |
| Test status | |
| Simulation time | 36306318 ps |
| CPU time | 5.7 seconds |
| Started | Jun 28 08:40:43 PM PDT 24 |
| Finished | Jun 28 08:41:00 PM PDT 24 |
| Peak memory | 574180 kb |
| Host | smart-2ed0538c-5752-4f15-ad1b-4633daecdd2f |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2916246232 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.xbar_smoke_zero_delay s.2916246232 |
| Directory | /workspace/34.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/34.xbar_stress_all.1336813769 |
| Short name | T550 |
| Test name | |
| Test status | |
| Simulation time | 1044560695 ps |
| CPU time | 86.9 seconds |
| Started | Jun 28 08:40:23 PM PDT 24 |
| Finished | Jun 28 08:41:54 PM PDT 24 |
| Peak memory | 575356 kb |
| Host | smart-b5178478-5210-48b0-a5ce-354b26d08c95 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1336813769 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.xbar_stress_all.1336813769 |
| Directory | /workspace/34.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/34.xbar_stress_all_with_error.1710209813 |
| Short name | T2044 |
| Test name | |
| Test status | |
| Simulation time | 9679362876 ps |
| CPU time | 301.41 seconds |
| Started | Jun 28 08:40:43 PM PDT 24 |
| Finished | Jun 28 08:45:56 PM PDT 24 |
| Peak memory | 574424 kb |
| Host | smart-e2ac42a9-ee2e-44d8-8a00-5a0686552340 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1710209813 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.xbar_stress_all_with_error.1710209813 |
| Directory | /workspace/34.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/34.xbar_stress_all_with_rand_reset.1448034917 |
| Short name | T495 |
| Test name | |
| Test status | |
| Simulation time | 5885763195 ps |
| CPU time | 775.24 seconds |
| Started | Jun 28 08:40:26 PM PDT 24 |
| Finished | Jun 28 08:53:24 PM PDT 24 |
| Peak memory | 575552 kb |
| Host | smart-92d41947-bdd9-4d57-898c-0345ea1457e1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1448034917 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.xbar_stress_all _with_rand_reset.1448034917 |
| Directory | /workspace/34.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/34.xbar_unmapped_addr.1371408013 |
| Short name | T2772 |
| Test name | |
| Test status | |
| Simulation time | 858158804 ps |
| CPU time | 42.47 seconds |
| Started | Jun 28 08:40:24 PM PDT 24 |
| Finished | Jun 28 08:41:10 PM PDT 24 |
| Peak memory | 575292 kb |
| Host | smart-448d516a-bf27-486d-a3e5-6cfc5acbde14 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1371408013 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.xbar_unmapped_addr.1371408013 |
| Directory | /workspace/34.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/35.xbar_access_same_device.390356029 |
| Short name | T795 |
| Test name | |
| Test status | |
| Simulation time | 1129095953 ps |
| CPU time | 46.42 seconds |
| Started | Jun 28 08:40:41 PM PDT 24 |
| Finished | Jun 28 08:41:38 PM PDT 24 |
| Peak memory | 575256 kb |
| Host | smart-f3009a6e-e9b7-42b3-b247-f03515e2afb1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=390356029 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.xbar_access_same_device. 390356029 |
| Directory | /workspace/35.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/35.xbar_error_and_unmapped_addr.2891410772 |
| Short name | T2602 |
| Test name | |
| Test status | |
| Simulation time | 120628622 ps |
| CPU time | 17.63 seconds |
| Started | Jun 28 08:40:40 PM PDT 24 |
| Finished | Jun 28 08:41:06 PM PDT 24 |
| Peak memory | 573860 kb |
| Host | smart-7ffc9265-e4e1-4ae3-aa7f-43384b0147e7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2891410772 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.xbar_error_and_unmapped_add r.2891410772 |
| Directory | /workspace/35.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/35.xbar_error_random.4067806537 |
| Short name | T1432 |
| Test name | |
| Test status | |
| Simulation time | 2056562674 ps |
| CPU time | 81.6 seconds |
| Started | Jun 28 08:40:40 PM PDT 24 |
| Finished | Jun 28 08:42:10 PM PDT 24 |
| Peak memory | 573736 kb |
| Host | smart-4c165b0a-45c6-4025-b5e4-b23209960f4a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4067806537 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.xbar_error_random.4067806537 |
| Directory | /workspace/35.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/35.xbar_random.879997540 |
| Short name | T2149 |
| Test name | |
| Test status | |
| Simulation time | 344871656 ps |
| CPU time | 35.85 seconds |
| Started | Jun 28 08:40:20 PM PDT 24 |
| Finished | Jun 28 08:41:01 PM PDT 24 |
| Peak memory | 575236 kb |
| Host | smart-719fbd8a-ef44-43f7-8aa3-d86a68b7c4e1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=879997540 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.xbar_random.879997540 |
| Directory | /workspace/35.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/35.xbar_random_large_delays.2382241037 |
| Short name | T2783 |
| Test name | |
| Test status | |
| Simulation time | 27830893147 ps |
| CPU time | 285.11 seconds |
| Started | Jun 28 08:40:45 PM PDT 24 |
| Finished | Jun 28 08:45:44 PM PDT 24 |
| Peak memory | 575356 kb |
| Host | smart-d8ee3d5e-7c6d-4208-a16c-4662deeb8b3f |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2382241037 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.xbar_random_large_delays.2382241037 |
| Directory | /workspace/35.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/35.xbar_random_slow_rsp.2111690729 |
| Short name | T580 |
| Test name | |
| Test status | |
| Simulation time | 71857075656 ps |
| CPU time | 1206.11 seconds |
| Started | Jun 28 08:40:23 PM PDT 24 |
| Finished | Jun 28 09:00:34 PM PDT 24 |
| Peak memory | 575340 kb |
| Host | smart-af0d6acc-afb5-4f4f-be77-b9f9b554a10e |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2111690729 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.xbar_random_slow_rsp.2111690729 |
| Directory | /workspace/35.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/35.xbar_random_zero_delays.3036506047 |
| Short name | T2047 |
| Test name | |
| Test status | |
| Simulation time | 610794191 ps |
| CPU time | 64.5 seconds |
| Started | Jun 28 08:40:25 PM PDT 24 |
| Finished | Jun 28 08:41:33 PM PDT 24 |
| Peak memory | 574208 kb |
| Host | smart-1b471d6b-ad04-4299-afe0-f0b50bdb5304 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3036506047 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.xbar_random_zero_del ays.3036506047 |
| Directory | /workspace/35.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/35.xbar_same_source.1815657471 |
| Short name | T1649 |
| Test name | |
| Test status | |
| Simulation time | 916112909 ps |
| CPU time | 25.85 seconds |
| Started | Jun 28 08:40:46 PM PDT 24 |
| Finished | Jun 28 08:41:25 PM PDT 24 |
| Peak memory | 575216 kb |
| Host | smart-0d8b3a20-e21f-4821-9cfd-cad7a7025647 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1815657471 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.xbar_same_source.1815657471 |
| Directory | /workspace/35.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/35.xbar_smoke.1479922582 |
| Short name | T2859 |
| Test name | |
| Test status | |
| Simulation time | 242531087 ps |
| CPU time | 10.44 seconds |
| Started | Jun 28 08:40:29 PM PDT 24 |
| Finished | Jun 28 08:40:41 PM PDT 24 |
| Peak memory | 574168 kb |
| Host | smart-99beb382-86eb-4634-b471-525c4c517d84 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1479922582 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.xbar_smoke.1479922582 |
| Directory | /workspace/35.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/35.xbar_smoke_large_delays.3794639319 |
| Short name | T2011 |
| Test name | |
| Test status | |
| Simulation time | 10027160438 ps |
| CPU time | 103.01 seconds |
| Started | Jun 28 08:40:23 PM PDT 24 |
| Finished | Jun 28 08:42:10 PM PDT 24 |
| Peak memory | 574244 kb |
| Host | smart-ac7c921a-02a0-4b89-8cc2-97fd7372557c |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3794639319 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.xbar_smoke_large_delays.3794639319 |
| Directory | /workspace/35.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/35.xbar_smoke_slow_rsp.290142764 |
| Short name | T1868 |
| Test name | |
| Test status | |
| Simulation time | 5645658795 ps |
| CPU time | 94.74 seconds |
| Started | Jun 28 08:40:24 PM PDT 24 |
| Finished | Jun 28 08:42:03 PM PDT 24 |
| Peak memory | 574136 kb |
| Host | smart-9fb02d7b-e4ae-4fda-a011-a5d46552dee2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=290142764 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.xbar_smoke_slow_rsp.290142764 |
| Directory | /workspace/35.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/35.xbar_smoke_zero_delays.2932670853 |
| Short name | T2842 |
| Test name | |
| Test status | |
| Simulation time | 45603332 ps |
| CPU time | 6.42 seconds |
| Started | Jun 28 08:40:24 PM PDT 24 |
| Finished | Jun 28 08:40:35 PM PDT 24 |
| Peak memory | 574092 kb |
| Host | smart-e1aa8391-2dd4-400b-9103-a0a0190315e6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2932670853 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.xbar_smoke_zero_delay s.2932670853 |
| Directory | /workspace/35.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/35.xbar_stress_all.4001901909 |
| Short name | T2640 |
| Test name | |
| Test status | |
| Simulation time | 3656718018 ps |
| CPU time | 313.48 seconds |
| Started | Jun 28 08:40:40 PM PDT 24 |
| Finished | Jun 28 08:46:02 PM PDT 24 |
| Peak memory | 575468 kb |
| Host | smart-6c92f382-117f-4946-90de-ec476c4b4a9a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4001901909 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.xbar_stress_all.4001901909 |
| Directory | /workspace/35.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/35.xbar_stress_all_with_error.3478679350 |
| Short name | T1615 |
| Test name | |
| Test status | |
| Simulation time | 16395245033 ps |
| CPU time | 674.75 seconds |
| Started | Jun 28 08:40:41 PM PDT 24 |
| Finished | Jun 28 08:52:07 PM PDT 24 |
| Peak memory | 574668 kb |
| Host | smart-a1135179-5f87-40ac-8b49-63d7e5065e1e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3478679350 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.xbar_stress_all_with_error.3478679350 |
| Directory | /workspace/35.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/35.xbar_stress_all_with_rand_reset.3889261415 |
| Short name | T2624 |
| Test name | |
| Test status | |
| Simulation time | 1115629825 ps |
| CPU time | 215.59 seconds |
| Started | Jun 28 08:40:44 PM PDT 24 |
| Finished | Jun 28 08:44:31 PM PDT 24 |
| Peak memory | 575392 kb |
| Host | smart-ea2f4a11-18d8-4f22-ab9e-7ee4f0147d80 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3889261415 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.xbar_stress_all _with_rand_reset.3889261415 |
| Directory | /workspace/35.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/35.xbar_stress_all_with_reset_error.1491452431 |
| Short name | T2497 |
| Test name | |
| Test status | |
| Simulation time | 9640665693 ps |
| CPU time | 637.27 seconds |
| Started | Jun 28 08:40:41 PM PDT 24 |
| Finished | Jun 28 08:51:30 PM PDT 24 |
| Peak memory | 574620 kb |
| Host | smart-8ce55554-97a3-44b6-8e2b-7827f17a1cf1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1491452431 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.xbar_stress_al l_with_reset_error.1491452431 |
| Directory | /workspace/35.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/35.xbar_unmapped_addr.1797591988 |
| Short name | T2767 |
| Test name | |
| Test status | |
| Simulation time | 827150628 ps |
| CPU time | 41.89 seconds |
| Started | Jun 28 08:40:41 PM PDT 24 |
| Finished | Jun 28 08:41:34 PM PDT 24 |
| Peak memory | 575324 kb |
| Host | smart-1510ea8c-ecd4-4a48-8f18-8a959c42e1b3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1797591988 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.xbar_unmapped_addr.1797591988 |
| Directory | /workspace/35.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/36.xbar_access_same_device.2089458452 |
| Short name | T1639 |
| Test name | |
| Test status | |
| Simulation time | 101018847 ps |
| CPU time | 11.72 seconds |
| Started | Jun 28 08:40:40 PM PDT 24 |
| Finished | Jun 28 08:41:00 PM PDT 24 |
| Peak memory | 575220 kb |
| Host | smart-a3e5890c-04f8-4b28-827d-cff0c18c8036 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2089458452 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.xbar_access_same_device .2089458452 |
| Directory | /workspace/36.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/36.xbar_access_same_device_slow_rsp.2140924883 |
| Short name | T788 |
| Test name | |
| Test status | |
| Simulation time | 20846347166 ps |
| CPU time | 344.08 seconds |
| Started | Jun 28 08:40:39 PM PDT 24 |
| Finished | Jun 28 08:46:31 PM PDT 24 |
| Peak memory | 575276 kb |
| Host | smart-0a48eb68-4147-404d-b120-11456bf3ca21 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2140924883 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.xbar_access_same_ device_slow_rsp.2140924883 |
| Directory | /workspace/36.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/36.xbar_error_and_unmapped_addr.3111995629 |
| Short name | T1865 |
| Test name | |
| Test status | |
| Simulation time | 103492357 ps |
| CPU time | 14.15 seconds |
| Started | Jun 28 08:40:42 PM PDT 24 |
| Finished | Jun 28 08:41:06 PM PDT 24 |
| Peak memory | 573984 kb |
| Host | smart-9b75e2a7-260e-4d7c-809f-c715aff1c68d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3111995629 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.xbar_error_and_unmapped_add r.3111995629 |
| Directory | /workspace/36.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/36.xbar_error_random.1167795340 |
| Short name | T1889 |
| Test name | |
| Test status | |
| Simulation time | 384257702 ps |
| CPU time | 14.08 seconds |
| Started | Jun 28 08:40:44 PM PDT 24 |
| Finished | Jun 28 08:41:11 PM PDT 24 |
| Peak memory | 573840 kb |
| Host | smart-92c6a957-3a88-4929-b452-141eb6b5a9df |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1167795340 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.xbar_error_random.1167795340 |
| Directory | /workspace/36.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/36.xbar_random.1832476677 |
| Short name | T1822 |
| Test name | |
| Test status | |
| Simulation time | 365578785 ps |
| CPU time | 31.71 seconds |
| Started | Jun 28 08:40:40 PM PDT 24 |
| Finished | Jun 28 08:41:20 PM PDT 24 |
| Peak memory | 575200 kb |
| Host | smart-bfd5a861-3f81-4de6-8fe2-e13ee4517ed8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1832476677 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.xbar_random.1832476677 |
| Directory | /workspace/36.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/36.xbar_random_large_delays.2791531992 |
| Short name | T1867 |
| Test name | |
| Test status | |
| Simulation time | 25670188125 ps |
| CPU time | 245.1 seconds |
| Started | Jun 28 08:40:45 PM PDT 24 |
| Finished | Jun 28 08:45:03 PM PDT 24 |
| Peak memory | 575320 kb |
| Host | smart-c9ccf143-3816-4321-9f13-4475f12c9e71 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2791531992 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.xbar_random_large_delays.2791531992 |
| Directory | /workspace/36.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/36.xbar_random_slow_rsp.2995857835 |
| Short name | T2307 |
| Test name | |
| Test status | |
| Simulation time | 56779901539 ps |
| CPU time | 1002.95 seconds |
| Started | Jun 28 08:40:46 PM PDT 24 |
| Finished | Jun 28 08:57:42 PM PDT 24 |
| Peak memory | 575336 kb |
| Host | smart-40d9fd9d-c447-4f79-b3e3-7c017b305b65 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2995857835 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.xbar_random_slow_rsp.2995857835 |
| Directory | /workspace/36.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/36.xbar_random_zero_delays.2124972319 |
| Short name | T1420 |
| Test name | |
| Test status | |
| Simulation time | 214864204 ps |
| CPU time | 23.88 seconds |
| Started | Jun 28 08:40:39 PM PDT 24 |
| Finished | Jun 28 08:41:11 PM PDT 24 |
| Peak memory | 575228 kb |
| Host | smart-62736b53-2c72-443f-80c4-191bea72f263 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2124972319 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.xbar_random_zero_del ays.2124972319 |
| Directory | /workspace/36.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/36.xbar_same_source.137427415 |
| Short name | T2327 |
| Test name | |
| Test status | |
| Simulation time | 541310077 ps |
| CPU time | 39.28 seconds |
| Started | Jun 28 08:40:39 PM PDT 24 |
| Finished | Jun 28 08:41:27 PM PDT 24 |
| Peak memory | 575252 kb |
| Host | smart-518fe99c-02f6-4210-b26d-be83cf89fa25 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=137427415 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.xbar_same_source.137427415 |
| Directory | /workspace/36.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/36.xbar_smoke.1257227962 |
| Short name | T1472 |
| Test name | |
| Test status | |
| Simulation time | 190054285 ps |
| CPU time | 8.85 seconds |
| Started | Jun 28 08:40:40 PM PDT 24 |
| Finished | Jun 28 08:40:58 PM PDT 24 |
| Peak memory | 574276 kb |
| Host | smart-dc9d24e5-eba5-4d0c-8bad-7511a5ba5567 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1257227962 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.xbar_smoke.1257227962 |
| Directory | /workspace/36.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/36.xbar_smoke_large_delays.361188821 |
| Short name | T2803 |
| Test name | |
| Test status | |
| Simulation time | 7337897742 ps |
| CPU time | 78.74 seconds |
| Started | Jun 28 08:40:42 PM PDT 24 |
| Finished | Jun 28 08:42:12 PM PDT 24 |
| Peak memory | 566020 kb |
| Host | smart-57fad567-aef6-45a8-87a7-e5a5c84cfb63 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=361188821 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.xbar_smoke_large_delays.361188821 |
| Directory | /workspace/36.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/36.xbar_smoke_slow_rsp.3280410523 |
| Short name | T2500 |
| Test name | |
| Test status | |
| Simulation time | 7042154860 ps |
| CPU time | 120.84 seconds |
| Started | Jun 28 08:40:42 PM PDT 24 |
| Finished | Jun 28 08:42:53 PM PDT 24 |
| Peak memory | 574176 kb |
| Host | smart-60e41aac-5b3c-40a4-abe6-ab6d6316e156 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3280410523 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.xbar_smoke_slow_rsp.3280410523 |
| Directory | /workspace/36.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/36.xbar_smoke_zero_delays.3155244659 |
| Short name | T1597 |
| Test name | |
| Test status | |
| Simulation time | 54173530 ps |
| CPU time | 7.34 seconds |
| Started | Jun 28 08:40:42 PM PDT 24 |
| Finished | Jun 28 08:40:59 PM PDT 24 |
| Peak memory | 565956 kb |
| Host | smart-d6d255cf-7144-419c-8fb3-149f1e335d3c |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3155244659 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.xbar_smoke_zero_delay s.3155244659 |
| Directory | /workspace/36.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/36.xbar_stress_all.1053366671 |
| Short name | T2363 |
| Test name | |
| Test status | |
| Simulation time | 2225952268 ps |
| CPU time | 194.01 seconds |
| Started | Jun 28 08:40:44 PM PDT 24 |
| Finished | Jun 28 08:44:10 PM PDT 24 |
| Peak memory | 575400 kb |
| Host | smart-6d1de6d9-388f-45b1-b08c-ca90a633a1e2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1053366671 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.xbar_stress_all.1053366671 |
| Directory | /workspace/36.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/36.xbar_stress_all_with_error.3416591995 |
| Short name | T1520 |
| Test name | |
| Test status | |
| Simulation time | 13684790069 ps |
| CPU time | 501.17 seconds |
| Started | Jun 28 08:40:40 PM PDT 24 |
| Finished | Jun 28 08:49:10 PM PDT 24 |
| Peak memory | 574668 kb |
| Host | smart-e743c236-7d75-4486-92d4-5d0f50f50a73 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3416591995 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.xbar_stress_all_with_error.3416591995 |
| Directory | /workspace/36.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/36.xbar_stress_all_with_rand_reset.327185877 |
| Short name | T850 |
| Test name | |
| Test status | |
| Simulation time | 186431348 ps |
| CPU time | 67.09 seconds |
| Started | Jun 28 08:40:39 PM PDT 24 |
| Finished | Jun 28 08:41:55 PM PDT 24 |
| Peak memory | 575380 kb |
| Host | smart-4c0384c0-71a8-42f4-8017-e75529ea62d1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=327185877 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_res et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.xbar_stress_all_ with_rand_reset.327185877 |
| Directory | /workspace/36.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/36.xbar_stress_all_with_reset_error.3701367813 |
| Short name | T2269 |
| Test name | |
| Test status | |
| Simulation time | 99704303 ps |
| CPU time | 29.73 seconds |
| Started | Jun 28 08:41:05 PM PDT 24 |
| Finished | Jun 28 08:41:39 PM PDT 24 |
| Peak memory | 574588 kb |
| Host | smart-493f106b-b41d-49f0-be81-943284beeddf |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3701367813 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.xbar_stress_al l_with_reset_error.3701367813 |
| Directory | /workspace/36.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/36.xbar_unmapped_addr.3483422036 |
| Short name | T613 |
| Test name | |
| Test status | |
| Simulation time | 582590982 ps |
| CPU time | 28.92 seconds |
| Started | Jun 28 08:40:44 PM PDT 24 |
| Finished | Jun 28 08:41:25 PM PDT 24 |
| Peak memory | 574248 kb |
| Host | smart-473df3b1-3286-4cfb-a847-7adc925f8390 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3483422036 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.xbar_unmapped_addr.3483422036 |
| Directory | /workspace/36.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/37.xbar_access_same_device.2464185523 |
| Short name | T2773 |
| Test name | |
| Test status | |
| Simulation time | 2593211296 ps |
| CPU time | 110.37 seconds |
| Started | Jun 28 08:41:06 PM PDT 24 |
| Finished | Jun 28 08:43:01 PM PDT 24 |
| Peak memory | 574220 kb |
| Host | smart-8031b5ef-f978-46e3-b7a8-0712dfa03637 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2464185523 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.xbar_access_same_device .2464185523 |
| Directory | /workspace/37.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/37.xbar_access_same_device_slow_rsp.2127778422 |
| Short name | T2874 |
| Test name | |
| Test status | |
| Simulation time | 110044671610 ps |
| CPU time | 2027.85 seconds |
| Started | Jun 28 08:41:08 PM PDT 24 |
| Finished | Jun 28 09:15:00 PM PDT 24 |
| Peak memory | 575360 kb |
| Host | smart-db567723-0324-47a7-809c-61da24ca6540 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2127778422 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.xbar_access_same_ device_slow_rsp.2127778422 |
| Directory | /workspace/37.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/37.xbar_error_and_unmapped_addr.1398939617 |
| Short name | T1551 |
| Test name | |
| Test status | |
| Simulation time | 212641302 ps |
| CPU time | 13.16 seconds |
| Started | Jun 28 08:41:06 PM PDT 24 |
| Finished | Jun 28 08:41:24 PM PDT 24 |
| Peak memory | 574196 kb |
| Host | smart-75dbaaa6-0d42-4763-b7e7-64669f48a810 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1398939617 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.xbar_error_and_unmapped_add r.1398939617 |
| Directory | /workspace/37.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/37.xbar_error_random.790604604 |
| Short name | T1410 |
| Test name | |
| Test status | |
| Simulation time | 453228542 ps |
| CPU time | 42.51 seconds |
| Started | Jun 28 08:41:05 PM PDT 24 |
| Finished | Jun 28 08:41:52 PM PDT 24 |
| Peak memory | 574432 kb |
| Host | smart-0eb04b2f-b7af-439b-8344-275e722e4b07 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=790604604 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.xbar_error_random.790604604 |
| Directory | /workspace/37.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/37.xbar_random.2598227028 |
| Short name | T1388 |
| Test name | |
| Test status | |
| Simulation time | 134758148 ps |
| CPU time | 15.79 seconds |
| Started | Jun 28 08:41:06 PM PDT 24 |
| Finished | Jun 28 08:41:26 PM PDT 24 |
| Peak memory | 574192 kb |
| Host | smart-a168a365-34bb-4142-b84b-862b2233259f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2598227028 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.xbar_random.2598227028 |
| Directory | /workspace/37.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/37.xbar_random_large_delays.898228608 |
| Short name | T567 |
| Test name | |
| Test status | |
| Simulation time | 6893966694 ps |
| CPU time | 78.59 seconds |
| Started | Jun 28 08:41:06 PM PDT 24 |
| Finished | Jun 28 08:42:28 PM PDT 24 |
| Peak memory | 574092 kb |
| Host | smart-28a368e7-8af8-46d6-bd98-e5d145407caf |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=898228608 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.xbar_random_large_delays.898228608 |
| Directory | /workspace/37.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/37.xbar_random_slow_rsp.3288556763 |
| Short name | T1411 |
| Test name | |
| Test status | |
| Simulation time | 14091312384 ps |
| CPU time | 260.71 seconds |
| Started | Jun 28 08:41:07 PM PDT 24 |
| Finished | Jun 28 08:45:31 PM PDT 24 |
| Peak memory | 575352 kb |
| Host | smart-9de78818-96cd-4ea7-bf60-00f9fe33f246 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3288556763 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.xbar_random_slow_rsp.3288556763 |
| Directory | /workspace/37.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/37.xbar_random_zero_delays.1672302281 |
| Short name | T2370 |
| Test name | |
| Test status | |
| Simulation time | 184506753 ps |
| CPU time | 20.15 seconds |
| Started | Jun 28 08:41:05 PM PDT 24 |
| Finished | Jun 28 08:41:29 PM PDT 24 |
| Peak memory | 574192 kb |
| Host | smart-9c0d7019-4403-492a-88f5-e634d3e814dd |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1672302281 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.xbar_random_zero_del ays.1672302281 |
| Directory | /workspace/37.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/37.xbar_same_source.3600866115 |
| Short name | T2416 |
| Test name | |
| Test status | |
| Simulation time | 2492247227 ps |
| CPU time | 89.11 seconds |
| Started | Jun 28 08:41:04 PM PDT 24 |
| Finished | Jun 28 08:42:38 PM PDT 24 |
| Peak memory | 575308 kb |
| Host | smart-c3c82d45-51ff-43f8-9f4f-4eb25a07c4f6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3600866115 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.xbar_same_source.3600866115 |
| Directory | /workspace/37.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/37.xbar_smoke.3713951723 |
| Short name | T1357 |
| Test name | |
| Test status | |
| Simulation time | 50332239 ps |
| CPU time | 7.08 seconds |
| Started | Jun 28 08:41:06 PM PDT 24 |
| Finished | Jun 28 08:41:17 PM PDT 24 |
| Peak memory | 574196 kb |
| Host | smart-e7f50292-4cbd-4809-a679-ce9a348ab5fa |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3713951723 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.xbar_smoke.3713951723 |
| Directory | /workspace/37.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/37.xbar_smoke_large_delays.2290287908 |
| Short name | T1981 |
| Test name | |
| Test status | |
| Simulation time | 8130097049 ps |
| CPU time | 85.28 seconds |
| Started | Jun 28 08:41:06 PM PDT 24 |
| Finished | Jun 28 08:42:35 PM PDT 24 |
| Peak memory | 566020 kb |
| Host | smart-ee1934c7-678c-4dc6-9aea-2d75873f5c2a |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2290287908 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.xbar_smoke_large_delays.2290287908 |
| Directory | /workspace/37.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/37.xbar_smoke_slow_rsp.3624204989 |
| Short name | T2833 |
| Test name | |
| Test status | |
| Simulation time | 4195370394 ps |
| CPU time | 74.05 seconds |
| Started | Jun 28 08:41:07 PM PDT 24 |
| Finished | Jun 28 08:42:25 PM PDT 24 |
| Peak memory | 574248 kb |
| Host | smart-9269bab4-06f0-4266-96bf-6087dd3d3224 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3624204989 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.xbar_smoke_slow_rsp.3624204989 |
| Directory | /workspace/37.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/37.xbar_smoke_zero_delays.2016789927 |
| Short name | T2302 |
| Test name | |
| Test status | |
| Simulation time | 39149692 ps |
| CPU time | 5.99 seconds |
| Started | Jun 28 08:41:05 PM PDT 24 |
| Finished | Jun 28 08:41:15 PM PDT 24 |
| Peak memory | 565908 kb |
| Host | smart-e959df59-8893-48cf-ae88-dfc0b3c4031e |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2016789927 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.xbar_smoke_zero_delay s.2016789927 |
| Directory | /workspace/37.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/37.xbar_stress_all.2124786141 |
| Short name | T2298 |
| Test name | |
| Test status | |
| Simulation time | 3404286808 ps |
| CPU time | 302.14 seconds |
| Started | Jun 28 08:41:07 PM PDT 24 |
| Finished | Jun 28 08:46:13 PM PDT 24 |
| Peak memory | 574480 kb |
| Host | smart-576d8f11-4220-4c19-bff4-f292f47c8c2a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2124786141 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.xbar_stress_all.2124786141 |
| Directory | /workspace/37.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/37.xbar_stress_all_with_error.2403983518 |
| Short name | T2861 |
| Test name | |
| Test status | |
| Simulation time | 11984274406 ps |
| CPU time | 448.93 seconds |
| Started | Jun 28 08:41:06 PM PDT 24 |
| Finished | Jun 28 08:48:39 PM PDT 24 |
| Peak memory | 574628 kb |
| Host | smart-2b13e49f-08e9-41ee-8b45-30c145e1a060 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2403983518 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.xbar_stress_all_with_error.2403983518 |
| Directory | /workspace/37.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/37.xbar_stress_all_with_reset_error.1454746865 |
| Short name | T796 |
| Test name | |
| Test status | |
| Simulation time | 12988843732 ps |
| CPU time | 601.19 seconds |
| Started | Jun 28 08:41:05 PM PDT 24 |
| Finished | Jun 28 08:51:10 PM PDT 24 |
| Peak memory | 575456 kb |
| Host | smart-0f82199e-6037-42c0-b434-5e3443db1200 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1454746865 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.xbar_stress_al l_with_reset_error.1454746865 |
| Directory | /workspace/37.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/37.xbar_unmapped_addr.540108537 |
| Short name | T484 |
| Test name | |
| Test status | |
| Simulation time | 219483778 ps |
| CPU time | 30.56 seconds |
| Started | Jun 28 08:41:07 PM PDT 24 |
| Finished | Jun 28 08:41:41 PM PDT 24 |
| Peak memory | 575304 kb |
| Host | smart-69031003-deac-435d-b93c-31e1bea9862e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=540108537 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.xbar_unmapped_addr.540108537 |
| Directory | /workspace/37.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/38.xbar_access_same_device.2414667393 |
| Short name | T2051 |
| Test name | |
| Test status | |
| Simulation time | 43185060 ps |
| CPU time | 7.46 seconds |
| Started | Jun 28 08:41:33 PM PDT 24 |
| Finished | Jun 28 08:41:45 PM PDT 24 |
| Peak memory | 565888 kb |
| Host | smart-114e1de6-4a3b-4770-b1dc-71cd21427807 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2414667393 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.xbar_access_same_device .2414667393 |
| Directory | /workspace/38.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/38.xbar_access_same_device_slow_rsp.3088097647 |
| Short name | T2433 |
| Test name | |
| Test status | |
| Simulation time | 80686930567 ps |
| CPU time | 1367.6 seconds |
| Started | Jun 28 08:41:34 PM PDT 24 |
| Finished | Jun 28 09:04:27 PM PDT 24 |
| Peak memory | 574320 kb |
| Host | smart-6af2fe9c-3cd9-4ca8-8a56-dd5aa264ba7a |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3088097647 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.xbar_access_same_ device_slow_rsp.3088097647 |
| Directory | /workspace/38.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/38.xbar_error_and_unmapped_addr.3315815173 |
| Short name | T1955 |
| Test name | |
| Test status | |
| Simulation time | 1027736857 ps |
| CPU time | 39.54 seconds |
| Started | Jun 28 08:41:36 PM PDT 24 |
| Finished | Jun 28 08:42:20 PM PDT 24 |
| Peak memory | 574436 kb |
| Host | smart-c8b55097-ff5f-414a-97d9-285df951bf9a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3315815173 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.xbar_error_and_unmapped_add r.3315815173 |
| Directory | /workspace/38.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/38.xbar_error_random.674321043 |
| Short name | T2217 |
| Test name | |
| Test status | |
| Simulation time | 61425369 ps |
| CPU time | 8.14 seconds |
| Started | Jun 28 08:41:32 PM PDT 24 |
| Finished | Jun 28 08:41:43 PM PDT 24 |
| Peak memory | 573848 kb |
| Host | smart-96fef2f4-6eae-451e-a262-4a0c7af6adba |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=674321043 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.xbar_error_random.674321043 |
| Directory | /workspace/38.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/38.xbar_random.3754965704 |
| Short name | T586 |
| Test name | |
| Test status | |
| Simulation time | 175976652 ps |
| CPU time | 17.02 seconds |
| Started | Jun 28 08:41:09 PM PDT 24 |
| Finished | Jun 28 08:41:29 PM PDT 24 |
| Peak memory | 575244 kb |
| Host | smart-0b08d211-44cf-4b60-ae6f-d70cecf98e37 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3754965704 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.xbar_random.3754965704 |
| Directory | /workspace/38.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/38.xbar_random_large_delays.4134921461 |
| Short name | T2111 |
| Test name | |
| Test status | |
| Simulation time | 46608029184 ps |
| CPU time | 498.51 seconds |
| Started | Jun 28 08:41:32 PM PDT 24 |
| Finished | Jun 28 08:49:54 PM PDT 24 |
| Peak memory | 575332 kb |
| Host | smart-c47c750a-75f6-40cd-a875-f0fa79672737 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4134921461 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.xbar_random_large_delays.4134921461 |
| Directory | /workspace/38.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/38.xbar_random_slow_rsp.3163276885 |
| Short name | T1962 |
| Test name | |
| Test status | |
| Simulation time | 58940489968 ps |
| CPU time | 1011.59 seconds |
| Started | Jun 28 08:41:34 PM PDT 24 |
| Finished | Jun 28 08:58:30 PM PDT 24 |
| Peak memory | 575292 kb |
| Host | smart-c081f109-6e87-49fc-85dd-1aedeced9cad |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3163276885 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.xbar_random_slow_rsp.3163276885 |
| Directory | /workspace/38.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/38.xbar_random_zero_delays.3293617259 |
| Short name | T2717 |
| Test name | |
| Test status | |
| Simulation time | 422428630 ps |
| CPU time | 40.42 seconds |
| Started | Jun 28 08:41:32 PM PDT 24 |
| Finished | Jun 28 08:42:16 PM PDT 24 |
| Peak memory | 575240 kb |
| Host | smart-95f2466c-5d48-41a3-9ef9-a8ff85918663 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3293617259 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.xbar_random_zero_del ays.3293617259 |
| Directory | /workspace/38.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/38.xbar_same_source.2586420314 |
| Short name | T1672 |
| Test name | |
| Test status | |
| Simulation time | 2017600134 ps |
| CPU time | 67.07 seconds |
| Started | Jun 28 08:41:35 PM PDT 24 |
| Finished | Jun 28 08:42:47 PM PDT 24 |
| Peak memory | 575232 kb |
| Host | smart-6821af58-7fce-4d00-a879-ec09ac4e8e46 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2586420314 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.xbar_same_source.2586420314 |
| Directory | /workspace/38.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/38.xbar_smoke.1862717225 |
| Short name | T1580 |
| Test name | |
| Test status | |
| Simulation time | 176604430 ps |
| CPU time | 8.81 seconds |
| Started | Jun 28 08:41:05 PM PDT 24 |
| Finished | Jun 28 08:41:18 PM PDT 24 |
| Peak memory | 565852 kb |
| Host | smart-ef3d4464-5ed5-4d19-9173-6bb676c74a8b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1862717225 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.xbar_smoke.1862717225 |
| Directory | /workspace/38.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/38.xbar_smoke_large_delays.2127169226 |
| Short name | T2155 |
| Test name | |
| Test status | |
| Simulation time | 4633433852 ps |
| CPU time | 49.54 seconds |
| Started | Jun 28 08:41:06 PM PDT 24 |
| Finished | Jun 28 08:41:59 PM PDT 24 |
| Peak memory | 574040 kb |
| Host | smart-9d5b5d77-e441-4db1-a067-40bd00ba402d |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2127169226 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.xbar_smoke_large_delays.2127169226 |
| Directory | /workspace/38.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/38.xbar_smoke_slow_rsp.2585220729 |
| Short name | T1634 |
| Test name | |
| Test status | |
| Simulation time | 5045342582 ps |
| CPU time | 88.91 seconds |
| Started | Jun 28 08:41:06 PM PDT 24 |
| Finished | Jun 28 08:42:39 PM PDT 24 |
| Peak memory | 574116 kb |
| Host | smart-2563963f-5965-497d-a6fa-c9f8b5c32aac |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2585220729 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.xbar_smoke_slow_rsp.2585220729 |
| Directory | /workspace/38.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/38.xbar_smoke_zero_delays.3645986021 |
| Short name | T2119 |
| Test name | |
| Test status | |
| Simulation time | 42183016 ps |
| CPU time | 6.94 seconds |
| Started | Jun 28 08:41:05 PM PDT 24 |
| Finished | Jun 28 08:41:16 PM PDT 24 |
| Peak memory | 574168 kb |
| Host | smart-a48d2989-02a5-42a6-affc-c9fa76b90c39 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3645986021 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.xbar_smoke_zero_delay s.3645986021 |
| Directory | /workspace/38.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/38.xbar_stress_all.3625202319 |
| Short name | T1462 |
| Test name | |
| Test status | |
| Simulation time | 421278453 ps |
| CPU time | 43.65 seconds |
| Started | Jun 28 08:41:35 PM PDT 24 |
| Finished | Jun 28 08:42:24 PM PDT 24 |
| Peak memory | 575312 kb |
| Host | smart-5c5a3c19-e87f-416f-9ff8-f364eb1db78a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3625202319 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.xbar_stress_all.3625202319 |
| Directory | /workspace/38.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/38.xbar_stress_all_with_error.3651813820 |
| Short name | T1950 |
| Test name | |
| Test status | |
| Simulation time | 8037990669 ps |
| CPU time | 332.98 seconds |
| Started | Jun 28 08:41:35 PM PDT 24 |
| Finished | Jun 28 08:47:13 PM PDT 24 |
| Peak memory | 574648 kb |
| Host | smart-5d8a0b92-cf50-43b0-9c96-497e1d7e9c05 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3651813820 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.xbar_stress_all_with_error.3651813820 |
| Directory | /workspace/38.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/38.xbar_stress_all_with_rand_reset.4236665 |
| Short name | T2010 |
| Test name | |
| Test status | |
| Simulation time | 2137744547 ps |
| CPU time | 416.79 seconds |
| Started | Jun 28 08:41:36 PM PDT 24 |
| Finished | Jun 28 08:48:38 PM PDT 24 |
| Peak memory | 575388 kb |
| Host | smart-20313f69-9be2-490c-8e74-fc9cdc428e3f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4236665 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.xbar_stress_all_wi th_rand_reset.4236665 |
| Directory | /workspace/38.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/38.xbar_stress_all_with_reset_error.1086314082 |
| Short name | T2466 |
| Test name | |
| Test status | |
| Simulation time | 148662604 ps |
| CPU time | 38.51 seconds |
| Started | Jun 28 08:41:30 PM PDT 24 |
| Finished | Jun 28 08:42:10 PM PDT 24 |
| Peak memory | 575384 kb |
| Host | smart-23b731b5-525a-4d64-abe5-df033cb9c872 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1086314082 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.xbar_stress_al l_with_reset_error.1086314082 |
| Directory | /workspace/38.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/38.xbar_unmapped_addr.120856616 |
| Short name | T1934 |
| Test name | |
| Test status | |
| Simulation time | 388546882 ps |
| CPU time | 21.67 seconds |
| Started | Jun 28 08:41:35 PM PDT 24 |
| Finished | Jun 28 08:42:02 PM PDT 24 |
| Peak memory | 575280 kb |
| Host | smart-903f3b9a-01d0-4a02-9c8a-0eb8c8de52aa |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=120856616 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.xbar_unmapped_addr.120856616 |
| Directory | /workspace/38.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/39.xbar_access_same_device.2644669964 |
| Short name | T581 |
| Test name | |
| Test status | |
| Simulation time | 367152964 ps |
| CPU time | 33.89 seconds |
| Started | Jun 28 08:41:32 PM PDT 24 |
| Finished | Jun 28 08:42:09 PM PDT 24 |
| Peak memory | 574184 kb |
| Host | smart-8b0f2c00-70b7-487e-9ff5-7b2fb74fdf47 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2644669964 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.xbar_access_same_device .2644669964 |
| Directory | /workspace/39.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/39.xbar_access_same_device_slow_rsp.2625555858 |
| Short name | T808 |
| Test name | |
| Test status | |
| Simulation time | 55894090098 ps |
| CPU time | 1013.26 seconds |
| Started | Jun 28 08:41:33 PM PDT 24 |
| Finished | Jun 28 08:58:31 PM PDT 24 |
| Peak memory | 575304 kb |
| Host | smart-47288b3a-13df-42ba-8dd9-c7f251a768e9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2625555858 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.xbar_access_same_ device_slow_rsp.2625555858 |
| Directory | /workspace/39.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/39.xbar_error_and_unmapped_addr.240897407 |
| Short name | T2710 |
| Test name | |
| Test status | |
| Simulation time | 73531778 ps |
| CPU time | 10.99 seconds |
| Started | Jun 28 08:41:32 PM PDT 24 |
| Finished | Jun 28 08:41:45 PM PDT 24 |
| Peak memory | 573848 kb |
| Host | smart-bc1f389e-6b35-4663-8803-a2d92da2f0e7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=240897407 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.xbar_error_and_unmapped_addr .240897407 |
| Directory | /workspace/39.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/39.xbar_error_random.4239451487 |
| Short name | T1796 |
| Test name | |
| Test status | |
| Simulation time | 1675628110 ps |
| CPU time | 60.68 seconds |
| Started | Jun 28 08:41:34 PM PDT 24 |
| Finished | Jun 28 08:42:39 PM PDT 24 |
| Peak memory | 574428 kb |
| Host | smart-c4e658ce-0aff-42ec-b2f6-9fd555e1d58b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4239451487 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.xbar_error_random.4239451487 |
| Directory | /workspace/39.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/39.xbar_random.1857986559 |
| Short name | T2465 |
| Test name | |
| Test status | |
| Simulation time | 1085513537 ps |
| CPU time | 41.83 seconds |
| Started | Jun 28 08:41:35 PM PDT 24 |
| Finished | Jun 28 08:42:22 PM PDT 24 |
| Peak memory | 574160 kb |
| Host | smart-4ec1b0e5-76e4-4a11-ad4f-7d72ded45719 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1857986559 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.xbar_random.1857986559 |
| Directory | /workspace/39.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/39.xbar_random_large_delays.2533389912 |
| Short name | T453 |
| Test name | |
| Test status | |
| Simulation time | 57586722818 ps |
| CPU time | 628.86 seconds |
| Started | Jun 28 08:41:35 PM PDT 24 |
| Finished | Jun 28 08:52:09 PM PDT 24 |
| Peak memory | 575312 kb |
| Host | smart-282221ea-4382-4137-9399-fe13873f2012 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2533389912 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.xbar_random_large_delays.2533389912 |
| Directory | /workspace/39.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/39.xbar_random_slow_rsp.3338669760 |
| Short name | T1953 |
| Test name | |
| Test status | |
| Simulation time | 23849544403 ps |
| CPU time | 388.53 seconds |
| Started | Jun 28 08:41:36 PM PDT 24 |
| Finished | Jun 28 08:48:10 PM PDT 24 |
| Peak memory | 575328 kb |
| Host | smart-a8d9ae3f-7958-4fe0-a69c-9f78f7df02c3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3338669760 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.xbar_random_slow_rsp.3338669760 |
| Directory | /workspace/39.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/39.xbar_random_zero_delays.1656293823 |
| Short name | T2468 |
| Test name | |
| Test status | |
| Simulation time | 566087858 ps |
| CPU time | 57.73 seconds |
| Started | Jun 28 08:41:33 PM PDT 24 |
| Finished | Jun 28 08:42:35 PM PDT 24 |
| Peak memory | 575216 kb |
| Host | smart-89d98ac6-d310-4a05-b064-5ef0bb9e230e |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1656293823 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.xbar_random_zero_del ays.1656293823 |
| Directory | /workspace/39.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/39.xbar_same_source.3983600646 |
| Short name | T555 |
| Test name | |
| Test status | |
| Simulation time | 2494952462 ps |
| CPU time | 93.23 seconds |
| Started | Jun 28 08:41:38 PM PDT 24 |
| Finished | Jun 28 08:43:15 PM PDT 24 |
| Peak memory | 575300 kb |
| Host | smart-0df11c76-2214-4e7e-8d40-d20ac3a7c568 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3983600646 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.xbar_same_source.3983600646 |
| Directory | /workspace/39.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/39.xbar_smoke.3547754486 |
| Short name | T1823 |
| Test name | |
| Test status | |
| Simulation time | 178053759 ps |
| CPU time | 8.68 seconds |
| Started | Jun 28 08:41:35 PM PDT 24 |
| Finished | Jun 28 08:41:49 PM PDT 24 |
| Peak memory | 574188 kb |
| Host | smart-a086726c-e968-4097-875d-314a4b2e797d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3547754486 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.xbar_smoke.3547754486 |
| Directory | /workspace/39.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/39.xbar_smoke_large_delays.1827965643 |
| Short name | T2002 |
| Test name | |
| Test status | |
| Simulation time | 7334501234 ps |
| CPU time | 82.52 seconds |
| Started | Jun 28 08:41:35 PM PDT 24 |
| Finished | Jun 28 08:43:03 PM PDT 24 |
| Peak memory | 574256 kb |
| Host | smart-0ac3c392-77e9-43f7-bc16-0d937aeae085 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1827965643 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.xbar_smoke_large_delays.1827965643 |
| Directory | /workspace/39.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/39.xbar_smoke_slow_rsp.470971056 |
| Short name | T1870 |
| Test name | |
| Test status | |
| Simulation time | 6291142215 ps |
| CPU time | 113.18 seconds |
| Started | Jun 28 08:41:34 PM PDT 24 |
| Finished | Jun 28 08:43:32 PM PDT 24 |
| Peak memory | 574280 kb |
| Host | smart-58a033f5-09ac-4c91-8ac0-e373848691c2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=470971056 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.xbar_smoke_slow_rsp.470971056 |
| Directory | /workspace/39.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/39.xbar_smoke_zero_delays.2859409829 |
| Short name | T1482 |
| Test name | |
| Test status | |
| Simulation time | 44858926 ps |
| CPU time | 6.74 seconds |
| Started | Jun 28 08:41:32 PM PDT 24 |
| Finished | Jun 28 08:41:41 PM PDT 24 |
| Peak memory | 574172 kb |
| Host | smart-2d2aee21-896f-4adb-85ee-18eea26ee946 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2859409829 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.xbar_smoke_zero_delay s.2859409829 |
| Directory | /workspace/39.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/39.xbar_stress_all.1833164125 |
| Short name | T2209 |
| Test name | |
| Test status | |
| Simulation time | 1693879312 ps |
| CPU time | 57.81 seconds |
| Started | Jun 28 08:41:34 PM PDT 24 |
| Finished | Jun 28 08:42:37 PM PDT 24 |
| Peak memory | 575248 kb |
| Host | smart-3de10a6b-2b02-40cf-a11b-ab7e5a840433 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1833164125 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.xbar_stress_all.1833164125 |
| Directory | /workspace/39.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/39.xbar_stress_all_with_error.3295677502 |
| Short name | T807 |
| Test name | |
| Test status | |
| Simulation time | 1344949900 ps |
| CPU time | 115.44 seconds |
| Started | Jun 28 08:41:32 PM PDT 24 |
| Finished | Jun 28 08:43:31 PM PDT 24 |
| Peak memory | 574556 kb |
| Host | smart-c66c1418-ba98-4daa-a4f6-112c7211fc50 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3295677502 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.xbar_stress_all_with_error.3295677502 |
| Directory | /workspace/39.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/39.xbar_stress_all_with_rand_reset.2314293932 |
| Short name | T2657 |
| Test name | |
| Test status | |
| Simulation time | 436748482 ps |
| CPU time | 77.38 seconds |
| Started | Jun 28 08:41:34 PM PDT 24 |
| Finished | Jun 28 08:42:56 PM PDT 24 |
| Peak memory | 574308 kb |
| Host | smart-a67b9be2-d52e-4d97-be4d-252a0cac6832 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2314293932 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.xbar_stress_all _with_rand_reset.2314293932 |
| Directory | /workspace/39.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/39.xbar_stress_all_with_reset_error.1263466764 |
| Short name | T2325 |
| Test name | |
| Test status | |
| Simulation time | 25345909 ps |
| CPU time | 10.11 seconds |
| Started | Jun 28 08:41:34 PM PDT 24 |
| Finished | Jun 28 08:41:50 PM PDT 24 |
| Peak memory | 565984 kb |
| Host | smart-0c0987c6-79f6-4609-8fa0-1345f0404afd |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1263466764 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.xbar_stress_al l_with_reset_error.1263466764 |
| Directory | /workspace/39.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/39.xbar_unmapped_addr.1546857721 |
| Short name | T2027 |
| Test name | |
| Test status | |
| Simulation time | 804716149 ps |
| CPU time | 37.98 seconds |
| Started | Jun 28 08:41:38 PM PDT 24 |
| Finished | Jun 28 08:42:20 PM PDT 24 |
| Peak memory | 575312 kb |
| Host | smart-5973056e-0993-4e09-8838-7276719095f3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1546857721 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.xbar_unmapped_addr.1546857721 |
| Directory | /workspace/39.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/4.chip_csr_aliasing.1107664071 |
| Short name | T1763 |
| Test name | |
| Test status | |
| Simulation time | 56146463472 ps |
| CPU time | 10513.3 seconds |
| Started | Jun 28 08:30:19 PM PDT 24 |
| Finished | Jun 28 11:25:38 PM PDT 24 |
| Peak memory | 640384 kb |
| Host | smart-84402cad-066b-4e14-84e1-9777d4bc9c69 |
| User | root |
| Command | /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +csr_aliasing +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1107664071 -assert nopostproc +UVM_TESTNAME=chip_ base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/ null -cm_name 4.chip_csr_aliasing.1107664071 |
| Directory | /workspace/4.chip_csr_aliasing/latest |
| Test location | /workspace/coverage/cover_reg_top/4.chip_csr_bit_bash.3461282835 |
| Short name | T1795 |
| Test name | |
| Test status | |
| Simulation time | 9747627780 ps |
| CPU time | 1078.23 seconds |
| Started | Jun 28 08:30:25 PM PDT 24 |
| Finished | Jun 28 08:48:30 PM PDT 24 |
| Peak memory | 589312 kb |
| Host | smart-0a257998-c411-4587-8740-8acb210d0437 |
| User | root |
| Command | /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +num_test_csrs=200 +csr_bit_bash +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3461282835 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to p.vdb -cm_log /dev/null -cm_name 4.chip_csr_bit_bash.3461282835 |
| Directory | /workspace/4.chip_csr_bit_bash/latest |
| Test location | /workspace/coverage/cover_reg_top/4.chip_same_csr_outstanding.114100178 |
| Short name | T399 |
| Test name | |
| Test status | |
| Simulation time | 27623794708 ps |
| CPU time | 4135.93 seconds |
| Started | Jun 28 08:30:17 PM PDT 24 |
| Finished | Jun 28 09:39:19 PM PDT 24 |
| Peak memory | 591684 kb |
| Host | smart-3b54c74f-b91a-4216-b719-8724ce3d1238 |
| User | root |
| Command | /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +run_same_csr_outstanding +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=114100178 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c m_log /dev/null -cm_name 4.chip_same_csr_outstanding.114100178 |
| Directory | /workspace/4.chip_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/4.xbar_access_same_device.2423123406 |
| Short name | T1965 |
| Test name | |
| Test status | |
| Simulation time | 1674460481 ps |
| CPU time | 83.14 seconds |
| Started | Jun 28 08:30:31 PM PDT 24 |
| Finished | Jun 28 08:32:01 PM PDT 24 |
| Peak memory | 575236 kb |
| Host | smart-5bd4a39a-a81a-4154-9eac-a6c57d5cc591 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2423123406 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.xbar_access_same_device. 2423123406 |
| Directory | /workspace/4.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/4.xbar_access_same_device_slow_rsp.1300171640 |
| Short name | T2810 |
| Test name | |
| Test status | |
| Simulation time | 85329179599 ps |
| CPU time | 1498.42 seconds |
| Started | Jun 28 08:30:34 PM PDT 24 |
| Finished | Jun 28 08:55:38 PM PDT 24 |
| Peak memory | 575448 kb |
| Host | smart-25c59270-df73-4cf4-a1ea-88e114ab92b4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1300171640 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.xbar_access_same_d evice_slow_rsp.1300171640 |
| Directory | /workspace/4.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/4.xbar_error_and_unmapped_addr.1321853493 |
| Short name | T2349 |
| Test name | |
| Test status | |
| Simulation time | 153760784 ps |
| CPU time | 9.33 seconds |
| Started | Jun 28 08:30:30 PM PDT 24 |
| Finished | Jun 28 08:30:45 PM PDT 24 |
| Peak memory | 574200 kb |
| Host | smart-7994416f-de47-4d10-86c6-b31db8ad08c4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1321853493 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.xbar_error_and_unmapped_addr .1321853493 |
| Directory | /workspace/4.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/4.xbar_error_random.1440730514 |
| Short name | T1392 |
| Test name | |
| Test status | |
| Simulation time | 450696346 ps |
| CPU time | 41.89 seconds |
| Started | Jun 28 08:30:34 PM PDT 24 |
| Finished | Jun 28 08:31:22 PM PDT 24 |
| Peak memory | 574440 kb |
| Host | smart-dce10b7b-330f-459b-961a-90820925d441 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1440730514 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.xbar_error_random.1440730514 |
| Directory | /workspace/4.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/4.xbar_random.2116250616 |
| Short name | T2095 |
| Test name | |
| Test status | |
| Simulation time | 557420908 ps |
| CPU time | 22.88 seconds |
| Started | Jun 28 08:30:26 PM PDT 24 |
| Finished | Jun 28 08:30:57 PM PDT 24 |
| Peak memory | 574172 kb |
| Host | smart-a8c7d9ae-ecd2-4001-a9ec-fe607c414604 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2116250616 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.xbar_random.2116250616 |
| Directory | /workspace/4.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/4.xbar_random_large_delays.787773858 |
| Short name | T1936 |
| Test name | |
| Test status | |
| Simulation time | 91868197824 ps |
| CPU time | 996.21 seconds |
| Started | Jun 28 08:30:30 PM PDT 24 |
| Finished | Jun 28 08:47:13 PM PDT 24 |
| Peak memory | 575336 kb |
| Host | smart-4e834200-267d-4a5f-b1bf-7c9492b9015e |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=787773858 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.xbar_random_large_delays.787773858 |
| Directory | /workspace/4.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/4.xbar_random_slow_rsp.741255168 |
| Short name | T1892 |
| Test name | |
| Test status | |
| Simulation time | 48552955879 ps |
| CPU time | 788.54 seconds |
| Started | Jun 28 08:30:30 PM PDT 24 |
| Finished | Jun 28 08:43:45 PM PDT 24 |
| Peak memory | 574256 kb |
| Host | smart-0e0f4609-3438-4d0a-9b65-2605a43734e7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=741255168 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.xbar_random_slow_rsp.741255168 |
| Directory | /workspace/4.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/4.xbar_random_zero_delays.2339904254 |
| Short name | T2793 |
| Test name | |
| Test status | |
| Simulation time | 604634612 ps |
| CPU time | 50.55 seconds |
| Started | Jun 28 08:30:32 PM PDT 24 |
| Finished | Jun 28 08:31:29 PM PDT 24 |
| Peak memory | 575256 kb |
| Host | smart-a46e5f98-8f2e-415c-a10f-ef4f6e762eca |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2339904254 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.xbar_random_zero_dela ys.2339904254 |
| Directory | /workspace/4.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/4.xbar_same_source.212243574 |
| Short name | T1476 |
| Test name | |
| Test status | |
| Simulation time | 1117069565 ps |
| CPU time | 34.5 seconds |
| Started | Jun 28 08:30:33 PM PDT 24 |
| Finished | Jun 28 08:31:13 PM PDT 24 |
| Peak memory | 575244 kb |
| Host | smart-52faeedb-8104-423c-b231-b5f90eeda4cb |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=212243574 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.xbar_same_source.212243574 |
| Directory | /workspace/4.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/4.xbar_smoke.1219050932 |
| Short name | T2608 |
| Test name | |
| Test status | |
| Simulation time | 230608275 ps |
| CPU time | 10.05 seconds |
| Started | Jun 28 08:30:24 PM PDT 24 |
| Finished | Jun 28 08:30:39 PM PDT 24 |
| Peak memory | 565948 kb |
| Host | smart-8b056556-ef7b-4445-8e3c-6b4da3b815ac |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1219050932 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.xbar_smoke.1219050932 |
| Directory | /workspace/4.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/4.xbar_smoke_large_delays.2121495566 |
| Short name | T1398 |
| Test name | |
| Test status | |
| Simulation time | 7990577488 ps |
| CPU time | 88.47 seconds |
| Started | Jun 28 08:30:16 PM PDT 24 |
| Finished | Jun 28 08:31:48 PM PDT 24 |
| Peak memory | 574232 kb |
| Host | smart-7f7b62d5-6ccf-4f11-b6eb-538b8c591d20 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2121495566 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.xbar_smoke_large_delays.2121495566 |
| Directory | /workspace/4.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/4.xbar_smoke_slow_rsp.854063146 |
| Short name | T2446 |
| Test name | |
| Test status | |
| Simulation time | 5050313209 ps |
| CPU time | 89.44 seconds |
| Started | Jun 28 08:30:20 PM PDT 24 |
| Finished | Jun 28 08:31:55 PM PDT 24 |
| Peak memory | 574240 kb |
| Host | smart-f0194abf-210d-485e-ab52-d8d0cb7ee8a5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=854063146 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.xbar_smoke_slow_rsp.854063146 |
| Directory | /workspace/4.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/4.xbar_smoke_zero_delays.3014983893 |
| Short name | T2026 |
| Test name | |
| Test status | |
| Simulation time | 54729871 ps |
| CPU time | 6.58 seconds |
| Started | Jun 28 08:30:24 PM PDT 24 |
| Finished | Jun 28 08:30:37 PM PDT 24 |
| Peak memory | 574188 kb |
| Host | smart-a34003a7-c303-408f-b750-122f38330bb6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3014983893 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.xbar_smoke_zero_delays .3014983893 |
| Directory | /workspace/4.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/4.xbar_stress_all.2296073256 |
| Short name | T2356 |
| Test name | |
| Test status | |
| Simulation time | 1357465729 ps |
| CPU time | 127.34 seconds |
| Started | Jun 28 08:30:54 PM PDT 24 |
| Finished | Jun 28 08:33:03 PM PDT 24 |
| Peak memory | 575316 kb |
| Host | smart-7d6af4bf-eb79-4aab-a95b-99de0ac162ee |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2296073256 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.xbar_stress_all.2296073256 |
| Directory | /workspace/4.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/4.xbar_stress_all_with_error.2934083842 |
| Short name | T2248 |
| Test name | |
| Test status | |
| Simulation time | 8800628005 ps |
| CPU time | 305.53 seconds |
| Started | Jun 28 08:30:52 PM PDT 24 |
| Finished | Jun 28 08:35:59 PM PDT 24 |
| Peak memory | 574572 kb |
| Host | smart-ba5ad485-d63e-4504-9335-bee964bdedd0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2934083842 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.xbar_stress_all_with_error.2934083842 |
| Directory | /workspace/4.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/4.xbar_stress_all_with_reset_error.1670891340 |
| Short name | T2260 |
| Test name | |
| Test status | |
| Simulation time | 259434996 ps |
| CPU time | 79.85 seconds |
| Started | Jun 28 08:30:50 PM PDT 24 |
| Finished | Jun 28 08:32:12 PM PDT 24 |
| Peak memory | 574604 kb |
| Host | smart-283e3b36-5785-4685-a5a7-42727522e444 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1670891340 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.xbar_stress_all _with_reset_error.1670891340 |
| Directory | /workspace/4.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/4.xbar_unmapped_addr.1965038690 |
| Short name | T2056 |
| Test name | |
| Test status | |
| Simulation time | 124365501 ps |
| CPU time | 17.57 seconds |
| Started | Jun 28 08:30:34 PM PDT 24 |
| Finished | Jun 28 08:30:57 PM PDT 24 |
| Peak memory | 575268 kb |
| Host | smart-f2584515-2e42-4a17-9df1-cfeb85944a81 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1965038690 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.xbar_unmapped_addr.1965038690 |
| Directory | /workspace/4.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/40.xbar_access_same_device.136041894 |
| Short name | T2585 |
| Test name | |
| Test status | |
| Simulation time | 841917345 ps |
| CPU time | 74.99 seconds |
| Started | Jun 28 08:41:32 PM PDT 24 |
| Finished | Jun 28 08:42:52 PM PDT 24 |
| Peak memory | 574328 kb |
| Host | smart-447026a0-36e3-458c-a7d9-fc7fb5ccf546 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=136041894 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.xbar_access_same_device. 136041894 |
| Directory | /workspace/40.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/40.xbar_access_same_device_slow_rsp.2623387001 |
| Short name | T2068 |
| Test name | |
| Test status | |
| Simulation time | 127510525344 ps |
| CPU time | 2278.45 seconds |
| Started | Jun 28 08:41:34 PM PDT 24 |
| Finished | Jun 28 09:19:37 PM PDT 24 |
| Peak memory | 574372 kb |
| Host | smart-0efc7ce4-8595-41cf-88af-4c0ae13c9036 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2623387001 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.xbar_access_same_ device_slow_rsp.2623387001 |
| Directory | /workspace/40.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/40.xbar_error_and_unmapped_addr.2342454910 |
| Short name | T2599 |
| Test name | |
| Test status | |
| Simulation time | 155334209 ps |
| CPU time | 18.58 seconds |
| Started | Jun 28 08:41:35 PM PDT 24 |
| Finished | Jun 28 08:41:59 PM PDT 24 |
| Peak memory | 574200 kb |
| Host | smart-0317a1bf-e66a-4d73-ade9-c9eaf3c1f5c6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2342454910 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.xbar_error_and_unmapped_add r.2342454910 |
| Directory | /workspace/40.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/40.xbar_error_random.645413010 |
| Short name | T1797 |
| Test name | |
| Test status | |
| Simulation time | 590045565 ps |
| CPU time | 24.2 seconds |
| Started | Jun 28 08:41:34 PM PDT 24 |
| Finished | Jun 28 08:42:03 PM PDT 24 |
| Peak memory | 573840 kb |
| Host | smart-1bb25ac3-c386-4635-843d-71831f142535 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=645413010 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.xbar_error_random.645413010 |
| Directory | /workspace/40.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/40.xbar_random.2214459509 |
| Short name | T1752 |
| Test name | |
| Test status | |
| Simulation time | 1447834501 ps |
| CPU time | 52.49 seconds |
| Started | Jun 28 08:41:34 PM PDT 24 |
| Finished | Jun 28 08:42:31 PM PDT 24 |
| Peak memory | 575248 kb |
| Host | smart-aaf658ca-533a-4e49-b667-f285b9efa431 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2214459509 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.xbar_random.2214459509 |
| Directory | /workspace/40.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/40.xbar_random_large_delays.1440254553 |
| Short name | T2726 |
| Test name | |
| Test status | |
| Simulation time | 47209546913 ps |
| CPU time | 484.41 seconds |
| Started | Jun 28 08:41:31 PM PDT 24 |
| Finished | Jun 28 08:49:38 PM PDT 24 |
| Peak memory | 575296 kb |
| Host | smart-ae369e07-fccd-41f2-9f38-746eba2e5ffc |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1440254553 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.xbar_random_large_delays.1440254553 |
| Directory | /workspace/40.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/40.xbar_random_slow_rsp.1979884077 |
| Short name | T2023 |
| Test name | |
| Test status | |
| Simulation time | 55461059149 ps |
| CPU time | 941.27 seconds |
| Started | Jun 28 08:41:35 PM PDT 24 |
| Finished | Jun 28 08:57:21 PM PDT 24 |
| Peak memory | 574304 kb |
| Host | smart-d88972a6-aafc-4758-88a9-77558a544e01 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1979884077 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.xbar_random_slow_rsp.1979884077 |
| Directory | /workspace/40.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/40.xbar_random_zero_delays.1405886745 |
| Short name | T2763 |
| Test name | |
| Test status | |
| Simulation time | 254928139 ps |
| CPU time | 27.46 seconds |
| Started | Jun 28 08:41:32 PM PDT 24 |
| Finished | Jun 28 08:42:04 PM PDT 24 |
| Peak memory | 574200 kb |
| Host | smart-ec118cfd-ec76-46d3-a4af-1f81284d5e3f |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1405886745 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.xbar_random_zero_del ays.1405886745 |
| Directory | /workspace/40.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/40.xbar_same_source.602146931 |
| Short name | T2276 |
| Test name | |
| Test status | |
| Simulation time | 1545294506 ps |
| CPU time | 47.15 seconds |
| Started | Jun 28 08:41:34 PM PDT 24 |
| Finished | Jun 28 08:42:26 PM PDT 24 |
| Peak memory | 574180 kb |
| Host | smart-2f312c14-95f8-4829-a63f-99e18165c725 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=602146931 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.xbar_same_source.602146931 |
| Directory | /workspace/40.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/40.xbar_smoke.3180323124 |
| Short name | T2313 |
| Test name | |
| Test status | |
| Simulation time | 56761542 ps |
| CPU time | 7.7 seconds |
| Started | Jun 28 08:41:33 PM PDT 24 |
| Finished | Jun 28 08:41:45 PM PDT 24 |
| Peak memory | 574296 kb |
| Host | smart-b33411a5-fb46-453e-b5af-656c67cde2d4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3180323124 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.xbar_smoke.3180323124 |
| Directory | /workspace/40.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/40.xbar_smoke_large_delays.617048336 |
| Short name | T1320 |
| Test name | |
| Test status | |
| Simulation time | 7727658694 ps |
| CPU time | 80.76 seconds |
| Started | Jun 28 08:41:34 PM PDT 24 |
| Finished | Jun 28 08:43:00 PM PDT 24 |
| Peak memory | 574248 kb |
| Host | smart-d9b381ac-054e-41a8-ac4f-67e2e38e97a4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=617048336 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.xbar_smoke_large_delays.617048336 |
| Directory | /workspace/40.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/40.xbar_smoke_slow_rsp.589348041 |
| Short name | T2100 |
| Test name | |
| Test status | |
| Simulation time | 3983581852 ps |
| CPU time | 71.9 seconds |
| Started | Jun 28 08:41:32 PM PDT 24 |
| Finished | Jun 28 08:42:49 PM PDT 24 |
| Peak memory | 574260 kb |
| Host | smart-98326950-6ac9-41d7-9b83-a439534fea87 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=589348041 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.xbar_smoke_slow_rsp.589348041 |
| Directory | /workspace/40.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/40.xbar_smoke_zero_delays.1849313800 |
| Short name | T1470 |
| Test name | |
| Test status | |
| Simulation time | 54326908 ps |
| CPU time | 7.09 seconds |
| Started | Jun 28 08:41:35 PM PDT 24 |
| Finished | Jun 28 08:41:47 PM PDT 24 |
| Peak memory | 574192 kb |
| Host | smart-7a930a42-c697-459d-934d-1c8a39cd2b93 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1849313800 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.xbar_smoke_zero_delay s.1849313800 |
| Directory | /workspace/40.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/40.xbar_stress_all.368354481 |
| Short name | T1891 |
| Test name | |
| Test status | |
| Simulation time | 12683322849 ps |
| CPU time | 545.86 seconds |
| Started | Jun 28 08:41:35 PM PDT 24 |
| Finished | Jun 28 08:50:46 PM PDT 24 |
| Peak memory | 575428 kb |
| Host | smart-8b9e8e9a-60f2-4cd6-b434-f5e10d5a93f3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=368354481 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.xbar_stress_all.368354481 |
| Directory | /workspace/40.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/40.xbar_stress_all_with_error.3446551030 |
| Short name | T1770 |
| Test name | |
| Test status | |
| Simulation time | 12007443537 ps |
| CPU time | 481.18 seconds |
| Started | Jun 28 08:42:12 PM PDT 24 |
| Finished | Jun 28 08:50:27 PM PDT 24 |
| Peak memory | 574284 kb |
| Host | smart-76b15415-482c-4f26-b53d-f3bdcbcb7b47 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3446551030 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.xbar_stress_all_with_error.3446551030 |
| Directory | /workspace/40.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/40.xbar_stress_all_with_rand_reset.1016847064 |
| Short name | T2420 |
| Test name | |
| Test status | |
| Simulation time | 52040441 ps |
| CPU time | 71.67 seconds |
| Started | Jun 28 08:42:11 PM PDT 24 |
| Finished | Jun 28 08:43:36 PM PDT 24 |
| Peak memory | 575384 kb |
| Host | smart-5158800f-495a-4378-9fbc-ea6c7261f74f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1016847064 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.xbar_stress_all _with_rand_reset.1016847064 |
| Directory | /workspace/40.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/40.xbar_stress_all_with_reset_error.2807258567 |
| Short name | T1876 |
| Test name | |
| Test status | |
| Simulation time | 1414312817 ps |
| CPU time | 237.24 seconds |
| Started | Jun 28 08:42:12 PM PDT 24 |
| Finished | Jun 28 08:46:23 PM PDT 24 |
| Peak memory | 574360 kb |
| Host | smart-f646ba81-7d2c-4fe8-95fa-be9fc6679812 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2807258567 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.xbar_stress_al l_with_reset_error.2807258567 |
| Directory | /workspace/40.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/40.xbar_unmapped_addr.1854208693 |
| Short name | T1754 |
| Test name | |
| Test status | |
| Simulation time | 507177273 ps |
| CPU time | 25.03 seconds |
| Started | Jun 28 08:41:34 PM PDT 24 |
| Finished | Jun 28 08:42:03 PM PDT 24 |
| Peak memory | 574204 kb |
| Host | smart-06a81d41-7ac2-4aee-a731-829e5c8412b1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1854208693 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.xbar_unmapped_addr.1854208693 |
| Directory | /workspace/40.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/41.xbar_access_same_device.3611631352 |
| Short name | T2383 |
| Test name | |
| Test status | |
| Simulation time | 221438253 ps |
| CPU time | 25.59 seconds |
| Started | Jun 28 08:42:12 PM PDT 24 |
| Finished | Jun 28 08:42:52 PM PDT 24 |
| Peak memory | 575324 kb |
| Host | smart-73121242-dc07-455c-933c-1829a95d716f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3611631352 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.xbar_access_same_device .3611631352 |
| Directory | /workspace/41.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/41.xbar_access_same_device_slow_rsp.1121708618 |
| Short name | T1587 |
| Test name | |
| Test status | |
| Simulation time | 61341428505 ps |
| CPU time | 1033.86 seconds |
| Started | Jun 28 08:42:13 PM PDT 24 |
| Finished | Jun 28 08:59:45 PM PDT 24 |
| Peak memory | 575384 kb |
| Host | smart-b0977437-d15b-411f-b13b-ed8e944b7a68 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1121708618 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.xbar_access_same_ device_slow_rsp.1121708618 |
| Directory | /workspace/41.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/41.xbar_error_and_unmapped_addr.231648833 |
| Short name | T2813 |
| Test name | |
| Test status | |
| Simulation time | 119953884 ps |
| CPU time | 8.59 seconds |
| Started | Jun 28 08:42:12 PM PDT 24 |
| Finished | Jun 28 08:42:38 PM PDT 24 |
| Peak memory | 574096 kb |
| Host | smart-cd89d216-319b-41b2-9baf-f1a8313ebd98 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=231648833 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.xbar_error_and_unmapped_addr .231648833 |
| Directory | /workspace/41.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/41.xbar_error_random.1117794447 |
| Short name | T1691 |
| Test name | |
| Test status | |
| Simulation time | 1618480492 ps |
| CPU time | 52.97 seconds |
| Started | Jun 28 08:42:11 PM PDT 24 |
| Finished | Jun 28 08:43:17 PM PDT 24 |
| Peak memory | 574344 kb |
| Host | smart-330b5f34-3cc4-4935-aa02-99f02e358946 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1117794447 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.xbar_error_random.1117794447 |
| Directory | /workspace/41.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/41.xbar_random.358927980 |
| Short name | T2756 |
| Test name | |
| Test status | |
| Simulation time | 1591264676 ps |
| CPU time | 65.24 seconds |
| Started | Jun 28 08:42:12 PM PDT 24 |
| Finished | Jun 28 08:43:31 PM PDT 24 |
| Peak memory | 575284 kb |
| Host | smart-a1851c04-9802-4d47-afe6-4efdf6a4c71f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=358927980 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.xbar_random.358927980 |
| Directory | /workspace/41.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/41.xbar_random_large_delays.3489828061 |
| Short name | T1840 |
| Test name | |
| Test status | |
| Simulation time | 67980831516 ps |
| CPU time | 741.85 seconds |
| Started | Jun 28 08:42:12 PM PDT 24 |
| Finished | Jun 28 08:54:48 PM PDT 24 |
| Peak memory | 574260 kb |
| Host | smart-4a23b650-9e95-43b8-bb00-2d621f224217 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3489828061 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.xbar_random_large_delays.3489828061 |
| Directory | /workspace/41.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/41.xbar_random_slow_rsp.1890534179 |
| Short name | T1422 |
| Test name | |
| Test status | |
| Simulation time | 3071925321 ps |
| CPU time | 50.5 seconds |
| Started | Jun 28 08:42:12 PM PDT 24 |
| Finished | Jun 28 08:43:17 PM PDT 24 |
| Peak memory | 574140 kb |
| Host | smart-36cb4ae6-91be-4d8e-ae80-811ec371c3a4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1890534179 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.xbar_random_slow_rsp.1890534179 |
| Directory | /workspace/41.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/41.xbar_random_zero_delays.3748523163 |
| Short name | T2754 |
| Test name | |
| Test status | |
| Simulation time | 526956673 ps |
| CPU time | 49.52 seconds |
| Started | Jun 28 08:42:13 PM PDT 24 |
| Finished | Jun 28 08:43:19 PM PDT 24 |
| Peak memory | 575276 kb |
| Host | smart-5aa342bc-7ae1-493c-a49a-b64dc298eb62 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3748523163 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.xbar_random_zero_del ays.3748523163 |
| Directory | /workspace/41.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/41.xbar_same_source.3145885073 |
| Short name | T1546 |
| Test name | |
| Test status | |
| Simulation time | 381491071 ps |
| CPU time | 29.16 seconds |
| Started | Jun 28 08:42:12 PM PDT 24 |
| Finished | Jun 28 08:42:57 PM PDT 24 |
| Peak memory | 575208 kb |
| Host | smart-9b5d8e75-cb65-46a5-9996-2397828510be |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3145885073 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.xbar_same_source.3145885073 |
| Directory | /workspace/41.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/41.xbar_smoke.1340641229 |
| Short name | T2247 |
| Test name | |
| Test status | |
| Simulation time | 155798243 ps |
| CPU time | 8.2 seconds |
| Started | Jun 28 08:42:14 PM PDT 24 |
| Finished | Jun 28 08:42:41 PM PDT 24 |
| Peak memory | 565960 kb |
| Host | smart-0474bc88-b4ca-4d64-b833-45ca0e5c2bce |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1340641229 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.xbar_smoke.1340641229 |
| Directory | /workspace/41.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/41.xbar_smoke_large_delays.410993635 |
| Short name | T2547 |
| Test name | |
| Test status | |
| Simulation time | 8730954222 ps |
| CPU time | 88.86 seconds |
| Started | Jun 28 08:42:11 PM PDT 24 |
| Finished | Jun 28 08:43:55 PM PDT 24 |
| Peak memory | 574260 kb |
| Host | smart-0350cc20-0371-43fc-8968-46aa3fddbc3b |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=410993635 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.xbar_smoke_large_delays.410993635 |
| Directory | /workspace/41.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/41.xbar_smoke_slow_rsp.1752605291 |
| Short name | T2019 |
| Test name | |
| Test status | |
| Simulation time | 4751779180 ps |
| CPU time | 82.9 seconds |
| Started | Jun 28 08:42:11 PM PDT 24 |
| Finished | Jun 28 08:43:49 PM PDT 24 |
| Peak memory | 574232 kb |
| Host | smart-daa5ff4b-b09e-4c11-87c3-ba29950ea378 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1752605291 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.xbar_smoke_slow_rsp.1752605291 |
| Directory | /workspace/41.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/41.xbar_smoke_zero_delays.1415587674 |
| Short name | T2826 |
| Test name | |
| Test status | |
| Simulation time | 44010555 ps |
| CPU time | 5.83 seconds |
| Started | Jun 28 08:42:14 PM PDT 24 |
| Finished | Jun 28 08:42:38 PM PDT 24 |
| Peak memory | 574184 kb |
| Host | smart-202500f3-6851-42b9-9a33-e5a56c408c6f |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1415587674 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.xbar_smoke_zero_delay s.1415587674 |
| Directory | /workspace/41.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/41.xbar_stress_all.2877272258 |
| Short name | T2736 |
| Test name | |
| Test status | |
| Simulation time | 7181388510 ps |
| CPU time | 295.16 seconds |
| Started | Jun 28 08:42:12 PM PDT 24 |
| Finished | Jun 28 08:47:23 PM PDT 24 |
| Peak memory | 575444 kb |
| Host | smart-195a760d-205f-4088-aa02-f0d6448a56d9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2877272258 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.xbar_stress_all.2877272258 |
| Directory | /workspace/41.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/41.xbar_stress_all_with_error.3900998033 |
| Short name | T2109 |
| Test name | |
| Test status | |
| Simulation time | 829287730 ps |
| CPU time | 61.97 seconds |
| Started | Jun 28 08:42:13 PM PDT 24 |
| Finished | Jun 28 08:43:33 PM PDT 24 |
| Peak memory | 574456 kb |
| Host | smart-4ae9a373-975f-45e8-9d8a-9253ea549fb1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3900998033 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.xbar_stress_all_with_error.3900998033 |
| Directory | /workspace/41.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/41.xbar_stress_all_with_rand_reset.2516002935 |
| Short name | T2079 |
| Test name | |
| Test status | |
| Simulation time | 238060034 ps |
| CPU time | 35.99 seconds |
| Started | Jun 28 08:42:15 PM PDT 24 |
| Finished | Jun 28 08:43:09 PM PDT 24 |
| Peak memory | 575364 kb |
| Host | smart-d8720861-2201-4517-be34-6d34e6bbede7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2516002935 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.xbar_stress_all _with_rand_reset.2516002935 |
| Directory | /workspace/41.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/41.xbar_stress_all_with_reset_error.2690753305 |
| Short name | T2088 |
| Test name | |
| Test status | |
| Simulation time | 382562760 ps |
| CPU time | 97.84 seconds |
| Started | Jun 28 08:42:08 PM PDT 24 |
| Finished | Jun 28 08:43:55 PM PDT 24 |
| Peak memory | 576396 kb |
| Host | smart-ffb82532-f8fd-4073-82d9-fe925a2c45b7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2690753305 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.xbar_stress_al l_with_reset_error.2690753305 |
| Directory | /workspace/41.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/41.xbar_unmapped_addr.404578701 |
| Short name | T1660 |
| Test name | |
| Test status | |
| Simulation time | 1285136183 ps |
| CPU time | 58.64 seconds |
| Started | Jun 28 08:42:14 PM PDT 24 |
| Finished | Jun 28 08:43:31 PM PDT 24 |
| Peak memory | 575276 kb |
| Host | smart-6c19950b-349d-42fb-82a3-903a6c9da09e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=404578701 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.xbar_unmapped_addr.404578701 |
| Directory | /workspace/41.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/42.xbar_access_same_device.2545454960 |
| Short name | T820 |
| Test name | |
| Test status | |
| Simulation time | 3329457759 ps |
| CPU time | 158.79 seconds |
| Started | Jun 28 08:42:17 PM PDT 24 |
| Finished | Jun 28 08:45:14 PM PDT 24 |
| Peak memory | 575264 kb |
| Host | smart-c9e486e1-8ec4-4153-b48f-d3e3823043be |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2545454960 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.xbar_access_same_device .2545454960 |
| Directory | /workspace/42.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/42.xbar_access_same_device_slow_rsp.499465424 |
| Short name | T1805 |
| Test name | |
| Test status | |
| Simulation time | 62886170072 ps |
| CPU time | 1158.61 seconds |
| Started | Jun 28 08:42:17 PM PDT 24 |
| Finished | Jun 28 09:01:54 PM PDT 24 |
| Peak memory | 574264 kb |
| Host | smart-685f2dd5-bf16-429f-84fa-55405a860ae0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=499465424 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.xbar_access_same_d evice_slow_rsp.499465424 |
| Directory | /workspace/42.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/42.xbar_error_and_unmapped_addr.50392581 |
| Short name | T2654 |
| Test name | |
| Test status | |
| Simulation time | 60724169 ps |
| CPU time | 10.33 seconds |
| Started | Jun 28 08:42:15 PM PDT 24 |
| Finished | Jun 28 08:42:44 PM PDT 24 |
| Peak memory | 574200 kb |
| Host | smart-475d8195-e8b9-4c43-a8ad-2e773a7f6f95 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50392581 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.xbar_error_and_unmapped_addr.50392581 |
| Directory | /workspace/42.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/42.xbar_error_random.2529701634 |
| Short name | T2845 |
| Test name | |
| Test status | |
| Simulation time | 174848098 ps |
| CPU time | 15.17 seconds |
| Started | Jun 28 08:42:15 PM PDT 24 |
| Finished | Jun 28 08:42:49 PM PDT 24 |
| Peak memory | 573804 kb |
| Host | smart-0b060b68-0014-479d-8bcb-0d8ad29254a2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2529701634 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.xbar_error_random.2529701634 |
| Directory | /workspace/42.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/42.xbar_random.1886469365 |
| Short name | T1809 |
| Test name | |
| Test status | |
| Simulation time | 481407931 ps |
| CPU time | 19.48 seconds |
| Started | Jun 28 08:42:19 PM PDT 24 |
| Finished | Jun 28 08:42:55 PM PDT 24 |
| Peak memory | 575212 kb |
| Host | smart-87f1f2aa-e659-4aac-9a1c-57d3b75d2715 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1886469365 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.xbar_random.1886469365 |
| Directory | /workspace/42.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/42.xbar_random_large_delays.3595747820 |
| Short name | T1670 |
| Test name | |
| Test status | |
| Simulation time | 53036019462 ps |
| CPU time | 569.21 seconds |
| Started | Jun 28 08:42:17 PM PDT 24 |
| Finished | Jun 28 08:52:05 PM PDT 24 |
| Peak memory | 575348 kb |
| Host | smart-98354edd-68e5-4907-8301-93373d9b1d28 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3595747820 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.xbar_random_large_delays.3595747820 |
| Directory | /workspace/42.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/42.xbar_random_slow_rsp.2491127246 |
| Short name | T1665 |
| Test name | |
| Test status | |
| Simulation time | 24690158273 ps |
| CPU time | 426.36 seconds |
| Started | Jun 28 08:42:16 PM PDT 24 |
| Finished | Jun 28 08:49:41 PM PDT 24 |
| Peak memory | 575276 kb |
| Host | smart-89a3e606-327a-472f-9536-7fab9dea6084 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2491127246 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.xbar_random_slow_rsp.2491127246 |
| Directory | /workspace/42.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/42.xbar_random_zero_delays.191948090 |
| Short name | T2376 |
| Test name | |
| Test status | |
| Simulation time | 478649572 ps |
| CPU time | 45.89 seconds |
| Started | Jun 28 08:42:15 PM PDT 24 |
| Finished | Jun 28 08:43:19 PM PDT 24 |
| Peak memory | 575288 kb |
| Host | smart-a7627278-0f26-42bc-8313-726fd7162696 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=191948090 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.xbar_random_zero_dela ys.191948090 |
| Directory | /workspace/42.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/42.xbar_same_source.2833384209 |
| Short name | T525 |
| Test name | |
| Test status | |
| Simulation time | 259718708 ps |
| CPU time | 20.78 seconds |
| Started | Jun 28 08:42:17 PM PDT 24 |
| Finished | Jun 28 08:42:56 PM PDT 24 |
| Peak memory | 574168 kb |
| Host | smart-82a901c4-b4b0-4f43-a443-2363a2974fc4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2833384209 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.xbar_same_source.2833384209 |
| Directory | /workspace/42.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/42.xbar_smoke.2937872500 |
| Short name | T1969 |
| Test name | |
| Test status | |
| Simulation time | 172151142 ps |
| CPU time | 8.88 seconds |
| Started | Jun 28 08:42:14 PM PDT 24 |
| Finished | Jun 28 08:42:40 PM PDT 24 |
| Peak memory | 565944 kb |
| Host | smart-58bc5e10-9015-4b73-8325-b1dfc9919b07 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2937872500 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.xbar_smoke.2937872500 |
| Directory | /workspace/42.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/42.xbar_smoke_large_delays.448300930 |
| Short name | T2317 |
| Test name | |
| Test status | |
| Simulation time | 8175298946 ps |
| CPU time | 90.96 seconds |
| Started | Jun 28 08:42:13 PM PDT 24 |
| Finished | Jun 28 08:44:02 PM PDT 24 |
| Peak memory | 574252 kb |
| Host | smart-af81db55-ad69-49aa-996d-cd49861cef1d |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=448300930 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.xbar_smoke_large_delays.448300930 |
| Directory | /workspace/42.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/42.xbar_smoke_slow_rsp.423674932 |
| Short name | T1801 |
| Test name | |
| Test status | |
| Simulation time | 3443419481 ps |
| CPU time | 61.81 seconds |
| Started | Jun 28 08:42:12 PM PDT 24 |
| Finished | Jun 28 08:43:28 PM PDT 24 |
| Peak memory | 574132 kb |
| Host | smart-5f1fd3c1-c203-4ff6-98dc-712076790b38 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=423674932 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.xbar_smoke_slow_rsp.423674932 |
| Directory | /workspace/42.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/42.xbar_smoke_zero_delays.650423043 |
| Short name | T1905 |
| Test name | |
| Test status | |
| Simulation time | 34930276 ps |
| CPU time | 5.89 seconds |
| Started | Jun 28 08:42:14 PM PDT 24 |
| Finished | Jun 28 08:42:38 PM PDT 24 |
| Peak memory | 574140 kb |
| Host | smart-61861fa9-ec97-4dc9-9552-fc42889ba11b |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=650423043 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.xbar_smoke_zero_delays .650423043 |
| Directory | /workspace/42.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/42.xbar_stress_all.3377355815 |
| Short name | T1829 |
| Test name | |
| Test status | |
| Simulation time | 6378371799 ps |
| CPU time | 335.61 seconds |
| Started | Jun 28 08:42:17 PM PDT 24 |
| Finished | Jun 28 08:48:11 PM PDT 24 |
| Peak memory | 575452 kb |
| Host | smart-d078bb91-aaed-451c-a8c4-de704a890d06 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3377355815 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.xbar_stress_all.3377355815 |
| Directory | /workspace/42.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/42.xbar_stress_all_with_error.2555847087 |
| Short name | T1322 |
| Test name | |
| Test status | |
| Simulation time | 997888276 ps |
| CPU time | 42.77 seconds |
| Started | Jun 28 08:42:16 PM PDT 24 |
| Finished | Jun 28 08:43:17 PM PDT 24 |
| Peak memory | 573972 kb |
| Host | smart-5c73615d-8490-4e93-877a-20f5a9d609b8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2555847087 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.xbar_stress_all_with_error.2555847087 |
| Directory | /workspace/42.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/42.xbar_stress_all_with_rand_reset.2332654821 |
| Short name | T1497 |
| Test name | |
| Test status | |
| Simulation time | 192307078 ps |
| CPU time | 65.02 seconds |
| Started | Jun 28 08:42:18 PM PDT 24 |
| Finished | Jun 28 08:43:41 PM PDT 24 |
| Peak memory | 575380 kb |
| Host | smart-877d96f8-0041-4827-8243-05ed3509a2d3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2332654821 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.xbar_stress_all _with_rand_reset.2332654821 |
| Directory | /workspace/42.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/42.xbar_stress_all_with_reset_error.2466641831 |
| Short name | T844 |
| Test name | |
| Test status | |
| Simulation time | 6394819599 ps |
| CPU time | 412.76 seconds |
| Started | Jun 28 08:42:20 PM PDT 24 |
| Finished | Jun 28 08:49:29 PM PDT 24 |
| Peak memory | 575420 kb |
| Host | smart-ee09e206-4eff-422e-8d76-79c8642fa862 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2466641831 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.xbar_stress_al l_with_reset_error.2466641831 |
| Directory | /workspace/42.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/42.xbar_unmapped_addr.601313810 |
| Short name | T1996 |
| Test name | |
| Test status | |
| Simulation time | 113834279 ps |
| CPU time | 16.66 seconds |
| Started | Jun 28 08:42:16 PM PDT 24 |
| Finished | Jun 28 08:42:51 PM PDT 24 |
| Peak memory | 575292 kb |
| Host | smart-6900b82f-41ef-4888-a01e-62f3982bc477 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=601313810 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.xbar_unmapped_addr.601313810 |
| Directory | /workspace/42.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/43.xbar_access_same_device.2095588617 |
| Short name | T800 |
| Test name | |
| Test status | |
| Simulation time | 2136911056 ps |
| CPU time | 104.81 seconds |
| Started | Jun 28 08:42:18 PM PDT 24 |
| Finished | Jun 28 08:44:20 PM PDT 24 |
| Peak memory | 574220 kb |
| Host | smart-d0062a9d-0575-4171-abe8-10137413adca |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2095588617 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.xbar_access_same_device .2095588617 |
| Directory | /workspace/43.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/43.xbar_access_same_device_slow_rsp.1689310938 |
| Short name | T2828 |
| Test name | |
| Test status | |
| Simulation time | 108108442767 ps |
| CPU time | 1891.16 seconds |
| Started | Jun 28 08:42:19 PM PDT 24 |
| Finished | Jun 28 09:14:07 PM PDT 24 |
| Peak memory | 574284 kb |
| Host | smart-7ef29e4b-2e0f-4133-af99-c1c5b85ed3d7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1689310938 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.xbar_access_same_ device_slow_rsp.1689310938 |
| Directory | /workspace/43.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/43.xbar_error_and_unmapped_addr.4147149322 |
| Short name | T1505 |
| Test name | |
| Test status | |
| Simulation time | 162677628 ps |
| CPU time | 10.28 seconds |
| Started | Jun 28 08:42:14 PM PDT 24 |
| Finished | Jun 28 08:42:43 PM PDT 24 |
| Peak memory | 574196 kb |
| Host | smart-09ae54f1-de27-4196-903f-a31ccbbf5868 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4147149322 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.xbar_error_and_unmapped_add r.4147149322 |
| Directory | /workspace/43.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/43.xbar_error_random.2867124913 |
| Short name | T1718 |
| Test name | |
| Test status | |
| Simulation time | 1304627132 ps |
| CPU time | 45.55 seconds |
| Started | Jun 28 08:42:14 PM PDT 24 |
| Finished | Jun 28 08:43:18 PM PDT 24 |
| Peak memory | 573844 kb |
| Host | smart-f929542b-4f38-4766-9838-c4ef0a25f988 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2867124913 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.xbar_error_random.2867124913 |
| Directory | /workspace/43.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/43.xbar_random.667759823 |
| Short name | T564 |
| Test name | |
| Test status | |
| Simulation time | 341929448 ps |
| CPU time | 28.9 seconds |
| Started | Jun 28 08:42:16 PM PDT 24 |
| Finished | Jun 28 08:43:04 PM PDT 24 |
| Peak memory | 575244 kb |
| Host | smart-d49ecc98-fcea-4a1b-a3a1-dfb243db0107 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=667759823 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.xbar_random.667759823 |
| Directory | /workspace/43.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/43.xbar_random_large_delays.3635671179 |
| Short name | T1919 |
| Test name | |
| Test status | |
| Simulation time | 91374697565 ps |
| CPU time | 916.53 seconds |
| Started | Jun 28 08:42:14 PM PDT 24 |
| Finished | Jun 28 08:57:49 PM PDT 24 |
| Peak memory | 574272 kb |
| Host | smart-93449455-290a-4acd-b757-13cb8ff17884 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3635671179 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.xbar_random_large_delays.3635671179 |
| Directory | /workspace/43.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/43.xbar_random_slow_rsp.1451795544 |
| Short name | T2396 |
| Test name | |
| Test status | |
| Simulation time | 34123397865 ps |
| CPU time | 582.63 seconds |
| Started | Jun 28 08:42:19 PM PDT 24 |
| Finished | Jun 28 08:52:19 PM PDT 24 |
| Peak memory | 574276 kb |
| Host | smart-701e431b-b226-4fb1-a5a0-6d6ce990022b |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1451795544 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.xbar_random_slow_rsp.1451795544 |
| Directory | /workspace/43.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/43.xbar_random_zero_delays.9858590 |
| Short name | T2121 |
| Test name | |
| Test status | |
| Simulation time | 499491441 ps |
| CPU time | 46.11 seconds |
| Started | Jun 28 08:42:18 PM PDT 24 |
| Finished | Jun 28 08:43:22 PM PDT 24 |
| Peak memory | 575232 kb |
| Host | smart-572a4064-b97e-4cc1-9285-e4a0670c106e |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=9858590 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.xbar_random_zero_delays.9858590 |
| Directory | /workspace/43.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/43.xbar_same_source.1268691686 |
| Short name | T1523 |
| Test name | |
| Test status | |
| Simulation time | 149278204 ps |
| CPU time | 14.62 seconds |
| Started | Jun 28 08:42:19 PM PDT 24 |
| Finished | Jun 28 08:42:51 PM PDT 24 |
| Peak memory | 574108 kb |
| Host | smart-308b82e0-c9de-436e-aae1-12d6ae28b2a5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1268691686 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.xbar_same_source.1268691686 |
| Directory | /workspace/43.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/43.xbar_smoke.3525626926 |
| Short name | T2390 |
| Test name | |
| Test status | |
| Simulation time | 50122807 ps |
| CPU time | 6.66 seconds |
| Started | Jun 28 08:42:14 PM PDT 24 |
| Finished | Jun 28 08:42:39 PM PDT 24 |
| Peak memory | 565956 kb |
| Host | smart-e2429b0f-ff5a-41a4-bd3f-ca5d27b24f8e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3525626926 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.xbar_smoke.3525626926 |
| Directory | /workspace/43.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/43.xbar_smoke_large_delays.3647251666 |
| Short name | T1327 |
| Test name | |
| Test status | |
| Simulation time | 7134947395 ps |
| CPU time | 74.62 seconds |
| Started | Jun 28 08:42:20 PM PDT 24 |
| Finished | Jun 28 08:43:51 PM PDT 24 |
| Peak memory | 574260 kb |
| Host | smart-b62883dc-823c-4bd9-9672-04243ebb8cce |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3647251666 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.xbar_smoke_large_delays.3647251666 |
| Directory | /workspace/43.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/43.xbar_smoke_slow_rsp.804255015 |
| Short name | T2799 |
| Test name | |
| Test status | |
| Simulation time | 5335903718 ps |
| CPU time | 90.68 seconds |
| Started | Jun 28 08:42:19 PM PDT 24 |
| Finished | Jun 28 08:44:07 PM PDT 24 |
| Peak memory | 574132 kb |
| Host | smart-352ca50b-c935-4014-91e6-31e4d6c9e7f4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=804255015 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.xbar_smoke_slow_rsp.804255015 |
| Directory | /workspace/43.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/43.xbar_smoke_zero_delays.2932314296 |
| Short name | T2646 |
| Test name | |
| Test status | |
| Simulation time | 42894662 ps |
| CPU time | 6.18 seconds |
| Started | Jun 28 08:42:20 PM PDT 24 |
| Finished | Jun 28 08:42:43 PM PDT 24 |
| Peak memory | 574148 kb |
| Host | smart-3d6734de-d7a7-47ad-8aea-c13cdaff2842 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2932314296 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.xbar_smoke_zero_delay s.2932314296 |
| Directory | /workspace/43.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/43.xbar_stress_all.2711557425 |
| Short name | T1646 |
| Test name | |
| Test status | |
| Simulation time | 4125054607 ps |
| CPU time | 163.91 seconds |
| Started | Jun 28 08:42:13 PM PDT 24 |
| Finished | Jun 28 08:45:13 PM PDT 24 |
| Peak memory | 575560 kb |
| Host | smart-33dc6c62-f9ea-4fd5-bd07-7c29646b1798 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2711557425 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.xbar_stress_all.2711557425 |
| Directory | /workspace/43.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/43.xbar_stress_all_with_error.2176980321 |
| Short name | T2659 |
| Test name | |
| Test status | |
| Simulation time | 7964243600 ps |
| CPU time | 326.38 seconds |
| Started | Jun 28 08:42:50 PM PDT 24 |
| Finished | Jun 28 08:48:28 PM PDT 24 |
| Peak memory | 574340 kb |
| Host | smart-24174c11-0d0f-447a-b4e7-f91dda6e6d26 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2176980321 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.xbar_stress_all_with_error.2176980321 |
| Directory | /workspace/43.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/43.xbar_stress_all_with_rand_reset.1931965386 |
| Short name | T2076 |
| Test name | |
| Test status | |
| Simulation time | 1229335149 ps |
| CPU time | 293.91 seconds |
| Started | Jun 28 08:42:13 PM PDT 24 |
| Finished | Jun 28 08:47:23 PM PDT 24 |
| Peak memory | 574332 kb |
| Host | smart-5c5108ac-9622-48ec-9866-05d2e4d21743 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1931965386 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.xbar_stress_all _with_rand_reset.1931965386 |
| Directory | /workspace/43.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/43.xbar_stress_all_with_reset_error.666623875 |
| Short name | T2293 |
| Test name | |
| Test status | |
| Simulation time | 636323547 ps |
| CPU time | 214.37 seconds |
| Started | Jun 28 08:42:55 PM PDT 24 |
| Finished | Jun 28 08:46:45 PM PDT 24 |
| Peak memory | 574344 kb |
| Host | smart-808eedb6-fd07-4cbb-890f-5facb38e1419 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=666623875 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.xbar_stress_all _with_reset_error.666623875 |
| Directory | /workspace/43.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/43.xbar_unmapped_addr.634952543 |
| Short name | T2197 |
| Test name | |
| Test status | |
| Simulation time | 124771350 ps |
| CPU time | 16.98 seconds |
| Started | Jun 28 08:42:18 PM PDT 24 |
| Finished | Jun 28 08:42:53 PM PDT 24 |
| Peak memory | 575272 kb |
| Host | smart-c6d4d30c-69e6-455c-88c4-a2367d38c700 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=634952543 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.xbar_unmapped_addr.634952543 |
| Directory | /workspace/43.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/44.xbar_access_same_device.3079138462 |
| Short name | T1864 |
| Test name | |
| Test status | |
| Simulation time | 2572048591 ps |
| CPU time | 103.98 seconds |
| Started | Jun 28 08:42:44 PM PDT 24 |
| Finished | Jun 28 08:44:30 PM PDT 24 |
| Peak memory | 575292 kb |
| Host | smart-b27aaec4-1def-4915-ac70-cd95399da84d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3079138462 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.xbar_access_same_device .3079138462 |
| Directory | /workspace/44.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/44.xbar_access_same_device_slow_rsp.941422490 |
| Short name | T2797 |
| Test name | |
| Test status | |
| Simulation time | 28411834190 ps |
| CPU time | 501.37 seconds |
| Started | Jun 28 08:42:54 PM PDT 24 |
| Finished | Jun 28 08:51:31 PM PDT 24 |
| Peak memory | 575316 kb |
| Host | smart-91efe7d3-ddaf-41bc-9ea0-257e1dac0d03 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=941422490 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.xbar_access_same_d evice_slow_rsp.941422490 |
| Directory | /workspace/44.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/44.xbar_error_and_unmapped_addr.4072447040 |
| Short name | T1390 |
| Test name | |
| Test status | |
| Simulation time | 640417779 ps |
| CPU time | 27.46 seconds |
| Started | Jun 28 08:42:47 PM PDT 24 |
| Finished | Jun 28 08:43:21 PM PDT 24 |
| Peak memory | 574204 kb |
| Host | smart-a6a20e08-46e0-44b3-a3cb-9d8e4d65ddab |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4072447040 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.xbar_error_and_unmapped_add r.4072447040 |
| Directory | /workspace/44.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/44.xbar_error_random.874029358 |
| Short name | T2855 |
| Test name | |
| Test status | |
| Simulation time | 1336348970 ps |
| CPU time | 51.89 seconds |
| Started | Jun 28 08:42:54 PM PDT 24 |
| Finished | Jun 28 08:44:01 PM PDT 24 |
| Peak memory | 574416 kb |
| Host | smart-8444c6dc-016e-46d8-91b1-9f520503d514 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=874029358 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.xbar_error_random.874029358 |
| Directory | /workspace/44.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/44.xbar_random.3622827139 |
| Short name | T518 |
| Test name | |
| Test status | |
| Simulation time | 118293897 ps |
| CPU time | 8.18 seconds |
| Started | Jun 28 08:42:48 PM PDT 24 |
| Finished | Jun 28 08:43:04 PM PDT 24 |
| Peak memory | 565872 kb |
| Host | smart-85e01ee5-fb6b-4e2d-b830-01454eb1f524 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3622827139 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.xbar_random.3622827139 |
| Directory | /workspace/44.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/44.xbar_random_large_delays.711200915 |
| Short name | T626 |
| Test name | |
| Test status | |
| Simulation time | 100027372842 ps |
| CPU time | 1105.65 seconds |
| Started | Jun 28 08:42:44 PM PDT 24 |
| Finished | Jun 28 09:01:12 PM PDT 24 |
| Peak memory | 575312 kb |
| Host | smart-6099a25a-fb2c-43ef-892d-5934abf60516 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=711200915 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.xbar_random_large_delays.711200915 |
| Directory | /workspace/44.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/44.xbar_random_slow_rsp.3900612605 |
| Short name | T1450 |
| Test name | |
| Test status | |
| Simulation time | 14139056298 ps |
| CPU time | 263.45 seconds |
| Started | Jun 28 08:42:44 PM PDT 24 |
| Finished | Jun 28 08:47:10 PM PDT 24 |
| Peak memory | 575348 kb |
| Host | smart-60988035-8015-4cd6-bfeb-b35f1c3e695c |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3900612605 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.xbar_random_slow_rsp.3900612605 |
| Directory | /workspace/44.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/44.xbar_random_zero_delays.3868575755 |
| Short name | T2168 |
| Test name | |
| Test status | |
| Simulation time | 616007407 ps |
| CPU time | 53.82 seconds |
| Started | Jun 28 08:42:46 PM PDT 24 |
| Finished | Jun 28 08:43:43 PM PDT 24 |
| Peak memory | 574200 kb |
| Host | smart-5d4cb3bc-8211-4c3f-9ab0-76c8b0992a92 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3868575755 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.xbar_random_zero_del ays.3868575755 |
| Directory | /workspace/44.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/44.xbar_same_source.1107098099 |
| Short name | T1987 |
| Test name | |
| Test status | |
| Simulation time | 869386010 ps |
| CPU time | 27.94 seconds |
| Started | Jun 28 08:42:56 PM PDT 24 |
| Finished | Jun 28 08:43:40 PM PDT 24 |
| Peak memory | 575220 kb |
| Host | smart-e1264e0a-583e-48a7-9db7-653c1498b07e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1107098099 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.xbar_same_source.1107098099 |
| Directory | /workspace/44.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/44.xbar_smoke.3388900227 |
| Short name | T1311 |
| Test name | |
| Test status | |
| Simulation time | 220372161 ps |
| CPU time | 10.22 seconds |
| Started | Jun 28 08:42:52 PM PDT 24 |
| Finished | Jun 28 08:43:17 PM PDT 24 |
| Peak memory | 574196 kb |
| Host | smart-963a44bb-2f6b-4b1a-ba9d-58f686964c8a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3388900227 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.xbar_smoke.3388900227 |
| Directory | /workspace/44.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/44.xbar_smoke_large_delays.2557007461 |
| Short name | T1483 |
| Test name | |
| Test status | |
| Simulation time | 8645582477 ps |
| CPU time | 100.83 seconds |
| Started | Jun 28 08:42:46 PM PDT 24 |
| Finished | Jun 28 08:44:30 PM PDT 24 |
| Peak memory | 574256 kb |
| Host | smart-3494c3c9-214e-455f-9ff5-80b0e8371f21 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2557007461 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.xbar_smoke_large_delays.2557007461 |
| Directory | /workspace/44.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/44.xbar_smoke_slow_rsp.2591474274 |
| Short name | T2690 |
| Test name | |
| Test status | |
| Simulation time | 4914117712 ps |
| CPU time | 88.42 seconds |
| Started | Jun 28 08:42:57 PM PDT 24 |
| Finished | Jun 28 08:44:42 PM PDT 24 |
| Peak memory | 566016 kb |
| Host | smart-65c67a2e-bc9c-481c-ad14-d0fbd7f889cf |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2591474274 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.xbar_smoke_slow_rsp.2591474274 |
| Directory | /workspace/44.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/44.xbar_smoke_zero_delays.1844994695 |
| Short name | T1407 |
| Test name | |
| Test status | |
| Simulation time | 37965877 ps |
| CPU time | 6.33 seconds |
| Started | Jun 28 08:42:56 PM PDT 24 |
| Finished | Jun 28 08:43:18 PM PDT 24 |
| Peak memory | 574176 kb |
| Host | smart-37ecc45c-fa5a-471f-a37d-679761158a8d |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1844994695 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.xbar_smoke_zero_delay s.1844994695 |
| Directory | /workspace/44.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/44.xbar_stress_all.2813963687 |
| Short name | T2371 |
| Test name | |
| Test status | |
| Simulation time | 1752533276 ps |
| CPU time | 136.84 seconds |
| Started | Jun 28 08:42:58 PM PDT 24 |
| Finished | Jun 28 08:45:31 PM PDT 24 |
| Peak memory | 575392 kb |
| Host | smart-6a3337b8-3cba-46e9-9904-57fbce08f3ab |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2813963687 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.xbar_stress_all.2813963687 |
| Directory | /workspace/44.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/44.xbar_stress_all_with_error.1455487744 |
| Short name | T1547 |
| Test name | |
| Test status | |
| Simulation time | 3568700260 ps |
| CPU time | 140.88 seconds |
| Started | Jun 28 08:42:46 PM PDT 24 |
| Finished | Jun 28 08:45:10 PM PDT 24 |
| Peak memory | 574004 kb |
| Host | smart-d0740035-abd6-483e-8af3-1e1742b4dafe |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1455487744 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.xbar_stress_all_with_error.1455487744 |
| Directory | /workspace/44.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/44.xbar_stress_all_with_rand_reset.891039952 |
| Short name | T2451 |
| Test name | |
| Test status | |
| Simulation time | 2220199597 ps |
| CPU time | 294.18 seconds |
| Started | Jun 28 08:42:47 PM PDT 24 |
| Finished | Jun 28 08:47:48 PM PDT 24 |
| Peak memory | 575456 kb |
| Host | smart-984fd888-88b9-411d-9056-57c8448fe90d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=891039952 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_res et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.xbar_stress_all_ with_rand_reset.891039952 |
| Directory | /workspace/44.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/44.xbar_stress_all_with_reset_error.2202622976 |
| Short name | T839 |
| Test name | |
| Test status | |
| Simulation time | 2062839173 ps |
| CPU time | 344.99 seconds |
| Started | Jun 28 08:42:55 PM PDT 24 |
| Finished | Jun 28 08:48:56 PM PDT 24 |
| Peak memory | 574324 kb |
| Host | smart-f587234b-03a8-4ce8-aa08-63caf35c7bcf |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2202622976 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.xbar_stress_al l_with_reset_error.2202622976 |
| Directory | /workspace/44.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/44.xbar_unmapped_addr.3259829132 |
| Short name | T1452 |
| Test name | |
| Test status | |
| Simulation time | 356360089 ps |
| CPU time | 38.32 seconds |
| Started | Jun 28 08:42:46 PM PDT 24 |
| Finished | Jun 28 08:43:27 PM PDT 24 |
| Peak memory | 575312 kb |
| Host | smart-d98c290a-f73e-43b7-a791-e5fcfe13793a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3259829132 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.xbar_unmapped_addr.3259829132 |
| Directory | /workspace/44.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/45.xbar_access_same_device.3317668568 |
| Short name | T1866 |
| Test name | |
| Test status | |
| Simulation time | 352382835 ps |
| CPU time | 29.58 seconds |
| Started | Jun 28 08:42:47 PM PDT 24 |
| Finished | Jun 28 08:43:23 PM PDT 24 |
| Peak memory | 575240 kb |
| Host | smart-4a186af7-0a13-41aa-a660-a6016b4d2db0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3317668568 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.xbar_access_same_device .3317668568 |
| Directory | /workspace/45.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/45.xbar_access_same_device_slow_rsp.3537699574 |
| Short name | T821 |
| Test name | |
| Test status | |
| Simulation time | 74332128099 ps |
| CPU time | 1324.71 seconds |
| Started | Jun 28 08:42:48 PM PDT 24 |
| Finished | Jun 28 09:04:59 PM PDT 24 |
| Peak memory | 575328 kb |
| Host | smart-f2778c9c-d1d3-4479-92c8-7586174b13c0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3537699574 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.xbar_access_same_ device_slow_rsp.3537699574 |
| Directory | /workspace/45.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/45.xbar_error_and_unmapped_addr.1664946870 |
| Short name | T531 |
| Test name | |
| Test status | |
| Simulation time | 1255542471 ps |
| CPU time | 53.29 seconds |
| Started | Jun 28 08:42:45 PM PDT 24 |
| Finished | Jun 28 08:43:41 PM PDT 24 |
| Peak memory | 574444 kb |
| Host | smart-81434559-9e5c-4c74-aa97-f47f21e4dfff |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1664946870 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.xbar_error_and_unmapped_add r.1664946870 |
| Directory | /workspace/45.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/45.xbar_error_random.533901840 |
| Short name | T1412 |
| Test name | |
| Test status | |
| Simulation time | 2004282249 ps |
| CPU time | 70 seconds |
| Started | Jun 28 08:42:45 PM PDT 24 |
| Finished | Jun 28 08:43:57 PM PDT 24 |
| Peak memory | 574432 kb |
| Host | smart-2ff34104-2701-4140-84d8-21fa13575acf |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=533901840 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.xbar_error_random.533901840 |
| Directory | /workspace/45.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/45.xbar_random.1368910636 |
| Short name | T1518 |
| Test name | |
| Test status | |
| Simulation time | 584971611 ps |
| CPU time | 56.07 seconds |
| Started | Jun 28 08:42:45 PM PDT 24 |
| Finished | Jun 28 08:43:43 PM PDT 24 |
| Peak memory | 575240 kb |
| Host | smart-0638a3bd-ec2b-4261-9fa2-659c508f2024 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1368910636 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.xbar_random.1368910636 |
| Directory | /workspace/45.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/45.xbar_random_large_delays.2869817240 |
| Short name | T1603 |
| Test name | |
| Test status | |
| Simulation time | 46792571726 ps |
| CPU time | 482.4 seconds |
| Started | Jun 28 08:42:56 PM PDT 24 |
| Finished | Jun 28 08:51:15 PM PDT 24 |
| Peak memory | 575344 kb |
| Host | smart-9289a855-6e97-4f98-a7e1-bd5b16dd8fb2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2869817240 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.xbar_random_large_delays.2869817240 |
| Directory | /workspace/45.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/45.xbar_random_slow_rsp.2544606495 |
| Short name | T2683 |
| Test name | |
| Test status | |
| Simulation time | 43825197283 ps |
| CPU time | 761.08 seconds |
| Started | Jun 28 08:42:46 PM PDT 24 |
| Finished | Jun 28 08:55:31 PM PDT 24 |
| Peak memory | 574248 kb |
| Host | smart-650a2327-f6b4-4c50-b6b9-72c1c4a2f353 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2544606495 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.xbar_random_slow_rsp.2544606495 |
| Directory | /workspace/45.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/45.xbar_random_zero_delays.2810771089 |
| Short name | T2441 |
| Test name | |
| Test status | |
| Simulation time | 519089148 ps |
| CPU time | 53.08 seconds |
| Started | Jun 28 08:42:44 PM PDT 24 |
| Finished | Jun 28 08:43:40 PM PDT 24 |
| Peak memory | 575168 kb |
| Host | smart-f547e980-76b7-45f4-a463-2537a892ec46 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2810771089 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.xbar_random_zero_del ays.2810771089 |
| Directory | /workspace/45.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/45.xbar_same_source.933431524 |
| Short name | T1731 |
| Test name | |
| Test status | |
| Simulation time | 557138675 ps |
| CPU time | 53.13 seconds |
| Started | Jun 28 08:42:45 PM PDT 24 |
| Finished | Jun 28 08:43:40 PM PDT 24 |
| Peak memory | 575228 kb |
| Host | smart-b8c9de93-a607-45fe-b660-afb29a5e69e8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=933431524 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.xbar_same_source.933431524 |
| Directory | /workspace/45.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/45.xbar_smoke.1173231986 |
| Short name | T1572 |
| Test name | |
| Test status | |
| Simulation time | 52661497 ps |
| CPU time | 7.35 seconds |
| Started | Jun 28 08:42:43 PM PDT 24 |
| Finished | Jun 28 08:42:53 PM PDT 24 |
| Peak memory | 574188 kb |
| Host | smart-59f34788-cd4f-4402-94b2-a37cc4927fb7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1173231986 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.xbar_smoke.1173231986 |
| Directory | /workspace/45.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/45.xbar_smoke_large_delays.1352568627 |
| Short name | T2164 |
| Test name | |
| Test status | |
| Simulation time | 7811758530 ps |
| CPU time | 88.05 seconds |
| Started | Jun 28 08:42:48 PM PDT 24 |
| Finished | Jun 28 08:44:24 PM PDT 24 |
| Peak memory | 574260 kb |
| Host | smart-8ee56dba-f1f6-4288-ad14-de10add317e4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1352568627 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.xbar_smoke_large_delays.1352568627 |
| Directory | /workspace/45.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/45.xbar_smoke_slow_rsp.1394296492 |
| Short name | T1708 |
| Test name | |
| Test status | |
| Simulation time | 4622233742 ps |
| CPU time | 84.07 seconds |
| Started | Jun 28 08:42:47 PM PDT 24 |
| Finished | Jun 28 08:44:18 PM PDT 24 |
| Peak memory | 574264 kb |
| Host | smart-66b0781b-e28a-486b-a8d9-db1e2a42dda2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1394296492 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.xbar_smoke_slow_rsp.1394296492 |
| Directory | /workspace/45.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/45.xbar_smoke_zero_delays.2157025166 |
| Short name | T1628 |
| Test name | |
| Test status | |
| Simulation time | 56793390 ps |
| CPU time | 7.65 seconds |
| Started | Jun 28 08:42:48 PM PDT 24 |
| Finished | Jun 28 08:43:04 PM PDT 24 |
| Peak memory | 565956 kb |
| Host | smart-2499a7b6-43b5-414f-aa94-8086415327fa |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2157025166 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.xbar_smoke_zero_delay s.2157025166 |
| Directory | /workspace/45.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/45.xbar_stress_all.3822221291 |
| Short name | T1952 |
| Test name | |
| Test status | |
| Simulation time | 7198479325 ps |
| CPU time | 330.33 seconds |
| Started | Jun 28 08:42:47 PM PDT 24 |
| Finished | Jun 28 08:48:23 PM PDT 24 |
| Peak memory | 575444 kb |
| Host | smart-cc3f0f9d-3caf-4aa5-8616-938f5797501e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3822221291 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.xbar_stress_all.3822221291 |
| Directory | /workspace/45.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/45.xbar_stress_all_with_error.2677026332 |
| Short name | T1463 |
| Test name | |
| Test status | |
| Simulation time | 857091874 ps |
| CPU time | 71.88 seconds |
| Started | Jun 28 08:42:56 PM PDT 24 |
| Finished | Jun 28 08:44:24 PM PDT 24 |
| Peak memory | 574528 kb |
| Host | smart-969c41d9-46c6-448c-a698-4d0efe91f6cf |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2677026332 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.xbar_stress_all_with_error.2677026332 |
| Directory | /workspace/45.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/45.xbar_stress_all_with_rand_reset.1814452627 |
| Short name | T2603 |
| Test name | |
| Test status | |
| Simulation time | 17631638010 ps |
| CPU time | 938.79 seconds |
| Started | Jun 28 08:42:59 PM PDT 24 |
| Finished | Jun 28 08:58:53 PM PDT 24 |
| Peak memory | 575396 kb |
| Host | smart-0075c1cc-943d-4ea9-a2e7-df855ee5e595 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1814452627 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.xbar_stress_all _with_rand_reset.1814452627 |
| Directory | /workspace/45.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/45.xbar_stress_all_with_reset_error.2803462561 |
| Short name | T1409 |
| Test name | |
| Test status | |
| Simulation time | 175438622 ps |
| CPU time | 87.36 seconds |
| Started | Jun 28 08:42:58 PM PDT 24 |
| Finished | Jun 28 08:44:41 PM PDT 24 |
| Peak memory | 574364 kb |
| Host | smart-22cd4f45-8c44-46de-b956-aa6ed41218ce |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2803462561 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.xbar_stress_al l_with_reset_error.2803462561 |
| Directory | /workspace/45.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/45.xbar_unmapped_addr.4093747657 |
| Short name | T1730 |
| Test name | |
| Test status | |
| Simulation time | 170930748 ps |
| CPU time | 24.86 seconds |
| Started | Jun 28 08:42:49 PM PDT 24 |
| Finished | Jun 28 08:43:25 PM PDT 24 |
| Peak memory | 574156 kb |
| Host | smart-0c46c15d-f528-4492-a450-6c207a1a8e1e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4093747657 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.xbar_unmapped_addr.4093747657 |
| Directory | /workspace/45.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/46.xbar_access_same_device.2792692692 |
| Short name | T813 |
| Test name | |
| Test status | |
| Simulation time | 262958464 ps |
| CPU time | 22.06 seconds |
| Started | Jun 28 08:42:56 PM PDT 24 |
| Finished | Jun 28 08:43:34 PM PDT 24 |
| Peak memory | 575244 kb |
| Host | smart-87f330af-ed14-4c90-a0a3-5fe23e201755 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2792692692 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.xbar_access_same_device .2792692692 |
| Directory | /workspace/46.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/46.xbar_access_same_device_slow_rsp.3153630820 |
| Short name | T2144 |
| Test name | |
| Test status | |
| Simulation time | 79580974844 ps |
| CPU time | 1369.09 seconds |
| Started | Jun 28 08:42:48 PM PDT 24 |
| Finished | Jun 28 09:05:45 PM PDT 24 |
| Peak memory | 575332 kb |
| Host | smart-b6aa9a81-fc6e-4a37-b190-8033af859360 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3153630820 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.xbar_access_same_ device_slow_rsp.3153630820 |
| Directory | /workspace/46.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/46.xbar_error_and_unmapped_addr.1880849755 |
| Short name | T2734 |
| Test name | |
| Test status | |
| Simulation time | 286086141 ps |
| CPU time | 15.04 seconds |
| Started | Jun 28 08:42:57 PM PDT 24 |
| Finished | Jun 28 08:43:28 PM PDT 24 |
| Peak memory | 573872 kb |
| Host | smart-f31fee11-95ad-4f58-b02a-38f2d42c4569 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1880849755 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.xbar_error_and_unmapped_add r.1880849755 |
| Directory | /workspace/46.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/46.xbar_error_random.1990690189 |
| Short name | T1358 |
| Test name | |
| Test status | |
| Simulation time | 368320084 ps |
| CPU time | 30 seconds |
| Started | Jun 28 08:42:53 PM PDT 24 |
| Finished | Jun 28 08:43:39 PM PDT 24 |
| Peak memory | 573856 kb |
| Host | smart-28af5f4c-d61e-4ca2-9416-26c7f7772250 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1990690189 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.xbar_error_random.1990690189 |
| Directory | /workspace/46.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/46.xbar_random.2193664330 |
| Short name | T568 |
| Test name | |
| Test status | |
| Simulation time | 2057087646 ps |
| CPU time | 78.13 seconds |
| Started | Jun 28 08:42:46 PM PDT 24 |
| Finished | Jun 28 08:44:10 PM PDT 24 |
| Peak memory | 575244 kb |
| Host | smart-52e2ac3b-5432-4f8d-9a0f-51422197fc66 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2193664330 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.xbar_random.2193664330 |
| Directory | /workspace/46.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/46.xbar_random_large_delays.4239277574 |
| Short name | T2477 |
| Test name | |
| Test status | |
| Simulation time | 42890908048 ps |
| CPU time | 463.71 seconds |
| Started | Jun 28 08:42:46 PM PDT 24 |
| Finished | Jun 28 08:50:33 PM PDT 24 |
| Peak memory | 575340 kb |
| Host | smart-14ceeba9-445d-4935-beaa-f8c9ed92dd22 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4239277574 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.xbar_random_large_delays.4239277574 |
| Directory | /workspace/46.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/46.xbar_random_slow_rsp.1456499444 |
| Short name | T2020 |
| Test name | |
| Test status | |
| Simulation time | 24887618706 ps |
| CPU time | 461.46 seconds |
| Started | Jun 28 08:42:55 PM PDT 24 |
| Finished | Jun 28 08:50:53 PM PDT 24 |
| Peak memory | 575320 kb |
| Host | smart-151c209c-08d0-451f-af43-b6afd21191e0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1456499444 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.xbar_random_slow_rsp.1456499444 |
| Directory | /workspace/46.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/46.xbar_random_zero_delays.1461990027 |
| Short name | T2435 |
| Test name | |
| Test status | |
| Simulation time | 159964608 ps |
| CPU time | 17.31 seconds |
| Started | Jun 28 08:42:46 PM PDT 24 |
| Finished | Jun 28 08:43:07 PM PDT 24 |
| Peak memory | 574152 kb |
| Host | smart-631cc5f9-b92e-4a5d-a309-23a0d1ff099b |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1461990027 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.xbar_random_zero_del ays.1461990027 |
| Directory | /workspace/46.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/46.xbar_same_source.3137817918 |
| Short name | T2182 |
| Test name | |
| Test status | |
| Simulation time | 304515818 ps |
| CPU time | 21.41 seconds |
| Started | Jun 28 08:42:44 PM PDT 24 |
| Finished | Jun 28 08:43:08 PM PDT 24 |
| Peak memory | 575228 kb |
| Host | smart-c5760d32-366f-4973-8a1a-bb39311b33c7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3137817918 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.xbar_same_source.3137817918 |
| Directory | /workspace/46.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/46.xbar_smoke.3541107863 |
| Short name | T2008 |
| Test name | |
| Test status | |
| Simulation time | 187616771 ps |
| CPU time | 8.86 seconds |
| Started | Jun 28 08:42:46 PM PDT 24 |
| Finished | Jun 28 08:42:59 PM PDT 24 |
| Peak memory | 574184 kb |
| Host | smart-5699c9e5-016f-4d16-8303-64a3ce3669b1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3541107863 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.xbar_smoke.3541107863 |
| Directory | /workspace/46.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/46.xbar_smoke_large_delays.1078788854 |
| Short name | T1342 |
| Test name | |
| Test status | |
| Simulation time | 4708918523 ps |
| CPU time | 50.25 seconds |
| Started | Jun 28 08:42:52 PM PDT 24 |
| Finished | Jun 28 08:43:57 PM PDT 24 |
| Peak memory | 566020 kb |
| Host | smart-74640e19-1285-47ad-a94a-17c831240da8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1078788854 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.xbar_smoke_large_delays.1078788854 |
| Directory | /workspace/46.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/46.xbar_smoke_slow_rsp.3940897338 |
| Short name | T1373 |
| Test name | |
| Test status | |
| Simulation time | 5221990263 ps |
| CPU time | 88.07 seconds |
| Started | Jun 28 08:42:54 PM PDT 24 |
| Finished | Jun 28 08:44:38 PM PDT 24 |
| Peak memory | 566032 kb |
| Host | smart-590eec9e-5c8f-478a-9259-b4f1b53bab72 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3940897338 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.xbar_smoke_slow_rsp.3940897338 |
| Directory | /workspace/46.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/46.xbar_smoke_zero_delays.3394255378 |
| Short name | T1516 |
| Test name | |
| Test status | |
| Simulation time | 52216818 ps |
| CPU time | 6.53 seconds |
| Started | Jun 28 08:42:51 PM PDT 24 |
| Finished | Jun 28 08:43:11 PM PDT 24 |
| Peak memory | 574188 kb |
| Host | smart-e68ad814-c4f2-4f3e-9956-36d6f8d69675 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3394255378 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.xbar_smoke_zero_delay s.3394255378 |
| Directory | /workspace/46.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/46.xbar_stress_all.1229651211 |
| Short name | T503 |
| Test name | |
| Test status | |
| Simulation time | 6279535713 ps |
| CPU time | 251.41 seconds |
| Started | Jun 28 08:42:59 PM PDT 24 |
| Finished | Jun 28 08:47:26 PM PDT 24 |
| Peak memory | 574324 kb |
| Host | smart-dd22e659-2ecb-47d2-b2fe-016533128c9e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1229651211 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.xbar_stress_all.1229651211 |
| Directory | /workspace/46.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/46.xbar_stress_all_with_error.449611372 |
| Short name | T1693 |
| Test name | |
| Test status | |
| Simulation time | 14022914095 ps |
| CPU time | 540.13 seconds |
| Started | Jun 28 08:42:54 PM PDT 24 |
| Finished | Jun 28 08:52:09 PM PDT 24 |
| Peak memory | 574688 kb |
| Host | smart-6c5499a1-ce28-4189-a8b0-1eadfffb24c9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=449611372 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.xbar_stress_all_with_error.449611372 |
| Directory | /workspace/46.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/46.xbar_stress_all_with_rand_reset.1129884980 |
| Short name | T2858 |
| Test name | |
| Test status | |
| Simulation time | 815578872 ps |
| CPU time | 98.84 seconds |
| Started | Jun 28 08:42:52 PM PDT 24 |
| Finished | Jun 28 08:44:44 PM PDT 24 |
| Peak memory | 576372 kb |
| Host | smart-fde67de0-7c83-4dfa-b5df-7ba9b4984db6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1129884980 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.xbar_stress_all _with_rand_reset.1129884980 |
| Directory | /workspace/46.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/46.xbar_stress_all_with_reset_error.4091009467 |
| Short name | T2846 |
| Test name | |
| Test status | |
| Simulation time | 6477841822 ps |
| CPU time | 300.99 seconds |
| Started | Jun 28 08:42:59 PM PDT 24 |
| Finished | Jun 28 08:48:15 PM PDT 24 |
| Peak memory | 574348 kb |
| Host | smart-6ac7da90-3ebf-40dc-8697-d02f7a77d6e5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4091009467 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.xbar_stress_al l_with_reset_error.4091009467 |
| Directory | /workspace/46.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/46.xbar_unmapped_addr.3212984109 |
| Short name | T1984 |
| Test name | |
| Test status | |
| Simulation time | 340303995 ps |
| CPU time | 17.84 seconds |
| Started | Jun 28 08:42:49 PM PDT 24 |
| Finished | Jun 28 08:43:14 PM PDT 24 |
| Peak memory | 574204 kb |
| Host | smart-a7a54147-c540-44ec-bc8f-2be4d8cfc8c5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3212984109 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.xbar_unmapped_addr.3212984109 |
| Directory | /workspace/46.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/47.xbar_access_same_device.2455629618 |
| Short name | T2292 |
| Test name | |
| Test status | |
| Simulation time | 2697598466 ps |
| CPU time | 115.61 seconds |
| Started | Jun 28 08:42:56 PM PDT 24 |
| Finished | Jun 28 08:45:08 PM PDT 24 |
| Peak memory | 575292 kb |
| Host | smart-3b6abdba-6532-4f2b-8b18-bdc30ac244a0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2455629618 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.xbar_access_same_device .2455629618 |
| Directory | /workspace/47.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/47.xbar_access_same_device_slow_rsp.1395095431 |
| Short name | T2154 |
| Test name | |
| Test status | |
| Simulation time | 15724278512 ps |
| CPU time | 267.66 seconds |
| Started | Jun 28 08:42:56 PM PDT 24 |
| Finished | Jun 28 08:47:40 PM PDT 24 |
| Peak memory | 575344 kb |
| Host | smart-aeded4cb-2e10-4ee9-ab21-80f7fb09bee8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1395095431 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.xbar_access_same_ device_slow_rsp.1395095431 |
| Directory | /workspace/47.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/47.xbar_error_and_unmapped_addr.3678502550 |
| Short name | T1380 |
| Test name | |
| Test status | |
| Simulation time | 305328030 ps |
| CPU time | 17.24 seconds |
| Started | Jun 28 08:42:48 PM PDT 24 |
| Finished | Jun 28 08:43:12 PM PDT 24 |
| Peak memory | 574208 kb |
| Host | smart-a1aece46-a249-4d77-ac42-932c5108c96c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3678502550 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.xbar_error_and_unmapped_add r.3678502550 |
| Directory | /workspace/47.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/47.xbar_error_random.1015618537 |
| Short name | T515 |
| Test name | |
| Test status | |
| Simulation time | 591004799 ps |
| CPU time | 57.25 seconds |
| Started | Jun 28 08:42:59 PM PDT 24 |
| Finished | Jun 28 08:44:11 PM PDT 24 |
| Peak memory | 573776 kb |
| Host | smart-777039e4-eafa-432e-8bc2-23d8c57dce5d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1015618537 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.xbar_error_random.1015618537 |
| Directory | /workspace/47.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/47.xbar_random.1938819193 |
| Short name | T2382 |
| Test name | |
| Test status | |
| Simulation time | 38751582 ps |
| CPU time | 6.73 seconds |
| Started | Jun 28 08:42:49 PM PDT 24 |
| Finished | Jun 28 08:43:04 PM PDT 24 |
| Peak memory | 574116 kb |
| Host | smart-d7aa528a-bba5-42fa-9e6e-c91682a38a29 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1938819193 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.xbar_random.1938819193 |
| Directory | /workspace/47.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/47.xbar_random_large_delays.2028337953 |
| Short name | T2258 |
| Test name | |
| Test status | |
| Simulation time | 16202883750 ps |
| CPU time | 180.97 seconds |
| Started | Jun 28 08:42:55 PM PDT 24 |
| Finished | Jun 28 08:46:12 PM PDT 24 |
| Peak memory | 575308 kb |
| Host | smart-c3845502-a5fc-42c3-8803-2c6868ad134a |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2028337953 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.xbar_random_large_delays.2028337953 |
| Directory | /workspace/47.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/47.xbar_random_slow_rsp.794990009 |
| Short name | T1916 |
| Test name | |
| Test status | |
| Simulation time | 19867635627 ps |
| CPU time | 342.38 seconds |
| Started | Jun 28 08:42:47 PM PDT 24 |
| Finished | Jun 28 08:48:34 PM PDT 24 |
| Peak memory | 575296 kb |
| Host | smart-8733336d-1c48-4996-813a-bedc249ba4d6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=794990009 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.xbar_random_slow_rsp.794990009 |
| Directory | /workspace/47.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/47.xbar_random_zero_delays.3059493644 |
| Short name | T2618 |
| Test name | |
| Test status | |
| Simulation time | 568807236 ps |
| CPU time | 52.66 seconds |
| Started | Jun 28 08:42:52 PM PDT 24 |
| Finished | Jun 28 08:43:59 PM PDT 24 |
| Peak memory | 575272 kb |
| Host | smart-a71eab8d-c6cd-4c22-8971-314249f6eb7b |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3059493644 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.xbar_random_zero_del ays.3059493644 |
| Directory | /workspace/47.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/47.xbar_same_source.2174163296 |
| Short name | T1406 |
| Test name | |
| Test status | |
| Simulation time | 786044225 ps |
| CPU time | 26.36 seconds |
| Started | Jun 28 08:42:46 PM PDT 24 |
| Finished | Jun 28 08:43:17 PM PDT 24 |
| Peak memory | 575216 kb |
| Host | smart-c06de76f-b2d4-4fda-bce3-b2be6105ce96 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2174163296 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.xbar_same_source.2174163296 |
| Directory | /workspace/47.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/47.xbar_smoke.4038062354 |
| Short name | T1345 |
| Test name | |
| Test status | |
| Simulation time | 54736500 ps |
| CPU time | 7.24 seconds |
| Started | Jun 28 08:42:51 PM PDT 24 |
| Finished | Jun 28 08:43:12 PM PDT 24 |
| Peak memory | 574192 kb |
| Host | smart-d9720cff-7f7b-428c-9a4b-920a1b5c749e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4038062354 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.xbar_smoke.4038062354 |
| Directory | /workspace/47.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/47.xbar_smoke_large_delays.463363055 |
| Short name | T2242 |
| Test name | |
| Test status | |
| Simulation time | 6190291453 ps |
| CPU time | 67.87 seconds |
| Started | Jun 28 08:42:59 PM PDT 24 |
| Finished | Jun 28 08:44:22 PM PDT 24 |
| Peak memory | 574084 kb |
| Host | smart-a180ef56-4829-4e52-83fa-84ace03991fd |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=463363055 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.xbar_smoke_large_delays.463363055 |
| Directory | /workspace/47.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/47.xbar_smoke_slow_rsp.3246815468 |
| Short name | T2872 |
| Test name | |
| Test status | |
| Simulation time | 3492716226 ps |
| CPU time | 61.7 seconds |
| Started | Jun 28 08:42:57 PM PDT 24 |
| Finished | Jun 28 08:44:15 PM PDT 24 |
| Peak memory | 574272 kb |
| Host | smart-5b1ffaf1-1e9b-4fb5-a143-1bdf419e6958 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3246815468 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.xbar_smoke_slow_rsp.3246815468 |
| Directory | /workspace/47.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/47.xbar_smoke_zero_delays.2605952705 |
| Short name | T2676 |
| Test name | |
| Test status | |
| Simulation time | 49062206 ps |
| CPU time | 7 seconds |
| Started | Jun 28 08:42:53 PM PDT 24 |
| Finished | Jun 28 08:43:16 PM PDT 24 |
| Peak memory | 574204 kb |
| Host | smart-7caf39b3-5757-431f-a142-0963bb42cf19 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2605952705 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.xbar_smoke_zero_delay s.2605952705 |
| Directory | /workspace/47.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/47.xbar_stress_all_with_error.129722292 |
| Short name | T2065 |
| Test name | |
| Test status | |
| Simulation time | 6785758471 ps |
| CPU time | 250.25 seconds |
| Started | Jun 28 08:43:12 PM PDT 24 |
| Finished | Jun 28 08:47:30 PM PDT 24 |
| Peak memory | 574420 kb |
| Host | smart-30b43a1a-5a99-4ced-94f4-fc5e07245f1c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=129722292 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.xbar_stress_all_with_error.129722292 |
| Directory | /workspace/47.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/47.xbar_stress_all_with_reset_error.3106268777 |
| Short name | T2521 |
| Test name | |
| Test status | |
| Simulation time | 121352202 ps |
| CPU time | 31.79 seconds |
| Started | Jun 28 08:43:27 PM PDT 24 |
| Finished | Jun 28 08:44:03 PM PDT 24 |
| Peak memory | 574560 kb |
| Host | smart-428bb92d-bac6-4e98-b62f-07f9a7bc403b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3106268777 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.xbar_stress_al l_with_reset_error.3106268777 |
| Directory | /workspace/47.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/47.xbar_unmapped_addr.2554378870 |
| Short name | T573 |
| Test name | |
| Test status | |
| Simulation time | 1118338082 ps |
| CPU time | 52.96 seconds |
| Started | Jun 28 08:42:56 PM PDT 24 |
| Finished | Jun 28 08:44:05 PM PDT 24 |
| Peak memory | 575312 kb |
| Host | smart-cf01aa69-904c-4992-982c-16dd13095b4e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2554378870 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.xbar_unmapped_addr.2554378870 |
| Directory | /workspace/47.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/48.xbar_access_same_device.2596317623 |
| Short name | T469 |
| Test name | |
| Test status | |
| Simulation time | 1425276349 ps |
| CPU time | 54.26 seconds |
| Started | Jun 28 08:43:18 PM PDT 24 |
| Finished | Jun 28 08:44:16 PM PDT 24 |
| Peak memory | 574144 kb |
| Host | smart-dabe6018-d023-4c9b-9817-e06d38165512 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2596317623 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.xbar_access_same_device .2596317623 |
| Directory | /workspace/48.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/48.xbar_access_same_device_slow_rsp.4240749459 |
| Short name | T2228 |
| Test name | |
| Test status | |
| Simulation time | 23867701555 ps |
| CPU time | 415.37 seconds |
| Started | Jun 28 08:43:13 PM PDT 24 |
| Finished | Jun 28 08:50:15 PM PDT 24 |
| Peak memory | 575352 kb |
| Host | smart-d741ba01-da65-49d1-abe5-04a94d19386a |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4240749459 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.xbar_access_same_ device_slow_rsp.4240749459 |
| Directory | /workspace/48.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/48.xbar_error_and_unmapped_addr.1063321665 |
| Short name | T1714 |
| Test name | |
| Test status | |
| Simulation time | 203138108 ps |
| CPU time | 22.54 seconds |
| Started | Jun 28 08:43:25 PM PDT 24 |
| Finished | Jun 28 08:43:51 PM PDT 24 |
| Peak memory | 574428 kb |
| Host | smart-ac2b4fc5-1ad8-411b-893b-fea88af03f9a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1063321665 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.xbar_error_and_unmapped_add r.1063321665 |
| Directory | /workspace/48.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/48.xbar_error_random.1981574251 |
| Short name | T1855 |
| Test name | |
| Test status | |
| Simulation time | 1110667388 ps |
| CPU time | 36.43 seconds |
| Started | Jun 28 08:43:19 PM PDT 24 |
| Finished | Jun 28 08:43:59 PM PDT 24 |
| Peak memory | 574424 kb |
| Host | smart-2f7f23e8-fb3b-4604-a749-dd430dff3c5f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1981574251 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.xbar_error_random.1981574251 |
| Directory | /workspace/48.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/48.xbar_random.2023032595 |
| Short name | T2561 |
| Test name | |
| Test status | |
| Simulation time | 655529812 ps |
| CPU time | 60.88 seconds |
| Started | Jun 28 08:43:13 PM PDT 24 |
| Finished | Jun 28 08:44:21 PM PDT 24 |
| Peak memory | 575244 kb |
| Host | smart-37ad6c10-b5ec-4a8b-be4a-99a26fa89b23 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2023032595 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.xbar_random.2023032595 |
| Directory | /workspace/48.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/48.xbar_random_large_delays.2734582086 |
| Short name | T623 |
| Test name | |
| Test status | |
| Simulation time | 41875762649 ps |
| CPU time | 440.61 seconds |
| Started | Jun 28 08:43:11 PM PDT 24 |
| Finished | Jun 28 08:50:40 PM PDT 24 |
| Peak memory | 574252 kb |
| Host | smart-e263a898-370d-4603-bd95-04b1a16d9569 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2734582086 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.xbar_random_large_delays.2734582086 |
| Directory | /workspace/48.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/48.xbar_random_slow_rsp.2494682933 |
| Short name | T2456 |
| Test name | |
| Test status | |
| Simulation time | 41092672523 ps |
| CPU time | 701.49 seconds |
| Started | Jun 28 08:43:14 PM PDT 24 |
| Finished | Jun 28 08:55:02 PM PDT 24 |
| Peak memory | 574288 kb |
| Host | smart-2e287262-a05d-4065-8cbe-7dac3f977155 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2494682933 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.xbar_random_slow_rsp.2494682933 |
| Directory | /workspace/48.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/48.xbar_random_zero_delays.601410519 |
| Short name | T1620 |
| Test name | |
| Test status | |
| Simulation time | 562585242 ps |
| CPU time | 51.64 seconds |
| Started | Jun 28 08:43:12 PM PDT 24 |
| Finished | Jun 28 08:44:11 PM PDT 24 |
| Peak memory | 575244 kb |
| Host | smart-9d55dc3f-5132-485e-b6d1-baf5fc51afa0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=601410519 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.xbar_random_zero_dela ys.601410519 |
| Directory | /workspace/48.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/48.xbar_same_source.768113794 |
| Short name | T576 |
| Test name | |
| Test status | |
| Simulation time | 760894433 ps |
| CPU time | 25.03 seconds |
| Started | Jun 28 08:43:24 PM PDT 24 |
| Finished | Jun 28 08:43:51 PM PDT 24 |
| Peak memory | 574148 kb |
| Host | smart-9b96d55c-0dab-40f9-a18d-2435ce9a9b9b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=768113794 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.xbar_same_source.768113794 |
| Directory | /workspace/48.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/48.xbar_smoke.1436541792 |
| Short name | T1343 |
| Test name | |
| Test status | |
| Simulation time | 214106275 ps |
| CPU time | 9.64 seconds |
| Started | Jun 28 08:43:12 PM PDT 24 |
| Finished | Jun 28 08:43:29 PM PDT 24 |
| Peak memory | 574168 kb |
| Host | smart-2fa04d45-d9e1-4b8b-b468-0a095f6a0477 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1436541792 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.xbar_smoke.1436541792 |
| Directory | /workspace/48.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/48.xbar_smoke_large_delays.2288511225 |
| Short name | T2239 |
| Test name | |
| Test status | |
| Simulation time | 8425283879 ps |
| CPU time | 88.49 seconds |
| Started | Jun 28 08:43:11 PM PDT 24 |
| Finished | Jun 28 08:44:47 PM PDT 24 |
| Peak memory | 574252 kb |
| Host | smart-7b7bfdfe-9139-4eb5-92c7-7fb63c86c04d |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2288511225 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.xbar_smoke_large_delays.2288511225 |
| Directory | /workspace/48.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/48.xbar_smoke_slow_rsp.1510449996 |
| Short name | T2156 |
| Test name | |
| Test status | |
| Simulation time | 6028408677 ps |
| CPU time | 102.89 seconds |
| Started | Jun 28 08:43:13 PM PDT 24 |
| Finished | Jun 28 08:45:03 PM PDT 24 |
| Peak memory | 566020 kb |
| Host | smart-4d83c589-2937-4424-b1ee-76b3ac33ec6f |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1510449996 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.xbar_smoke_slow_rsp.1510449996 |
| Directory | /workspace/48.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/48.xbar_smoke_zero_delays.2861400819 |
| Short name | T1911 |
| Test name | |
| Test status | |
| Simulation time | 41148462 ps |
| CPU time | 6.48 seconds |
| Started | Jun 28 08:43:26 PM PDT 24 |
| Finished | Jun 28 08:43:36 PM PDT 24 |
| Peak memory | 574168 kb |
| Host | smart-aeacbbe9-1c76-494d-bba2-7b0d9a46247e |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2861400819 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.xbar_smoke_zero_delay s.2861400819 |
| Directory | /workspace/48.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/48.xbar_stress_all.621598396 |
| Short name | T1495 |
| Test name | |
| Test status | |
| Simulation time | 7520530942 ps |
| CPU time | 260.38 seconds |
| Started | Jun 28 08:43:14 PM PDT 24 |
| Finished | Jun 28 08:47:41 PM PDT 24 |
| Peak memory | 574384 kb |
| Host | smart-4fb452e7-a494-4fb6-8570-c8760ea7a289 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=621598396 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.xbar_stress_all.621598396 |
| Directory | /workspace/48.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/48.xbar_stress_all_with_error.3561473700 |
| Short name | T1648 |
| Test name | |
| Test status | |
| Simulation time | 4139355778 ps |
| CPU time | 161.71 seconds |
| Started | Jun 28 08:43:25 PM PDT 24 |
| Finished | Jun 28 08:46:09 PM PDT 24 |
| Peak memory | 574608 kb |
| Host | smart-d9a74c89-2d11-4b12-b62a-1ce0f77604de |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3561473700 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.xbar_stress_all_with_error.3561473700 |
| Directory | /workspace/48.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/48.xbar_stress_all_with_rand_reset.1892702576 |
| Short name | T1727 |
| Test name | |
| Test status | |
| Simulation time | 1126651596 ps |
| CPU time | 237.16 seconds |
| Started | Jun 28 08:43:13 PM PDT 24 |
| Finished | Jun 28 08:47:17 PM PDT 24 |
| Peak memory | 575364 kb |
| Host | smart-39ceeeb5-c070-4bf7-adbf-c472b6e16d42 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1892702576 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.xbar_stress_all _with_rand_reset.1892702576 |
| Directory | /workspace/48.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/48.xbar_stress_all_with_reset_error.3914374994 |
| Short name | T2329 |
| Test name | |
| Test status | |
| Simulation time | 944171874 ps |
| CPU time | 247.14 seconds |
| Started | Jun 28 08:43:16 PM PDT 24 |
| Finished | Jun 28 08:47:28 PM PDT 24 |
| Peak memory | 576380 kb |
| Host | smart-60c25652-1b6b-4e8e-8e84-8c8e9e0f7a94 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3914374994 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.xbar_stress_al l_with_reset_error.3914374994 |
| Directory | /workspace/48.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/48.xbar_unmapped_addr.2472181129 |
| Short name | T2394 |
| Test name | |
| Test status | |
| Simulation time | 98244499 ps |
| CPU time | 14.91 seconds |
| Started | Jun 28 08:43:15 PM PDT 24 |
| Finished | Jun 28 08:43:36 PM PDT 24 |
| Peak memory | 575276 kb |
| Host | smart-02aec51c-3e00-4cf5-8bbe-746aa4d050aa |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2472181129 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.xbar_unmapped_addr.2472181129 |
| Directory | /workspace/48.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/49.xbar_access_same_device.104603490 |
| Short name | T1858 |
| Test name | |
| Test status | |
| Simulation time | 400339888 ps |
| CPU time | 39.15 seconds |
| Started | Jun 28 08:43:13 PM PDT 24 |
| Finished | Jun 28 08:43:59 PM PDT 24 |
| Peak memory | 575256 kb |
| Host | smart-a2cb4561-cb84-4230-9817-b00ed8fcf41f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=104603490 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.xbar_access_same_device. 104603490 |
| Directory | /workspace/49.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/49.xbar_access_same_device_slow_rsp.891937619 |
| Short name | T2778 |
| Test name | |
| Test status | |
| Simulation time | 41457612059 ps |
| CPU time | 737.7 seconds |
| Started | Jun 28 08:43:13 PM PDT 24 |
| Finished | Jun 28 08:55:38 PM PDT 24 |
| Peak memory | 575400 kb |
| Host | smart-a6b5a264-3baf-42fe-b10a-3aa62584f52d |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=891937619 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.xbar_access_same_d evice_slow_rsp.891937619 |
| Directory | /workspace/49.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/49.xbar_error_and_unmapped_addr.328528305 |
| Short name | T1552 |
| Test name | |
| Test status | |
| Simulation time | 205013313 ps |
| CPU time | 11.78 seconds |
| Started | Jun 28 08:43:25 PM PDT 24 |
| Finished | Jun 28 08:43:39 PM PDT 24 |
| Peak memory | 573840 kb |
| Host | smart-ebd310bc-0489-4f69-afd2-3d4ccc042972 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=328528305 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.xbar_error_and_unmapped_addr .328528305 |
| Directory | /workspace/49.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/49.xbar_error_random.3584209358 |
| Short name | T2878 |
| Test name | |
| Test status | |
| Simulation time | 1414076799 ps |
| CPU time | 53.8 seconds |
| Started | Jun 28 08:43:15 PM PDT 24 |
| Finished | Jun 28 08:44:15 PM PDT 24 |
| Peak memory | 574412 kb |
| Host | smart-7bffe84a-9e10-4e4a-b7fe-c37ae28ac2a6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3584209358 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.xbar_error_random.3584209358 |
| Directory | /workspace/49.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/49.xbar_random.2447874031 |
| Short name | T2637 |
| Test name | |
| Test status | |
| Simulation time | 1553657474 ps |
| CPU time | 59.96 seconds |
| Started | Jun 28 08:43:11 PM PDT 24 |
| Finished | Jun 28 08:44:19 PM PDT 24 |
| Peak memory | 575236 kb |
| Host | smart-4f98a99c-9ea8-4e8f-868e-c0125c939011 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2447874031 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.xbar_random.2447874031 |
| Directory | /workspace/49.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/49.xbar_random_large_delays.733825450 |
| Short name | T2632 |
| Test name | |
| Test status | |
| Simulation time | 94405965334 ps |
| CPU time | 1011.71 seconds |
| Started | Jun 28 08:43:14 PM PDT 24 |
| Finished | Jun 28 09:00:13 PM PDT 24 |
| Peak memory | 574324 kb |
| Host | smart-9ac60814-d6ab-4112-950d-5eabeb1bb0a0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=733825450 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.xbar_random_large_delays.733825450 |
| Directory | /workspace/49.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/49.xbar_random_slow_rsp.1396588118 |
| Short name | T2174 |
| Test name | |
| Test status | |
| Simulation time | 21461870136 ps |
| CPU time | 400.27 seconds |
| Started | Jun 28 08:43:14 PM PDT 24 |
| Finished | Jun 28 08:50:01 PM PDT 24 |
| Peak memory | 575432 kb |
| Host | smart-61481b25-e26d-417a-98ce-5415278c5cd2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1396588118 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.xbar_random_slow_rsp.1396588118 |
| Directory | /workspace/49.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/49.xbar_random_zero_delays.1258327347 |
| Short name | T1841 |
| Test name | |
| Test status | |
| Simulation time | 423585255 ps |
| CPU time | 37.63 seconds |
| Started | Jun 28 08:43:24 PM PDT 24 |
| Finished | Jun 28 08:44:03 PM PDT 24 |
| Peak memory | 575248 kb |
| Host | smart-76278143-b540-4f97-871d-63053dc88504 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1258327347 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.xbar_random_zero_del ays.1258327347 |
| Directory | /workspace/49.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/49.xbar_same_source.553450772 |
| Short name | T1502 |
| Test name | |
| Test status | |
| Simulation time | 377576884 ps |
| CPU time | 27.51 seconds |
| Started | Jun 28 08:43:12 PM PDT 24 |
| Finished | Jun 28 08:43:47 PM PDT 24 |
| Peak memory | 575220 kb |
| Host | smart-4eba5c8e-ad85-41be-bd28-924508e5b8fe |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=553450772 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.xbar_same_source.553450772 |
| Directory | /workspace/49.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/49.xbar_smoke.1915203090 |
| Short name | T1312 |
| Test name | |
| Test status | |
| Simulation time | 209225564 ps |
| CPU time | 8.38 seconds |
| Started | Jun 28 08:43:15 PM PDT 24 |
| Finished | Jun 28 08:43:29 PM PDT 24 |
| Peak memory | 574188 kb |
| Host | smart-c329d4d4-4911-4ce9-9e4c-fc9ca6f4e5db |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1915203090 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.xbar_smoke.1915203090 |
| Directory | /workspace/49.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/49.xbar_smoke_large_delays.3956265686 |
| Short name | T1491 |
| Test name | |
| Test status | |
| Simulation time | 8621613468 ps |
| CPU time | 89.07 seconds |
| Started | Jun 28 08:43:17 PM PDT 24 |
| Finished | Jun 28 08:44:50 PM PDT 24 |
| Peak memory | 574264 kb |
| Host | smart-eafeeba4-4cc9-46dd-a26f-71aa69e77e7c |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3956265686 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.xbar_smoke_large_delays.3956265686 |
| Directory | /workspace/49.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/49.xbar_smoke_slow_rsp.3126638725 |
| Short name | T1744 |
| Test name | |
| Test status | |
| Simulation time | 4276900197 ps |
| CPU time | 72.66 seconds |
| Started | Jun 28 08:43:11 PM PDT 24 |
| Finished | Jun 28 08:44:32 PM PDT 24 |
| Peak memory | 565984 kb |
| Host | smart-01a24ac1-33f1-4a35-b1b8-447a48ca7304 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3126638725 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.xbar_smoke_slow_rsp.3126638725 |
| Directory | /workspace/49.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/49.xbar_smoke_zero_delays.3339063927 |
| Short name | T1338 |
| Test name | |
| Test status | |
| Simulation time | 51953459 ps |
| CPU time | 7.1 seconds |
| Started | Jun 28 08:43:32 PM PDT 24 |
| Finished | Jun 28 08:43:41 PM PDT 24 |
| Peak memory | 574172 kb |
| Host | smart-c99b78a3-b28a-4c58-bb63-68fb95d5c7ad |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3339063927 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.xbar_smoke_zero_delay s.3339063927 |
| Directory | /workspace/49.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/49.xbar_stress_all.1886529747 |
| Short name | T2085 |
| Test name | |
| Test status | |
| Simulation time | 1399410797 ps |
| CPU time | 101.77 seconds |
| Started | Jun 28 08:43:11 PM PDT 24 |
| Finished | Jun 28 08:45:01 PM PDT 24 |
| Peak memory | 574172 kb |
| Host | smart-777ab69e-bd7c-4eb0-8de1-7f6130e3c392 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1886529747 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.xbar_stress_all.1886529747 |
| Directory | /workspace/49.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/49.xbar_stress_all_with_error.2437565526 |
| Short name | T1514 |
| Test name | |
| Test status | |
| Simulation time | 11635819472 ps |
| CPU time | 404.88 seconds |
| Started | Jun 28 08:43:19 PM PDT 24 |
| Finished | Jun 28 08:50:07 PM PDT 24 |
| Peak memory | 574412 kb |
| Host | smart-f667bfa7-8d49-4869-ab56-f8c56fe4be01 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2437565526 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.xbar_stress_all_with_error.2437565526 |
| Directory | /workspace/49.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/49.xbar_stress_all_with_rand_reset.806858118 |
| Short name | T2208 |
| Test name | |
| Test status | |
| Simulation time | 87715915 ps |
| CPU time | 42.42 seconds |
| Started | Jun 28 08:43:11 PM PDT 24 |
| Finished | Jun 28 08:44:01 PM PDT 24 |
| Peak memory | 575376 kb |
| Host | smart-42a3f96f-91fe-4789-9f19-805e597452a1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=806858118 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_res et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.xbar_stress_all_ with_rand_reset.806858118 |
| Directory | /workspace/49.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/49.xbar_stress_all_with_reset_error.2501182798 |
| Short name | T1635 |
| Test name | |
| Test status | |
| Simulation time | 912912482 ps |
| CPU time | 248.29 seconds |
| Started | Jun 28 08:43:32 PM PDT 24 |
| Finished | Jun 28 08:47:42 PM PDT 24 |
| Peak memory | 574324 kb |
| Host | smart-7f23f85d-09c0-4760-b33f-888449e3583e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2501182798 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.xbar_stress_al l_with_reset_error.2501182798 |
| Directory | /workspace/49.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/49.xbar_unmapped_addr.1160465851 |
| Short name | T2105 |
| Test name | |
| Test status | |
| Simulation time | 242099824 ps |
| CPU time | 30.96 seconds |
| Started | Jun 28 08:43:12 PM PDT 24 |
| Finished | Jun 28 08:43:50 PM PDT 24 |
| Peak memory | 575308 kb |
| Host | smart-691b1377-3f0f-4616-8887-5c5fdbde5d4f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1160465851 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.xbar_unmapped_addr.1160465851 |
| Directory | /workspace/49.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/5.chip_csr_rw.953405260 |
| Short name | T2017 |
| Test name | |
| Test status | |
| Simulation time | 5826048442 ps |
| CPU time | 674.29 seconds |
| Started | Jun 28 08:31:34 PM PDT 24 |
| Finished | Jun 28 08:43:02 PM PDT 24 |
| Peak memory | 598064 kb |
| Host | smart-50191a37-a61b-4466-add5-706015685ed2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=953405260 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.chip_csr_rw.953405260 |
| Directory | /workspace/5.chip_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/5.chip_same_csr_outstanding.726459741 |
| Short name | T438 |
| Test name | |
| Test status | |
| Simulation time | 15612270578 ps |
| CPU time | 1724.65 seconds |
| Started | Jun 28 08:31:15 PM PDT 24 |
| Finished | Jun 28 09:00:16 PM PDT 24 |
| Peak memory | 591664 kb |
| Host | smart-381811c3-1d20-4b57-87f1-eb2967ee5f29 |
| User | root |
| Command | /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +run_same_csr_outstanding +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=726459741 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c m_log /dev/null -cm_name 5.chip_same_csr_outstanding.726459741 |
| Directory | /workspace/5.chip_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/5.chip_tl_errors.1369261288 |
| Short name | T2290 |
| Test name | |
| Test status | |
| Simulation time | 2243616515 ps |
| CPU time | 87.95 seconds |
| Started | Jun 28 08:31:15 PM PDT 24 |
| Finished | Jun 28 08:32:59 PM PDT 24 |
| Peak memory | 597284 kb |
| Host | smart-09b69ea1-d893-4cd7-96fa-34ad5611db6f |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1369261288 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.chip_tl_errors.1369261288 |
| Directory | /workspace/5.chip_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/5.xbar_access_same_device.3841925222 |
| Short name | T617 |
| Test name | |
| Test status | |
| Simulation time | 1610371042 ps |
| CPU time | 64.6 seconds |
| Started | Jun 28 08:31:36 PM PDT 24 |
| Finished | Jun 28 08:32:54 PM PDT 24 |
| Peak memory | 575184 kb |
| Host | smart-743c404f-50ac-4dc6-9152-50233bb94d5a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3841925222 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.xbar_access_same_device. 3841925222 |
| Directory | /workspace/5.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/5.xbar_access_same_device_slow_rsp.1026805375 |
| Short name | T2501 |
| Test name | |
| Test status | |
| Simulation time | 17293123836 ps |
| CPU time | 330.86 seconds |
| Started | Jun 28 08:31:38 PM PDT 24 |
| Finished | Jun 28 08:37:21 PM PDT 24 |
| Peak memory | 575464 kb |
| Host | smart-3e3571cb-6b79-4b17-9eb3-2cde9e941995 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1026805375 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.xbar_access_same_d evice_slow_rsp.1026805375 |
| Directory | /workspace/5.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/5.xbar_error_and_unmapped_addr.1530638244 |
| Short name | T2178 |
| Test name | |
| Test status | |
| Simulation time | 158156073 ps |
| CPU time | 9.08 seconds |
| Started | Jun 28 08:31:38 PM PDT 24 |
| Finished | Jun 28 08:31:59 PM PDT 24 |
| Peak memory | 565736 kb |
| Host | smart-5a75acd4-4fdf-4b59-800d-89e9da468090 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1530638244 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.xbar_error_and_unmapped_addr .1530638244 |
| Directory | /workspace/5.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/5.xbar_error_random.1874395412 |
| Short name | T1370 |
| Test name | |
| Test status | |
| Simulation time | 1195327316 ps |
| CPU time | 44.98 seconds |
| Started | Jun 28 08:31:34 PM PDT 24 |
| Finished | Jun 28 08:32:33 PM PDT 24 |
| Peak memory | 574196 kb |
| Host | smart-3b0bb0e9-0113-486f-a90a-f2afa0d7a46f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1874395412 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.xbar_error_random.1874395412 |
| Directory | /workspace/5.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/5.xbar_random.163957043 |
| Short name | T2571 |
| Test name | |
| Test status | |
| Simulation time | 337446799 ps |
| CPU time | 33.2 seconds |
| Started | Jun 28 08:31:14 PM PDT 24 |
| Finished | Jun 28 08:32:04 PM PDT 24 |
| Peak memory | 575220 kb |
| Host | smart-b257c636-1a12-4243-9915-666486d091aa |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=163957043 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.xbar_random.163957043 |
| Directory | /workspace/5.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/5.xbar_random_large_delays.3474800973 |
| Short name | T2306 |
| Test name | |
| Test status | |
| Simulation time | 88614336690 ps |
| CPU time | 855.76 seconds |
| Started | Jun 28 08:31:19 PM PDT 24 |
| Finished | Jun 28 08:45:53 PM PDT 24 |
| Peak memory | 575364 kb |
| Host | smart-749ab371-4c86-4a27-bfec-25c3e4d068ab |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3474800973 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.xbar_random_large_delays.3474800973 |
| Directory | /workspace/5.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/5.xbar_random_slow_rsp.4021474006 |
| Short name | T2452 |
| Test name | |
| Test status | |
| Simulation time | 6812776853 ps |
| CPU time | 116.43 seconds |
| Started | Jun 28 08:31:16 PM PDT 24 |
| Finished | Jun 28 08:33:31 PM PDT 24 |
| Peak memory | 574312 kb |
| Host | smart-9b5e1c54-0622-4597-84a2-278611f93b6c |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4021474006 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.xbar_random_slow_rsp.4021474006 |
| Directory | /workspace/5.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/5.xbar_random_zero_delays.95166944 |
| Short name | T1945 |
| Test name | |
| Test status | |
| Simulation time | 34378203 ps |
| CPU time | 6.71 seconds |
| Started | Jun 28 08:31:18 PM PDT 24 |
| Finished | Jun 28 08:31:44 PM PDT 24 |
| Peak memory | 574204 kb |
| Host | smart-166fc440-827c-4402-8edc-c6bf0980280a |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95166944 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.xbar_random_zero_delays .95166944 |
| Directory | /workspace/5.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/5.xbar_same_source.246550249 |
| Short name | T1994 |
| Test name | |
| Test status | |
| Simulation time | 575552886 ps |
| CPU time | 46.31 seconds |
| Started | Jun 28 08:31:35 PM PDT 24 |
| Finished | Jun 28 08:32:35 PM PDT 24 |
| Peak memory | 575228 kb |
| Host | smart-9576e3a9-5607-481a-9ec7-0f03ed32c390 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=246550249 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.xbar_same_source.246550249 |
| Directory | /workspace/5.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/5.xbar_smoke.95061339 |
| Short name | T2464 |
| Test name | |
| Test status | |
| Simulation time | 207369131 ps |
| CPU time | 10.17 seconds |
| Started | Jun 28 08:31:18 PM PDT 24 |
| Finished | Jun 28 08:31:47 PM PDT 24 |
| Peak memory | 574184 kb |
| Host | smart-b3d703a3-ba0f-4954-ac77-97a232605224 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95061339 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.xbar_smoke.95061339 |
| Directory | /workspace/5.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/5.xbar_smoke_large_delays.1850902109 |
| Short name | T1318 |
| Test name | |
| Test status | |
| Simulation time | 8235691586 ps |
| CPU time | 89.52 seconds |
| Started | Jun 28 08:31:16 PM PDT 24 |
| Finished | Jun 28 08:33:04 PM PDT 24 |
| Peak memory | 574240 kb |
| Host | smart-e2a3ad92-5feb-4bc4-8265-8c0f9741abeb |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1850902109 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.xbar_smoke_large_delays.1850902109 |
| Directory | /workspace/5.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/5.xbar_smoke_slow_rsp.2541614589 |
| Short name | T1310 |
| Test name | |
| Test status | |
| Simulation time | 4686107750 ps |
| CPU time | 83 seconds |
| Started | Jun 28 08:31:15 PM PDT 24 |
| Finished | Jun 28 08:32:56 PM PDT 24 |
| Peak memory | 574260 kb |
| Host | smart-dcedc8de-7c1c-4ebf-b4d9-abad380f4ac3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2541614589 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.xbar_smoke_slow_rsp.2541614589 |
| Directory | /workspace/5.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/5.xbar_smoke_zero_delays.3467556372 |
| Short name | T1362 |
| Test name | |
| Test status | |
| Simulation time | 43659756 ps |
| CPU time | 6.41 seconds |
| Started | Jun 28 08:31:16 PM PDT 24 |
| Finished | Jun 28 08:31:41 PM PDT 24 |
| Peak memory | 574176 kb |
| Host | smart-c7f7ccd5-d2af-4874-8215-b41ff8933288 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3467556372 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.xbar_smoke_zero_delays .3467556372 |
| Directory | /workspace/5.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/5.xbar_stress_all.3826582676 |
| Short name | T1405 |
| Test name | |
| Test status | |
| Simulation time | 399153523 ps |
| CPU time | 40.39 seconds |
| Started | Jun 28 08:31:36 PM PDT 24 |
| Finished | Jun 28 08:32:29 PM PDT 24 |
| Peak memory | 575316 kb |
| Host | smart-ec5445bd-d103-4583-b6c5-19e11f1c4eda |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3826582676 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.xbar_stress_all.3826582676 |
| Directory | /workspace/5.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/5.xbar_stress_all_with_error.2872552120 |
| Short name | T790 |
| Test name | |
| Test status | |
| Simulation time | 2885569378 ps |
| CPU time | 224.77 seconds |
| Started | Jun 28 08:31:36 PM PDT 24 |
| Finished | Jun 28 08:35:34 PM PDT 24 |
| Peak memory | 574336 kb |
| Host | smart-3162a5fe-b0bf-4338-ac76-ae0f2790d4e7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2872552120 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.xbar_stress_all_with_error.2872552120 |
| Directory | /workspace/5.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/5.xbar_stress_all_with_rand_reset.4225008849 |
| Short name | T489 |
| Test name | |
| Test status | |
| Simulation time | 799515724 ps |
| CPU time | 290.73 seconds |
| Started | Jun 28 08:31:34 PM PDT 24 |
| Finished | Jun 28 08:36:38 PM PDT 24 |
| Peak memory | 575400 kb |
| Host | smart-273e52f3-9caa-4cb1-ab01-46253f0fc7fb |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4225008849 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.xbar_stress_all_ with_rand_reset.4225008849 |
| Directory | /workspace/5.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/5.xbar_stress_all_with_reset_error.2158947267 |
| Short name | T2462 |
| Test name | |
| Test status | |
| Simulation time | 359605856 ps |
| CPU time | 134.01 seconds |
| Started | Jun 28 08:31:36 PM PDT 24 |
| Finished | Jun 28 08:34:03 PM PDT 24 |
| Peak memory | 576280 kb |
| Host | smart-d7215032-f3b9-46ae-a5f8-44b95ce11020 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2158947267 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.xbar_stress_all _with_reset_error.2158947267 |
| Directory | /workspace/5.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/5.xbar_unmapped_addr.1904917525 |
| Short name | T498 |
| Test name | |
| Test status | |
| Simulation time | 713524983 ps |
| CPU time | 33.71 seconds |
| Started | Jun 28 08:31:34 PM PDT 24 |
| Finished | Jun 28 08:32:21 PM PDT 24 |
| Peak memory | 575252 kb |
| Host | smart-09064a27-390b-4158-8b05-012708df5e34 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1904917525 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.xbar_unmapped_addr.1904917525 |
| Directory | /workspace/5.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/50.xbar_access_same_device.1823669437 |
| Short name | T2200 |
| Test name | |
| Test status | |
| Simulation time | 169191835 ps |
| CPU time | 15.53 seconds |
| Started | Jun 28 08:43:14 PM PDT 24 |
| Finished | Jun 28 08:43:36 PM PDT 24 |
| Peak memory | 574176 kb |
| Host | smart-cd948caa-5835-48a7-8676-76ebe6bc501b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1823669437 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 50.xbar_access_same_device .1823669437 |
| Directory | /workspace/50.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/50.xbar_error_and_unmapped_addr.627857567 |
| Short name | T1617 |
| Test name | |
| Test status | |
| Simulation time | 92601242 ps |
| CPU time | 12.44 seconds |
| Started | Jun 28 08:43:24 PM PDT 24 |
| Finished | Jun 28 08:43:39 PM PDT 24 |
| Peak memory | 574188 kb |
| Host | smart-abca5e10-59b5-4ac9-bc6a-2f65653a221b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=627857567 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 50.xbar_error_and_unmapped_addr .627857567 |
| Directory | /workspace/50.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/50.xbar_error_random.638677568 |
| Short name | T1912 |
| Test name | |
| Test status | |
| Simulation time | 66076692 ps |
| CPU time | 9.63 seconds |
| Started | Jun 28 08:43:15 PM PDT 24 |
| Finished | Jun 28 08:43:31 PM PDT 24 |
| Peak memory | 573812 kb |
| Host | smart-612bb36c-4168-41fb-84f8-8569c342a7be |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=638677568 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 50.xbar_error_random.638677568 |
| Directory | /workspace/50.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/50.xbar_random.2355853356 |
| Short name | T2046 |
| Test name | |
| Test status | |
| Simulation time | 433926030 ps |
| CPU time | 40.12 seconds |
| Started | Jun 28 08:43:32 PM PDT 24 |
| Finished | Jun 28 08:44:14 PM PDT 24 |
| Peak memory | 574152 kb |
| Host | smart-94be80c8-92e2-4b6f-9185-5c699ea542fd |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2355853356 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 50.xbar_random.2355853356 |
| Directory | /workspace/50.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/50.xbar_random_large_delays.663877717 |
| Short name | T2722 |
| Test name | |
| Test status | |
| Simulation time | 80901572619 ps |
| CPU time | 853.46 seconds |
| Started | Jun 28 08:43:14 PM PDT 24 |
| Finished | Jun 28 08:57:34 PM PDT 24 |
| Peak memory | 575332 kb |
| Host | smart-a3df1909-ff9d-45b2-9516-ec6c4ee3d447 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=663877717 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 50.xbar_random_large_delays.663877717 |
| Directory | /workspace/50.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/50.xbar_random_slow_rsp.2118545843 |
| Short name | T1778 |
| Test name | |
| Test status | |
| Simulation time | 19614698837 ps |
| CPU time | 330.29 seconds |
| Started | Jun 28 08:43:23 PM PDT 24 |
| Finished | Jun 28 08:48:56 PM PDT 24 |
| Peak memory | 574264 kb |
| Host | smart-e4a53c89-b029-491c-b750-790006c4f2f1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2118545843 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 50.xbar_random_slow_rsp.2118545843 |
| Directory | /workspace/50.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/50.xbar_random_zero_delays.2854104791 |
| Short name | T2739 |
| Test name | |
| Test status | |
| Simulation time | 335868213 ps |
| CPU time | 36.15 seconds |
| Started | Jun 28 08:43:11 PM PDT 24 |
| Finished | Jun 28 08:43:55 PM PDT 24 |
| Peak memory | 574176 kb |
| Host | smart-614fb6ac-ba0e-40f3-a691-c489d95c090d |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2854104791 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 50.xbar_random_zero_del ays.2854104791 |
| Directory | /workspace/50.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/50.xbar_same_source.1052266415 |
| Short name | T2427 |
| Test name | |
| Test status | |
| Simulation time | 2067064784 ps |
| CPU time | 70.98 seconds |
| Started | Jun 28 08:43:14 PM PDT 24 |
| Finished | Jun 28 08:44:32 PM PDT 24 |
| Peak memory | 575232 kb |
| Host | smart-8f341683-fa24-4361-bc53-5c97e3ec1500 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1052266415 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 50.xbar_same_source.1052266415 |
| Directory | /workspace/50.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/50.xbar_smoke.3644068092 |
| Short name | T2285 |
| Test name | |
| Test status | |
| Simulation time | 263672598 ps |
| CPU time | 10.66 seconds |
| Started | Jun 28 08:43:10 PM PDT 24 |
| Finished | Jun 28 08:43:29 PM PDT 24 |
| Peak memory | 574172 kb |
| Host | smart-5f0ed2d2-9b82-4aa0-8fa5-61583b877085 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3644068092 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 50.xbar_smoke.3644068092 |
| Directory | /workspace/50.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/50.xbar_smoke_large_delays.204266627 |
| Short name | T2283 |
| Test name | |
| Test status | |
| Simulation time | 8706002914 ps |
| CPU time | 97.31 seconds |
| Started | Jun 28 08:43:11 PM PDT 24 |
| Finished | Jun 28 08:44:56 PM PDT 24 |
| Peak memory | 574264 kb |
| Host | smart-c265c279-dd5b-4fe1-ad85-05ee0304aaf5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=204266627 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 50.xbar_smoke_large_delays.204266627 |
| Directory | /workspace/50.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/50.xbar_smoke_slow_rsp.2598848639 |
| Short name | T2338 |
| Test name | |
| Test status | |
| Simulation time | 5213619047 ps |
| CPU time | 88.87 seconds |
| Started | Jun 28 08:43:25 PM PDT 24 |
| Finished | Jun 28 08:44:58 PM PDT 24 |
| Peak memory | 566004 kb |
| Host | smart-c111fb0c-1784-49cd-b16a-d3aad9f095d0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2598848639 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 50.xbar_smoke_slow_rsp.2598848639 |
| Directory | /workspace/50.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/50.xbar_smoke_zero_delays.3137945105 |
| Short name | T2043 |
| Test name | |
| Test status | |
| Simulation time | 48691810 ps |
| CPU time | 7 seconds |
| Started | Jun 28 08:43:32 PM PDT 24 |
| Finished | Jun 28 08:43:41 PM PDT 24 |
| Peak memory | 574172 kb |
| Host | smart-c2a43199-34f1-49ae-94bf-0d21bda693c7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3137945105 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 50.xbar_smoke_zero_delay s.3137945105 |
| Directory | /workspace/50.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/50.xbar_stress_all.3317024245 |
| Short name | T2629 |
| Test name | |
| Test status | |
| Simulation time | 5597565738 ps |
| CPU time | 191.7 seconds |
| Started | Jun 28 08:43:23 PM PDT 24 |
| Finished | Jun 28 08:46:37 PM PDT 24 |
| Peak memory | 574396 kb |
| Host | smart-57e16426-a932-462f-b5c9-66c2eb304ef3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3317024245 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 50.xbar_stress_all.3317024245 |
| Directory | /workspace/50.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/50.xbar_stress_all_with_error.3044130463 |
| Short name | T2764 |
| Test name | |
| Test status | |
| Simulation time | 7135544786 ps |
| CPU time | 253.83 seconds |
| Started | Jun 28 08:43:15 PM PDT 24 |
| Finished | Jun 28 08:47:35 PM PDT 24 |
| Peak memory | 574604 kb |
| Host | smart-e544781e-f5f0-45b6-b8aa-dbf5923f6fba |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3044130463 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 50.xbar_stress_all_with_error.3044130463 |
| Directory | /workspace/50.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/50.xbar_stress_all_with_rand_reset.694341474 |
| Short name | T1568 |
| Test name | |
| Test status | |
| Simulation time | 545203497 ps |
| CPU time | 270.54 seconds |
| Started | Jun 28 08:43:23 PM PDT 24 |
| Finished | Jun 28 08:47:56 PM PDT 24 |
| Peak memory | 575388 kb |
| Host | smart-199a577e-392f-4989-94e0-d8f24ff57301 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=694341474 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_res et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 50.xbar_stress_all_ with_rand_reset.694341474 |
| Directory | /workspace/50.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/50.xbar_stress_all_with_reset_error.3464768163 |
| Short name | T852 |
| Test name | |
| Test status | |
| Simulation time | 216903787 ps |
| CPU time | 29.59 seconds |
| Started | Jun 28 08:43:18 PM PDT 24 |
| Finished | Jun 28 08:43:51 PM PDT 24 |
| Peak memory | 574584 kb |
| Host | smart-3e58b354-fa01-4661-99ec-3edfe398727f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3464768163 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 50.xbar_stress_al l_with_reset_error.3464768163 |
| Directory | /workspace/50.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/50.xbar_unmapped_addr.4269246677 |
| Short name | T1762 |
| Test name | |
| Test status | |
| Simulation time | 249972365 ps |
| CPU time | 28.95 seconds |
| Started | Jun 28 08:43:32 PM PDT 24 |
| Finished | Jun 28 08:44:03 PM PDT 24 |
| Peak memory | 575276 kb |
| Host | smart-f5f60c24-c719-4b1f-aa18-5e0c88e68119 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4269246677 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 50.xbar_unmapped_addr.4269246677 |
| Directory | /workspace/50.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/51.xbar_access_same_device.1601517229 |
| Short name | T452 |
| Test name | |
| Test status | |
| Simulation time | 2715431760 ps |
| CPU time | 96.5 seconds |
| Started | Jun 28 08:43:47 PM PDT 24 |
| Finished | Jun 28 08:45:24 PM PDT 24 |
| Peak memory | 575328 kb |
| Host | smart-2112aedc-71c7-4e40-ace9-ccb5f39cf0e6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1601517229 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 51.xbar_access_same_device .1601517229 |
| Directory | /workspace/51.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/51.xbar_access_same_device_slow_rsp.3389424563 |
| Short name | T2347 |
| Test name | |
| Test status | |
| Simulation time | 135489398878 ps |
| CPU time | 2283.69 seconds |
| Started | Jun 28 08:43:52 PM PDT 24 |
| Finished | Jun 28 09:21:58 PM PDT 24 |
| Peak memory | 574392 kb |
| Host | smart-e00921ae-289e-4b6b-9a26-964a8b257513 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3389424563 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 51.xbar_access_same_ device_slow_rsp.3389424563 |
| Directory | /workspace/51.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/51.xbar_error_and_unmapped_addr.4158836704 |
| Short name | T2254 |
| Test name | |
| Test status | |
| Simulation time | 701019404 ps |
| CPU time | 29.6 seconds |
| Started | Jun 28 08:43:50 PM PDT 24 |
| Finished | Jun 28 08:44:22 PM PDT 24 |
| Peak memory | 574192 kb |
| Host | smart-b5983454-9737-4424-a5d0-07380993d74c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4158836704 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 51.xbar_error_and_unmapped_add r.4158836704 |
| Directory | /workspace/51.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/51.xbar_error_random.2901288523 |
| Short name | T1755 |
| Test name | |
| Test status | |
| Simulation time | 2330235976 ps |
| CPU time | 89.63 seconds |
| Started | Jun 28 08:43:50 PM PDT 24 |
| Finished | Jun 28 08:45:22 PM PDT 24 |
| Peak memory | 574488 kb |
| Host | smart-f592c8df-8a83-4b46-927a-78dc09d5aa3c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2901288523 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 51.xbar_error_random.2901288523 |
| Directory | /workspace/51.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/51.xbar_random.3654440208 |
| Short name | T1658 |
| Test name | |
| Test status | |
| Simulation time | 487782843 ps |
| CPU time | 49.13 seconds |
| Started | Jun 28 08:43:48 PM PDT 24 |
| Finished | Jun 28 08:44:39 PM PDT 24 |
| Peak memory | 575268 kb |
| Host | smart-d02c3e6a-03ad-469e-9f0f-5bbd5af46cc4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3654440208 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 51.xbar_random.3654440208 |
| Directory | /workspace/51.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/51.xbar_random_large_delays.3653841762 |
| Short name | T487 |
| Test name | |
| Test status | |
| Simulation time | 96499896267 ps |
| CPU time | 1019.36 seconds |
| Started | Jun 28 08:43:48 PM PDT 24 |
| Finished | Jun 28 09:00:49 PM PDT 24 |
| Peak memory | 575332 kb |
| Host | smart-c0ad1719-1789-42fb-bebb-adb327a5df6e |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3653841762 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 51.xbar_random_large_delays.3653841762 |
| Directory | /workspace/51.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/51.xbar_random_slow_rsp.3828207184 |
| Short name | T552 |
| Test name | |
| Test status | |
| Simulation time | 16695576812 ps |
| CPU time | 269.92 seconds |
| Started | Jun 28 08:43:55 PM PDT 24 |
| Finished | Jun 28 08:48:27 PM PDT 24 |
| Peak memory | 575300 kb |
| Host | smart-1b64f65d-dbbb-4b34-bb33-5714982dafa3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3828207184 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 51.xbar_random_slow_rsp.3828207184 |
| Directory | /workspace/51.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/51.xbar_random_zero_delays.2243242496 |
| Short name | T1877 |
| Test name | |
| Test status | |
| Simulation time | 226086339 ps |
| CPU time | 21.61 seconds |
| Started | Jun 28 08:43:50 PM PDT 24 |
| Finished | Jun 28 08:44:14 PM PDT 24 |
| Peak memory | 575240 kb |
| Host | smart-a719bd59-6c95-4e01-8374-d0762a34463e |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2243242496 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 51.xbar_random_zero_del ays.2243242496 |
| Directory | /workspace/51.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/51.xbar_same_source.191884466 |
| Short name | T2159 |
| Test name | |
| Test status | |
| Simulation time | 717619237 ps |
| CPU time | 25.54 seconds |
| Started | Jun 28 08:43:49 PM PDT 24 |
| Finished | Jun 28 08:44:16 PM PDT 24 |
| Peak memory | 575128 kb |
| Host | smart-e83cf98c-4a11-425c-ba19-871a5b21091c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=191884466 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 51.xbar_same_source.191884466 |
| Directory | /workspace/51.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/51.xbar_smoke.994576002 |
| Short name | T2779 |
| Test name | |
| Test status | |
| Simulation time | 247743651 ps |
| CPU time | 10.89 seconds |
| Started | Jun 28 08:43:32 PM PDT 24 |
| Finished | Jun 28 08:43:45 PM PDT 24 |
| Peak memory | 565892 kb |
| Host | smart-698e4f52-e033-4c8b-9279-f002386b3c1c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=994576002 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 51.xbar_smoke.994576002 |
| Directory | /workspace/51.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/51.xbar_smoke_large_delays.1669852472 |
| Short name | T1771 |
| Test name | |
| Test status | |
| Simulation time | 7181226259 ps |
| CPU time | 71.83 seconds |
| Started | Jun 28 08:43:50 PM PDT 24 |
| Finished | Jun 28 08:45:05 PM PDT 24 |
| Peak memory | 574244 kb |
| Host | smart-cac55c1e-9330-47e9-820d-53152631ff96 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1669852472 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 51.xbar_smoke_large_delays.1669852472 |
| Directory | /workspace/51.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/51.xbar_smoke_slow_rsp.280509801 |
| Short name | T621 |
| Test name | |
| Test status | |
| Simulation time | 4542333107 ps |
| CPU time | 80.17 seconds |
| Started | Jun 28 08:43:48 PM PDT 24 |
| Finished | Jun 28 08:45:10 PM PDT 24 |
| Peak memory | 574248 kb |
| Host | smart-5809e3f1-c034-47ee-8e52-361b8dd29b8a |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=280509801 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 51.xbar_smoke_slow_rsp.280509801 |
| Directory | /workspace/51.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/51.xbar_smoke_zero_delays.4126173606 |
| Short name | T2748 |
| Test name | |
| Test status | |
| Simulation time | 38313188 ps |
| CPU time | 5.75 seconds |
| Started | Jun 28 08:43:19 PM PDT 24 |
| Finished | Jun 28 08:43:28 PM PDT 24 |
| Peak memory | 574180 kb |
| Host | smart-0711d4f7-f3a2-4e2d-b93e-f7163ecc6334 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4126173606 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 51.xbar_smoke_zero_delay s.4126173606 |
| Directory | /workspace/51.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/51.xbar_stress_all.4091330278 |
| Short name | T1480 |
| Test name | |
| Test status | |
| Simulation time | 3179902967 ps |
| CPU time | 157.53 seconds |
| Started | Jun 28 08:43:50 PM PDT 24 |
| Finished | Jun 28 08:46:30 PM PDT 24 |
| Peak memory | 575436 kb |
| Host | smart-64278c5c-284b-47ed-bad3-24141c7c8a91 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4091330278 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 51.xbar_stress_all.4091330278 |
| Directory | /workspace/51.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/51.xbar_stress_all_with_error.3869817058 |
| Short name | T1436 |
| Test name | |
| Test status | |
| Simulation time | 13426966404 ps |
| CPU time | 447.44 seconds |
| Started | Jun 28 08:43:54 PM PDT 24 |
| Finished | Jun 28 08:51:24 PM PDT 24 |
| Peak memory | 574360 kb |
| Host | smart-4a4d905b-163b-4ab9-96cb-75e11ebeebb0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3869817058 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 51.xbar_stress_all_with_error.3869817058 |
| Directory | /workspace/51.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/51.xbar_stress_all_with_rand_reset.2104630688 |
| Short name | T2586 |
| Test name | |
| Test status | |
| Simulation time | 272734983 ps |
| CPU time | 122.4 seconds |
| Started | Jun 28 08:43:49 PM PDT 24 |
| Finished | Jun 28 08:45:53 PM PDT 24 |
| Peak memory | 576368 kb |
| Host | smart-9deb665c-4a93-4141-beab-a1685bc0c0fe |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2104630688 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 51.xbar_stress_all _with_rand_reset.2104630688 |
| Directory | /workspace/51.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/51.xbar_stress_all_with_reset_error.1297702264 |
| Short name | T822 |
| Test name | |
| Test status | |
| Simulation time | 519065443 ps |
| CPU time | 179.69 seconds |
| Started | Jun 28 08:43:48 PM PDT 24 |
| Finished | Jun 28 08:46:50 PM PDT 24 |
| Peak memory | 576408 kb |
| Host | smart-f50f4027-1271-4e63-baa0-8f54f1ca892b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1297702264 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 51.xbar_stress_al l_with_reset_error.1297702264 |
| Directory | /workspace/51.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/51.xbar_unmapped_addr.3375984557 |
| Short name | T2127 |
| Test name | |
| Test status | |
| Simulation time | 150452482 ps |
| CPU time | 18.07 seconds |
| Started | Jun 28 08:43:53 PM PDT 24 |
| Finished | Jun 28 08:44:14 PM PDT 24 |
| Peak memory | 575296 kb |
| Host | smart-2ba2efcc-59bd-4f8a-b3ad-ced0d9a66760 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3375984557 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 51.xbar_unmapped_addr.3375984557 |
| Directory | /workspace/51.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/52.xbar_access_same_device.3169473474 |
| Short name | T1862 |
| Test name | |
| Test status | |
| Simulation time | 1585631087 ps |
| CPU time | 66.65 seconds |
| Started | Jun 28 08:43:51 PM PDT 24 |
| Finished | Jun 28 08:45:00 PM PDT 24 |
| Peak memory | 575188 kb |
| Host | smart-1841e9f8-33dc-47e8-abb2-3088582ac465 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3169473474 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 52.xbar_access_same_device .3169473474 |
| Directory | /workspace/52.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/52.xbar_access_same_device_slow_rsp.101915569 |
| Short name | T2406 |
| Test name | |
| Test status | |
| Simulation time | 114509693816 ps |
| CPU time | 1890.92 seconds |
| Started | Jun 28 08:43:48 PM PDT 24 |
| Finished | Jun 28 09:15:21 PM PDT 24 |
| Peak memory | 575448 kb |
| Host | smart-7288c765-06fc-40ea-8b97-09d14ce1fc31 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=101915569 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 52.xbar_access_same_d evice_slow_rsp.101915569 |
| Directory | /workspace/52.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/52.xbar_error_and_unmapped_addr.1842053497 |
| Short name | T1381 |
| Test name | |
| Test status | |
| Simulation time | 169668833 ps |
| CPU time | 22.44 seconds |
| Started | Jun 28 08:43:48 PM PDT 24 |
| Finished | Jun 28 08:44:12 PM PDT 24 |
| Peak memory | 574444 kb |
| Host | smart-201bf090-3ad1-475a-a43d-d57b04b65330 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1842053497 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 52.xbar_error_and_unmapped_add r.1842053497 |
| Directory | /workspace/52.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/52.xbar_error_random.3294359741 |
| Short name | T1484 |
| Test name | |
| Test status | |
| Simulation time | 292621827 ps |
| CPU time | 26.47 seconds |
| Started | Jun 28 08:43:50 PM PDT 24 |
| Finished | Jun 28 08:44:19 PM PDT 24 |
| Peak memory | 573788 kb |
| Host | smart-f723902d-0b27-402a-aa7d-0cc4b2410a11 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3294359741 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 52.xbar_error_random.3294359741 |
| Directory | /workspace/52.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/52.xbar_random.1773087816 |
| Short name | T1433 |
| Test name | |
| Test status | |
| Simulation time | 188285749 ps |
| CPU time | 9.55 seconds |
| Started | Jun 28 08:43:47 PM PDT 24 |
| Finished | Jun 28 08:43:58 PM PDT 24 |
| Peak memory | 565964 kb |
| Host | smart-a2a4733d-01cd-44e1-a3ec-cbc69d30664c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1773087816 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 52.xbar_random.1773087816 |
| Directory | /workspace/52.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/52.xbar_random_large_delays.213757036 |
| Short name | T2000 |
| Test name | |
| Test status | |
| Simulation time | 67142352287 ps |
| CPU time | 676.16 seconds |
| Started | Jun 28 08:43:48 PM PDT 24 |
| Finished | Jun 28 08:55:06 PM PDT 24 |
| Peak memory | 575352 kb |
| Host | smart-ab9d202f-0427-4c4b-99cd-c96e4e94e46e |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=213757036 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 52.xbar_random_large_delays.213757036 |
| Directory | /workspace/52.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/52.xbar_random_slow_rsp.3898321180 |
| Short name | T1555 |
| Test name | |
| Test status | |
| Simulation time | 18614657548 ps |
| CPU time | 325.82 seconds |
| Started | Jun 28 08:43:48 PM PDT 24 |
| Finished | Jun 28 08:49:16 PM PDT 24 |
| Peak memory | 575284 kb |
| Host | smart-fea64719-1d08-452a-b417-8310eff7a911 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3898321180 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 52.xbar_random_slow_rsp.3898321180 |
| Directory | /workspace/52.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/52.xbar_random_zero_delays.3030225385 |
| Short name | T461 |
| Test name | |
| Test status | |
| Simulation time | 320568506 ps |
| CPU time | 35.33 seconds |
| Started | Jun 28 08:43:52 PM PDT 24 |
| Finished | Jun 28 08:44:29 PM PDT 24 |
| Peak memory | 574180 kb |
| Host | smart-42de9dc7-b785-4161-80d0-f905b9a122a6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3030225385 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 52.xbar_random_zero_del ays.3030225385 |
| Directory | /workspace/52.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/52.xbar_same_source.1573988059 |
| Short name | T2405 |
| Test name | |
| Test status | |
| Simulation time | 2652144611 ps |
| CPU time | 75.78 seconds |
| Started | Jun 28 08:43:54 PM PDT 24 |
| Finished | Jun 28 08:45:12 PM PDT 24 |
| Peak memory | 575272 kb |
| Host | smart-a0def7c0-4cbe-4911-904c-d84ad5f27d28 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1573988059 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 52.xbar_same_source.1573988059 |
| Directory | /workspace/52.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/52.xbar_smoke.1483869792 |
| Short name | T2219 |
| Test name | |
| Test status | |
| Simulation time | 224868160 ps |
| CPU time | 10.08 seconds |
| Started | Jun 28 08:43:48 PM PDT 24 |
| Finished | Jun 28 08:44:01 PM PDT 24 |
| Peak memory | 574188 kb |
| Host | smart-c4f41905-f552-42f4-9de7-2d5ab1238029 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1483869792 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 52.xbar_smoke.1483869792 |
| Directory | /workspace/52.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/52.xbar_smoke_large_delays.2101349292 |
| Short name | T2639 |
| Test name | |
| Test status | |
| Simulation time | 7746857335 ps |
| CPU time | 83.18 seconds |
| Started | Jun 28 08:43:48 PM PDT 24 |
| Finished | Jun 28 08:45:14 PM PDT 24 |
| Peak memory | 574252 kb |
| Host | smart-37163dd5-f381-40a6-a920-8620a623454e |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2101349292 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 52.xbar_smoke_large_delays.2101349292 |
| Directory | /workspace/52.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/52.xbar_smoke_slow_rsp.1625834528 |
| Short name | T1350 |
| Test name | |
| Test status | |
| Simulation time | 4483075757 ps |
| CPU time | 78.45 seconds |
| Started | Jun 28 08:43:48 PM PDT 24 |
| Finished | Jun 28 08:45:09 PM PDT 24 |
| Peak memory | 574236 kb |
| Host | smart-61d37860-b6eb-4e3d-91c4-f073f811329f |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1625834528 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 52.xbar_smoke_slow_rsp.1625834528 |
| Directory | /workspace/52.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/52.xbar_smoke_zero_delays.66750136 |
| Short name | T1586 |
| Test name | |
| Test status | |
| Simulation time | 48223232 ps |
| CPU time | 6.87 seconds |
| Started | Jun 28 08:43:53 PM PDT 24 |
| Finished | Jun 28 08:44:02 PM PDT 24 |
| Peak memory | 574196 kb |
| Host | smart-31ef0c03-8605-4bf1-bc06-3bfb97fd3f16 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66750136 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 52.xbar_smoke_zero_delays.66750136 |
| Directory | /workspace/52.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/52.xbar_stress_all.849102831 |
| Short name | T2194 |
| Test name | |
| Test status | |
| Simulation time | 147403742 ps |
| CPU time | 19.96 seconds |
| Started | Jun 28 08:43:48 PM PDT 24 |
| Finished | Jun 28 08:44:11 PM PDT 24 |
| Peak memory | 575320 kb |
| Host | smart-499d2a84-e15e-4066-8ad5-cbe2b419dd89 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=849102831 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 52.xbar_stress_all.849102831 |
| Directory | /workspace/52.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/52.xbar_stress_all_with_error.787099776 |
| Short name | T2850 |
| Test name | |
| Test status | |
| Simulation time | 2082057137 ps |
| CPU time | 72.57 seconds |
| Started | Jun 28 08:44:46 PM PDT 24 |
| Finished | Jun 28 08:46:18 PM PDT 24 |
| Peak memory | 573868 kb |
| Host | smart-016b149e-6534-43eb-a6ef-ff373029ef72 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=787099776 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 52.xbar_stress_all_with_error.787099776 |
| Directory | /workspace/52.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/52.xbar_stress_all_with_rand_reset.1338745652 |
| Short name | T825 |
| Test name | |
| Test status | |
| Simulation time | 11807320543 ps |
| CPU time | 660.5 seconds |
| Started | Jun 28 08:43:52 PM PDT 24 |
| Finished | Jun 28 08:54:54 PM PDT 24 |
| Peak memory | 576416 kb |
| Host | smart-2f229eb1-374d-400d-b698-adb1bac52355 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1338745652 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 52.xbar_stress_all _with_rand_reset.1338745652 |
| Directory | /workspace/52.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/52.xbar_stress_all_with_reset_error.3354726796 |
| Short name | T2411 |
| Test name | |
| Test status | |
| Simulation time | 3666026308 ps |
| CPU time | 310.9 seconds |
| Started | Jun 28 08:44:45 PM PDT 24 |
| Finished | Jun 28 08:50:14 PM PDT 24 |
| Peak memory | 574396 kb |
| Host | smart-61a026c9-c3ee-474f-a52a-57d0f9c6769f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3354726796 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 52.xbar_stress_al l_with_reset_error.3354726796 |
| Directory | /workspace/52.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/52.xbar_unmapped_addr.536949245 |
| Short name | T2321 |
| Test name | |
| Test status | |
| Simulation time | 61295874 ps |
| CPU time | 6.79 seconds |
| Started | Jun 28 08:43:52 PM PDT 24 |
| Finished | Jun 28 08:44:01 PM PDT 24 |
| Peak memory | 574028 kb |
| Host | smart-bec38767-4e31-403a-9f87-2f783d8fed6d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=536949245 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 52.xbar_unmapped_addr.536949245 |
| Directory | /workspace/52.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/53.xbar_access_same_device.2553605057 |
| Short name | T1588 |
| Test name | |
| Test status | |
| Simulation time | 1818897743 ps |
| CPU time | 78.62 seconds |
| Started | Jun 28 08:44:49 PM PDT 24 |
| Finished | Jun 28 08:46:27 PM PDT 24 |
| Peak memory | 575308 kb |
| Host | smart-7493c2ed-69a7-4208-972f-d49abf6a170b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2553605057 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 53.xbar_access_same_device .2553605057 |
| Directory | /workspace/53.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/53.xbar_access_same_device_slow_rsp.976226282 |
| Short name | T2733 |
| Test name | |
| Test status | |
| Simulation time | 136747359749 ps |
| CPU time | 2361.07 seconds |
| Started | Jun 28 08:44:46 PM PDT 24 |
| Finished | Jun 28 09:24:26 PM PDT 24 |
| Peak memory | 575432 kb |
| Host | smart-1a4eb590-0450-470a-9dae-078fd38dc3d4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=976226282 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 53.xbar_access_same_d evice_slow_rsp.976226282 |
| Directory | /workspace/53.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/53.xbar_error_and_unmapped_addr.1922321668 |
| Short name | T2727 |
| Test name | |
| Test status | |
| Simulation time | 571201772 ps |
| CPU time | 25.72 seconds |
| Started | Jun 28 08:44:49 PM PDT 24 |
| Finished | Jun 28 08:45:34 PM PDT 24 |
| Peak memory | 574436 kb |
| Host | smart-114587f3-3694-4b77-8283-3836c93ae7f1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1922321668 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 53.xbar_error_and_unmapped_add r.1922321668 |
| Directory | /workspace/53.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/53.xbar_error_random.4065759670 |
| Short name | T2025 |
| Test name | |
| Test status | |
| Simulation time | 1520782917 ps |
| CPU time | 58.56 seconds |
| Started | Jun 28 08:44:43 PM PDT 24 |
| Finished | Jun 28 08:46:00 PM PDT 24 |
| Peak memory | 574408 kb |
| Host | smart-05c5ef95-4aaa-48fd-86b7-ab58b3c99777 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4065759670 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 53.xbar_error_random.4065759670 |
| Directory | /workspace/53.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/53.xbar_random.2328112635 |
| Short name | T2528 |
| Test name | |
| Test status | |
| Simulation time | 186528180 ps |
| CPU time | 18.65 seconds |
| Started | Jun 28 08:44:44 PM PDT 24 |
| Finished | Jun 28 08:45:20 PM PDT 24 |
| Peak memory | 575240 kb |
| Host | smart-e59ac27e-6bf7-42f1-aaee-acadf98e7fbf |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2328112635 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 53.xbar_random.2328112635 |
| Directory | /workspace/53.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/53.xbar_random_slow_rsp.241833106 |
| Short name | T1863 |
| Test name | |
| Test status | |
| Simulation time | 35077483383 ps |
| CPU time | 630.1 seconds |
| Started | Jun 28 08:44:46 PM PDT 24 |
| Finished | Jun 28 08:55:34 PM PDT 24 |
| Peak memory | 575308 kb |
| Host | smart-293ecda4-96a9-4e94-9483-b68bface23ed |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=241833106 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 53.xbar_random_slow_rsp.241833106 |
| Directory | /workspace/53.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/53.xbar_random_zero_delays.2128847128 |
| Short name | T1765 |
| Test name | |
| Test status | |
| Simulation time | 192759146 ps |
| CPU time | 20.12 seconds |
| Started | Jun 28 08:44:46 PM PDT 24 |
| Finished | Jun 28 08:45:25 PM PDT 24 |
| Peak memory | 575236 kb |
| Host | smart-32a24a3f-371b-4ee1-bc01-2abe24a91653 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2128847128 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 53.xbar_random_zero_del ays.2128847128 |
| Directory | /workspace/53.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/53.xbar_same_source.2149538899 |
| Short name | T2817 |
| Test name | |
| Test status | |
| Simulation time | 973071843 ps |
| CPU time | 33.84 seconds |
| Started | Jun 28 08:44:45 PM PDT 24 |
| Finished | Jun 28 08:45:37 PM PDT 24 |
| Peak memory | 575036 kb |
| Host | smart-6635dcc9-81c1-4159-9d04-98d570b56ad4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2149538899 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 53.xbar_same_source.2149538899 |
| Directory | /workspace/53.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/53.xbar_smoke.3996990228 |
| Short name | T2557 |
| Test name | |
| Test status | |
| Simulation time | 50578086 ps |
| CPU time | 7.34 seconds |
| Started | Jun 28 08:44:44 PM PDT 24 |
| Finished | Jun 28 08:45:10 PM PDT 24 |
| Peak memory | 574124 kb |
| Host | smart-e786e4ce-8800-4d0f-b645-6b2ef61dd4d1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3996990228 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 53.xbar_smoke.3996990228 |
| Directory | /workspace/53.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/53.xbar_smoke_large_delays.1006305642 |
| Short name | T2041 |
| Test name | |
| Test status | |
| Simulation time | 7780332818 ps |
| CPU time | 81.41 seconds |
| Started | Jun 28 08:44:50 PM PDT 24 |
| Finished | Jun 28 08:46:30 PM PDT 24 |
| Peak memory | 574252 kb |
| Host | smart-83fb1351-25b3-4cf6-92f2-7bf2331eeea0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1006305642 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 53.xbar_smoke_large_delays.1006305642 |
| Directory | /workspace/53.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/53.xbar_smoke_slow_rsp.3274675109 |
| Short name | T1650 |
| Test name | |
| Test status | |
| Simulation time | 5662071925 ps |
| CPU time | 97.36 seconds |
| Started | Jun 28 08:44:47 PM PDT 24 |
| Finished | Jun 28 08:46:43 PM PDT 24 |
| Peak memory | 565960 kb |
| Host | smart-4ab207b5-8a05-456e-b3b0-20633c4865c5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3274675109 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 53.xbar_smoke_slow_rsp.3274675109 |
| Directory | /workspace/53.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/53.xbar_smoke_zero_delays.2427182383 |
| Short name | T1681 |
| Test name | |
| Test status | |
| Simulation time | 37708358 ps |
| CPU time | 6.65 seconds |
| Started | Jun 28 08:44:50 PM PDT 24 |
| Finished | Jun 28 08:45:16 PM PDT 24 |
| Peak memory | 565908 kb |
| Host | smart-25417c97-89cf-40d4-973f-ab895108c973 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2427182383 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 53.xbar_smoke_zero_delay s.2427182383 |
| Directory | /workspace/53.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/53.xbar_stress_all.2470941838 |
| Short name | T2805 |
| Test name | |
| Test status | |
| Simulation time | 4056586762 ps |
| CPU time | 364.66 seconds |
| Started | Jun 28 08:44:47 PM PDT 24 |
| Finished | Jun 28 08:51:10 PM PDT 24 |
| Peak memory | 575452 kb |
| Host | smart-ec551c30-17d3-4ee0-8264-54f1f52e98a5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2470941838 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 53.xbar_stress_all.2470941838 |
| Directory | /workspace/53.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/53.xbar_stress_all_with_error.3000171197 |
| Short name | T2418 |
| Test name | |
| Test status | |
| Simulation time | 1278231380 ps |
| CPU time | 107.83 seconds |
| Started | Jun 28 08:44:43 PM PDT 24 |
| Finished | Jun 28 08:46:49 PM PDT 24 |
| Peak memory | 574272 kb |
| Host | smart-d3e5f0bc-6eaf-463c-9d44-4387ff09e70f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3000171197 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 53.xbar_stress_all_with_error.3000171197 |
| Directory | /workspace/53.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/53.xbar_stress_all_with_rand_reset.1771943022 |
| Short name | T2471 |
| Test name | |
| Test status | |
| Simulation time | 692843858 ps |
| CPU time | 293.75 seconds |
| Started | Jun 28 08:44:43 PM PDT 24 |
| Finished | Jun 28 08:49:55 PM PDT 24 |
| Peak memory | 576376 kb |
| Host | smart-4a2a7ed3-16b4-4563-a983-8186c19dcf48 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1771943022 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 53.xbar_stress_all _with_rand_reset.1771943022 |
| Directory | /workspace/53.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/53.xbar_stress_all_with_reset_error.2831514447 |
| Short name | T2847 |
| Test name | |
| Test status | |
| Simulation time | 2752792261 ps |
| CPU time | 321.9 seconds |
| Started | Jun 28 08:44:45 PM PDT 24 |
| Finished | Jun 28 08:50:26 PM PDT 24 |
| Peak memory | 574428 kb |
| Host | smart-03722400-df16-478d-9b26-c812d74ef7e3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2831514447 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 53.xbar_stress_al l_with_reset_error.2831514447 |
| Directory | /workspace/53.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/53.xbar_unmapped_addr.1865454625 |
| Short name | T1498 |
| Test name | |
| Test status | |
| Simulation time | 276653911 ps |
| CPU time | 15.42 seconds |
| Started | Jun 28 08:44:44 PM PDT 24 |
| Finished | Jun 28 08:45:18 PM PDT 24 |
| Peak memory | 574208 kb |
| Host | smart-f22abe8e-7d01-437b-97d5-d7c2c2aa2988 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1865454625 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 53.xbar_unmapped_addr.1865454625 |
| Directory | /workspace/53.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/54.xbar_access_same_device.3059850527 |
| Short name | T1663 |
| Test name | |
| Test status | |
| Simulation time | 3438624273 ps |
| CPU time | 148.06 seconds |
| Started | Jun 28 08:44:43 PM PDT 24 |
| Finished | Jun 28 08:47:29 PM PDT 24 |
| Peak memory | 575316 kb |
| Host | smart-d5ba9e14-6768-47c6-b2d6-05449d25c28a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3059850527 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 54.xbar_access_same_device .3059850527 |
| Directory | /workspace/54.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/54.xbar_access_same_device_slow_rsp.2194032209 |
| Short name | T2746 |
| Test name | |
| Test status | |
| Simulation time | 21714392347 ps |
| CPU time | 383.98 seconds |
| Started | Jun 28 08:44:46 PM PDT 24 |
| Finished | Jun 28 08:51:28 PM PDT 24 |
| Peak memory | 575300 kb |
| Host | smart-aec60386-b75d-4360-9bfd-9051086876b5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2194032209 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 54.xbar_access_same_ device_slow_rsp.2194032209 |
| Directory | /workspace/54.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/54.xbar_error_and_unmapped_addr.267003280 |
| Short name | T1417 |
| Test name | |
| Test status | |
| Simulation time | 303703140 ps |
| CPU time | 36.46 seconds |
| Started | Jun 28 08:44:43 PM PDT 24 |
| Finished | Jun 28 08:45:37 PM PDT 24 |
| Peak memory | 573900 kb |
| Host | smart-faad7a61-ff89-43cf-a1f4-504e5a35ecbf |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=267003280 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 54.xbar_error_and_unmapped_addr .267003280 |
| Directory | /workspace/54.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/54.xbar_error_random.2139073258 |
| Short name | T1331 |
| Test name | |
| Test status | |
| Simulation time | 1051641828 ps |
| CPU time | 36.19 seconds |
| Started | Jun 28 08:44:46 PM PDT 24 |
| Finished | Jun 28 08:45:40 PM PDT 24 |
| Peak memory | 573968 kb |
| Host | smart-9cb5848b-0cd2-4bee-8978-81f160544772 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2139073258 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 54.xbar_error_random.2139073258 |
| Directory | /workspace/54.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/54.xbar_random.15137292 |
| Short name | T2617 |
| Test name | |
| Test status | |
| Simulation time | 449194532 ps |
| CPU time | 43.43 seconds |
| Started | Jun 28 08:44:43 PM PDT 24 |
| Finished | Jun 28 08:45:45 PM PDT 24 |
| Peak memory | 575228 kb |
| Host | smart-033b69e2-08d2-4b75-9272-cc6b85dda8cc |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15137292 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 54.xbar_random.15137292 |
| Directory | /workspace/54.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/54.xbar_random_large_delays.2719828910 |
| Short name | T1562 |
| Test name | |
| Test status | |
| Simulation time | 52848757914 ps |
| CPU time | 581.32 seconds |
| Started | Jun 28 08:44:47 PM PDT 24 |
| Finished | Jun 28 08:54:48 PM PDT 24 |
| Peak memory | 575368 kb |
| Host | smart-1c0511e1-8be9-41ac-8423-7814d476f146 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2719828910 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 54.xbar_random_large_delays.2719828910 |
| Directory | /workspace/54.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/54.xbar_random_slow_rsp.1019062481 |
| Short name | T594 |
| Test name | |
| Test status | |
| Simulation time | 41943874426 ps |
| CPU time | 727.54 seconds |
| Started | Jun 28 08:44:47 PM PDT 24 |
| Finished | Jun 28 08:57:13 PM PDT 24 |
| Peak memory | 575360 kb |
| Host | smart-8854edc9-7af8-4db4-8d2e-6bfff066e3c9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1019062481 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 54.xbar_random_slow_rsp.1019062481 |
| Directory | /workspace/54.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/54.xbar_random_zero_delays.1840957850 |
| Short name | T2527 |
| Test name | |
| Test status | |
| Simulation time | 635562912 ps |
| CPU time | 64.9 seconds |
| Started | Jun 28 08:44:44 PM PDT 24 |
| Finished | Jun 28 08:46:08 PM PDT 24 |
| Peak memory | 574216 kb |
| Host | smart-3f432444-7584-4714-a4c1-36f722e720ec |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1840957850 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 54.xbar_random_zero_del ays.1840957850 |
| Directory | /workspace/54.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/54.xbar_same_source.2096886848 |
| Short name | T2278 |
| Test name | |
| Test status | |
| Simulation time | 866799779 ps |
| CPU time | 27.96 seconds |
| Started | Jun 28 08:44:46 PM PDT 24 |
| Finished | Jun 28 08:45:33 PM PDT 24 |
| Peak memory | 575216 kb |
| Host | smart-303fc124-2a0d-4a5a-ab3a-038f71035f99 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2096886848 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 54.xbar_same_source.2096886848 |
| Directory | /workspace/54.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/54.xbar_smoke.1632131014 |
| Short name | T1742 |
| Test name | |
| Test status | |
| Simulation time | 162005764 ps |
| CPU time | 8.44 seconds |
| Started | Jun 28 08:44:45 PM PDT 24 |
| Finished | Jun 28 08:45:12 PM PDT 24 |
| Peak memory | 574060 kb |
| Host | smart-5c9f9ecd-33a7-4cf9-9e46-eaf4136d05c5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1632131014 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 54.xbar_smoke.1632131014 |
| Directory | /workspace/54.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/54.xbar_smoke_large_delays.2849121839 |
| Short name | T1810 |
| Test name | |
| Test status | |
| Simulation time | 5216147470 ps |
| CPU time | 57.74 seconds |
| Started | Jun 28 08:44:44 PM PDT 24 |
| Finished | Jun 28 08:46:01 PM PDT 24 |
| Peak memory | 566020 kb |
| Host | smart-7a9a8886-5a00-4eaf-a0c1-6a8937e4a764 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2849121839 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 54.xbar_smoke_large_delays.2849121839 |
| Directory | /workspace/54.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/54.xbar_smoke_slow_rsp.1216182018 |
| Short name | T1511 |
| Test name | |
| Test status | |
| Simulation time | 3994109707 ps |
| CPU time | 68.02 seconds |
| Started | Jun 28 08:44:42 PM PDT 24 |
| Finished | Jun 28 08:46:08 PM PDT 24 |
| Peak memory | 574260 kb |
| Host | smart-2a9adcf5-cf48-495d-8825-5009e2881584 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1216182018 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 54.xbar_smoke_slow_rsp.1216182018 |
| Directory | /workspace/54.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/54.xbar_smoke_zero_delays.1191494145 |
| Short name | T1529 |
| Test name | |
| Test status | |
| Simulation time | 54812086 ps |
| CPU time | 7.43 seconds |
| Started | Jun 28 08:44:48 PM PDT 24 |
| Finished | Jun 28 08:45:15 PM PDT 24 |
| Peak memory | 574180 kb |
| Host | smart-690a8447-96a6-4695-93c6-fa9fcc7c095b |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1191494145 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 54.xbar_smoke_zero_delay s.1191494145 |
| Directory | /workspace/54.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/54.xbar_stress_all.2825832384 |
| Short name | T2514 |
| Test name | |
| Test status | |
| Simulation time | 2762012702 ps |
| CPU time | 257.12 seconds |
| Started | Jun 28 08:44:47 PM PDT 24 |
| Finished | Jun 28 08:49:23 PM PDT 24 |
| Peak memory | 575524 kb |
| Host | smart-17b54dee-b09e-4a17-a443-7dad998d16ea |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2825832384 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 54.xbar_stress_all.2825832384 |
| Directory | /workspace/54.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/54.xbar_stress_all_with_error.63111041 |
| Short name | T2852 |
| Test name | |
| Test status | |
| Simulation time | 1540136405 ps |
| CPU time | 116.52 seconds |
| Started | Jun 28 08:44:47 PM PDT 24 |
| Finished | Jun 28 08:47:04 PM PDT 24 |
| Peak memory | 574316 kb |
| Host | smart-e4ce96aa-3b2c-400e-a0e0-b39701f3e190 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63111041 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 54.xbar_stress_all_with_error.63111041 |
| Directory | /workspace/54.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/54.xbar_stress_all_with_reset_error.2617946317 |
| Short name | T1521 |
| Test name | |
| Test status | |
| Simulation time | 381824778 ps |
| CPU time | 116.55 seconds |
| Started | Jun 28 08:44:46 PM PDT 24 |
| Finished | Jun 28 08:47:00 PM PDT 24 |
| Peak memory | 576320 kb |
| Host | smart-97120fe0-ebe9-48d0-9439-7a8b26d8f8f5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2617946317 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 54.xbar_stress_al l_with_reset_error.2617946317 |
| Directory | /workspace/54.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/54.xbar_unmapped_addr.2610516535 |
| Short name | T2331 |
| Test name | |
| Test status | |
| Simulation time | 298595464 ps |
| CPU time | 38.31 seconds |
| Started | Jun 28 08:44:43 PM PDT 24 |
| Finished | Jun 28 08:45:39 PM PDT 24 |
| Peak memory | 575272 kb |
| Host | smart-0167b87f-7a14-4f24-ad64-a526900df0d5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2610516535 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 54.xbar_unmapped_addr.2610516535 |
| Directory | /workspace/54.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/55.xbar_access_same_device.1763382991 |
| Short name | T1387 |
| Test name | |
| Test status | |
| Simulation time | 66527676 ps |
| CPU time | 10.89 seconds |
| Started | Jun 28 08:44:45 PM PDT 24 |
| Finished | Jun 28 08:45:14 PM PDT 24 |
| Peak memory | 575216 kb |
| Host | smart-c1a19eb8-2864-4cbb-8a75-0303188e5953 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1763382991 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 55.xbar_access_same_device .1763382991 |
| Directory | /workspace/55.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/55.xbar_access_same_device_slow_rsp.225752376 |
| Short name | T1760 |
| Test name | |
| Test status | |
| Simulation time | 110528850299 ps |
| CPU time | 1814.08 seconds |
| Started | Jun 28 08:44:47 PM PDT 24 |
| Finished | Jun 28 09:15:20 PM PDT 24 |
| Peak memory | 574280 kb |
| Host | smart-bf09adb7-47ea-4c77-830f-474a88a3f318 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=225752376 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 55.xbar_access_same_d evice_slow_rsp.225752376 |
| Directory | /workspace/55.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/55.xbar_error_and_unmapped_addr.3498083222 |
| Short name | T1788 |
| Test name | |
| Test status | |
| Simulation time | 697596981 ps |
| CPU time | 30.62 seconds |
| Started | Jun 28 08:44:47 PM PDT 24 |
| Finished | Jun 28 08:45:37 PM PDT 24 |
| Peak memory | 574352 kb |
| Host | smart-5a6b2bfb-d23e-4e7e-bb6e-9bcdf175fb38 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3498083222 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 55.xbar_error_and_unmapped_add r.3498083222 |
| Directory | /workspace/55.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/55.xbar_error_random.2174639332 |
| Short name | T1313 |
| Test name | |
| Test status | |
| Simulation time | 2257856446 ps |
| CPU time | 74.6 seconds |
| Started | Jun 28 08:44:43 PM PDT 24 |
| Finished | Jun 28 08:46:14 PM PDT 24 |
| Peak memory | 573944 kb |
| Host | smart-f1139d4e-560a-4c4e-a89b-da90c205bbe9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2174639332 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 55.xbar_error_random.2174639332 |
| Directory | /workspace/55.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/55.xbar_random.1136161416 |
| Short name | T1776 |
| Test name | |
| Test status | |
| Simulation time | 533475548 ps |
| CPU time | 51.32 seconds |
| Started | Jun 28 08:44:48 PM PDT 24 |
| Finished | Jun 28 08:45:58 PM PDT 24 |
| Peak memory | 575256 kb |
| Host | smart-145db3c9-cdbd-4fbe-8eac-169097485565 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1136161416 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 55.xbar_random.1136161416 |
| Directory | /workspace/55.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/55.xbar_random_large_delays.432651846 |
| Short name | T1917 |
| Test name | |
| Test status | |
| Simulation time | 88118398865 ps |
| CPU time | 1012.21 seconds |
| Started | Jun 28 08:44:49 PM PDT 24 |
| Finished | Jun 28 09:02:01 PM PDT 24 |
| Peak memory | 575328 kb |
| Host | smart-f9418fc2-a488-4ebd-95ec-be70ea30fa81 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=432651846 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 55.xbar_random_large_delays.432651846 |
| Directory | /workspace/55.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/55.xbar_random_slow_rsp.2925486697 |
| Short name | T1769 |
| Test name | |
| Test status | |
| Simulation time | 54072850247 ps |
| CPU time | 935.34 seconds |
| Started | Jun 28 08:44:43 PM PDT 24 |
| Finished | Jun 28 09:00:36 PM PDT 24 |
| Peak memory | 575492 kb |
| Host | smart-b4a1d374-ead1-4722-b298-6bcc30060bd0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2925486697 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 55.xbar_random_slow_rsp.2925486697 |
| Directory | /workspace/55.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/55.xbar_random_zero_delays.1023028842 |
| Short name | T2513 |
| Test name | |
| Test status | |
| Simulation time | 299576552 ps |
| CPU time | 30.79 seconds |
| Started | Jun 28 08:44:47 PM PDT 24 |
| Finished | Jun 28 08:45:36 PM PDT 24 |
| Peak memory | 575260 kb |
| Host | smart-b7fcc9f8-9b0f-4936-9a23-e505c2052b8e |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1023028842 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 55.xbar_random_zero_del ays.1023028842 |
| Directory | /workspace/55.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/55.xbar_same_source.305474746 |
| Short name | T2049 |
| Test name | |
| Test status | |
| Simulation time | 2636691768 ps |
| CPU time | 85.95 seconds |
| Started | Jun 28 08:44:44 PM PDT 24 |
| Finished | Jun 28 08:46:29 PM PDT 24 |
| Peak memory | 574172 kb |
| Host | smart-1f625ed2-7680-44dd-a95a-5666c0a7824e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=305474746 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 55.xbar_same_source.305474746 |
| Directory | /workspace/55.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/55.xbar_smoke.3351010949 |
| Short name | T2238 |
| Test name | |
| Test status | |
| Simulation time | 58328588 ps |
| CPU time | 6.81 seconds |
| Started | Jun 28 08:44:45 PM PDT 24 |
| Finished | Jun 28 08:45:10 PM PDT 24 |
| Peak memory | 565956 kb |
| Host | smart-dd5ee5ca-9a5d-4e3b-87cb-94b1eaa8fae4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3351010949 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 55.xbar_smoke.3351010949 |
| Directory | /workspace/55.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/55.xbar_smoke_large_delays.602412130 |
| Short name | T2612 |
| Test name | |
| Test status | |
| Simulation time | 9381449887 ps |
| CPU time | 104.76 seconds |
| Started | Jun 28 08:44:46 PM PDT 24 |
| Finished | Jun 28 08:46:50 PM PDT 24 |
| Peak memory | 574260 kb |
| Host | smart-c02339ee-5e50-412b-a774-73ddceb142e6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=602412130 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 55.xbar_smoke_large_delays.602412130 |
| Directory | /workspace/55.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/55.xbar_smoke_slow_rsp.2311456900 |
| Short name | T2206 |
| Test name | |
| Test status | |
| Simulation time | 6430287856 ps |
| CPU time | 118.51 seconds |
| Started | Jun 28 08:44:46 PM PDT 24 |
| Finished | Jun 28 08:47:04 PM PDT 24 |
| Peak memory | 574280 kb |
| Host | smart-9e0a17c7-4d8e-4b86-a02c-4092532e2900 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2311456900 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 55.xbar_smoke_slow_rsp.2311456900 |
| Directory | /workspace/55.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/55.xbar_smoke_zero_delays.3986156545 |
| Short name | T2078 |
| Test name | |
| Test status | |
| Simulation time | 57472569 ps |
| CPU time | 7.58 seconds |
| Started | Jun 28 08:44:47 PM PDT 24 |
| Finished | Jun 28 08:45:14 PM PDT 24 |
| Peak memory | 574060 kb |
| Host | smart-4b47aed4-42d7-412b-bfa8-f7ca669e38f0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3986156545 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 55.xbar_smoke_zero_delay s.3986156545 |
| Directory | /workspace/55.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/55.xbar_stress_all_with_error.3632620984 |
| Short name | T2257 |
| Test name | |
| Test status | |
| Simulation time | 16942783316 ps |
| CPU time | 692.91 seconds |
| Started | Jun 28 08:45:25 PM PDT 24 |
| Finished | Jun 28 08:57:27 PM PDT 24 |
| Peak memory | 574432 kb |
| Host | smart-925f7afd-56d3-4352-91a5-02a6e3223580 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3632620984 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 55.xbar_stress_all_with_error.3632620984 |
| Directory | /workspace/55.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/55.xbar_stress_all_with_rand_reset.3620492563 |
| Short name | T1539 |
| Test name | |
| Test status | |
| Simulation time | 5882018679 ps |
| CPU time | 426.63 seconds |
| Started | Jun 28 08:45:18 PM PDT 24 |
| Finished | Jun 28 08:52:52 PM PDT 24 |
| Peak memory | 576436 kb |
| Host | smart-a2e8c3fa-bb4a-4719-91ac-4059fe07e521 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3620492563 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 55.xbar_stress_all _with_rand_reset.3620492563 |
| Directory | /workspace/55.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/55.xbar_stress_all_with_reset_error.282100513 |
| Short name | T2141 |
| Test name | |
| Test status | |
| Simulation time | 79387331 ps |
| CPU time | 10.11 seconds |
| Started | Jun 28 08:45:24 PM PDT 24 |
| Finished | Jun 28 08:46:04 PM PDT 24 |
| Peak memory | 574220 kb |
| Host | smart-74f1623d-874b-4d18-ac0f-0e367b141a48 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=282100513 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 55.xbar_stress_all _with_reset_error.282100513 |
| Directory | /workspace/55.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/55.xbar_unmapped_addr.3865172559 |
| Short name | T2510 |
| Test name | |
| Test status | |
| Simulation time | 297037067 ps |
| CPU time | 16.91 seconds |
| Started | Jun 28 08:44:44 PM PDT 24 |
| Finished | Jun 28 08:45:20 PM PDT 24 |
| Peak memory | 574200 kb |
| Host | smart-4f8bb495-fe46-4b8d-86b0-e5b5e0c18db1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3865172559 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 55.xbar_unmapped_addr.3865172559 |
| Directory | /workspace/55.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/56.xbar_access_same_device.914159891 |
| Short name | T1997 |
| Test name | |
| Test status | |
| Simulation time | 1058630299 ps |
| CPU time | 48.33 seconds |
| Started | Jun 28 08:45:20 PM PDT 24 |
| Finished | Jun 28 08:46:37 PM PDT 24 |
| Peak memory | 575232 kb |
| Host | smart-b2aa3d5f-a933-44f8-903f-4c281adef64e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=914159891 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 56.xbar_access_same_device. 914159891 |
| Directory | /workspace/56.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/56.xbar_access_same_device_slow_rsp.1502526244 |
| Short name | T2653 |
| Test name | |
| Test status | |
| Simulation time | 104433505136 ps |
| CPU time | 1777.53 seconds |
| Started | Jun 28 08:45:25 PM PDT 24 |
| Finished | Jun 28 09:15:31 PM PDT 24 |
| Peak memory | 575476 kb |
| Host | smart-733f2be7-c980-4736-bd06-77db463cb218 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1502526244 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 56.xbar_access_same_ device_slow_rsp.1502526244 |
| Directory | /workspace/56.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/56.xbar_error_and_unmapped_addr.3434811235 |
| Short name | T2250 |
| Test name | |
| Test status | |
| Simulation time | 296911308 ps |
| CPU time | 38.59 seconds |
| Started | Jun 28 08:45:16 PM PDT 24 |
| Finished | Jun 28 08:46:22 PM PDT 24 |
| Peak memory | 574208 kb |
| Host | smart-6cbac79c-21fc-45cf-a690-4798b15582ab |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3434811235 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 56.xbar_error_and_unmapped_add r.3434811235 |
| Directory | /workspace/56.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/56.xbar_error_random.1163527400 |
| Short name | T1439 |
| Test name | |
| Test status | |
| Simulation time | 587031244 ps |
| CPU time | 48.46 seconds |
| Started | Jun 28 08:45:16 PM PDT 24 |
| Finished | Jun 28 08:46:32 PM PDT 24 |
| Peak memory | 573836 kb |
| Host | smart-3f8a2511-54bf-4eb3-b0c9-32d5499e88df |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1163527400 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 56.xbar_error_random.1163527400 |
| Directory | /workspace/56.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/56.xbar_random.3801037094 |
| Short name | T2668 |
| Test name | |
| Test status | |
| Simulation time | 1644154412 ps |
| CPU time | 62.22 seconds |
| Started | Jun 28 08:45:18 PM PDT 24 |
| Finished | Jun 28 08:46:49 PM PDT 24 |
| Peak memory | 575392 kb |
| Host | smart-66d96089-6b0e-49db-a1aa-80346dcb6147 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3801037094 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 56.xbar_random.3801037094 |
| Directory | /workspace/56.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/56.xbar_random_large_delays.1285363735 |
| Short name | T2508 |
| Test name | |
| Test status | |
| Simulation time | 36095110247 ps |
| CPU time | 407.37 seconds |
| Started | Jun 28 08:45:19 PM PDT 24 |
| Finished | Jun 28 08:52:33 PM PDT 24 |
| Peak memory | 574256 kb |
| Host | smart-acbccedb-af5a-4025-98e3-7fab1ffed724 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1285363735 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 56.xbar_random_large_delays.1285363735 |
| Directory | /workspace/56.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/56.xbar_random_slow_rsp.2128660219 |
| Short name | T1963 |
| Test name | |
| Test status | |
| Simulation time | 64747419658 ps |
| CPU time | 1123.13 seconds |
| Started | Jun 28 08:45:27 PM PDT 24 |
| Finished | Jun 28 09:04:39 PM PDT 24 |
| Peak memory | 575312 kb |
| Host | smart-66273965-c180-4c40-8ac9-05a32742aa6b |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2128660219 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 56.xbar_random_slow_rsp.2128660219 |
| Directory | /workspace/56.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/56.xbar_random_zero_delays.3326708595 |
| Short name | T2638 |
| Test name | |
| Test status | |
| Simulation time | 104618516 ps |
| CPU time | 12.6 seconds |
| Started | Jun 28 08:45:22 PM PDT 24 |
| Finished | Jun 28 08:46:03 PM PDT 24 |
| Peak memory | 575216 kb |
| Host | smart-37ea0ac0-3277-42b2-b374-2b4ba3c7d38f |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3326708595 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 56.xbar_random_zero_del ays.3326708595 |
| Directory | /workspace/56.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/56.xbar_same_source.633149932 |
| Short name | T600 |
| Test name | |
| Test status | |
| Simulation time | 389708373 ps |
| CPU time | 33.26 seconds |
| Started | Jun 28 08:45:19 PM PDT 24 |
| Finished | Jun 28 08:46:20 PM PDT 24 |
| Peak memory | 575232 kb |
| Host | smart-9fded89b-5d18-42cd-bbf8-638501488111 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=633149932 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 56.xbar_same_source.633149932 |
| Directory | /workspace/56.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/56.xbar_smoke.1600199187 |
| Short name | T1918 |
| Test name | |
| Test status | |
| Simulation time | 168363457 ps |
| CPU time | 8.5 seconds |
| Started | Jun 28 08:45:25 PM PDT 24 |
| Finished | Jun 28 08:46:02 PM PDT 24 |
| Peak memory | 574044 kb |
| Host | smart-b185ef88-8f1f-4143-99b6-080751f72087 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1600199187 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 56.xbar_smoke.1600199187 |
| Directory | /workspace/56.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/56.xbar_smoke_large_delays.4017668604 |
| Short name | T1843 |
| Test name | |
| Test status | |
| Simulation time | 7406689758 ps |
| CPU time | 77.09 seconds |
| Started | Jun 28 08:45:17 PM PDT 24 |
| Finished | Jun 28 08:47:01 PM PDT 24 |
| Peak memory | 574276 kb |
| Host | smart-5d239b92-8641-4779-983d-747ae9d76c82 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4017668604 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 56.xbar_smoke_large_delays.4017668604 |
| Directory | /workspace/56.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/56.xbar_smoke_slow_rsp.3200643223 |
| Short name | T1469 |
| Test name | |
| Test status | |
| Simulation time | 4232062124 ps |
| CPU time | 73.63 seconds |
| Started | Jun 28 08:45:18 PM PDT 24 |
| Finished | Jun 28 08:46:58 PM PDT 24 |
| Peak memory | 565968 kb |
| Host | smart-ea08b3f3-a29c-48c7-b7b0-a1fbaeecc125 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3200643223 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 56.xbar_smoke_slow_rsp.3200643223 |
| Directory | /workspace/56.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/56.xbar_smoke_zero_delays.3960509107 |
| Short name | T2650 |
| Test name | |
| Test status | |
| Simulation time | 53747505 ps |
| CPU time | 6.38 seconds |
| Started | Jun 28 08:45:23 PM PDT 24 |
| Finished | Jun 28 08:46:00 PM PDT 24 |
| Peak memory | 565844 kb |
| Host | smart-ee74a667-a395-4052-81b8-4c20a2a04634 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3960509107 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 56.xbar_smoke_zero_delay s.3960509107 |
| Directory | /workspace/56.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/56.xbar_stress_all.3392593433 |
| Short name | T570 |
| Test name | |
| Test status | |
| Simulation time | 552758074 ps |
| CPU time | 50.14 seconds |
| Started | Jun 28 08:45:16 PM PDT 24 |
| Finished | Jun 28 08:46:34 PM PDT 24 |
| Peak memory | 575296 kb |
| Host | smart-e3f08534-6d52-40ba-b7a1-8216d0c4604c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3392593433 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 56.xbar_stress_all.3392593433 |
| Directory | /workspace/56.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/56.xbar_stress_all_with_error.4266421007 |
| Short name | T2122 |
| Test name | |
| Test status | |
| Simulation time | 15322690921 ps |
| CPU time | 617.34 seconds |
| Started | Jun 28 08:45:24 PM PDT 24 |
| Finished | Jun 28 08:56:11 PM PDT 24 |
| Peak memory | 574668 kb |
| Host | smart-7b0ff8de-2057-4e98-97cc-85f2e27f4386 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4266421007 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 56.xbar_stress_all_with_error.4266421007 |
| Directory | /workspace/56.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/56.xbar_stress_all_with_rand_reset.2449411589 |
| Short name | T1786 |
| Test name | |
| Test status | |
| Simulation time | 5030489732 ps |
| CPU time | 402.45 seconds |
| Started | Jun 28 08:45:17 PM PDT 24 |
| Finished | Jun 28 08:52:26 PM PDT 24 |
| Peak memory | 577568 kb |
| Host | smart-3777cef1-c2e7-447c-b65a-658728300b5b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2449411589 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 56.xbar_stress_all _with_rand_reset.2449411589 |
| Directory | /workspace/56.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/56.xbar_stress_all_with_reset_error.4014001599 |
| Short name | T827 |
| Test name | |
| Test status | |
| Simulation time | 15114341926 ps |
| CPU time | 739.96 seconds |
| Started | Jun 28 08:45:25 PM PDT 24 |
| Finished | Jun 28 08:58:14 PM PDT 24 |
| Peak memory | 576476 kb |
| Host | smart-ff4988d9-b374-4b38-ac31-45a71efbf948 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4014001599 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 56.xbar_stress_al l_with_reset_error.4014001599 |
| Directory | /workspace/56.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/56.xbar_unmapped_addr.373516064 |
| Short name | T2715 |
| Test name | |
| Test status | |
| Simulation time | 1010120352 ps |
| CPU time | 43.43 seconds |
| Started | Jun 28 08:45:16 PM PDT 24 |
| Finished | Jun 28 08:46:27 PM PDT 24 |
| Peak memory | 575288 kb |
| Host | smart-c55fdf13-b435-4ce1-9cde-63b16ffb10f9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=373516064 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 56.xbar_unmapped_addr.373516064 |
| Directory | /workspace/56.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/57.xbar_access_same_device.3814073339 |
| Short name | T2143 |
| Test name | |
| Test status | |
| Simulation time | 859666737 ps |
| CPU time | 66.78 seconds |
| Started | Jun 28 08:45:16 PM PDT 24 |
| Finished | Jun 28 08:46:50 PM PDT 24 |
| Peak memory | 575236 kb |
| Host | smart-01dd4d3c-f232-49d2-8239-410d7dcc0316 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3814073339 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 57.xbar_access_same_device .3814073339 |
| Directory | /workspace/57.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/57.xbar_access_same_device_slow_rsp.2300886574 |
| Short name | T1930 |
| Test name | |
| Test status | |
| Simulation time | 141473174207 ps |
| CPU time | 2400.98 seconds |
| Started | Jun 28 08:45:25 PM PDT 24 |
| Finished | Jun 28 09:25:55 PM PDT 24 |
| Peak memory | 575416 kb |
| Host | smart-877eb347-14b9-4f18-bcde-c87772209f74 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2300886574 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 57.xbar_access_same_ device_slow_rsp.2300886574 |
| Directory | /workspace/57.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/57.xbar_error_and_unmapped_addr.289186255 |
| Short name | T2541 |
| Test name | |
| Test status | |
| Simulation time | 1204926718 ps |
| CPU time | 50.16 seconds |
| Started | Jun 28 08:45:17 PM PDT 24 |
| Finished | Jun 28 08:46:34 PM PDT 24 |
| Peak memory | 573912 kb |
| Host | smart-85869e74-c55c-468a-8853-bd5cae2952ef |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=289186255 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 57.xbar_error_and_unmapped_addr .289186255 |
| Directory | /workspace/57.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/57.xbar_error_random.2281373087 |
| Short name | T1537 |
| Test name | |
| Test status | |
| Simulation time | 1642131904 ps |
| CPU time | 60.41 seconds |
| Started | Jun 28 08:45:21 PM PDT 24 |
| Finished | Jun 28 08:46:50 PM PDT 24 |
| Peak memory | 574404 kb |
| Host | smart-d4c8e2b6-3551-47f6-a801-c1b162cec70b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2281373087 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 57.xbar_error_random.2281373087 |
| Directory | /workspace/57.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/57.xbar_random.2409411639 |
| Short name | T2493 |
| Test name | |
| Test status | |
| Simulation time | 73178031 ps |
| CPU time | 10.02 seconds |
| Started | Jun 28 08:45:25 PM PDT 24 |
| Finished | Jun 28 08:46:04 PM PDT 24 |
| Peak memory | 574232 kb |
| Host | smart-e0c5945b-622b-47e1-8286-cf26b6ceb02a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2409411639 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 57.xbar_random.2409411639 |
| Directory | /workspace/57.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/57.xbar_random_large_delays.3269688109 |
| Short name | T2075 |
| Test name | |
| Test status | |
| Simulation time | 55276821268 ps |
| CPU time | 616.87 seconds |
| Started | Jun 28 08:45:19 PM PDT 24 |
| Finished | Jun 28 08:56:04 PM PDT 24 |
| Peak memory | 575444 kb |
| Host | smart-fed3f73b-6450-46c8-a601-d727958fed25 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3269688109 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 57.xbar_random_large_delays.3269688109 |
| Directory | /workspace/57.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/57.xbar_random_slow_rsp.1253938933 |
| Short name | T1421 |
| Test name | |
| Test status | |
| Simulation time | 4178785510 ps |
| CPU time | 68.29 seconds |
| Started | Jun 28 08:45:17 PM PDT 24 |
| Finished | Jun 28 08:46:52 PM PDT 24 |
| Peak memory | 574256 kb |
| Host | smart-4c2ffab3-5a26-4538-af95-3ba9cc16cc08 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1253938933 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 57.xbar_random_slow_rsp.1253938933 |
| Directory | /workspace/57.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/57.xbar_random_zero_delays.1410410592 |
| Short name | T1784 |
| Test name | |
| Test status | |
| Simulation time | 287250230 ps |
| CPU time | 26.52 seconds |
| Started | Jun 28 08:45:22 PM PDT 24 |
| Finished | Jun 28 08:46:17 PM PDT 24 |
| Peak memory | 575244 kb |
| Host | smart-9b7e62e1-bc6a-4451-8d01-c9a73f812de3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1410410592 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 57.xbar_random_zero_del ays.1410410592 |
| Directory | /workspace/57.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/57.xbar_same_source.379954575 |
| Short name | T2791 |
| Test name | |
| Test status | |
| Simulation time | 242561618 ps |
| CPU time | 10.55 seconds |
| Started | Jun 28 08:45:19 PM PDT 24 |
| Finished | Jun 28 08:45:58 PM PDT 24 |
| Peak memory | 574016 kb |
| Host | smart-c1aa2fea-1338-4098-b6ae-d61e7202fe97 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=379954575 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 57.xbar_same_source.379954575 |
| Directory | /workspace/57.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/57.xbar_smoke.3326668224 |
| Short name | T2860 |
| Test name | |
| Test status | |
| Simulation time | 52028755 ps |
| CPU time | 6.21 seconds |
| Started | Jun 28 08:45:22 PM PDT 24 |
| Finished | Jun 28 08:45:56 PM PDT 24 |
| Peak memory | 574100 kb |
| Host | smart-71868546-5fea-44ac-9460-1cf9cc9995ab |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3326668224 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 57.xbar_smoke.3326668224 |
| Directory | /workspace/57.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/57.xbar_smoke_large_delays.3599564393 |
| Short name | T2361 |
| Test name | |
| Test status | |
| Simulation time | 8044717375 ps |
| CPU time | 83.51 seconds |
| Started | Jun 28 08:45:20 PM PDT 24 |
| Finished | Jun 28 08:47:11 PM PDT 24 |
| Peak memory | 574256 kb |
| Host | smart-5b1defeb-0688-4fe0-a492-ac400be0406b |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3599564393 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 57.xbar_smoke_large_delays.3599564393 |
| Directory | /workspace/57.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/57.xbar_smoke_slow_rsp.1647327880 |
| Short name | T1811 |
| Test name | |
| Test status | |
| Simulation time | 4565419994 ps |
| CPU time | 80.65 seconds |
| Started | Jun 28 08:45:20 PM PDT 24 |
| Finished | Jun 28 08:47:08 PM PDT 24 |
| Peak memory | 574244 kb |
| Host | smart-8e136ab1-b41e-4c61-b865-67c7c075a573 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1647327880 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 57.xbar_smoke_slow_rsp.1647327880 |
| Directory | /workspace/57.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/57.xbar_smoke_zero_delays.2895833700 |
| Short name | T2701 |
| Test name | |
| Test status | |
| Simulation time | 47828422 ps |
| CPU time | 6.8 seconds |
| Started | Jun 28 08:45:19 PM PDT 24 |
| Finished | Jun 28 08:45:54 PM PDT 24 |
| Peak memory | 565940 kb |
| Host | smart-c5034681-fd6c-4ae1-b813-19988e17548e |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2895833700 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 57.xbar_smoke_zero_delay s.2895833700 |
| Directory | /workspace/57.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/57.xbar_stress_all.3076247666 |
| Short name | T1705 |
| Test name | |
| Test status | |
| Simulation time | 981735761 ps |
| CPU time | 86.16 seconds |
| Started | Jun 28 08:45:16 PM PDT 24 |
| Finished | Jun 28 08:47:10 PM PDT 24 |
| Peak memory | 575368 kb |
| Host | smart-e6c0af70-b6e6-4a65-b8be-28c20f879e93 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3076247666 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 57.xbar_stress_all.3076247666 |
| Directory | /workspace/57.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/57.xbar_stress_all_with_error.4245397414 |
| Short name | T1826 |
| Test name | |
| Test status | |
| Simulation time | 1062394955 ps |
| CPU time | 97.78 seconds |
| Started | Jun 28 08:45:24 PM PDT 24 |
| Finished | Jun 28 08:47:31 PM PDT 24 |
| Peak memory | 574236 kb |
| Host | smart-de2e444a-793b-4708-9709-341704fbc022 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4245397414 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 57.xbar_stress_all_with_error.4245397414 |
| Directory | /workspace/57.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/57.xbar_stress_all_with_rand_reset.1628861340 |
| Short name | T2424 |
| Test name | |
| Test status | |
| Simulation time | 740517333 ps |
| CPU time | 263.94 seconds |
| Started | Jun 28 08:45:23 PM PDT 24 |
| Finished | Jun 28 08:50:17 PM PDT 24 |
| Peak memory | 575392 kb |
| Host | smart-12dc4252-73e8-484a-85ea-3627e7870ea1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1628861340 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 57.xbar_stress_all _with_rand_reset.1628861340 |
| Directory | /workspace/57.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/57.xbar_stress_all_with_reset_error.2200893446 |
| Short name | T2765 |
| Test name | |
| Test status | |
| Simulation time | 8898235478 ps |
| CPU time | 805.91 seconds |
| Started | Jun 28 08:45:19 PM PDT 24 |
| Finished | Jun 28 08:59:13 PM PDT 24 |
| Peak memory | 574376 kb |
| Host | smart-eefc167e-4048-45a5-a625-136029751894 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2200893446 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 57.xbar_stress_al l_with_reset_error.2200893446 |
| Directory | /workspace/57.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/57.xbar_unmapped_addr.8332566 |
| Short name | T2877 |
| Test name | |
| Test status | |
| Simulation time | 59506548 ps |
| CPU time | 6.16 seconds |
| Started | Jun 28 08:45:25 PM PDT 24 |
| Finished | Jun 28 08:46:00 PM PDT 24 |
| Peak memory | 565968 kb |
| Host | smart-dfc62c47-ccd2-4653-8a3d-9ab6ca297e47 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=8332566 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 57.xbar_unmapped_addr.8332566 |
| Directory | /workspace/57.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/58.xbar_access_same_device.1595147718 |
| Short name | T2753 |
| Test name | |
| Test status | |
| Simulation time | 2188017886 ps |
| CPU time | 126.43 seconds |
| Started | Jun 28 08:45:20 PM PDT 24 |
| Finished | Jun 28 08:47:56 PM PDT 24 |
| Peak memory | 574276 kb |
| Host | smart-cdd0764d-dc87-4d7e-81d7-3b0843b43ed9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1595147718 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 58.xbar_access_same_device .1595147718 |
| Directory | /workspace/58.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/58.xbar_access_same_device_slow_rsp.1899986067 |
| Short name | T817 |
| Test name | |
| Test status | |
| Simulation time | 94829573486 ps |
| CPU time | 1634.59 seconds |
| Started | Jun 28 08:45:25 PM PDT 24 |
| Finished | Jun 28 09:13:09 PM PDT 24 |
| Peak memory | 575432 kb |
| Host | smart-d0f83306-8103-4634-b5f3-299746f9ae52 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1899986067 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 58.xbar_access_same_ device_slow_rsp.1899986067 |
| Directory | /workspace/58.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/58.xbar_error_and_unmapped_addr.1702054799 |
| Short name | T1413 |
| Test name | |
| Test status | |
| Simulation time | 739968293 ps |
| CPU time | 31.37 seconds |
| Started | Jun 28 08:45:24 PM PDT 24 |
| Finished | Jun 28 08:46:25 PM PDT 24 |
| Peak memory | 574392 kb |
| Host | smart-d533807f-cab2-4913-a7c3-d0ae713e3897 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1702054799 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 58.xbar_error_and_unmapped_add r.1702054799 |
| Directory | /workspace/58.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/58.xbar_error_random.1717407574 |
| Short name | T2474 |
| Test name | |
| Test status | |
| Simulation time | 40258788 ps |
| CPU time | 6.61 seconds |
| Started | Jun 28 08:45:16 PM PDT 24 |
| Finished | Jun 28 08:45:50 PM PDT 24 |
| Peak memory | 565628 kb |
| Host | smart-66c713b4-b247-40e5-97b8-5e413503c8af |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1717407574 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 58.xbar_error_random.1717407574 |
| Directory | /workspace/58.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/58.xbar_random.1675642256 |
| Short name | T1793 |
| Test name | |
| Test status | |
| Simulation time | 178079684 ps |
| CPU time | 17.68 seconds |
| Started | Jun 28 08:45:18 PM PDT 24 |
| Finished | Jun 28 08:46:02 PM PDT 24 |
| Peak memory | 575244 kb |
| Host | smart-7be71a11-f3e7-467b-8222-63680e290299 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1675642256 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 58.xbar_random.1675642256 |
| Directory | /workspace/58.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/58.xbar_random_large_delays.4066177472 |
| Short name | T1722 |
| Test name | |
| Test status | |
| Simulation time | 5199465265 ps |
| CPU time | 54.89 seconds |
| Started | Jun 28 08:45:21 PM PDT 24 |
| Finished | Jun 28 08:46:45 PM PDT 24 |
| Peak memory | 566056 kb |
| Host | smart-b6092cd5-7fd7-4009-80dc-8e77981cdad4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4066177472 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 58.xbar_random_large_delays.4066177472 |
| Directory | /workspace/58.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/58.xbar_random_slow_rsp.649889098 |
| Short name | T616 |
| Test name | |
| Test status | |
| Simulation time | 47413656498 ps |
| CPU time | 815.26 seconds |
| Started | Jun 28 08:45:25 PM PDT 24 |
| Finished | Jun 28 08:59:29 PM PDT 24 |
| Peak memory | 575324 kb |
| Host | smart-3584f148-a93b-42b8-9c88-6f5eb94fbded |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=649889098 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 58.xbar_random_slow_rsp.649889098 |
| Directory | /workspace/58.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/58.xbar_random_zero_delays.4101200634 |
| Short name | T2595 |
| Test name | |
| Test status | |
| Simulation time | 220812906 ps |
| CPU time | 23.78 seconds |
| Started | Jun 28 08:45:23 PM PDT 24 |
| Finished | Jun 28 08:46:17 PM PDT 24 |
| Peak memory | 575248 kb |
| Host | smart-8692a42a-2f6b-4e03-a2d9-8d2661f7e378 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4101200634 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 58.xbar_random_zero_del ays.4101200634 |
| Directory | /workspace/58.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/58.xbar_same_source.1673586581 |
| Short name | T1496 |
| Test name | |
| Test status | |
| Simulation time | 456652643 ps |
| CPU time | 16.5 seconds |
| Started | Jun 28 08:45:18 PM PDT 24 |
| Finished | Jun 28 08:46:02 PM PDT 24 |
| Peak memory | 574156 kb |
| Host | smart-6d9321cb-87a9-495d-8106-c6ab3ecba78e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1673586581 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 58.xbar_same_source.1673586581 |
| Directory | /workspace/58.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/58.xbar_smoke.2194635958 |
| Short name | T2071 |
| Test name | |
| Test status | |
| Simulation time | 42146792 ps |
| CPU time | 6.44 seconds |
| Started | Jun 28 08:45:17 PM PDT 24 |
| Finished | Jun 28 08:45:50 PM PDT 24 |
| Peak memory | 574168 kb |
| Host | smart-4aa46521-d2ca-42c8-b9cd-573ea8c5a7f1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2194635958 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 58.xbar_smoke.2194635958 |
| Directory | /workspace/58.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/58.xbar_smoke_large_delays.2821204753 |
| Short name | T2486 |
| Test name | |
| Test status | |
| Simulation time | 5567186051 ps |
| CPU time | 62.16 seconds |
| Started | Jun 28 08:45:18 PM PDT 24 |
| Finished | Jun 28 08:46:46 PM PDT 24 |
| Peak memory | 574080 kb |
| Host | smart-2547694e-a5e8-44b1-a06e-7dff04152dcf |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2821204753 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 58.xbar_smoke_large_delays.2821204753 |
| Directory | /workspace/58.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/58.xbar_smoke_slow_rsp.2360347099 |
| Short name | T2233 |
| Test name | |
| Test status | |
| Simulation time | 4614684987 ps |
| CPU time | 81.61 seconds |
| Started | Jun 28 08:45:25 PM PDT 24 |
| Finished | Jun 28 08:47:16 PM PDT 24 |
| Peak memory | 574132 kb |
| Host | smart-722a4105-62d3-41ea-92f2-75f3afc39268 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2360347099 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 58.xbar_smoke_slow_rsp.2360347099 |
| Directory | /workspace/58.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/58.xbar_smoke_zero_delays.2924875028 |
| Short name | T2836 |
| Test name | |
| Test status | |
| Simulation time | 47167581 ps |
| CPU time | 6.8 seconds |
| Started | Jun 28 08:45:17 PM PDT 24 |
| Finished | Jun 28 08:45:51 PM PDT 24 |
| Peak memory | 574184 kb |
| Host | smart-4fe5abe4-2c27-43a4-bf20-204d0718e48e |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2924875028 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 58.xbar_smoke_zero_delay s.2924875028 |
| Directory | /workspace/58.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/58.xbar_stress_all.3805230920 |
| Short name | T2536 |
| Test name | |
| Test status | |
| Simulation time | 7356082414 ps |
| CPU time | 312 seconds |
| Started | Jun 28 08:45:17 PM PDT 24 |
| Finished | Jun 28 08:50:56 PM PDT 24 |
| Peak memory | 575448 kb |
| Host | smart-3f28bb07-e331-4888-89bf-e79541757b52 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3805230920 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 58.xbar_stress_all.3805230920 |
| Directory | /workspace/58.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/58.xbar_stress_all_with_error.2928161649 |
| Short name | T2551 |
| Test name | |
| Test status | |
| Simulation time | 3688943160 ps |
| CPU time | 315 seconds |
| Started | Jun 28 08:45:26 PM PDT 24 |
| Finished | Jun 28 08:51:11 PM PDT 24 |
| Peak memory | 574312 kb |
| Host | smart-58eef6cd-8a83-4665-9f92-b242ee22cf1c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2928161649 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 58.xbar_stress_all_with_error.2928161649 |
| Directory | /workspace/58.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/58.xbar_stress_all_with_rand_reset.3426981399 |
| Short name | T466 |
| Test name | |
| Test status | |
| Simulation time | 1370076528 ps |
| CPU time | 177.29 seconds |
| Started | Jun 28 08:45:27 PM PDT 24 |
| Finished | Jun 28 08:48:53 PM PDT 24 |
| Peak memory | 575384 kb |
| Host | smart-b9bfd927-2502-4c9f-a34f-8bf775cc1c12 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3426981399 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 58.xbar_stress_all _with_rand_reset.3426981399 |
| Directory | /workspace/58.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/58.xbar_stress_all_with_reset_error.391105683 |
| Short name | T793 |
| Test name | |
| Test status | |
| Simulation time | 5691259422 ps |
| CPU time | 481.84 seconds |
| Started | Jun 28 08:45:26 PM PDT 24 |
| Finished | Jun 28 08:53:58 PM PDT 24 |
| Peak memory | 574436 kb |
| Host | smart-ec182725-104b-4b0e-aea7-385b7ac18f1e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=391105683 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 58.xbar_stress_all _with_reset_error.391105683 |
| Directory | /workspace/58.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/58.xbar_unmapped_addr.1921981142 |
| Short name | T2524 |
| Test name | |
| Test status | |
| Simulation time | 298063503 ps |
| CPU time | 38.61 seconds |
| Started | Jun 28 08:45:22 PM PDT 24 |
| Finished | Jun 28 08:46:29 PM PDT 24 |
| Peak memory | 574232 kb |
| Host | smart-ecc00dab-4d17-4784-8077-6ee0a6f7a8d9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1921981142 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 58.xbar_unmapped_addr.1921981142 |
| Directory | /workspace/58.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/59.xbar_access_same_device.3742742782 |
| Short name | T2312 |
| Test name | |
| Test status | |
| Simulation time | 1673684967 ps |
| CPU time | 69.94 seconds |
| Started | Jun 28 08:45:30 PM PDT 24 |
| Finished | Jun 28 08:47:07 PM PDT 24 |
| Peak memory | 575232 kb |
| Host | smart-529ea4dd-8151-40ba-9460-e6d43eb2b0ef |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3742742782 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 59.xbar_access_same_device .3742742782 |
| Directory | /workspace/59.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/59.xbar_access_same_device_slow_rsp.3267861331 |
| Short name | T2841 |
| Test name | |
| Test status | |
| Simulation time | 97304032674 ps |
| CPU time | 1559.14 seconds |
| Started | Jun 28 08:45:30 PM PDT 24 |
| Finished | Jun 28 09:11:57 PM PDT 24 |
| Peak memory | 574364 kb |
| Host | smart-3b26ee4e-d27a-4bbb-9827-54474a34d7c8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3267861331 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 59.xbar_access_same_ device_slow_rsp.3267861331 |
| Directory | /workspace/59.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/59.xbar_error_and_unmapped_addr.2400061292 |
| Short name | T1577 |
| Test name | |
| Test status | |
| Simulation time | 926405019 ps |
| CPU time | 36.55 seconds |
| Started | Jun 28 08:45:31 PM PDT 24 |
| Finished | Jun 28 08:46:34 PM PDT 24 |
| Peak memory | 574200 kb |
| Host | smart-b6a194f1-0eec-449c-ae90-d7ab77ee259f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2400061292 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 59.xbar_error_and_unmapped_add r.2400061292 |
| Directory | /workspace/59.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/59.xbar_error_random.1769811884 |
| Short name | T1720 |
| Test name | |
| Test status | |
| Simulation time | 473459584 ps |
| CPU time | 44.28 seconds |
| Started | Jun 28 08:45:17 PM PDT 24 |
| Finished | Jun 28 08:46:28 PM PDT 24 |
| Peak memory | 573808 kb |
| Host | smart-d8650aba-2f07-4cba-93c0-32df10fa57a1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1769811884 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 59.xbar_error_random.1769811884 |
| Directory | /workspace/59.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/59.xbar_random.232184613 |
| Short name | T2675 |
| Test name | |
| Test status | |
| Simulation time | 951090575 ps |
| CPU time | 33.85 seconds |
| Started | Jun 28 08:45:25 PM PDT 24 |
| Finished | Jun 28 08:46:27 PM PDT 24 |
| Peak memory | 574168 kb |
| Host | smart-76ee3534-0596-4cee-9e26-e264d32afbcf |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=232184613 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 59.xbar_random.232184613 |
| Directory | /workspace/59.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/59.xbar_random_large_delays.3624932856 |
| Short name | T2117 |
| Test name | |
| Test status | |
| Simulation time | 66958133214 ps |
| CPU time | 729.2 seconds |
| Started | Jun 28 08:45:30 PM PDT 24 |
| Finished | Jun 28 08:58:07 PM PDT 24 |
| Peak memory | 575336 kb |
| Host | smart-5be67486-ddaa-466c-8b66-5945bcf47b62 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3624932856 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 59.xbar_random_large_delays.3624932856 |
| Directory | /workspace/59.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/59.xbar_random_slow_rsp.3660509075 |
| Short name | T2151 |
| Test name | |
| Test status | |
| Simulation time | 26973078601 ps |
| CPU time | 460.52 seconds |
| Started | Jun 28 08:45:24 PM PDT 24 |
| Finished | Jun 28 08:53:34 PM PDT 24 |
| Peak memory | 575340 kb |
| Host | smart-fa36ee84-59a5-4bb9-a399-4ed750852244 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3660509075 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 59.xbar_random_slow_rsp.3660509075 |
| Directory | /workspace/59.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/59.xbar_random_zero_delays.3140201425 |
| Short name | T2518 |
| Test name | |
| Test status | |
| Simulation time | 613591799 ps |
| CPU time | 53.94 seconds |
| Started | Jun 28 08:45:27 PM PDT 24 |
| Finished | Jun 28 08:46:50 PM PDT 24 |
| Peak memory | 575140 kb |
| Host | smart-7f61d8cd-29aa-4248-9631-4e6abb8379f9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3140201425 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 59.xbar_random_zero_del ays.3140201425 |
| Directory | /workspace/59.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/59.xbar_same_source.1845228926 |
| Short name | T1528 |
| Test name | |
| Test status | |
| Simulation time | 2091470892 ps |
| CPU time | 61.84 seconds |
| Started | Jun 28 08:45:30 PM PDT 24 |
| Finished | Jun 28 08:46:59 PM PDT 24 |
| Peak memory | 575232 kb |
| Host | smart-51f852d7-22a4-4771-9c0f-28ded8225543 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1845228926 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 59.xbar_same_source.1845228926 |
| Directory | /workspace/59.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/59.xbar_smoke.3955572160 |
| Short name | T1348 |
| Test name | |
| Test status | |
| Simulation time | 46694722 ps |
| CPU time | 6.28 seconds |
| Started | Jun 28 08:45:25 PM PDT 24 |
| Finished | Jun 28 08:46:00 PM PDT 24 |
| Peak memory | 565956 kb |
| Host | smart-11c6f26b-7736-43c7-b40c-7d6e06fd4f8e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3955572160 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 59.xbar_smoke.3955572160 |
| Directory | /workspace/59.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/59.xbar_smoke_large_delays.3272256013 |
| Short name | T1885 |
| Test name | |
| Test status | |
| Simulation time | 7363262391 ps |
| CPU time | 80.28 seconds |
| Started | Jun 28 08:45:24 PM PDT 24 |
| Finished | Jun 28 08:47:14 PM PDT 24 |
| Peak memory | 574260 kb |
| Host | smart-14a458ad-8f51-4ac4-b9de-fb446e591125 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3272256013 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 59.xbar_smoke_large_delays.3272256013 |
| Directory | /workspace/59.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/59.xbar_smoke_slow_rsp.3398535272 |
| Short name | T2520 |
| Test name | |
| Test status | |
| Simulation time | 6702557750 ps |
| CPU time | 110.59 seconds |
| Started | Jun 28 08:45:24 PM PDT 24 |
| Finished | Jun 28 08:47:44 PM PDT 24 |
| Peak memory | 574256 kb |
| Host | smart-93867a4f-d1a1-4113-8d7b-5e01a3e11097 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3398535272 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 59.xbar_smoke_slow_rsp.3398535272 |
| Directory | /workspace/59.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/59.xbar_smoke_zero_delays.3695364328 |
| Short name | T2063 |
| Test name | |
| Test status | |
| Simulation time | 48541636 ps |
| CPU time | 6.59 seconds |
| Started | Jun 28 08:45:30 PM PDT 24 |
| Finished | Jun 28 08:46:04 PM PDT 24 |
| Peak memory | 574188 kb |
| Host | smart-b7928c82-3faa-4323-9677-3f6d53de5f3a |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3695364328 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 59.xbar_smoke_zero_delay s.3695364328 |
| Directory | /workspace/59.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/59.xbar_stress_all.1497348190 |
| Short name | T2796 |
| Test name | |
| Test status | |
| Simulation time | 3963501500 ps |
| CPU time | 141.03 seconds |
| Started | Jun 28 08:45:30 PM PDT 24 |
| Finished | Jun 28 08:48:19 PM PDT 24 |
| Peak memory | 575440 kb |
| Host | smart-755b4611-ef79-4205-964c-20952198e743 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1497348190 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 59.xbar_stress_all.1497348190 |
| Directory | /workspace/59.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/59.xbar_stress_all_with_error.3439713384 |
| Short name | T1818 |
| Test name | |
| Test status | |
| Simulation time | 421432842 ps |
| CPU time | 33.5 seconds |
| Started | Jun 28 08:45:20 PM PDT 24 |
| Finished | Jun 28 08:46:23 PM PDT 24 |
| Peak memory | 574180 kb |
| Host | smart-f51a91b4-f20e-4a1b-9a85-fc7e034a580a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3439713384 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 59.xbar_stress_all_with_error.3439713384 |
| Directory | /workspace/59.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/59.xbar_stress_all_with_rand_reset.3501799746 |
| Short name | T2522 |
| Test name | |
| Test status | |
| Simulation time | 15643553455 ps |
| CPU time | 778.41 seconds |
| Started | Jun 28 08:45:31 PM PDT 24 |
| Finished | Jun 28 08:58:56 PM PDT 24 |
| Peak memory | 576440 kb |
| Host | smart-f5f48070-fc5a-4f41-b4d2-32431f2087c9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3501799746 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 59.xbar_stress_all _with_rand_reset.3501799746 |
| Directory | /workspace/59.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/59.xbar_unmapped_addr.602038834 |
| Short name | T2205 |
| Test name | |
| Test status | |
| Simulation time | 1234118185 ps |
| CPU time | 52.75 seconds |
| Started | Jun 28 08:45:30 PM PDT 24 |
| Finished | Jun 28 08:46:51 PM PDT 24 |
| Peak memory | 575312 kb |
| Host | smart-839a2c07-5a1a-4916-9b00-d6bfae03e379 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=602038834 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 59.xbar_unmapped_addr.602038834 |
| Directory | /workspace/59.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/6.chip_csr_rw.1681098159 |
| Short name | T380 |
| Test name | |
| Test status | |
| Simulation time | 4115265935 ps |
| CPU time | 412.92 seconds |
| Started | Jun 28 08:31:57 PM PDT 24 |
| Finished | Jun 28 08:39:01 PM PDT 24 |
| Peak memory | 595820 kb |
| Host | smart-2b9de815-9286-453f-a4b6-90ab252846d5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1681098159 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.chip_csr_rw.1681098159 |
| Directory | /workspace/6.chip_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/6.xbar_access_same_device.1297780796 |
| Short name | T2566 |
| Test name | |
| Test status | |
| Simulation time | 14495048 ps |
| CPU time | 7.1 seconds |
| Started | Jun 28 08:31:57 PM PDT 24 |
| Finished | Jun 28 08:32:14 PM PDT 24 |
| Peak memory | 574220 kb |
| Host | smart-1deb8d4e-084d-48a8-98a3-1931bbc296f5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1297780796 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.xbar_access_same_device. 1297780796 |
| Directory | /workspace/6.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/6.xbar_access_same_device_slow_rsp.3041753834 |
| Short name | T816 |
| Test name | |
| Test status | |
| Simulation time | 102071001680 ps |
| CPU time | 1822.46 seconds |
| Started | Jun 28 08:31:57 PM PDT 24 |
| Finished | Jun 28 09:02:31 PM PDT 24 |
| Peak memory | 575420 kb |
| Host | smart-c4df8f9d-0442-40a4-aed7-8d5862df6624 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3041753834 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.xbar_access_same_d evice_slow_rsp.3041753834 |
| Directory | /workspace/6.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/6.xbar_error_and_unmapped_addr.3885462826 |
| Short name | T1828 |
| Test name | |
| Test status | |
| Simulation time | 385227711 ps |
| CPU time | 19.54 seconds |
| Started | Jun 28 08:31:54 PM PDT 24 |
| Finished | Jun 28 08:32:24 PM PDT 24 |
| Peak memory | 574436 kb |
| Host | smart-d275085a-5c54-4d24-965a-e4ea0e4eb1d9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3885462826 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.xbar_error_and_unmapped_addr .3885462826 |
| Directory | /workspace/6.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/6.xbar_error_random.2153844129 |
| Short name | T2157 |
| Test name | |
| Test status | |
| Simulation time | 1558979945 ps |
| CPU time | 58.23 seconds |
| Started | Jun 28 08:31:56 PM PDT 24 |
| Finished | Jun 28 08:33:04 PM PDT 24 |
| Peak memory | 574444 kb |
| Host | smart-f295105b-7307-43fc-b6d7-24bc25771c8e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2153844129 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.xbar_error_random.2153844129 |
| Directory | /workspace/6.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/6.xbar_random.661958113 |
| Short name | T1789 |
| Test name | |
| Test status | |
| Simulation time | 1776394153 ps |
| CPU time | 65.06 seconds |
| Started | Jun 28 08:31:55 PM PDT 24 |
| Finished | Jun 28 08:33:10 PM PDT 24 |
| Peak memory | 574204 kb |
| Host | smart-8e59f9b3-c239-4b2e-8ffd-8c9621d03309 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=661958113 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.xbar_random.661958113 |
| Directory | /workspace/6.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/6.xbar_random_large_delays.4260384463 |
| Short name | T1910 |
| Test name | |
| Test status | |
| Simulation time | 34901850283 ps |
| CPU time | 363.69 seconds |
| Started | Jun 28 08:31:58 PM PDT 24 |
| Finished | Jun 28 08:38:12 PM PDT 24 |
| Peak memory | 575328 kb |
| Host | smart-1ca883f0-2239-4c16-b01c-3b3bfffe3077 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4260384463 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.xbar_random_large_delays.4260384463 |
| Directory | /workspace/6.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/6.xbar_random_slow_rsp.652686447 |
| Short name | T1544 |
| Test name | |
| Test status | |
| Simulation time | 43477312228 ps |
| CPU time | 764.22 seconds |
| Started | Jun 28 08:31:58 PM PDT 24 |
| Finished | Jun 28 08:44:53 PM PDT 24 |
| Peak memory | 575372 kb |
| Host | smart-8fc29c76-33eb-44df-b213-427c5efa1169 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=652686447 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.xbar_random_slow_rsp.652686447 |
| Directory | /workspace/6.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/6.xbar_random_zero_delays.2841517878 |
| Short name | T1503 |
| Test name | |
| Test status | |
| Simulation time | 166351659 ps |
| CPU time | 17.33 seconds |
| Started | Jun 28 08:31:55 PM PDT 24 |
| Finished | Jun 28 08:32:22 PM PDT 24 |
| Peak memory | 575212 kb |
| Host | smart-a19a2247-1f37-421e-9e1d-483bb93691b3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2841517878 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.xbar_random_zero_dela ys.2841517878 |
| Directory | /workspace/6.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/6.xbar_same_source.4019163059 |
| Short name | T1768 |
| Test name | |
| Test status | |
| Simulation time | 228577510 ps |
| CPU time | 21.45 seconds |
| Started | Jun 28 08:31:59 PM PDT 24 |
| Finished | Jun 28 08:32:31 PM PDT 24 |
| Peak memory | 574108 kb |
| Host | smart-1be55bc6-0f8f-4a08-92f0-bd0ef7a7d0af |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4019163059 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.xbar_same_source.4019163059 |
| Directory | /workspace/6.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/6.xbar_smoke.2427182737 |
| Short name | T1548 |
| Test name | |
| Test status | |
| Simulation time | 123607208 ps |
| CPU time | 7.57 seconds |
| Started | Jun 28 08:31:38 PM PDT 24 |
| Finished | Jun 28 08:31:58 PM PDT 24 |
| Peak memory | 573996 kb |
| Host | smart-c3b9918e-d21a-495d-b5ef-94289ae14a15 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2427182737 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.xbar_smoke.2427182737 |
| Directory | /workspace/6.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/6.xbar_smoke_large_delays.3200760237 |
| Short name | T1488 |
| Test name | |
| Test status | |
| Simulation time | 7677476967 ps |
| CPU time | 84.46 seconds |
| Started | Jun 28 08:31:38 PM PDT 24 |
| Finished | Jun 28 08:33:15 PM PDT 24 |
| Peak memory | 574236 kb |
| Host | smart-bf43129e-903e-4ec8-a9a5-9d77a3372551 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3200760237 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.xbar_smoke_large_delays.3200760237 |
| Directory | /workspace/6.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/6.xbar_smoke_slow_rsp.3513847694 |
| Short name | T2630 |
| Test name | |
| Test status | |
| Simulation time | 4194412781 ps |
| CPU time | 71.82 seconds |
| Started | Jun 28 08:31:35 PM PDT 24 |
| Finished | Jun 28 08:33:00 PM PDT 24 |
| Peak memory | 566004 kb |
| Host | smart-bdac1d42-5cbe-4c5a-9b61-ed7ab692b848 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3513847694 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.xbar_smoke_slow_rsp.3513847694 |
| Directory | /workspace/6.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/6.xbar_smoke_zero_delays.3862152909 |
| Short name | T2072 |
| Test name | |
| Test status | |
| Simulation time | 39310462 ps |
| CPU time | 6.64 seconds |
| Started | Jun 28 08:31:37 PM PDT 24 |
| Finished | Jun 28 08:31:56 PM PDT 24 |
| Peak memory | 574168 kb |
| Host | smart-acda968b-0ae6-424b-937a-ba4dae1fec13 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3862152909 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.xbar_smoke_zero_delays .3862152909 |
| Directory | /workspace/6.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/6.xbar_stress_all.2583558604 |
| Short name | T444 |
| Test name | |
| Test status | |
| Simulation time | 7753952467 ps |
| CPU time | 279.2 seconds |
| Started | Jun 28 08:31:54 PM PDT 24 |
| Finished | Jun 28 08:36:43 PM PDT 24 |
| Peak memory | 575424 kb |
| Host | smart-bab0745e-16f4-479a-872b-8eddc132c3f8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2583558604 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.xbar_stress_all.2583558604 |
| Directory | /workspace/6.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/6.xbar_stress_all_with_error.3684547286 |
| Short name | T2819 |
| Test name | |
| Test status | |
| Simulation time | 3406527050 ps |
| CPU time | 290.04 seconds |
| Started | Jun 28 08:31:57 PM PDT 24 |
| Finished | Jun 28 08:36:58 PM PDT 24 |
| Peak memory | 574760 kb |
| Host | smart-70194ba3-b3cc-43d3-8882-eda2c6bd3d86 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3684547286 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.xbar_stress_all_with_error.3684547286 |
| Directory | /workspace/6.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/6.xbar_stress_all_with_rand_reset.3123372860 |
| Short name | T829 |
| Test name | |
| Test status | |
| Simulation time | 765464422 ps |
| CPU time | 271.17 seconds |
| Started | Jun 28 08:31:56 PM PDT 24 |
| Finished | Jun 28 08:36:38 PM PDT 24 |
| Peak memory | 576372 kb |
| Host | smart-1d0153e1-d673-4ddf-bcc5-98473e7fee10 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3123372860 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.xbar_stress_all_ with_rand_reset.3123372860 |
| Directory | /workspace/6.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/6.xbar_stress_all_with_reset_error.286351157 |
| Short name | T1418 |
| Test name | |
| Test status | |
| Simulation time | 2624697085 ps |
| CPU time | 105.73 seconds |
| Started | Jun 28 08:31:59 PM PDT 24 |
| Finished | Jun 28 08:33:55 PM PDT 24 |
| Peak memory | 574576 kb |
| Host | smart-6bb3ee27-a882-422b-a6df-0438dec7c694 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=286351157 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.xbar_stress_all_ with_reset_error.286351157 |
| Directory | /workspace/6.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/6.xbar_unmapped_addr.2413390073 |
| Short name | T2605 |
| Test name | |
| Test status | |
| Simulation time | 78287494 ps |
| CPU time | 15.36 seconds |
| Started | Jun 28 08:31:55 PM PDT 24 |
| Finished | Jun 28 08:32:20 PM PDT 24 |
| Peak memory | 575288 kb |
| Host | smart-c8eba17b-eae3-430c-ad66-894435925c17 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2413390073 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.xbar_unmapped_addr.2413390073 |
| Directory | /workspace/6.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/60.xbar_access_same_device.4035941372 |
| Short name | T1853 |
| Test name | |
| Test status | |
| Simulation time | 3312730504 ps |
| CPU time | 133.69 seconds |
| Started | Jun 28 08:45:34 PM PDT 24 |
| Finished | Jun 28 08:48:15 PM PDT 24 |
| Peak memory | 575348 kb |
| Host | smart-00f231a9-7bd7-4c85-bd0f-1a19f2f70f9e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4035941372 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 60.xbar_access_same_device .4035941372 |
| Directory | /workspace/60.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/60.xbar_access_same_device_slow_rsp.1481318107 |
| Short name | T2880 |
| Test name | |
| Test status | |
| Simulation time | 15468085216 ps |
| CPU time | 258.08 seconds |
| Started | Jun 28 08:45:34 PM PDT 24 |
| Finished | Jun 28 08:50:20 PM PDT 24 |
| Peak memory | 575308 kb |
| Host | smart-83738547-0ec7-428d-9dc9-0c1d4daba34b |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1481318107 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 60.xbar_access_same_ device_slow_rsp.1481318107 |
| Directory | /workspace/60.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/60.xbar_error_and_unmapped_addr.2567802127 |
| Short name | T2225 |
| Test name | |
| Test status | |
| Simulation time | 1402680333 ps |
| CPU time | 61.38 seconds |
| Started | Jun 28 08:45:30 PM PDT 24 |
| Finished | Jun 28 08:46:59 PM PDT 24 |
| Peak memory | 574184 kb |
| Host | smart-5971350b-3504-4698-960a-89685e8432c8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2567802127 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 60.xbar_error_and_unmapped_add r.2567802127 |
| Directory | /workspace/60.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/60.xbar_error_random.1306333996 |
| Short name | T2546 |
| Test name | |
| Test status | |
| Simulation time | 2271851633 ps |
| CPU time | 89.33 seconds |
| Started | Jun 28 08:45:08 PM PDT 24 |
| Finished | Jun 28 08:47:04 PM PDT 24 |
| Peak memory | 574488 kb |
| Host | smart-a0d17d04-ff51-4b93-8a86-872d5f0d8707 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1306333996 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 60.xbar_error_random.1306333996 |
| Directory | /workspace/60.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/60.xbar_random.2878408839 |
| Short name | T2761 |
| Test name | |
| Test status | |
| Simulation time | 2081972996 ps |
| CPU time | 70.88 seconds |
| Started | Jun 28 08:45:34 PM PDT 24 |
| Finished | Jun 28 08:47:13 PM PDT 24 |
| Peak memory | 574168 kb |
| Host | smart-39f59862-9d6c-4ae0-ad51-87de08087aca |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2878408839 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 60.xbar_random.2878408839 |
| Directory | /workspace/60.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/60.xbar_random_large_delays.1170503317 |
| Short name | T2207 |
| Test name | |
| Test status | |
| Simulation time | 59938760671 ps |
| CPU time | 615.07 seconds |
| Started | Jun 28 08:45:35 PM PDT 24 |
| Finished | Jun 28 08:56:18 PM PDT 24 |
| Peak memory | 574244 kb |
| Host | smart-f4d1311e-079c-4f38-bf43-3b3f47654fe6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1170503317 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 60.xbar_random_large_delays.1170503317 |
| Directory | /workspace/60.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/60.xbar_random_slow_rsp.1188458375 |
| Short name | T2387 |
| Test name | |
| Test status | |
| Simulation time | 26490827419 ps |
| CPU time | 449.74 seconds |
| Started | Jun 28 08:45:20 PM PDT 24 |
| Finished | Jun 28 08:53:17 PM PDT 24 |
| Peak memory | 574248 kb |
| Host | smart-ef56cea3-2a8e-46a7-89fc-c4c71c6d53c8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1188458375 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 60.xbar_random_slow_rsp.1188458375 |
| Directory | /workspace/60.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/60.xbar_random_zero_delays.3998604750 |
| Short name | T2192 |
| Test name | |
| Test status | |
| Simulation time | 161913738 ps |
| CPU time | 18.73 seconds |
| Started | Jun 28 08:45:28 PM PDT 24 |
| Finished | Jun 28 08:46:15 PM PDT 24 |
| Peak memory | 575236 kb |
| Host | smart-e5e5ecbc-698d-4b11-9495-b4df630661d0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3998604750 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 60.xbar_random_zero_del ays.3998604750 |
| Directory | /workspace/60.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/60.xbar_same_source.3897792848 |
| Short name | T2695 |
| Test name | |
| Test status | |
| Simulation time | 747502722 ps |
| CPU time | 24.07 seconds |
| Started | Jun 28 08:45:35 PM PDT 24 |
| Finished | Jun 28 08:46:26 PM PDT 24 |
| Peak memory | 575216 kb |
| Host | smart-bedb7af0-9016-4638-8390-bfdb198272fe |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3897792848 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 60.xbar_same_source.3897792848 |
| Directory | /workspace/60.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/60.xbar_smoke.1756054063 |
| Short name | T2096 |
| Test name | |
| Test status | |
| Simulation time | 127816507 ps |
| CPU time | 7.68 seconds |
| Started | Jun 28 08:45:31 PM PDT 24 |
| Finished | Jun 28 08:46:06 PM PDT 24 |
| Peak memory | 565888 kb |
| Host | smart-b18e2d72-f76e-4fca-8f23-e455c8f1efbc |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1756054063 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 60.xbar_smoke.1756054063 |
| Directory | /workspace/60.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/60.xbar_smoke_large_delays.1789276757 |
| Short name | T2627 |
| Test name | |
| Test status | |
| Simulation time | 9277455220 ps |
| CPU time | 101.11 seconds |
| Started | Jun 28 08:45:27 PM PDT 24 |
| Finished | Jun 28 08:47:37 PM PDT 24 |
| Peak memory | 565924 kb |
| Host | smart-bdb4bd36-27fb-46dd-b436-d5088c970453 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1789276757 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 60.xbar_smoke_large_delays.1789276757 |
| Directory | /workspace/60.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/60.xbar_smoke_slow_rsp.2532176444 |
| Short name | T2397 |
| Test name | |
| Test status | |
| Simulation time | 6029704096 ps |
| CPU time | 104.15 seconds |
| Started | Jun 28 08:45:35 PM PDT 24 |
| Finished | Jun 28 08:47:46 PM PDT 24 |
| Peak memory | 574148 kb |
| Host | smart-7c037dbd-8360-42f3-986c-5622c903fbc0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2532176444 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 60.xbar_smoke_slow_rsp.2532176444 |
| Directory | /workspace/60.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/60.xbar_smoke_zero_delays.2312755615 |
| Short name | T2400 |
| Test name | |
| Test status | |
| Simulation time | 44249649 ps |
| CPU time | 6.65 seconds |
| Started | Jun 28 08:45:26 PM PDT 24 |
| Finished | Jun 28 08:46:03 PM PDT 24 |
| Peak memory | 574088 kb |
| Host | smart-83862637-713a-4231-9cab-d7b1224ff515 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2312755615 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 60.xbar_smoke_zero_delay s.2312755615 |
| Directory | /workspace/60.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/60.xbar_stress_all.2399388650 |
| Short name | T2301 |
| Test name | |
| Test status | |
| Simulation time | 1498230151 ps |
| CPU time | 60.85 seconds |
| Started | Jun 28 08:45:27 PM PDT 24 |
| Finished | Jun 28 08:46:57 PM PDT 24 |
| Peak memory | 575268 kb |
| Host | smart-3e1bbae8-9d0e-4063-9c9a-37c17a6a55d9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2399388650 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 60.xbar_stress_all.2399388650 |
| Directory | /workspace/60.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/60.xbar_stress_all_with_error.47158175 |
| Short name | T539 |
| Test name | |
| Test status | |
| Simulation time | 1331564230 ps |
| CPU time | 120.91 seconds |
| Started | Jun 28 08:45:27 PM PDT 24 |
| Finished | Jun 28 08:47:57 PM PDT 24 |
| Peak memory | 574316 kb |
| Host | smart-51e8fb72-8698-4555-94fe-dd7925264c1d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47158175 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 60.xbar_stress_all_with_error.47158175 |
| Directory | /workspace/60.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/60.xbar_stress_all_with_rand_reset.1703512675 |
| Short name | T1921 |
| Test name | |
| Test status | |
| Simulation time | 18877054 ps |
| CPU time | 11.09 seconds |
| Started | Jun 28 08:45:30 PM PDT 24 |
| Finished | Jun 28 08:46:09 PM PDT 24 |
| Peak memory | 575328 kb |
| Host | smart-4b9b6912-f1c2-4083-9de8-69a0645270d1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1703512675 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 60.xbar_stress_all _with_rand_reset.1703512675 |
| Directory | /workspace/60.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/60.xbar_stress_all_with_reset_error.2580182702 |
| Short name | T809 |
| Test name | |
| Test status | |
| Simulation time | 3833802836 ps |
| CPU time | 452.78 seconds |
| Started | Jun 28 08:45:25 PM PDT 24 |
| Finished | Jun 28 08:53:26 PM PDT 24 |
| Peak memory | 575584 kb |
| Host | smart-992a5e02-eb09-4f06-a55c-331640e36ed9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2580182702 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 60.xbar_stress_al l_with_reset_error.2580182702 |
| Directory | /workspace/60.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/60.xbar_unmapped_addr.1818269153 |
| Short name | T1736 |
| Test name | |
| Test status | |
| Simulation time | 935182811 ps |
| CPU time | 46.77 seconds |
| Started | Jun 28 08:45:27 PM PDT 24 |
| Finished | Jun 28 08:46:43 PM PDT 24 |
| Peak memory | 575272 kb |
| Host | smart-bf43c769-3da5-4f77-8312-e12638a92416 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1818269153 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 60.xbar_unmapped_addr.1818269153 |
| Directory | /workspace/60.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/61.xbar_access_same_device.367315957 |
| Short name | T1897 |
| Test name | |
| Test status | |
| Simulation time | 2701746600 ps |
| CPU time | 99.92 seconds |
| Started | Jun 28 08:45:25 PM PDT 24 |
| Finished | Jun 28 08:47:33 PM PDT 24 |
| Peak memory | 575320 kb |
| Host | smart-0b6847cf-46ba-4bd2-92f3-de10373559a6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=367315957 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 61.xbar_access_same_device. 367315957 |
| Directory | /workspace/61.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/61.xbar_access_same_device_slow_rsp.3011600078 |
| Short name | T1893 |
| Test name | |
| Test status | |
| Simulation time | 48467582376 ps |
| CPU time | 892.98 seconds |
| Started | Jun 28 08:45:20 PM PDT 24 |
| Finished | Jun 28 09:00:43 PM PDT 24 |
| Peak memory | 575372 kb |
| Host | smart-c4de6f8f-b6aa-4468-bb87-288f970da5c2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3011600078 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 61.xbar_access_same_ device_slow_rsp.3011600078 |
| Directory | /workspace/61.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/61.xbar_error_and_unmapped_addr.8860142 |
| Short name | T1368 |
| Test name | |
| Test status | |
| Simulation time | 305607717 ps |
| CPU time | 33.72 seconds |
| Started | Jun 28 08:45:26 PM PDT 24 |
| Finished | Jun 28 08:46:28 PM PDT 24 |
| Peak memory | 574432 kb |
| Host | smart-dc44dba2-72b0-4404-a235-8f9c74f5b4c2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=8860142 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 61.xbar_error_and_unmapped_addr.8860142 |
| Directory | /workspace/61.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/61.xbar_error_random.4216076328 |
| Short name | T1725 |
| Test name | |
| Test status | |
| Simulation time | 451471947 ps |
| CPU time | 17.65 seconds |
| Started | Jun 28 08:45:26 PM PDT 24 |
| Finished | Jun 28 08:46:14 PM PDT 24 |
| Peak memory | 574416 kb |
| Host | smart-5f7f2ab2-134f-4776-a967-d00ab7ea5ebc |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4216076328 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 61.xbar_error_random.4216076328 |
| Directory | /workspace/61.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/61.xbar_random.2265308368 |
| Short name | T496 |
| Test name | |
| Test status | |
| Simulation time | 1252244004 ps |
| CPU time | 45.14 seconds |
| Started | Jun 28 08:45:25 PM PDT 24 |
| Finished | Jun 28 08:46:39 PM PDT 24 |
| Peak memory | 575256 kb |
| Host | smart-ee7673f5-3b9a-4d67-b100-4d5076634bc4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2265308368 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 61.xbar_random.2265308368 |
| Directory | /workspace/61.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/61.xbar_random_large_delays.2683478092 |
| Short name | T2373 |
| Test name | |
| Test status | |
| Simulation time | 3711548134 ps |
| CPU time | 41.13 seconds |
| Started | Jun 28 08:45:25 PM PDT 24 |
| Finished | Jun 28 08:46:36 PM PDT 24 |
| Peak memory | 574156 kb |
| Host | smart-22cca067-b1e1-4fb9-bd48-9228e99d70f6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2683478092 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 61.xbar_random_large_delays.2683478092 |
| Directory | /workspace/61.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/61.xbar_random_slow_rsp.4000678143 |
| Short name | T1589 |
| Test name | |
| Test status | |
| Simulation time | 49972140864 ps |
| CPU time | 835.22 seconds |
| Started | Jun 28 08:45:27 PM PDT 24 |
| Finished | Jun 28 08:59:51 PM PDT 24 |
| Peak memory | 575280 kb |
| Host | smart-9ad7d07e-0538-4fda-ad44-d015ed9a6bbf |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4000678143 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 61.xbar_random_slow_rsp.4000678143 |
| Directory | /workspace/61.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/61.xbar_random_zero_delays.3839904604 |
| Short name | T2412 |
| Test name | |
| Test status | |
| Simulation time | 287700995 ps |
| CPU time | 30.88 seconds |
| Started | Jun 28 08:45:28 PM PDT 24 |
| Finished | Jun 28 08:46:27 PM PDT 24 |
| Peak memory | 575240 kb |
| Host | smart-b233db40-615e-499b-be93-1f525c3fed42 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3839904604 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 61.xbar_random_zero_del ays.3839904604 |
| Directory | /workspace/61.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/61.xbar_same_source.3581319900 |
| Short name | T612 |
| Test name | |
| Test status | |
| Simulation time | 195585598 ps |
| CPU time | 17.95 seconds |
| Started | Jun 28 08:45:24 PM PDT 24 |
| Finished | Jun 28 08:46:11 PM PDT 24 |
| Peak memory | 574160 kb |
| Host | smart-3129f1bd-b619-4f9e-8ade-6fed11711898 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3581319900 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 61.xbar_same_source.3581319900 |
| Directory | /workspace/61.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/61.xbar_smoke.3133637997 |
| Short name | T2245 |
| Test name | |
| Test status | |
| Simulation time | 50213193 ps |
| CPU time | 6.7 seconds |
| Started | Jun 28 08:45:22 PM PDT 24 |
| Finished | Jun 28 08:45:57 PM PDT 24 |
| Peak memory | 574216 kb |
| Host | smart-c0dc0267-0a94-4ab7-b2c2-e75cc68217fe |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3133637997 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 61.xbar_smoke.3133637997 |
| Directory | /workspace/61.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/61.xbar_smoke_large_delays.2279648763 |
| Short name | T1328 |
| Test name | |
| Test status | |
| Simulation time | 9325461887 ps |
| CPU time | 97.86 seconds |
| Started | Jun 28 08:45:27 PM PDT 24 |
| Finished | Jun 28 08:47:34 PM PDT 24 |
| Peak memory | 574232 kb |
| Host | smart-c2b2e5b2-bf99-4cd0-810e-ca3745921a0c |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2279648763 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 61.xbar_smoke_large_delays.2279648763 |
| Directory | /workspace/61.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/61.xbar_smoke_slow_rsp.2385208778 |
| Short name | T1563 |
| Test name | |
| Test status | |
| Simulation time | 4682930051 ps |
| CPU time | 79.71 seconds |
| Started | Jun 28 08:45:24 PM PDT 24 |
| Finished | Jun 28 08:47:13 PM PDT 24 |
| Peak memory | 566012 kb |
| Host | smart-361f8c46-1bad-45ba-a68f-f6095f48f4ca |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2385208778 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 61.xbar_smoke_slow_rsp.2385208778 |
| Directory | /workspace/61.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/61.xbar_smoke_zero_delays.799277341 |
| Short name | T2403 |
| Test name | |
| Test status | |
| Simulation time | 46645140 ps |
| CPU time | 6.72 seconds |
| Started | Jun 28 08:45:26 PM PDT 24 |
| Finished | Jun 28 08:46:03 PM PDT 24 |
| Peak memory | 574192 kb |
| Host | smart-25acd937-2d72-4510-895e-db8247c68883 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=799277341 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 61.xbar_smoke_zero_delays .799277341 |
| Directory | /workspace/61.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/61.xbar_stress_all.783418658 |
| Short name | T583 |
| Test name | |
| Test status | |
| Simulation time | 9369156040 ps |
| CPU time | 326.28 seconds |
| Started | Jun 28 08:45:26 PM PDT 24 |
| Finished | Jun 28 08:51:22 PM PDT 24 |
| Peak memory | 575444 kb |
| Host | smart-6a3fe73f-15b9-4627-932f-a5afce4521df |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=783418658 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 61.xbar_stress_all.783418658 |
| Directory | /workspace/61.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/61.xbar_stress_all_with_error.2116873979 |
| Short name | T1766 |
| Test name | |
| Test status | |
| Simulation time | 3287918556 ps |
| CPU time | 264.18 seconds |
| Started | Jun 28 08:45:36 PM PDT 24 |
| Finished | Jun 28 08:50:28 PM PDT 24 |
| Peak memory | 574660 kb |
| Host | smart-c5d22b8b-75e0-47e4-89bb-fb7369e6f937 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2116873979 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 61.xbar_stress_all_with_error.2116873979 |
| Directory | /workspace/61.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/61.xbar_stress_all_with_rand_reset.1060468298 |
| Short name | T1812 |
| Test name | |
| Test status | |
| Simulation time | 35110157 ps |
| CPU time | 31.72 seconds |
| Started | Jun 28 08:45:44 PM PDT 24 |
| Finished | Jun 28 08:46:41 PM PDT 24 |
| Peak memory | 574304 kb |
| Host | smart-4408e00f-5927-4363-8900-6691f61f1371 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1060468298 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 61.xbar_stress_all _with_rand_reset.1060468298 |
| Directory | /workspace/61.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/61.xbar_stress_all_with_reset_error.3375014916 |
| Short name | T1956 |
| Test name | |
| Test status | |
| Simulation time | 300433015 ps |
| CPU time | 60.59 seconds |
| Started | Jun 28 08:45:43 PM PDT 24 |
| Finished | Jun 28 08:47:08 PM PDT 24 |
| Peak memory | 574284 kb |
| Host | smart-7dc939e6-6c51-4ff1-ac56-b190a9edee17 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3375014916 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 61.xbar_stress_al l_with_reset_error.3375014916 |
| Directory | /workspace/61.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/61.xbar_unmapped_addr.3545408765 |
| Short name | T1607 |
| Test name | |
| Test status | |
| Simulation time | 238144532 ps |
| CPU time | 13.78 seconds |
| Started | Jun 28 08:45:24 PM PDT 24 |
| Finished | Jun 28 08:46:07 PM PDT 24 |
| Peak memory | 574192 kb |
| Host | smart-4c071a10-a44b-4e34-a4ab-bf7bb5d48191 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3545408765 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 61.xbar_unmapped_addr.3545408765 |
| Directory | /workspace/61.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/62.xbar_access_same_device.4205579197 |
| Short name | T2236 |
| Test name | |
| Test status | |
| Simulation time | 620082309 ps |
| CPU time | 32.25 seconds |
| Started | Jun 28 08:45:47 PM PDT 24 |
| Finished | Jun 28 08:46:44 PM PDT 24 |
| Peak memory | 575224 kb |
| Host | smart-07dc30b0-ecea-44f1-a088-4b92958a924f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4205579197 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 62.xbar_access_same_device .4205579197 |
| Directory | /workspace/62.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/62.xbar_access_same_device_slow_rsp.4129358649 |
| Short name | T2042 |
| Test name | |
| Test status | |
| Simulation time | 107001105882 ps |
| CPU time | 1740.18 seconds |
| Started | Jun 28 08:45:42 PM PDT 24 |
| Finished | Jun 28 09:15:08 PM PDT 24 |
| Peak memory | 575344 kb |
| Host | smart-1d06266d-d4dd-4bb3-bf3e-542de1edc40c |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4129358649 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 62.xbar_access_same_ device_slow_rsp.4129358649 |
| Directory | /workspace/62.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/62.xbar_error_and_unmapped_addr.3083357087 |
| Short name | T2045 |
| Test name | |
| Test status | |
| Simulation time | 1269570699 ps |
| CPU time | 49.61 seconds |
| Started | Jun 28 08:45:58 PM PDT 24 |
| Finished | Jun 28 08:47:05 PM PDT 24 |
| Peak memory | 574448 kb |
| Host | smart-41be2cdb-3af7-45f6-8c74-ea8d590c4bdf |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3083357087 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 62.xbar_error_and_unmapped_add r.3083357087 |
| Directory | /workspace/62.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/62.xbar_error_random.2092055398 |
| Short name | T2669 |
| Test name | |
| Test status | |
| Simulation time | 256861879 ps |
| CPU time | 12.37 seconds |
| Started | Jun 28 08:45:49 PM PDT 24 |
| Finished | Jun 28 08:46:25 PM PDT 24 |
| Peak memory | 574432 kb |
| Host | smart-3c043c08-0998-4937-8061-3a9281eb292d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2092055398 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 62.xbar_error_random.2092055398 |
| Directory | /workspace/62.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/62.xbar_random.3584169986 |
| Short name | T2070 |
| Test name | |
| Test status | |
| Simulation time | 39990519 ps |
| CPU time | 6.77 seconds |
| Started | Jun 28 08:45:47 PM PDT 24 |
| Finished | Jun 28 08:46:19 PM PDT 24 |
| Peak memory | 565944 kb |
| Host | smart-5656f840-a9e7-49e7-9e59-d11ec8ffe3bb |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3584169986 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 62.xbar_random.3584169986 |
| Directory | /workspace/62.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/62.xbar_random_large_delays.1276640857 |
| Short name | T572 |
| Test name | |
| Test status | |
| Simulation time | 41831166845 ps |
| CPU time | 413.55 seconds |
| Started | Jun 28 08:45:42 PM PDT 24 |
| Finished | Jun 28 08:53:01 PM PDT 24 |
| Peak memory | 575300 kb |
| Host | smart-72b06a5b-475d-49e0-b81b-ff49be7311ee |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1276640857 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 62.xbar_random_large_delays.1276640857 |
| Directory | /workspace/62.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/62.xbar_random_slow_rsp.4132394677 |
| Short name | T1856 |
| Test name | |
| Test status | |
| Simulation time | 16522805633 ps |
| CPU time | 286.28 seconds |
| Started | Jun 28 08:45:57 PM PDT 24 |
| Finished | Jun 28 08:51:02 PM PDT 24 |
| Peak memory | 575328 kb |
| Host | smart-f5bd9848-95eb-466a-b6d6-bdc54f00a6c2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4132394677 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 62.xbar_random_slow_rsp.4132394677 |
| Directory | /workspace/62.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/62.xbar_random_zero_delays.4034898451 |
| Short name | T1690 |
| Test name | |
| Test status | |
| Simulation time | 356237621 ps |
| CPU time | 37.15 seconds |
| Started | Jun 28 08:45:45 PM PDT 24 |
| Finished | Jun 28 08:46:47 PM PDT 24 |
| Peak memory | 574172 kb |
| Host | smart-cd9b4d48-d5fd-43f6-a3bb-216b57c2f042 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4034898451 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 62.xbar_random_zero_del ays.4034898451 |
| Directory | /workspace/62.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/62.xbar_same_source.4207166182 |
| Short name | T618 |
| Test name | |
| Test status | |
| Simulation time | 1158609605 ps |
| CPU time | 31.98 seconds |
| Started | Jun 28 08:45:42 PM PDT 24 |
| Finished | Jun 28 08:46:39 PM PDT 24 |
| Peak memory | 575140 kb |
| Host | smart-793e87d2-6f25-47ea-b33c-98fd186197b8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4207166182 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 62.xbar_same_source.4207166182 |
| Directory | /workspace/62.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/62.xbar_smoke.253390841 |
| Short name | T1800 |
| Test name | |
| Test status | |
| Simulation time | 215377981 ps |
| CPU time | 9.89 seconds |
| Started | Jun 28 08:45:40 PM PDT 24 |
| Finished | Jun 28 08:46:16 PM PDT 24 |
| Peak memory | 565896 kb |
| Host | smart-08c17c23-496c-4c75-a3f5-268ac9bb67d0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=253390841 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 62.xbar_smoke.253390841 |
| Directory | /workspace/62.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/62.xbar_smoke_large_delays.3133301640 |
| Short name | T1982 |
| Test name | |
| Test status | |
| Simulation time | 4678222025 ps |
| CPU time | 51.26 seconds |
| Started | Jun 28 08:45:39 PM PDT 24 |
| Finished | Jun 28 08:46:57 PM PDT 24 |
| Peak memory | 566024 kb |
| Host | smart-ca1ec8b7-e323-48a0-bf1f-dc0e44838463 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3133301640 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 62.xbar_smoke_large_delays.3133301640 |
| Directory | /workspace/62.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/62.xbar_smoke_slow_rsp.1587131888 |
| Short name | T2750 |
| Test name | |
| Test status | |
| Simulation time | 5977628119 ps |
| CPU time | 102.9 seconds |
| Started | Jun 28 08:45:39 PM PDT 24 |
| Finished | Jun 28 08:47:48 PM PDT 24 |
| Peak memory | 566012 kb |
| Host | smart-e3882250-70f2-4649-a057-9f8f461bad11 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1587131888 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 62.xbar_smoke_slow_rsp.1587131888 |
| Directory | /workspace/62.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/62.xbar_smoke_zero_delays.4249956723 |
| Short name | T2568 |
| Test name | |
| Test status | |
| Simulation time | 42446427 ps |
| CPU time | 6.63 seconds |
| Started | Jun 28 08:45:38 PM PDT 24 |
| Finished | Jun 28 08:46:12 PM PDT 24 |
| Peak memory | 574176 kb |
| Host | smart-ae83f151-b726-48ee-9fb3-5b18ca9d0a28 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4249956723 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 62.xbar_smoke_zero_delay s.4249956723 |
| Directory | /workspace/62.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/62.xbar_stress_all.2551201547 |
| Short name | T2367 |
| Test name | |
| Test status | |
| Simulation time | 11467411299 ps |
| CPU time | 534.55 seconds |
| Started | Jun 28 08:45:41 PM PDT 24 |
| Finished | Jun 28 08:55:01 PM PDT 24 |
| Peak memory | 575412 kb |
| Host | smart-23d66462-f189-4231-b1a0-d625387520fd |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2551201547 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 62.xbar_stress_all.2551201547 |
| Directory | /workspace/62.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/62.xbar_stress_all_with_error.1687952596 |
| Short name | T1647 |
| Test name | |
| Test status | |
| Simulation time | 2120894117 ps |
| CPU time | 82.31 seconds |
| Started | Jun 28 08:45:42 PM PDT 24 |
| Finished | Jun 28 08:47:30 PM PDT 24 |
| Peak memory | 574440 kb |
| Host | smart-5de9794b-12b8-4f5a-bdd6-bb95d9a2e630 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1687952596 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 62.xbar_stress_all_with_error.1687952596 |
| Directory | /workspace/62.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/62.xbar_stress_all_with_rand_reset.3070475090 |
| Short name | T2487 |
| Test name | |
| Test status | |
| Simulation time | 3096298653 ps |
| CPU time | 385.38 seconds |
| Started | Jun 28 08:45:42 PM PDT 24 |
| Finished | Jun 28 08:52:33 PM PDT 24 |
| Peak memory | 575452 kb |
| Host | smart-e068560a-5619-4b0c-858c-f504ca920aad |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3070475090 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 62.xbar_stress_all _with_rand_reset.3070475090 |
| Directory | /workspace/62.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/62.xbar_stress_all_with_reset_error.1138125011 |
| Short name | T2724 |
| Test name | |
| Test status | |
| Simulation time | 575209560 ps |
| CPU time | 151.87 seconds |
| Started | Jun 28 08:45:42 PM PDT 24 |
| Finished | Jun 28 08:48:39 PM PDT 24 |
| Peak memory | 574364 kb |
| Host | smart-66ecff79-f00f-422b-b7e3-c47e20538af5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1138125011 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 62.xbar_stress_al l_with_reset_error.1138125011 |
| Directory | /workspace/62.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/62.xbar_unmapped_addr.1899255058 |
| Short name | T1527 |
| Test name | |
| Test status | |
| Simulation time | 285861932 ps |
| CPU time | 35 seconds |
| Started | Jun 28 08:45:42 PM PDT 24 |
| Finished | Jun 28 08:46:42 PM PDT 24 |
| Peak memory | 575308 kb |
| Host | smart-9d590107-a551-45a6-85c1-329491a07941 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1899255058 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 62.xbar_unmapped_addr.1899255058 |
| Directory | /workspace/62.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/63.xbar_access_same_device.2283278043 |
| Short name | T2470 |
| Test name | |
| Test status | |
| Simulation time | 3279745541 ps |
| CPU time | 121.56 seconds |
| Started | Jun 28 08:45:48 PM PDT 24 |
| Finished | Jun 28 08:48:14 PM PDT 24 |
| Peak memory | 575292 kb |
| Host | smart-01a10fd9-8347-4cfa-b211-51ad5d60db68 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2283278043 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 63.xbar_access_same_device .2283278043 |
| Directory | /workspace/63.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/63.xbar_error_and_unmapped_addr.318776219 |
| Short name | T1335 |
| Test name | |
| Test status | |
| Simulation time | 708307126 ps |
| CPU time | 32.32 seconds |
| Started | Jun 28 08:45:50 PM PDT 24 |
| Finished | Jun 28 08:46:45 PM PDT 24 |
| Peak memory | 574204 kb |
| Host | smart-99e0e1bd-1516-4bc0-892a-4fe540f85727 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=318776219 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 63.xbar_error_and_unmapped_addr .318776219 |
| Directory | /workspace/63.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/63.xbar_error_random.197723401 |
| Short name | T650 |
| Test name | |
| Test status | |
| Simulation time | 1631846596 ps |
| CPU time | 61.62 seconds |
| Started | Jun 28 08:45:49 PM PDT 24 |
| Finished | Jun 28 08:47:13 PM PDT 24 |
| Peak memory | 574204 kb |
| Host | smart-3d2d6e1f-3fb0-43d3-aa85-14e97a013405 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=197723401 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 63.xbar_error_random.197723401 |
| Directory | /workspace/63.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/63.xbar_random.1944008851 |
| Short name | T1985 |
| Test name | |
| Test status | |
| Simulation time | 522310836 ps |
| CPU time | 51.22 seconds |
| Started | Jun 28 08:45:49 PM PDT 24 |
| Finished | Jun 28 08:47:03 PM PDT 24 |
| Peak memory | 575300 kb |
| Host | smart-7869f7a3-a72e-4d74-a30c-53039d328b5e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1944008851 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 63.xbar_random.1944008851 |
| Directory | /workspace/63.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/63.xbar_random_large_delays.1062981796 |
| Short name | T607 |
| Test name | |
| Test status | |
| Simulation time | 105215407108 ps |
| CPU time | 1179.72 seconds |
| Started | Jun 28 08:45:39 PM PDT 24 |
| Finished | Jun 28 09:05:45 PM PDT 24 |
| Peak memory | 575308 kb |
| Host | smart-c20529a0-5c9e-4050-adc8-fc29d181ca60 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1062981796 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 63.xbar_random_large_delays.1062981796 |
| Directory | /workspace/63.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/63.xbar_random_slow_rsp.3197704590 |
| Short name | T1827 |
| Test name | |
| Test status | |
| Simulation time | 44953885874 ps |
| CPU time | 818.82 seconds |
| Started | Jun 28 08:45:41 PM PDT 24 |
| Finished | Jun 28 08:59:45 PM PDT 24 |
| Peak memory | 575384 kb |
| Host | smart-8a7a735c-56a1-4306-91f3-e20fc60d2acb |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3197704590 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 63.xbar_random_slow_rsp.3197704590 |
| Directory | /workspace/63.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/63.xbar_random_zero_delays.1387243248 |
| Short name | T2184 |
| Test name | |
| Test status | |
| Simulation time | 302617005 ps |
| CPU time | 28.03 seconds |
| Started | Jun 28 08:45:43 PM PDT 24 |
| Finished | Jun 28 08:46:36 PM PDT 24 |
| Peak memory | 575236 kb |
| Host | smart-26a0ecf1-6c4e-4858-8946-b811cdab2141 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1387243248 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 63.xbar_random_zero_del ays.1387243248 |
| Directory | /workspace/63.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/63.xbar_same_source.3595526489 |
| Short name | T2576 |
| Test name | |
| Test status | |
| Simulation time | 403075065 ps |
| CPU time | 33.57 seconds |
| Started | Jun 28 08:45:38 PM PDT 24 |
| Finished | Jun 28 08:46:39 PM PDT 24 |
| Peak memory | 574184 kb |
| Host | smart-7e9009cc-e2ae-409f-b064-cb0b15f0d413 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3595526489 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 63.xbar_same_source.3595526489 |
| Directory | /workspace/63.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/63.xbar_smoke.2114090350 |
| Short name | T2213 |
| Test name | |
| Test status | |
| Simulation time | 51402127 ps |
| CPU time | 7.09 seconds |
| Started | Jun 28 08:45:45 PM PDT 24 |
| Finished | Jun 28 08:46:17 PM PDT 24 |
| Peak memory | 574196 kb |
| Host | smart-01f30cac-7047-4721-9d26-89c913b92dfb |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2114090350 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 63.xbar_smoke.2114090350 |
| Directory | /workspace/63.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/63.xbar_smoke_large_delays.2127641683 |
| Short name | T1908 |
| Test name | |
| Test status | |
| Simulation time | 8840906075 ps |
| CPU time | 95.38 seconds |
| Started | Jun 28 08:45:50 PM PDT 24 |
| Finished | Jun 28 08:47:48 PM PDT 24 |
| Peak memory | 574272 kb |
| Host | smart-c0fbb808-4c58-48bc-9331-132605196c4f |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2127641683 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 63.xbar_smoke_large_delays.2127641683 |
| Directory | /workspace/63.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/63.xbar_smoke_slow_rsp.281084914 |
| Short name | T442 |
| Test name | |
| Test status | |
| Simulation time | 5031402885 ps |
| CPU time | 86.14 seconds |
| Started | Jun 28 08:45:54 PM PDT 24 |
| Finished | Jun 28 08:47:41 PM PDT 24 |
| Peak memory | 574252 kb |
| Host | smart-ec027dcf-4d2c-4db6-8692-9327fa77acaa |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=281084914 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 63.xbar_smoke_slow_rsp.281084914 |
| Directory | /workspace/63.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/63.xbar_smoke_zero_delays.3305111066 |
| Short name | T2610 |
| Test name | |
| Test status | |
| Simulation time | 44947258 ps |
| CPU time | 6.38 seconds |
| Started | Jun 28 08:45:58 PM PDT 24 |
| Finished | Jun 28 08:46:22 PM PDT 24 |
| Peak memory | 574188 kb |
| Host | smart-f00b1899-bdfd-4b14-8e50-e49383f7cae4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3305111066 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 63.xbar_smoke_zero_delay s.3305111066 |
| Directory | /workspace/63.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/63.xbar_stress_all.1959665814 |
| Short name | T458 |
| Test name | |
| Test status | |
| Simulation time | 5354430021 ps |
| CPU time | 205.99 seconds |
| Started | Jun 28 08:45:42 PM PDT 24 |
| Finished | Jun 28 08:49:33 PM PDT 24 |
| Peak memory | 575360 kb |
| Host | smart-a5583c9e-bc23-422e-9f8f-8393a8c8eae8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1959665814 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 63.xbar_stress_all.1959665814 |
| Directory | /workspace/63.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/63.xbar_stress_all_with_error.2986538190 |
| Short name | T2843 |
| Test name | |
| Test status | |
| Simulation time | 8432200894 ps |
| CPU time | 282.34 seconds |
| Started | Jun 28 08:45:38 PM PDT 24 |
| Finished | Jun 28 08:50:47 PM PDT 24 |
| Peak memory | 574380 kb |
| Host | smart-a65a2a2f-1a18-4cab-b322-9d451366d955 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2986538190 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 63.xbar_stress_all_with_error.2986538190 |
| Directory | /workspace/63.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/63.xbar_stress_all_with_rand_reset.1241190415 |
| Short name | T1564 |
| Test name | |
| Test status | |
| Simulation time | 102170707 ps |
| CPU time | 51.71 seconds |
| Started | Jun 28 08:45:43 PM PDT 24 |
| Finished | Jun 28 08:46:59 PM PDT 24 |
| Peak memory | 575372 kb |
| Host | smart-199a76d8-f013-4f23-bb28-fdf3bfa64e4f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1241190415 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 63.xbar_stress_all _with_rand_reset.1241190415 |
| Directory | /workspace/63.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/63.xbar_stress_all_with_reset_error.385726180 |
| Short name | T1489 |
| Test name | |
| Test status | |
| Simulation time | 3370035454 ps |
| CPU time | 427.99 seconds |
| Started | Jun 28 08:45:45 PM PDT 24 |
| Finished | Jun 28 08:53:18 PM PDT 24 |
| Peak memory | 576456 kb |
| Host | smart-12390681-c1ae-4f28-99f7-d835f0abf7bd |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=385726180 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 63.xbar_stress_all _with_reset_error.385726180 |
| Directory | /workspace/63.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/63.xbar_unmapped_addr.1471082286 |
| Short name | T2186 |
| Test name | |
| Test status | |
| Simulation time | 314960661 ps |
| CPU time | 17.03 seconds |
| Started | Jun 28 08:45:46 PM PDT 24 |
| Finished | Jun 28 08:46:28 PM PDT 24 |
| Peak memory | 575288 kb |
| Host | smart-44be799f-c143-4109-b1d8-78432043da24 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1471082286 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 63.xbar_unmapped_addr.1471082286 |
| Directory | /workspace/63.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/64.xbar_access_same_device.1007135364 |
| Short name | T1813 |
| Test name | |
| Test status | |
| Simulation time | 644419108 ps |
| CPU time | 63.14 seconds |
| Started | Jun 28 08:45:48 PM PDT 24 |
| Finished | Jun 28 08:47:15 PM PDT 24 |
| Peak memory | 575236 kb |
| Host | smart-6f0fe0e5-dca4-4e1a-a170-1f18e278664d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1007135364 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 64.xbar_access_same_device .1007135364 |
| Directory | /workspace/64.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/64.xbar_error_and_unmapped_addr.627324638 |
| Short name | T1683 |
| Test name | |
| Test status | |
| Simulation time | 163267484 ps |
| CPU time | 21.04 seconds |
| Started | Jun 28 08:45:55 PM PDT 24 |
| Finished | Jun 28 08:46:36 PM PDT 24 |
| Peak memory | 574440 kb |
| Host | smart-93a435f0-c541-44ec-bef4-2c66a07f0940 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=627324638 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 64.xbar_error_and_unmapped_addr .627324638 |
| Directory | /workspace/64.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/64.xbar_error_random.594889040 |
| Short name | T1501 |
| Test name | |
| Test status | |
| Simulation time | 1168500048 ps |
| CPU time | 38.27 seconds |
| Started | Jun 28 08:45:44 PM PDT 24 |
| Finished | Jun 28 08:46:48 PM PDT 24 |
| Peak memory | 574208 kb |
| Host | smart-494f43cf-81db-45b1-983d-c774d9dac67e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=594889040 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 64.xbar_error_random.594889040 |
| Directory | /workspace/64.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/64.xbar_random.3824593344 |
| Short name | T528 |
| Test name | |
| Test status | |
| Simulation time | 65824682 ps |
| CPU time | 8.1 seconds |
| Started | Jun 28 08:45:54 PM PDT 24 |
| Finished | Jun 28 08:46:22 PM PDT 24 |
| Peak memory | 574236 kb |
| Host | smart-b89730af-96b9-41bd-b394-829453d8bd8b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3824593344 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 64.xbar_random.3824593344 |
| Directory | /workspace/64.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/64.xbar_random_large_delays.2084516709 |
| Short name | T2575 |
| Test name | |
| Test status | |
| Simulation time | 105476275562 ps |
| CPU time | 1116.87 seconds |
| Started | Jun 28 08:45:39 PM PDT 24 |
| Finished | Jun 28 09:04:42 PM PDT 24 |
| Peak memory | 575360 kb |
| Host | smart-2076088a-6c2d-4de6-a2b9-adb40ce8bf8d |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2084516709 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 64.xbar_random_large_delays.2084516709 |
| Directory | /workspace/64.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/64.xbar_random_slow_rsp.1647179296 |
| Short name | T2107 |
| Test name | |
| Test status | |
| Simulation time | 49930538010 ps |
| CPU time | 837.82 seconds |
| Started | Jun 28 08:45:57 PM PDT 24 |
| Finished | Jun 28 09:00:13 PM PDT 24 |
| Peak memory | 575316 kb |
| Host | smart-1e439b3d-7ee2-41de-beeb-ef3ada261e78 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1647179296 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 64.xbar_random_slow_rsp.1647179296 |
| Directory | /workspace/64.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/64.xbar_random_zero_delays.913407187 |
| Short name | T2380 |
| Test name | |
| Test status | |
| Simulation time | 329799843 ps |
| CPU time | 31.26 seconds |
| Started | Jun 28 08:45:58 PM PDT 24 |
| Finished | Jun 28 08:46:47 PM PDT 24 |
| Peak memory | 574176 kb |
| Host | smart-ef46d7d4-7028-4251-950c-2b1882a8c53f |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=913407187 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 64.xbar_random_zero_dela ys.913407187 |
| Directory | /workspace/64.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/64.xbar_same_source.1313110003 |
| Short name | T2410 |
| Test name | |
| Test status | |
| Simulation time | 495244347 ps |
| CPU time | 16.59 seconds |
| Started | Jun 28 08:45:50 PM PDT 24 |
| Finished | Jun 28 08:46:29 PM PDT 24 |
| Peak memory | 575224 kb |
| Host | smart-1667897c-cf6b-42fc-b29b-4081807ee068 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1313110003 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 64.xbar_same_source.1313110003 |
| Directory | /workspace/64.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/64.xbar_smoke.402975572 |
| Short name | T2314 |
| Test name | |
| Test status | |
| Simulation time | 228869648 ps |
| CPU time | 9.53 seconds |
| Started | Jun 28 08:45:44 PM PDT 24 |
| Finished | Jun 28 08:46:19 PM PDT 24 |
| Peak memory | 574180 kb |
| Host | smart-a2a6ad3f-a967-4d48-9aa5-753be1457b49 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=402975572 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 64.xbar_smoke.402975572 |
| Directory | /workspace/64.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/64.xbar_smoke_large_delays.2073061992 |
| Short name | T2526 |
| Test name | |
| Test status | |
| Simulation time | 7930517233 ps |
| CPU time | 83.57 seconds |
| Started | Jun 28 08:45:48 PM PDT 24 |
| Finished | Jun 28 08:47:36 PM PDT 24 |
| Peak memory | 574236 kb |
| Host | smart-fd3c644c-dd6f-44fc-a2de-f521e4a91b1c |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2073061992 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 64.xbar_smoke_large_delays.2073061992 |
| Directory | /workspace/64.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/64.xbar_smoke_slow_rsp.3049909882 |
| Short name | T1536 |
| Test name | |
| Test status | |
| Simulation time | 5331410875 ps |
| CPU time | 92.66 seconds |
| Started | Jun 28 08:45:58 PM PDT 24 |
| Finished | Jun 28 08:47:49 PM PDT 24 |
| Peak memory | 574248 kb |
| Host | smart-d6ca3e5f-592e-4501-8bdb-a4cc9cc185d4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3049909882 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 64.xbar_smoke_slow_rsp.3049909882 |
| Directory | /workspace/64.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/64.xbar_smoke_zero_delays.2879236570 |
| Short name | T1854 |
| Test name | |
| Test status | |
| Simulation time | 51818638 ps |
| CPU time | 7.06 seconds |
| Started | Jun 28 08:45:39 PM PDT 24 |
| Finished | Jun 28 08:46:11 PM PDT 24 |
| Peak memory | 574132 kb |
| Host | smart-851d0ac0-f200-4e70-8a09-e7078c29385a |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2879236570 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 64.xbar_smoke_zero_delay s.2879236570 |
| Directory | /workspace/64.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/64.xbar_stress_all.3110454319 |
| Short name | T2499 |
| Test name | |
| Test status | |
| Simulation time | 10326345417 ps |
| CPU time | 332.4 seconds |
| Started | Jun 28 08:45:48 PM PDT 24 |
| Finished | Jun 28 08:51:45 PM PDT 24 |
| Peak memory | 575444 kb |
| Host | smart-72b59b85-895e-455f-8a69-868cc7d5e428 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3110454319 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 64.xbar_stress_all.3110454319 |
| Directory | /workspace/64.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/64.xbar_stress_all_with_error.2556393641 |
| Short name | T2130 |
| Test name | |
| Test status | |
| Simulation time | 2177307989 ps |
| CPU time | 74.68 seconds |
| Started | Jun 28 08:45:55 PM PDT 24 |
| Finished | Jun 28 08:47:29 PM PDT 24 |
| Peak memory | 573948 kb |
| Host | smart-8b731891-1ded-49af-8036-c1bc47d83c99 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2556393641 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 64.xbar_stress_all_with_error.2556393641 |
| Directory | /workspace/64.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/64.xbar_stress_all_with_rand_reset.1128303866 |
| Short name | T2692 |
| Test name | |
| Test status | |
| Simulation time | 95010605 ps |
| CPU time | 44.19 seconds |
| Started | Jun 28 08:45:55 PM PDT 24 |
| Finished | Jun 28 08:46:59 PM PDT 24 |
| Peak memory | 576380 kb |
| Host | smart-63911e25-fda5-467f-8795-cdafdd7d80b4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1128303866 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 64.xbar_stress_all _with_rand_reset.1128303866 |
| Directory | /workspace/64.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/64.xbar_stress_all_with_reset_error.230028392 |
| Short name | T854 |
| Test name | |
| Test status | |
| Simulation time | 7317319773 ps |
| CPU time | 395.6 seconds |
| Started | Jun 28 08:46:08 PM PDT 24 |
| Finished | Jun 28 08:52:55 PM PDT 24 |
| Peak memory | 574344 kb |
| Host | smart-41f0ef7d-e41b-418c-9693-2e08ffb9f357 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=230028392 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 64.xbar_stress_all _with_reset_error.230028392 |
| Directory | /workspace/64.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/64.xbar_unmapped_addr.866269454 |
| Short name | T2181 |
| Test name | |
| Test status | |
| Simulation time | 287629209 ps |
| CPU time | 34.42 seconds |
| Started | Jun 28 08:45:49 PM PDT 24 |
| Finished | Jun 28 08:46:46 PM PDT 24 |
| Peak memory | 574232 kb |
| Host | smart-beabc6fb-7c0e-419d-aab7-7ca0b1d1000d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=866269454 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 64.xbar_unmapped_addr.866269454 |
| Directory | /workspace/64.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/65.xbar_access_same_device.1128417302 |
| Short name | T2672 |
| Test name | |
| Test status | |
| Simulation time | 536361543 ps |
| CPU time | 23.91 seconds |
| Started | Jun 28 08:46:01 PM PDT 24 |
| Finished | Jun 28 08:46:41 PM PDT 24 |
| Peak memory | 574164 kb |
| Host | smart-d600d527-3fb5-495f-b1d8-15558ed1766a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1128417302 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 65.xbar_access_same_device .1128417302 |
| Directory | /workspace/65.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/65.xbar_access_same_device_slow_rsp.172224347 |
| Short name | T2189 |
| Test name | |
| Test status | |
| Simulation time | 142981001485 ps |
| CPU time | 2352.27 seconds |
| Started | Jun 28 08:46:09 PM PDT 24 |
| Finished | Jun 28 09:25:32 PM PDT 24 |
| Peak memory | 575336 kb |
| Host | smart-c9c8afe9-10f4-4826-8e62-a6e5235a9fc5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=172224347 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 65.xbar_access_same_d evice_slow_rsp.172224347 |
| Directory | /workspace/65.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/65.xbar_error_and_unmapped_addr.3649249555 |
| Short name | T1428 |
| Test name | |
| Test status | |
| Simulation time | 217306806 ps |
| CPU time | 25.24 seconds |
| Started | Jun 28 08:46:00 PM PDT 24 |
| Finished | Jun 28 08:46:42 PM PDT 24 |
| Peak memory | 574432 kb |
| Host | smart-ff767444-92b0-45ca-901f-fe59c2930b9f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3649249555 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 65.xbar_error_and_unmapped_add r.3649249555 |
| Directory | /workspace/65.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/65.xbar_error_random.521164595 |
| Short name | T2770 |
| Test name | |
| Test status | |
| Simulation time | 1511864534 ps |
| CPU time | 51.15 seconds |
| Started | Jun 28 08:46:01 PM PDT 24 |
| Finished | Jun 28 08:47:08 PM PDT 24 |
| Peak memory | 574420 kb |
| Host | smart-37c49e8a-da31-46bf-a0fd-6bb999873120 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=521164595 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 65.xbar_error_random.521164595 |
| Directory | /workspace/65.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/65.xbar_random.3891561385 |
| Short name | T2496 |
| Test name | |
| Test status | |
| Simulation time | 2173811557 ps |
| CPU time | 71.55 seconds |
| Started | Jun 28 08:46:07 PM PDT 24 |
| Finished | Jun 28 08:47:31 PM PDT 24 |
| Peak memory | 575260 kb |
| Host | smart-32901b82-3ddf-4338-a387-551551c1dd34 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3891561385 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 65.xbar_random.3891561385 |
| Directory | /workspace/65.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/65.xbar_random_large_delays.3573378472 |
| Short name | T2532 |
| Test name | |
| Test status | |
| Simulation time | 42527542071 ps |
| CPU time | 488.3 seconds |
| Started | Jun 28 08:46:00 PM PDT 24 |
| Finished | Jun 28 08:54:25 PM PDT 24 |
| Peak memory | 575340 kb |
| Host | smart-7b8276e6-8ade-41fe-9c29-528d249c32f8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3573378472 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 65.xbar_random_large_delays.3573378472 |
| Directory | /workspace/65.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/65.xbar_random_slow_rsp.371094392 |
| Short name | T1427 |
| Test name | |
| Test status | |
| Simulation time | 4391249622 ps |
| CPU time | 74.88 seconds |
| Started | Jun 28 08:46:00 PM PDT 24 |
| Finished | Jun 28 08:47:32 PM PDT 24 |
| Peak memory | 574132 kb |
| Host | smart-4e08faab-6e94-4dba-92ca-9be9a4201271 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=371094392 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 65.xbar_random_slow_rsp.371094392 |
| Directory | /workspace/65.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/65.xbar_random_zero_delays.2318363004 |
| Short name | T1612 |
| Test name | |
| Test status | |
| Simulation time | 518482756 ps |
| CPU time | 42.49 seconds |
| Started | Jun 28 08:46:04 PM PDT 24 |
| Finished | Jun 28 08:47:00 PM PDT 24 |
| Peak memory | 575168 kb |
| Host | smart-dfe09b94-5b0c-4c97-b12a-6e468423198b |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2318363004 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 65.xbar_random_zero_del ays.2318363004 |
| Directory | /workspace/65.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/65.xbar_same_source.571625357 |
| Short name | T2580 |
| Test name | |
| Test status | |
| Simulation time | 1817855429 ps |
| CPU time | 58.58 seconds |
| Started | Jun 28 08:46:00 PM PDT 24 |
| Finished | Jun 28 08:47:16 PM PDT 24 |
| Peak memory | 575220 kb |
| Host | smart-4bc5d454-3c00-4319-a56c-920f456def80 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=571625357 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 65.xbar_same_source.571625357 |
| Directory | /workspace/65.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/65.xbar_smoke.1613616248 |
| Short name | T2674 |
| Test name | |
| Test status | |
| Simulation time | 173931418 ps |
| CPU time | 8.43 seconds |
| Started | Jun 28 08:46:00 PM PDT 24 |
| Finished | Jun 28 08:46:25 PM PDT 24 |
| Peak memory | 574020 kb |
| Host | smart-06e8ca45-986f-4ee9-93d9-8254a09f9753 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1613616248 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 65.xbar_smoke.1613616248 |
| Directory | /workspace/65.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/65.xbar_smoke_large_delays.4237965349 |
| Short name | T1807 |
| Test name | |
| Test status | |
| Simulation time | 9496094224 ps |
| CPU time | 105.82 seconds |
| Started | Jun 28 08:46:00 PM PDT 24 |
| Finished | Jun 28 08:48:02 PM PDT 24 |
| Peak memory | 566024 kb |
| Host | smart-a299989e-a0ab-4ab4-b12e-1dadc761bf3c |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4237965349 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 65.xbar_smoke_large_delays.4237965349 |
| Directory | /workspace/65.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/65.xbar_smoke_slow_rsp.1939168574 |
| Short name | T1820 |
| Test name | |
| Test status | |
| Simulation time | 6466298703 ps |
| CPU time | 108.84 seconds |
| Started | Jun 28 08:46:08 PM PDT 24 |
| Finished | Jun 28 08:48:08 PM PDT 24 |
| Peak memory | 574180 kb |
| Host | smart-16799f22-4a6b-4d1e-9683-ab6c8e050205 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1939168574 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 65.xbar_smoke_slow_rsp.1939168574 |
| Directory | /workspace/65.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/65.xbar_smoke_zero_delays.1703420046 |
| Short name | T2643 |
| Test name | |
| Test status | |
| Simulation time | 49713241 ps |
| CPU time | 7.21 seconds |
| Started | Jun 28 08:46:09 PM PDT 24 |
| Finished | Jun 28 08:46:27 PM PDT 24 |
| Peak memory | 574180 kb |
| Host | smart-5303de00-97b6-45a4-b10b-3982f8ccea46 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1703420046 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 65.xbar_smoke_zero_delay s.1703420046 |
| Directory | /workspace/65.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/65.xbar_stress_all.3053106516 |
| Short name | T604 |
| Test name | |
| Test status | |
| Simulation time | 1646681738 ps |
| CPU time | 71.48 seconds |
| Started | Jun 28 08:46:01 PM PDT 24 |
| Finished | Jun 28 08:47:29 PM PDT 24 |
| Peak memory | 574316 kb |
| Host | smart-6141ab08-c84e-497e-b97d-64e40dbd7e4b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3053106516 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 65.xbar_stress_all.3053106516 |
| Directory | /workspace/65.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/65.xbar_stress_all_with_error.1260664723 |
| Short name | T1728 |
| Test name | |
| Test status | |
| Simulation time | 2377743311 ps |
| CPU time | 105.91 seconds |
| Started | Jun 28 08:46:02 PM PDT 24 |
| Finished | Jun 28 08:48:03 PM PDT 24 |
| Peak memory | 574588 kb |
| Host | smart-2f4c4787-dcd5-4dea-b324-9abbd75d2c19 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1260664723 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 65.xbar_stress_all_with_error.1260664723 |
| Directory | /workspace/65.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/65.xbar_stress_all_with_rand_reset.1351776733 |
| Short name | T2820 |
| Test name | |
| Test status | |
| Simulation time | 3460793568 ps |
| CPU time | 325.65 seconds |
| Started | Jun 28 08:46:01 PM PDT 24 |
| Finished | Jun 28 08:51:43 PM PDT 24 |
| Peak memory | 575444 kb |
| Host | smart-b6c6f15b-2904-4f6d-9130-f80a6d16ff47 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1351776733 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 65.xbar_stress_all _with_rand_reset.1351776733 |
| Directory | /workspace/65.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/65.xbar_stress_all_with_reset_error.1279368812 |
| Short name | T2092 |
| Test name | |
| Test status | |
| Simulation time | 6053947889 ps |
| CPU time | 627.16 seconds |
| Started | Jun 28 08:46:00 PM PDT 24 |
| Finished | Jun 28 08:56:44 PM PDT 24 |
| Peak memory | 576472 kb |
| Host | smart-4bd99597-6649-4a0d-b865-bc90d80314fe |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1279368812 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 65.xbar_stress_al l_with_reset_error.1279368812 |
| Directory | /workspace/65.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/65.xbar_unmapped_addr.3193812602 |
| Short name | T2266 |
| Test name | |
| Test status | |
| Simulation time | 1300444005 ps |
| CPU time | 60.12 seconds |
| Started | Jun 28 08:46:02 PM PDT 24 |
| Finished | Jun 28 08:47:17 PM PDT 24 |
| Peak memory | 575312 kb |
| Host | smart-534c7fdc-77d0-4c9c-84bd-7b47b5e9c18e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3193812602 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 65.xbar_unmapped_addr.3193812602 |
| Directory | /workspace/65.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/66.xbar_access_same_device.3732940427 |
| Short name | T1687 |
| Test name | |
| Test status | |
| Simulation time | 298376461 ps |
| CPU time | 30.45 seconds |
| Started | Jun 28 08:46:29 PM PDT 24 |
| Finished | Jun 28 08:47:04 PM PDT 24 |
| Peak memory | 574172 kb |
| Host | smart-7a2a6723-9f77-4829-ba2d-ced1075bf56a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3732940427 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 66.xbar_access_same_device .3732940427 |
| Directory | /workspace/66.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/66.xbar_access_same_device_slow_rsp.1205049855 |
| Short name | T460 |
| Test name | |
| Test status | |
| Simulation time | 84023690536 ps |
| CPU time | 1460.05 seconds |
| Started | Jun 28 08:46:35 PM PDT 24 |
| Finished | Jun 28 09:11:13 PM PDT 24 |
| Peak memory | 574324 kb |
| Host | smart-35d95037-08fd-488b-9de2-e12934b7c528 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1205049855 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 66.xbar_access_same_ device_slow_rsp.1205049855 |
| Directory | /workspace/66.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/66.xbar_error_and_unmapped_addr.674049799 |
| Short name | T1886 |
| Test name | |
| Test status | |
| Simulation time | 580873168 ps |
| CPU time | 27.59 seconds |
| Started | Jun 28 08:46:30 PM PDT 24 |
| Finished | Jun 28 08:47:03 PM PDT 24 |
| Peak memory | 573828 kb |
| Host | smart-800830ac-59e8-4883-a56c-93c3bf507037 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=674049799 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 66.xbar_error_and_unmapped_addr .674049799 |
| Directory | /workspace/66.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/66.xbar_error_random.1462934470 |
| Short name | T1651 |
| Test name | |
| Test status | |
| Simulation time | 1240668825 ps |
| CPU time | 43.33 seconds |
| Started | Jun 28 08:46:30 PM PDT 24 |
| Finished | Jun 28 08:47:19 PM PDT 24 |
| Peak memory | 574432 kb |
| Host | smart-3caa7663-6993-45f7-b972-58e64a1e7ce3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1462934470 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 66.xbar_error_random.1462934470 |
| Directory | /workspace/66.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/66.xbar_random.1216188242 |
| Short name | T1662 |
| Test name | |
| Test status | |
| Simulation time | 130944530 ps |
| CPU time | 16.06 seconds |
| Started | Jun 28 08:46:02 PM PDT 24 |
| Finished | Jun 28 08:46:34 PM PDT 24 |
| Peak memory | 575136 kb |
| Host | smart-c517ba49-fffa-4b26-86a8-158506541c82 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1216188242 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 66.xbar_random.1216188242 |
| Directory | /workspace/66.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/66.xbar_random_large_delays.2337161778 |
| Short name | T2811 |
| Test name | |
| Test status | |
| Simulation time | 106224951426 ps |
| CPU time | 1110.8 seconds |
| Started | Jun 28 08:46:08 PM PDT 24 |
| Finished | Jun 28 09:04:50 PM PDT 24 |
| Peak memory | 574188 kb |
| Host | smart-c23974e7-de02-4d5e-9e4c-a1b234c87942 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2337161778 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 66.xbar_random_large_delays.2337161778 |
| Directory | /workspace/66.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/66.xbar_random_slow_rsp.3591460994 |
| Short name | T2029 |
| Test name | |
| Test status | |
| Simulation time | 30832549565 ps |
| CPU time | 536.48 seconds |
| Started | Jun 28 08:46:30 PM PDT 24 |
| Finished | Jun 28 08:55:33 PM PDT 24 |
| Peak memory | 575300 kb |
| Host | smart-c2a64001-8c8d-4f4d-9917-cd2ffde4f69e |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3591460994 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 66.xbar_random_slow_rsp.3591460994 |
| Directory | /workspace/66.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/66.xbar_random_zero_delays.1906685370 |
| Short name | T1485 |
| Test name | |
| Test status | |
| Simulation time | 500280385 ps |
| CPU time | 46.47 seconds |
| Started | Jun 28 08:45:59 PM PDT 24 |
| Finished | Jun 28 08:47:02 PM PDT 24 |
| Peak memory | 574172 kb |
| Host | smart-046a8f51-1baa-477d-a553-fbb1a9c5efd8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1906685370 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 66.xbar_random_zero_del ays.1906685370 |
| Directory | /workspace/66.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/66.xbar_same_source.1078772290 |
| Short name | T2308 |
| Test name | |
| Test status | |
| Simulation time | 450586446 ps |
| CPU time | 32.9 seconds |
| Started | Jun 28 08:46:32 PM PDT 24 |
| Finished | Jun 28 08:47:16 PM PDT 24 |
| Peak memory | 574164 kb |
| Host | smart-547d6fe9-5e87-490f-8826-07d31c4fa68e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1078772290 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 66.xbar_same_source.1078772290 |
| Directory | /workspace/66.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/66.xbar_smoke.4104413320 |
| Short name | T1872 |
| Test name | |
| Test status | |
| Simulation time | 207518599 ps |
| CPU time | 9.62 seconds |
| Started | Jun 28 08:46:10 PM PDT 24 |
| Finished | Jun 28 08:46:29 PM PDT 24 |
| Peak memory | 574156 kb |
| Host | smart-24179041-307b-4250-a5bc-4d92d14fd844 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4104413320 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 66.xbar_smoke.4104413320 |
| Directory | /workspace/66.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/66.xbar_smoke_large_delays.2158446911 |
| Short name | T2330 |
| Test name | |
| Test status | |
| Simulation time | 8036880444 ps |
| CPU time | 81.89 seconds |
| Started | Jun 28 08:46:03 PM PDT 24 |
| Finished | Jun 28 08:47:40 PM PDT 24 |
| Peak memory | 574248 kb |
| Host | smart-1817cf1f-df2a-42dd-bb2c-f5926b9a7150 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2158446911 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 66.xbar_smoke_large_delays.2158446911 |
| Directory | /workspace/66.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/66.xbar_smoke_slow_rsp.2236345991 |
| Short name | T1717 |
| Test name | |
| Test status | |
| Simulation time | 6572841112 ps |
| CPU time | 108.76 seconds |
| Started | Jun 28 08:45:59 PM PDT 24 |
| Finished | Jun 28 08:48:05 PM PDT 24 |
| Peak memory | 566024 kb |
| Host | smart-e697beb5-d891-4b7d-b10d-9d0990453332 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2236345991 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 66.xbar_smoke_slow_rsp.2236345991 |
| Directory | /workspace/66.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/66.xbar_smoke_zero_delays.1853703605 |
| Short name | T2867 |
| Test name | |
| Test status | |
| Simulation time | 35256302 ps |
| CPU time | 6.15 seconds |
| Started | Jun 28 08:46:03 PM PDT 24 |
| Finished | Jun 28 08:46:24 PM PDT 24 |
| Peak memory | 574184 kb |
| Host | smart-04eec15c-7074-4a6f-8b17-514ded84039d |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1853703605 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 66.xbar_smoke_zero_delay s.1853703605 |
| Directory | /workspace/66.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/66.xbar_stress_all.1170452152 |
| Short name | T2310 |
| Test name | |
| Test status | |
| Simulation time | 2688748699 ps |
| CPU time | 247.37 seconds |
| Started | Jun 28 08:46:31 PM PDT 24 |
| Finished | Jun 28 08:50:46 PM PDT 24 |
| Peak memory | 575420 kb |
| Host | smart-917631b2-8fc3-4a07-be93-a521bb12010d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1170452152 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 66.xbar_stress_all.1170452152 |
| Directory | /workspace/66.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/66.xbar_stress_all_with_error.881816284 |
| Short name | T1560 |
| Test name | |
| Test status | |
| Simulation time | 11587588313 ps |
| CPU time | 460.77 seconds |
| Started | Jun 28 08:46:31 PM PDT 24 |
| Finished | Jun 28 08:54:19 PM PDT 24 |
| Peak memory | 574336 kb |
| Host | smart-c0b2e8bf-4816-4a63-a81e-a708ef945045 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=881816284 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 66.xbar_stress_all_with_error.881816284 |
| Directory | /workspace/66.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/66.xbar_stress_all_with_rand_reset.2600382746 |
| Short name | T2080 |
| Test name | |
| Test status | |
| Simulation time | 98171609 ps |
| CPU time | 107.92 seconds |
| Started | Jun 28 08:46:30 PM PDT 24 |
| Finished | Jun 28 08:48:23 PM PDT 24 |
| Peak memory | 575396 kb |
| Host | smart-3ee029a0-4057-4297-a31e-99b820e72233 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2600382746 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 66.xbar_stress_all _with_rand_reset.2600382746 |
| Directory | /workspace/66.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/66.xbar_stress_all_with_reset_error.3691618449 |
| Short name | T2574 |
| Test name | |
| Test status | |
| Simulation time | 2701452488 ps |
| CPU time | 243.78 seconds |
| Started | Jun 28 08:46:30 PM PDT 24 |
| Finished | Jun 28 08:50:40 PM PDT 24 |
| Peak memory | 574392 kb |
| Host | smart-be54e227-9be0-4ac7-bf56-59c79419cfe8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3691618449 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 66.xbar_stress_al l_with_reset_error.3691618449 |
| Directory | /workspace/66.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/66.xbar_unmapped_addr.41117174 |
| Short name | T1928 |
| Test name | |
| Test status | |
| Simulation time | 273595015 ps |
| CPU time | 15.05 seconds |
| Started | Jun 28 08:46:29 PM PDT 24 |
| Finished | Jun 28 08:46:49 PM PDT 24 |
| Peak memory | 575264 kb |
| Host | smart-68426423-8b7d-4195-9c37-b8c59a6a30ab |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41117174 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 66.xbar_unmapped_addr.41117174 |
| Directory | /workspace/66.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/67.xbar_access_same_device.1637129679 |
| Short name | T2223 |
| Test name | |
| Test status | |
| Simulation time | 270719005 ps |
| CPU time | 15.58 seconds |
| Started | Jun 28 08:46:30 PM PDT 24 |
| Finished | Jun 28 08:46:52 PM PDT 24 |
| Peak memory | 574012 kb |
| Host | smart-7920932b-2a58-49f8-918e-7e60542525f2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1637129679 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 67.xbar_access_same_device .1637129679 |
| Directory | /workspace/67.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/67.xbar_access_same_device_slow_rsp.4263190605 |
| Short name | T2368 |
| Test name | |
| Test status | |
| Simulation time | 78503036300 ps |
| CPU time | 1308.81 seconds |
| Started | Jun 28 08:46:30 PM PDT 24 |
| Finished | Jun 28 09:08:25 PM PDT 24 |
| Peak memory | 575544 kb |
| Host | smart-01dfb517-4846-423a-a5d0-1d9b3c4ddb55 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4263190605 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 67.xbar_access_same_ device_slow_rsp.4263190605 |
| Directory | /workspace/67.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/67.xbar_error_and_unmapped_addr.3866363632 |
| Short name | T2751 |
| Test name | |
| Test status | |
| Simulation time | 165160641 ps |
| CPU time | 18.62 seconds |
| Started | Jun 28 08:47:03 PM PDT 24 |
| Finished | Jun 28 08:47:52 PM PDT 24 |
| Peak memory | 574424 kb |
| Host | smart-0614a8eb-25bc-4576-805a-d3ec058e4040 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3866363632 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 67.xbar_error_and_unmapped_add r.3866363632 |
| Directory | /workspace/67.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/67.xbar_error_random.369285951 |
| Short name | T1447 |
| Test name | |
| Test status | |
| Simulation time | 2375330695 ps |
| CPU time | 83.44 seconds |
| Started | Jun 28 08:46:33 PM PDT 24 |
| Finished | Jun 28 08:48:10 PM PDT 24 |
| Peak memory | 574252 kb |
| Host | smart-3a8b78c5-6047-487f-a0e8-eedd6fbf2873 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=369285951 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 67.xbar_error_random.369285951 |
| Directory | /workspace/67.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/67.xbar_random.4281161213 |
| Short name | T2196 |
| Test name | |
| Test status | |
| Simulation time | 543895802 ps |
| CPU time | 47.78 seconds |
| Started | Jun 28 08:46:30 PM PDT 24 |
| Finished | Jun 28 08:47:23 PM PDT 24 |
| Peak memory | 574204 kb |
| Host | smart-a768321c-421d-4aa8-a9b1-9e68c61a3e71 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4281161213 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 67.xbar_random.4281161213 |
| Directory | /workspace/67.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/67.xbar_random_large_delays.1126817690 |
| Short name | T2742 |
| Test name | |
| Test status | |
| Simulation time | 77885064676 ps |
| CPU time | 767.42 seconds |
| Started | Jun 28 08:46:30 PM PDT 24 |
| Finished | Jun 28 08:59:25 PM PDT 24 |
| Peak memory | 574192 kb |
| Host | smart-8158d511-2773-4ec4-83ef-ec75b24547a4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1126817690 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 67.xbar_random_large_delays.1126817690 |
| Directory | /workspace/67.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/67.xbar_random_slow_rsp.10421389 |
| Short name | T571 |
| Test name | |
| Test status | |
| Simulation time | 55781181609 ps |
| CPU time | 1035.01 seconds |
| Started | Jun 28 08:46:28 PM PDT 24 |
| Finished | Jun 28 09:03:48 PM PDT 24 |
| Peak memory | 575340 kb |
| Host | smart-6e7eaf19-a0a8-4f36-9681-7664cabbbbfc |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10421389 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 67.xbar_random_slow_rsp.10421389 |
| Directory | /workspace/67.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/67.xbar_random_zero_delays.1311294154 |
| Short name | T2183 |
| Test name | |
| Test status | |
| Simulation time | 263059224 ps |
| CPU time | 28.33 seconds |
| Started | Jun 28 08:46:32 PM PDT 24 |
| Finished | Jun 28 08:47:11 PM PDT 24 |
| Peak memory | 574204 kb |
| Host | smart-ce63cbcf-d9e1-49bc-9eeb-9dd2bd3b6560 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1311294154 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 67.xbar_random_zero_del ays.1311294154 |
| Directory | /workspace/67.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/67.xbar_same_source.3700691674 |
| Short name | T2579 |
| Test name | |
| Test status | |
| Simulation time | 375762372 ps |
| CPU time | 28.55 seconds |
| Started | Jun 28 08:46:29 PM PDT 24 |
| Finished | Jun 28 08:47:01 PM PDT 24 |
| Peak memory | 574148 kb |
| Host | smart-5dce7809-50f2-488d-87e4-c6fe2fbffa4d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3700691674 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 67.xbar_same_source.3700691674 |
| Directory | /workspace/67.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/67.xbar_smoke.755017556 |
| Short name | T2680 |
| Test name | |
| Test status | |
| Simulation time | 231398733 ps |
| CPU time | 10.9 seconds |
| Started | Jun 28 08:46:30 PM PDT 24 |
| Finished | Jun 28 08:46:45 PM PDT 24 |
| Peak memory | 565928 kb |
| Host | smart-77495d00-4ee9-4c7a-9d77-ecdeec5eff3f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=755017556 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 67.xbar_smoke.755017556 |
| Directory | /workspace/67.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/67.xbar_smoke_large_delays.1524625348 |
| Short name | T1779 |
| Test name | |
| Test status | |
| Simulation time | 8010781026 ps |
| CPU time | 87.71 seconds |
| Started | Jun 28 08:46:29 PM PDT 24 |
| Finished | Jun 28 08:48:02 PM PDT 24 |
| Peak memory | 574260 kb |
| Host | smart-86c40e94-7513-4815-bed5-fe7e58bef6b5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1524625348 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 67.xbar_smoke_large_delays.1524625348 |
| Directory | /workspace/67.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/67.xbar_smoke_slow_rsp.2821830530 |
| Short name | T1835 |
| Test name | |
| Test status | |
| Simulation time | 2905602078 ps |
| CPU time | 51.53 seconds |
| Started | Jun 28 08:46:29 PM PDT 24 |
| Finished | Jun 28 08:47:25 PM PDT 24 |
| Peak memory | 574132 kb |
| Host | smart-08a446fd-f944-4257-a3fb-7c98868485d1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2821830530 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 67.xbar_smoke_slow_rsp.2821830530 |
| Directory | /workspace/67.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/67.xbar_smoke_zero_delays.253696536 |
| Short name | T1512 |
| Test name | |
| Test status | |
| Simulation time | 37378469 ps |
| CPU time | 5.88 seconds |
| Started | Jun 28 08:46:29 PM PDT 24 |
| Finished | Jun 28 08:46:40 PM PDT 24 |
| Peak memory | 574192 kb |
| Host | smart-a5b3d235-d62e-4b99-9e57-8e9578bde9ce |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=253696536 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 67.xbar_smoke_zero_delays .253696536 |
| Directory | /workspace/67.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/67.xbar_stress_all.123186975 |
| Short name | T2126 |
| Test name | |
| Test status | |
| Simulation time | 179303915 ps |
| CPU time | 23.03 seconds |
| Started | Jun 28 08:46:56 PM PDT 24 |
| Finished | Jun 28 08:47:50 PM PDT 24 |
| Peak memory | 574284 kb |
| Host | smart-00a44631-0817-40e7-9196-a800d0ec85a0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=123186975 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 67.xbar_stress_all.123186975 |
| Directory | /workspace/67.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/67.xbar_stress_all_with_error.2308016822 |
| Short name | T1376 |
| Test name | |
| Test status | |
| Simulation time | 2984402942 ps |
| CPU time | 113.57 seconds |
| Started | Jun 28 08:47:03 PM PDT 24 |
| Finished | Jun 28 08:49:27 PM PDT 24 |
| Peak memory | 574524 kb |
| Host | smart-bd0a3d7d-7244-420b-a59b-8b7373442bc3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2308016822 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 67.xbar_stress_all_with_error.2308016822 |
| Directory | /workspace/67.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/67.xbar_stress_all_with_reset_error.986816719 |
| Short name | T832 |
| Test name | |
| Test status | |
| Simulation time | 842785101 ps |
| CPU time | 239.1 seconds |
| Started | Jun 28 08:46:54 PM PDT 24 |
| Finished | Jun 28 08:51:25 PM PDT 24 |
| Peak memory | 574360 kb |
| Host | smart-3a6caf0d-2830-47da-bb27-67d9ce278dd8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=986816719 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 67.xbar_stress_all _with_reset_error.986816719 |
| Directory | /workspace/67.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/67.xbar_unmapped_addr.1813801900 |
| Short name | T1416 |
| Test name | |
| Test status | |
| Simulation time | 1284506477 ps |
| CPU time | 57.93 seconds |
| Started | Jun 28 08:46:59 PM PDT 24 |
| Finished | Jun 28 08:48:27 PM PDT 24 |
| Peak memory | 574248 kb |
| Host | smart-7251c3df-b4eb-48eb-aec3-e67cae55ad3b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1813801900 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 67.xbar_unmapped_addr.1813801900 |
| Directory | /workspace/67.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/68.xbar_access_same_device.627473019 |
| Short name | T1419 |
| Test name | |
| Test status | |
| Simulation time | 493440685 ps |
| CPU time | 31.44 seconds |
| Started | Jun 28 08:46:55 PM PDT 24 |
| Finished | Jun 28 08:47:58 PM PDT 24 |
| Peak memory | 575228 kb |
| Host | smart-2bfcdd20-e6b1-42f5-85c1-45265b2c4e77 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=627473019 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 68.xbar_access_same_device. 627473019 |
| Directory | /workspace/68.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/68.xbar_access_same_device_slow_rsp.1362340862 |
| Short name | T787 |
| Test name | |
| Test status | |
| Simulation time | 46099680048 ps |
| CPU time | 792.9 seconds |
| Started | Jun 28 08:46:57 PM PDT 24 |
| Finished | Jun 28 09:00:41 PM PDT 24 |
| Peak memory | 575380 kb |
| Host | smart-421df375-de22-428f-a805-060b40883820 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1362340862 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 68.xbar_access_same_ device_slow_rsp.1362340862 |
| Directory | /workspace/68.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/68.xbar_error_and_unmapped_addr.472102539 |
| Short name | T2358 |
| Test name | |
| Test status | |
| Simulation time | 342408493 ps |
| CPU time | 16.53 seconds |
| Started | Jun 28 08:46:55 PM PDT 24 |
| Finished | Jun 28 08:47:43 PM PDT 24 |
| Peak memory | 574436 kb |
| Host | smart-1cf71e6b-3ecc-4bdb-898f-3714a52277d4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=472102539 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 68.xbar_error_and_unmapped_addr .472102539 |
| Directory | /workspace/68.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/68.xbar_error_random.804615528 |
| Short name | T2830 |
| Test name | |
| Test status | |
| Simulation time | 1761423838 ps |
| CPU time | 64.75 seconds |
| Started | Jun 28 08:46:59 PM PDT 24 |
| Finished | Jun 28 08:48:34 PM PDT 24 |
| Peak memory | 574424 kb |
| Host | smart-7b4eb33b-48a5-4cc7-bb7c-3c8e72686ed8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=804615528 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 68.xbar_error_random.804615528 |
| Directory | /workspace/68.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/68.xbar_random.3429472456 |
| Short name | T1542 |
| Test name | |
| Test status | |
| Simulation time | 236824919 ps |
| CPU time | 23.12 seconds |
| Started | Jun 28 08:47:00 PM PDT 24 |
| Finished | Jun 28 08:47:54 PM PDT 24 |
| Peak memory | 575232 kb |
| Host | smart-7ec81a52-76d7-4a09-8866-043d020b10b4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3429472456 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 68.xbar_random.3429472456 |
| Directory | /workspace/68.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/68.xbar_random_large_delays.232718312 |
| Short name | T2498 |
| Test name | |
| Test status | |
| Simulation time | 52020697447 ps |
| CPU time | 554.46 seconds |
| Started | Jun 28 08:46:59 PM PDT 24 |
| Finished | Jun 28 08:56:44 PM PDT 24 |
| Peak memory | 575300 kb |
| Host | smart-17dff0d2-243d-44e1-8feb-a41d780163ab |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=232718312 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 68.xbar_random_large_delays.232718312 |
| Directory | /workspace/68.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/68.xbar_random_slow_rsp.2822668911 |
| Short name | T1819 |
| Test name | |
| Test status | |
| Simulation time | 49080953807 ps |
| CPU time | 866.58 seconds |
| Started | Jun 28 08:47:02 PM PDT 24 |
| Finished | Jun 28 09:02:00 PM PDT 24 |
| Peak memory | 575340 kb |
| Host | smart-17329a4a-55ca-4914-82be-3df8eaf29450 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2822668911 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 68.xbar_random_slow_rsp.2822668911 |
| Directory | /workspace/68.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/68.xbar_random_zero_delays.429264161 |
| Short name | T2366 |
| Test name | |
| Test status | |
| Simulation time | 501032344 ps |
| CPU time | 48.53 seconds |
| Started | Jun 28 08:46:59 PM PDT 24 |
| Finished | Jun 28 08:48:18 PM PDT 24 |
| Peak memory | 575416 kb |
| Host | smart-13f625c0-a768-4e24-bd0f-fcfe5142763b |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=429264161 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 68.xbar_random_zero_dela ys.429264161 |
| Directory | /workspace/68.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/68.xbar_same_source.1703099595 |
| Short name | T2677 |
| Test name | |
| Test status | |
| Simulation time | 297614929 ps |
| CPU time | 23.33 seconds |
| Started | Jun 28 08:46:56 PM PDT 24 |
| Finished | Jun 28 08:47:51 PM PDT 24 |
| Peak memory | 574168 kb |
| Host | smart-269e1a8f-7bc7-4250-84d2-358289b19e5f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1703099595 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 68.xbar_same_source.1703099595 |
| Directory | /workspace/68.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/68.xbar_smoke.3269356516 |
| Short name | T1559 |
| Test name | |
| Test status | |
| Simulation time | 49996001 ps |
| CPU time | 6.76 seconds |
| Started | Jun 28 08:46:59 PM PDT 24 |
| Finished | Jun 28 08:47:36 PM PDT 24 |
| Peak memory | 574180 kb |
| Host | smart-65a97c9e-35d1-45ae-a59a-7dfc07b1ae1f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3269356516 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 68.xbar_smoke.3269356516 |
| Directory | /workspace/68.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/68.xbar_smoke_large_delays.3516964932 |
| Short name | T534 |
| Test name | |
| Test status | |
| Simulation time | 10979381709 ps |
| CPU time | 109.91 seconds |
| Started | Jun 28 08:46:56 PM PDT 24 |
| Finished | Jun 28 08:49:18 PM PDT 24 |
| Peak memory | 574268 kb |
| Host | smart-cdc174d7-965b-425a-92b9-66cd50da578c |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3516964932 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 68.xbar_smoke_large_delays.3516964932 |
| Directory | /workspace/68.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/68.xbar_smoke_slow_rsp.2659454849 |
| Short name | T1556 |
| Test name | |
| Test status | |
| Simulation time | 5149066387 ps |
| CPU time | 87.94 seconds |
| Started | Jun 28 08:46:59 PM PDT 24 |
| Finished | Jun 28 08:48:57 PM PDT 24 |
| Peak memory | 574256 kb |
| Host | smart-a8154a54-9f97-4d27-8aa1-80b3b3acd207 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2659454849 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 68.xbar_smoke_slow_rsp.2659454849 |
| Directory | /workspace/68.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/68.xbar_smoke_zero_delays.2435160737 |
| Short name | T1319 |
| Test name | |
| Test status | |
| Simulation time | 37560444 ps |
| CPU time | 6.08 seconds |
| Started | Jun 28 08:47:03 PM PDT 24 |
| Finished | Jun 28 08:47:40 PM PDT 24 |
| Peak memory | 565932 kb |
| Host | smart-83fa1da6-0f88-43cf-b926-30952651edd7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2435160737 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 68.xbar_smoke_zero_delay s.2435160737 |
| Directory | /workspace/68.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/68.xbar_stress_all.2036452432 |
| Short name | T2686 |
| Test name | |
| Test status | |
| Simulation time | 11788190118 ps |
| CPU time | 470.97 seconds |
| Started | Jun 28 08:46:56 PM PDT 24 |
| Finished | Jun 28 08:55:17 PM PDT 24 |
| Peak memory | 575424 kb |
| Host | smart-f995656c-4931-421a-8f67-616fccc404a5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2036452432 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 68.xbar_stress_all.2036452432 |
| Directory | /workspace/68.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/68.xbar_stress_all_with_error.4066518782 |
| Short name | T2706 |
| Test name | |
| Test status | |
| Simulation time | 5866732 ps |
| CPU time | 4 seconds |
| Started | Jun 28 08:46:56 PM PDT 24 |
| Finished | Jun 28 08:47:32 PM PDT 24 |
| Peak memory | 565396 kb |
| Host | smart-d3d7faa4-203b-420c-80d7-29810a45dcd5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4066518782 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 68.xbar_stress_all_with_error.4066518782 |
| Directory | /workspace/68.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/68.xbar_stress_all_with_rand_reset.3464933755 |
| Short name | T463 |
| Test name | |
| Test status | |
| Simulation time | 2179444189 ps |
| CPU time | 209.34 seconds |
| Started | Jun 28 08:46:59 PM PDT 24 |
| Finished | Jun 28 08:50:59 PM PDT 24 |
| Peak memory | 575580 kb |
| Host | smart-a87f0b68-8c56-46e0-8432-1daf8551209b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3464933755 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 68.xbar_stress_all _with_rand_reset.3464933755 |
| Directory | /workspace/68.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/68.xbar_stress_all_with_reset_error.1646121273 |
| Short name | T2548 |
| Test name | |
| Test status | |
| Simulation time | 746167476 ps |
| CPU time | 219.39 seconds |
| Started | Jun 28 08:47:02 PM PDT 24 |
| Finished | Jun 28 08:51:12 PM PDT 24 |
| Peak memory | 576408 kb |
| Host | smart-e5ae5398-2253-4cfe-8134-4fd11c56b607 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1646121273 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 68.xbar_stress_al l_with_reset_error.1646121273 |
| Directory | /workspace/68.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/68.xbar_unmapped_addr.199025951 |
| Short name | T2732 |
| Test name | |
| Test status | |
| Simulation time | 963344379 ps |
| CPU time | 45.13 seconds |
| Started | Jun 28 08:46:59 PM PDT 24 |
| Finished | Jun 28 08:48:15 PM PDT 24 |
| Peak memory | 575264 kb |
| Host | smart-ea16e324-bf3f-4d8d-89a0-7837a6299d08 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=199025951 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 68.xbar_unmapped_addr.199025951 |
| Directory | /workspace/68.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/69.xbar_access_same_device.504173053 |
| Short name | T1434 |
| Test name | |
| Test status | |
| Simulation time | 228371644 ps |
| CPU time | 22.19 seconds |
| Started | Jun 28 08:47:23 PM PDT 24 |
| Finished | Jun 28 08:48:11 PM PDT 24 |
| Peak memory | 575352 kb |
| Host | smart-158f9e53-bbdb-46e2-a682-bea899847dbc |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=504173053 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 69.xbar_access_same_device. 504173053 |
| Directory | /workspace/69.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/69.xbar_access_same_device_slow_rsp.1763838121 |
| Short name | T1598 |
| Test name | |
| Test status | |
| Simulation time | 118309144582 ps |
| CPU time | 1976.18 seconds |
| Started | Jun 28 08:47:26 PM PDT 24 |
| Finished | Jun 28 09:20:47 PM PDT 24 |
| Peak memory | 574336 kb |
| Host | smart-5ab90f8c-3331-4654-a54e-e5938dcc82c9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1763838121 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 69.xbar_access_same_ device_slow_rsp.1763838121 |
| Directory | /workspace/69.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/69.xbar_error_and_unmapped_addr.3698978962 |
| Short name | T2161 |
| Test name | |
| Test status | |
| Simulation time | 215792951 ps |
| CPU time | 12.51 seconds |
| Started | Jun 28 08:47:24 PM PDT 24 |
| Finished | Jun 28 08:48:02 PM PDT 24 |
| Peak memory | 574384 kb |
| Host | smart-54162c29-0d44-4c73-abbf-46243a6c0476 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3698978962 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 69.xbar_error_and_unmapped_add r.3698978962 |
| Directory | /workspace/69.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/69.xbar_error_random.2408727391 |
| Short name | T1321 |
| Test name | |
| Test status | |
| Simulation time | 531360937 ps |
| CPU time | 18.47 seconds |
| Started | Jun 28 08:47:27 PM PDT 24 |
| Finished | Jun 28 08:48:09 PM PDT 24 |
| Peak memory | 573836 kb |
| Host | smart-c5b8f9eb-d792-43d5-a0cc-2eb4d6f85172 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2408727391 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 69.xbar_error_random.2408727391 |
| Directory | /workspace/69.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/69.xbar_random.1836333692 |
| Short name | T1657 |
| Test name | |
| Test status | |
| Simulation time | 2028167288 ps |
| CPU time | 96.5 seconds |
| Started | Jun 28 08:46:59 PM PDT 24 |
| Finished | Jun 28 08:49:08 PM PDT 24 |
| Peak memory | 574208 kb |
| Host | smart-626eca28-125d-4fca-be95-2c94acf4cefe |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1836333692 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 69.xbar_random.1836333692 |
| Directory | /workspace/69.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/69.xbar_random_large_delays.2856855289 |
| Short name | T615 |
| Test name | |
| Test status | |
| Simulation time | 57431077965 ps |
| CPU time | 602.24 seconds |
| Started | Jun 28 08:46:53 PM PDT 24 |
| Finished | Jun 28 08:57:28 PM PDT 24 |
| Peak memory | 574300 kb |
| Host | smart-714e6210-6ae2-4b9f-bc10-327bf889779d |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2856855289 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 69.xbar_random_large_delays.2856855289 |
| Directory | /workspace/69.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/69.xbar_random_slow_rsp.4186266502 |
| Short name | T627 |
| Test name | |
| Test status | |
| Simulation time | 47068719462 ps |
| CPU time | 804.82 seconds |
| Started | Jun 28 08:46:56 PM PDT 24 |
| Finished | Jun 28 09:00:51 PM PDT 24 |
| Peak memory | 575312 kb |
| Host | smart-31ea82ba-ce0f-4146-8295-55b8a0c610e8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4186266502 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 69.xbar_random_slow_rsp.4186266502 |
| Directory | /workspace/69.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/69.xbar_random_zero_delays.3484897579 |
| Short name | T2055 |
| Test name | |
| Test status | |
| Simulation time | 452602792 ps |
| CPU time | 39.84 seconds |
| Started | Jun 28 08:47:02 PM PDT 24 |
| Finished | Jun 28 08:48:14 PM PDT 24 |
| Peak memory | 574164 kb |
| Host | smart-ba99f34a-f577-4368-8042-6c7405745190 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3484897579 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 69.xbar_random_zero_del ays.3484897579 |
| Directory | /workspace/69.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/69.xbar_same_source.4170627356 |
| Short name | T2577 |
| Test name | |
| Test status | |
| Simulation time | 84838728 ps |
| CPU time | 10.91 seconds |
| Started | Jun 28 08:47:25 PM PDT 24 |
| Finished | Jun 28 08:48:00 PM PDT 24 |
| Peak memory | 574160 kb |
| Host | smart-77b3a6b0-adaa-44f0-89d6-7ed6d435a5de |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4170627356 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 69.xbar_same_source.4170627356 |
| Directory | /workspace/69.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/69.xbar_smoke.3549889085 |
| Short name | T2267 |
| Test name | |
| Test status | |
| Simulation time | 43159043 ps |
| CPU time | 6.07 seconds |
| Started | Jun 28 08:46:59 PM PDT 24 |
| Finished | Jun 28 08:47:35 PM PDT 24 |
| Peak memory | 565948 kb |
| Host | smart-843ded9f-5fa9-4d47-ae83-4d21fece3c97 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3549889085 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 69.xbar_smoke.3549889085 |
| Directory | /workspace/69.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/69.xbar_smoke_large_delays.1216301857 |
| Short name | T622 |
| Test name | |
| Test status | |
| Simulation time | 5172795649 ps |
| CPU time | 57.66 seconds |
| Started | Jun 28 08:46:56 PM PDT 24 |
| Finished | Jun 28 08:48:24 PM PDT 24 |
| Peak memory | 574252 kb |
| Host | smart-ea4da425-90f7-4eb7-89d2-374eda8908b9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1216301857 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 69.xbar_smoke_large_delays.1216301857 |
| Directory | /workspace/69.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/69.xbar_smoke_slow_rsp.2785776007 |
| Short name | T1599 |
| Test name | |
| Test status | |
| Simulation time | 3957312946 ps |
| CPU time | 65.15 seconds |
| Started | Jun 28 08:47:02 PM PDT 24 |
| Finished | Jun 28 08:48:39 PM PDT 24 |
| Peak memory | 574056 kb |
| Host | smart-fb0bb190-0844-41cc-8eb3-5accc2b5c7c5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2785776007 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 69.xbar_smoke_slow_rsp.2785776007 |
| Directory | /workspace/69.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/69.xbar_smoke_zero_delays.1752033577 |
| Short name | T530 |
| Test name | |
| Test status | |
| Simulation time | 53164641 ps |
| CPU time | 6.64 seconds |
| Started | Jun 28 08:46:59 PM PDT 24 |
| Finished | Jun 28 08:47:36 PM PDT 24 |
| Peak memory | 574176 kb |
| Host | smart-49992407-e883-4ae6-a060-6a9a2e09d88d |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1752033577 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 69.xbar_smoke_zero_delay s.1752033577 |
| Directory | /workspace/69.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/69.xbar_stress_all.2110735740 |
| Short name | T2758 |
| Test name | |
| Test status | |
| Simulation time | 13495799985 ps |
| CPU time | 541.31 seconds |
| Started | Jun 28 08:47:27 PM PDT 24 |
| Finished | Jun 28 08:56:52 PM PDT 24 |
| Peak memory | 574412 kb |
| Host | smart-6c87e436-eeca-407d-be1e-d59ffb773b00 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2110735740 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 69.xbar_stress_all.2110735740 |
| Directory | /workspace/69.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/69.xbar_stress_all_with_error.3784975993 |
| Short name | T1697 |
| Test name | |
| Test status | |
| Simulation time | 2376683440 ps |
| CPU time | 191.9 seconds |
| Started | Jun 28 08:47:23 PM PDT 24 |
| Finished | Jun 28 08:50:59 PM PDT 24 |
| Peak memory | 574652 kb |
| Host | smart-0eefe9e4-af68-44bc-b9fa-9346b501ea2e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3784975993 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 69.xbar_stress_all_with_error.3784975993 |
| Directory | /workspace/69.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/69.xbar_stress_all_with_rand_reset.1043812193 |
| Short name | T80 |
| Test name | |
| Test status | |
| Simulation time | 233208496 ps |
| CPU time | 50.54 seconds |
| Started | Jun 28 08:47:22 PM PDT 24 |
| Finished | Jun 28 08:48:37 PM PDT 24 |
| Peak memory | 575388 kb |
| Host | smart-28ac5b64-001c-4df4-a461-993a9a1ca09d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1043812193 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 69.xbar_stress_all _with_rand_reset.1043812193 |
| Directory | /workspace/69.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/69.xbar_stress_all_with_reset_error.431913569 |
| Short name | T2592 |
| Test name | |
| Test status | |
| Simulation time | 2065138095 ps |
| CPU time | 145.81 seconds |
| Started | Jun 28 08:47:28 PM PDT 24 |
| Finished | Jun 28 08:50:18 PM PDT 24 |
| Peak memory | 574604 kb |
| Host | smart-7f5e3740-7129-46bf-892b-b41511c59a51 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=431913569 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 69.xbar_stress_all _with_reset_error.431913569 |
| Directory | /workspace/69.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/69.xbar_unmapped_addr.784132645 |
| Short name | T1437 |
| Test name | |
| Test status | |
| Simulation time | 342526190 ps |
| CPU time | 43.4 seconds |
| Started | Jun 28 08:47:25 PM PDT 24 |
| Finished | Jun 28 08:48:33 PM PDT 24 |
| Peak memory | 575280 kb |
| Host | smart-858a781c-3c2a-4ecd-9ba4-5ba9c8ec514f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=784132645 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 69.xbar_unmapped_addr.784132645 |
| Directory | /workspace/69.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/7.chip_csr_rw.3757153798 |
| Short name | T424 |
| Test name | |
| Test status | |
| Simulation time | 4275823292 ps |
| CPU time | 356.79 seconds |
| Started | Jun 28 08:32:46 PM PDT 24 |
| Finished | Jun 28 08:38:44 PM PDT 24 |
| Peak memory | 596120 kb |
| Host | smart-da09d844-e100-4c38-a6a0-265572fa80f8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3757153798 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.chip_csr_rw.3757153798 |
| Directory | /workspace/7.chip_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/7.chip_same_csr_outstanding.2609762172 |
| Short name | T2824 |
| Test name | |
| Test status | |
| Simulation time | 16766927261 ps |
| CPU time | 2026.83 seconds |
| Started | Jun 28 08:31:56 PM PDT 24 |
| Finished | Jun 28 09:05:54 PM PDT 24 |
| Peak memory | 591836 kb |
| Host | smart-e2930e7c-0c61-4063-b31c-091fc0c64da1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +run_same_csr_outstanding +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2609762172 -assert nopostproc +UVM_TE STNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb - cm_log /dev/null -cm_name 7.chip_same_csr_outstanding.2609762172 |
| Directory | /workspace/7.chip_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/7.chip_tl_errors.1063742955 |
| Short name | T2173 |
| Test name | |
| Test status | |
| Simulation time | 2479448998 ps |
| CPU time | 106.06 seconds |
| Started | Jun 28 08:32:20 PM PDT 24 |
| Finished | Jun 28 08:34:11 PM PDT 24 |
| Peak memory | 597444 kb |
| Host | smart-38a8d076-569e-432b-a1cd-a61cda0747c5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1063742955 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.chip_tl_errors.1063742955 |
| Directory | /workspace/7.chip_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/7.xbar_access_same_device.284659844 |
| Short name | T2101 |
| Test name | |
| Test status | |
| Simulation time | 382626015 ps |
| CPU time | 33.82 seconds |
| Started | Jun 28 08:32:45 PM PDT 24 |
| Finished | Jun 28 08:33:20 PM PDT 24 |
| Peak memory | 575236 kb |
| Host | smart-7f3f3aca-ee55-4223-b359-27af7140ac4e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=284659844 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.xbar_access_same_device.284659844 |
| Directory | /workspace/7.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/7.xbar_access_same_device_slow_rsp.2928983589 |
| Short name | T1900 |
| Test name | |
| Test status | |
| Simulation time | 63672621261 ps |
| CPU time | 1160.71 seconds |
| Started | Jun 28 08:32:47 PM PDT 24 |
| Finished | Jun 28 08:52:09 PM PDT 24 |
| Peak memory | 574296 kb |
| Host | smart-df05b785-58c1-4723-a400-f665a999fec4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2928983589 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.xbar_access_same_d evice_slow_rsp.2928983589 |
| Directory | /workspace/7.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/7.xbar_error_and_unmapped_addr.2894278374 |
| Short name | T1506 |
| Test name | |
| Test status | |
| Simulation time | 229629783 ps |
| CPU time | 29.3 seconds |
| Started | Jun 28 08:32:50 PM PDT 24 |
| Finished | Jun 28 08:33:20 PM PDT 24 |
| Peak memory | 574440 kb |
| Host | smart-d2e31202-e9b7-42d4-9680-e8d7420b2db8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2894278374 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.xbar_error_and_unmapped_addr .2894278374 |
| Directory | /workspace/7.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/7.xbar_error_random.73874487 |
| Short name | T1569 |
| Test name | |
| Test status | |
| Simulation time | 157342373 ps |
| CPU time | 17.99 seconds |
| Started | Jun 28 08:32:45 PM PDT 24 |
| Finished | Jun 28 08:33:05 PM PDT 24 |
| Peak memory | 574416 kb |
| Host | smart-15d17037-f969-463e-9e34-e2097338decb |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73874487 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.xbar_error_random.73874487 |
| Directory | /workspace/7.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/7.xbar_random.3970501588 |
| Short name | T1834 |
| Test name | |
| Test status | |
| Simulation time | 150878791 ps |
| CPU time | 17.93 seconds |
| Started | Jun 28 08:32:20 PM PDT 24 |
| Finished | Jun 28 08:32:42 PM PDT 24 |
| Peak memory | 575228 kb |
| Host | smart-3fe81b54-1541-4465-8af4-045aef9466e3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3970501588 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.xbar_random.3970501588 |
| Directory | /workspace/7.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/7.xbar_random_large_delays.2265932660 |
| Short name | T2218 |
| Test name | |
| Test status | |
| Simulation time | 5346061580 ps |
| CPU time | 60.14 seconds |
| Started | Jun 28 08:32:22 PM PDT 24 |
| Finished | Jun 28 08:33:25 PM PDT 24 |
| Peak memory | 574224 kb |
| Host | smart-76f4e315-89ef-4fad-9e41-f60854ea0a59 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2265932660 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.xbar_random_large_delays.2265932660 |
| Directory | /workspace/7.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/7.xbar_random_slow_rsp.569401090 |
| Short name | T1741 |
| Test name | |
| Test status | |
| Simulation time | 11497830158 ps |
| CPU time | 208.84 seconds |
| Started | Jun 28 08:32:48 PM PDT 24 |
| Finished | Jun 28 08:36:19 PM PDT 24 |
| Peak memory | 575316 kb |
| Host | smart-dbdd7349-9a23-42b4-9567-738be5d6b2d5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=569401090 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.xbar_random_slow_rsp.569401090 |
| Directory | /workspace/7.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/7.xbar_random_zero_delays.3458721020 |
| Short name | T1341 |
| Test name | |
| Test status | |
| Simulation time | 114293371 ps |
| CPU time | 13.63 seconds |
| Started | Jun 28 08:32:18 PM PDT 24 |
| Finished | Jun 28 08:32:33 PM PDT 24 |
| Peak memory | 575120 kb |
| Host | smart-b5014044-6c58-4039-8d31-36048cc32755 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3458721020 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.xbar_random_zero_dela ys.3458721020 |
| Directory | /workspace/7.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/7.xbar_same_source.791908666 |
| Short name | T2147 |
| Test name | |
| Test status | |
| Simulation time | 2188690146 ps |
| CPU time | 76.53 seconds |
| Started | Jun 28 08:32:44 PM PDT 24 |
| Finished | Jun 28 08:34:02 PM PDT 24 |
| Peak memory | 574144 kb |
| Host | smart-ad8cbe84-8b03-4f17-8952-2ce293087579 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=791908666 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.xbar_same_source.791908666 |
| Directory | /workspace/7.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/7.xbar_smoke.3518587036 |
| Short name | T1645 |
| Test name | |
| Test status | |
| Simulation time | 179761783 ps |
| CPU time | 9.2 seconds |
| Started | Jun 28 08:32:21 PM PDT 24 |
| Finished | Jun 28 08:32:34 PM PDT 24 |
| Peak memory | 565884 kb |
| Host | smart-5a77a7aa-592a-489b-8bcd-f84cf566ffac |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3518587036 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.xbar_smoke.3518587036 |
| Directory | /workspace/7.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/7.xbar_smoke_large_delays.3286442711 |
| Short name | T1446 |
| Test name | |
| Test status | |
| Simulation time | 8736213339 ps |
| CPU time | 90.32 seconds |
| Started | Jun 28 08:32:20 PM PDT 24 |
| Finished | Jun 28 08:33:54 PM PDT 24 |
| Peak memory | 566012 kb |
| Host | smart-8138b891-45c7-46fd-a619-2f83f184a6e1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3286442711 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.xbar_smoke_large_delays.3286442711 |
| Directory | /workspace/7.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/7.xbar_smoke_slow_rsp.2863140037 |
| Short name | T2252 |
| Test name | |
| Test status | |
| Simulation time | 3443157105 ps |
| CPU time | 60.36 seconds |
| Started | Jun 28 08:32:21 PM PDT 24 |
| Finished | Jun 28 08:33:25 PM PDT 24 |
| Peak memory | 565960 kb |
| Host | smart-adde934f-2fe4-44f5-bb45-68ba6519be31 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2863140037 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.xbar_smoke_slow_rsp.2863140037 |
| Directory | /workspace/7.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/7.xbar_smoke_zero_delays.3740471860 |
| Short name | T1942 |
| Test name | |
| Test status | |
| Simulation time | 48878556 ps |
| CPU time | 7.02 seconds |
| Started | Jun 28 08:32:18 PM PDT 24 |
| Finished | Jun 28 08:32:26 PM PDT 24 |
| Peak memory | 574176 kb |
| Host | smart-e2e1b6e9-09fa-4d4e-bb3c-3782c465d249 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3740471860 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.xbar_smoke_zero_delays .3740471860 |
| Directory | /workspace/7.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/7.xbar_stress_all.3610848653 |
| Short name | T2687 |
| Test name | |
| Test status | |
| Simulation time | 9357309508 ps |
| CPU time | 363.15 seconds |
| Started | Jun 28 08:32:47 PM PDT 24 |
| Finished | Jun 28 08:38:51 PM PDT 24 |
| Peak memory | 575428 kb |
| Host | smart-fa912496-046a-4175-a1c8-35932da80917 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3610848653 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.xbar_stress_all.3610848653 |
| Directory | /workspace/7.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/7.xbar_stress_all_with_error.2625026065 |
| Short name | T536 |
| Test name | |
| Test status | |
| Simulation time | 533828337 ps |
| CPU time | 51.93 seconds |
| Started | Jun 28 08:32:44 PM PDT 24 |
| Finished | Jun 28 08:33:37 PM PDT 24 |
| Peak memory | 574312 kb |
| Host | smart-2ea4cf60-351d-47b8-ba04-dd340a3c8aa1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2625026065 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.xbar_stress_all_with_error.2625026065 |
| Directory | /workspace/7.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/7.xbar_stress_all_with_rand_reset.862680767 |
| Short name | T824 |
| Test name | |
| Test status | |
| Simulation time | 909758940 ps |
| CPU time | 217.24 seconds |
| Started | Jun 28 08:32:49 PM PDT 24 |
| Finished | Jun 28 08:36:28 PM PDT 24 |
| Peak memory | 575384 kb |
| Host | smart-e9c506ee-d9ba-47d0-87d8-26feac879d13 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=862680767 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_res et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.xbar_stress_all_w ith_rand_reset.862680767 |
| Directory | /workspace/7.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/7.xbar_stress_all_with_reset_error.3080163857 |
| Short name | T2775 |
| Test name | |
| Test status | |
| Simulation time | 20626393 ps |
| CPU time | 22.41 seconds |
| Started | Jun 28 08:32:45 PM PDT 24 |
| Finished | Jun 28 08:33:09 PM PDT 24 |
| Peak memory | 575336 kb |
| Host | smart-5f97561f-ed8a-4fc6-93cb-2855ccd4841b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3080163857 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.xbar_stress_all _with_reset_error.3080163857 |
| Directory | /workspace/7.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/7.xbar_unmapped_addr.3441456223 |
| Short name | T575 |
| Test name | |
| Test status | |
| Simulation time | 274159894 ps |
| CPU time | 36.7 seconds |
| Started | Jun 28 08:32:45 PM PDT 24 |
| Finished | Jun 28 08:33:24 PM PDT 24 |
| Peak memory | 574196 kb |
| Host | smart-abe7d709-3a20-41a2-813b-2e70d36aa8bf |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3441456223 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.xbar_unmapped_addr.3441456223 |
| Directory | /workspace/7.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/70.xbar_access_same_device.2938945221 |
| Short name | T1602 |
| Test name | |
| Test status | |
| Simulation time | 742730244 ps |
| CPU time | 30.52 seconds |
| Started | Jun 28 08:47:23 PM PDT 24 |
| Finished | Jun 28 08:48:17 PM PDT 24 |
| Peak memory | 574160 kb |
| Host | smart-ea73afa0-d894-4321-847f-144d23a12090 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2938945221 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 70.xbar_access_same_device .2938945221 |
| Directory | /workspace/70.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/70.xbar_access_same_device_slow_rsp.521055121 |
| Short name | T2633 |
| Test name | |
| Test status | |
| Simulation time | 119914084520 ps |
| CPU time | 2037.8 seconds |
| Started | Jun 28 08:47:25 PM PDT 24 |
| Finished | Jun 28 09:21:47 PM PDT 24 |
| Peak memory | 574384 kb |
| Host | smart-9e96a817-7e58-487e-a7b4-553acb001d0b |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=521055121 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 70.xbar_access_same_d evice_slow_rsp.521055121 |
| Directory | /workspace/70.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/70.xbar_error_and_unmapped_addr.3037268263 |
| Short name | T1323 |
| Test name | |
| Test status | |
| Simulation time | 282452094 ps |
| CPU time | 13.97 seconds |
| Started | Jun 28 08:47:23 PM PDT 24 |
| Finished | Jun 28 08:48:01 PM PDT 24 |
| Peak memory | 573884 kb |
| Host | smart-045d9787-564f-4897-bffd-3c4b62852a44 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3037268263 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 70.xbar_error_and_unmapped_add r.3037268263 |
| Directory | /workspace/70.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/70.xbar_error_random.2022650329 |
| Short name | T2731 |
| Test name | |
| Test status | |
| Simulation time | 62495280 ps |
| CPU time | 8.41 seconds |
| Started | Jun 28 08:47:25 PM PDT 24 |
| Finished | Jun 28 08:47:58 PM PDT 24 |
| Peak memory | 574428 kb |
| Host | smart-811739ba-b9bc-41e5-812f-45595dcaa582 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2022650329 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 70.xbar_error_random.2022650329 |
| Directory | /workspace/70.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/70.xbar_random.2303134085 |
| Short name | T1696 |
| Test name | |
| Test status | |
| Simulation time | 100076601 ps |
| CPU time | 7.99 seconds |
| Started | Jun 28 08:47:23 PM PDT 24 |
| Finished | Jun 28 08:47:55 PM PDT 24 |
| Peak memory | 574092 kb |
| Host | smart-39fd9211-8a08-4cdd-ac66-22fe3698713b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2303134085 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 70.xbar_random.2303134085 |
| Directory | /workspace/70.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/70.xbar_random_large_delays.2394117757 |
| Short name | T1920 |
| Test name | |
| Test status | |
| Simulation time | 29259569208 ps |
| CPU time | 329.97 seconds |
| Started | Jun 28 08:47:24 PM PDT 24 |
| Finished | Jun 28 08:53:19 PM PDT 24 |
| Peak memory | 575324 kb |
| Host | smart-fa91f5be-04e7-477d-80f8-5a0fe6537dad |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2394117757 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 70.xbar_random_large_delays.2394117757 |
| Directory | /workspace/70.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/70.xbar_random_slow_rsp.3039313766 |
| Short name | T2275 |
| Test name | |
| Test status | |
| Simulation time | 25373930998 ps |
| CPU time | 440.56 seconds |
| Started | Jun 28 08:47:27 PM PDT 24 |
| Finished | Jun 28 08:55:11 PM PDT 24 |
| Peak memory | 574256 kb |
| Host | smart-d1a46d62-f77b-4730-bd77-3e64ad602026 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3039313766 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 70.xbar_random_slow_rsp.3039313766 |
| Directory | /workspace/70.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/70.xbar_random_zero_delays.3429720034 |
| Short name | T2393 |
| Test name | |
| Test status | |
| Simulation time | 162766633 ps |
| CPU time | 18.64 seconds |
| Started | Jun 28 08:47:24 PM PDT 24 |
| Finished | Jun 28 08:48:08 PM PDT 24 |
| Peak memory | 575228 kb |
| Host | smart-b204cda4-386c-4eb4-bd8b-74d217fc5be8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3429720034 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 70.xbar_random_zero_del ays.3429720034 |
| Directory | /workspace/70.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/70.xbar_same_source.3723976555 |
| Short name | T1704 |
| Test name | |
| Test status | |
| Simulation time | 551679106 ps |
| CPU time | 38.21 seconds |
| Started | Jun 28 08:47:28 PM PDT 24 |
| Finished | Jun 28 08:48:31 PM PDT 24 |
| Peak memory | 575228 kb |
| Host | smart-e18e941e-d9d9-4128-a1bb-1583eb08f4e3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3723976555 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 70.xbar_same_source.3723976555 |
| Directory | /workspace/70.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/70.xbar_smoke.4010809825 |
| Short name | T1703 |
| Test name | |
| Test status | |
| Simulation time | 53886513 ps |
| CPU time | 7.13 seconds |
| Started | Jun 28 08:47:25 PM PDT 24 |
| Finished | Jun 28 08:47:56 PM PDT 24 |
| Peak memory | 565960 kb |
| Host | smart-71e8ffe7-2ff3-4cd5-84cf-55e863cff717 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4010809825 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 70.xbar_smoke.4010809825 |
| Directory | /workspace/70.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/70.xbar_smoke_large_delays.212553673 |
| Short name | T2494 |
| Test name | |
| Test status | |
| Simulation time | 8563943528 ps |
| CPU time | 95.72 seconds |
| Started | Jun 28 08:47:25 PM PDT 24 |
| Finished | Jun 28 08:49:25 PM PDT 24 |
| Peak memory | 566004 kb |
| Host | smart-8499f49a-b734-46be-8ef3-90caa934dbad |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=212553673 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 70.xbar_smoke_large_delays.212553673 |
| Directory | /workspace/70.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/70.xbar_smoke_slow_rsp.4206391923 |
| Short name | T2187 |
| Test name | |
| Test status | |
| Simulation time | 6288049817 ps |
| CPU time | 114.81 seconds |
| Started | Jun 28 08:47:29 PM PDT 24 |
| Finished | Jun 28 08:49:48 PM PDT 24 |
| Peak memory | 574256 kb |
| Host | smart-61890825-5033-4e88-b56e-114ff9ee3b35 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4206391923 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 70.xbar_smoke_slow_rsp.4206391923 |
| Directory | /workspace/70.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/70.xbar_smoke_zero_delays.1633576669 |
| Short name | T1641 |
| Test name | |
| Test status | |
| Simulation time | 41083117 ps |
| CPU time | 5.82 seconds |
| Started | Jun 28 08:47:25 PM PDT 24 |
| Finished | Jun 28 08:47:55 PM PDT 24 |
| Peak memory | 574100 kb |
| Host | smart-e02239ee-252b-4ca8-8209-7329b418c0dd |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1633576669 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 70.xbar_smoke_zero_delay s.1633576669 |
| Directory | /workspace/70.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/70.xbar_stress_all.1215248011 |
| Short name | T1993 |
| Test name | |
| Test status | |
| Simulation time | 9955743164 ps |
| CPU time | 426.32 seconds |
| Started | Jun 28 08:47:25 PM PDT 24 |
| Finished | Jun 28 08:54:55 PM PDT 24 |
| Peak memory | 575432 kb |
| Host | smart-152345f9-7aaa-43b2-8451-479413324c0e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1215248011 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 70.xbar_stress_all.1215248011 |
| Directory | /workspace/70.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/70.xbar_stress_all_with_error.1979455127 |
| Short name | T2251 |
| Test name | |
| Test status | |
| Simulation time | 6624773540 ps |
| CPU time | 211.61 seconds |
| Started | Jun 28 08:47:27 PM PDT 24 |
| Finished | Jun 28 08:51:22 PM PDT 24 |
| Peak memory | 574620 kb |
| Host | smart-704fcbae-2dad-4b2a-9d60-23ec01fc2d1e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1979455127 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 70.xbar_stress_all_with_error.1979455127 |
| Directory | /workspace/70.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/70.xbar_stress_all_with_rand_reset.2127509994 |
| Short name | T2133 |
| Test name | |
| Test status | |
| Simulation time | 716760498 ps |
| CPU time | 250.6 seconds |
| Started | Jun 28 08:47:28 PM PDT 24 |
| Finished | Jun 28 08:52:03 PM PDT 24 |
| Peak memory | 575408 kb |
| Host | smart-6cfde6b3-3cbe-4892-a985-3ad0e7ad6959 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2127509994 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 70.xbar_stress_all _with_rand_reset.2127509994 |
| Directory | /workspace/70.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/70.xbar_stress_all_with_reset_error.304406983 |
| Short name | T1926 |
| Test name | |
| Test status | |
| Simulation time | 2930353655 ps |
| CPU time | 218.75 seconds |
| Started | Jun 28 08:47:24 PM PDT 24 |
| Finished | Jun 28 08:51:28 PM PDT 24 |
| Peak memory | 574664 kb |
| Host | smart-1b3e33f1-0bb9-4e2d-ac20-b89b810ad0b2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=304406983 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 70.xbar_stress_all _with_reset_error.304406983 |
| Directory | /workspace/70.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/70.xbar_unmapped_addr.4051910426 |
| Short name | T2417 |
| Test name | |
| Test status | |
| Simulation time | 918763117 ps |
| CPU time | 42.59 seconds |
| Started | Jun 28 08:47:28 PM PDT 24 |
| Finished | Jun 28 08:48:35 PM PDT 24 |
| Peak memory | 574244 kb |
| Host | smart-9b3f6630-9d16-4c72-b862-11bc5587162e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4051910426 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 70.xbar_unmapped_addr.4051910426 |
| Directory | /workspace/70.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/71.xbar_access_same_device.336228834 |
| Short name | T1882 |
| Test name | |
| Test status | |
| Simulation time | 866744616 ps |
| CPU time | 76.05 seconds |
| Started | Jun 28 08:47:56 PM PDT 24 |
| Finished | Jun 28 08:49:34 PM PDT 24 |
| Peak memory | 575292 kb |
| Host | smart-632e6415-787b-4b8a-9992-ac5bd6d885a3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=336228834 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 71.xbar_access_same_device. 336228834 |
| Directory | /workspace/71.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/71.xbar_access_same_device_slow_rsp.1816027373 |
| Short name | T2844 |
| Test name | |
| Test status | |
| Simulation time | 125842805029 ps |
| CPU time | 2241.92 seconds |
| Started | Jun 28 08:47:58 PM PDT 24 |
| Finished | Jun 28 09:25:41 PM PDT 24 |
| Peak memory | 575436 kb |
| Host | smart-e4c6fdf5-8e50-457a-baa4-1d78e9b3be94 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1816027373 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 71.xbar_access_same_ device_slow_rsp.1816027373 |
| Directory | /workspace/71.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/71.xbar_error_and_unmapped_addr.2882275991 |
| Short name | T1349 |
| Test name | |
| Test status | |
| Simulation time | 310125168 ps |
| CPU time | 38.23 seconds |
| Started | Jun 28 08:47:59 PM PDT 24 |
| Finished | Jun 28 08:48:59 PM PDT 24 |
| Peak memory | 574360 kb |
| Host | smart-4063b3bf-d169-4d6f-a9aa-740cc6ea018b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2882275991 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 71.xbar_error_and_unmapped_add r.2882275991 |
| Directory | /workspace/71.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/71.xbar_error_random.1193530721 |
| Short name | T2495 |
| Test name | |
| Test status | |
| Simulation time | 1943087313 ps |
| CPU time | 69.63 seconds |
| Started | Jun 28 08:47:58 PM PDT 24 |
| Finished | Jun 28 08:49:29 PM PDT 24 |
| Peak memory | 574424 kb |
| Host | smart-e9ca7e09-93a5-4082-9497-939db0496cf8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1193530721 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 71.xbar_error_random.1193530721 |
| Directory | /workspace/71.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/71.xbar_random.227279391 |
| Short name | T589 |
| Test name | |
| Test status | |
| Simulation time | 200721007 ps |
| CPU time | 21.76 seconds |
| Started | Jun 28 08:48:00 PM PDT 24 |
| Finished | Jun 28 08:48:43 PM PDT 24 |
| Peak memory | 575220 kb |
| Host | smart-22f0cd31-902b-4133-b3a3-78e7ac97215e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=227279391 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 71.xbar_random.227279391 |
| Directory | /workspace/71.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/71.xbar_random_large_delays.4136059962 |
| Short name | T2067 |
| Test name | |
| Test status | |
| Simulation time | 49620812957 ps |
| CPU time | 536.93 seconds |
| Started | Jun 28 08:47:56 PM PDT 24 |
| Finished | Jun 28 08:57:15 PM PDT 24 |
| Peak memory | 575304 kb |
| Host | smart-2d08aeb0-42cf-47ca-b9f3-54dcc88a7521 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4136059962 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 71.xbar_random_large_delays.4136059962 |
| Directory | /workspace/71.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/71.xbar_random_slow_rsp.4052849713 |
| Short name | T562 |
| Test name | |
| Test status | |
| Simulation time | 57710721488 ps |
| CPU time | 974.01 seconds |
| Started | Jun 28 08:47:56 PM PDT 24 |
| Finished | Jun 28 09:04:32 PM PDT 24 |
| Peak memory | 575316 kb |
| Host | smart-f3af1554-0d59-4dca-970c-5db3e155968a |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4052849713 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 71.xbar_random_slow_rsp.4052849713 |
| Directory | /workspace/71.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/71.xbar_random_zero_delays.4156538926 |
| Short name | T2491 |
| Test name | |
| Test status | |
| Simulation time | 152951657 ps |
| CPU time | 17.04 seconds |
| Started | Jun 28 08:47:56 PM PDT 24 |
| Finished | Jun 28 08:48:35 PM PDT 24 |
| Peak memory | 575240 kb |
| Host | smart-77b31cdc-7b4e-4f47-a638-2503d996e81a |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4156538926 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 71.xbar_random_zero_del ays.4156538926 |
| Directory | /workspace/71.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/71.xbar_same_source.1705408194 |
| Short name | T1443 |
| Test name | |
| Test status | |
| Simulation time | 281378439 ps |
| CPU time | 22.17 seconds |
| Started | Jun 28 08:47:59 PM PDT 24 |
| Finished | Jun 28 08:48:43 PM PDT 24 |
| Peak memory | 575220 kb |
| Host | smart-fd116e60-af9e-44ed-9fe7-0fa8904520d9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1705408194 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 71.xbar_same_source.1705408194 |
| Directory | /workspace/71.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/71.xbar_smoke.996643673 |
| Short name | T2340 |
| Test name | |
| Test status | |
| Simulation time | 233041279 ps |
| CPU time | 10.77 seconds |
| Started | Jun 28 08:47:25 PM PDT 24 |
| Finished | Jun 28 08:48:00 PM PDT 24 |
| Peak memory | 574196 kb |
| Host | smart-7a87aabd-7f90-481c-aa80-90deadcccedc |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=996643673 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 71.xbar_smoke.996643673 |
| Directory | /workspace/71.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/71.xbar_smoke_large_delays.707535518 |
| Short name | T1775 |
| Test name | |
| Test status | |
| Simulation time | 8547637871 ps |
| CPU time | 92.8 seconds |
| Started | Jun 28 08:47:23 PM PDT 24 |
| Finished | Jun 28 08:49:21 PM PDT 24 |
| Peak memory | 566004 kb |
| Host | smart-79c7f88c-0c98-41db-a2cb-b36d45663a44 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=707535518 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 71.xbar_smoke_large_delays.707535518 |
| Directory | /workspace/71.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/71.xbar_smoke_slow_rsp.2522731200 |
| Short name | T2458 |
| Test name | |
| Test status | |
| Simulation time | 5326107907 ps |
| CPU time | 89.27 seconds |
| Started | Jun 28 08:47:23 PM PDT 24 |
| Finished | Jun 28 08:49:16 PM PDT 24 |
| Peak memory | 566012 kb |
| Host | smart-30f06ba7-41b8-47ed-884f-cbb3ad99f972 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2522731200 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 71.xbar_smoke_slow_rsp.2522731200 |
| Directory | /workspace/71.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/71.xbar_smoke_zero_delays.3860550066 |
| Short name | T1610 |
| Test name | |
| Test status | |
| Simulation time | 46733248 ps |
| CPU time | 6.5 seconds |
| Started | Jun 28 08:47:28 PM PDT 24 |
| Finished | Jun 28 08:47:59 PM PDT 24 |
| Peak memory | 574200 kb |
| Host | smart-aba934d1-fab4-460b-a301-97e91cea13f5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3860550066 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 71.xbar_smoke_zero_delay s.3860550066 |
| Directory | /workspace/71.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/71.xbar_stress_all.3946405392 |
| Short name | T1664 |
| Test name | |
| Test status | |
| Simulation time | 2623876898 ps |
| CPU time | 99.11 seconds |
| Started | Jun 28 08:47:59 PM PDT 24 |
| Finished | Jun 28 08:50:00 PM PDT 24 |
| Peak memory | 575420 kb |
| Host | smart-25502ecc-0b25-45d0-a06c-5657df164200 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3946405392 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 71.xbar_stress_all.3946405392 |
| Directory | /workspace/71.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/71.xbar_stress_all_with_error.2463142100 |
| Short name | T1879 |
| Test name | |
| Test status | |
| Simulation time | 5055772652 ps |
| CPU time | 195.08 seconds |
| Started | Jun 28 08:48:00 PM PDT 24 |
| Finished | Jun 28 08:51:38 PM PDT 24 |
| Peak memory | 574284 kb |
| Host | smart-ed749390-da38-44c3-80a6-7eda71a84c47 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2463142100 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 71.xbar_stress_all_with_error.2463142100 |
| Directory | /workspace/71.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/71.xbar_stress_all_with_rand_reset.2413678404 |
| Short name | T610 |
| Test name | |
| Test status | |
| Simulation time | 887356885 ps |
| CPU time | 209.08 seconds |
| Started | Jun 28 08:48:02 PM PDT 24 |
| Finished | Jun 28 08:51:52 PM PDT 24 |
| Peak memory | 575392 kb |
| Host | smart-62507b6b-ef44-4701-bb04-97426eecafbc |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2413678404 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 71.xbar_stress_all _with_rand_reset.2413678404 |
| Directory | /workspace/71.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/71.xbar_stress_all_with_reset_error.995809414 |
| Short name | T815 |
| Test name | |
| Test status | |
| Simulation time | 3221852483 ps |
| CPU time | 442.61 seconds |
| Started | Jun 28 08:47:59 PM PDT 24 |
| Finished | Jun 28 08:55:44 PM PDT 24 |
| Peak memory | 576300 kb |
| Host | smart-908188ba-b038-4ad5-91e0-7cd904c00552 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=995809414 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 71.xbar_stress_all _with_reset_error.995809414 |
| Directory | /workspace/71.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/71.xbar_unmapped_addr.3503997203 |
| Short name | T1915 |
| Test name | |
| Test status | |
| Simulation time | 141986294 ps |
| CPU time | 19.2 seconds |
| Started | Jun 28 08:47:56 PM PDT 24 |
| Finished | Jun 28 08:48:37 PM PDT 24 |
| Peak memory | 574212 kb |
| Host | smart-a67dc902-e92b-4e7f-9ca6-08cbf4e0a18a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3503997203 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 71.xbar_unmapped_addr.3503997203 |
| Directory | /workspace/71.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/72.xbar_access_same_device.353104843 |
| Short name | T2202 |
| Test name | |
| Test status | |
| Simulation time | 254533572 ps |
| CPU time | 25.67 seconds |
| Started | Jun 28 08:47:56 PM PDT 24 |
| Finished | Jun 28 08:48:43 PM PDT 24 |
| Peak memory | 575256 kb |
| Host | smart-adcacb2b-f58a-4325-90cc-969de9eb8c51 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=353104843 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 72.xbar_access_same_device. 353104843 |
| Directory | /workspace/72.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/72.xbar_access_same_device_slow_rsp.969086266 |
| Short name | T2707 |
| Test name | |
| Test status | |
| Simulation time | 65479977118 ps |
| CPU time | 1149.93 seconds |
| Started | Jun 28 08:47:56 PM PDT 24 |
| Finished | Jun 28 09:07:27 PM PDT 24 |
| Peak memory | 575408 kb |
| Host | smart-eae16179-d0c9-43f8-b81d-71ecf551216b |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=969086266 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 72.xbar_access_same_d evice_slow_rsp.969086266 |
| Directory | /workspace/72.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/72.xbar_error_and_unmapped_addr.2371938731 |
| Short name | T1584 |
| Test name | |
| Test status | |
| Simulation time | 76650629 ps |
| CPU time | 6.59 seconds |
| Started | Jun 28 08:47:59 PM PDT 24 |
| Finished | Jun 28 08:48:28 PM PDT 24 |
| Peak memory | 565972 kb |
| Host | smart-27dbaf13-dffe-48f9-9c52-c3a2ec271c18 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2371938731 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 72.xbar_error_and_unmapped_add r.2371938731 |
| Directory | /workspace/72.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/72.xbar_error_random.2166960957 |
| Short name | T2705 |
| Test name | |
| Test status | |
| Simulation time | 35112181 ps |
| CPU time | 6.27 seconds |
| Started | Jun 28 08:47:59 PM PDT 24 |
| Finished | Jun 28 08:48:28 PM PDT 24 |
| Peak memory | 573904 kb |
| Host | smart-1c91452b-c6c7-455c-a3fe-77b8d6e65298 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2166960957 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 72.xbar_error_random.2166960957 |
| Directory | /workspace/72.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/72.xbar_random.3782979988 |
| Short name | T1992 |
| Test name | |
| Test status | |
| Simulation time | 834090521 ps |
| CPU time | 30.18 seconds |
| Started | Jun 28 08:48:00 PM PDT 24 |
| Finished | Jun 28 08:48:53 PM PDT 24 |
| Peak memory | 575272 kb |
| Host | smart-22ec6d95-51f7-4af5-a86a-b1bb5b61c24b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3782979988 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 72.xbar_random.3782979988 |
| Directory | /workspace/72.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/72.xbar_random_large_delays.2200009610 |
| Short name | T1456 |
| Test name | |
| Test status | |
| Simulation time | 106567914669 ps |
| CPU time | 1179.91 seconds |
| Started | Jun 28 08:47:55 PM PDT 24 |
| Finished | Jun 28 09:07:57 PM PDT 24 |
| Peak memory | 575408 kb |
| Host | smart-6ba44bcb-077c-49ac-bada-feb3483f423d |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2200009610 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 72.xbar_random_large_delays.2200009610 |
| Directory | /workspace/72.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/72.xbar_random_slow_rsp.1338372355 |
| Short name | T2303 |
| Test name | |
| Test status | |
| Simulation time | 63381120111 ps |
| CPU time | 1140.89 seconds |
| Started | Jun 28 08:47:56 PM PDT 24 |
| Finished | Jun 28 09:07:19 PM PDT 24 |
| Peak memory | 574256 kb |
| Host | smart-004f0dbf-21da-4870-ab46-8fcd95e33d8c |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1338372355 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 72.xbar_random_slow_rsp.1338372355 |
| Directory | /workspace/72.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/72.xbar_random_zero_delays.4255344638 |
| Short name | T2013 |
| Test name | |
| Test status | |
| Simulation time | 195821904 ps |
| CPU time | 18.5 seconds |
| Started | Jun 28 08:47:59 PM PDT 24 |
| Finished | Jun 28 08:48:39 PM PDT 24 |
| Peak memory | 574164 kb |
| Host | smart-43022dda-c0a0-4786-9879-9377edda57ef |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4255344638 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 72.xbar_random_zero_del ays.4255344638 |
| Directory | /workspace/72.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/72.xbar_same_source.893894484 |
| Short name | T2825 |
| Test name | |
| Test status | |
| Simulation time | 435814348 ps |
| CPU time | 32.31 seconds |
| Started | Jun 28 08:47:58 PM PDT 24 |
| Finished | Jun 28 08:48:52 PM PDT 24 |
| Peak memory | 575204 kb |
| Host | smart-a2b1fccc-c928-4338-9d7b-9983650d02cf |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=893894484 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 72.xbar_same_source.893894484 |
| Directory | /workspace/72.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/72.xbar_smoke.4101416548 |
| Short name | T2346 |
| Test name | |
| Test status | |
| Simulation time | 225305812 ps |
| CPU time | 9.58 seconds |
| Started | Jun 28 08:48:01 PM PDT 24 |
| Finished | Jun 28 08:48:33 PM PDT 24 |
| Peak memory | 565960 kb |
| Host | smart-306741b2-2b22-48be-9728-46ddc6fb4097 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4101416548 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 72.xbar_smoke.4101416548 |
| Directory | /workspace/72.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/72.xbar_smoke_large_delays.2345355529 |
| Short name | T1377 |
| Test name | |
| Test status | |
| Simulation time | 8410301521 ps |
| CPU time | 87.65 seconds |
| Started | Jun 28 08:47:59 PM PDT 24 |
| Finished | Jun 28 08:49:47 PM PDT 24 |
| Peak memory | 574264 kb |
| Host | smart-26292504-27cf-474a-ae76-77721a336d1d |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2345355529 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 72.xbar_smoke_large_delays.2345355529 |
| Directory | /workspace/72.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/72.xbar_smoke_slow_rsp.858193441 |
| Short name | T2479 |
| Test name | |
| Test status | |
| Simulation time | 7170589917 ps |
| CPU time | 127.23 seconds |
| Started | Jun 28 08:48:01 PM PDT 24 |
| Finished | Jun 28 08:50:30 PM PDT 24 |
| Peak memory | 574260 kb |
| Host | smart-907bdcf3-b840-44b1-a733-1105d14ed5d0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=858193441 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 72.xbar_smoke_slow_rsp.858193441 |
| Directory | /workspace/72.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/72.xbar_smoke_zero_delays.1495227093 |
| Short name | T2879 |
| Test name | |
| Test status | |
| Simulation time | 46852070 ps |
| CPU time | 6.63 seconds |
| Started | Jun 28 08:47:58 PM PDT 24 |
| Finished | Jun 28 08:48:26 PM PDT 24 |
| Peak memory | 574180 kb |
| Host | smart-3004798f-8a22-4855-b9f1-602c7551a15c |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1495227093 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 72.xbar_smoke_zero_delay s.1495227093 |
| Directory | /workspace/72.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/72.xbar_stress_all_with_error.1271666477 |
| Short name | T2626 |
| Test name | |
| Test status | |
| Simulation time | 3649820008 ps |
| CPU time | 304.43 seconds |
| Started | Jun 28 08:48:00 PM PDT 24 |
| Finished | Jun 28 08:53:27 PM PDT 24 |
| Peak memory | 574344 kb |
| Host | smart-24ec98ad-8e64-4242-bbf5-a23180c5e61d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1271666477 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 72.xbar_stress_all_with_error.1271666477 |
| Directory | /workspace/72.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/72.xbar_stress_all_with_rand_reset.110574320 |
| Short name | T457 |
| Test name | |
| Test status | |
| Simulation time | 9624492198 ps |
| CPU time | 533.6 seconds |
| Started | Jun 28 08:47:59 PM PDT 24 |
| Finished | Jun 28 08:57:13 PM PDT 24 |
| Peak memory | 575452 kb |
| Host | smart-2fe12dd6-6c10-4156-bb60-4d180e463a97 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=110574320 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_res et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 72.xbar_stress_all_ with_rand_reset.110574320 |
| Directory | /workspace/72.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/72.xbar_stress_all_with_reset_error.1882972283 |
| Short name | T2769 |
| Test name | |
| Test status | |
| Simulation time | 5695878409 ps |
| CPU time | 244.97 seconds |
| Started | Jun 28 08:47:59 PM PDT 24 |
| Finished | Jun 28 08:52:26 PM PDT 24 |
| Peak memory | 574368 kb |
| Host | smart-61393c15-55e1-430f-b794-d9d080de40df |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1882972283 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 72.xbar_stress_al l_with_reset_error.1882972283 |
| Directory | /workspace/72.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/72.xbar_unmapped_addr.56824192 |
| Short name | T1465 |
| Test name | |
| Test status | |
| Simulation time | 467121632 ps |
| CPU time | 23.71 seconds |
| Started | Jun 28 08:47:57 PM PDT 24 |
| Finished | Jun 28 08:48:43 PM PDT 24 |
| Peak memory | 575204 kb |
| Host | smart-67f246c4-5c23-4083-a37a-417d3907a7f8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56824192 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 72.xbar_unmapped_addr.56824192 |
| Directory | /workspace/72.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/73.xbar_access_same_device.3750333289 |
| Short name | T620 |
| Test name | |
| Test status | |
| Simulation time | 1079004751 ps |
| CPU time | 80.66 seconds |
| Started | Jun 28 08:48:00 PM PDT 24 |
| Finished | Jun 28 08:49:43 PM PDT 24 |
| Peak memory | 574228 kb |
| Host | smart-6ccb2eed-ba67-4f88-8481-68a1881d5c0b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3750333289 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 73.xbar_access_same_device .3750333289 |
| Directory | /workspace/73.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/73.xbar_access_same_device_slow_rsp.2242883699 |
| Short name | T1625 |
| Test name | |
| Test status | |
| Simulation time | 137157412168 ps |
| CPU time | 2495.65 seconds |
| Started | Jun 28 08:48:01 PM PDT 24 |
| Finished | Jun 28 09:29:59 PM PDT 24 |
| Peak memory | 574176 kb |
| Host | smart-cca53d1d-3c91-4465-bb3d-a1dc11d4504a |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2242883699 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 73.xbar_access_same_ device_slow_rsp.2242883699 |
| Directory | /workspace/73.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/73.xbar_error_and_unmapped_addr.1490256703 |
| Short name | T2094 |
| Test name | |
| Test status | |
| Simulation time | 1180420505 ps |
| CPU time | 46.98 seconds |
| Started | Jun 28 08:48:00 PM PDT 24 |
| Finished | Jun 28 08:49:09 PM PDT 24 |
| Peak memory | 574432 kb |
| Host | smart-2869f344-a701-4d5f-beff-2cdcee190336 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1490256703 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 73.xbar_error_and_unmapped_add r.1490256703 |
| Directory | /workspace/73.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/73.xbar_error_random.2414744311 |
| Short name | T1721 |
| Test name | |
| Test status | |
| Simulation time | 936574769 ps |
| CPU time | 36.16 seconds |
| Started | Jun 28 08:47:56 PM PDT 24 |
| Finished | Jun 28 08:48:54 PM PDT 24 |
| Peak memory | 573956 kb |
| Host | smart-7379984f-ebba-4d93-8704-cea42ff0a442 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2414744311 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 73.xbar_error_random.2414744311 |
| Directory | /workspace/73.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/73.xbar_random.3603814431 |
| Short name | T2352 |
| Test name | |
| Test status | |
| Simulation time | 1933602241 ps |
| CPU time | 70.48 seconds |
| Started | Jun 28 08:47:56 PM PDT 24 |
| Finished | Jun 28 08:49:28 PM PDT 24 |
| Peak memory | 575240 kb |
| Host | smart-0e53ad9e-03b3-404d-94dd-45f3370ce163 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3603814431 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 73.xbar_random.3603814431 |
| Directory | /workspace/73.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/73.xbar_random_large_delays.2546067156 |
| Short name | T2611 |
| Test name | |
| Test status | |
| Simulation time | 69834500660 ps |
| CPU time | 710.16 seconds |
| Started | Jun 28 08:47:58 PM PDT 24 |
| Finished | Jun 28 09:00:09 PM PDT 24 |
| Peak memory | 575340 kb |
| Host | smart-7d32c987-1ff1-4a5d-b1c5-44a0a1fba5e1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2546067156 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 73.xbar_random_large_delays.2546067156 |
| Directory | /workspace/73.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/73.xbar_random_slow_rsp.1357424459 |
| Short name | T1596 |
| Test name | |
| Test status | |
| Simulation time | 43543283457 ps |
| CPU time | 732.61 seconds |
| Started | Jun 28 08:47:58 PM PDT 24 |
| Finished | Jun 28 09:00:32 PM PDT 24 |
| Peak memory | 575328 kb |
| Host | smart-4a46b86b-96bd-4cb6-9503-86907d0c31fa |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1357424459 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 73.xbar_random_slow_rsp.1357424459 |
| Directory | /workspace/73.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/73.xbar_random_zero_delays.2702621777 |
| Short name | T2032 |
| Test name | |
| Test status | |
| Simulation time | 155576724 ps |
| CPU time | 17.49 seconds |
| Started | Jun 28 08:48:01 PM PDT 24 |
| Finished | Jun 28 08:48:40 PM PDT 24 |
| Peak memory | 575248 kb |
| Host | smart-88ee657b-553a-462a-8903-8c6211ec7bb7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2702621777 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 73.xbar_random_zero_del ays.2702621777 |
| Directory | /workspace/73.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/73.xbar_same_source.3687138516 |
| Short name | T1777 |
| Test name | |
| Test status | |
| Simulation time | 2768955388 ps |
| CPU time | 92.91 seconds |
| Started | Jun 28 08:48:01 PM PDT 24 |
| Finished | Jun 28 08:49:56 PM PDT 24 |
| Peak memory | 574228 kb |
| Host | smart-5a4f1f44-30df-4302-b6d2-465935f4e490 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3687138516 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 73.xbar_same_source.3687138516 |
| Directory | /workspace/73.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/73.xbar_smoke.91305042 |
| Short name | T2570 |
| Test name | |
| Test status | |
| Simulation time | 187969500 ps |
| CPU time | 9.66 seconds |
| Started | Jun 28 08:47:56 PM PDT 24 |
| Finished | Jun 28 08:48:28 PM PDT 24 |
| Peak memory | 574164 kb |
| Host | smart-3d32e198-f2ed-4858-9b38-c63973be8780 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=91305042 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 73.xbar_smoke.91305042 |
| Directory | /workspace/73.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/73.xbar_smoke_large_delays.4219304528 |
| Short name | T2840 |
| Test name | |
| Test status | |
| Simulation time | 7300286836 ps |
| CPU time | 73.95 seconds |
| Started | Jun 28 08:47:58 PM PDT 24 |
| Finished | Jun 28 08:49:33 PM PDT 24 |
| Peak memory | 574252 kb |
| Host | smart-62d69858-3c64-41f1-978b-a3732856f18f |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4219304528 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 73.xbar_smoke_large_delays.4219304528 |
| Directory | /workspace/73.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/73.xbar_smoke_slow_rsp.516462528 |
| Short name | T2215 |
| Test name | |
| Test status | |
| Simulation time | 4465209005 ps |
| CPU time | 77.21 seconds |
| Started | Jun 28 08:47:58 PM PDT 24 |
| Finished | Jun 28 08:49:36 PM PDT 24 |
| Peak memory | 574128 kb |
| Host | smart-c0095a4d-b7a3-40ff-a463-dc33394844da |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=516462528 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 73.xbar_smoke_slow_rsp.516462528 |
| Directory | /workspace/73.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/73.xbar_smoke_zero_delays.2905788896 |
| Short name | T1914 |
| Test name | |
| Test status | |
| Simulation time | 44287759 ps |
| CPU time | 5.83 seconds |
| Started | Jun 28 08:47:58 PM PDT 24 |
| Finished | Jun 28 08:48:25 PM PDT 24 |
| Peak memory | 565888 kb |
| Host | smart-eb4a277e-d138-45d5-a6b0-1890580faf51 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2905788896 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 73.xbar_smoke_zero_delay s.2905788896 |
| Directory | /workspace/73.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/73.xbar_stress_all.1684484423 |
| Short name | T2801 |
| Test name | |
| Test status | |
| Simulation time | 3791827211 ps |
| CPU time | 161.71 seconds |
| Started | Jun 28 08:47:59 PM PDT 24 |
| Finished | Jun 28 08:51:03 PM PDT 24 |
| Peak memory | 575444 kb |
| Host | smart-6d8769cb-2ba9-4361-bdaa-c5bda5b2c91f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1684484423 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 73.xbar_stress_all.1684484423 |
| Directory | /workspace/73.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/73.xbar_stress_all_with_rand_reset.4251415213 |
| Short name | T1850 |
| Test name | |
| Test status | |
| Simulation time | 12255104735 ps |
| CPU time | 627.56 seconds |
| Started | Jun 28 08:48:03 PM PDT 24 |
| Finished | Jun 28 08:58:52 PM PDT 24 |
| Peak memory | 575448 kb |
| Host | smart-1445d9c2-6edd-4346-ba64-50d1270ce343 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4251415213 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 73.xbar_stress_all _with_rand_reset.4251415213 |
| Directory | /workspace/73.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/73.xbar_stress_all_with_reset_error.3890416219 |
| Short name | T2781 |
| Test name | |
| Test status | |
| Simulation time | 1374456452 ps |
| CPU time | 201.57 seconds |
| Started | Jun 28 08:48:02 PM PDT 24 |
| Finished | Jun 28 08:51:46 PM PDT 24 |
| Peak memory | 576376 kb |
| Host | smart-93776ca6-5198-4c84-89dc-c6cd065d8997 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3890416219 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 73.xbar_stress_al l_with_reset_error.3890416219 |
| Directory | /workspace/73.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/73.xbar_unmapped_addr.1612986353 |
| Short name | T1787 |
| Test name | |
| Test status | |
| Simulation time | 240436289 ps |
| CPU time | 28.82 seconds |
| Started | Jun 28 08:48:00 PM PDT 24 |
| Finished | Jun 28 08:48:50 PM PDT 24 |
| Peak memory | 575288 kb |
| Host | smart-7e570838-0ee6-4f58-919b-6270cb968467 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1612986353 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 73.xbar_unmapped_addr.1612986353 |
| Directory | /workspace/73.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/74.xbar_access_same_device.1258993503 |
| Short name | T2663 |
| Test name | |
| Test status | |
| Simulation time | 1947296609 ps |
| CPU time | 86.81 seconds |
| Started | Jun 28 08:48:03 PM PDT 24 |
| Finished | Jun 28 08:49:52 PM PDT 24 |
| Peak memory | 575200 kb |
| Host | smart-bf9b170d-21a7-49a5-a2e1-d4a9da6099c7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1258993503 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 74.xbar_access_same_device .1258993503 |
| Directory | /workspace/74.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/74.xbar_access_same_device_slow_rsp.1569372841 |
| Short name | T2428 |
| Test name | |
| Test status | |
| Simulation time | 95986547706 ps |
| CPU time | 1818.9 seconds |
| Started | Jun 28 08:47:57 PM PDT 24 |
| Finished | Jun 28 09:18:38 PM PDT 24 |
| Peak memory | 574340 kb |
| Host | smart-0d79e316-db64-4421-aafb-91beabce628f |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1569372841 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 74.xbar_access_same_ device_slow_rsp.1569372841 |
| Directory | /workspace/74.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/74.xbar_error_and_unmapped_addr.2577835667 |
| Short name | T1750 |
| Test name | |
| Test status | |
| Simulation time | 554394899 ps |
| CPU time | 25.99 seconds |
| Started | Jun 28 08:48:19 PM PDT 24 |
| Finished | Jun 28 08:49:01 PM PDT 24 |
| Peak memory | 574204 kb |
| Host | smart-3c8af6ab-6ddb-4c03-a5cc-782766182964 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2577835667 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 74.xbar_error_and_unmapped_add r.2577835667 |
| Directory | /workspace/74.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/74.xbar_error_random.2924805723 |
| Short name | T2614 |
| Test name | |
| Test status | |
| Simulation time | 565797021 ps |
| CPU time | 57.42 seconds |
| Started | Jun 28 08:48:00 PM PDT 24 |
| Finished | Jun 28 08:49:20 PM PDT 24 |
| Peak memory | 574144 kb |
| Host | smart-b1dc1860-84a3-4a66-8f2c-66630bf058be |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2924805723 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 74.xbar_error_random.2924805723 |
| Directory | /workspace/74.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/74.xbar_random.3006547963 |
| Short name | T2335 |
| Test name | |
| Test status | |
| Simulation time | 513218803 ps |
| CPU time | 48.52 seconds |
| Started | Jun 28 08:48:06 PM PDT 24 |
| Finished | Jun 28 08:49:15 PM PDT 24 |
| Peak memory | 575288 kb |
| Host | smart-989f1a4a-58aa-4cd8-b55e-12f47039d934 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3006547963 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 74.xbar_random.3006547963 |
| Directory | /workspace/74.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/74.xbar_random_large_delays.4131701102 |
| Short name | T1468 |
| Test name | |
| Test status | |
| Simulation time | 79672096490 ps |
| CPU time | 834.01 seconds |
| Started | Jun 28 08:48:06 PM PDT 24 |
| Finished | Jun 28 09:02:20 PM PDT 24 |
| Peak memory | 574260 kb |
| Host | smart-afef7a48-31ec-442e-8f68-571fb401a14d |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4131701102 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 74.xbar_random_large_delays.4131701102 |
| Directory | /workspace/74.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/74.xbar_random_slow_rsp.121950382 |
| Short name | T2210 |
| Test name | |
| Test status | |
| Simulation time | 13153161683 ps |
| CPU time | 229.98 seconds |
| Started | Jun 28 08:48:03 PM PDT 24 |
| Finished | Jun 28 08:52:15 PM PDT 24 |
| Peak memory | 574228 kb |
| Host | smart-9231b861-45b0-44ea-8558-b6628181d8fd |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=121950382 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 74.xbar_random_slow_rsp.121950382 |
| Directory | /workspace/74.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/74.xbar_random_zero_delays.2815390039 |
| Short name | T451 |
| Test name | |
| Test status | |
| Simulation time | 334408977 ps |
| CPU time | 35.06 seconds |
| Started | Jun 28 08:48:04 PM PDT 24 |
| Finished | Jun 28 08:49:00 PM PDT 24 |
| Peak memory | 574188 kb |
| Host | smart-f18684b6-7467-4409-97ae-14394a435b64 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2815390039 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 74.xbar_random_zero_del ays.2815390039 |
| Directory | /workspace/74.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/74.xbar_same_source.859902488 |
| Short name | T2125 |
| Test name | |
| Test status | |
| Simulation time | 333173282 ps |
| CPU time | 27.31 seconds |
| Started | Jun 28 08:48:07 PM PDT 24 |
| Finished | Jun 28 08:48:53 PM PDT 24 |
| Peak memory | 575232 kb |
| Host | smart-4a92b680-d8a5-412d-9786-b2872784d910 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=859902488 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 74.xbar_same_source.859902488 |
| Directory | /workspace/74.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/74.xbar_smoke.907272171 |
| Short name | T1847 |
| Test name | |
| Test status | |
| Simulation time | 158171110 ps |
| CPU time | 8.43 seconds |
| Started | Jun 28 08:48:01 PM PDT 24 |
| Finished | Jun 28 08:48:31 PM PDT 24 |
| Peak memory | 574172 kb |
| Host | smart-7cf9a1cd-4666-4b80-9631-8ad2f899d690 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=907272171 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 74.xbar_smoke.907272171 |
| Directory | /workspace/74.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/74.xbar_smoke_large_delays.2060103466 |
| Short name | T1929 |
| Test name | |
| Test status | |
| Simulation time | 6726508106 ps |
| CPU time | 73.75 seconds |
| Started | Jun 28 08:48:01 PM PDT 24 |
| Finished | Jun 28 08:49:37 PM PDT 24 |
| Peak memory | 566004 kb |
| Host | smart-0d8cb63d-e2cd-483b-900b-d41fe7e36a5d |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2060103466 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 74.xbar_smoke_large_delays.2060103466 |
| Directory | /workspace/74.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/74.xbar_smoke_slow_rsp.696239125 |
| Short name | T1352 |
| Test name | |
| Test status | |
| Simulation time | 4304368683 ps |
| CPU time | 76.8 seconds |
| Started | Jun 28 08:48:01 PM PDT 24 |
| Finished | Jun 28 08:49:40 PM PDT 24 |
| Peak memory | 574240 kb |
| Host | smart-f33cc396-0255-443d-9d15-c801a9f1dc6a |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=696239125 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 74.xbar_smoke_slow_rsp.696239125 |
| Directory | /workspace/74.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/74.xbar_smoke_zero_delays.1405573818 |
| Short name | T527 |
| Test name | |
| Test status | |
| Simulation time | 54248896 ps |
| CPU time | 6.67 seconds |
| Started | Jun 28 08:48:00 PM PDT 24 |
| Finished | Jun 28 08:48:29 PM PDT 24 |
| Peak memory | 574180 kb |
| Host | smart-96044d4b-f33a-4631-bd22-01c56202fb80 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1405573818 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 74.xbar_smoke_zero_delay s.1405573818 |
| Directory | /workspace/74.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/74.xbar_stress_all.3286331685 |
| Short name | T1859 |
| Test name | |
| Test status | |
| Simulation time | 1364245478 ps |
| CPU time | 56.71 seconds |
| Started | Jun 28 08:48:24 PM PDT 24 |
| Finished | Jun 28 08:49:37 PM PDT 24 |
| Peak memory | 575376 kb |
| Host | smart-0b6469c6-36f7-4494-9500-ed82a5ded842 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3286331685 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 74.xbar_stress_all.3286331685 |
| Directory | /workspace/74.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/74.xbar_stress_all_with_error.781318818 |
| Short name | T1626 |
| Test name | |
| Test status | |
| Simulation time | 15046143004 ps |
| CPU time | 552.79 seconds |
| Started | Jun 28 08:48:25 PM PDT 24 |
| Finished | Jun 28 08:57:54 PM PDT 24 |
| Peak memory | 574612 kb |
| Host | smart-662187ee-0c41-4a13-8d77-148e514cf3bc |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=781318818 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 74.xbar_stress_all_with_error.781318818 |
| Directory | /workspace/74.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/74.xbar_stress_all_with_rand_reset.729258349 |
| Short name | T2319 |
| Test name | |
| Test status | |
| Simulation time | 8024849057 ps |
| CPU time | 624.05 seconds |
| Started | Jun 28 08:48:20 PM PDT 24 |
| Finished | Jun 28 08:59:01 PM PDT 24 |
| Peak memory | 575464 kb |
| Host | smart-8ec47dab-3308-468f-9322-282a6c8a1ae4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=729258349 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_res et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 74.xbar_stress_all_ with_rand_reset.729258349 |
| Directory | /workspace/74.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/74.xbar_stress_all_with_reset_error.3629829128 |
| Short name | T2658 |
| Test name | |
| Test status | |
| Simulation time | 4788121684 ps |
| CPU time | 470.19 seconds |
| Started | Jun 28 08:48:29 PM PDT 24 |
| Finished | Jun 28 08:56:34 PM PDT 24 |
| Peak memory | 574668 kb |
| Host | smart-c5a473dd-de30-4074-b091-ba0f00acecad |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3629829128 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 74.xbar_stress_al l_with_reset_error.3629829128 |
| Directory | /workspace/74.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/74.xbar_unmapped_addr.1772755696 |
| Short name | T593 |
| Test name | |
| Test status | |
| Simulation time | 293930388 ps |
| CPU time | 36.14 seconds |
| Started | Jun 28 08:48:01 PM PDT 24 |
| Finished | Jun 28 08:48:59 PM PDT 24 |
| Peak memory | 575308 kb |
| Host | smart-422cd2af-0abe-49ef-8d61-c87bea256b48 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1772755696 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 74.xbar_unmapped_addr.1772755696 |
| Directory | /workspace/74.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/75.xbar_access_same_device.509675467 |
| Short name | T462 |
| Test name | |
| Test status | |
| Simulation time | 402883334 ps |
| CPU time | 39.23 seconds |
| Started | Jun 28 08:48:32 PM PDT 24 |
| Finished | Jun 28 08:49:28 PM PDT 24 |
| Peak memory | 575232 kb |
| Host | smart-8ab2a5c9-d4d7-4468-b7e6-f1843a67fe72 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=509675467 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 75.xbar_access_same_device. 509675467 |
| Directory | /workspace/75.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/75.xbar_error_and_unmapped_addr.557394678 |
| Short name | T1592 |
| Test name | |
| Test status | |
| Simulation time | 313595929 ps |
| CPU time | 15.95 seconds |
| Started | Jun 28 08:48:18 PM PDT 24 |
| Finished | Jun 28 08:48:51 PM PDT 24 |
| Peak memory | 574432 kb |
| Host | smart-aa580da5-4fc6-4ea4-a2ad-ded80bd12a3b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=557394678 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 75.xbar_error_and_unmapped_addr .557394678 |
| Directory | /workspace/75.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/75.xbar_error_random.2659651290 |
| Short name | T2139 |
| Test name | |
| Test status | |
| Simulation time | 179260214 ps |
| CPU time | 18.64 seconds |
| Started | Jun 28 08:48:30 PM PDT 24 |
| Finished | Jun 28 08:49:03 PM PDT 24 |
| Peak memory | 573796 kb |
| Host | smart-909c6017-147c-4634-99fb-c05b34eafdf1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2659651290 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 75.xbar_error_random.2659651290 |
| Directory | /workspace/75.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/75.xbar_random.2468381133 |
| Short name | T2697 |
| Test name | |
| Test status | |
| Simulation time | 1648972910 ps |
| CPU time | 60.95 seconds |
| Started | Jun 28 08:48:19 PM PDT 24 |
| Finished | Jun 28 08:49:38 PM PDT 24 |
| Peak memory | 574168 kb |
| Host | smart-8ca15251-f629-4220-9f62-3ffc19b46f63 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2468381133 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 75.xbar_random.2468381133 |
| Directory | /workspace/75.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/75.xbar_random_large_delays.2051875377 |
| Short name | T1361 |
| Test name | |
| Test status | |
| Simulation time | 8717655634 ps |
| CPU time | 99.15 seconds |
| Started | Jun 28 08:48:25 PM PDT 24 |
| Finished | Jun 28 08:50:20 PM PDT 24 |
| Peak memory | 574320 kb |
| Host | smart-d5bb8173-07a8-48fc-909f-79b78e116e25 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2051875377 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 75.xbar_random_large_delays.2051875377 |
| Directory | /workspace/75.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/75.xbar_random_slow_rsp.3888241361 |
| Short name | T1534 |
| Test name | |
| Test status | |
| Simulation time | 17983974248 ps |
| CPU time | 327.97 seconds |
| Started | Jun 28 08:48:19 PM PDT 24 |
| Finished | Jun 28 08:54:03 PM PDT 24 |
| Peak memory | 575324 kb |
| Host | smart-e6960edc-a0b6-4313-81cf-eb76ffb5a2c9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3888241361 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 75.xbar_random_slow_rsp.3888241361 |
| Directory | /workspace/75.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/75.xbar_random_zero_delays.3979171556 |
| Short name | T2641 |
| Test name | |
| Test status | |
| Simulation time | 532135174 ps |
| CPU time | 51.77 seconds |
| Started | Jun 28 08:48:21 PM PDT 24 |
| Finished | Jun 28 08:49:30 PM PDT 24 |
| Peak memory | 574204 kb |
| Host | smart-c930847e-ee8e-474f-a727-24029d1f1b31 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3979171556 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 75.xbar_random_zero_del ays.3979171556 |
| Directory | /workspace/75.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/75.xbar_same_source.1641034682 |
| Short name | T2777 |
| Test name | |
| Test status | |
| Simulation time | 277174637 ps |
| CPU time | 22.6 seconds |
| Started | Jun 28 08:48:23 PM PDT 24 |
| Finished | Jun 28 08:49:02 PM PDT 24 |
| Peak memory | 575236 kb |
| Host | smart-c4a3a4db-f710-4dfe-9795-361cf5c6984a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1641034682 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 75.xbar_same_source.1641034682 |
| Directory | /workspace/75.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/75.xbar_smoke.1623268964 |
| Short name | T1654 |
| Test name | |
| Test status | |
| Simulation time | 43358925 ps |
| CPU time | 5.82 seconds |
| Started | Jun 28 08:48:29 PM PDT 24 |
| Finished | Jun 28 08:48:50 PM PDT 24 |
| Peak memory | 574196 kb |
| Host | smart-c406c585-038c-45ea-8a8f-08792aeb9208 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1623268964 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 75.xbar_smoke.1623268964 |
| Directory | /workspace/75.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/75.xbar_smoke_large_delays.3978529399 |
| Short name | T2655 |
| Test name | |
| Test status | |
| Simulation time | 4980583417 ps |
| CPU time | 52.97 seconds |
| Started | Jun 28 08:48:18 PM PDT 24 |
| Finished | Jun 28 08:49:28 PM PDT 24 |
| Peak memory | 574088 kb |
| Host | smart-c4666f53-5042-4a19-8c58-c29f9b2567b8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3978529399 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 75.xbar_smoke_large_delays.3978529399 |
| Directory | /workspace/75.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/75.xbar_smoke_slow_rsp.262271977 |
| Short name | T1478 |
| Test name | |
| Test status | |
| Simulation time | 4647039404 ps |
| CPU time | 82.48 seconds |
| Started | Jun 28 08:48:32 PM PDT 24 |
| Finished | Jun 28 08:50:11 PM PDT 24 |
| Peak memory | 574148 kb |
| Host | smart-bd4841f4-022d-4981-b2f2-a11dc037b1d6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=262271977 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 75.xbar_smoke_slow_rsp.262271977 |
| Directory | /workspace/75.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/75.xbar_smoke_zero_delays.2143228954 |
| Short name | T1554 |
| Test name | |
| Test status | |
| Simulation time | 46139376 ps |
| CPU time | 6.06 seconds |
| Started | Jun 28 08:48:31 PM PDT 24 |
| Finished | Jun 28 08:48:52 PM PDT 24 |
| Peak memory | 565868 kb |
| Host | smart-c735f130-cc84-49ae-896e-1b067ca78ba5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2143228954 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 75.xbar_smoke_zero_delay s.2143228954 |
| Directory | /workspace/75.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/75.xbar_stress_all.2867795091 |
| Short name | T2565 |
| Test name | |
| Test status | |
| Simulation time | 14878608704 ps |
| CPU time | 541.85 seconds |
| Started | Jun 28 08:48:33 PM PDT 24 |
| Finished | Jun 28 08:57:51 PM PDT 24 |
| Peak memory | 575444 kb |
| Host | smart-feccd528-19e8-4194-a134-c9f465a67708 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2867795091 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 75.xbar_stress_all.2867795091 |
| Directory | /workspace/75.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/75.xbar_stress_all_with_error.3327650300 |
| Short name | T2024 |
| Test name | |
| Test status | |
| Simulation time | 4296063973 ps |
| CPU time | 400.08 seconds |
| Started | Jun 28 08:48:22 PM PDT 24 |
| Finished | Jun 28 08:55:19 PM PDT 24 |
| Peak memory | 574668 kb |
| Host | smart-15f6cf1e-2b81-4f0f-9aac-1c66f303f948 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3327650300 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 75.xbar_stress_all_with_error.3327650300 |
| Directory | /workspace/75.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/75.xbar_stress_all_with_rand_reset.319362933 |
| Short name | T828 |
| Test name | |
| Test status | |
| Simulation time | 6668455583 ps |
| CPU time | 419.55 seconds |
| Started | Jun 28 08:48:20 PM PDT 24 |
| Finished | Jun 28 08:55:37 PM PDT 24 |
| Peak memory | 575368 kb |
| Host | smart-91c9cdd7-c501-4c0a-add6-54f8bd38cf9b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=319362933 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_res et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 75.xbar_stress_all_ with_rand_reset.319362933 |
| Directory | /workspace/75.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/75.xbar_stress_all_with_reset_error.1045526017 |
| Short name | T2606 |
| Test name | |
| Test status | |
| Simulation time | 191954840 ps |
| CPU time | 113.78 seconds |
| Started | Jun 28 08:48:20 PM PDT 24 |
| Finished | Jun 28 08:50:31 PM PDT 24 |
| Peak memory | 574344 kb |
| Host | smart-086fcdbb-a63f-46c7-824c-09f3cfcdba31 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1045526017 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 75.xbar_stress_al l_with_reset_error.1045526017 |
| Directory | /workspace/75.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/75.xbar_unmapped_addr.1811162384 |
| Short name | T582 |
| Test name | |
| Test status | |
| Simulation time | 607242408 ps |
| CPU time | 31.03 seconds |
| Started | Jun 28 08:48:24 PM PDT 24 |
| Finished | Jun 28 08:49:12 PM PDT 24 |
| Peak memory | 575312 kb |
| Host | smart-7327c122-008a-487e-aa1c-281aae0c5df3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1811162384 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 75.xbar_unmapped_addr.1811162384 |
| Directory | /workspace/75.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/76.xbar_access_same_device.2759408280 |
| Short name | T2774 |
| Test name | |
| Test status | |
| Simulation time | 1861349461 ps |
| CPU time | 76.47 seconds |
| Started | Jun 28 08:48:19 PM PDT 24 |
| Finished | Jun 28 08:49:52 PM PDT 24 |
| Peak memory | 574180 kb |
| Host | smart-4e9457b4-bd2e-4cd5-badd-7fd9d862bce8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2759408280 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 76.xbar_access_same_device .2759408280 |
| Directory | /workspace/76.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/76.xbar_access_same_device_slow_rsp.2352184171 |
| Short name | T1764 |
| Test name | |
| Test status | |
| Simulation time | 170146435822 ps |
| CPU time | 2757.4 seconds |
| Started | Jun 28 08:48:23 PM PDT 24 |
| Finished | Jun 28 09:34:36 PM PDT 24 |
| Peak memory | 575456 kb |
| Host | smart-83ad0630-dbc2-47b4-99d0-8e6895fc75aa |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2352184171 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 76.xbar_access_same_ device_slow_rsp.2352184171 |
| Directory | /workspace/76.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/76.xbar_error_and_unmapped_addr.2225323194 |
| Short name | T1726 |
| Test name | |
| Test status | |
| Simulation time | 495619062 ps |
| CPU time | 23.79 seconds |
| Started | Jun 28 08:48:26 PM PDT 24 |
| Finished | Jun 28 08:49:05 PM PDT 24 |
| Peak memory | 573836 kb |
| Host | smart-fa2cdc67-2895-4e15-bd5b-f64db2bcaa31 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2225323194 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 76.xbar_error_and_unmapped_add r.2225323194 |
| Directory | /workspace/76.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/76.xbar_error_random.361595809 |
| Short name | T2559 |
| Test name | |
| Test status | |
| Simulation time | 1467720958 ps |
| CPU time | 51.42 seconds |
| Started | Jun 28 08:48:25 PM PDT 24 |
| Finished | Jun 28 08:49:32 PM PDT 24 |
| Peak memory | 574368 kb |
| Host | smart-2af8bd3a-843e-4fed-a474-51c116f941f0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=361595809 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 76.xbar_error_random.361595809 |
| Directory | /workspace/76.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/76.xbar_random.200144509 |
| Short name | T1594 |
| Test name | |
| Test status | |
| Simulation time | 346464467 ps |
| CPU time | 34.21 seconds |
| Started | Jun 28 08:48:20 PM PDT 24 |
| Finished | Jun 28 08:49:11 PM PDT 24 |
| Peak memory | 575236 kb |
| Host | smart-3f803ce5-20d4-493e-9e34-35971e7ab064 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=200144509 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 76.xbar_random.200144509 |
| Directory | /workspace/76.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/76.xbar_random_large_delays.4116795507 |
| Short name | T2295 |
| Test name | |
| Test status | |
| Simulation time | 43754474353 ps |
| CPU time | 457.04 seconds |
| Started | Jun 28 08:48:27 PM PDT 24 |
| Finished | Jun 28 08:56:20 PM PDT 24 |
| Peak memory | 574256 kb |
| Host | smart-d916a84a-aeef-4782-afdc-e32d968a2c94 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4116795507 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 76.xbar_random_large_delays.4116795507 |
| Directory | /workspace/76.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/76.xbar_random_slow_rsp.3821310064 |
| Short name | T483 |
| Test name | |
| Test status | |
| Simulation time | 72271517192 ps |
| CPU time | 1214.99 seconds |
| Started | Jun 28 08:48:19 PM PDT 24 |
| Finished | Jun 28 09:08:50 PM PDT 24 |
| Peak memory | 575304 kb |
| Host | smart-0bb47bcb-aeb7-4ccb-958e-5e8143441084 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3821310064 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 76.xbar_random_slow_rsp.3821310064 |
| Directory | /workspace/76.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/76.xbar_random_zero_delays.2776846793 |
| Short name | T2757 |
| Test name | |
| Test status | |
| Simulation time | 399257532 ps |
| CPU time | 35.33 seconds |
| Started | Jun 28 08:48:29 PM PDT 24 |
| Finished | Jun 28 08:49:19 PM PDT 24 |
| Peak memory | 575240 kb |
| Host | smart-ab5a329b-9a61-4e62-8ff5-59109093a115 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2776846793 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 76.xbar_random_zero_del ays.2776846793 |
| Directory | /workspace/76.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/76.xbar_same_source.4218390835 |
| Short name | T2104 |
| Test name | |
| Test status | |
| Simulation time | 339521960 ps |
| CPU time | 24.61 seconds |
| Started | Jun 28 08:48:24 PM PDT 24 |
| Finished | Jun 28 08:49:05 PM PDT 24 |
| Peak memory | 575228 kb |
| Host | smart-3530f9a3-be85-49c7-b31a-d1b34b549437 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4218390835 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 76.xbar_same_source.4218390835 |
| Directory | /workspace/76.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/76.xbar_smoke.2321037281 |
| Short name | T1737 |
| Test name | |
| Test status | |
| Simulation time | 192621372 ps |
| CPU time | 8.43 seconds |
| Started | Jun 28 08:48:20 PM PDT 24 |
| Finished | Jun 28 08:48:45 PM PDT 24 |
| Peak memory | 565940 kb |
| Host | smart-c2d63e7f-b20f-4bf8-9214-3b9688b0ba9a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2321037281 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 76.xbar_smoke.2321037281 |
| Directory | /workspace/76.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/76.xbar_smoke_large_delays.4022838978 |
| Short name | T2001 |
| Test name | |
| Test status | |
| Simulation time | 7194817229 ps |
| CPU time | 73.65 seconds |
| Started | Jun 28 08:48:25 PM PDT 24 |
| Finished | Jun 28 08:49:55 PM PDT 24 |
| Peak memory | 574260 kb |
| Host | smart-38428a02-426b-48fa-89ac-54e4b09a6e13 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4022838978 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 76.xbar_smoke_large_delays.4022838978 |
| Directory | /workspace/76.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/76.xbar_smoke_slow_rsp.3205660469 |
| Short name | T1976 |
| Test name | |
| Test status | |
| Simulation time | 5325499284 ps |
| CPU time | 90.25 seconds |
| Started | Jun 28 08:48:32 PM PDT 24 |
| Finished | Jun 28 08:50:18 PM PDT 24 |
| Peak memory | 566016 kb |
| Host | smart-db48def5-d587-4b48-8c25-00fb084f772a |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3205660469 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 76.xbar_smoke_slow_rsp.3205660469 |
| Directory | /workspace/76.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/76.xbar_smoke_zero_delays.1652567882 |
| Short name | T1383 |
| Test name | |
| Test status | |
| Simulation time | 42179148 ps |
| CPU time | 6.2 seconds |
| Started | Jun 28 08:48:32 PM PDT 24 |
| Finished | Jun 28 08:48:55 PM PDT 24 |
| Peak memory | 574180 kb |
| Host | smart-3ce961f9-71ff-40f3-8d27-b8176bbc1cb4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1652567882 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 76.xbar_smoke_zero_delay s.1652567882 |
| Directory | /workspace/76.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/76.xbar_stress_all.2456538153 |
| Short name | T2054 |
| Test name | |
| Test status | |
| Simulation time | 6251846950 ps |
| CPU time | 277.71 seconds |
| Started | Jun 28 08:48:25 PM PDT 24 |
| Finished | Jun 28 08:53:19 PM PDT 24 |
| Peak memory | 575380 kb |
| Host | smart-4a7aa541-0f9d-48b4-9f6d-a978c3ab0c4c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2456538153 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 76.xbar_stress_all.2456538153 |
| Directory | /workspace/76.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/76.xbar_stress_all_with_error.3420424217 |
| Short name | T1500 |
| Test name | |
| Test status | |
| Simulation time | 1284076566 ps |
| CPU time | 43.35 seconds |
| Started | Jun 28 08:48:31 PM PDT 24 |
| Finished | Jun 28 08:49:29 PM PDT 24 |
| Peak memory | 574428 kb |
| Host | smart-0b8b5460-7633-4ba2-bdf9-74df50a99d7a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3420424217 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 76.xbar_stress_all_with_error.3420424217 |
| Directory | /workspace/76.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/76.xbar_stress_all_with_rand_reset.2961974879 |
| Short name | T2089 |
| Test name | |
| Test status | |
| Simulation time | 169740023 ps |
| CPU time | 107.1 seconds |
| Started | Jun 28 08:48:20 PM PDT 24 |
| Finished | Jun 28 08:50:24 PM PDT 24 |
| Peak memory | 575384 kb |
| Host | smart-216120c2-4c0a-46a8-ad82-394c5f78a1e5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2961974879 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 76.xbar_stress_all _with_rand_reset.2961974879 |
| Directory | /workspace/76.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/76.xbar_stress_all_with_reset_error.2509803227 |
| Short name | T830 |
| Test name | |
| Test status | |
| Simulation time | 560306205 ps |
| CPU time | 147.79 seconds |
| Started | Jun 28 08:48:31 PM PDT 24 |
| Finished | Jun 28 08:51:15 PM PDT 24 |
| Peak memory | 576360 kb |
| Host | smart-6cf7e5e9-af35-400e-b008-fe411c400b43 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2509803227 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 76.xbar_stress_al l_with_reset_error.2509803227 |
| Directory | /workspace/76.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/76.xbar_unmapped_addr.179938790 |
| Short name | T2235 |
| Test name | |
| Test status | |
| Simulation time | 1420866876 ps |
| CPU time | 59.46 seconds |
| Started | Jun 28 08:48:23 PM PDT 24 |
| Finished | Jun 28 08:49:39 PM PDT 24 |
| Peak memory | 575300 kb |
| Host | smart-c3a20415-5ea0-44e3-8728-73c9f1eff3d3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=179938790 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 76.xbar_unmapped_addr.179938790 |
| Directory | /workspace/76.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/77.xbar_access_same_device.2386314238 |
| Short name | T1957 |
| Test name | |
| Test status | |
| Simulation time | 2174304160 ps |
| CPU time | 93.91 seconds |
| Started | Jun 28 08:48:22 PM PDT 24 |
| Finished | Jun 28 08:50:12 PM PDT 24 |
| Peak memory | 575272 kb |
| Host | smart-8c6b588a-c4da-4e70-b78a-2def4fc4c428 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2386314238 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 77.xbar_access_same_device .2386314238 |
| Directory | /workspace/77.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/77.xbar_access_same_device_slow_rsp.3572578489 |
| Short name | T2492 |
| Test name | |
| Test status | |
| Simulation time | 18987456155 ps |
| CPU time | 351.41 seconds |
| Started | Jun 28 08:48:33 PM PDT 24 |
| Finished | Jun 28 08:54:42 PM PDT 24 |
| Peak memory | 575372 kb |
| Host | smart-5bbf65a0-f9e4-4bde-a10b-a95d8bb57fd9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3572578489 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 77.xbar_access_same_ device_slow_rsp.3572578489 |
| Directory | /workspace/77.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/77.xbar_error_and_unmapped_addr.3866678376 |
| Short name | T1531 |
| Test name | |
| Test status | |
| Simulation time | 91752963 ps |
| CPU time | 12.87 seconds |
| Started | Jun 28 08:48:31 PM PDT 24 |
| Finished | Jun 28 08:49:00 PM PDT 24 |
| Peak memory | 573808 kb |
| Host | smart-6a5cc7e6-7343-40e4-b0fe-c082b1dddbb1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3866678376 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 77.xbar_error_and_unmapped_add r.3866678376 |
| Directory | /workspace/77.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/77.xbar_error_random.3698248068 |
| Short name | T2698 |
| Test name | |
| Test status | |
| Simulation time | 259792864 ps |
| CPU time | 21.5 seconds |
| Started | Jun 28 08:48:25 PM PDT 24 |
| Finished | Jun 28 08:49:03 PM PDT 24 |
| Peak memory | 574428 kb |
| Host | smart-fb638335-afc8-4da8-b3cd-4a171a3da91c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3698248068 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 77.xbar_error_random.3698248068 |
| Directory | /workspace/77.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/77.xbar_random.40292582 |
| Short name | T1475 |
| Test name | |
| Test status | |
| Simulation time | 34680755 ps |
| CPU time | 6.42 seconds |
| Started | Jun 28 08:48:29 PM PDT 24 |
| Finished | Jun 28 08:48:50 PM PDT 24 |
| Peak memory | 574192 kb |
| Host | smart-4c2c9b71-b823-4fe1-b29f-4bc3c3f4afad |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40292582 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 77.xbar_random.40292582 |
| Directory | /workspace/77.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/77.xbar_random_large_delays.3681182498 |
| Short name | T2578 |
| Test name | |
| Test status | |
| Simulation time | 18571133640 ps |
| CPU time | 192.57 seconds |
| Started | Jun 28 08:48:21 PM PDT 24 |
| Finished | Jun 28 08:51:49 PM PDT 24 |
| Peak memory | 574232 kb |
| Host | smart-42cd50aa-a508-4d8b-8b06-4bab349da0fe |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3681182498 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 77.xbar_random_large_delays.3681182498 |
| Directory | /workspace/77.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/77.xbar_random_slow_rsp.3552346672 |
| Short name | T598 |
| Test name | |
| Test status | |
| Simulation time | 16916740089 ps |
| CPU time | 317.45 seconds |
| Started | Jun 28 08:48:15 PM PDT 24 |
| Finished | Jun 28 08:53:51 PM PDT 24 |
| Peak memory | 574248 kb |
| Host | smart-675615a9-e38e-4c57-aaef-ee8e12b86fc7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3552346672 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 77.xbar_random_slow_rsp.3552346672 |
| Directory | /workspace/77.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/77.xbar_random_zero_delays.419654603 |
| Short name | T473 |
| Test name | |
| Test status | |
| Simulation time | 438034936 ps |
| CPU time | 43.82 seconds |
| Started | Jun 28 08:48:32 PM PDT 24 |
| Finished | Jun 28 08:49:31 PM PDT 24 |
| Peak memory | 574172 kb |
| Host | smart-a84e3b0a-15ff-4a65-97b7-bec930a56ed0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=419654603 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 77.xbar_random_zero_dela ys.419654603 |
| Directory | /workspace/77.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/77.xbar_same_source.3144009620 |
| Short name | T540 |
| Test name | |
| Test status | |
| Simulation time | 272835114 ps |
| CPU time | 24.6 seconds |
| Started | Jun 28 08:48:33 PM PDT 24 |
| Finished | Jun 28 08:49:14 PM PDT 24 |
| Peak memory | 574164 kb |
| Host | smart-75462d3d-cc41-4b44-aa5f-f8b9d9df14e3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3144009620 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 77.xbar_same_source.3144009620 |
| Directory | /workspace/77.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/77.xbar_smoke.2739423001 |
| Short name | T1473 |
| Test name | |
| Test status | |
| Simulation time | 186710498 ps |
| CPU time | 9.31 seconds |
| Started | Jun 28 08:48:22 PM PDT 24 |
| Finished | Jun 28 08:48:49 PM PDT 24 |
| Peak memory | 574184 kb |
| Host | smart-eabcd3a8-04d8-4d2c-948f-607b513a4a82 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2739423001 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 77.xbar_smoke.2739423001 |
| Directory | /workspace/77.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/77.xbar_smoke_large_delays.1099345391 |
| Short name | T1958 |
| Test name | |
| Test status | |
| Simulation time | 11016846023 ps |
| CPU time | 124.26 seconds |
| Started | Jun 28 08:48:29 PM PDT 24 |
| Finished | Jun 28 08:50:48 PM PDT 24 |
| Peak memory | 566024 kb |
| Host | smart-7295d8ce-276d-44f1-9614-adf5e6f98f66 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1099345391 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 77.xbar_smoke_large_delays.1099345391 |
| Directory | /workspace/77.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/77.xbar_smoke_slow_rsp.2357200989 |
| Short name | T2237 |
| Test name | |
| Test status | |
| Simulation time | 5908151339 ps |
| CPU time | 98.34 seconds |
| Started | Jun 28 08:48:19 PM PDT 24 |
| Finished | Jun 28 08:50:15 PM PDT 24 |
| Peak memory | 574252 kb |
| Host | smart-35d63c13-04a0-4c8a-8280-202005eb20ee |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2357200989 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 77.xbar_smoke_slow_rsp.2357200989 |
| Directory | /workspace/77.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/77.xbar_smoke_zero_delays.510435937 |
| Short name | T2440 |
| Test name | |
| Test status | |
| Simulation time | 49183823 ps |
| CPU time | 7.13 seconds |
| Started | Jun 28 08:48:33 PM PDT 24 |
| Finished | Jun 28 08:48:56 PM PDT 24 |
| Peak memory | 574196 kb |
| Host | smart-28554275-c287-493a-a4b7-261d67ba03da |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=510435937 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 77.xbar_smoke_zero_delays .510435937 |
| Directory | /workspace/77.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/77.xbar_stress_all_with_rand_reset.32354575 |
| Short name | T1959 |
| Test name | |
| Test status | |
| Simulation time | 372070376 ps |
| CPU time | 151.32 seconds |
| Started | Jun 28 08:48:29 PM PDT 24 |
| Finished | Jun 28 08:51:15 PM PDT 24 |
| Peak memory | 575396 kb |
| Host | smart-8d57ce45-9c70-4b81-affc-fcc2897eeed1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32354575 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_rese t_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 77.xbar_stress_all_w ith_rand_reset.32354575 |
| Directory | /workspace/77.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/77.xbar_stress_all_with_reset_error.2295034666 |
| Short name | T2607 |
| Test name | |
| Test status | |
| Simulation time | 6107534859 ps |
| CPU time | 567.17 seconds |
| Started | Jun 28 08:48:30 PM PDT 24 |
| Finished | Jun 28 08:58:12 PM PDT 24 |
| Peak memory | 574388 kb |
| Host | smart-1f0bb54e-04b6-4744-963e-8ccc11e392cc |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2295034666 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 77.xbar_stress_al l_with_reset_error.2295034666 |
| Directory | /workspace/77.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/77.xbar_unmapped_addr.3562794239 |
| Short name | T2379 |
| Test name | |
| Test status | |
| Simulation time | 646683900 ps |
| CPU time | 30.82 seconds |
| Started | Jun 28 08:48:32 PM PDT 24 |
| Finished | Jun 28 08:49:18 PM PDT 24 |
| Peak memory | 575296 kb |
| Host | smart-9c56e747-329b-4982-ba94-75febf996708 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3562794239 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 77.xbar_unmapped_addr.3562794239 |
| Directory | /workspace/77.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/78.xbar_access_same_device.1960965876 |
| Short name | T2381 |
| Test name | |
| Test status | |
| Simulation time | 110443135 ps |
| CPU time | 12.28 seconds |
| Started | Jun 28 08:49:06 PM PDT 24 |
| Finished | Jun 28 08:49:25 PM PDT 24 |
| Peak memory | 575196 kb |
| Host | smart-f488b562-8a52-49bc-89e2-dceafa9be990 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1960965876 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 78.xbar_access_same_device .1960965876 |
| Directory | /workspace/78.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/78.xbar_access_same_device_slow_rsp.173237393 |
| Short name | T1852 |
| Test name | |
| Test status | |
| Simulation time | 54408161864 ps |
| CPU time | 922.42 seconds |
| Started | Jun 28 08:49:05 PM PDT 24 |
| Finished | Jun 28 09:04:34 PM PDT 24 |
| Peak memory | 574316 kb |
| Host | smart-474c9d39-f184-4001-b16c-bf0339259d45 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=173237393 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 78.xbar_access_same_d evice_slow_rsp.173237393 |
| Directory | /workspace/78.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/78.xbar_error_and_unmapped_addr.6292611 |
| Short name | T2652 |
| Test name | |
| Test status | |
| Simulation time | 1077161263 ps |
| CPU time | 47.91 seconds |
| Started | Jun 28 08:49:03 PM PDT 24 |
| Finished | Jun 28 08:50:00 PM PDT 24 |
| Peak memory | 573884 kb |
| Host | smart-5e046425-523e-43ce-a863-0d4822b481f5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=6292611 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 78.xbar_error_and_unmapped_addr.6292611 |
| Directory | /workspace/78.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/78.xbar_error_random.4064234673 |
| Short name | T2322 |
| Test name | |
| Test status | |
| Simulation time | 471648443 ps |
| CPU time | 18.94 seconds |
| Started | Jun 28 08:49:02 PM PDT 24 |
| Finished | Jun 28 08:49:30 PM PDT 24 |
| Peak memory | 573860 kb |
| Host | smart-64a4afce-6de3-4ee0-9424-99194adef7b4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4064234673 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 78.xbar_error_random.4064234673 |
| Directory | /workspace/78.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/78.xbar_random.945762400 |
| Short name | T553 |
| Test name | |
| Test status | |
| Simulation time | 443203660 ps |
| CPU time | 41.15 seconds |
| Started | Jun 28 08:48:32 PM PDT 24 |
| Finished | Jun 28 08:49:30 PM PDT 24 |
| Peak memory | 575256 kb |
| Host | smart-c8c95dd6-288b-4efc-b6f3-cb0aba555954 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=945762400 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 78.xbar_random.945762400 |
| Directory | /workspace/78.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/78.xbar_random_large_delays.4071474315 |
| Short name | T1675 |
| Test name | |
| Test status | |
| Simulation time | 66123425363 ps |
| CPU time | 700.88 seconds |
| Started | Jun 28 08:48:55 PM PDT 24 |
| Finished | Jun 28 09:00:49 PM PDT 24 |
| Peak memory | 575316 kb |
| Host | smart-6bc4e0a1-c98f-4abc-adca-c9a6be338e42 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4071474315 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 78.xbar_random_large_delays.4071474315 |
| Directory | /workspace/78.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/78.xbar_random_slow_rsp.394938247 |
| Short name | T2291 |
| Test name | |
| Test status | |
| Simulation time | 12423298696 ps |
| CPU time | 212.67 seconds |
| Started | Jun 28 08:49:02 PM PDT 24 |
| Finished | Jun 28 08:52:43 PM PDT 24 |
| Peak memory | 574188 kb |
| Host | smart-6dfd55bb-c03b-4fe0-98f6-8432bfcf37a3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=394938247 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 78.xbar_random_slow_rsp.394938247 |
| Directory | /workspace/78.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/78.xbar_random_zero_delays.4135741354 |
| Short name | T2807 |
| Test name | |
| Test status | |
| Simulation time | 329003191 ps |
| CPU time | 28.59 seconds |
| Started | Jun 28 08:48:24 PM PDT 24 |
| Finished | Jun 28 08:49:09 PM PDT 24 |
| Peak memory | 574176 kb |
| Host | smart-a25ce125-7119-4d69-a511-e21ababb6b64 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4135741354 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 78.xbar_random_zero_del ays.4135741354 |
| Directory | /workspace/78.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/78.xbar_same_source.3171405722 |
| Short name | T2115 |
| Test name | |
| Test status | |
| Simulation time | 236893675 ps |
| CPU time | 11.33 seconds |
| Started | Jun 28 08:49:06 PM PDT 24 |
| Finished | Jun 28 08:49:24 PM PDT 24 |
| Peak memory | 565940 kb |
| Host | smart-954c744c-c366-47e2-8017-2afb7662af2a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3171405722 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 78.xbar_same_source.3171405722 |
| Directory | /workspace/78.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/78.xbar_smoke.1435531407 |
| Short name | T2673 |
| Test name | |
| Test status | |
| Simulation time | 45916484 ps |
| CPU time | 6.3 seconds |
| Started | Jun 28 08:48:28 PM PDT 24 |
| Finished | Jun 28 08:48:50 PM PDT 24 |
| Peak memory | 574192 kb |
| Host | smart-78b728a7-2359-4376-951f-3edf67eafe50 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1435531407 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 78.xbar_smoke.1435531407 |
| Directory | /workspace/78.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/78.xbar_smoke_large_delays.1922931833 |
| Short name | T2053 |
| Test name | |
| Test status | |
| Simulation time | 7224145599 ps |
| CPU time | 77.74 seconds |
| Started | Jun 28 08:48:24 PM PDT 24 |
| Finished | Jun 28 08:49:58 PM PDT 24 |
| Peak memory | 566024 kb |
| Host | smart-73dfe85a-cdd1-494f-b7dd-f146e451f9d0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1922931833 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 78.xbar_smoke_large_delays.1922931833 |
| Directory | /workspace/78.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/78.xbar_smoke_slow_rsp.2051300063 |
| Short name | T2343 |
| Test name | |
| Test status | |
| Simulation time | 3197410345 ps |
| CPU time | 55.84 seconds |
| Started | Jun 28 08:48:21 PM PDT 24 |
| Finished | Jun 28 08:49:35 PM PDT 24 |
| Peak memory | 574128 kb |
| Host | smart-26571b94-ebdb-4c9a-9e2d-34608a93d995 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2051300063 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 78.xbar_smoke_slow_rsp.2051300063 |
| Directory | /workspace/78.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/78.xbar_smoke_zero_delays.3618681577 |
| Short name | T1751 |
| Test name | |
| Test status | |
| Simulation time | 55726070 ps |
| CPU time | 7.04 seconds |
| Started | Jun 28 08:48:32 PM PDT 24 |
| Finished | Jun 28 08:48:55 PM PDT 24 |
| Peak memory | 574176 kb |
| Host | smart-df3352a9-8912-4716-93e0-f5e1809d3b51 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3618681577 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 78.xbar_smoke_zero_delay s.3618681577 |
| Directory | /workspace/78.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/78.xbar_stress_all.723873232 |
| Short name | T494 |
| Test name | |
| Test status | |
| Simulation time | 9893048234 ps |
| CPU time | 350.56 seconds |
| Started | Jun 28 08:49:05 PM PDT 24 |
| Finished | Jun 28 08:55:03 PM PDT 24 |
| Peak memory | 575448 kb |
| Host | smart-8edbc30f-4a99-40a6-a82c-c0fb6bee74fc |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=723873232 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 78.xbar_stress_all.723873232 |
| Directory | /workspace/78.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/78.xbar_stress_all_with_error.2294817759 |
| Short name | T2804 |
| Test name | |
| Test status | |
| Simulation time | 4603892337 ps |
| CPU time | 154.82 seconds |
| Started | Jun 28 08:49:03 PM PDT 24 |
| Finished | Jun 28 08:51:46 PM PDT 24 |
| Peak memory | 574348 kb |
| Host | smart-6a51ec34-56c0-4506-b144-d8b4342ba5d5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2294817759 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 78.xbar_stress_all_with_error.2294817759 |
| Directory | /workspace/78.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/78.xbar_stress_all_with_rand_reset.1910148888 |
| Short name | T1515 |
| Test name | |
| Test status | |
| Simulation time | 3223912380 ps |
| CPU time | 347.49 seconds |
| Started | Jun 28 08:49:02 PM PDT 24 |
| Finished | Jun 28 08:54:58 PM PDT 24 |
| Peak memory | 575440 kb |
| Host | smart-de260062-699e-4c19-867b-5fcc17246a68 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1910148888 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 78.xbar_stress_all _with_rand_reset.1910148888 |
| Directory | /workspace/78.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/78.xbar_stress_all_with_reset_error.3697807626 |
| Short name | T2821 |
| Test name | |
| Test status | |
| Simulation time | 12216397055 ps |
| CPU time | 500.15 seconds |
| Started | Jun 28 08:49:06 PM PDT 24 |
| Finished | Jun 28 08:57:33 PM PDT 24 |
| Peak memory | 574436 kb |
| Host | smart-a5621c0b-54f3-49a5-a41d-49da9630c70b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3697807626 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 78.xbar_stress_al l_with_reset_error.3697807626 |
| Directory | /workspace/78.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/78.xbar_unmapped_addr.124826198 |
| Short name | T2034 |
| Test name | |
| Test status | |
| Simulation time | 760797073 ps |
| CPU time | 36.26 seconds |
| Started | Jun 28 08:49:06 PM PDT 24 |
| Finished | Jun 28 08:49:49 PM PDT 24 |
| Peak memory | 575264 kb |
| Host | smart-82ebabba-a90c-42df-aff0-3c964459fea1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=124826198 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 78.xbar_unmapped_addr.124826198 |
| Directory | /workspace/78.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/79.xbar_access_same_device.2118896608 |
| Short name | T2429 |
| Test name | |
| Test status | |
| Simulation time | 410834369 ps |
| CPU time | 34.43 seconds |
| Started | Jun 28 08:49:05 PM PDT 24 |
| Finished | Jun 28 08:49:47 PM PDT 24 |
| Peak memory | 575248 kb |
| Host | smart-629b9914-4001-4622-acdf-d15a8d1f727c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2118896608 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 79.xbar_access_same_device .2118896608 |
| Directory | /workspace/79.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/79.xbar_access_same_device_slow_rsp.2618807059 |
| Short name | T1550 |
| Test name | |
| Test status | |
| Simulation time | 123685249327 ps |
| CPU time | 2010.1 seconds |
| Started | Jun 28 08:49:03 PM PDT 24 |
| Finished | Jun 28 09:22:42 PM PDT 24 |
| Peak memory | 575348 kb |
| Host | smart-51236c48-4576-4da6-ad15-637bc3d7cb99 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2618807059 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 79.xbar_access_same_ device_slow_rsp.2618807059 |
| Directory | /workspace/79.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/79.xbar_error_and_unmapped_addr.3706710273 |
| Short name | T2421 |
| Test name | |
| Test status | |
| Simulation time | 103023933 ps |
| CPU time | 12.62 seconds |
| Started | Jun 28 08:49:04 PM PDT 24 |
| Finished | Jun 28 08:49:24 PM PDT 24 |
| Peak memory | 574452 kb |
| Host | smart-d3ef1eda-5889-4cd5-bae4-8592d8ae105f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3706710273 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 79.xbar_error_and_unmapped_add r.3706710273 |
| Directory | /workspace/79.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/79.xbar_error_random.3284307640 |
| Short name | T2270 |
| Test name | |
| Test status | |
| Simulation time | 1183379673 ps |
| CPU time | 39.87 seconds |
| Started | Jun 28 08:49:03 PM PDT 24 |
| Finished | Jun 28 08:49:51 PM PDT 24 |
| Peak memory | 574204 kb |
| Host | smart-c64e12c2-9a41-409d-9851-3023231f5813 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3284307640 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 79.xbar_error_random.3284307640 |
| Directory | /workspace/79.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/79.xbar_random.1676841865 |
| Short name | T1739 |
| Test name | |
| Test status | |
| Simulation time | 478688708 ps |
| CPU time | 47.11 seconds |
| Started | Jun 28 08:49:03 PM PDT 24 |
| Finished | Jun 28 08:49:59 PM PDT 24 |
| Peak memory | 574212 kb |
| Host | smart-4dd42338-5c94-4579-bc0e-b5d9d72af2b8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1676841865 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 79.xbar_random.1676841865 |
| Directory | /workspace/79.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/79.xbar_random_large_delays.289346687 |
| Short name | T2443 |
| Test name | |
| Test status | |
| Simulation time | 105120488665 ps |
| CPU time | 1112.5 seconds |
| Started | Jun 28 08:49:03 PM PDT 24 |
| Finished | Jun 28 09:07:44 PM PDT 24 |
| Peak memory | 575340 kb |
| Host | smart-ad446e49-9f49-4fe3-9650-f6e2c14f5f6e |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=289346687 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 79.xbar_random_large_delays.289346687 |
| Directory | /workspace/79.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/79.xbar_random_slow_rsp.3310777154 |
| Short name | T2372 |
| Test name | |
| Test status | |
| Simulation time | 60395023830 ps |
| CPU time | 990.15 seconds |
| Started | Jun 28 08:49:06 PM PDT 24 |
| Finished | Jun 28 09:05:43 PM PDT 24 |
| Peak memory | 574236 kb |
| Host | smart-5705e504-0a69-4a77-9e6d-2d39d0edcd2f |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3310777154 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 79.xbar_random_slow_rsp.3310777154 |
| Directory | /workspace/79.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/79.xbar_random_zero_delays.2878978202 |
| Short name | T1346 |
| Test name | |
| Test status | |
| Simulation time | 57013346 ps |
| CPU time | 8.56 seconds |
| Started | Jun 28 08:49:06 PM PDT 24 |
| Finished | Jun 28 08:49:21 PM PDT 24 |
| Peak memory | 574216 kb |
| Host | smart-ed3d72f9-6181-4d47-bf55-e90ce071db76 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2878978202 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 79.xbar_random_zero_del ays.2878978202 |
| Directory | /workspace/79.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/79.xbar_same_source.3221578000 |
| Short name | T488 |
| Test name | |
| Test status | |
| Simulation time | 2026287152 ps |
| CPU time | 67.57 seconds |
| Started | Jun 28 08:49:04 PM PDT 24 |
| Finished | Jun 28 08:50:19 PM PDT 24 |
| Peak memory | 575228 kb |
| Host | smart-9244bd7a-c487-403e-bb34-1394c4998ea4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3221578000 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 79.xbar_same_source.3221578000 |
| Directory | /workspace/79.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/79.xbar_smoke.2813764756 |
| Short name | T1394 |
| Test name | |
| Test status | |
| Simulation time | 46474847 ps |
| CPU time | 6.59 seconds |
| Started | Jun 28 08:49:03 PM PDT 24 |
| Finished | Jun 28 08:49:18 PM PDT 24 |
| Peak memory | 565888 kb |
| Host | smart-a86cc656-eaf3-41a3-8b72-a504a4ee8c49 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2813764756 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 79.xbar_smoke.2813764756 |
| Directory | /workspace/79.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/79.xbar_smoke_large_delays.921030610 |
| Short name | T1391 |
| Test name | |
| Test status | |
| Simulation time | 6623473223 ps |
| CPU time | 67.46 seconds |
| Started | Jun 28 08:49:07 PM PDT 24 |
| Finished | Jun 28 08:50:21 PM PDT 24 |
| Peak memory | 574236 kb |
| Host | smart-8f370c46-277c-4b2e-84a9-fc926a3ad90a |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=921030610 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 79.xbar_smoke_large_delays.921030610 |
| Directory | /workspace/79.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/79.xbar_smoke_slow_rsp.1600635512 |
| Short name | T2098 |
| Test name | |
| Test status | |
| Simulation time | 5227185325 ps |
| CPU time | 87.54 seconds |
| Started | Jun 28 08:49:05 PM PDT 24 |
| Finished | Jun 28 08:50:40 PM PDT 24 |
| Peak memory | 574240 kb |
| Host | smart-1aa27b7f-514f-4280-9475-4ae7f92ef157 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1600635512 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 79.xbar_smoke_slow_rsp.1600635512 |
| Directory | /workspace/79.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/79.xbar_smoke_zero_delays.653459290 |
| Short name | T1785 |
| Test name | |
| Test status | |
| Simulation time | 42417790 ps |
| CPU time | 6.35 seconds |
| Started | Jun 28 08:49:03 PM PDT 24 |
| Finished | Jun 28 08:49:18 PM PDT 24 |
| Peak memory | 574080 kb |
| Host | smart-5c057914-064e-4020-8f36-cfdfb7deb2c2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=653459290 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 79.xbar_smoke_zero_delays .653459290 |
| Directory | /workspace/79.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/79.xbar_stress_all.4131369747 |
| Short name | T1659 |
| Test name | |
| Test status | |
| Simulation time | 8891525991 ps |
| CPU time | 314.87 seconds |
| Started | Jun 28 08:49:04 PM PDT 24 |
| Finished | Jun 28 08:54:27 PM PDT 24 |
| Peak memory | 575428 kb |
| Host | smart-e59326b8-8ca9-4e80-bba7-d9687d10f94d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4131369747 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 79.xbar_stress_all.4131369747 |
| Directory | /workspace/79.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/79.xbar_stress_all_with_error.150493444 |
| Short name | T1830 |
| Test name | |
| Test status | |
| Simulation time | 1004678904 ps |
| CPU time | 93.95 seconds |
| Started | Jun 28 08:49:06 PM PDT 24 |
| Finished | Jun 28 08:50:47 PM PDT 24 |
| Peak memory | 574284 kb |
| Host | smart-030d2a3e-ba3c-41c6-ab1a-441f479d1171 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=150493444 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 79.xbar_stress_all_with_error.150493444 |
| Directory | /workspace/79.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/79.xbar_stress_all_with_rand_reset.3942846095 |
| Short name | T558 |
| Test name | |
| Test status | |
| Simulation time | 15848873754 ps |
| CPU time | 811.6 seconds |
| Started | Jun 28 08:49:04 PM PDT 24 |
| Finished | Jun 28 09:02:43 PM PDT 24 |
| Peak memory | 575444 kb |
| Host | smart-243a7300-bad2-4179-8fe1-8a02ae147bef |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3942846095 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 79.xbar_stress_all _with_rand_reset.3942846095 |
| Directory | /workspace/79.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/79.xbar_stress_all_with_reset_error.4107918182 |
| Short name | T1898 |
| Test name | |
| Test status | |
| Simulation time | 9920933675 ps |
| CPU time | 477.61 seconds |
| Started | Jun 28 08:49:07 PM PDT 24 |
| Finished | Jun 28 08:57:11 PM PDT 24 |
| Peak memory | 574440 kb |
| Host | smart-e711d9bc-c190-48db-b522-f73ff7bd3728 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4107918182 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 79.xbar_stress_al l_with_reset_error.4107918182 |
| Directory | /workspace/79.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/79.xbar_unmapped_addr.3370341333 |
| Short name | T2328 |
| Test name | |
| Test status | |
| Simulation time | 33051008 ps |
| CPU time | 7.07 seconds |
| Started | Jun 28 08:49:04 PM PDT 24 |
| Finished | Jun 28 08:49:19 PM PDT 24 |
| Peak memory | 566000 kb |
| Host | smart-fbf50eb7-5005-4d55-a37c-a9faa767050a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3370341333 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 79.xbar_unmapped_addr.3370341333 |
| Directory | /workspace/79.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/8.chip_csr_rw.2069352670 |
| Short name | T2482 |
| Test name | |
| Test status | |
| Simulation time | 4888760650 ps |
| CPU time | 299.79 seconds |
| Started | Jun 28 08:34:00 PM PDT 24 |
| Finished | Jun 28 08:39:10 PM PDT 24 |
| Peak memory | 596784 kb |
| Host | smart-1e25f8ac-f95f-4ece-85e1-d26cf48491c1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2069352670 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.chip_csr_rw.2069352670 |
| Directory | /workspace/8.chip_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/8.chip_same_csr_outstanding.1462448836 |
| Short name | T401 |
| Test name | |
| Test status | |
| Simulation time | 16132253199 ps |
| CPU time | 1853.77 seconds |
| Started | Jun 28 08:32:46 PM PDT 24 |
| Finished | Jun 28 09:03:41 PM PDT 24 |
| Peak memory | 591524 kb |
| Host | smart-05b8098d-12f4-48f7-b0cd-137bbb89a5a5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +run_same_csr_outstanding +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1462448836 -assert nopostproc +UVM_TE STNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb - cm_log /dev/null -cm_name 8.chip_same_csr_outstanding.1462448836 |
| Directory | /workspace/8.chip_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/8.chip_tl_errors.2068646732 |
| Short name | T547 |
| Test name | |
| Test status | |
| Simulation time | 3556497352 ps |
| CPU time | 251.76 seconds |
| Started | Jun 28 08:33:23 PM PDT 24 |
| Finished | Jun 28 08:37:36 PM PDT 24 |
| Peak memory | 603216 kb |
| Host | smart-67b32dfd-b396-4b86-b59b-7747a502ac2b |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2068646732 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.chip_tl_errors.2068646732 |
| Directory | /workspace/8.chip_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/8.xbar_access_same_device.2524831488 |
| Short name | T1629 |
| Test name | |
| Test status | |
| Simulation time | 883281791 ps |
| CPU time | 77.17 seconds |
| Started | Jun 28 08:33:23 PM PDT 24 |
| Finished | Jun 28 08:34:42 PM PDT 24 |
| Peak memory | 574176 kb |
| Host | smart-9c7267b1-5384-4ad3-8680-c07669ba28e0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2524831488 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.xbar_access_same_device. 2524831488 |
| Directory | /workspace/8.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/8.xbar_access_same_device_slow_rsp.2240437554 |
| Short name | T2818 |
| Test name | |
| Test status | |
| Simulation time | 31786944218 ps |
| CPU time | 547.47 seconds |
| Started | Jun 28 08:33:32 PM PDT 24 |
| Finished | Jun 28 08:42:43 PM PDT 24 |
| Peak memory | 575344 kb |
| Host | smart-f87a758c-0e57-4846-8f8e-aefcf1e2b390 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2240437554 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.xbar_access_same_d evice_slow_rsp.2240437554 |
| Directory | /workspace/8.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/8.xbar_error_and_unmapped_addr.3924685921 |
| Short name | T2704 |
| Test name | |
| Test status | |
| Simulation time | 51050455 ps |
| CPU time | 9.62 seconds |
| Started | Jun 28 08:34:00 PM PDT 24 |
| Finished | Jun 28 08:34:18 PM PDT 24 |
| Peak memory | 574172 kb |
| Host | smart-66e65e73-ce34-4d41-8a6f-5ebf92442a73 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3924685921 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.xbar_error_and_unmapped_addr .3924685921 |
| Directory | /workspace/8.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/8.xbar_error_random.1047582710 |
| Short name | T2453 |
| Test name | |
| Test status | |
| Simulation time | 1165823023 ps |
| CPU time | 41.88 seconds |
| Started | Jun 28 08:34:00 PM PDT 24 |
| Finished | Jun 28 08:34:50 PM PDT 24 |
| Peak memory | 573800 kb |
| Host | smart-a3f636ee-d7da-432b-b081-32c5e274dd49 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1047582710 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.xbar_error_random.1047582710 |
| Directory | /workspace/8.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/8.xbar_random.4079287942 |
| Short name | T2426 |
| Test name | |
| Test status | |
| Simulation time | 2298246721 ps |
| CPU time | 84.07 seconds |
| Started | Jun 28 08:33:24 PM PDT 24 |
| Finished | Jun 28 08:34:51 PM PDT 24 |
| Peak memory | 574236 kb |
| Host | smart-3d48529b-2c72-45e1-85d4-ede788b99a0d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4079287942 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.xbar_random.4079287942 |
| Directory | /workspace/8.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/8.xbar_random_large_delays.2560303421 |
| Short name | T2365 |
| Test name | |
| Test status | |
| Simulation time | 64347843085 ps |
| CPU time | 692.53 seconds |
| Started | Jun 28 08:33:25 PM PDT 24 |
| Finished | Jun 28 08:45:00 PM PDT 24 |
| Peak memory | 575320 kb |
| Host | smart-cc71052f-95cd-42f4-99bb-6331a31151bb |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2560303421 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.xbar_random_large_delays.2560303421 |
| Directory | /workspace/8.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/8.xbar_random_slow_rsp.192192154 |
| Short name | T2709 |
| Test name | |
| Test status | |
| Simulation time | 47789068074 ps |
| CPU time | 847.06 seconds |
| Started | Jun 28 08:33:23 PM PDT 24 |
| Finished | Jun 28 08:47:32 PM PDT 24 |
| Peak memory | 574252 kb |
| Host | smart-e0cda3c1-cebc-454b-86b6-e771fb4ff846 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=192192154 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.xbar_random_slow_rsp.192192154 |
| Directory | /workspace/8.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/8.xbar_random_zero_delays.2848744677 |
| Short name | T2636 |
| Test name | |
| Test status | |
| Simulation time | 385669496 ps |
| CPU time | 32.01 seconds |
| Started | Jun 28 08:33:27 PM PDT 24 |
| Finished | Jun 28 08:34:01 PM PDT 24 |
| Peak memory | 575260 kb |
| Host | smart-7c52f8b2-f8e5-41f3-ae56-0ce4b3be4480 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2848744677 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.xbar_random_zero_dela ys.2848744677 |
| Directory | /workspace/8.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/8.xbar_same_source.854896870 |
| Short name | T472 |
| Test name | |
| Test status | |
| Simulation time | 361411585 ps |
| CPU time | 31.23 seconds |
| Started | Jun 28 08:33:24 PM PDT 24 |
| Finished | Jun 28 08:33:56 PM PDT 24 |
| Peak memory | 575232 kb |
| Host | smart-51d5c1a9-3a36-41d7-a7c0-6f36ccba82d5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=854896870 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.xbar_same_source.854896870 |
| Directory | /workspace/8.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/8.xbar_smoke.2056844951 |
| Short name | T1593 |
| Test name | |
| Test status | |
| Simulation time | 54840786 ps |
| CPU time | 7.35 seconds |
| Started | Jun 28 08:33:23 PM PDT 24 |
| Finished | Jun 28 08:33:32 PM PDT 24 |
| Peak memory | 574180 kb |
| Host | smart-e6dd99ca-88c0-4be0-8549-d30b2cc3e762 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2056844951 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.xbar_smoke.2056844951 |
| Directory | /workspace/8.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/8.xbar_smoke_large_delays.464922772 |
| Short name | T2323 |
| Test name | |
| Test status | |
| Simulation time | 7268228233 ps |
| CPU time | 74.52 seconds |
| Started | Jun 28 08:33:25 PM PDT 24 |
| Finished | Jun 28 08:34:42 PM PDT 24 |
| Peak memory | 574188 kb |
| Host | smart-85fc35b6-3dd4-4468-90d0-748c6bf341a6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=464922772 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.xbar_smoke_large_delays.464922772 |
| Directory | /workspace/8.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/8.xbar_smoke_slow_rsp.3675873218 |
| Short name | T2593 |
| Test name | |
| Test status | |
| Simulation time | 6082104012 ps |
| CPU time | 102.33 seconds |
| Started | Jun 28 08:33:24 PM PDT 24 |
| Finished | Jun 28 08:35:08 PM PDT 24 |
| Peak memory | 574388 kb |
| Host | smart-11f4a015-865c-4c19-8218-cb427068b6e0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3675873218 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.xbar_smoke_slow_rsp.3675873218 |
| Directory | /workspace/8.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/8.xbar_smoke_zero_delays.3474675251 |
| Short name | T1642 |
| Test name | |
| Test status | |
| Simulation time | 49921272 ps |
| CPU time | 7.25 seconds |
| Started | Jun 28 08:33:24 PM PDT 24 |
| Finished | Jun 28 08:33:32 PM PDT 24 |
| Peak memory | 574136 kb |
| Host | smart-08a57c99-91a2-465e-a0ca-3ab5fda5fe50 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3474675251 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.xbar_smoke_zero_delays .3474675251 |
| Directory | /workspace/8.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/8.xbar_stress_all.1765924410 |
| Short name | T2678 |
| Test name | |
| Test status | |
| Simulation time | 1323031892 ps |
| CPU time | 117.49 seconds |
| Started | Jun 28 08:34:07 PM PDT 24 |
| Finished | Jun 28 08:36:15 PM PDT 24 |
| Peak memory | 575388 kb |
| Host | smart-d1d66c32-f992-48f0-bcf5-62af8ef80bf2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1765924410 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.xbar_stress_all.1765924410 |
| Directory | /workspace/8.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/8.xbar_stress_all_with_error.717627430 |
| Short name | T783 |
| Test name | |
| Test status | |
| Simulation time | 17307789302 ps |
| CPU time | 706.87 seconds |
| Started | Jun 28 08:34:06 PM PDT 24 |
| Finished | Jun 28 08:46:04 PM PDT 24 |
| Peak memory | 574664 kb |
| Host | smart-d5d74da3-ca9d-4ed0-8308-09d9932a393f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=717627430 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.xbar_stress_all_with_error.717627430 |
| Directory | /workspace/8.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/8.xbar_stress_all_with_rand_reset.950228521 |
| Short name | T548 |
| Test name | |
| Test status | |
| Simulation time | 273269381 ps |
| CPU time | 88.12 seconds |
| Started | Jun 28 08:33:59 PM PDT 24 |
| Finished | Jun 28 08:35:36 PM PDT 24 |
| Peak memory | 575292 kb |
| Host | smart-2d25456c-ca18-4a48-b49b-baeebc8e0924 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=950228521 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_res et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.xbar_stress_all_w ith_rand_reset.950228521 |
| Directory | /workspace/8.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/8.xbar_stress_all_with_reset_error.793813154 |
| Short name | T823 |
| Test name | |
| Test status | |
| Simulation time | 2222363117 ps |
| CPU time | 238.16 seconds |
| Started | Jun 28 08:34:03 PM PDT 24 |
| Finished | Jun 28 08:38:11 PM PDT 24 |
| Peak memory | 574616 kb |
| Host | smart-276a7434-d0bf-473f-887e-02e447f06cd7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=793813154 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.xbar_stress_all_ with_reset_error.793813154 |
| Directory | /workspace/8.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/8.xbar_unmapped_addr.3767828046 |
| Short name | T1794 |
| Test name | |
| Test status | |
| Simulation time | 74852489 ps |
| CPU time | 13.07 seconds |
| Started | Jun 28 08:34:00 PM PDT 24 |
| Finished | Jun 28 08:34:21 PM PDT 24 |
| Peak memory | 575260 kb |
| Host | smart-e841d6c6-4c2a-40c1-a8da-09cac3e83d0f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3767828046 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.xbar_unmapped_addr.3767828046 |
| Directory | /workspace/8.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/80.xbar_access_same_device.1716772137 |
| Short name | T814 |
| Test name | |
| Test status | |
| Simulation time | 667708921 ps |
| CPU time | 68.96 seconds |
| Started | Jun 28 08:49:04 PM PDT 24 |
| Finished | Jun 28 08:50:20 PM PDT 24 |
| Peak memory | 575300 kb |
| Host | smart-e3ccb0fa-389e-48d3-a2de-2e50e1239840 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1716772137 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 80.xbar_access_same_device .1716772137 |
| Directory | /workspace/80.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/80.xbar_access_same_device_slow_rsp.1644044077 |
| Short name | T1903 |
| Test name | |
| Test status | |
| Simulation time | 138017041692 ps |
| CPU time | 2336.24 seconds |
| Started | Jun 28 08:49:04 PM PDT 24 |
| Finished | Jun 28 09:28:08 PM PDT 24 |
| Peak memory | 574288 kb |
| Host | smart-6d370e7f-f02d-4e22-96fa-8c4de7c3fe4e |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1644044077 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 80.xbar_access_same_ device_slow_rsp.1644044077 |
| Directory | /workspace/80.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/80.xbar_error_and_unmapped_addr.2992516556 |
| Short name | T2787 |
| Test name | |
| Test status | |
| Simulation time | 305425734 ps |
| CPU time | 14.85 seconds |
| Started | Jun 28 08:49:46 PM PDT 24 |
| Finished | Jun 28 08:50:24 PM PDT 24 |
| Peak memory | 574420 kb |
| Host | smart-3127c877-a704-498f-9992-355fcc703171 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2992516556 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 80.xbar_error_and_unmapped_add r.2992516556 |
| Directory | /workspace/80.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/80.xbar_error_random.883650992 |
| Short name | T1972 |
| Test name | |
| Test status | |
| Simulation time | 384715594 ps |
| CPU time | 18.35 seconds |
| Started | Jun 28 08:49:02 PM PDT 24 |
| Finished | Jun 28 08:49:29 PM PDT 24 |
| Peak memory | 574420 kb |
| Host | smart-380f28d4-c0b0-47b3-9911-22879a60479b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=883650992 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 80.xbar_error_random.883650992 |
| Directory | /workspace/80.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/80.xbar_random.884000293 |
| Short name | T569 |
| Test name | |
| Test status | |
| Simulation time | 535931731 ps |
| CPU time | 48.46 seconds |
| Started | Jun 28 08:49:04 PM PDT 24 |
| Finished | Jun 28 08:50:00 PM PDT 24 |
| Peak memory | 575240 kb |
| Host | smart-d227abd2-c21a-444d-b384-fe0ad0414837 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=884000293 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 80.xbar_random.884000293 |
| Directory | /workspace/80.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/80.xbar_random_large_delays.3462519101 |
| Short name | T2682 |
| Test name | |
| Test status | |
| Simulation time | 6000243764 ps |
| CPU time | 67.67 seconds |
| Started | Jun 28 08:49:02 PM PDT 24 |
| Finished | Jun 28 08:50:18 PM PDT 24 |
| Peak memory | 566032 kb |
| Host | smart-96b4812c-6ca6-457b-8bb3-07404d1a93e9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3462519101 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 80.xbar_random_large_delays.3462519101 |
| Directory | /workspace/80.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/80.xbar_random_slow_rsp.3401401375 |
| Short name | T1902 |
| Test name | |
| Test status | |
| Simulation time | 68057237543 ps |
| CPU time | 1100.17 seconds |
| Started | Jun 28 08:49:07 PM PDT 24 |
| Finished | Jun 28 09:07:34 PM PDT 24 |
| Peak memory | 575304 kb |
| Host | smart-ea0c9718-4050-4625-abb9-f48b9366e38e |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3401401375 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 80.xbar_random_slow_rsp.3401401375 |
| Directory | /workspace/80.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/80.xbar_random_zero_delays.3793461581 |
| Short name | T2132 |
| Test name | |
| Test status | |
| Simulation time | 275229998 ps |
| CPU time | 29.6 seconds |
| Started | Jun 28 08:49:03 PM PDT 24 |
| Finished | Jun 28 08:49:41 PM PDT 24 |
| Peak memory | 574216 kb |
| Host | smart-a7e8f3d8-4914-469e-991e-7b7e686f2c7f |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3793461581 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 80.xbar_random_zero_del ays.3793461581 |
| Directory | /workspace/80.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/80.xbar_same_source.3929036399 |
| Short name | T481 |
| Test name | |
| Test status | |
| Simulation time | 2671924619 ps |
| CPU time | 87.07 seconds |
| Started | Jun 28 08:49:04 PM PDT 24 |
| Finished | Jun 28 08:50:39 PM PDT 24 |
| Peak memory | 574240 kb |
| Host | smart-b49d1737-9507-4f79-a7a3-5b616a3ece77 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3929036399 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 80.xbar_same_source.3929036399 |
| Directory | /workspace/80.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/80.xbar_smoke.3388733817 |
| Short name | T2516 |
| Test name | |
| Test status | |
| Simulation time | 230645535 ps |
| CPU time | 10.44 seconds |
| Started | Jun 28 08:49:02 PM PDT 24 |
| Finished | Jun 28 08:49:21 PM PDT 24 |
| Peak memory | 574188 kb |
| Host | smart-cf086978-0174-4951-a497-5ab86e72784a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3388733817 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 80.xbar_smoke.3388733817 |
| Directory | /workspace/80.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/80.xbar_smoke_large_delays.3780132281 |
| Short name | T2815 |
| Test name | |
| Test status | |
| Simulation time | 10152574201 ps |
| CPU time | 101.16 seconds |
| Started | Jun 28 08:49:07 PM PDT 24 |
| Finished | Jun 28 08:50:54 PM PDT 24 |
| Peak memory | 574252 kb |
| Host | smart-7d3b3baa-9438-4f31-bba4-00d97d2e32c7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3780132281 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 80.xbar_smoke_large_delays.3780132281 |
| Directory | /workspace/80.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/80.xbar_smoke_slow_rsp.619447775 |
| Short name | T2696 |
| Test name | |
| Test status | |
| Simulation time | 6286315564 ps |
| CPU time | 103.82 seconds |
| Started | Jun 28 08:49:04 PM PDT 24 |
| Finished | Jun 28 08:50:56 PM PDT 24 |
| Peak memory | 574168 kb |
| Host | smart-b87d4b32-4fc2-4a35-81f8-3ddacd8f082a |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=619447775 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 80.xbar_smoke_slow_rsp.619447775 |
| Directory | /workspace/80.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/80.xbar_smoke_zero_delays.4002700241 |
| Short name | T1611 |
| Test name | |
| Test status | |
| Simulation time | 54326112 ps |
| CPU time | 7.3 seconds |
| Started | Jun 28 08:49:02 PM PDT 24 |
| Finished | Jun 28 08:49:18 PM PDT 24 |
| Peak memory | 574188 kb |
| Host | smart-2b9fd7d4-168d-469b-b8f1-25a6e9dc4959 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4002700241 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 80.xbar_smoke_zero_delay s.4002700241 |
| Directory | /workspace/80.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/80.xbar_stress_all.1689238916 |
| Short name | T501 |
| Test name | |
| Test status | |
| Simulation time | 10736462345 ps |
| CPU time | 390.98 seconds |
| Started | Jun 28 08:49:46 PM PDT 24 |
| Finished | Jun 28 08:56:40 PM PDT 24 |
| Peak memory | 575456 kb |
| Host | smart-0c7963d6-4443-4146-abff-c9dd26ab9265 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1689238916 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 80.xbar_stress_all.1689238916 |
| Directory | /workspace/80.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/80.xbar_stress_all_with_error.1323207490 |
| Short name | T1861 |
| Test name | |
| Test status | |
| Simulation time | 1907196408 ps |
| CPU time | 73.27 seconds |
| Started | Jun 28 08:49:45 PM PDT 24 |
| Finished | Jun 28 08:51:20 PM PDT 24 |
| Peak memory | 574224 kb |
| Host | smart-f2b637b6-1af4-4eee-a137-f0ca3bb03cad |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1323207490 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 80.xbar_stress_all_with_error.1323207490 |
| Directory | /workspace/80.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/80.xbar_stress_all_with_rand_reset.3187840930 |
| Short name | T853 |
| Test name | |
| Test status | |
| Simulation time | 5325161705 ps |
| CPU time | 365.29 seconds |
| Started | Jun 28 08:49:45 PM PDT 24 |
| Finished | Jun 28 08:56:10 PM PDT 24 |
| Peak memory | 576436 kb |
| Host | smart-7f5a6340-375d-4e9d-95ce-2994b8ef3a4c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3187840930 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 80.xbar_stress_all _with_rand_reset.3187840930 |
| Directory | /workspace/80.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/80.xbar_stress_all_with_reset_error.576903407 |
| Short name | T1389 |
| Test name | |
| Test status | |
| Simulation time | 5051167075 ps |
| CPU time | 192.42 seconds |
| Started | Jun 28 08:49:44 PM PDT 24 |
| Finished | Jun 28 08:53:16 PM PDT 24 |
| Peak memory | 575424 kb |
| Host | smart-3e56e795-b99a-4c56-bc31-967961bfc97c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=576903407 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 80.xbar_stress_all _with_reset_error.576903407 |
| Directory | /workspace/80.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/80.xbar_unmapped_addr.229879911 |
| Short name | T1677 |
| Test name | |
| Test status | |
| Simulation time | 250829518 ps |
| CPU time | 29.57 seconds |
| Started | Jun 28 08:49:03 PM PDT 24 |
| Finished | Jun 28 08:49:41 PM PDT 24 |
| Peak memory | 575292 kb |
| Host | smart-15c38560-612f-4b17-9aeb-954a78d054ce |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=229879911 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 80.xbar_unmapped_addr.229879911 |
| Directory | /workspace/80.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/81.xbar_access_same_device.4132989477 |
| Short name | T1821 |
| Test name | |
| Test status | |
| Simulation time | 2182686857 ps |
| CPU time | 101.2 seconds |
| Started | Jun 28 08:49:49 PM PDT 24 |
| Finished | Jun 28 08:51:56 PM PDT 24 |
| Peak memory | 575328 kb |
| Host | smart-d6021127-45f9-4377-b6e3-bbd6afefa312 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4132989477 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 81.xbar_access_same_device .4132989477 |
| Directory | /workspace/81.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/81.xbar_access_same_device_slow_rsp.2554744101 |
| Short name | T2621 |
| Test name | |
| Test status | |
| Simulation time | 89701054995 ps |
| CPU time | 1501.54 seconds |
| Started | Jun 28 08:49:54 PM PDT 24 |
| Finished | Jun 28 09:15:28 PM PDT 24 |
| Peak memory | 575388 kb |
| Host | smart-b571016d-b6f5-4b2d-aedf-8d927153d1ad |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2554744101 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 81.xbar_access_same_ device_slow_rsp.2554744101 |
| Directory | /workspace/81.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/81.xbar_error_and_unmapped_addr.2252110219 |
| Short name | T2281 |
| Test name | |
| Test status | |
| Simulation time | 79151426 ps |
| CPU time | 10.73 seconds |
| Started | Jun 28 08:49:52 PM PDT 24 |
| Finished | Jun 28 08:50:29 PM PDT 24 |
| Peak memory | 574436 kb |
| Host | smart-daebd4f8-985f-4449-8242-85606e45492c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2252110219 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 81.xbar_error_and_unmapped_add r.2252110219 |
| Directory | /workspace/81.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/81.xbar_error_random.1308312942 |
| Short name | T1440 |
| Test name | |
| Test status | |
| Simulation time | 242579468 ps |
| CPU time | 19.65 seconds |
| Started | Jun 28 08:49:49 PM PDT 24 |
| Finished | Jun 28 08:50:32 PM PDT 24 |
| Peak memory | 574384 kb |
| Host | smart-42efebad-850d-41c9-90a0-a926bb8610d0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1308312942 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 81.xbar_error_random.1308312942 |
| Directory | /workspace/81.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/81.xbar_random.1697057087 |
| Short name | T1509 |
| Test name | |
| Test status | |
| Simulation time | 108556439 ps |
| CPU time | 7.05 seconds |
| Started | Jun 28 08:49:45 PM PDT 24 |
| Finished | Jun 28 08:50:12 PM PDT 24 |
| Peak memory | 565948 kb |
| Host | smart-c383fe57-8971-4543-98cd-5bbb999e530d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1697057087 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 81.xbar_random.1697057087 |
| Directory | /workspace/81.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/81.xbar_random_large_delays.826419106 |
| Short name | T2112 |
| Test name | |
| Test status | |
| Simulation time | 86232894532 ps |
| CPU time | 856.07 seconds |
| Started | Jun 28 08:49:48 PM PDT 24 |
| Finished | Jun 28 09:04:29 PM PDT 24 |
| Peak memory | 575500 kb |
| Host | smart-052f9d66-7449-48c9-ac2b-87b54d2670c2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=826419106 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 81.xbar_random_large_delays.826419106 |
| Directory | /workspace/81.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/81.xbar_random_slow_rsp.4184207871 |
| Short name | T2829 |
| Test name | |
| Test status | |
| Simulation time | 46314554808 ps |
| CPU time | 823.49 seconds |
| Started | Jun 28 08:49:50 PM PDT 24 |
| Finished | Jun 28 09:03:59 PM PDT 24 |
| Peak memory | 574196 kb |
| Host | smart-4d4e6f35-3baa-4e41-96fc-eb433de0cd1b |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4184207871 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 81.xbar_random_slow_rsp.4184207871 |
| Directory | /workspace/81.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/81.xbar_random_zero_delays.2232546087 |
| Short name | T592 |
| Test name | |
| Test status | |
| Simulation time | 347756687 ps |
| CPU time | 32.6 seconds |
| Started | Jun 28 08:49:49 PM PDT 24 |
| Finished | Jun 28 08:50:46 PM PDT 24 |
| Peak memory | 575212 kb |
| Host | smart-8092cf5d-67d3-4b60-b3df-44f58fadfa65 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2232546087 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 81.xbar_random_zero_del ays.2232546087 |
| Directory | /workspace/81.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/81.xbar_same_source.221097969 |
| Short name | T603 |
| Test name | |
| Test status | |
| Simulation time | 2239718361 ps |
| CPU time | 75.83 seconds |
| Started | Jun 28 08:49:51 PM PDT 24 |
| Finished | Jun 28 08:51:34 PM PDT 24 |
| Peak memory | 575268 kb |
| Host | smart-e6903986-839d-4ada-9018-9414fc6badf5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=221097969 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 81.xbar_same_source.221097969 |
| Directory | /workspace/81.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/81.xbar_smoke.1901014749 |
| Short name | T2798 |
| Test name | |
| Test status | |
| Simulation time | 163504290 ps |
| CPU time | 8.13 seconds |
| Started | Jun 28 08:49:50 PM PDT 24 |
| Finished | Jun 28 08:50:23 PM PDT 24 |
| Peak memory | 574172 kb |
| Host | smart-782cac58-ea8b-45fb-8721-27f64bed0efc |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1901014749 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 81.xbar_smoke.1901014749 |
| Directory | /workspace/81.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/81.xbar_smoke_large_delays.3408280526 |
| Short name | T1561 |
| Test name | |
| Test status | |
| Simulation time | 9833499139 ps |
| CPU time | 105.48 seconds |
| Started | Jun 28 08:49:46 PM PDT 24 |
| Finished | Jun 28 08:51:52 PM PDT 24 |
| Peak memory | 574264 kb |
| Host | smart-1443ef44-3cec-4981-982d-b7099d5ce196 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3408280526 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 81.xbar_smoke_large_delays.3408280526 |
| Directory | /workspace/81.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/81.xbar_smoke_slow_rsp.2098496717 |
| Short name | T1365 |
| Test name | |
| Test status | |
| Simulation time | 3461525100 ps |
| CPU time | 59.4 seconds |
| Started | Jun 28 08:49:45 PM PDT 24 |
| Finished | Jun 28 08:51:05 PM PDT 24 |
| Peak memory | 574244 kb |
| Host | smart-bf03d5f0-dae6-4478-813d-61335ee3008d |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2098496717 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 81.xbar_smoke_slow_rsp.2098496717 |
| Directory | /workspace/81.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/81.xbar_smoke_zero_delays.3962316749 |
| Short name | T2022 |
| Test name | |
| Test status | |
| Simulation time | 50311682 ps |
| CPU time | 6.98 seconds |
| Started | Jun 28 08:49:46 PM PDT 24 |
| Finished | Jun 28 08:50:15 PM PDT 24 |
| Peak memory | 574200 kb |
| Host | smart-f9f69950-6683-4f7a-aca9-c9744df5e490 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3962316749 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 81.xbar_smoke_zero_delay s.3962316749 |
| Directory | /workspace/81.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/81.xbar_stress_all.4193106414 |
| Short name | T1533 |
| Test name | |
| Test status | |
| Simulation time | 418964184 ps |
| CPU time | 33.71 seconds |
| Started | Jun 28 08:49:49 PM PDT 24 |
| Finished | Jun 28 08:50:46 PM PDT 24 |
| Peak memory | 575268 kb |
| Host | smart-114ce51e-fcd8-4f5e-b892-af16ddf45291 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4193106414 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 81.xbar_stress_all.4193106414 |
| Directory | /workspace/81.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/81.xbar_stress_all_with_error.2238097597 |
| Short name | T2359 |
| Test name | |
| Test status | |
| Simulation time | 969042813 ps |
| CPU time | 83.29 seconds |
| Started | Jun 28 08:49:45 PM PDT 24 |
| Finished | Jun 28 08:51:28 PM PDT 24 |
| Peak memory | 574464 kb |
| Host | smart-c8e8b629-a8ef-4c96-8f48-58b9d3d2c03a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2238097597 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 81.xbar_stress_all_with_error.2238097597 |
| Directory | /workspace/81.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/81.xbar_stress_all_with_rand_reset.3986510200 |
| Short name | T2169 |
| Test name | |
| Test status | |
| Simulation time | 4715006876 ps |
| CPU time | 361.02 seconds |
| Started | Jun 28 08:49:50 PM PDT 24 |
| Finished | Jun 28 08:56:16 PM PDT 24 |
| Peak memory | 576440 kb |
| Host | smart-979af395-5b83-4a04-a74a-4bde51614947 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3986510200 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 81.xbar_stress_all _with_rand_reset.3986510200 |
| Directory | /workspace/81.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/81.xbar_stress_all_with_reset_error.4064209342 |
| Short name | T843 |
| Test name | |
| Test status | |
| Simulation time | 601625768 ps |
| CPU time | 164.26 seconds |
| Started | Jun 28 08:49:50 PM PDT 24 |
| Finished | Jun 28 08:52:59 PM PDT 24 |
| Peak memory | 575380 kb |
| Host | smart-1055245a-da89-4e76-bf91-477cafeedd95 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4064209342 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 81.xbar_stress_al l_with_reset_error.4064209342 |
| Directory | /workspace/81.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/81.xbar_unmapped_addr.616225709 |
| Short name | T1400 |
| Test name | |
| Test status | |
| Simulation time | 130348398 ps |
| CPU time | 9.02 seconds |
| Started | Jun 28 08:49:49 PM PDT 24 |
| Finished | Jun 28 08:50:23 PM PDT 24 |
| Peak memory | 574140 kb |
| Host | smart-829c5400-80ee-4d7a-9bbb-b0ac39f83a72 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=616225709 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 81.xbar_unmapped_addr.616225709 |
| Directory | /workspace/81.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/82.xbar_access_same_device.3640151487 |
| Short name | T804 |
| Test name | |
| Test status | |
| Simulation time | 322845220 ps |
| CPU time | 20.68 seconds |
| Started | Jun 28 08:49:47 PM PDT 24 |
| Finished | Jun 28 08:50:31 PM PDT 24 |
| Peak memory | 574160 kb |
| Host | smart-2f159913-3f70-46d2-830d-ffda492fb0ec |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3640151487 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 82.xbar_access_same_device .3640151487 |
| Directory | /workspace/82.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/82.xbar_access_same_device_slow_rsp.2618446476 |
| Short name | T1931 |
| Test name | |
| Test status | |
| Simulation time | 91728532483 ps |
| CPU time | 1626.99 seconds |
| Started | Jun 28 08:49:45 PM PDT 24 |
| Finished | Jun 28 09:17:12 PM PDT 24 |
| Peak memory | 575468 kb |
| Host | smart-2fb85ba6-d1e8-43ad-aed6-98a6f3b998f3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2618446476 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 82.xbar_access_same_ device_slow_rsp.2618446476 |
| Directory | /workspace/82.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/82.xbar_error_and_unmapped_addr.3788729302 |
| Short name | T1700 |
| Test name | |
| Test status | |
| Simulation time | 196048431 ps |
| CPU time | 23.1 seconds |
| Started | Jun 28 08:49:50 PM PDT 24 |
| Finished | Jun 28 08:50:38 PM PDT 24 |
| Peak memory | 574148 kb |
| Host | smart-5ebad34e-a3a8-4182-896e-853deb84c2f7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3788729302 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 82.xbar_error_and_unmapped_add r.3788729302 |
| Directory | /workspace/82.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/82.xbar_error_random.1418136071 |
| Short name | T2480 |
| Test name | |
| Test status | |
| Simulation time | 62560657 ps |
| CPU time | 7.6 seconds |
| Started | Jun 28 08:49:47 PM PDT 24 |
| Finished | Jun 28 08:50:18 PM PDT 24 |
| Peak memory | 574432 kb |
| Host | smart-07943299-7fc2-4a49-8beb-f0afce11ac99 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1418136071 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 82.xbar_error_random.1418136071 |
| Directory | /workspace/82.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/82.xbar_random.2200463542 |
| Short name | T1816 |
| Test name | |
| Test status | |
| Simulation time | 667135281 ps |
| CPU time | 28.02 seconds |
| Started | Jun 28 08:49:48 PM PDT 24 |
| Finished | Jun 28 08:50:38 PM PDT 24 |
| Peak memory | 574172 kb |
| Host | smart-087e76ab-8629-46ec-bd94-a29728eaa2b9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2200463542 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 82.xbar_random.2200463542 |
| Directory | /workspace/82.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/82.xbar_random_large_delays.2315379174 |
| Short name | T1884 |
| Test name | |
| Test status | |
| Simulation time | 103577993086 ps |
| CPU time | 1094.91 seconds |
| Started | Jun 28 08:49:45 PM PDT 24 |
| Finished | Jun 28 09:08:20 PM PDT 24 |
| Peak memory | 575292 kb |
| Host | smart-dbe423bc-2247-4cd1-9826-6f68b5266e4e |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2315379174 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 82.xbar_random_large_delays.2315379174 |
| Directory | /workspace/82.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/82.xbar_random_slow_rsp.3045719092 |
| Short name | T608 |
| Test name | |
| Test status | |
| Simulation time | 8264156388 ps |
| CPU time | 139.34 seconds |
| Started | Jun 28 08:49:48 PM PDT 24 |
| Finished | Jun 28 08:52:30 PM PDT 24 |
| Peak memory | 575336 kb |
| Host | smart-9b621df9-b91d-4930-b732-88a7174a40c8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3045719092 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 82.xbar_random_slow_rsp.3045719092 |
| Directory | /workspace/82.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/82.xbar_random_zero_delays.284680988 |
| Short name | T1947 |
| Test name | |
| Test status | |
| Simulation time | 492881774 ps |
| CPU time | 46.41 seconds |
| Started | Jun 28 08:49:50 PM PDT 24 |
| Finished | Jun 28 08:51:02 PM PDT 24 |
| Peak memory | 575244 kb |
| Host | smart-89dc34dd-6afc-48cc-9a64-f38d7e7174dd |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=284680988 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 82.xbar_random_zero_dela ys.284680988 |
| Directory | /workspace/82.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/82.xbar_same_source.2872797059 |
| Short name | T1845 |
| Test name | |
| Test status | |
| Simulation time | 856206602 ps |
| CPU time | 27.83 seconds |
| Started | Jun 28 08:49:49 PM PDT 24 |
| Finished | Jun 28 08:50:42 PM PDT 24 |
| Peak memory | 575184 kb |
| Host | smart-529af502-55d9-4a86-af29-8b9ef1d4e06a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2872797059 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 82.xbar_same_source.2872797059 |
| Directory | /workspace/82.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/82.xbar_smoke.1517368161 |
| Short name | T1600 |
| Test name | |
| Test status | |
| Simulation time | 184833290 ps |
| CPU time | 8.76 seconds |
| Started | Jun 28 08:49:48 PM PDT 24 |
| Finished | Jun 28 08:50:19 PM PDT 24 |
| Peak memory | 574184 kb |
| Host | smart-c650f1e2-1ced-4922-b2fc-7a4a850c4a8d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1517368161 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 82.xbar_smoke.1517368161 |
| Directory | /workspace/82.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/82.xbar_smoke_large_delays.1955275022 |
| Short name | T2099 |
| Test name | |
| Test status | |
| Simulation time | 6362071415 ps |
| CPU time | 65.48 seconds |
| Started | Jun 28 08:49:49 PM PDT 24 |
| Finished | Jun 28 08:51:19 PM PDT 24 |
| Peak memory | 566008 kb |
| Host | smart-1764780a-130a-44c7-b018-82c5fb40094b |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1955275022 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 82.xbar_smoke_large_delays.1955275022 |
| Directory | /workspace/82.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/82.xbar_smoke_slow_rsp.966091832 |
| Short name | T1431 |
| Test name | |
| Test status | |
| Simulation time | 4199377933 ps |
| CPU time | 69.01 seconds |
| Started | Jun 28 08:49:52 PM PDT 24 |
| Finished | Jun 28 08:51:27 PM PDT 24 |
| Peak memory | 565964 kb |
| Host | smart-924991fa-2436-4267-a78d-ece600a1e8ef |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=966091832 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 82.xbar_smoke_slow_rsp.966091832 |
| Directory | /workspace/82.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/82.xbar_smoke_zero_delays.818477112 |
| Short name | T2870 |
| Test name | |
| Test status | |
| Simulation time | 45986760 ps |
| CPU time | 6.81 seconds |
| Started | Jun 28 08:49:46 PM PDT 24 |
| Finished | Jun 28 08:50:14 PM PDT 24 |
| Peak memory | 574196 kb |
| Host | smart-0b6a68ef-9aec-48ae-8064-097dc1f04f51 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=818477112 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 82.xbar_smoke_zero_delays .818477112 |
| Directory | /workspace/82.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/82.xbar_stress_all.131295923 |
| Short name | T2679 |
| Test name | |
| Test status | |
| Simulation time | 1171196496 ps |
| CPU time | 87.79 seconds |
| Started | Jun 28 08:49:49 PM PDT 24 |
| Finished | Jun 28 08:51:41 PM PDT 24 |
| Peak memory | 575332 kb |
| Host | smart-2422842e-3660-449e-87bc-df3d48fc8e4c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=131295923 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 82.xbar_stress_all.131295923 |
| Directory | /workspace/82.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/82.xbar_stress_all_with_error.1499666536 |
| Short name | T2864 |
| Test name | |
| Test status | |
| Simulation time | 9952903388 ps |
| CPU time | 384.21 seconds |
| Started | Jun 28 08:49:45 PM PDT 24 |
| Finished | Jun 28 08:56:29 PM PDT 24 |
| Peak memory | 574392 kb |
| Host | smart-d0385f0a-374b-4fb3-84a4-6235788b89d2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1499666536 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 82.xbar_stress_all_with_error.1499666536 |
| Directory | /workspace/82.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/82.xbar_stress_all_with_rand_reset.232318854 |
| Short name | T2762 |
| Test name | |
| Test status | |
| Simulation time | 3938792221 ps |
| CPU time | 428.2 seconds |
| Started | Jun 28 08:49:46 PM PDT 24 |
| Finished | Jun 28 08:57:17 PM PDT 24 |
| Peak memory | 574400 kb |
| Host | smart-9ce4fcbb-6163-4c42-b17c-c6ac97ba0645 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=232318854 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_res et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 82.xbar_stress_all_ with_rand_reset.232318854 |
| Directory | /workspace/82.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/82.xbar_stress_all_with_reset_error.2696610264 |
| Short name | T2601 |
| Test name | |
| Test status | |
| Simulation time | 14837914899 ps |
| CPU time | 647.12 seconds |
| Started | Jun 28 08:49:48 PM PDT 24 |
| Finished | Jun 28 09:01:00 PM PDT 24 |
| Peak memory | 576576 kb |
| Host | smart-75c8a056-94b5-4505-bb96-240c0139d5bf |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2696610264 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 82.xbar_stress_al l_with_reset_error.2696610264 |
| Directory | /workspace/82.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/82.xbar_unmapped_addr.4203042165 |
| Short name | T2375 |
| Test name | |
| Test status | |
| Simulation time | 122308611 ps |
| CPU time | 17.13 seconds |
| Started | Jun 28 08:49:48 PM PDT 24 |
| Finished | Jun 28 08:50:30 PM PDT 24 |
| Peak memory | 574212 kb |
| Host | smart-0bbf707d-78d3-424e-8074-48cea573d8e0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4203042165 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 82.xbar_unmapped_addr.4203042165 |
| Directory | /workspace/82.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/83.xbar_access_same_device.3015875636 |
| Short name | T1989 |
| Test name | |
| Test status | |
| Simulation time | 922060318 ps |
| CPU time | 46.77 seconds |
| Started | Jun 28 08:49:49 PM PDT 24 |
| Finished | Jun 28 08:51:00 PM PDT 24 |
| Peak memory | 575208 kb |
| Host | smart-0cc83dd2-c546-4398-b636-07106f9608c5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3015875636 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 83.xbar_access_same_device .3015875636 |
| Directory | /workspace/83.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/83.xbar_access_same_device_slow_rsp.2405999227 |
| Short name | T2662 |
| Test name | |
| Test status | |
| Simulation time | 130498485718 ps |
| CPU time | 2160.54 seconds |
| Started | Jun 28 08:49:54 PM PDT 24 |
| Finished | Jun 28 09:26:28 PM PDT 24 |
| Peak memory | 575392 kb |
| Host | smart-c1139318-56f0-4f6e-be04-10da79f3b279 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2405999227 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 83.xbar_access_same_ device_slow_rsp.2405999227 |
| Directory | /workspace/83.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/83.xbar_error_and_unmapped_addr.2474438700 |
| Short name | T2180 |
| Test name | |
| Test status | |
| Simulation time | 298808058 ps |
| CPU time | 14.85 seconds |
| Started | Jun 28 08:49:49 PM PDT 24 |
| Finished | Jun 28 08:50:29 PM PDT 24 |
| Peak memory | 574444 kb |
| Host | smart-5d195d3a-c6d9-4d69-98e7-2bccc98736c5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2474438700 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 83.xbar_error_and_unmapped_add r.2474438700 |
| Directory | /workspace/83.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/83.xbar_error_random.1457743169 |
| Short name | T1712 |
| Test name | |
| Test status | |
| Simulation time | 581289058 ps |
| CPU time | 21.43 seconds |
| Started | Jun 28 08:49:54 PM PDT 24 |
| Finished | Jun 28 08:50:49 PM PDT 24 |
| Peak memory | 573812 kb |
| Host | smart-f76d67eb-09bd-4075-9f5b-a6f5c9a31c73 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1457743169 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 83.xbar_error_random.1457743169 |
| Directory | /workspace/83.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/83.xbar_random.1308918817 |
| Short name | T2374 |
| Test name | |
| Test status | |
| Simulation time | 1783143035 ps |
| CPU time | 65.12 seconds |
| Started | Jun 28 08:49:51 PM PDT 24 |
| Finished | Jun 28 08:51:23 PM PDT 24 |
| Peak memory | 574176 kb |
| Host | smart-124cb633-3dfa-463f-9314-5c18fa95ec52 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1308918817 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 83.xbar_random.1308918817 |
| Directory | /workspace/83.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/83.xbar_random_large_delays.3105515707 |
| Short name | T1913 |
| Test name | |
| Test status | |
| Simulation time | 48029976713 ps |
| CPU time | 506.78 seconds |
| Started | Jun 28 08:49:48 PM PDT 24 |
| Finished | Jun 28 08:58:40 PM PDT 24 |
| Peak memory | 574256 kb |
| Host | smart-412158ac-c2c8-444b-ab97-e41e38b6815e |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3105515707 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 83.xbar_random_large_delays.3105515707 |
| Directory | /workspace/83.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/83.xbar_random_slow_rsp.3786953062 |
| Short name | T2201 |
| Test name | |
| Test status | |
| Simulation time | 59500354834 ps |
| CPU time | 1080.47 seconds |
| Started | Jun 28 08:49:49 PM PDT 24 |
| Finished | Jun 28 09:08:14 PM PDT 24 |
| Peak memory | 575344 kb |
| Host | smart-42c76e00-28ec-4d4e-aea4-2e3716d66036 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3786953062 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 83.xbar_random_slow_rsp.3786953062 |
| Directory | /workspace/83.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/83.xbar_random_zero_delays.1161676059 |
| Short name | T2544 |
| Test name | |
| Test status | |
| Simulation time | 383316683 ps |
| CPU time | 34.91 seconds |
| Started | Jun 28 08:49:49 PM PDT 24 |
| Finished | Jun 28 08:50:50 PM PDT 24 |
| Peak memory | 575212 kb |
| Host | smart-e43b5290-f946-4e17-ad05-fac2e60a4db1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1161676059 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 83.xbar_random_zero_del ays.1161676059 |
| Directory | /workspace/83.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/83.xbar_same_source.1702560121 |
| Short name | T2856 |
| Test name | |
| Test status | |
| Simulation time | 1637495719 ps |
| CPU time | 48.32 seconds |
| Started | Jun 28 08:49:53 PM PDT 24 |
| Finished | Jun 28 08:51:10 PM PDT 24 |
| Peak memory | 575220 kb |
| Host | smart-cbeca8a1-e94b-4d41-99db-a2c9c7b415be |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1702560121 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 83.xbar_same_source.1702560121 |
| Directory | /workspace/83.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/83.xbar_smoke.251844621 |
| Short name | T1558 |
| Test name | |
| Test status | |
| Simulation time | 47694090 ps |
| CPU time | 6.67 seconds |
| Started | Jun 28 08:49:46 PM PDT 24 |
| Finished | Jun 28 08:50:14 PM PDT 24 |
| Peak memory | 565892 kb |
| Host | smart-3eda2126-35f7-474f-8a85-02792aa070ee |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=251844621 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 83.xbar_smoke.251844621 |
| Directory | /workspace/83.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/83.xbar_smoke_large_delays.3886311276 |
| Short name | T2703 |
| Test name | |
| Test status | |
| Simulation time | 10760799864 ps |
| CPU time | 108.72 seconds |
| Started | Jun 28 08:49:52 PM PDT 24 |
| Finished | Jun 28 08:52:07 PM PDT 24 |
| Peak memory | 574256 kb |
| Host | smart-0160aef9-5f65-42a7-ada9-3134c9f4fd60 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3886311276 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 83.xbar_smoke_large_delays.3886311276 |
| Directory | /workspace/83.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/83.xbar_smoke_slow_rsp.1107891928 |
| Short name | T1735 |
| Test name | |
| Test status | |
| Simulation time | 5060965468 ps |
| CPU time | 86.61 seconds |
| Started | Jun 28 08:49:46 PM PDT 24 |
| Finished | Jun 28 08:51:34 PM PDT 24 |
| Peak memory | 566028 kb |
| Host | smart-dd2a5af1-2cb1-45d2-aeed-2f3d46145086 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1107891928 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 83.xbar_smoke_slow_rsp.1107891928 |
| Directory | /workspace/83.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/83.xbar_smoke_zero_delays.1871259729 |
| Short name | T2737 |
| Test name | |
| Test status | |
| Simulation time | 48914364 ps |
| CPU time | 6.88 seconds |
| Started | Jun 28 08:49:46 PM PDT 24 |
| Finished | Jun 28 08:50:15 PM PDT 24 |
| Peak memory | 574136 kb |
| Host | smart-bbd805ce-be1a-40ea-a6bb-95c5ea62ac7c |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1871259729 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 83.xbar_smoke_zero_delay s.1871259729 |
| Directory | /workspace/83.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/83.xbar_stress_all.3703989548 |
| Short name | T1971 |
| Test name | |
| Test status | |
| Simulation time | 4206092656 ps |
| CPU time | 193.42 seconds |
| Started | Jun 28 08:49:50 PM PDT 24 |
| Finished | Jun 28 08:53:28 PM PDT 24 |
| Peak memory | 575356 kb |
| Host | smart-fae9742d-4ec9-48ac-b914-a6b9b63bd0d1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3703989548 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 83.xbar_stress_all.3703989548 |
| Directory | /workspace/83.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/83.xbar_stress_all_with_error.73846023 |
| Short name | T2623 |
| Test name | |
| Test status | |
| Simulation time | 7777301860 ps |
| CPU time | 286.8 seconds |
| Started | Jun 28 08:49:52 PM PDT 24 |
| Finished | Jun 28 08:55:08 PM PDT 24 |
| Peak memory | 574616 kb |
| Host | smart-19a7c0bc-c006-4ea4-8ee5-5ae237aa0fd4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73846023 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 83.xbar_stress_all_with_error.73846023 |
| Directory | /workspace/83.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/83.xbar_stress_all_with_rand_reset.2656916812 |
| Short name | T846 |
| Test name | |
| Test status | |
| Simulation time | 71452784 ps |
| CPU time | 43.45 seconds |
| Started | Jun 28 08:49:50 PM PDT 24 |
| Finished | Jun 28 08:50:59 PM PDT 24 |
| Peak memory | 574368 kb |
| Host | smart-acb9608e-ae21-480d-9a3e-4779173c0380 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2656916812 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 83.xbar_stress_all _with_rand_reset.2656916812 |
| Directory | /workspace/83.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/83.xbar_stress_all_with_reset_error.3400142610 |
| Short name | T2108 |
| Test name | |
| Test status | |
| Simulation time | 5143384592 ps |
| CPU time | 546.31 seconds |
| Started | Jun 28 08:49:47 PM PDT 24 |
| Finished | Jun 28 08:59:16 PM PDT 24 |
| Peak memory | 574664 kb |
| Host | smart-f201f629-b72f-4b06-bd04-6ac9de7153a9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3400142610 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 83.xbar_stress_al l_with_reset_error.3400142610 |
| Directory | /workspace/83.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/83.xbar_unmapped_addr.2172196992 |
| Short name | T596 |
| Test name | |
| Test status | |
| Simulation time | 637427409 ps |
| CPU time | 25.41 seconds |
| Started | Jun 28 08:49:58 PM PDT 24 |
| Finished | Jun 28 08:50:58 PM PDT 24 |
| Peak memory | 575268 kb |
| Host | smart-8b37c278-8ef3-4dfb-bf03-2ce1acf44dc6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2172196992 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 83.xbar_unmapped_addr.2172196992 |
| Directory | /workspace/83.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/84.xbar_access_same_device.680709121 |
| Short name | T819 |
| Test name | |
| Test status | |
| Simulation time | 121288632 ps |
| CPU time | 11.95 seconds |
| Started | Jun 28 08:50:09 PM PDT 24 |
| Finished | Jun 28 08:51:02 PM PDT 24 |
| Peak memory | 575040 kb |
| Host | smart-d1a6ace4-8479-4f69-bb94-a3fd6ca94ee0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=680709121 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 84.xbar_access_same_device. 680709121 |
| Directory | /workspace/84.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/84.xbar_access_same_device_slow_rsp.1138299142 |
| Short name | T1836 |
| Test name | |
| Test status | |
| Simulation time | 99492105629 ps |
| CPU time | 1815.62 seconds |
| Started | Jun 28 08:50:05 PM PDT 24 |
| Finished | Jun 28 09:20:59 PM PDT 24 |
| Peak memory | 575440 kb |
| Host | smart-579a7cef-988e-459d-990f-ca10680c64fc |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1138299142 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 84.xbar_access_same_ device_slow_rsp.1138299142 |
| Directory | /workspace/84.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/84.xbar_error_and_unmapped_addr.3726765683 |
| Short name | T1798 |
| Test name | |
| Test status | |
| Simulation time | 131226868 ps |
| CPU time | 16.04 seconds |
| Started | Jun 28 08:50:10 PM PDT 24 |
| Finished | Jun 28 08:51:06 PM PDT 24 |
| Peak memory | 574188 kb |
| Host | smart-905e72db-c24d-47ed-bc05-5bbed62873d6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3726765683 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 84.xbar_error_and_unmapped_add r.3726765683 |
| Directory | /workspace/84.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/84.xbar_error_random.884644551 |
| Short name | T2129 |
| Test name | |
| Test status | |
| Simulation time | 334996691 ps |
| CPU time | 30.56 seconds |
| Started | Jun 28 08:50:10 PM PDT 24 |
| Finished | Jun 28 08:51:21 PM PDT 24 |
| Peak memory | 573728 kb |
| Host | smart-030be2da-e108-4c78-b02d-032f4acf2d90 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=884644551 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 84.xbar_error_random.884644551 |
| Directory | /workspace/84.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/84.xbar_random.1729899961 |
| Short name | T1540 |
| Test name | |
| Test status | |
| Simulation time | 183052394 ps |
| CPU time | 20.8 seconds |
| Started | Jun 28 08:49:52 PM PDT 24 |
| Finished | Jun 28 08:50:42 PM PDT 24 |
| Peak memory | 575252 kb |
| Host | smart-4e0ac7dd-a4a1-48f5-93ee-f320d1069b76 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1729899961 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 84.xbar_random.1729899961 |
| Directory | /workspace/84.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/84.xbar_random_large_delays.3771619606 |
| Short name | T1524 |
| Test name | |
| Test status | |
| Simulation time | 41273977467 ps |
| CPU time | 404.67 seconds |
| Started | Jun 28 08:49:57 PM PDT 24 |
| Finished | Jun 28 08:57:18 PM PDT 24 |
| Peak memory | 575288 kb |
| Host | smart-5aa4a516-749a-44c8-9c57-d3ab67cf541f |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3771619606 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 84.xbar_random_large_delays.3771619606 |
| Directory | /workspace/84.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/84.xbar_random_slow_rsp.4061495225 |
| Short name | T579 |
| Test name | |
| Test status | |
| Simulation time | 27871809576 ps |
| CPU time | 476.88 seconds |
| Started | Jun 28 08:50:09 PM PDT 24 |
| Finished | Jun 28 08:58:46 PM PDT 24 |
| Peak memory | 575240 kb |
| Host | smart-8fcfcd94-d60e-4802-baad-780dd85c0e69 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4061495225 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 84.xbar_random_slow_rsp.4061495225 |
| Directory | /workspace/84.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/84.xbar_random_zero_delays.2566192957 |
| Short name | T2028 |
| Test name | |
| Test status | |
| Simulation time | 157245242 ps |
| CPU time | 14.22 seconds |
| Started | Jun 28 08:49:52 PM PDT 24 |
| Finished | Jun 28 08:50:32 PM PDT 24 |
| Peak memory | 575148 kb |
| Host | smart-813b02a3-699e-48cb-8700-25e50426cb22 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2566192957 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 84.xbar_random_zero_del ays.2566192957 |
| Directory | /workspace/84.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/84.xbar_same_source.698010814 |
| Short name | T455 |
| Test name | |
| Test status | |
| Simulation time | 2159513562 ps |
| CPU time | 60.16 seconds |
| Started | Jun 28 08:50:00 PM PDT 24 |
| Finished | Jun 28 08:51:38 PM PDT 24 |
| Peak memory | 575300 kb |
| Host | smart-27dafa2d-88d2-468c-b067-53d7662bdb40 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=698010814 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 84.xbar_same_source.698010814 |
| Directory | /workspace/84.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/84.xbar_smoke.886092426 |
| Short name | T2227 |
| Test name | |
| Test status | |
| Simulation time | 157389675 ps |
| CPU time | 8.02 seconds |
| Started | Jun 28 08:49:58 PM PDT 24 |
| Finished | Jun 28 08:50:43 PM PDT 24 |
| Peak memory | 574156 kb |
| Host | smart-9ebe6fda-51e3-4328-87b1-142f660dd8d4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=886092426 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 84.xbar_smoke.886092426 |
| Directory | /workspace/84.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/84.xbar_smoke_large_delays.1222351750 |
| Short name | T2431 |
| Test name | |
| Test status | |
| Simulation time | 7743410874 ps |
| CPU time | 79.55 seconds |
| Started | Jun 28 08:49:52 PM PDT 24 |
| Finished | Jun 28 08:51:38 PM PDT 24 |
| Peak memory | 574256 kb |
| Host | smart-cdcb8d5d-e923-4f72-8c57-a2bc8eb31213 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1222351750 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 84.xbar_smoke_large_delays.1222351750 |
| Directory | /workspace/84.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/84.xbar_smoke_slow_rsp.3207278585 |
| Short name | T2074 |
| Test name | |
| Test status | |
| Simulation time | 4185297587 ps |
| CPU time | 72.14 seconds |
| Started | Jun 28 08:49:58 PM PDT 24 |
| Finished | Jun 28 08:51:48 PM PDT 24 |
| Peak memory | 565932 kb |
| Host | smart-a8c204f1-b6cd-421d-8edb-713315171588 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3207278585 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 84.xbar_smoke_slow_rsp.3207278585 |
| Directory | /workspace/84.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/84.xbar_smoke_zero_delays.3367725539 |
| Short name | T2542 |
| Test name | |
| Test status | |
| Simulation time | 46914334 ps |
| CPU time | 6.43 seconds |
| Started | Jun 28 08:49:58 PM PDT 24 |
| Finished | Jun 28 08:50:42 PM PDT 24 |
| Peak memory | 574168 kb |
| Host | smart-5319a6a2-6c0f-4545-8d75-797b206a4067 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3367725539 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 84.xbar_smoke_zero_delay s.3367725539 |
| Directory | /workspace/84.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/84.xbar_stress_all.221363810 |
| Short name | T2719 |
| Test name | |
| Test status | |
| Simulation time | 886478643 ps |
| CPU time | 67.25 seconds |
| Started | Jun 28 08:50:00 PM PDT 24 |
| Finished | Jun 28 08:51:46 PM PDT 24 |
| Peak memory | 575380 kb |
| Host | smart-3df84536-8e9b-40c8-b2f6-0eea509f1bf9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=221363810 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 84.xbar_stress_all.221363810 |
| Directory | /workspace/84.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/84.xbar_stress_all_with_error.467858982 |
| Short name | T789 |
| Test name | |
| Test status | |
| Simulation time | 10843344123 ps |
| CPU time | 432.47 seconds |
| Started | Jun 28 08:50:12 PM PDT 24 |
| Finished | Jun 28 08:58:05 PM PDT 24 |
| Peak memory | 574392 kb |
| Host | smart-7409d3b5-d123-4a7e-b6a7-00c316e624eb |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=467858982 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 84.xbar_stress_all_with_error.467858982 |
| Directory | /workspace/84.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/84.xbar_stress_all_with_rand_reset.3006702700 |
| Short name | T1415 |
| Test name | |
| Test status | |
| Simulation time | 471440888 ps |
| CPU time | 183.17 seconds |
| Started | Jun 28 08:50:03 PM PDT 24 |
| Finished | Jun 28 08:53:46 PM PDT 24 |
| Peak memory | 576372 kb |
| Host | smart-90a76fe2-f5a2-4c00-901d-c80f7b26edde |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3006702700 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 84.xbar_stress_all _with_rand_reset.3006702700 |
| Directory | /workspace/84.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/84.xbar_stress_all_with_reset_error.2140416905 |
| Short name | T2150 |
| Test name | |
| Test status | |
| Simulation time | 8190240656 ps |
| CPU time | 391.29 seconds |
| Started | Jun 28 08:50:06 PM PDT 24 |
| Finished | Jun 28 08:57:17 PM PDT 24 |
| Peak memory | 576440 kb |
| Host | smart-151102d1-83e7-4173-abb9-24fdf95a879c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2140416905 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 84.xbar_stress_al l_with_reset_error.2140416905 |
| Directory | /workspace/84.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/84.xbar_unmapped_addr.1801375 |
| Short name | T2553 |
| Test name | |
| Test status | |
| Simulation time | 295931761 ps |
| CPU time | 14.88 seconds |
| Started | Jun 28 08:50:06 PM PDT 24 |
| Finished | Jun 28 08:51:00 PM PDT 24 |
| Peak memory | 574184 kb |
| Host | smart-847c1ce8-52cd-4822-875a-7a15bce66779 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1801375 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 84.xbar_unmapped_addr.1801375 |
| Directory | /workspace/84.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/85.xbar_access_same_device.1256712899 |
| Short name | T1424 |
| Test name | |
| Test status | |
| Simulation time | 1629863720 ps |
| CPU time | 68.02 seconds |
| Started | Jun 28 08:50:13 PM PDT 24 |
| Finished | Jun 28 08:52:00 PM PDT 24 |
| Peak memory | 575228 kb |
| Host | smart-7503d189-4209-4382-9c39-fa590fe0b0f5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1256712899 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 85.xbar_access_same_device .1256712899 |
| Directory | /workspace/85.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/85.xbar_access_same_device_slow_rsp.784401515 |
| Short name | T2809 |
| Test name | |
| Test status | |
| Simulation time | 131954780433 ps |
| CPU time | 2097.55 seconds |
| Started | Jun 28 08:50:14 PM PDT 24 |
| Finished | Jun 28 09:25:51 PM PDT 24 |
| Peak memory | 575376 kb |
| Host | smart-bd788ce3-2fa3-41f8-9c23-0626b3dfea84 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=784401515 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 85.xbar_access_same_d evice_slow_rsp.784401515 |
| Directory | /workspace/85.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/85.xbar_error_and_unmapped_addr.1448779836 |
| Short name | T1753 |
| Test name | |
| Test status | |
| Simulation time | 264935386 ps |
| CPU time | 29.01 seconds |
| Started | Jun 28 08:50:10 PM PDT 24 |
| Finished | Jun 28 08:51:19 PM PDT 24 |
| Peak memory | 574436 kb |
| Host | smart-606b56b8-baa1-4f55-8b14-40563c842291 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1448779836 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 85.xbar_error_and_unmapped_add r.1448779836 |
| Directory | /workspace/85.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/85.xbar_error_random.3077449475 |
| Short name | T2473 |
| Test name | |
| Test status | |
| Simulation time | 940069697 ps |
| CPU time | 31.38 seconds |
| Started | Jun 28 08:50:12 PM PDT 24 |
| Finished | Jun 28 08:51:23 PM PDT 24 |
| Peak memory | 574408 kb |
| Host | smart-3bb7bce5-c33f-46dd-9ef5-435c580403af |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3077449475 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 85.xbar_error_random.3077449475 |
| Directory | /workspace/85.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/85.xbar_random.49996078 |
| Short name | T1590 |
| Test name | |
| Test status | |
| Simulation time | 460226971 ps |
| CPU time | 19.85 seconds |
| Started | Jun 28 08:50:05 PM PDT 24 |
| Finished | Jun 28 08:51:03 PM PDT 24 |
| Peak memory | 575108 kb |
| Host | smart-318fba6f-1a60-4691-98f6-bed1842fc854 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49996078 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 85.xbar_random.49996078 |
| Directory | /workspace/85.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/85.xbar_random_large_delays.2550718266 |
| Short name | T1935 |
| Test name | |
| Test status | |
| Simulation time | 73275873055 ps |
| CPU time | 725.64 seconds |
| Started | Jun 28 08:50:14 PM PDT 24 |
| Finished | Jun 28 09:02:58 PM PDT 24 |
| Peak memory | 575300 kb |
| Host | smart-a413869c-36da-4306-8c8d-b441e7926d17 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2550718266 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 85.xbar_random_large_delays.2550718266 |
| Directory | /workspace/85.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/85.xbar_random_slow_rsp.138581253 |
| Short name | T2222 |
| Test name | |
| Test status | |
| Simulation time | 64141360444 ps |
| CPU time | 1057.58 seconds |
| Started | Jun 28 08:49:58 PM PDT 24 |
| Finished | Jun 28 09:08:14 PM PDT 24 |
| Peak memory | 575316 kb |
| Host | smart-662b0d08-664d-4bbd-9e4e-ae6d26c92768 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=138581253 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 85.xbar_random_slow_rsp.138581253 |
| Directory | /workspace/85.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/85.xbar_random_zero_delays.1950700856 |
| Short name | T2854 |
| Test name | |
| Test status | |
| Simulation time | 312947628 ps |
| CPU time | 32.39 seconds |
| Started | Jun 28 08:50:01 PM PDT 24 |
| Finished | Jun 28 08:51:12 PM PDT 24 |
| Peak memory | 575240 kb |
| Host | smart-abd24dad-9b61-400c-a2ab-0dd67ece7b0e |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1950700856 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 85.xbar_random_zero_del ays.1950700856 |
| Directory | /workspace/85.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/85.xbar_same_source.2417266928 |
| Short name | T2622 |
| Test name | |
| Test status | |
| Simulation time | 420662817 ps |
| CPU time | 33.4 seconds |
| Started | Jun 28 08:50:08 PM PDT 24 |
| Finished | Jun 28 08:51:20 PM PDT 24 |
| Peak memory | 575236 kb |
| Host | smart-4e866b84-eafb-45c9-af75-a5e0b3996768 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2417266928 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 85.xbar_same_source.2417266928 |
| Directory | /workspace/85.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/85.xbar_smoke.772519951 |
| Short name | T1401 |
| Test name | |
| Test status | |
| Simulation time | 227319945 ps |
| CPU time | 10.33 seconds |
| Started | Jun 28 08:50:10 PM PDT 24 |
| Finished | Jun 28 08:51:01 PM PDT 24 |
| Peak memory | 574096 kb |
| Host | smart-fc519168-70c9-4b92-855d-0d148950d692 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=772519951 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 85.xbar_smoke.772519951 |
| Directory | /workspace/85.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/85.xbar_smoke_large_delays.242159899 |
| Short name | T2021 |
| Test name | |
| Test status | |
| Simulation time | 7301975301 ps |
| CPU time | 76.88 seconds |
| Started | Jun 28 08:50:15 PM PDT 24 |
| Finished | Jun 28 08:52:11 PM PDT 24 |
| Peak memory | 574184 kb |
| Host | smart-d2c30a4d-e391-475e-acce-2e17e43d5fed |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=242159899 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 85.xbar_smoke_large_delays.242159899 |
| Directory | /workspace/85.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/85.xbar_smoke_slow_rsp.3032573989 |
| Short name | T1595 |
| Test name | |
| Test status | |
| Simulation time | 5157144897 ps |
| CPU time | 90.56 seconds |
| Started | Jun 28 08:50:00 PM PDT 24 |
| Finished | Jun 28 08:52:09 PM PDT 24 |
| Peak memory | 566004 kb |
| Host | smart-59b8e8d1-fac6-4185-b759-665d658751bc |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3032573989 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 85.xbar_smoke_slow_rsp.3032573989 |
| Directory | /workspace/85.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/85.xbar_smoke_zero_delays.2877842550 |
| Short name | T1686 |
| Test name | |
| Test status | |
| Simulation time | 45253147 ps |
| CPU time | 6.54 seconds |
| Started | Jun 28 08:50:15 PM PDT 24 |
| Finished | Jun 28 08:51:01 PM PDT 24 |
| Peak memory | 574116 kb |
| Host | smart-242df78d-e04e-4d7e-a25f-f4f7e0045bb2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2877842550 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 85.xbar_smoke_zero_delay s.2877842550 |
| Directory | /workspace/85.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/85.xbar_stress_all.1565293925 |
| Short name | T2005 |
| Test name | |
| Test status | |
| Simulation time | 940426900 ps |
| CPU time | 73.82 seconds |
| Started | Jun 28 08:50:02 PM PDT 24 |
| Finished | Jun 28 08:51:56 PM PDT 24 |
| Peak memory | 574240 kb |
| Host | smart-2b6a1e91-064b-481d-bad6-adf54aaf86e5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1565293925 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 85.xbar_stress_all.1565293925 |
| Directory | /workspace/85.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/85.xbar_stress_all_with_error.1481460459 |
| Short name | T2485 |
| Test name | |
| Test status | |
| Simulation time | 11985030524 ps |
| CPU time | 394.17 seconds |
| Started | Jun 28 08:50:03 PM PDT 24 |
| Finished | Jun 28 08:57:17 PM PDT 24 |
| Peak memory | 574664 kb |
| Host | smart-6d712b96-0619-4f62-9a8f-c413773a7cd5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1481460459 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 85.xbar_stress_all_with_error.1481460459 |
| Directory | /workspace/85.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/85.xbar_stress_all_with_rand_reset.681600520 |
| Short name | T1909 |
| Test name | |
| Test status | |
| Simulation time | 4674247950 ps |
| CPU time | 562.54 seconds |
| Started | Jun 28 08:50:01 PM PDT 24 |
| Finished | Jun 28 09:00:02 PM PDT 24 |
| Peak memory | 575388 kb |
| Host | smart-b70b100a-b3ef-4239-b99f-4cd329b2cea1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=681600520 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_res et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 85.xbar_stress_all_ with_rand_reset.681600520 |
| Directory | /workspace/85.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/85.xbar_stress_all_with_reset_error.1755999174 |
| Short name | T2478 |
| Test name | |
| Test status | |
| Simulation time | 10673452407 ps |
| CPU time | 471.29 seconds |
| Started | Jun 28 08:50:16 PM PDT 24 |
| Finished | Jun 28 08:58:46 PM PDT 24 |
| Peak memory | 574332 kb |
| Host | smart-4abcc5e3-5210-4bfb-8092-e7ddb7e819ce |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1755999174 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 85.xbar_stress_al l_with_reset_error.1755999174 |
| Directory | /workspace/85.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/85.xbar_unmapped_addr.3005421429 |
| Short name | T2091 |
| Test name | |
| Test status | |
| Simulation time | 884637959 ps |
| CPU time | 43.52 seconds |
| Started | Jun 28 08:50:13 PM PDT 24 |
| Finished | Jun 28 08:51:36 PM PDT 24 |
| Peak memory | 575300 kb |
| Host | smart-293bba19-7f6e-428f-bfe1-1796c4e54f76 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3005421429 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 85.xbar_unmapped_addr.3005421429 |
| Directory | /workspace/85.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/86.xbar_access_same_device.1208629390 |
| Short name | T799 |
| Test name | |
| Test status | |
| Simulation time | 1581845948 ps |
| CPU time | 76.57 seconds |
| Started | Jun 28 08:50:08 PM PDT 24 |
| Finished | Jun 28 08:52:03 PM PDT 24 |
| Peak memory | 575304 kb |
| Host | smart-96ca5aa0-a045-43b2-ac35-e60d2566f752 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1208629390 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 86.xbar_access_same_device .1208629390 |
| Directory | /workspace/86.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/86.xbar_access_same_device_slow_rsp.3473677308 |
| Short name | T2030 |
| Test name | |
| Test status | |
| Simulation time | 145179868216 ps |
| CPU time | 2382.05 seconds |
| Started | Jun 28 08:50:09 PM PDT 24 |
| Finished | Jun 28 09:30:32 PM PDT 24 |
| Peak memory | 575436 kb |
| Host | smart-e7420902-1d9d-4cba-9388-c7fa504fea0d |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3473677308 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 86.xbar_access_same_ device_slow_rsp.3473677308 |
| Directory | /workspace/86.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/86.xbar_error_and_unmapped_addr.2371350554 |
| Short name | T2401 |
| Test name | |
| Test status | |
| Simulation time | 115364541 ps |
| CPU time | 15.34 seconds |
| Started | Jun 28 08:50:00 PM PDT 24 |
| Finished | Jun 28 08:50:54 PM PDT 24 |
| Peak memory | 573820 kb |
| Host | smart-ba7eeb24-a025-4a74-9897-e630f22b47ee |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2371350554 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 86.xbar_error_and_unmapped_add r.2371350554 |
| Directory | /workspace/86.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/86.xbar_error_random.2251882441 |
| Short name | T1637 |
| Test name | |
| Test status | |
| Simulation time | 455551056 ps |
| CPU time | 33.14 seconds |
| Started | Jun 28 08:50:04 PM PDT 24 |
| Finished | Jun 28 08:51:16 PM PDT 24 |
| Peak memory | 574400 kb |
| Host | smart-34d5446a-f9df-49fc-933e-2b5a19fbacf8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2251882441 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 86.xbar_error_random.2251882441 |
| Directory | /workspace/86.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/86.xbar_random.3038309681 |
| Short name | T1707 |
| Test name | |
| Test status | |
| Simulation time | 262620341 ps |
| CPU time | 11.28 seconds |
| Started | Jun 28 08:50:12 PM PDT 24 |
| Finished | Jun 28 08:51:03 PM PDT 24 |
| Peak memory | 574232 kb |
| Host | smart-775aafa5-9c19-4783-b4ad-52c3e339acec |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3038309681 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 86.xbar_random.3038309681 |
| Directory | /workspace/86.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/86.xbar_random_large_delays.3391289076 |
| Short name | T1430 |
| Test name | |
| Test status | |
| Simulation time | 13036077415 ps |
| CPU time | 134.98 seconds |
| Started | Jun 28 08:50:14 PM PDT 24 |
| Finished | Jun 28 08:53:09 PM PDT 24 |
| Peak memory | 575268 kb |
| Host | smart-fe369f1b-0d9e-441d-b17c-7e1a2436c2e8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3391289076 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 86.xbar_random_large_delays.3391289076 |
| Directory | /workspace/86.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/86.xbar_random_slow_rsp.2201344542 |
| Short name | T2808 |
| Test name | |
| Test status | |
| Simulation time | 9861079777 ps |
| CPU time | 177.91 seconds |
| Started | Jun 28 08:50:03 PM PDT 24 |
| Finished | Jun 28 08:53:41 PM PDT 24 |
| Peak memory | 574256 kb |
| Host | smart-d2406f26-dda1-493e-a727-bc0bf2175d03 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2201344542 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 86.xbar_random_slow_rsp.2201344542 |
| Directory | /workspace/86.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/86.xbar_random_zero_delays.3657824930 |
| Short name | T2280 |
| Test name | |
| Test status | |
| Simulation time | 561281536 ps |
| CPU time | 52.87 seconds |
| Started | Jun 28 08:50:10 PM PDT 24 |
| Finished | Jun 28 08:51:43 PM PDT 24 |
| Peak memory | 575256 kb |
| Host | smart-0ab1c0da-a0b7-4fe4-9614-c785265c96e9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3657824930 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 86.xbar_random_zero_del ays.3657824930 |
| Directory | /workspace/86.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/86.xbar_same_source.3545142874 |
| Short name | T1699 |
| Test name | |
| Test status | |
| Simulation time | 2751838977 ps |
| CPU time | 87.95 seconds |
| Started | Jun 28 08:50:05 PM PDT 24 |
| Finished | Jun 28 08:52:13 PM PDT 24 |
| Peak memory | 575296 kb |
| Host | smart-e137c1e6-0a61-4a09-93a8-7304f95b88fe |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3545142874 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 86.xbar_same_source.3545142874 |
| Directory | /workspace/86.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/86.xbar_smoke.372675305 |
| Short name | T2221 |
| Test name | |
| Test status | |
| Simulation time | 151466707 ps |
| CPU time | 7.41 seconds |
| Started | Jun 28 08:50:14 PM PDT 24 |
| Finished | Jun 28 08:51:00 PM PDT 24 |
| Peak memory | 565916 kb |
| Host | smart-8d9f7ab5-4473-4ef0-bdfc-6fab9c5be96a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=372675305 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 86.xbar_smoke.372675305 |
| Directory | /workspace/86.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/86.xbar_smoke_large_delays.3720723709 |
| Short name | T2506 |
| Test name | |
| Test status | |
| Simulation time | 5878164392 ps |
| CPU time | 63.78 seconds |
| Started | Jun 28 08:50:04 PM PDT 24 |
| Finished | Jun 28 08:51:47 PM PDT 24 |
| Peak memory | 574072 kb |
| Host | smart-28e82518-0517-4945-a405-3095be428c6d |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3720723709 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 86.xbar_smoke_large_delays.3720723709 |
| Directory | /workspace/86.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/86.xbar_smoke_slow_rsp.1559720768 |
| Short name | T1851 |
| Test name | |
| Test status | |
| Simulation time | 4071126400 ps |
| CPU time | 69.96 seconds |
| Started | Jun 28 08:50:07 PM PDT 24 |
| Finished | Jun 28 08:51:57 PM PDT 24 |
| Peak memory | 574164 kb |
| Host | smart-1b3abd64-276e-4719-9323-4c7e9377e817 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1559720768 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 86.xbar_smoke_slow_rsp.1559720768 |
| Directory | /workspace/86.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/86.xbar_smoke_zero_delays.2109305507 |
| Short name | T1522 |
| Test name | |
| Test status | |
| Simulation time | 47980452 ps |
| CPU time | 6.41 seconds |
| Started | Jun 28 08:50:09 PM PDT 24 |
| Finished | Jun 28 08:50:56 PM PDT 24 |
| Peak memory | 565800 kb |
| Host | smart-d7b166ac-202b-497b-901e-805da1154065 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2109305507 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 86.xbar_smoke_zero_delay s.2109305507 |
| Directory | /workspace/86.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/86.xbar_stress_all.2062068867 |
| Short name | T2048 |
| Test name | |
| Test status | |
| Simulation time | 5145655528 ps |
| CPU time | 462.54 seconds |
| Started | Jun 28 08:50:15 PM PDT 24 |
| Finished | Jun 28 08:58:37 PM PDT 24 |
| Peak memory | 574332 kb |
| Host | smart-133c5e19-4258-47dc-8009-75406d29bd7d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2062068867 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 86.xbar_stress_all.2062068867 |
| Directory | /workspace/86.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/86.xbar_stress_all_with_error.1056613358 |
| Short name | T798 |
| Test name | |
| Test status | |
| Simulation time | 11072663362 ps |
| CPU time | 369.87 seconds |
| Started | Jun 28 08:50:10 PM PDT 24 |
| Finished | Jun 28 08:57:00 PM PDT 24 |
| Peak memory | 574420 kb |
| Host | smart-98db94cb-6037-4c69-b0ea-3a947c69cc49 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1056613358 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 86.xbar_stress_all_with_error.1056613358 |
| Directory | /workspace/86.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/86.xbar_stress_all_with_rand_reset.1664769473 |
| Short name | T1946 |
| Test name | |
| Test status | |
| Simulation time | 5120487184 ps |
| CPU time | 311.65 seconds |
| Started | Jun 28 08:50:07 PM PDT 24 |
| Finished | Jun 28 08:55:58 PM PDT 24 |
| Peak memory | 575468 kb |
| Host | smart-35319983-e3a4-4b64-8b4e-b7bd89ae46d6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1664769473 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 86.xbar_stress_all _with_rand_reset.1664769473 |
| Directory | /workspace/86.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/86.xbar_stress_all_with_reset_error.1163044663 |
| Short name | T2277 |
| Test name | |
| Test status | |
| Simulation time | 15672478566 ps |
| CPU time | 612.59 seconds |
| Started | Jun 28 08:50:07 PM PDT 24 |
| Finished | Jun 28 09:00:59 PM PDT 24 |
| Peak memory | 574384 kb |
| Host | smart-1ab47051-4feb-4800-97ed-2ff9fc695104 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1163044663 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 86.xbar_stress_al l_with_reset_error.1163044663 |
| Directory | /workspace/86.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/86.xbar_unmapped_addr.2479007388 |
| Short name | T1471 |
| Test name | |
| Test status | |
| Simulation time | 63482714 ps |
| CPU time | 9.05 seconds |
| Started | Jun 28 08:50:12 PM PDT 24 |
| Finished | Jun 28 08:51:01 PM PDT 24 |
| Peak memory | 575304 kb |
| Host | smart-df87d9dd-fb69-4c50-b003-4b84e8ac937a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2479007388 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 86.xbar_unmapped_addr.2479007388 |
| Directory | /workspace/86.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/87.xbar_access_same_device.4236092081 |
| Short name | T1578 |
| Test name | |
| Test status | |
| Simulation time | 407681855 ps |
| CPU time | 37.05 seconds |
| Started | Jun 28 08:50:10 PM PDT 24 |
| Finished | Jun 28 08:51:27 PM PDT 24 |
| Peak memory | 574152 kb |
| Host | smart-5ae3e5cc-87cb-4822-9fcc-a4be163482e0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4236092081 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 87.xbar_access_same_device .4236092081 |
| Directory | /workspace/87.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/87.xbar_access_same_device_slow_rsp.3961230055 |
| Short name | T2395 |
| Test name | |
| Test status | |
| Simulation time | 98943394335 ps |
| CPU time | 1628.37 seconds |
| Started | Jun 28 08:50:10 PM PDT 24 |
| Finished | Jun 28 09:17:59 PM PDT 24 |
| Peak memory | 575384 kb |
| Host | smart-b6f41a9e-d47d-4caa-ba9d-011b2e9da688 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3961230055 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 87.xbar_access_same_ device_slow_rsp.3961230055 |
| Directory | /workspace/87.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/87.xbar_error_and_unmapped_addr.422576932 |
| Short name | T1927 |
| Test name | |
| Test status | |
| Simulation time | 301162968 ps |
| CPU time | 34.76 seconds |
| Started | Jun 28 08:50:28 PM PDT 24 |
| Finished | Jun 28 08:51:34 PM PDT 24 |
| Peak memory | 574444 kb |
| Host | smart-9ee67a95-f4f4-4cd6-ba37-bbb76f8e625d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=422576932 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 87.xbar_error_and_unmapped_addr .422576932 |
| Directory | /workspace/87.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/87.xbar_error_random.1923953105 |
| Short name | T1535 |
| Test name | |
| Test status | |
| Simulation time | 2158534945 ps |
| CPU time | 85.34 seconds |
| Started | Jun 28 08:50:07 PM PDT 24 |
| Finished | Jun 28 08:52:12 PM PDT 24 |
| Peak memory | 574288 kb |
| Host | smart-f857ad8b-d859-4869-935e-fa1336a72e53 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1923953105 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 87.xbar_error_random.1923953105 |
| Directory | /workspace/87.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/87.xbar_random.35173729 |
| Short name | T1831 |
| Test name | |
| Test status | |
| Simulation time | 297724113 ps |
| CPU time | 27.94 seconds |
| Started | Jun 28 08:50:07 PM PDT 24 |
| Finished | Jun 28 08:51:15 PM PDT 24 |
| Peak memory | 575208 kb |
| Host | smart-b0817720-793f-4e1c-a688-7d4b3906b56a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35173729 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 87.xbar_random.35173729 |
| Directory | /workspace/87.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/87.xbar_random_large_delays.3075307352 |
| Short name | T1940 |
| Test name | |
| Test status | |
| Simulation time | 69195840703 ps |
| CPU time | 696.62 seconds |
| Started | Jun 28 08:50:12 PM PDT 24 |
| Finished | Jun 28 09:02:29 PM PDT 24 |
| Peak memory | 574256 kb |
| Host | smart-71a658e4-1e7a-4de5-a1e7-d45360c09b5d |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3075307352 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 87.xbar_random_large_delays.3075307352 |
| Directory | /workspace/87.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/87.xbar_random_slow_rsp.224305020 |
| Short name | T1815 |
| Test name | |
| Test status | |
| Simulation time | 12999272878 ps |
| CPU time | 218.83 seconds |
| Started | Jun 28 08:50:12 PM PDT 24 |
| Finished | Jun 28 08:54:31 PM PDT 24 |
| Peak memory | 575316 kb |
| Host | smart-bf99cb31-3e9a-4b78-a092-b903de3cc642 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=224305020 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 87.xbar_random_slow_rsp.224305020 |
| Directory | /workspace/87.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/87.xbar_random_zero_delays.3331968560 |
| Short name | T504 |
| Test name | |
| Test status | |
| Simulation time | 584607227 ps |
| CPU time | 51.77 seconds |
| Started | Jun 28 08:50:05 PM PDT 24 |
| Finished | Jun 28 08:51:36 PM PDT 24 |
| Peak memory | 575232 kb |
| Host | smart-07a405b9-2b38-41fc-b7ef-742ed4351b47 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3331968560 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 87.xbar_random_zero_del ays.3331968560 |
| Directory | /workspace/87.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/87.xbar_same_source.2306042103 |
| Short name | T1460 |
| Test name | |
| Test status | |
| Simulation time | 327338942 ps |
| CPU time | 23.67 seconds |
| Started | Jun 28 08:50:15 PM PDT 24 |
| Finished | Jun 28 08:51:18 PM PDT 24 |
| Peak memory | 575152 kb |
| Host | smart-665f20ee-7787-47a4-85a7-3d401539d0ad |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2306042103 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 87.xbar_same_source.2306042103 |
| Directory | /workspace/87.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/87.xbar_smoke.1026845541 |
| Short name | T2572 |
| Test name | |
| Test status | |
| Simulation time | 242557402 ps |
| CPU time | 10.69 seconds |
| Started | Jun 28 08:50:13 PM PDT 24 |
| Finished | Jun 28 08:51:03 PM PDT 24 |
| Peak memory | 574188 kb |
| Host | smart-e8422668-cd8a-4324-bb4f-ea1ef078e91b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1026845541 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 87.xbar_smoke.1026845541 |
| Directory | /workspace/87.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/87.xbar_smoke_large_delays.1244886860 |
| Short name | T1631 |
| Test name | |
| Test status | |
| Simulation time | 9531373796 ps |
| CPU time | 96.51 seconds |
| Started | Jun 28 08:50:03 PM PDT 24 |
| Finished | Jun 28 08:52:19 PM PDT 24 |
| Peak memory | 574252 kb |
| Host | smart-b2328195-8268-4c1a-b478-48630516ba61 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1244886860 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 87.xbar_smoke_large_delays.1244886860 |
| Directory | /workspace/87.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/87.xbar_smoke_slow_rsp.4138352532 |
| Short name | T2656 |
| Test name | |
| Test status | |
| Simulation time | 4283111117 ps |
| CPU time | 75.67 seconds |
| Started | Jun 28 08:50:05 PM PDT 24 |
| Finished | Jun 28 08:52:00 PM PDT 24 |
| Peak memory | 574128 kb |
| Host | smart-4bd07eb4-4028-4487-b681-5873b1072286 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4138352532 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 87.xbar_smoke_slow_rsp.4138352532 |
| Directory | /workspace/87.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/87.xbar_smoke_zero_delays.614268314 |
| Short name | T1423 |
| Test name | |
| Test status | |
| Simulation time | 50598372 ps |
| CPU time | 6.78 seconds |
| Started | Jun 28 08:50:14 PM PDT 24 |
| Finished | Jun 28 08:50:59 PM PDT 24 |
| Peak memory | 565912 kb |
| Host | smart-8b52b145-48ef-4a2a-9353-aab8983f797e |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=614268314 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 87.xbar_smoke_zero_delays .614268314 |
| Directory | /workspace/87.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/87.xbar_stress_all.1871111991 |
| Short name | T1606 |
| Test name | |
| Test status | |
| Simulation time | 414514735 ps |
| CPU time | 16.16 seconds |
| Started | Jun 28 08:50:19 PM PDT 24 |
| Finished | Jun 28 08:51:13 PM PDT 24 |
| Peak memory | 575236 kb |
| Host | smart-1c9c6734-b271-4b33-ab59-7ac14d921eba |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1871111991 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 87.xbar_stress_all.1871111991 |
| Directory | /workspace/87.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/87.xbar_stress_all_with_error.4088016643 |
| Short name | T2694 |
| Test name | |
| Test status | |
| Simulation time | 4723334699 ps |
| CPU time | 168.41 seconds |
| Started | Jun 28 08:50:25 PM PDT 24 |
| Finished | Jun 28 08:53:46 PM PDT 24 |
| Peak memory | 574340 kb |
| Host | smart-b645d4fa-af48-4635-ab6f-bc5c06e6cdd2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4088016643 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 87.xbar_stress_all_with_error.4088016643 |
| Directory | /workspace/87.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/87.xbar_stress_all_with_reset_error.3109391753 |
| Short name | T1978 |
| Test name | |
| Test status | |
| Simulation time | 4883830473 ps |
| CPU time | 235.09 seconds |
| Started | Jun 28 08:50:27 PM PDT 24 |
| Finished | Jun 28 08:54:54 PM PDT 24 |
| Peak memory | 574432 kb |
| Host | smart-7158db98-e57a-4a57-831d-1c95f84ff72f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3109391753 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 87.xbar_stress_al l_with_reset_error.3109391753 |
| Directory | /workspace/87.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/87.xbar_unmapped_addr.1099497886 |
| Short name | T468 |
| Test name | |
| Test status | |
| Simulation time | 246513901 ps |
| CPU time | 33.42 seconds |
| Started | Jun 28 08:50:28 PM PDT 24 |
| Finished | Jun 28 08:51:33 PM PDT 24 |
| Peak memory | 574216 kb |
| Host | smart-cb75b550-e1f1-42fe-ba53-eba8768445dd |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1099497886 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 87.xbar_unmapped_addr.1099497886 |
| Directory | /workspace/87.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/88.xbar_access_same_device.2720320211 |
| Short name | T1922 |
| Test name | |
| Test status | |
| Simulation time | 783236559 ps |
| CPU time | 32.83 seconds |
| Started | Jun 28 08:50:20 PM PDT 24 |
| Finished | Jun 28 08:51:30 PM PDT 24 |
| Peak memory | 575240 kb |
| Host | smart-9d033e6e-bc69-4f00-bc1e-4e67712fa1cc |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2720320211 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 88.xbar_access_same_device .2720320211 |
| Directory | /workspace/88.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/88.xbar_access_same_device_slow_rsp.1374891658 |
| Short name | T812 |
| Test name | |
| Test status | |
| Simulation time | 124499425264 ps |
| CPU time | 2149.3 seconds |
| Started | Jun 28 08:50:26 PM PDT 24 |
| Finished | Jun 28 09:26:47 PM PDT 24 |
| Peak memory | 575352 kb |
| Host | smart-97415b6b-bf3a-4b03-a005-b466ed98fb23 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1374891658 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 88.xbar_access_same_ device_slow_rsp.1374891658 |
| Directory | /workspace/88.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/88.xbar_error_and_unmapped_addr.1889985177 |
| Short name | T1403 |
| Test name | |
| Test status | |
| Simulation time | 509561566 ps |
| CPU time | 20.38 seconds |
| Started | Jun 28 08:50:22 PM PDT 24 |
| Finished | Jun 28 08:51:18 PM PDT 24 |
| Peak memory | 574444 kb |
| Host | smart-28d9b7e2-4376-44f1-a060-f72f9af9aacd |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1889985177 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 88.xbar_error_and_unmapped_add r.1889985177 |
| Directory | /workspace/88.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/88.xbar_error_random.3206991564 |
| Short name | T79 |
| Test name | |
| Test status | |
| Simulation time | 451431956 ps |
| CPU time | 35.46 seconds |
| Started | Jun 28 08:50:24 PM PDT 24 |
| Finished | Jun 28 08:51:33 PM PDT 24 |
| Peak memory | 574420 kb |
| Host | smart-db3ad4fd-fbd0-45bf-82b9-f971982753e6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3206991564 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 88.xbar_error_random.3206991564 |
| Directory | /workspace/88.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/88.xbar_random.3255718540 |
| Short name | T2064 |
| Test name | |
| Test status | |
| Simulation time | 407665975 ps |
| CPU time | 37.67 seconds |
| Started | Jun 28 08:50:22 PM PDT 24 |
| Finished | Jun 28 08:51:35 PM PDT 24 |
| Peak memory | 575244 kb |
| Host | smart-3fedc4f6-1bb9-46b6-8014-628a305b6cd2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3255718540 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 88.xbar_random.3255718540 |
| Directory | /workspace/88.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/88.xbar_random_large_delays.3165793158 |
| Short name | T1372 |
| Test name | |
| Test status | |
| Simulation time | 61990654450 ps |
| CPU time | 639.8 seconds |
| Started | Jun 28 08:50:22 PM PDT 24 |
| Finished | Jun 28 09:01:37 PM PDT 24 |
| Peak memory | 575328 kb |
| Host | smart-cc67cbc3-0044-4cb8-b24b-cb1623f9064f |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3165793158 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 88.xbar_random_large_delays.3165793158 |
| Directory | /workspace/88.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/88.xbar_random_slow_rsp.3540293420 |
| Short name | T2530 |
| Test name | |
| Test status | |
| Simulation time | 10548912816 ps |
| CPU time | 176.01 seconds |
| Started | Jun 28 08:50:25 PM PDT 24 |
| Finished | Jun 28 08:53:53 PM PDT 24 |
| Peak memory | 575324 kb |
| Host | smart-e32605c8-1838-4579-91ef-7aed3bf88461 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3540293420 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 88.xbar_random_slow_rsp.3540293420 |
| Directory | /workspace/88.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/88.xbar_random_zero_delays.2602762676 |
| Short name | T1792 |
| Test name | |
| Test status | |
| Simulation time | 286524839 ps |
| CPU time | 27.25 seconds |
| Started | Jun 28 08:50:26 PM PDT 24 |
| Finished | Jun 28 08:51:26 PM PDT 24 |
| Peak memory | 575256 kb |
| Host | smart-77f25934-1e43-4978-b540-f9608c1b78ec |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2602762676 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 88.xbar_random_zero_del ays.2602762676 |
| Directory | /workspace/88.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/88.xbar_same_source.35390635 |
| Short name | T560 |
| Test name | |
| Test status | |
| Simulation time | 462151952 ps |
| CPU time | 31.89 seconds |
| Started | Jun 28 08:50:19 PM PDT 24 |
| Finished | Jun 28 08:51:29 PM PDT 24 |
| Peak memory | 575212 kb |
| Host | smart-0bd05bbd-efda-4121-93d6-3dc88cef1b37 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35390635 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 88.xbar_same_source.35390635 |
| Directory | /workspace/88.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/88.xbar_smoke.1416669688 |
| Short name | T1481 |
| Test name | |
| Test status | |
| Simulation time | 228408175 ps |
| CPU time | 9.8 seconds |
| Started | Jun 28 08:50:25 PM PDT 24 |
| Finished | Jun 28 08:51:07 PM PDT 24 |
| Peak memory | 574176 kb |
| Host | smart-8834bc87-b817-45d4-b562-2b38988664ea |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1416669688 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 88.xbar_smoke.1416669688 |
| Directory | /workspace/88.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/88.xbar_smoke_large_delays.3177568044 |
| Short name | T2661 |
| Test name | |
| Test status | |
| Simulation time | 9795831202 ps |
| CPU time | 105.54 seconds |
| Started | Jun 28 08:50:27 PM PDT 24 |
| Finished | Jun 28 08:52:45 PM PDT 24 |
| Peak memory | 574260 kb |
| Host | smart-06328d91-62e2-4cd6-99e0-7eb4381955ae |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3177568044 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 88.xbar_smoke_large_delays.3177568044 |
| Directory | /workspace/88.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/88.xbar_smoke_slow_rsp.1304963888 |
| Short name | T1619 |
| Test name | |
| Test status | |
| Simulation time | 4504023591 ps |
| CPU time | 80.48 seconds |
| Started | Jun 28 08:50:21 PM PDT 24 |
| Finished | Jun 28 08:52:18 PM PDT 24 |
| Peak memory | 574264 kb |
| Host | smart-78613294-f31f-4dc6-ada9-fd7c3ed0bc5f |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1304963888 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 88.xbar_smoke_slow_rsp.1304963888 |
| Directory | /workspace/88.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/88.xbar_smoke_zero_delays.1632790968 |
| Short name | T1803 |
| Test name | |
| Test status | |
| Simulation time | 48371909 ps |
| CPU time | 6.35 seconds |
| Started | Jun 28 08:50:24 PM PDT 24 |
| Finished | Jun 28 08:51:03 PM PDT 24 |
| Peak memory | 565952 kb |
| Host | smart-cf145902-2104-41a6-8092-f1ceb4afc6a2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1632790968 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 88.xbar_smoke_zero_delay s.1632790968 |
| Directory | /workspace/88.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/88.xbar_stress_all.3920674312 |
| Short name | T497 |
| Test name | |
| Test status | |
| Simulation time | 8062760374 ps |
| CPU time | 299.21 seconds |
| Started | Jun 28 08:50:26 PM PDT 24 |
| Finished | Jun 28 08:55:58 PM PDT 24 |
| Peak memory | 575448 kb |
| Host | smart-05dca30e-0331-4c5b-9294-3216cbe7f2d1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3920674312 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 88.xbar_stress_all.3920674312 |
| Directory | /workspace/88.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/88.xbar_stress_all_with_error.735135975 |
| Short name | T2345 |
| Test name | |
| Test status | |
| Simulation time | 3512790299 ps |
| CPU time | 154.46 seconds |
| Started | Jun 28 08:50:26 PM PDT 24 |
| Finished | Jun 28 08:53:33 PM PDT 24 |
| Peak memory | 574400 kb |
| Host | smart-08afe952-9b84-4582-84a5-8c3f1f89bced |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=735135975 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 88.xbar_stress_all_with_error.735135975 |
| Directory | /workspace/88.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/88.xbar_stress_all_with_rand_reset.1614427212 |
| Short name | T834 |
| Test name | |
| Test status | |
| Simulation time | 312772334 ps |
| CPU time | 167.91 seconds |
| Started | Jun 28 08:50:22 PM PDT 24 |
| Finished | Jun 28 08:53:45 PM PDT 24 |
| Peak memory | 576376 kb |
| Host | smart-869c6381-2507-48a8-85cd-3c24a50a5f4a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1614427212 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 88.xbar_stress_all _with_rand_reset.1614427212 |
| Directory | /workspace/88.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/88.xbar_unmapped_addr.3176850492 |
| Short name | T2204 |
| Test name | |
| Test status | |
| Simulation time | 358783008 ps |
| CPU time | 18.87 seconds |
| Started | Jun 28 08:50:22 PM PDT 24 |
| Finished | Jun 28 08:51:16 PM PDT 24 |
| Peak memory | 575300 kb |
| Host | smart-ca6bf21b-64ee-4811-ba0d-c06642a03f98 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3176850492 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 88.xbar_unmapped_addr.3176850492 |
| Directory | /workspace/88.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/89.xbar_access_same_device.1453055467 |
| Short name | T2814 |
| Test name | |
| Test status | |
| Simulation time | 3528652728 ps |
| CPU time | 148.82 seconds |
| Started | Jun 28 08:50:38 PM PDT 24 |
| Finished | Jun 28 08:53:33 PM PDT 24 |
| Peak memory | 574212 kb |
| Host | smart-cc5e84ad-0968-4e58-a27c-b934e3b7dbf6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1453055467 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 89.xbar_access_same_device .1453055467 |
| Directory | /workspace/89.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/89.xbar_access_same_device_slow_rsp.3860452130 |
| Short name | T2883 |
| Test name | |
| Test status | |
| Simulation time | 86618119232 ps |
| CPU time | 1558.77 seconds |
| Started | Jun 28 08:50:40 PM PDT 24 |
| Finished | Jun 28 09:17:04 PM PDT 24 |
| Peak memory | 575416 kb |
| Host | smart-2efb334b-2140-45ca-a644-6ba293e6340b |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3860452130 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 89.xbar_access_same_ device_slow_rsp.3860452130 |
| Directory | /workspace/89.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/89.xbar_error_and_unmapped_addr.3223181240 |
| Short name | T1445 |
| Test name | |
| Test status | |
| Simulation time | 1108170009 ps |
| CPU time | 51.53 seconds |
| Started | Jun 28 08:50:42 PM PDT 24 |
| Finished | Jun 28 08:51:58 PM PDT 24 |
| Peak memory | 574380 kb |
| Host | smart-df6c4d2f-8b5c-4890-affb-c5054ba61939 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3223181240 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 89.xbar_error_and_unmapped_add r.3223181240 |
| Directory | /workspace/89.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/89.xbar_error_random.2513255122 |
| Short name | T1314 |
| Test name | |
| Test status | |
| Simulation time | 201884465 ps |
| CPU time | 19.83 seconds |
| Started | Jun 28 08:50:41 PM PDT 24 |
| Finished | Jun 28 08:51:25 PM PDT 24 |
| Peak memory | 574348 kb |
| Host | smart-7586c080-d339-4a66-96f6-71ef7a6294e6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2513255122 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 89.xbar_error_random.2513255122 |
| Directory | /workspace/89.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/89.xbar_random.4241613236 |
| Short name | T490 |
| Test name | |
| Test status | |
| Simulation time | 408836203 ps |
| CPU time | 41.96 seconds |
| Started | Jun 28 08:50:38 PM PDT 24 |
| Finished | Jun 28 08:51:47 PM PDT 24 |
| Peak memory | 575292 kb |
| Host | smart-c672ab9d-aa40-4891-8a5e-c31cfffea193 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4241613236 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 89.xbar_random.4241613236 |
| Directory | /workspace/89.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/89.xbar_random_large_delays.2599838519 |
| Short name | T2259 |
| Test name | |
| Test status | |
| Simulation time | 3471818525 ps |
| CPU time | 37.72 seconds |
| Started | Jun 28 08:50:42 PM PDT 24 |
| Finished | Jun 28 08:51:45 PM PDT 24 |
| Peak memory | 574088 kb |
| Host | smart-fbcdd0bd-da6b-4ba6-88fb-e264a31c62e8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2599838519 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 89.xbar_random_large_delays.2599838519 |
| Directory | /workspace/89.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/89.xbar_random_slow_rsp.3534513259 |
| Short name | T2415 |
| Test name | |
| Test status | |
| Simulation time | 56893398500 ps |
| CPU time | 1000.12 seconds |
| Started | Jun 28 08:50:42 PM PDT 24 |
| Finished | Jun 28 09:07:48 PM PDT 24 |
| Peak memory | 575308 kb |
| Host | smart-52db3d07-69a3-4681-8268-2d676b90e83c |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3534513259 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 89.xbar_random_slow_rsp.3534513259 |
| Directory | /workspace/89.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/89.xbar_random_zero_delays.202660834 |
| Short name | T2876 |
| Test name | |
| Test status | |
| Simulation time | 127291280 ps |
| CPU time | 12.59 seconds |
| Started | Jun 28 08:50:43 PM PDT 24 |
| Finished | Jun 28 08:51:20 PM PDT 24 |
| Peak memory | 575228 kb |
| Host | smart-402f7fa0-1b06-4a86-8d1f-000a4c79bec3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=202660834 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 89.xbar_random_zero_dela ys.202660834 |
| Directory | /workspace/89.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/89.xbar_same_source.216169808 |
| Short name | T2768 |
| Test name | |
| Test status | |
| Simulation time | 1853714051 ps |
| CPU time | 59.91 seconds |
| Started | Jun 28 08:50:40 PM PDT 24 |
| Finished | Jun 28 08:52:05 PM PDT 24 |
| Peak memory | 574160 kb |
| Host | smart-93b846ba-3e7d-4ccd-a436-601381593940 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=216169808 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 89.xbar_same_source.216169808 |
| Directory | /workspace/89.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/89.xbar_smoke.2307357071 |
| Short name | T1747 |
| Test name | |
| Test status | |
| Simulation time | 237489008 ps |
| CPU time | 9.97 seconds |
| Started | Jun 28 08:50:22 PM PDT 24 |
| Finished | Jun 28 08:51:06 PM PDT 24 |
| Peak memory | 574192 kb |
| Host | smart-b3792280-2685-4893-8b22-abc04b46e755 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2307357071 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 89.xbar_smoke.2307357071 |
| Directory | /workspace/89.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/89.xbar_smoke_large_delays.147162873 |
| Short name | T2166 |
| Test name | |
| Test status | |
| Simulation time | 7497346304 ps |
| CPU time | 77.67 seconds |
| Started | Jun 28 08:50:22 PM PDT 24 |
| Finished | Jun 28 08:52:15 PM PDT 24 |
| Peak memory | 574164 kb |
| Host | smart-e91d4398-dc13-4727-8b4a-cd0fae4cc825 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=147162873 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 89.xbar_smoke_large_delays.147162873 |
| Directory | /workspace/89.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/89.xbar_smoke_slow_rsp.709211955 |
| Short name | T1315 |
| Test name | |
| Test status | |
| Simulation time | 4065749903 ps |
| CPU time | 73.53 seconds |
| Started | Jun 28 08:50:22 PM PDT 24 |
| Finished | Jun 28 08:52:10 PM PDT 24 |
| Peak memory | 574380 kb |
| Host | smart-8da8733a-476b-4957-a93a-f68c2aa007c0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=709211955 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 89.xbar_smoke_slow_rsp.709211955 |
| Directory | /workspace/89.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/89.xbar_smoke_zero_delays.410494042 |
| Short name | T2326 |
| Test name | |
| Test status | |
| Simulation time | 53606234 ps |
| CPU time | 6.97 seconds |
| Started | Jun 28 08:50:26 PM PDT 24 |
| Finished | Jun 28 08:51:06 PM PDT 24 |
| Peak memory | 574188 kb |
| Host | smart-9c0d054d-c7d5-4e4c-a530-7f3ab2eb6650 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=410494042 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 89.xbar_smoke_zero_delays .410494042 |
| Directory | /workspace/89.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/89.xbar_stress_all.3552697362 |
| Short name | T2272 |
| Test name | |
| Test status | |
| Simulation time | 8500279385 ps |
| CPU time | 331.04 seconds |
| Started | Jun 28 08:50:40 PM PDT 24 |
| Finished | Jun 28 08:56:36 PM PDT 24 |
| Peak memory | 575452 kb |
| Host | smart-703c7534-9b8a-45bc-bac1-340a88d1d509 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3552697362 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 89.xbar_stress_all.3552697362 |
| Directory | /workspace/89.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/89.xbar_stress_all_with_error.716559824 |
| Short name | T2788 |
| Test name | |
| Test status | |
| Simulation time | 620640036 ps |
| CPU time | 49.44 seconds |
| Started | Jun 28 08:50:43 PM PDT 24 |
| Finished | Jun 28 08:51:57 PM PDT 24 |
| Peak memory | 574176 kb |
| Host | smart-9083b76a-e7df-4775-8d75-9155043e4c2f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=716559824 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 89.xbar_stress_all_with_error.716559824 |
| Directory | /workspace/89.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/89.xbar_stress_all_with_rand_reset.2246897021 |
| Short name | T2337 |
| Test name | |
| Test status | |
| Simulation time | 81111346 ps |
| CPU time | 13.71 seconds |
| Started | Jun 28 08:50:42 PM PDT 24 |
| Finished | Jun 28 08:51:21 PM PDT 24 |
| Peak memory | 574284 kb |
| Host | smart-c0347e87-5588-4f60-b097-f6befd77668b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2246897021 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 89.xbar_stress_all _with_rand_reset.2246897021 |
| Directory | /workspace/89.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/89.xbar_stress_all_with_reset_error.629023744 |
| Short name | T847 |
| Test name | |
| Test status | |
| Simulation time | 123921121 ps |
| CPU time | 52.72 seconds |
| Started | Jun 28 08:50:40 PM PDT 24 |
| Finished | Jun 28 08:51:58 PM PDT 24 |
| Peak memory | 574320 kb |
| Host | smart-ef15932d-2cbb-4d89-a153-1039175e21e3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=629023744 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 89.xbar_stress_all _with_reset_error.629023744 |
| Directory | /workspace/89.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/89.xbar_unmapped_addr.2559792316 |
| Short name | T2142 |
| Test name | |
| Test status | |
| Simulation time | 365651599 ps |
| CPU time | 38.53 seconds |
| Started | Jun 28 08:50:40 PM PDT 24 |
| Finished | Jun 28 08:51:44 PM PDT 24 |
| Peak memory | 575268 kb |
| Host | smart-2d849e46-fc8e-45a5-bbaf-c3abc1c00668 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2559792316 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 89.xbar_unmapped_addr.2559792316 |
| Directory | /workspace/89.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/9.chip_csr_rw.2647634943 |
| Short name | T1880 |
| Test name | |
| Test status | |
| Simulation time | 4376029200 ps |
| CPU time | 369.27 seconds |
| Started | Jun 28 08:34:05 PM PDT 24 |
| Finished | Jun 28 08:40:25 PM PDT 24 |
| Peak memory | 596188 kb |
| Host | smart-99b72aa8-109b-4e36-92e3-546f5f0c46c9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2647634943 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.chip_csr_rw.2647634943 |
| Directory | /workspace/9.chip_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/9.chip_same_csr_outstanding.881033858 |
| Short name | T2357 |
| Test name | |
| Test status | |
| Simulation time | 29932402720 ps |
| CPU time | 3043.38 seconds |
| Started | Jun 28 08:34:01 PM PDT 24 |
| Finished | Jun 28 09:24:54 PM PDT 24 |
| Peak memory | 592112 kb |
| Host | smart-9a8d8ebb-86f2-4214-930d-70e5df2cd266 |
| User | root |
| Command | /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +run_same_csr_outstanding +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=881033858 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c m_log /dev/null -cm_name 9.chip_same_csr_outstanding.881033858 |
| Directory | /workspace/9.chip_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/9.chip_tl_errors.987779563 |
| Short name | T656 |
| Test name | |
| Test status | |
| Simulation time | 5110626305 ps |
| CPU time | 369.98 seconds |
| Started | Jun 28 08:34:07 PM PDT 24 |
| Finished | Jun 28 08:40:28 PM PDT 24 |
| Peak memory | 597652 kb |
| Host | smart-7d3ecfb8-3184-4247-8ec1-bae21c66c7ab |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=987779563 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.chip_tl_errors.987779563 |
| Directory | /workspace/9.chip_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/9.xbar_access_same_device.2658489474 |
| Short name | T805 |
| Test name | |
| Test status | |
| Simulation time | 798961008 ps |
| CPU time | 60.6 seconds |
| Started | Jun 28 08:34:05 PM PDT 24 |
| Finished | Jun 28 08:35:16 PM PDT 24 |
| Peak memory | 575272 kb |
| Host | smart-e232efd7-0ce6-4e76-a3a6-d5662dd2d4ef |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2658489474 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.xbar_access_same_device. 2658489474 |
| Directory | /workspace/9.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/9.xbar_error_and_unmapped_addr.2149923426 |
| Short name | T1336 |
| Test name | |
| Test status | |
| Simulation time | 133358298 ps |
| CPU time | 8.51 seconds |
| Started | Jun 28 08:34:05 PM PDT 24 |
| Finished | Jun 28 08:34:25 PM PDT 24 |
| Peak memory | 574200 kb |
| Host | smart-b9d9942f-b280-4ba0-a8b6-39e033f8034c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2149923426 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.xbar_error_and_unmapped_addr .2149923426 |
| Directory | /workspace/9.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/9.xbar_error_random.227272268 |
| Short name | T1833 |
| Test name | |
| Test status | |
| Simulation time | 2013122173 ps |
| CPU time | 76.96 seconds |
| Started | Jun 28 08:34:04 PM PDT 24 |
| Finished | Jun 28 08:35:31 PM PDT 24 |
| Peak memory | 574208 kb |
| Host | smart-0f153c46-74e6-46ff-9ea0-ca350603601c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=227272268 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.xbar_error_random.227272268 |
| Directory | /workspace/9.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/9.xbar_random.655697468 |
| Short name | T1571 |
| Test name | |
| Test status | |
| Simulation time | 33173448 ps |
| CPU time | 6.59 seconds |
| Started | Jun 28 08:34:05 PM PDT 24 |
| Finished | Jun 28 08:34:22 PM PDT 24 |
| Peak memory | 574188 kb |
| Host | smart-60ceedd3-b1c7-4acd-9086-961833db4c1f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=655697468 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.xbar_random.655697468 |
| Directory | /workspace/9.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/9.xbar_random_large_delays.3624860828 |
| Short name | T2163 |
| Test name | |
| Test status | |
| Simulation time | 35815145605 ps |
| CPU time | 379.48 seconds |
| Started | Jun 28 08:34:02 PM PDT 24 |
| Finished | Jun 28 08:40:32 PM PDT 24 |
| Peak memory | 575288 kb |
| Host | smart-140dda27-5029-47d8-ab23-e60e4f59f67d |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3624860828 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.xbar_random_large_delays.3624860828 |
| Directory | /workspace/9.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/9.xbar_random_slow_rsp.1740034278 |
| Short name | T2336 |
| Test name | |
| Test status | |
| Simulation time | 63931630004 ps |
| CPU time | 1103.2 seconds |
| Started | Jun 28 08:34:01 PM PDT 24 |
| Finished | Jun 28 08:52:34 PM PDT 24 |
| Peak memory | 575328 kb |
| Host | smart-3d183593-a633-4270-b88f-8c247b529b74 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1740034278 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.xbar_random_slow_rsp.1740034278 |
| Directory | /workspace/9.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/9.xbar_random_zero_delays.2706036750 |
| Short name | T535 |
| Test name | |
| Test status | |
| Simulation time | 76713592 ps |
| CPU time | 9.86 seconds |
| Started | Jun 28 08:34:07 PM PDT 24 |
| Finished | Jun 28 08:34:28 PM PDT 24 |
| Peak memory | 575224 kb |
| Host | smart-6fc4a0b7-20fa-4910-90ad-4b4e25422724 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2706036750 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.xbar_random_zero_dela ys.2706036750 |
| Directory | /workspace/9.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/9.xbar_same_source.2444624239 |
| Short name | T1799 |
| Test name | |
| Test status | |
| Simulation time | 2655397608 ps |
| CPU time | 92.23 seconds |
| Started | Jun 28 08:34:02 PM PDT 24 |
| Finished | Jun 28 08:35:43 PM PDT 24 |
| Peak memory | 575292 kb |
| Host | smart-79bc87fb-cfea-49a7-b3a2-621998b058b2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2444624239 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.xbar_same_source.2444624239 |
| Directory | /workspace/9.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/9.xbar_smoke.3609319403 |
| Short name | T1425 |
| Test name | |
| Test status | |
| Simulation time | 140580911 ps |
| CPU time | 7.6 seconds |
| Started | Jun 28 08:34:01 PM PDT 24 |
| Finished | Jun 28 08:34:18 PM PDT 24 |
| Peak memory | 574060 kb |
| Host | smart-ec61653d-18bf-4367-8aae-73861fcb5f87 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3609319403 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.xbar_smoke.3609319403 |
| Directory | /workspace/9.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/9.xbar_smoke_large_delays.4121782387 |
| Short name | T1979 |
| Test name | |
| Test status | |
| Simulation time | 8342333493 ps |
| CPU time | 90.96 seconds |
| Started | Jun 28 08:33:59 PM PDT 24 |
| Finished | Jun 28 08:35:39 PM PDT 24 |
| Peak memory | 574260 kb |
| Host | smart-5fe2b9ea-de12-4044-b41d-59e23fba55a0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4121782387 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.xbar_smoke_large_delays.4121782387 |
| Directory | /workspace/9.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/9.xbar_smoke_slow_rsp.3464725338 |
| Short name | T538 |
| Test name | |
| Test status | |
| Simulation time | 6773544783 ps |
| CPU time | 112.96 seconds |
| Started | Jun 28 08:34:00 PM PDT 24 |
| Finished | Jun 28 08:36:01 PM PDT 24 |
| Peak memory | 566032 kb |
| Host | smart-4cef501f-c832-48dd-89ef-7da8e7e1635e |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3464725338 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.xbar_smoke_slow_rsp.3464725338 |
| Directory | /workspace/9.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/9.xbar_smoke_zero_delays.698468322 |
| Short name | T1382 |
| Test name | |
| Test status | |
| Simulation time | 47330604 ps |
| CPU time | 6.51 seconds |
| Started | Jun 28 08:34:06 PM PDT 24 |
| Finished | Jun 28 08:34:23 PM PDT 24 |
| Peak memory | 574184 kb |
| Host | smart-0aa9bb94-de28-4917-96f4-e06818b02240 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=698468322 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.xbar_smoke_zero_delays. 698468322 |
| Directory | /workspace/9.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/9.xbar_stress_all.1902542565 |
| Short name | T1733 |
| Test name | |
| Test status | |
| Simulation time | 9056599836 ps |
| CPU time | 385.21 seconds |
| Started | Jun 28 08:34:01 PM PDT 24 |
| Finished | Jun 28 08:40:35 PM PDT 24 |
| Peak memory | 575464 kb |
| Host | smart-86056f85-0415-4d95-a68d-ac3f198249b1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1902542565 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.xbar_stress_all.1902542565 |
| Directory | /workspace/9.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/9.xbar_stress_all_with_error.1146804644 |
| Short name | T2378 |
| Test name | |
| Test status | |
| Simulation time | 4242994559 ps |
| CPU time | 175.7 seconds |
| Started | Jun 28 08:34:07 PM PDT 24 |
| Finished | Jun 28 08:37:14 PM PDT 24 |
| Peak memory | 574368 kb |
| Host | smart-fb5bf914-1438-4161-883d-41ece3408165 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1146804644 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.xbar_stress_all_with_error.1146804644 |
| Directory | /workspace/9.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/9.xbar_stress_all_with_rand_reset.3064318449 |
| Short name | T2165 |
| Test name | |
| Test status | |
| Simulation time | 350196769 ps |
| CPU time | 264.43 seconds |
| Started | Jun 28 08:34:04 PM PDT 24 |
| Finished | Jun 28 08:38:37 PM PDT 24 |
| Peak memory | 575376 kb |
| Host | smart-df315f83-ee51-437e-8c64-e79ad688d549 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3064318449 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.xbar_stress_all_ with_rand_reset.3064318449 |
| Directory | /workspace/9.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/9.xbar_stress_all_with_reset_error.171192556 |
| Short name | T1923 |
| Test name | |
| Test status | |
| Simulation time | 19802176557 ps |
| CPU time | 848.99 seconds |
| Started | Jun 28 08:33:59 PM PDT 24 |
| Finished | Jun 28 08:48:17 PM PDT 24 |
| Peak memory | 574568 kb |
| Host | smart-e0f650a8-394a-401b-a7dd-752b19de3ad4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=171192556 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.xbar_stress_all_ with_reset_error.171192556 |
| Directory | /workspace/9.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/9.xbar_unmapped_addr.4180711336 |
| Short name | T554 |
| Test name | |
| Test status | |
| Simulation time | 575918290 ps |
| CPU time | 25.56 seconds |
| Started | Jun 28 08:34:07 PM PDT 24 |
| Finished | Jun 28 08:34:43 PM PDT 24 |
| Peak memory | 575304 kb |
| Host | smart-28c449a2-0fb9-4ff8-b7eb-eadd833ac7f5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4180711336 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.xbar_unmapped_addr.4180711336 |
| Directory | /workspace/9.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/90.xbar_access_same_device.2599267582 |
| Short name | T1464 |
| Test name | |
| Test status | |
| Simulation time | 1438753129 ps |
| CPU time | 75.38 seconds |
| Started | Jun 28 08:50:38 PM PDT 24 |
| Finished | Jun 28 08:52:20 PM PDT 24 |
| Peak memory | 575276 kb |
| Host | smart-8cb1cdb1-3df2-4484-91d0-d90444edf3c6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2599267582 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 90.xbar_access_same_device .2599267582 |
| Directory | /workspace/90.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/90.xbar_access_same_device_slow_rsp.424237282 |
| Short name | T1574 |
| Test name | |
| Test status | |
| Simulation time | 89175410545 ps |
| CPU time | 1512.6 seconds |
| Started | Jun 28 08:50:39 PM PDT 24 |
| Finished | Jun 28 09:16:17 PM PDT 24 |
| Peak memory | 575328 kb |
| Host | smart-f901cb59-6786-49f3-9c69-d759c7c64111 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=424237282 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 90.xbar_access_same_d evice_slow_rsp.424237282 |
| Directory | /workspace/90.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/90.xbar_error_and_unmapped_addr.453261058 |
| Short name | T649 |
| Test name | |
| Test status | |
| Simulation time | 160482051 ps |
| CPU time | 20.04 seconds |
| Started | Jun 28 08:50:45 PM PDT 24 |
| Finished | Jun 28 08:51:30 PM PDT 24 |
| Peak memory | 574416 kb |
| Host | smart-6df831f5-fc1e-4731-9c4d-713e455b869d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=453261058 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 90.xbar_error_and_unmapped_addr .453261058 |
| Directory | /workspace/90.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/90.xbar_error_random.553674941 |
| Short name | T1333 |
| Test name | |
| Test status | |
| Simulation time | 279235768 ps |
| CPU time | 13.34 seconds |
| Started | Jun 28 08:50:40 PM PDT 24 |
| Finished | Jun 28 08:51:19 PM PDT 24 |
| Peak memory | 574424 kb |
| Host | smart-f6a669a6-0469-4d79-ab5d-ec1eb8f45964 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=553674941 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 90.xbar_error_random.553674941 |
| Directory | /workspace/90.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/90.xbar_random.2793750394 |
| Short name | T1832 |
| Test name | |
| Test status | |
| Simulation time | 2002007134 ps |
| CPU time | 88.35 seconds |
| Started | Jun 28 08:50:39 PM PDT 24 |
| Finished | Jun 28 08:52:33 PM PDT 24 |
| Peak memory | 575336 kb |
| Host | smart-6accdcf7-bd42-418d-a265-55ff05f001e3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2793750394 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 90.xbar_random.2793750394 |
| Directory | /workspace/90.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/90.xbar_random_large_delays.309107023 |
| Short name | T561 |
| Test name | |
| Test status | |
| Simulation time | 36373406293 ps |
| CPU time | 376.34 seconds |
| Started | Jun 28 08:50:39 PM PDT 24 |
| Finished | Jun 28 08:57:21 PM PDT 24 |
| Peak memory | 575316 kb |
| Host | smart-fd698009-b740-40c3-9dc3-39fb9c1b93d4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=309107023 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 90.xbar_random_large_delays.309107023 |
| Directory | /workspace/90.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/90.xbar_random_slow_rsp.253954211 |
| Short name | T2834 |
| Test name | |
| Test status | |
| Simulation time | 14690399134 ps |
| CPU time | 267.71 seconds |
| Started | Jun 28 08:50:43 PM PDT 24 |
| Finished | Jun 28 08:55:35 PM PDT 24 |
| Peak memory | 575332 kb |
| Host | smart-cfa5d698-b1b6-448c-8ec8-13a35bedb429 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=253954211 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 90.xbar_random_slow_rsp.253954211 |
| Directory | /workspace/90.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/90.xbar_random_zero_delays.1217962088 |
| Short name | T2839 |
| Test name | |
| Test status | |
| Simulation time | 275558034 ps |
| CPU time | 27.12 seconds |
| Started | Jun 28 08:50:42 PM PDT 24 |
| Finished | Jun 28 08:51:35 PM PDT 24 |
| Peak memory | 575236 kb |
| Host | smart-05522566-3d40-4afb-a872-cf56ad1885f7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1217962088 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 90.xbar_random_zero_del ays.1217962088 |
| Directory | /workspace/90.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/90.xbar_same_source.2856630651 |
| Short name | T2549 |
| Test name | |
| Test status | |
| Simulation time | 1691220154 ps |
| CPU time | 53.48 seconds |
| Started | Jun 28 08:50:39 PM PDT 24 |
| Finished | Jun 28 08:51:58 PM PDT 24 |
| Peak memory | 574164 kb |
| Host | smart-747af1d7-ca50-46f1-bb19-460d5487a572 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2856630651 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 90.xbar_same_source.2856630651 |
| Directory | /workspace/90.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/90.xbar_smoke.4030885570 |
| Short name | T1694 |
| Test name | |
| Test status | |
| Simulation time | 215689617 ps |
| CPU time | 9.52 seconds |
| Started | Jun 28 08:50:40 PM PDT 24 |
| Finished | Jun 28 08:51:15 PM PDT 24 |
| Peak memory | 565956 kb |
| Host | smart-cf64156e-fa04-441a-9d78-7a88cd883bdb |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4030885570 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 90.xbar_smoke.4030885570 |
| Directory | /workspace/90.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/90.xbar_smoke_large_delays.1071272613 |
| Short name | T1324 |
| Test name | |
| Test status | |
| Simulation time | 6869769425 ps |
| CPU time | 76.75 seconds |
| Started | Jun 28 08:50:40 PM PDT 24 |
| Finished | Jun 28 08:52:22 PM PDT 24 |
| Peak memory | 574256 kb |
| Host | smart-0790d1cc-766f-4c07-8623-9c238ffad089 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1071272613 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 90.xbar_smoke_large_delays.1071272613 |
| Directory | /workspace/90.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/90.xbar_smoke_slow_rsp.3563035272 |
| Short name | T2849 |
| Test name | |
| Test status | |
| Simulation time | 5117998314 ps |
| CPU time | 92.62 seconds |
| Started | Jun 28 08:50:43 PM PDT 24 |
| Finished | Jun 28 08:52:41 PM PDT 24 |
| Peak memory | 574272 kb |
| Host | smart-1319a348-8811-47d2-a6e6-79350b9143f7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3563035272 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 90.xbar_smoke_slow_rsp.3563035272 |
| Directory | /workspace/90.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/90.xbar_smoke_zero_delays.3236138076 |
| Short name | T2423 |
| Test name | |
| Test status | |
| Simulation time | 45143913 ps |
| CPU time | 6.92 seconds |
| Started | Jun 28 08:50:40 PM PDT 24 |
| Finished | Jun 28 08:51:12 PM PDT 24 |
| Peak memory | 574184 kb |
| Host | smart-46c3a317-8ae1-420c-a820-efc0fb72b807 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3236138076 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 90.xbar_smoke_zero_delay s.3236138076 |
| Directory | /workspace/90.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/90.xbar_stress_all.4080503875 |
| Short name | T448 |
| Test name | |
| Test status | |
| Simulation time | 20876046359 ps |
| CPU time | 634.37 seconds |
| Started | Jun 28 08:50:42 PM PDT 24 |
| Finished | Jun 28 09:01:42 PM PDT 24 |
| Peak memory | 575432 kb |
| Host | smart-2174640f-8e22-4000-868a-8d1f38928393 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4080503875 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 90.xbar_stress_all.4080503875 |
| Directory | /workspace/90.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/90.xbar_stress_all_with_error.1369109778 |
| Short name | T1949 |
| Test name | |
| Test status | |
| Simulation time | 2200260261 ps |
| CPU time | 172.29 seconds |
| Started | Jun 28 08:51:06 PM PDT 24 |
| Finished | Jun 28 08:54:26 PM PDT 24 |
| Peak memory | 574668 kb |
| Host | smart-5d1df07d-e19f-4f83-b04c-5b268ff17d69 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1369109778 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 90.xbar_stress_all_with_error.1369109778 |
| Directory | /workspace/90.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/90.xbar_stress_all_with_rand_reset.990179264 |
| Short name | T2037 |
| Test name | |
| Test status | |
| Simulation time | 451209512 ps |
| CPU time | 274.16 seconds |
| Started | Jun 28 08:51:06 PM PDT 24 |
| Finished | Jun 28 08:56:08 PM PDT 24 |
| Peak memory | 575384 kb |
| Host | smart-46be7af7-a7d8-462d-802c-dee1feaa3e71 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=990179264 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_res et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 90.xbar_stress_all_ with_rand_reset.990179264 |
| Directory | /workspace/90.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/90.xbar_stress_all_with_reset_error.1248379882 |
| Short name | T1838 |
| Test name | |
| Test status | |
| Simulation time | 579858533 ps |
| CPU time | 234.36 seconds |
| Started | Jun 28 08:51:05 PM PDT 24 |
| Finished | Jun 28 08:55:26 PM PDT 24 |
| Peak memory | 574600 kb |
| Host | smart-488c9858-e1ef-4806-9386-a47a394ca8bf |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1248379882 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 90.xbar_stress_al l_with_reset_error.1248379882 |
| Directory | /workspace/90.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/90.xbar_unmapped_addr.2280535136 |
| Short name | T1689 |
| Test name | |
| Test status | |
| Simulation time | 86575810 ps |
| CPU time | 7.04 seconds |
| Started | Jun 28 08:50:40 PM PDT 24 |
| Finished | Jun 28 08:51:12 PM PDT 24 |
| Peak memory | 565952 kb |
| Host | smart-d9983733-d390-4c89-af56-4ba23faab720 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2280535136 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 90.xbar_unmapped_addr.2280535136 |
| Directory | /workspace/90.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/91.xbar_access_same_device.2551812691 |
| Short name | T2648 |
| Test name | |
| Test status | |
| Simulation time | 1454071626 ps |
| CPU time | 66.21 seconds |
| Started | Jun 28 08:51:08 PM PDT 24 |
| Finished | Jun 28 08:52:43 PM PDT 24 |
| Peak memory | 575236 kb |
| Host | smart-ada17ef3-76f7-4016-9081-995e1cb611ef |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2551812691 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 91.xbar_access_same_device .2551812691 |
| Directory | /workspace/91.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/91.xbar_access_same_device_slow_rsp.3191205327 |
| Short name | T2316 |
| Test name | |
| Test status | |
| Simulation time | 161216975266 ps |
| CPU time | 2738.44 seconds |
| Started | Jun 28 08:51:10 PM PDT 24 |
| Finished | Jun 28 09:37:17 PM PDT 24 |
| Peak memory | 574276 kb |
| Host | smart-11753697-d925-4482-a90a-2aa3c317d486 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3191205327 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 91.xbar_access_same_ device_slow_rsp.3191205327 |
| Directory | /workspace/91.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/91.xbar_error_and_unmapped_addr.1099473317 |
| Short name | T2211 |
| Test name | |
| Test status | |
| Simulation time | 818140728 ps |
| CPU time | 37.87 seconds |
| Started | Jun 28 08:51:07 PM PDT 24 |
| Finished | Jun 28 08:52:13 PM PDT 24 |
| Peak memory | 574440 kb |
| Host | smart-c331a3ba-5aa6-4441-a4dd-651e4e69672d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1099473317 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 91.xbar_error_and_unmapped_add r.1099473317 |
| Directory | /workspace/91.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/91.xbar_error_random.3131717897 |
| Short name | T2014 |
| Test name | |
| Test status | |
| Simulation time | 1941373012 ps |
| CPU time | 82.14 seconds |
| Started | Jun 28 08:51:08 PM PDT 24 |
| Finished | Jun 28 08:52:58 PM PDT 24 |
| Peak memory | 574204 kb |
| Host | smart-a2b1b46a-98dc-4267-bfa1-368427083d69 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3131717897 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 91.xbar_error_random.3131717897 |
| Directory | /workspace/91.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/91.xbar_random.860431772 |
| Short name | T1332 |
| Test name | |
| Test status | |
| Simulation time | 233959940 ps |
| CPU time | 11.5 seconds |
| Started | Jun 28 08:51:07 PM PDT 24 |
| Finished | Jun 28 08:51:46 PM PDT 24 |
| Peak memory | 574232 kb |
| Host | smart-44fa6d30-848f-476c-a7d0-0a87e697d9f2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=860431772 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 91.xbar_random.860431772 |
| Directory | /workspace/91.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/91.xbar_random_large_delays.3224428431 |
| Short name | T1732 |
| Test name | |
| Test status | |
| Simulation time | 71253149721 ps |
| CPU time | 725.7 seconds |
| Started | Jun 28 08:51:06 PM PDT 24 |
| Finished | Jun 28 09:03:40 PM PDT 24 |
| Peak memory | 575336 kb |
| Host | smart-a2453058-413f-4420-9dd1-1a7fc591ec33 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3224428431 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 91.xbar_random_large_delays.3224428431 |
| Directory | /workspace/91.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/91.xbar_random_slow_rsp.388655054 |
| Short name | T2741 |
| Test name | |
| Test status | |
| Simulation time | 55134581720 ps |
| CPU time | 956.09 seconds |
| Started | Jun 28 08:51:05 PM PDT 24 |
| Finished | Jun 28 09:07:27 PM PDT 24 |
| Peak memory | 575356 kb |
| Host | smart-39a4399d-57ad-4eaa-a6f2-3e07e8cf8e29 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=388655054 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 91.xbar_random_slow_rsp.388655054 |
| Directory | /workspace/91.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/91.xbar_random_zero_delays.3014440494 |
| Short name | T2195 |
| Test name | |
| Test status | |
| Simulation time | 214971139 ps |
| CPU time | 24.9 seconds |
| Started | Jun 28 08:51:00 PM PDT 24 |
| Finished | Jun 28 08:51:52 PM PDT 24 |
| Peak memory | 575224 kb |
| Host | smart-6f36168a-a93e-45da-921e-5721f8fbbbc7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3014440494 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 91.xbar_random_zero_del ays.3014440494 |
| Directory | /workspace/91.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/91.xbar_same_source.2754625697 |
| Short name | T2296 |
| Test name | |
| Test status | |
| Simulation time | 411160414 ps |
| CPU time | 34.65 seconds |
| Started | Jun 28 08:51:11 PM PDT 24 |
| Finished | Jun 28 08:52:13 PM PDT 24 |
| Peak memory | 574108 kb |
| Host | smart-36a07c6d-6cd4-4481-8685-26a7441e4f5a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2754625697 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 91.xbar_same_source.2754625697 |
| Directory | /workspace/91.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/91.xbar_smoke.1071192297 |
| Short name | T2231 |
| Test name | |
| Test status | |
| Simulation time | 35006051 ps |
| CPU time | 5.85 seconds |
| Started | Jun 28 08:51:07 PM PDT 24 |
| Finished | Jun 28 08:51:40 PM PDT 24 |
| Peak memory | 574008 kb |
| Host | smart-f8e5bb7b-9da4-44f4-93dd-5cb8a9bfe818 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1071192297 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 91.xbar_smoke.1071192297 |
| Directory | /workspace/91.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/91.xbar_smoke_large_delays.2159561261 |
| Short name | T1695 |
| Test name | |
| Test status | |
| Simulation time | 7387262390 ps |
| CPU time | 74 seconds |
| Started | Jun 28 08:51:05 PM PDT 24 |
| Finished | Jun 28 08:52:45 PM PDT 24 |
| Peak memory | 574264 kb |
| Host | smart-352e2913-37d5-431b-a79c-303f07316fa9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2159561261 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 91.xbar_smoke_large_delays.2159561261 |
| Directory | /workspace/91.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/91.xbar_smoke_slow_rsp.3733829239 |
| Short name | T2364 |
| Test name | |
| Test status | |
| Simulation time | 5062811648 ps |
| CPU time | 86.31 seconds |
| Started | Jun 28 08:51:06 PM PDT 24 |
| Finished | Jun 28 08:53:00 PM PDT 24 |
| Peak memory | 574240 kb |
| Host | smart-6b5c2085-1bed-45a6-8786-9c17d63cbf88 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3733829239 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 91.xbar_smoke_slow_rsp.3733829239 |
| Directory | /workspace/91.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/91.xbar_smoke_zero_delays.1755191525 |
| Short name | T2884 |
| Test name | |
| Test status | |
| Simulation time | 44242975 ps |
| CPU time | 6.3 seconds |
| Started | Jun 28 08:51:06 PM PDT 24 |
| Finished | Jun 28 08:51:40 PM PDT 24 |
| Peak memory | 565824 kb |
| Host | smart-cacbaa41-d7fb-4b39-b7a2-d35510a08c57 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1755191525 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 91.xbar_smoke_zero_delay s.1755191525 |
| Directory | /workspace/91.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/91.xbar_stress_all.1011547165 |
| Short name | T2344 |
| Test name | |
| Test status | |
| Simulation time | 11077418587 ps |
| CPU time | 531.03 seconds |
| Started | Jun 28 08:51:08 PM PDT 24 |
| Finished | Jun 28 09:00:27 PM PDT 24 |
| Peak memory | 575436 kb |
| Host | smart-180e4a46-dda9-44de-9ef1-ae97865c7958 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1011547165 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 91.xbar_stress_all.1011547165 |
| Directory | /workspace/91.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/91.xbar_stress_all_with_error.1301032091 |
| Short name | T2555 |
| Test name | |
| Test status | |
| Simulation time | 3134379659 ps |
| CPU time | 258.94 seconds |
| Started | Jun 28 08:51:06 PM PDT 24 |
| Finished | Jun 28 08:55:51 PM PDT 24 |
| Peak memory | 574656 kb |
| Host | smart-3feea091-1703-4d4a-983b-4130269657a5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1301032091 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 91.xbar_stress_all_with_error.1301032091 |
| Directory | /workspace/91.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/91.xbar_stress_all_with_rand_reset.601670868 |
| Short name | T1486 |
| Test name | |
| Test status | |
| Simulation time | 66957441 ps |
| CPU time | 27.92 seconds |
| Started | Jun 28 08:51:08 PM PDT 24 |
| Finished | Jun 28 08:52:04 PM PDT 24 |
| Peak memory | 574328 kb |
| Host | smart-a8aa7263-a6ce-4dee-9f61-a368201dd550 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=601670868 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_res et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 91.xbar_stress_all_ with_rand_reset.601670868 |
| Directory | /workspace/91.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/91.xbar_stress_all_with_reset_error.131969851 |
| Short name | T841 |
| Test name | |
| Test status | |
| Simulation time | 4660510498 ps |
| CPU time | 253.37 seconds |
| Started | Jun 28 08:51:05 PM PDT 24 |
| Finished | Jun 28 08:55:45 PM PDT 24 |
| Peak memory | 576432 kb |
| Host | smart-ab202fda-a4e4-4316-83cf-9791e8fd9378 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=131969851 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 91.xbar_stress_all _with_reset_error.131969851 |
| Directory | /workspace/91.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/91.xbar_unmapped_addr.1649431040 |
| Short name | T2318 |
| Test name | |
| Test status | |
| Simulation time | 355936123 ps |
| CPU time | 16.91 seconds |
| Started | Jun 28 08:51:08 PM PDT 24 |
| Finished | Jun 28 08:51:53 PM PDT 24 |
| Peak memory | 575296 kb |
| Host | smart-43923076-10f2-4937-afbc-98d6b5f261d2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1649431040 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 91.xbar_unmapped_addr.1649431040 |
| Directory | /workspace/91.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/92.xbar_access_same_device.862242382 |
| Short name | T2264 |
| Test name | |
| Test status | |
| Simulation time | 1989425216 ps |
| CPU time | 88.89 seconds |
| Started | Jun 28 08:51:05 PM PDT 24 |
| Finished | Jun 28 08:53:00 PM PDT 24 |
| Peak memory | 575256 kb |
| Host | smart-2da16e67-e252-4fea-a58b-58f2042d0afe |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=862242382 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 92.xbar_access_same_device. 862242382 |
| Directory | /workspace/92.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/92.xbar_access_same_device_slow_rsp.1861535639 |
| Short name | T1609 |
| Test name | |
| Test status | |
| Simulation time | 88430092967 ps |
| CPU time | 1435.61 seconds |
| Started | Jun 28 08:51:07 PM PDT 24 |
| Finished | Jun 28 09:15:30 PM PDT 24 |
| Peak memory | 575348 kb |
| Host | smart-ad66aa1f-c45c-4d40-9d4b-08274d6a5808 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1861535639 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 92.xbar_access_same_ device_slow_rsp.1861535639 |
| Directory | /workspace/92.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/92.xbar_error_and_unmapped_addr.2158126140 |
| Short name | T2558 |
| Test name | |
| Test status | |
| Simulation time | 423992638 ps |
| CPU time | 19 seconds |
| Started | Jun 28 08:51:26 PM PDT 24 |
| Finished | Jun 28 08:52:06 PM PDT 24 |
| Peak memory | 574200 kb |
| Host | smart-e40fd97b-c4dd-45ca-9885-688349bb44e4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2158126140 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 92.xbar_error_and_unmapped_add r.2158126140 |
| Directory | /workspace/92.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/92.xbar_error_random.4098876617 |
| Short name | T2625 |
| Test name | |
| Test status | |
| Simulation time | 177015634 ps |
| CPU time | 16.95 seconds |
| Started | Jun 28 08:51:07 PM PDT 24 |
| Finished | Jun 28 08:51:52 PM PDT 24 |
| Peak memory | 573808 kb |
| Host | smart-d6e9c893-2d55-4ece-aee3-5610070b96b5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4098876617 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 92.xbar_error_random.4098876617 |
| Directory | /workspace/92.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/92.xbar_random.872735668 |
| Short name | T2792 |
| Test name | |
| Test status | |
| Simulation time | 785538603 ps |
| CPU time | 32.37 seconds |
| Started | Jun 28 08:51:02 PM PDT 24 |
| Finished | Jun 28 08:52:00 PM PDT 24 |
| Peak memory | 574188 kb |
| Host | smart-1ffee950-286a-422b-8df9-ff5820004496 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=872735668 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 92.xbar_random.872735668 |
| Directory | /workspace/92.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/92.xbar_random_large_delays.4077926333 |
| Short name | T1814 |
| Test name | |
| Test status | |
| Simulation time | 54620828418 ps |
| CPU time | 575.68 seconds |
| Started | Jun 28 08:51:08 PM PDT 24 |
| Finished | Jun 28 09:01:12 PM PDT 24 |
| Peak memory | 574280 kb |
| Host | smart-613b47df-ba2a-4b8f-9942-89ea53308c3b |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4077926333 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 92.xbar_random_large_delays.4077926333 |
| Directory | /workspace/92.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/92.xbar_random_slow_rsp.1977504836 |
| Short name | T1849 |
| Test name | |
| Test status | |
| Simulation time | 15664493120 ps |
| CPU time | 263.65 seconds |
| Started | Jun 28 08:51:09 PM PDT 24 |
| Finished | Jun 28 08:56:01 PM PDT 24 |
| Peak memory | 575316 kb |
| Host | smart-bfd1704b-4163-4662-8467-0b0782744183 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1977504836 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 92.xbar_random_slow_rsp.1977504836 |
| Directory | /workspace/92.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/92.xbar_random_zero_delays.419219641 |
| Short name | T1566 |
| Test name | |
| Test status | |
| Simulation time | 275446378 ps |
| CPU time | 25.74 seconds |
| Started | Jun 28 08:51:05 PM PDT 24 |
| Finished | Jun 28 08:51:58 PM PDT 24 |
| Peak memory | 575240 kb |
| Host | smart-b4053be6-512f-4677-8300-a77301f26f33 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=419219641 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 92.xbar_random_zero_dela ys.419219641 |
| Directory | /workspace/92.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/92.xbar_same_source.419880972 |
| Short name | T2052 |
| Test name | |
| Test status | |
| Simulation time | 1201383528 ps |
| CPU time | 38 seconds |
| Started | Jun 28 08:51:10 PM PDT 24 |
| Finished | Jun 28 08:52:16 PM PDT 24 |
| Peak memory | 575108 kb |
| Host | smart-73bd3e1c-cfc2-4435-964e-c67e75b64253 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=419880972 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 92.xbar_same_source.419880972 |
| Directory | /workspace/92.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/92.xbar_smoke.2931847146 |
| Short name | T2033 |
| Test name | |
| Test status | |
| Simulation time | 151915614 ps |
| CPU time | 7.1 seconds |
| Started | Jun 28 08:51:09 PM PDT 24 |
| Finished | Jun 28 08:51:44 PM PDT 24 |
| Peak memory | 574064 kb |
| Host | smart-a913ba02-529f-4192-9768-ed5619ea33ac |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2931847146 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 92.xbar_smoke.2931847146 |
| Directory | /workspace/92.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/92.xbar_smoke_large_delays.3964366053 |
| Short name | T1624 |
| Test name | |
| Test status | |
| Simulation time | 7959833300 ps |
| CPU time | 91.38 seconds |
| Started | Jun 28 08:51:09 PM PDT 24 |
| Finished | Jun 28 08:53:08 PM PDT 24 |
| Peak memory | 574256 kb |
| Host | smart-d6e24181-6f03-4044-b7d0-fb3e5b1c28b6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3964366053 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 92.xbar_smoke_large_delays.3964366053 |
| Directory | /workspace/92.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/92.xbar_smoke_slow_rsp.3489787833 |
| Short name | T1988 |
| Test name | |
| Test status | |
| Simulation time | 6423367098 ps |
| CPU time | 109.17 seconds |
| Started | Jun 28 08:51:06 PM PDT 24 |
| Finished | Jun 28 08:53:23 PM PDT 24 |
| Peak memory | 574260 kb |
| Host | smart-c81dcfcb-2dfa-4324-a579-b91757aa1a26 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3489787833 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 92.xbar_smoke_slow_rsp.3489787833 |
| Directory | /workspace/92.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/92.xbar_smoke_zero_delays.3961443267 |
| Short name | T2162 |
| Test name | |
| Test status | |
| Simulation time | 43085517 ps |
| CPU time | 6.45 seconds |
| Started | Jun 28 08:50:59 PM PDT 24 |
| Finished | Jun 28 08:51:32 PM PDT 24 |
| Peak memory | 574172 kb |
| Host | smart-c5929dc3-5d4f-4c40-ba42-042384c3ad8a |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3961443267 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 92.xbar_smoke_zero_delay s.3961443267 |
| Directory | /workspace/92.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/92.xbar_stress_all.2873338476 |
| Short name | T2666 |
| Test name | |
| Test status | |
| Simulation time | 3742665485 ps |
| CPU time | 298 seconds |
| Started | Jun 28 08:51:29 PM PDT 24 |
| Finished | Jun 28 08:56:48 PM PDT 24 |
| Peak memory | 574400 kb |
| Host | smart-64ec6638-8c34-48be-ab3e-a2197d7f2acd |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2873338476 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 92.xbar_stress_all.2873338476 |
| Directory | /workspace/92.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/92.xbar_stress_all_with_error.3514400498 |
| Short name | T2711 |
| Test name | |
| Test status | |
| Simulation time | 3643069016 ps |
| CPU time | 114.99 seconds |
| Started | Jun 28 08:51:41 PM PDT 24 |
| Finished | Jun 28 08:53:53 PM PDT 24 |
| Peak memory | 574272 kb |
| Host | smart-c9603f50-5765-4523-afb9-625b258eeed0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3514400498 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 92.xbar_stress_all_with_error.3514400498 |
| Directory | /workspace/92.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/92.xbar_stress_all_with_rand_reset.3674341969 |
| Short name | T2274 |
| Test name | |
| Test status | |
| Simulation time | 2252016471 ps |
| CPU time | 242.59 seconds |
| Started | Jun 28 08:51:28 PM PDT 24 |
| Finished | Jun 28 08:55:51 PM PDT 24 |
| Peak memory | 574392 kb |
| Host | smart-31c9b5e4-1164-4e91-aa3a-24f0523779f6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3674341969 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 92.xbar_stress_all _with_rand_reset.3674341969 |
| Directory | /workspace/92.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/92.xbar_stress_all_with_reset_error.3178433979 |
| Short name | T849 |
| Test name | |
| Test status | |
| Simulation time | 242616702 ps |
| CPU time | 73.62 seconds |
| Started | Jun 28 08:51:25 PM PDT 24 |
| Finished | Jun 28 08:53:01 PM PDT 24 |
| Peak memory | 574344 kb |
| Host | smart-34b39953-d60a-4493-af7c-761215a3a696 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3178433979 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 92.xbar_stress_al l_with_reset_error.3178433979 |
| Directory | /workspace/92.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/92.xbar_unmapped_addr.3180375934 |
| Short name | T1817 |
| Test name | |
| Test status | |
| Simulation time | 1367409079 ps |
| CPU time | 60.12 seconds |
| Started | Jun 28 08:51:41 PM PDT 24 |
| Finished | Jun 28 08:52:57 PM PDT 24 |
| Peak memory | 575304 kb |
| Host | smart-9954bb9e-f443-43c6-8987-143aba901d24 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3180375934 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 92.xbar_unmapped_addr.3180375934 |
| Directory | /workspace/92.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/93.xbar_access_same_device.461270758 |
| Short name | T2567 |
| Test name | |
| Test status | |
| Simulation time | 613268570 ps |
| CPU time | 52.82 seconds |
| Started | Jun 28 08:51:41 PM PDT 24 |
| Finished | Jun 28 08:52:50 PM PDT 24 |
| Peak memory | 575224 kb |
| Host | smart-df3dfb65-2780-419d-9d4c-739727c4cf71 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=461270758 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 93.xbar_access_same_device. 461270758 |
| Directory | /workspace/93.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/93.xbar_access_same_device_slow_rsp.3725830958 |
| Short name | T2865 |
| Test name | |
| Test status | |
| Simulation time | 14406959895 ps |
| CPU time | 252.8 seconds |
| Started | Jun 28 08:51:27 PM PDT 24 |
| Finished | Jun 28 08:56:01 PM PDT 24 |
| Peak memory | 575316 kb |
| Host | smart-961a9539-e332-4604-921b-56b51fc70035 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3725830958 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 93.xbar_access_same_ device_slow_rsp.3725830958 |
| Directory | /workspace/93.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/93.xbar_error_and_unmapped_addr.3510468681 |
| Short name | T524 |
| Test name | |
| Test status | |
| Simulation time | 1150020026 ps |
| CPU time | 45.47 seconds |
| Started | Jun 28 08:51:27 PM PDT 24 |
| Finished | Jun 28 08:52:34 PM PDT 24 |
| Peak memory | 574436 kb |
| Host | smart-42fc2b8b-2f30-4b66-aaa6-7c7002a3f69d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3510468681 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 93.xbar_error_and_unmapped_add r.3510468681 |
| Directory | /workspace/93.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/93.xbar_error_random.1732168827 |
| Short name | T1713 |
| Test name | |
| Test status | |
| Simulation time | 1410704913 ps |
| CPU time | 47.01 seconds |
| Started | Jun 28 08:51:26 PM PDT 24 |
| Finished | Jun 28 08:52:34 PM PDT 24 |
| Peak memory | 574188 kb |
| Host | smart-cadf2d6a-08c2-4233-8893-b39ba936aac1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1732168827 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 93.xbar_error_random.1732168827 |
| Directory | /workspace/93.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/93.xbar_random.3131276506 |
| Short name | T2066 |
| Test name | |
| Test status | |
| Simulation time | 1483796743 ps |
| CPU time | 59.71 seconds |
| Started | Jun 28 08:51:26 PM PDT 24 |
| Finished | Jun 28 08:52:47 PM PDT 24 |
| Peak memory | 575192 kb |
| Host | smart-6ac6c82b-427c-4a3a-9229-043e24a81787 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3131276506 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 93.xbar_random.3131276506 |
| Directory | /workspace/93.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/93.xbar_random_large_delays.288516853 |
| Short name | T2873 |
| Test name | |
| Test status | |
| Simulation time | 29866165071 ps |
| CPU time | 289.27 seconds |
| Started | Jun 28 08:51:29 PM PDT 24 |
| Finished | Jun 28 08:56:39 PM PDT 24 |
| Peak memory | 575304 kb |
| Host | smart-cc6532f6-fbcc-4003-8c27-ba64a60ee7bc |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=288516853 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 93.xbar_random_large_delays.288516853 |
| Directory | /workspace/93.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/93.xbar_random_slow_rsp.3993558157 |
| Short name | T2388 |
| Test name | |
| Test status | |
| Simulation time | 28174345821 ps |
| CPU time | 480.12 seconds |
| Started | Jun 28 08:51:28 PM PDT 24 |
| Finished | Jun 28 08:59:49 PM PDT 24 |
| Peak memory | 575348 kb |
| Host | smart-8f00e660-24f4-4b64-97fb-4e3bee5ddeef |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3993558157 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 93.xbar_random_slow_rsp.3993558157 |
| Directory | /workspace/93.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/93.xbar_random_zero_delays.3164225994 |
| Short name | T2730 |
| Test name | |
| Test status | |
| Simulation time | 127430755 ps |
| CPU time | 14.62 seconds |
| Started | Jun 28 08:51:26 PM PDT 24 |
| Finished | Jun 28 08:52:02 PM PDT 24 |
| Peak memory | 575264 kb |
| Host | smart-433b409b-3c5f-403b-843d-8cd360c71cc2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3164225994 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 93.xbar_random_zero_del ays.3164225994 |
| Directory | /workspace/93.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/93.xbar_same_source.2226879360 |
| Short name | T1371 |
| Test name | |
| Test status | |
| Simulation time | 416661634 ps |
| CPU time | 30.61 seconds |
| Started | Jun 28 08:51:32 PM PDT 24 |
| Finished | Jun 28 08:52:22 PM PDT 24 |
| Peak memory | 575220 kb |
| Host | smart-890ad396-d755-4ae7-b8d7-ca005f25a35b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2226879360 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 93.xbar_same_source.2226879360 |
| Directory | /workspace/93.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/93.xbar_smoke.714231472 |
| Short name | T2786 |
| Test name | |
| Test status | |
| Simulation time | 49123232 ps |
| CPU time | 6.95 seconds |
| Started | Jun 28 08:51:32 PM PDT 24 |
| Finished | Jun 28 08:51:58 PM PDT 24 |
| Peak memory | 574172 kb |
| Host | smart-5f76f1cb-24b5-4eed-88ca-535d9a919e40 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=714231472 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 93.xbar_smoke.714231472 |
| Directory | /workspace/93.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/93.xbar_smoke_large_delays.1733676158 |
| Short name | T1426 |
| Test name | |
| Test status | |
| Simulation time | 8882721979 ps |
| CPU time | 90.95 seconds |
| Started | Jun 28 08:51:28 PM PDT 24 |
| Finished | Jun 28 08:53:20 PM PDT 24 |
| Peak memory | 574252 kb |
| Host | smart-5e118746-4107-41c5-944d-198a624c31ff |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1733676158 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 93.xbar_smoke_large_delays.1733676158 |
| Directory | /workspace/93.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/93.xbar_smoke_slow_rsp.2084906439 |
| Short name | T1543 |
| Test name | |
| Test status | |
| Simulation time | 6401831076 ps |
| CPU time | 114.27 seconds |
| Started | Jun 28 08:51:41 PM PDT 24 |
| Finished | Jun 28 08:53:52 PM PDT 24 |
| Peak memory | 574248 kb |
| Host | smart-2bad64aa-fa3d-406a-ade5-5c0a484ca95f |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2084906439 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 93.xbar_smoke_slow_rsp.2084906439 |
| Directory | /workspace/93.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/93.xbar_smoke_zero_delays.428869221 |
| Short name | T1860 |
| Test name | |
| Test status | |
| Simulation time | 50226189 ps |
| CPU time | 6.72 seconds |
| Started | Jun 28 08:51:32 PM PDT 24 |
| Finished | Jun 28 08:51:58 PM PDT 24 |
| Peak memory | 565924 kb |
| Host | smart-75cdbc6f-dec9-41fc-bca7-0f40e35a738b |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=428869221 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 93.xbar_smoke_zero_delays .428869221 |
| Directory | /workspace/93.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/93.xbar_stress_all.3015811575 |
| Short name | T1758 |
| Test name | |
| Test status | |
| Simulation time | 10864553907 ps |
| CPU time | 388.72 seconds |
| Started | Jun 28 08:51:26 PM PDT 24 |
| Finished | Jun 28 08:58:15 PM PDT 24 |
| Peak memory | 575436 kb |
| Host | smart-58650a7a-68e0-4310-8188-21154f330825 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3015811575 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 93.xbar_stress_all.3015811575 |
| Directory | /workspace/93.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/93.xbar_stress_all_with_error.1888594952 |
| Short name | T1494 |
| Test name | |
| Test status | |
| Simulation time | 12378480080 ps |
| CPU time | 362.72 seconds |
| Started | Jun 28 08:51:42 PM PDT 24 |
| Finished | Jun 28 08:58:01 PM PDT 24 |
| Peak memory | 574392 kb |
| Host | smart-695b032d-1a60-48ad-9301-aee753f174e2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1888594952 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 93.xbar_stress_all_with_error.1888594952 |
| Directory | /workspace/93.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/93.xbar_stress_all_with_rand_reset.1786546141 |
| Short name | T1613 |
| Test name | |
| Test status | |
| Simulation time | 185750326 ps |
| CPU time | 37.33 seconds |
| Started | Jun 28 08:51:25 PM PDT 24 |
| Finished | Jun 28 08:52:25 PM PDT 24 |
| Peak memory | 576468 kb |
| Host | smart-0bf1c6be-da44-46d2-b39f-660277216316 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1786546141 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 93.xbar_stress_all _with_rand_reset.1786546141 |
| Directory | /workspace/93.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/93.xbar_stress_all_with_reset_error.1275433143 |
| Short name | T833 |
| Test name | |
| Test status | |
| Simulation time | 13677825561 ps |
| CPU time | 661.43 seconds |
| Started | Jun 28 08:51:28 PM PDT 24 |
| Finished | Jun 28 09:02:50 PM PDT 24 |
| Peak memory | 576468 kb |
| Host | smart-4d1ed0cf-ee6d-4e61-917b-e0f63c2c90c5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1275433143 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 93.xbar_stress_al l_with_reset_error.1275433143 |
| Directory | /workspace/93.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/93.xbar_unmapped_addr.561929948 |
| Short name | T1783 |
| Test name | |
| Test status | |
| Simulation time | 1323872267 ps |
| CPU time | 57.12 seconds |
| Started | Jun 28 08:51:29 PM PDT 24 |
| Finished | Jun 28 08:52:47 PM PDT 24 |
| Peak memory | 575292 kb |
| Host | smart-ab6d6565-056c-4e35-9a54-964dd83b2d1d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=561929948 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 93.xbar_unmapped_addr.561929948 |
| Directory | /workspace/93.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/94.xbar_access_same_device.4175755617 |
| Short name | T502 |
| Test name | |
| Test status | |
| Simulation time | 2601357381 ps |
| CPU time | 114.97 seconds |
| Started | Jun 28 08:51:49 PM PDT 24 |
| Finished | Jun 28 08:54:02 PM PDT 24 |
| Peak memory | 575320 kb |
| Host | smart-68a94353-3948-4ba6-a911-fcf4ea602043 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4175755617 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 94.xbar_access_same_device .4175755617 |
| Directory | /workspace/94.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/94.xbar_access_same_device_slow_rsp.865417411 |
| Short name | T2271 |
| Test name | |
| Test status | |
| Simulation time | 17701672521 ps |
| CPU time | 317.53 seconds |
| Started | Jun 28 08:51:44 PM PDT 24 |
| Finished | Jun 28 08:57:19 PM PDT 24 |
| Peak memory | 574240 kb |
| Host | smart-55cb1685-8f13-40f2-a5a7-108bec74bd52 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=865417411 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 94.xbar_access_same_d evice_slow_rsp.865417411 |
| Directory | /workspace/94.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/94.xbar_error_and_unmapped_addr.2744506519 |
| Short name | T1414 |
| Test name | |
| Test status | |
| Simulation time | 1089436020 ps |
| CPU time | 44.66 seconds |
| Started | Jun 28 08:51:47 PM PDT 24 |
| Finished | Jun 28 08:52:49 PM PDT 24 |
| Peak memory | 574444 kb |
| Host | smart-59a55070-f9f8-4eb4-86c4-6c05d41b2aad |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2744506519 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 94.xbar_error_and_unmapped_add r.2744506519 |
| Directory | /workspace/94.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/94.xbar_error_random.2031315381 |
| Short name | T2304 |
| Test name | |
| Test status | |
| Simulation time | 538572856 ps |
| CPU time | 51.05 seconds |
| Started | Jun 28 08:51:48 PM PDT 24 |
| Finished | Jun 28 08:52:56 PM PDT 24 |
| Peak memory | 573768 kb |
| Host | smart-ec05500f-5f96-47d0-8b62-f1616898c526 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2031315381 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 94.xbar_error_random.2031315381 |
| Directory | /workspace/94.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/94.xbar_random.2394170887 |
| Short name | T1904 |
| Test name | |
| Test status | |
| Simulation time | 556518159 ps |
| CPU time | 54 seconds |
| Started | Jun 28 08:51:46 PM PDT 24 |
| Finished | Jun 28 08:52:57 PM PDT 24 |
| Peak memory | 575276 kb |
| Host | smart-da8165fb-2687-4b6a-9d1e-d0d8671ab867 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2394170887 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 94.xbar_random.2394170887 |
| Directory | /workspace/94.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/94.xbar_random_large_delays.1488184639 |
| Short name | T2771 |
| Test name | |
| Test status | |
| Simulation time | 74680742234 ps |
| CPU time | 735.72 seconds |
| Started | Jun 28 08:51:45 PM PDT 24 |
| Finished | Jun 28 09:04:17 PM PDT 24 |
| Peak memory | 575284 kb |
| Host | smart-0bb022d9-8201-4b90-bc37-ff1f6ee2129d |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1488184639 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 94.xbar_random_large_delays.1488184639 |
| Directory | /workspace/94.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/94.xbar_random_slow_rsp.2167477327 |
| Short name | T2689 |
| Test name | |
| Test status | |
| Simulation time | 47117282786 ps |
| CPU time | 791.48 seconds |
| Started | Jun 28 08:51:46 PM PDT 24 |
| Finished | Jun 28 09:05:15 PM PDT 24 |
| Peak memory | 575340 kb |
| Host | smart-becc1bc7-be3c-41a0-b64d-cc8de05f53ae |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2167477327 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 94.xbar_random_slow_rsp.2167477327 |
| Directory | /workspace/94.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/94.xbar_random_zero_delays.3819367945 |
| Short name | T2176 |
| Test name | |
| Test status | |
| Simulation time | 492806411 ps |
| CPU time | 46.85 seconds |
| Started | Jun 28 08:51:46 PM PDT 24 |
| Finished | Jun 28 08:52:50 PM PDT 24 |
| Peak memory | 575256 kb |
| Host | smart-b330d7bc-6366-4f89-92be-e3ad3183e777 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3819367945 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 94.xbar_random_zero_del ays.3819367945 |
| Directory | /workspace/94.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/94.xbar_same_source.2794218409 |
| Short name | T609 |
| Test name | |
| Test status | |
| Simulation time | 544743049 ps |
| CPU time | 42.83 seconds |
| Started | Jun 28 08:51:46 PM PDT 24 |
| Finished | Jun 28 08:52:46 PM PDT 24 |
| Peak memory | 575224 kb |
| Host | smart-55983fa3-1b55-4e93-b52c-b318d720a22d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2794218409 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 94.xbar_same_source.2794218409 |
| Directory | /workspace/94.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/94.xbar_smoke.2261226268 |
| Short name | T2776 |
| Test name | |
| Test status | |
| Simulation time | 212045351 ps |
| CPU time | 9.55 seconds |
| Started | Jun 28 08:51:26 PM PDT 24 |
| Finished | Jun 28 08:51:56 PM PDT 24 |
| Peak memory | 574200 kb |
| Host | smart-7efe6268-2f6a-4b64-bc5e-67c00a308c83 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2261226268 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 94.xbar_smoke.2261226268 |
| Directory | /workspace/94.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/94.xbar_smoke_large_delays.3074548275 |
| Short name | T1716 |
| Test name | |
| Test status | |
| Simulation time | 7798053360 ps |
| CPU time | 85.57 seconds |
| Started | Jun 28 08:51:45 PM PDT 24 |
| Finished | Jun 28 08:53:28 PM PDT 24 |
| Peak memory | 574208 kb |
| Host | smart-b590239d-9983-4c5d-991e-721d5acdfb4f |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3074548275 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 94.xbar_smoke_large_delays.3074548275 |
| Directory | /workspace/94.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/94.xbar_smoke_slow_rsp.3611047967 |
| Short name | T1685 |
| Test name | |
| Test status | |
| Simulation time | 4351903668 ps |
| CPU time | 76.98 seconds |
| Started | Jun 28 08:51:46 PM PDT 24 |
| Finished | Jun 28 08:53:20 PM PDT 24 |
| Peak memory | 566004 kb |
| Host | smart-16729115-3ff1-4ad0-b0e0-42e0e45b8b1a |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3611047967 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 94.xbar_smoke_slow_rsp.3611047967 |
| Directory | /workspace/94.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/94.xbar_smoke_zero_delays.22282875 |
| Short name | T1890 |
| Test name | |
| Test status | |
| Simulation time | 50143185 ps |
| CPU time | 6.24 seconds |
| Started | Jun 28 08:51:42 PM PDT 24 |
| Finished | Jun 28 08:52:05 PM PDT 24 |
| Peak memory | 574184 kb |
| Host | smart-12356b46-86a6-495d-8218-9d664e4b843f |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22282875 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 94.xbar_smoke_zero_delays.22282875 |
| Directory | /workspace/94.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/94.xbar_stress_all.1234419043 |
| Short name | T2188 |
| Test name | |
| Test status | |
| Simulation time | 2628809817 ps |
| CPU time | 234.26 seconds |
| Started | Jun 28 08:51:49 PM PDT 24 |
| Finished | Jun 28 08:56:01 PM PDT 24 |
| Peak memory | 575448 kb |
| Host | smart-6643978d-55f5-4fbf-aac7-fc5963d3e2f0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1234419043 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 94.xbar_stress_all.1234419043 |
| Directory | /workspace/94.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/94.xbar_stress_all_with_error.2086360507 |
| Short name | T806 |
| Test name | |
| Test status | |
| Simulation time | 2626213728 ps |
| CPU time | 153.29 seconds |
| Started | Jun 28 08:51:43 PM PDT 24 |
| Finished | Jun 28 08:54:33 PM PDT 24 |
| Peak memory | 574316 kb |
| Host | smart-d976b9f2-3fdc-4205-839f-ac48c2b1f6a5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2086360507 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 94.xbar_stress_all_with_error.2086360507 |
| Directory | /workspace/94.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/94.xbar_stress_all_with_rand_reset.2434349117 |
| Short name | T1604 |
| Test name | |
| Test status | |
| Simulation time | 68472026 ps |
| CPU time | 9.55 seconds |
| Started | Jun 28 08:51:54 PM PDT 24 |
| Finished | Jun 28 08:52:20 PM PDT 24 |
| Peak memory | 566092 kb |
| Host | smart-f44b5d83-ca78-4d1f-a628-fe2221e35417 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2434349117 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 94.xbar_stress_all _with_rand_reset.2434349117 |
| Directory | /workspace/94.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/94.xbar_stress_all_with_reset_error.607846133 |
| Short name | T2882 |
| Test name | |
| Test status | |
| Simulation time | 127969068 ps |
| CPU time | 33.03 seconds |
| Started | Jun 28 08:51:50 PM PDT 24 |
| Finished | Jun 28 08:52:40 PM PDT 24 |
| Peak memory | 576360 kb |
| Host | smart-6c95cbc2-8d09-43eb-9fdc-46966787947d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=607846133 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 94.xbar_stress_all _with_reset_error.607846133 |
| Directory | /workspace/94.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/94.xbar_unmapped_addr.515750252 |
| Short name | T2234 |
| Test name | |
| Test status | |
| Simulation time | 666497936 ps |
| CPU time | 29.69 seconds |
| Started | Jun 28 08:51:46 PM PDT 24 |
| Finished | Jun 28 08:52:32 PM PDT 24 |
| Peak memory | 574136 kb |
| Host | smart-25135090-af52-404d-8110-352cd278ec17 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=515750252 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 94.xbar_unmapped_addr.515750252 |
| Directory | /workspace/94.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/95.xbar_access_same_device.3593830714 |
| Short name | T2721 |
| Test name | |
| Test status | |
| Simulation time | 3069225717 ps |
| CPU time | 140.84 seconds |
| Started | Jun 28 08:52:09 PM PDT 24 |
| Finished | Jun 28 08:54:37 PM PDT 24 |
| Peak memory | 574212 kb |
| Host | smart-53a23e4c-7f7b-4fd8-a930-7f55c6defaba |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3593830714 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 95.xbar_access_same_device .3593830714 |
| Directory | /workspace/95.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/95.xbar_access_same_device_slow_rsp.1537165347 |
| Short name | T2268 |
| Test name | |
| Test status | |
| Simulation time | 151835523392 ps |
| CPU time | 2648.12 seconds |
| Started | Jun 28 08:52:13 PM PDT 24 |
| Finished | Jun 28 09:36:26 PM PDT 24 |
| Peak memory | 574364 kb |
| Host | smart-31712222-1ad5-4c17-b2f5-c9e648cdda78 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1537165347 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 95.xbar_access_same_ device_slow_rsp.1537165347 |
| Directory | /workspace/95.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/95.xbar_error_and_unmapped_addr.3081147787 |
| Short name | T2261 |
| Test name | |
| Test status | |
| Simulation time | 326665868 ps |
| CPU time | 34.88 seconds |
| Started | Jun 28 08:52:11 PM PDT 24 |
| Finished | Jun 28 08:52:52 PM PDT 24 |
| Peak memory | 574420 kb |
| Host | smart-c4c03532-ce4e-41b7-b708-256ae43cfd49 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3081147787 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 95.xbar_error_and_unmapped_add r.3081147787 |
| Directory | /workspace/95.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/95.xbar_error_random.4217705959 |
| Short name | T2631 |
| Test name | |
| Test status | |
| Simulation time | 194721524 ps |
| CPU time | 19.45 seconds |
| Started | Jun 28 08:52:10 PM PDT 24 |
| Finished | Jun 28 08:52:36 PM PDT 24 |
| Peak memory | 574404 kb |
| Host | smart-8eacd897-4fc2-4057-b286-51ddd6803440 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4217705959 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 95.xbar_error_random.4217705959 |
| Directory | /workspace/95.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/95.xbar_random.1475574767 |
| Short name | T2012 |
| Test name | |
| Test status | |
| Simulation time | 499654767 ps |
| CPU time | 44.74 seconds |
| Started | Jun 28 08:51:45 PM PDT 24 |
| Finished | Jun 28 08:52:47 PM PDT 24 |
| Peak memory | 575280 kb |
| Host | smart-9647140b-8a8c-45bb-934b-c4a15dd6abcc |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1475574767 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 95.xbar_random.1475574767 |
| Directory | /workspace/95.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/95.xbar_random_large_delays.303393258 |
| Short name | T1644 |
| Test name | |
| Test status | |
| Simulation time | 29832080295 ps |
| CPU time | 309.31 seconds |
| Started | Jun 28 08:51:47 PM PDT 24 |
| Finished | Jun 28 08:57:13 PM PDT 24 |
| Peak memory | 575324 kb |
| Host | smart-7e8f446f-d088-4742-ab41-2cf5591b0961 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=303393258 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 95.xbar_random_large_delays.303393258 |
| Directory | /workspace/95.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/95.xbar_random_slow_rsp.1890499739 |
| Short name | T2862 |
| Test name | |
| Test status | |
| Simulation time | 3985160541 ps |
| CPU time | 68.79 seconds |
| Started | Jun 28 08:51:49 PM PDT 24 |
| Finished | Jun 28 08:53:16 PM PDT 24 |
| Peak memory | 574092 kb |
| Host | smart-929a5496-7061-4cbf-9532-514ace159cd5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1890499739 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 95.xbar_random_slow_rsp.1890499739 |
| Directory | /workspace/95.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/95.xbar_random_zero_delays.2490931627 |
| Short name | T566 |
| Test name | |
| Test status | |
| Simulation time | 116465607 ps |
| CPU time | 13.8 seconds |
| Started | Jun 28 08:51:52 PM PDT 24 |
| Finished | Jun 28 08:52:23 PM PDT 24 |
| Peak memory | 575232 kb |
| Host | smart-5147b74d-fe3d-4dd9-a099-e067123fc2d0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2490931627 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 95.xbar_random_zero_del ays.2490931627 |
| Directory | /workspace/95.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/95.xbar_same_source.3487055570 |
| Short name | T2190 |
| Test name | |
| Test status | |
| Simulation time | 2450427743 ps |
| CPU time | 81.77 seconds |
| Started | Jun 28 08:52:10 PM PDT 24 |
| Finished | Jun 28 08:53:38 PM PDT 24 |
| Peak memory | 575308 kb |
| Host | smart-84890313-98c5-4c09-9ba3-7ffa347a8b73 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3487055570 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 95.xbar_same_source.3487055570 |
| Directory | /workspace/95.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/95.xbar_smoke.3605127807 |
| Short name | T2649 |
| Test name | |
| Test status | |
| Simulation time | 39505472 ps |
| CPU time | 6.26 seconds |
| Started | Jun 28 08:51:46 PM PDT 24 |
| Finished | Jun 28 08:52:09 PM PDT 24 |
| Peak memory | 565960 kb |
| Host | smart-3c9a91fd-774e-47b2-b12a-804679e7f18d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3605127807 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 95.xbar_smoke.3605127807 |
| Directory | /workspace/95.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/95.xbar_smoke_large_delays.1492787173 |
| Short name | T2113 |
| Test name | |
| Test status | |
| Simulation time | 8510142459 ps |
| CPU time | 87.97 seconds |
| Started | Jun 28 08:51:38 PM PDT 24 |
| Finished | Jun 28 08:53:22 PM PDT 24 |
| Peak memory | 574248 kb |
| Host | smart-5dec0c5d-08d5-4734-8a94-db9fbb207ee8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1492787173 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 95.xbar_smoke_large_delays.1492787173 |
| Directory | /workspace/95.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/95.xbar_smoke_slow_rsp.3727200002 |
| Short name | T2457 |
| Test name | |
| Test status | |
| Simulation time | 5251230497 ps |
| CPU time | 90.82 seconds |
| Started | Jun 28 08:51:49 PM PDT 24 |
| Finished | Jun 28 08:53:37 PM PDT 24 |
| Peak memory | 574268 kb |
| Host | smart-009757bb-f7f5-4074-9f61-3e8693559f3f |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3727200002 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 95.xbar_smoke_slow_rsp.3727200002 |
| Directory | /workspace/95.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/95.xbar_smoke_zero_delays.2356770395 |
| Short name | T1939 |
| Test name | |
| Test status | |
| Simulation time | 54196018 ps |
| CPU time | 6.23 seconds |
| Started | Jun 28 08:51:47 PM PDT 24 |
| Finished | Jun 28 08:52:10 PM PDT 24 |
| Peak memory | 574192 kb |
| Host | smart-888216ef-5f6e-4265-9417-fe15e3ed649d |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2356770395 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 95.xbar_smoke_zero_delay s.2356770395 |
| Directory | /workspace/95.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/95.xbar_stress_all_with_error.1460934426 |
| Short name | T2488 |
| Test name | |
| Test status | |
| Simulation time | 3065977347 ps |
| CPU time | 245.81 seconds |
| Started | Jun 28 08:52:12 PM PDT 24 |
| Finished | Jun 28 08:56:23 PM PDT 24 |
| Peak memory | 574676 kb |
| Host | smart-17a8812a-167c-4d12-8c89-bf6ae82ab99e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1460934426 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 95.xbar_stress_all_with_error.1460934426 |
| Directory | /workspace/95.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/95.xbar_stress_all_with_rand_reset.3109042701 |
| Short name | T835 |
| Test name | |
| Test status | |
| Simulation time | 5202550681 ps |
| CPU time | 400.71 seconds |
| Started | Jun 28 08:52:13 PM PDT 24 |
| Finished | Jun 28 08:58:58 PM PDT 24 |
| Peak memory | 575444 kb |
| Host | smart-9f5fc769-c779-42d7-a01f-43b4d2a42dd4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3109042701 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 95.xbar_stress_all _with_rand_reset.3109042701 |
| Directory | /workspace/95.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/95.xbar_stress_all_with_reset_error.3826267109 |
| Short name | T785 |
| Test name | |
| Test status | |
| Simulation time | 4618080270 ps |
| CPU time | 302.59 seconds |
| Started | Jun 28 08:52:13 PM PDT 24 |
| Finished | Jun 28 08:57:20 PM PDT 24 |
| Peak memory | 574664 kb |
| Host | smart-3a267eb5-0218-42d3-9aee-1a30deddac27 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3826267109 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 95.xbar_stress_al l_with_reset_error.3826267109 |
| Directory | /workspace/95.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/95.xbar_unmapped_addr.263529136 |
| Short name | T2124 |
| Test name | |
| Test status | |
| Simulation time | 139180882 ps |
| CPU time | 20.02 seconds |
| Started | Jun 28 08:52:10 PM PDT 24 |
| Finished | Jun 28 08:52:37 PM PDT 24 |
| Peak memory | 575292 kb |
| Host | smart-f5f09626-dcdc-4bd0-8d29-2e0a06aec99d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=263529136 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 95.xbar_unmapped_addr.263529136 |
| Directory | /workspace/95.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/96.xbar_access_same_device.1025704750 |
| Short name | T2869 |
| Test name | |
| Test status | |
| Simulation time | 1274241350 ps |
| CPU time | 88.86 seconds |
| Started | Jun 28 08:52:11 PM PDT 24 |
| Finished | Jun 28 08:53:46 PM PDT 24 |
| Peak memory | 575288 kb |
| Host | smart-13086b09-9a1e-4c63-b160-279638b89812 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1025704750 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 96.xbar_access_same_device .1025704750 |
| Directory | /workspace/96.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/96.xbar_access_same_device_slow_rsp.837916584 |
| Short name | T2171 |
| Test name | |
| Test status | |
| Simulation time | 107245627745 ps |
| CPU time | 1904.97 seconds |
| Started | Jun 28 08:52:12 PM PDT 24 |
| Finished | Jun 28 09:24:03 PM PDT 24 |
| Peak memory | 575420 kb |
| Host | smart-253171f2-c7b1-4f33-82a7-d6e42c60f8c5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=837916584 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 96.xbar_access_same_d evice_slow_rsp.837916584 |
| Directory | /workspace/96.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/96.xbar_error_and_unmapped_addr.516186446 |
| Short name | T2685 |
| Test name | |
| Test status | |
| Simulation time | 1320037043 ps |
| CPU time | 53.03 seconds |
| Started | Jun 28 08:52:12 PM PDT 24 |
| Finished | Jun 28 08:53:11 PM PDT 24 |
| Peak memory | 574448 kb |
| Host | smart-2caf54d6-eacc-4b0b-bee0-b3a45148c35f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=516186446 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 96.xbar_error_and_unmapped_addr .516186446 |
| Directory | /workspace/96.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/96.xbar_error_random.2051283592 |
| Short name | T1951 |
| Test name | |
| Test status | |
| Simulation time | 743131968 ps |
| CPU time | 29.03 seconds |
| Started | Jun 28 08:52:10 PM PDT 24 |
| Finished | Jun 28 08:52:46 PM PDT 24 |
| Peak memory | 574348 kb |
| Host | smart-c9cf0bc4-2b2a-4338-838f-6d67e1c85bce |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2051283592 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 96.xbar_error_random.2051283592 |
| Directory | /workspace/96.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/96.xbar_random.1583079282 |
| Short name | T1767 |
| Test name | |
| Test status | |
| Simulation time | 514562158 ps |
| CPU time | 47.77 seconds |
| Started | Jun 28 08:52:12 PM PDT 24 |
| Finished | Jun 28 08:53:05 PM PDT 24 |
| Peak memory | 574216 kb |
| Host | smart-6f3a5820-1d2f-4a93-8370-f9e8557032ef |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1583079282 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 96.xbar_random.1583079282 |
| Directory | /workspace/96.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/96.xbar_random_large_delays.3725619273 |
| Short name | T2505 |
| Test name | |
| Test status | |
| Simulation time | 110232486588 ps |
| CPU time | 1232.18 seconds |
| Started | Jun 28 08:52:11 PM PDT 24 |
| Finished | Jun 28 09:12:49 PM PDT 24 |
| Peak memory | 575352 kb |
| Host | smart-44a3d1be-b369-4925-ba8d-7dcc21b16912 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3725619273 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 96.xbar_random_large_delays.3725619273 |
| Directory | /workspace/96.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/96.xbar_random_slow_rsp.3751551495 |
| Short name | T2058 |
| Test name | |
| Test status | |
| Simulation time | 3546384513 ps |
| CPU time | 64.33 seconds |
| Started | Jun 28 08:52:12 PM PDT 24 |
| Finished | Jun 28 08:53:21 PM PDT 24 |
| Peak memory | 574148 kb |
| Host | smart-ee82af48-53fd-4832-948a-d8312a397806 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3751551495 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 96.xbar_random_slow_rsp.3751551495 |
| Directory | /workspace/96.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/96.xbar_random_zero_delays.1585999675 |
| Short name | T591 |
| Test name | |
| Test status | |
| Simulation time | 521635834 ps |
| CPU time | 56.48 seconds |
| Started | Jun 28 08:52:12 PM PDT 24 |
| Finished | Jun 28 08:53:14 PM PDT 24 |
| Peak memory | 575300 kb |
| Host | smart-2b1c50e6-751b-4781-8962-9386688704d1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1585999675 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 96.xbar_random_zero_del ays.1585999675 |
| Directory | /workspace/96.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/96.xbar_same_source.1475340683 |
| Short name | T2472 |
| Test name | |
| Test status | |
| Simulation time | 1396341376 ps |
| CPU time | 42.51 seconds |
| Started | Jun 28 08:52:12 PM PDT 24 |
| Finished | Jun 28 08:53:00 PM PDT 24 |
| Peak memory | 575356 kb |
| Host | smart-f8eff869-c9c0-44a7-9343-491fbc12d48c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1475340683 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 96.xbar_same_source.1475340683 |
| Directory | /workspace/96.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/96.xbar_smoke.4193835318 |
| Short name | T1656 |
| Test name | |
| Test status | |
| Simulation time | 208687198 ps |
| CPU time | 10.31 seconds |
| Started | Jun 28 08:52:13 PM PDT 24 |
| Finished | Jun 28 08:52:28 PM PDT 24 |
| Peak memory | 574156 kb |
| Host | smart-df4c62df-c00f-464c-bd82-6ef56cc4ae08 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4193835318 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 96.xbar_smoke.4193835318 |
| Directory | /workspace/96.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/96.xbar_smoke_large_delays.3496985820 |
| Short name | T1573 |
| Test name | |
| Test status | |
| Simulation time | 7698848328 ps |
| CPU time | 78.56 seconds |
| Started | Jun 28 08:52:10 PM PDT 24 |
| Finished | Jun 28 08:53:35 PM PDT 24 |
| Peak memory | 574256 kb |
| Host | smart-fbfda3fc-c3f7-49de-839c-f6a9ca6d907e |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3496985820 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 96.xbar_smoke_large_delays.3496985820 |
| Directory | /workspace/96.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/96.xbar_smoke_slow_rsp.4176842319 |
| Short name | T1378 |
| Test name | |
| Test status | |
| Simulation time | 5441565762 ps |
| CPU time | 95.31 seconds |
| Started | Jun 28 08:52:11 PM PDT 24 |
| Finished | Jun 28 08:53:52 PM PDT 24 |
| Peak memory | 574256 kb |
| Host | smart-8cc894e4-5c18-431c-ada4-f2b8bfc1ac41 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4176842319 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 96.xbar_smoke_slow_rsp.4176842319 |
| Directory | /workspace/96.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/96.xbar_smoke_zero_delays.2454451431 |
| Short name | T2712 |
| Test name | |
| Test status | |
| Simulation time | 44113037 ps |
| CPU time | 6.16 seconds |
| Started | Jun 28 08:52:11 PM PDT 24 |
| Finished | Jun 28 08:52:23 PM PDT 24 |
| Peak memory | 574192 kb |
| Host | smart-9aa60064-549e-4ecc-affb-fc2082916ed3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2454451431 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 96.xbar_smoke_zero_delay s.2454451431 |
| Directory | /workspace/96.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/96.xbar_stress_all.2908907455 |
| Short name | T1990 |
| Test name | |
| Test status | |
| Simulation time | 7618905968 ps |
| CPU time | 276.94 seconds |
| Started | Jun 28 08:52:15 PM PDT 24 |
| Finished | Jun 28 08:56:56 PM PDT 24 |
| Peak memory | 574372 kb |
| Host | smart-0ebeec3f-43de-497b-a697-32351738c5cd |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2908907455 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 96.xbar_stress_all.2908907455 |
| Directory | /workspace/96.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/96.xbar_stress_all_with_error.4157872804 |
| Short name | T1541 |
| Test name | |
| Test status | |
| Simulation time | 6671966 ps |
| CPU time | 3.95 seconds |
| Started | Jun 28 08:52:15 PM PDT 24 |
| Finished | Jun 28 08:52:22 PM PDT 24 |
| Peak memory | 565756 kb |
| Host | smart-fa5ce8b6-da39-433a-a54f-db5d8538a46a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4157872804 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 96.xbar_stress_all_with_error.4157872804 |
| Directory | /workspace/96.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/96.xbar_stress_all_with_rand_reset.1298386351 |
| Short name | T2552 |
| Test name | |
| Test status | |
| Simulation time | 8351258010 ps |
| CPU time | 535 seconds |
| Started | Jun 28 08:52:13 PM PDT 24 |
| Finished | Jun 28 09:01:13 PM PDT 24 |
| Peak memory | 575416 kb |
| Host | smart-d05bcd7b-7445-49d9-80dc-4afb53eb656a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1298386351 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 96.xbar_stress_all _with_rand_reset.1298386351 |
| Directory | /workspace/96.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/96.xbar_stress_all_with_reset_error.1076582437 |
| Short name | T2191 |
| Test name | |
| Test status | |
| Simulation time | 930348533 ps |
| CPU time | 277.4 seconds |
| Started | Jun 28 08:52:14 PM PDT 24 |
| Finished | Jun 28 08:56:55 PM PDT 24 |
| Peak memory | 574340 kb |
| Host | smart-d46566aa-48db-4ee6-bdf0-b0a1d7fe1795 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1076582437 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 96.xbar_stress_al l_with_reset_error.1076582437 |
| Directory | /workspace/96.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/96.xbar_unmapped_addr.2092759528 |
| Short name | T1344 |
| Test name | |
| Test status | |
| Simulation time | 502212883 ps |
| CPU time | 25.17 seconds |
| Started | Jun 28 08:52:14 PM PDT 24 |
| Finished | Jun 28 08:52:43 PM PDT 24 |
| Peak memory | 575264 kb |
| Host | smart-6c3c5e38-0b3d-4143-bcdb-36e1824bbc92 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2092759528 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 96.xbar_unmapped_addr.2092759528 |
| Directory | /workspace/96.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/97.xbar_access_same_device.739629792 |
| Short name | T1901 |
| Test name | |
| Test status | |
| Simulation time | 785089354 ps |
| CPU time | 76.15 seconds |
| Started | Jun 28 08:52:42 PM PDT 24 |
| Finished | Jun 28 08:54:02 PM PDT 24 |
| Peak memory | 574220 kb |
| Host | smart-a8d9778a-25d2-4102-82d2-374739f573aa |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=739629792 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 97.xbar_access_same_device. 739629792 |
| Directory | /workspace/97.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/97.xbar_access_same_device_slow_rsp.283167741 |
| Short name | T786 |
| Test name | |
| Test status | |
| Simulation time | 83539494072 ps |
| CPU time | 1363.15 seconds |
| Started | Jun 28 08:52:42 PM PDT 24 |
| Finished | Jun 28 09:15:29 PM PDT 24 |
| Peak memory | 575380 kb |
| Host | smart-79bc568a-2afb-4f67-b0f1-1e161aedbcc0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=283167741 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 97.xbar_access_same_d evice_slow_rsp.283167741 |
| Directory | /workspace/97.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/97.xbar_error_and_unmapped_addr.2893706170 |
| Short name | T2289 |
| Test name | |
| Test status | |
| Simulation time | 346355103 ps |
| CPU time | 17.31 seconds |
| Started | Jun 28 08:52:39 PM PDT 24 |
| Finished | Jun 28 08:52:58 PM PDT 24 |
| Peak memory | 573836 kb |
| Host | smart-d710d222-2727-4eee-b530-d706fb86c7dc |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2893706170 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 97.xbar_error_and_unmapped_add r.2893706170 |
| Directory | /workspace/97.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/97.xbar_error_random.4249164856 |
| Short name | T2835 |
| Test name | |
| Test status | |
| Simulation time | 436481608 ps |
| CPU time | 34.62 seconds |
| Started | Jun 28 08:52:42 PM PDT 24 |
| Finished | Jun 28 08:53:19 PM PDT 24 |
| Peak memory | 573868 kb |
| Host | smart-12ce2ca8-94f6-4409-b0f5-134b9b37b5bb |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4249164856 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 97.xbar_error_random.4249164856 |
| Directory | /workspace/97.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/97.xbar_random.3388498195 |
| Short name | T1366 |
| Test name | |
| Test status | |
| Simulation time | 1213538084 ps |
| CPU time | 42.52 seconds |
| Started | Jun 28 08:52:12 PM PDT 24 |
| Finished | Jun 28 08:53:00 PM PDT 24 |
| Peak memory | 575140 kb |
| Host | smart-75cee25e-2e97-48f0-95fd-0666ed7bc03c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3388498195 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 97.xbar_random.3388498195 |
| Directory | /workspace/97.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/97.xbar_random_large_delays.3923727527 |
| Short name | T2198 |
| Test name | |
| Test status | |
| Simulation time | 18027856648 ps |
| CPU time | 182.1 seconds |
| Started | Jun 28 08:52:42 PM PDT 24 |
| Finished | Jun 28 08:55:47 PM PDT 24 |
| Peak memory | 575312 kb |
| Host | smart-3d4566f4-04db-4beb-8df5-a7092a1485ac |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3923727527 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 97.xbar_random_large_delays.3923727527 |
| Directory | /workspace/97.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/97.xbar_random_slow_rsp.3761224950 |
| Short name | T1825 |
| Test name | |
| Test status | |
| Simulation time | 48940144785 ps |
| CPU time | 866.88 seconds |
| Started | Jun 28 08:52:42 PM PDT 24 |
| Finished | Jun 28 09:07:12 PM PDT 24 |
| Peak memory | 575364 kb |
| Host | smart-171fd5de-fdee-4945-84ad-1dd1f5403b01 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3761224950 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 97.xbar_random_slow_rsp.3761224950 |
| Directory | /workspace/97.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/97.xbar_random_zero_delays.3900335398 |
| Short name | T2339 |
| Test name | |
| Test status | |
| Simulation time | 61766212 ps |
| CPU time | 8.44 seconds |
| Started | Jun 28 08:52:38 PM PDT 24 |
| Finished | Jun 28 08:52:48 PM PDT 24 |
| Peak memory | 574228 kb |
| Host | smart-426423a3-b419-4db1-8867-566b86d25097 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3900335398 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 97.xbar_random_zero_del ays.3900335398 |
| Directory | /workspace/97.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/97.xbar_same_source.82525972 |
| Short name | T471 |
| Test name | |
| Test status | |
| Simulation time | 348865237 ps |
| CPU time | 27.94 seconds |
| Started | Jun 28 08:52:42 PM PDT 24 |
| Finished | Jun 28 08:53:13 PM PDT 24 |
| Peak memory | 575224 kb |
| Host | smart-7b4ffc60-76af-4d5e-a89c-672efcdf579b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82525972 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 97.xbar_same_source.82525972 |
| Directory | /workspace/97.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/97.xbar_smoke.1198179124 |
| Short name | T1991 |
| Test name | |
| Test status | |
| Simulation time | 42540404 ps |
| CPU time | 6.24 seconds |
| Started | Jun 28 08:52:15 PM PDT 24 |
| Finished | Jun 28 08:52:25 PM PDT 24 |
| Peak memory | 574136 kb |
| Host | smart-996fc1d4-e46f-4d17-93df-4062f0a8b753 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1198179124 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 97.xbar_smoke.1198179124 |
| Directory | /workspace/97.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/97.xbar_smoke_large_delays.536295398 |
| Short name | T1517 |
| Test name | |
| Test status | |
| Simulation time | 10253981891 ps |
| CPU time | 106.69 seconds |
| Started | Jun 28 08:52:15 PM PDT 24 |
| Finished | Jun 28 08:54:05 PM PDT 24 |
| Peak memory | 574256 kb |
| Host | smart-6b32decd-69c4-4df9-8279-c7862020162f |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=536295398 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 97.xbar_smoke_large_delays.536295398 |
| Directory | /workspace/97.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/97.xbar_smoke_slow_rsp.271261210 |
| Short name | T2490 |
| Test name | |
| Test status | |
| Simulation time | 6559189760 ps |
| CPU time | 115 seconds |
| Started | Jun 28 08:52:16 PM PDT 24 |
| Finished | Jun 28 08:54:14 PM PDT 24 |
| Peak memory | 566024 kb |
| Host | smart-37c699b5-416c-492c-8462-2e1eb1ffcfb5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=271261210 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 97.xbar_smoke_slow_rsp.271261210 |
| Directory | /workspace/97.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/97.xbar_smoke_zero_delays.1552138636 |
| Short name | T2018 |
| Test name | |
| Test status | |
| Simulation time | 47478728 ps |
| CPU time | 6.45 seconds |
| Started | Jun 28 08:52:15 PM PDT 24 |
| Finished | Jun 28 08:52:25 PM PDT 24 |
| Peak memory | 574124 kb |
| Host | smart-c81a24fd-825d-492a-b094-fa19ee040de5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1552138636 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 97.xbar_smoke_zero_delay s.1552138636 |
| Directory | /workspace/97.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/97.xbar_stress_all.1447677160 |
| Short name | T2502 |
| Test name | |
| Test status | |
| Simulation time | 15908997036 ps |
| CPU time | 556.66 seconds |
| Started | Jun 28 08:52:40 PM PDT 24 |
| Finished | Jun 28 09:01:59 PM PDT 24 |
| Peak memory | 575444 kb |
| Host | smart-c7fc1193-5732-481c-9998-295b045a7618 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1447677160 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 97.xbar_stress_all.1447677160 |
| Directory | /workspace/97.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/97.xbar_stress_all_with_error.2662392651 |
| Short name | T2146 |
| Test name | |
| Test status | |
| Simulation time | 734654332 ps |
| CPU time | 56.76 seconds |
| Started | Jun 28 08:52:39 PM PDT 24 |
| Finished | Jun 28 08:53:39 PM PDT 24 |
| Peak memory | 574292 kb |
| Host | smart-5a561fe4-09ea-4c74-8ece-5407b4564aa3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2662392651 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 97.xbar_stress_all_with_error.2662392651 |
| Directory | /workspace/97.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/97.xbar_stress_all_with_rand_reset.1583184882 |
| Short name | T838 |
| Test name | |
| Test status | |
| Simulation time | 401056916 ps |
| CPU time | 257.85 seconds |
| Started | Jun 28 08:52:39 PM PDT 24 |
| Finished | Jun 28 08:56:59 PM PDT 24 |
| Peak memory | 575392 kb |
| Host | smart-8c9b8d3f-fdf1-4fb5-9c7f-615d758f8118 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1583184882 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 97.xbar_stress_all _with_rand_reset.1583184882 |
| Directory | /workspace/97.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/97.xbar_stress_all_with_reset_error.73375468 |
| Short name | T1772 |
| Test name | |
| Test status | |
| Simulation time | 10784754669 ps |
| CPU time | 499.51 seconds |
| Started | Jun 28 08:52:41 PM PDT 24 |
| Finished | Jun 28 09:01:04 PM PDT 24 |
| Peak memory | 575424 kb |
| Host | smart-1346f25c-205d-4cb4-a7b1-e9171a853bb8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73375468 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_res et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 97.xbar_stress_all_ with_reset_error.73375468 |
| Directory | /workspace/97.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/97.xbar_unmapped_addr.3095987973 |
| Short name | T1674 |
| Test name | |
| Test status | |
| Simulation time | 321554133 ps |
| CPU time | 36.63 seconds |
| Started | Jun 28 08:52:41 PM PDT 24 |
| Finished | Jun 28 08:53:21 PM PDT 24 |
| Peak memory | 575280 kb |
| Host | smart-b743a87f-db4c-4808-acf2-2a11bea4f3d6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3095987973 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 97.xbar_unmapped_addr.3095987973 |
| Directory | /workspace/97.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/98.xbar_access_same_device.4036518218 |
| Short name | T676 |
| Test name | |
| Test status | |
| Simulation time | 341149931 ps |
| CPU time | 28.53 seconds |
| Started | Jun 28 08:52:41 PM PDT 24 |
| Finished | Jun 28 08:53:13 PM PDT 24 |
| Peak memory | 575252 kb |
| Host | smart-164c3cb2-933d-4559-85f0-e899856030b4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4036518218 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 98.xbar_access_same_device .4036518218 |
| Directory | /workspace/98.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/98.xbar_access_same_device_slow_rsp.532270558 |
| Short name | T2297 |
| Test name | |
| Test status | |
| Simulation time | 32071716552 ps |
| CPU time | 549.6 seconds |
| Started | Jun 28 08:52:39 PM PDT 24 |
| Finished | Jun 28 09:01:51 PM PDT 24 |
| Peak memory | 575236 kb |
| Host | smart-573b71a1-1d42-40d6-92b7-ba5ce319b9ed |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=532270558 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 98.xbar_access_same_d evice_slow_rsp.532270558 |
| Directory | /workspace/98.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/98.xbar_error_and_unmapped_addr.4232383038 |
| Short name | T1316 |
| Test name | |
| Test status | |
| Simulation time | 781464055 ps |
| CPU time | 27.58 seconds |
| Started | Jun 28 08:52:43 PM PDT 24 |
| Finished | Jun 28 08:53:14 PM PDT 24 |
| Peak memory | 573852 kb |
| Host | smart-24d2473c-8ae9-4b3e-9898-4fec663d5354 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4232383038 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 98.xbar_error_and_unmapped_add r.4232383038 |
| Directory | /workspace/98.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/98.xbar_error_random.2802470540 |
| Short name | T1944 |
| Test name | |
| Test status | |
| Simulation time | 267223534 ps |
| CPU time | 12.15 seconds |
| Started | Jun 28 08:52:41 PM PDT 24 |
| Finished | Jun 28 08:52:56 PM PDT 24 |
| Peak memory | 574436 kb |
| Host | smart-8bce1925-03a4-4c5e-9ee8-7632ca546b1f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2802470540 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 98.xbar_error_random.2802470540 |
| Directory | /workspace/98.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/98.xbar_random.1353620255 |
| Short name | T2398 |
| Test name | |
| Test status | |
| Simulation time | 492591130 ps |
| CPU time | 41.79 seconds |
| Started | Jun 28 08:52:42 PM PDT 24 |
| Finished | Jun 28 08:53:26 PM PDT 24 |
| Peak memory | 575224 kb |
| Host | smart-fa9694ce-e66a-465f-bc1d-68d111ac56d2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1353620255 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 98.xbar_random.1353620255 |
| Directory | /workspace/98.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/98.xbar_random_large_delays.717118836 |
| Short name | T2216 |
| Test name | |
| Test status | |
| Simulation time | 12637362349 ps |
| CPU time | 129.98 seconds |
| Started | Jun 28 08:52:38 PM PDT 24 |
| Finished | Jun 28 08:54:50 PM PDT 24 |
| Peak memory | 575316 kb |
| Host | smart-d8f40a6e-fe01-4f49-9a94-0ddc2ea83dcc |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=717118836 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 98.xbar_random_large_delays.717118836 |
| Directory | /workspace/98.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/98.xbar_random_slow_rsp.4097377230 |
| Short name | T2333 |
| Test name | |
| Test status | |
| Simulation time | 49286180365 ps |
| CPU time | 781.45 seconds |
| Started | Jun 28 08:52:42 PM PDT 24 |
| Finished | Jun 28 09:05:47 PM PDT 24 |
| Peak memory | 574240 kb |
| Host | smart-d67bd870-740f-4cb7-a338-844f05a436f5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4097377230 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 98.xbar_random_slow_rsp.4097377230 |
| Directory | /workspace/98.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/98.xbar_random_zero_delays.1576867429 |
| Short name | T2114 |
| Test name | |
| Test status | |
| Simulation time | 163897840 ps |
| CPU time | 18.13 seconds |
| Started | Jun 28 08:52:39 PM PDT 24 |
| Finished | Jun 28 08:52:59 PM PDT 24 |
| Peak memory | 575228 kb |
| Host | smart-546ed1cd-9fb4-4c75-89fc-f4adb3bf1d18 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1576867429 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 98.xbar_random_zero_del ays.1576867429 |
| Directory | /workspace/98.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/98.xbar_same_source.1932530924 |
| Short name | T2294 |
| Test name | |
| Test status | |
| Simulation time | 253838722 ps |
| CPU time | 20.01 seconds |
| Started | Jun 28 08:52:39 PM PDT 24 |
| Finished | Jun 28 08:53:01 PM PDT 24 |
| Peak memory | 575228 kb |
| Host | smart-c1554e09-265a-4140-bf42-a2d01c23cacb |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1932530924 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 98.xbar_same_source.1932530924 |
| Directory | /workspace/98.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/98.xbar_smoke.1971301889 |
| Short name | T2432 |
| Test name | |
| Test status | |
| Simulation time | 234849904 ps |
| CPU time | 10.3 seconds |
| Started | Jun 28 08:52:38 PM PDT 24 |
| Finished | Jun 28 08:52:50 PM PDT 24 |
| Peak memory | 565940 kb |
| Host | smart-d0eb83e1-de3a-4603-b836-87221cb52386 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1971301889 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 98.xbar_smoke.1971301889 |
| Directory | /workspace/98.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/98.xbar_smoke_large_delays.180366960 |
| Short name | T2504 |
| Test name | |
| Test status | |
| Simulation time | 7995711065 ps |
| CPU time | 89.64 seconds |
| Started | Jun 28 08:52:39 PM PDT 24 |
| Finished | Jun 28 08:54:11 PM PDT 24 |
| Peak memory | 574256 kb |
| Host | smart-f3ac66ac-c329-4c18-b9c1-cd08de06e4b7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=180366960 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 98.xbar_smoke_large_delays.180366960 |
| Directory | /workspace/98.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/98.xbar_smoke_slow_rsp.3507623022 |
| Short name | T2851 |
| Test name | |
| Test status | |
| Simulation time | 6339478851 ps |
| CPU time | 108.48 seconds |
| Started | Jun 28 08:52:41 PM PDT 24 |
| Finished | Jun 28 08:54:33 PM PDT 24 |
| Peak memory | 574240 kb |
| Host | smart-42a6d96e-61ba-4141-9451-adf150795c5c |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3507623022 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 98.xbar_smoke_slow_rsp.3507623022 |
| Directory | /workspace/98.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/98.xbar_smoke_zero_delays.1170382635 |
| Short name | T2806 |
| Test name | |
| Test status | |
| Simulation time | 50821253 ps |
| CPU time | 6.83 seconds |
| Started | Jun 28 08:52:40 PM PDT 24 |
| Finished | Jun 28 08:52:50 PM PDT 24 |
| Peak memory | 574184 kb |
| Host | smart-a630cd97-57b4-49dd-be49-d8f6f4bda764 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1170382635 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 98.xbar_smoke_zero_delay s.1170382635 |
| Directory | /workspace/98.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/98.xbar_stress_all.778373557 |
| Short name | T486 |
| Test name | |
| Test status | |
| Simulation time | 907231697 ps |
| CPU time | 86.66 seconds |
| Started | Jun 28 08:52:42 PM PDT 24 |
| Finished | Jun 28 08:54:12 PM PDT 24 |
| Peak memory | 575380 kb |
| Host | smart-baf87326-b003-4722-9997-8989107eb9d6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=778373557 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 98.xbar_stress_all.778373557 |
| Directory | /workspace/98.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/98.xbar_stress_all_with_error.3368425184 |
| Short name | T2220 |
| Test name | |
| Test status | |
| Simulation time | 1003850301 ps |
| CPU time | 70.71 seconds |
| Started | Jun 28 08:52:42 PM PDT 24 |
| Finished | Jun 28 08:53:56 PM PDT 24 |
| Peak memory | 574524 kb |
| Host | smart-fcebca90-a6f2-428f-9a22-139613bcdda6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3368425184 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 98.xbar_stress_all_with_error.3368425184 |
| Directory | /workspace/98.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/98.xbar_stress_all_with_rand_reset.3178306292 |
| Short name | T1448 |
| Test name | |
| Test status | |
| Simulation time | 296034514 ps |
| CPU time | 74.92 seconds |
| Started | Jun 28 08:52:39 PM PDT 24 |
| Finished | Jun 28 08:53:56 PM PDT 24 |
| Peak memory | 575328 kb |
| Host | smart-6441a26e-d1f5-4ba8-a614-1ccd95f2e59e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3178306292 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 98.xbar_stress_all _with_rand_reset.3178306292 |
| Directory | /workspace/98.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/98.xbar_stress_all_with_reset_error.2859215078 |
| Short name | T585 |
| Test name | |
| Test status | |
| Simulation time | 17199440152 ps |
| CPU time | 578.45 seconds |
| Started | Jun 28 08:52:40 PM PDT 24 |
| Finished | Jun 28 09:02:21 PM PDT 24 |
| Peak memory | 574324 kb |
| Host | smart-0ccafd59-efbb-43b1-bc28-9d363d24b296 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2859215078 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 98.xbar_stress_al l_with_reset_error.2859215078 |
| Directory | /workspace/98.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/98.xbar_unmapped_addr.1420639067 |
| Short name | T1582 |
| Test name | |
| Test status | |
| Simulation time | 209898877 ps |
| CPU time | 27.28 seconds |
| Started | Jun 28 08:52:40 PM PDT 24 |
| Finished | Jun 28 08:53:10 PM PDT 24 |
| Peak memory | 575276 kb |
| Host | smart-6e0c1395-c99f-4e90-9836-ec4a17e4423c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1420639067 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 98.xbar_unmapped_addr.1420639067 |
| Directory | /workspace/98.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/99.xbar_access_same_device.1231566704 |
| Short name | T802 |
| Test name | |
| Test status | |
| Simulation time | 2723471583 ps |
| CPU time | 95.96 seconds |
| Started | Jun 28 08:52:43 PM PDT 24 |
| Finished | Jun 28 08:54:22 PM PDT 24 |
| Peak memory | 575324 kb |
| Host | smart-533df502-e785-497a-bf3a-b27a99615aff |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1231566704 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 99.xbar_access_same_device .1231566704 |
| Directory | /workspace/99.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/99.xbar_access_same_device_slow_rsp.2405839723 |
| Short name | T1667 |
| Test name | |
| Test status | |
| Simulation time | 49816440623 ps |
| CPU time | 886.01 seconds |
| Started | Jun 28 08:52:40 PM PDT 24 |
| Finished | Jun 28 09:07:29 PM PDT 24 |
| Peak memory | 574292 kb |
| Host | smart-e36fbf87-5d6d-4985-880d-e858a5d6d377 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2405839723 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 99.xbar_access_same_ device_slow_rsp.2405839723 |
| Directory | /workspace/99.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/99.xbar_error_and_unmapped_addr.1327434740 |
| Short name | T1317 |
| Test name | |
| Test status | |
| Simulation time | 277692951 ps |
| CPU time | 32 seconds |
| Started | Jun 28 08:53:16 PM PDT 24 |
| Finished | Jun 28 08:53:59 PM PDT 24 |
| Peak memory | 573892 kb |
| Host | smart-7cd602c8-5849-47cf-aa1e-c6304e6f0d31 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1327434740 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 99.xbar_error_and_unmapped_add r.1327434740 |
| Directory | /workspace/99.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/99.xbar_error_random.1164633848 |
| Short name | T1438 |
| Test name | |
| Test status | |
| Simulation time | 179040644 ps |
| CPU time | 10.39 seconds |
| Started | Jun 28 08:53:18 PM PDT 24 |
| Finished | Jun 28 08:53:39 PM PDT 24 |
| Peak memory | 574188 kb |
| Host | smart-f67ae903-92c0-41d1-a565-aec1a12f5866 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1164633848 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 99.xbar_error_random.1164633848 |
| Directory | /workspace/99.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/99.xbar_random.3577871207 |
| Short name | T2305 |
| Test name | |
| Test status | |
| Simulation time | 91582430 ps |
| CPU time | 7.58 seconds |
| Started | Jun 28 08:52:40 PM PDT 24 |
| Finished | Jun 28 08:52:50 PM PDT 24 |
| Peak memory | 574100 kb |
| Host | smart-33c256ec-71b3-47a4-8e36-6f5992d8041f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3577871207 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 99.xbar_random.3577871207 |
| Directory | /workspace/99.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/99.xbar_random_large_delays.532223394 |
| Short name | T2031 |
| Test name | |
| Test status | |
| Simulation time | 85102990473 ps |
| CPU time | 943.19 seconds |
| Started | Jun 28 08:52:41 PM PDT 24 |
| Finished | Jun 28 09:08:28 PM PDT 24 |
| Peak memory | 575336 kb |
| Host | smart-daa66941-32b3-466a-b63c-5b8a132f9fea |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=532223394 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 99.xbar_random_large_delays.532223394 |
| Directory | /workspace/99.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/99.xbar_random_slow_rsp.3574140670 |
| Short name | T2832 |
| Test name | |
| Test status | |
| Simulation time | 18584260315 ps |
| CPU time | 314.3 seconds |
| Started | Jun 28 08:52:42 PM PDT 24 |
| Finished | Jun 28 08:58:00 PM PDT 24 |
| Peak memory | 575312 kb |
| Host | smart-eea1070e-382f-49da-973e-728e114b5be6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3574140670 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 99.xbar_random_slow_rsp.3574140670 |
| Directory | /workspace/99.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/99.xbar_random_zero_delays.3744090256 |
| Short name | T2407 |
| Test name | |
| Test status | |
| Simulation time | 241670290 ps |
| CPU time | 25.52 seconds |
| Started | Jun 28 08:52:41 PM PDT 24 |
| Finished | Jun 28 08:53:09 PM PDT 24 |
| Peak memory | 575236 kb |
| Host | smart-6ffef1fe-cb66-4c16-965a-7a7da720c90f |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3744090256 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 99.xbar_random_zero_del ays.3744090256 |
| Directory | /workspace/99.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/99.xbar_same_source.18762092 |
| Short name | T1995 |
| Test name | |
| Test status | |
| Simulation time | 2355189042 ps |
| CPU time | 84.49 seconds |
| Started | Jun 28 08:52:40 PM PDT 24 |
| Finished | Jun 28 08:54:07 PM PDT 24 |
| Peak memory | 575260 kb |
| Host | smart-c0f6b2e3-7289-42d6-8c30-0b757b9fcaff |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18762092 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 99.xbar_same_source.18762092 |
| Directory | /workspace/99.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/99.xbar_smoke.2944161260 |
| Short name | T1616 |
| Test name | |
| Test status | |
| Simulation time | 39703504 ps |
| CPU time | 6.06 seconds |
| Started | Jun 28 08:52:38 PM PDT 24 |
| Finished | Jun 28 08:52:46 PM PDT 24 |
| Peak memory | 574196 kb |
| Host | smart-b806c647-6330-4c02-b075-cc2c2c4abf7c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2944161260 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 99.xbar_smoke.2944161260 |
| Directory | /workspace/99.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/99.xbar_smoke_large_delays.1759777911 |
| Short name | T673 |
| Test name | |
| Test status | |
| Simulation time | 9303857626 ps |
| CPU time | 99.83 seconds |
| Started | Jun 28 08:52:42 PM PDT 24 |
| Finished | Jun 28 08:54:25 PM PDT 24 |
| Peak memory | 574236 kb |
| Host | smart-f4e65b46-e14b-495b-9077-9b60a6c8df6a |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1759777911 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 99.xbar_smoke_large_delays.1759777911 |
| Directory | /workspace/99.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/99.xbar_smoke_slow_rsp.3146769322 |
| Short name | T2073 |
| Test name | |
| Test status | |
| Simulation time | 4427393026 ps |
| CPU time | 83.34 seconds |
| Started | Jun 28 08:52:42 PM PDT 24 |
| Finished | Jun 28 08:54:09 PM PDT 24 |
| Peak memory | 574264 kb |
| Host | smart-56f6bd8d-cdab-4bf6-84f9-46281ff6579d |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3146769322 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 99.xbar_smoke_slow_rsp.3146769322 |
| Directory | /workspace/99.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/99.xbar_smoke_zero_delays.1101127576 |
| Short name | T2620 |
| Test name | |
| Test status | |
| Simulation time | 50835857 ps |
| CPU time | 6.83 seconds |
| Started | Jun 28 08:52:43 PM PDT 24 |
| Finished | Jun 28 08:52:53 PM PDT 24 |
| Peak memory | 574176 kb |
| Host | smart-889f448e-cd96-41aa-b01a-b3703671f419 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1101127576 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 99.xbar_smoke_zero_delay s.1101127576 |
| Directory | /workspace/99.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/99.xbar_stress_all.28053029 |
| Short name | T2059 |
| Test name | |
| Test status | |
| Simulation time | 1840538266 ps |
| CPU time | 139.37 seconds |
| Started | Jun 28 08:53:14 PM PDT 24 |
| Finished | Jun 28 08:55:45 PM PDT 24 |
| Peak memory | 575344 kb |
| Host | smart-c7a302a4-2d8e-4e5a-bba4-2f96f930c160 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28053029 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 99.xbar_stress_all.28053029 |
| Directory | /workspace/99.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/99.xbar_stress_all_with_error.117021631 |
| Short name | T248 |
| Test name | |
| Test status | |
| Simulation time | 1802629823 ps |
| CPU time | 181.55 seconds |
| Started | Jun 28 08:53:16 PM PDT 24 |
| Finished | Jun 28 08:56:28 PM PDT 24 |
| Peak memory | 574336 kb |
| Host | smart-85e3c63b-75bb-4509-82f1-00a4793a7809 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=117021631 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 99.xbar_stress_all_with_error.117021631 |
| Directory | /workspace/99.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/99.xbar_stress_all_with_rand_reset.1835802095 |
| Short name | T551 |
| Test name | |
| Test status | |
| Simulation time | 2866573279 ps |
| CPU time | 154.25 seconds |
| Started | Jun 28 08:53:14 PM PDT 24 |
| Finished | Jun 28 08:56:00 PM PDT 24 |
| Peak memory | 574372 kb |
| Host | smart-90eb4041-d8a2-42c9-8d7f-b736bd36bfcb |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1835802095 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 99.xbar_stress_all _with_rand_reset.1835802095 |
| Directory | /workspace/99.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/99.xbar_stress_all_with_reset_error.486293980 |
| Short name | T2728 |
| Test name | |
| Test status | |
| Simulation time | 5785483269 ps |
| CPU time | 345.49 seconds |
| Started | Jun 28 08:53:16 PM PDT 24 |
| Finished | Jun 28 08:59:12 PM PDT 24 |
| Peak memory | 574432 kb |
| Host | smart-6b351e8e-78cb-4f2b-8685-a5ad60866772 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=486293980 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 99.xbar_stress_all _with_reset_error.486293980 |
| Directory | /workspace/99.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/99.xbar_unmapped_addr.2329622536 |
| Short name | T2256 |
| Test name | |
| Test status | |
| Simulation time | 1089965599 ps |
| CPU time | 45.76 seconds |
| Started | Jun 28 08:53:17 PM PDT 24 |
| Finished | Jun 28 08:54:13 PM PDT 24 |
| Peak memory | 575276 kb |
| Host | smart-0a28f803-616b-4c28-9a54-e4cfc2c57ee4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2329622536 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 99.xbar_unmapped_addr.2329622536 |
| Directory | /workspace/99.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/default/0.chip_jtag_mem_access.332995562 |
| Short name | T194 |
| Test name | |
| Test status | |
| Simulation time | 13775035272 ps |
| CPU time | 1647.93 seconds |
| Started | Jun 28 07:52:11 PM PDT 24 |
| Finished | Jun 28 08:19:40 PM PDT 24 |
| Peak memory | 607324 kb |
| Host | smart-e0686d40-27eb-4abb-be0a-cc17a661057f |
| User | root |
| Command | /workspace/default/simv +create_jtag_riscv_map=1 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=332995562 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_jtag_m em_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_jtag_mem_access.332995562 |
| Directory | /workspace/0.chip_jtag_mem_access/latest |
| Test location | /workspace/coverage/default/0.chip_rv_dm_ndm_reset_req.524157693 |
| Short name | T410 |
| Test name | |
| Test status | |
| Simulation time | 4777200472 ps |
| CPU time | 446.34 seconds |
| Started | Jun 28 08:01:48 PM PDT 24 |
| Finished | Jun 28 08:09:16 PM PDT 24 |
| Peak memory | 617776 kb |
| Host | smart-d1bdd9e7-5d85-422b-86db-f538a89a3a5e |
| User | root |
| Command | /workspace/default/simv +en_scb_tl_err_chk=0 +use_jtag_dmi=1 +sw_build_device=sim_dv +sw_images=rv_dm_ndm_reset_req_rma:1:new_rules,test_rom:0 +cdc_in strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=5 24157693 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_rv_dm_ndm_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_rv_dm_ndm_reset_req.524157693 |
| Directory | /workspace/0.chip_rv_dm_ndm_reset_req/latest |
| Test location | /workspace/coverage/default/0.chip_sival_flash_info_access.2744544630 |
| Short name | T1073 |
| Test name | |
| Test status | |
| Simulation time | 3944000278 ps |
| CPU time | 358.09 seconds |
| Started | Jun 28 07:59:54 PM PDT 24 |
| Finished | Jun 28 08:05:54 PM PDT 24 |
| Peak memory | 607108 kb |
| Host | smart-1e26e3ca-1101-4344-b52d-7c9e0f404099 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStTestUnlocked0 +sw_build_device=sim_dv +sw_images=flash_ctrl_info_access_lc:1:new_rules,test_rom:0 +c dc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_s eed=2744544630 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sival_flash_info_access.2744544630 |
| Directory | /workspace/0.chip_sival_flash_info_access/latest |
| Test location | /workspace/coverage/default/0.chip_sw_aes_enc.1522566787 |
| Short name | T1011 |
| Test name | |
| Test status | |
| Simulation time | 2792556768 ps |
| CPU time | 228.79 seconds |
| Started | Jun 28 08:06:56 PM PDT 24 |
| Finished | Jun 28 08:10:46 PM PDT 24 |
| Peak memory | 609152 kb |
| Host | smart-e3dc5551-c4ed-4549-81bd-c1dcf7a534f8 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=22_000_000 +sw_build_device=sim_dv +sw_images=aes_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1522566787 -asser t nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag e/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_aes_enc.1522566787 |
| Directory | /workspace/0.chip_sw_aes_enc/latest |
| Test location | /workspace/coverage/default/0.chip_sw_aes_enc_jitter_en.309904953 |
| Short name | T1184 |
| Test name | |
| Test status | |
| Simulation time | 3411634049 ps |
| CPU time | 253.64 seconds |
| Started | Jun 28 08:01:42 PM PDT 24 |
| Finished | Jun 28 08:05:57 PM PDT 24 |
| Peak memory | 609192 kb |
| Host | smart-94266543-c683-41f9-9902-24e7d81db8db |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=26_000_000 +en_jitter=1 +sw_build_device=sim_dv +sw_images=aes_smoketest:1:new_rules,test_rom:0 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3099 04953 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_aes_enc_jitter_en.309904953 |
| Directory | /workspace/0.chip_sw_aes_enc_jitter_en/latest |
| Test location | /workspace/coverage/default/0.chip_sw_aes_enc_jitter_en_reduced_freq.957838565 |
| Short name | T980 |
| Test name | |
| Test status | |
| Simulation time | 3256097288 ps |
| CPU time | 247.39 seconds |
| Started | Jun 28 08:09:15 PM PDT 24 |
| Finished | Jun 28 08:13:24 PM PDT 24 |
| Peak memory | 609180 kb |
| Host | smart-1d7581fc-8f7b-4176-a165-8cb79a67478f |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=26_000_000 +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=aes_smoketest:1:new_rules, test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=957838565 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_aes_enc_jitter_en_reduced_freq.957838565 |
| Directory | /workspace/0.chip_sw_aes_enc_jitter_en_reduced_freq/latest |
| Test location | /workspace/coverage/default/0.chip_sw_aes_entropy.973671789 |
| Short name | T1145 |
| Test name | |
| Test status | |
| Simulation time | 2358427070 ps |
| CPU time | 185.58 seconds |
| Started | Jun 28 08:04:09 PM PDT 24 |
| Finished | Jun 28 08:07:16 PM PDT 24 |
| Peak memory | 609168 kb |
| Host | smart-db44691f-203b-4d56-b253-3cb60d846e5e |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=15_000_000 +sw_build_device=sim_dv +sw_images=aes_entropy_test:1:new_rules,test_rom:0 +cdc_instrumentation _enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=973671789 -ass ert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_aes_entropy.973671789 |
| Directory | /workspace/0.chip_sw_aes_entropy/latest |
| Test location | /workspace/coverage/default/0.chip_sw_aes_idle.405675813 |
| Short name | T901 |
| Test name | |
| Test status | |
| Simulation time | 3397711068 ps |
| CPU time | 241.83 seconds |
| Started | Jun 28 08:05:11 PM PDT 24 |
| Finished | Jun 28 08:09:14 PM PDT 24 |
| Peak memory | 607116 kb |
| Host | smart-56484360-b7c7-45d0-b83f-d49a1f419ac7 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=25_000_000 +sw_build_device=sim_dv +sw_images=aes_idle_test:1:new_rules,test_rom:0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=405675813 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage /default.vdb -cm_log /dev/null -cm_name 0.chip_sw_aes_idle.405675813 |
| Directory | /workspace/0.chip_sw_aes_idle/latest |
| Test location | /workspace/coverage/default/0.chip_sw_aes_masking_off.2528045621 |
| Short name | T722 |
| Test name | |
| Test status | |
| Simulation time | 3008541131 ps |
| CPU time | 407.31 seconds |
| Started | Jun 28 08:05:39 PM PDT 24 |
| Finished | Jun 28 08:12:28 PM PDT 24 |
| Peak memory | 609232 kb |
| Host | smart-da87d619-a11e-4874-8c4e-fb895984eb9b |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=aes_masking_off_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2528045621 -assert nopostproc +UVM_TESTNA ME=chip_base_test +UVM_TEST_SEQ=chip_sw_aes_masking_off_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_aes_masking_off.2528045621 |
| Directory | /workspace/0.chip_sw_aes_masking_off/latest |
| Test location | /workspace/coverage/default/0.chip_sw_aes_smoketest.3396265106 |
| Short name | T1173 |
| Test name | |
| Test status | |
| Simulation time | 3429415172 ps |
| CPU time | 405.81 seconds |
| Started | Jun 28 08:01:40 PM PDT 24 |
| Finished | Jun 28 08:08:27 PM PDT 24 |
| Peak memory | 606304 kb |
| Host | smart-033aec6a-3809-4dce-b2c6-948e5c431c73 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=aes_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3396265106 -assert nopostproc +UVM_TESTNAME=chip _base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_aes_smoketest.3396265106 |
| Directory | /workspace/0.chip_sw_aes_smoketest/latest |
| Test location | /workspace/coverage/default/0.chip_sw_alert_handler_entropy.1732494869 |
| Short name | T82 |
| Test name | |
| Test status | |
| Simulation time | 3061061030 ps |
| CPU time | 323.99 seconds |
| Started | Jun 28 08:07:14 PM PDT 24 |
| Finished | Jun 28 08:12:39 PM PDT 24 |
| Peak memory | 607776 kb |
| Host | smart-b702b025-a99b-4e66-ab3c-c7a8bc37a763 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=alert_handler_entropy_test:1:new_rules,test_ro m:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=1732494869 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_alert_handler_entropy.1732494869 |
| Directory | /workspace/0.chip_sw_alert_handler_entropy/latest |
| Test location | /workspace/coverage/default/0.chip_sw_alert_handler_escalation.1112277523 |
| Short name | T1039 |
| Test name | |
| Test status | |
| Simulation time | 4852470440 ps |
| CPU time | 500.88 seconds |
| Started | Jun 28 08:06:56 PM PDT 24 |
| Finished | Jun 28 08:15:19 PM PDT 24 |
| Peak memory | 613716 kb |
| Host | smart-d8d22f75-e837-4dda-854d-f468d0ced29f |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=alert_handler_escalation_test:1:new_rules,test _rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb _random_seed=1112277523 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_alert_handler_escalation_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_alert_handler_escalation.1112277523 |
| Directory | /workspace/0.chip_sw_alert_handler_escalation/latest |
| Test location | /workspace/coverage/default/0.chip_sw_alert_handler_lpg_clkoff.3287028739 |
| Short name | T1098 |
| Test name | |
| Test status | |
| Simulation time | 8182896776 ps |
| CPU time | 1896.45 seconds |
| Started | Jun 28 08:01:40 PM PDT 24 |
| Finished | Jun 28 08:33:18 PM PDT 24 |
| Peak memory | 608152 kb |
| Host | smart-aedb2d6d-111b-4343-ac51-d95a0c102090 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +sw_build_device=sim_dv +sw_images=alert_handler_lpg_clkoff_test:1:new_rules,test_r om:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r andom_seed=3287028739 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_alert_handler_lpg_clkoff_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_alert_handler_lpg_clkoff.3287028739 |
| Directory | /workspace/0.chip_sw_alert_handler_lpg_clkoff/latest |
| Test location | /workspace/coverage/default/0.chip_sw_alert_handler_lpg_reset_toggle.2999243876 |
| Short name | T100 |
| Test name | |
| Test status | |
| Simulation time | 6555196296 ps |
| CPU time | 1554.23 seconds |
| Started | Jun 28 08:08:14 PM PDT 24 |
| Finished | Jun 28 08:34:09 PM PDT 24 |
| Peak memory | 608224 kb |
| Host | smart-4990187a-3fd0-48ae-aada-fe011f7dda97 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +sw_build_device=sim_dv +sw_images=alert_handler_lpg_reset_toggle_test:1:new_rules, test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2999243876 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_alert_handler_shorten_ping_wait_cycle_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_alert_handler_lpg_reset_togg le.2999243876 |
| Directory | /workspace/0.chip_sw_alert_handler_lpg_reset_toggle/latest |
| Test location | /workspace/coverage/default/0.chip_sw_alert_handler_lpg_sleep_mode_pings.2334562676 |
| Short name | T256 |
| Test name | |
| Test status | |
| Simulation time | 9795649832 ps |
| CPU time | 1286.5 seconds |
| Started | Jun 28 08:03:40 PM PDT 24 |
| Finished | Jun 28 08:25:09 PM PDT 24 |
| Peak memory | 608828 kb |
| Host | smart-647fc727-da63-4b42-a17b-6bb74ce1cece |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=alert_handler _lpg_sleep_mode_pings_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2334562676 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_alert_han dler_shorten_ping_wait_cycle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_alert_handler_lpg_sleep_mode_pings.2334562676 |
| Directory | /workspace/0.chip_sw_alert_handler_lpg_sleep_mode_pings/latest |
| Test location | /workspace/coverage/default/0.chip_sw_alert_handler_ping_ok.1636840415 |
| Short name | T1064 |
| Test name | |
| Test status | |
| Simulation time | 7356771416 ps |
| CPU time | 1728.35 seconds |
| Started | Jun 28 08:07:34 PM PDT 24 |
| Finished | Jun 28 08:36:24 PM PDT 24 |
| Peak memory | 608232 kb |
| Host | smart-631325eb-bf20-4096-9bbd-1dbc8016a73b |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=24000000 +sw_build_device=sim_dv +sw_images=alert_handler_ping_ok_test:1:new_rules,test_rom:0 +c dc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_s eed=1636840415 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_alert_handler_ping_ok.1636840415 |
| Directory | /workspace/0.chip_sw_alert_handler_ping_ok/latest |
| Test location | /workspace/coverage/default/0.chip_sw_alert_handler_ping_timeout.1839326564 |
| Short name | T154 |
| Test name | |
| Test status | |
| Simulation time | 4625839082 ps |
| CPU time | 452.94 seconds |
| Started | Jun 28 08:05:44 PM PDT 24 |
| Finished | Jun 28 08:13:18 PM PDT 24 |
| Peak memory | 608220 kb |
| Host | smart-ff48da48-5c9e-43f8-94ea-932125434fb1 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=24000000 +sw_build_device=sim_dv +sw_images=alert_handler_ping_timeout_test:1:new_rules,test_rom :0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=1839326564 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_alert_handler_ping_timeout.1839326564 |
| Directory | /workspace/0.chip_sw_alert_handler_ping_timeout/latest |
| Test location | /workspace/coverage/default/0.chip_sw_alert_handler_reverse_ping_in_deep_sleep.1780320149 |
| Short name | T1301 |
| Test name | |
| Test status | |
| Simulation time | 255484399790 ps |
| CPU time | 13014.5 seconds |
| Started | Jun 28 08:06:40 PM PDT 24 |
| Finished | Jun 28 11:43:38 PM PDT 24 |
| Peak memory | 608448 kb |
| Host | smart-d80cacf6-79a7-4759-986d-4c09080214ed |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=300_000_000 +sw_build_device=sim_dv +sw_images=alert_handler_reverse_ping_in_deep_sleep_test:1:n ew_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1780320149 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_alert_handler_reverse_ping_in_deep_sleep.1780320149 |
| Directory | /workspace/0.chip_sw_alert_handler_reverse_ping_in_deep_sleep/latest |
| Test location | /workspace/coverage/default/0.chip_sw_aon_timer_irq.1309822599 |
| Short name | T1293 |
| Test name | |
| Test status | |
| Simulation time | 3845547120 ps |
| CPU time | 415.9 seconds |
| Started | Jun 28 08:05:47 PM PDT 24 |
| Finished | Jun 28 08:12:45 PM PDT 24 |
| Peak memory | 607636 kb |
| Host | smart-050acb10-b74c-4063-90e3-69c0a9f383a5 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=aon_timer_irq_test:1:new_rules,test_rom:0 +cdc_instrumentati on_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1309822599 - assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co verage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_aon_timer_irq.1309822599 |
| Directory | /workspace/0.chip_sw_aon_timer_irq/latest |
| Test location | /workspace/coverage/default/0.chip_sw_aon_timer_sleep_wdog_sleep_pause.3402227692 |
| Short name | T1273 |
| Test name | |
| Test status | |
| Simulation time | 6881187256 ps |
| CPU time | 405.58 seconds |
| Started | Jun 28 08:07:02 PM PDT 24 |
| Finished | Jun 28 08:13:49 PM PDT 24 |
| Peak memory | 609172 kb |
| Host | smart-a324865a-04dd-4271-944d-e4818e9a1372 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=aon_timer_sleep_wdog_sleep_pause_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=3402227692 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_aon_timer_sleep_wdog_sleep_pause.3402227692 |
| Directory | /workspace/0.chip_sw_aon_timer_sleep_wdog_sleep_pause/latest |
| Test location | /workspace/coverage/default/0.chip_sw_aon_timer_smoketest.511509750 |
| Short name | T931 |
| Test name | |
| Test status | |
| Simulation time | 2956690096 ps |
| CPU time | 326.18 seconds |
| Started | Jun 28 08:02:19 PM PDT 24 |
| Finished | Jun 28 08:07:46 PM PDT 24 |
| Peak memory | 607256 kb |
| Host | smart-f4792ea9-8797-41fd-ab09-6ef022a526dd |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=aon_timer_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=511509750 -assert nopostproc +UVM_TESTNAME =chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 0.chip_sw_aon_timer_smoketest.511509750 |
| Directory | /workspace/0.chip_sw_aon_timer_smoketest/latest |
| Test location | /workspace/coverage/default/0.chip_sw_aon_timer_wdog_bite_reset.1614753585 |
| Short name | T932 |
| Test name | |
| Test status | |
| Simulation time | 8142452784 ps |
| CPU time | 784.64 seconds |
| Started | Jun 28 08:06:53 PM PDT 24 |
| Finished | Jun 28 08:19:58 PM PDT 24 |
| Peak memory | 609168 kb |
| Host | smart-b7bb8055-e9b8-4271-8af3-b532cea71ad6 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=aon_timer_wdog_bite_reset_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 1614753585 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_aon_timer_wdog_bite_reset.1614753585 |
| Directory | /workspace/0.chip_sw_aon_timer_wdog_bite_reset/latest |
| Test location | /workspace/coverage/default/0.chip_sw_aon_timer_wdog_lc_escalate.1879458961 |
| Short name | T507 |
| Test name | |
| Test status | |
| Simulation time | 5391332956 ps |
| CPU time | 494.81 seconds |
| Started | Jun 28 08:06:27 PM PDT 24 |
| Finished | Jun 28 08:14:43 PM PDT 24 |
| Peak memory | 607300 kb |
| Host | smart-d3bfecd4-8e80-49c7-899b-5dbf3cf5d78c |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=aon_timer_wdog_lc_escalate_test:1:new_rules,test_rom:0 +cdc_ instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed =1879458961 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_aon_timer_wdog_lc_escalate.1879458961 |
| Directory | /workspace/0.chip_sw_aon_timer_wdog_lc_escalate/latest |
| Test location | /workspace/coverage/default/0.chip_sw_ast_clk_outputs.3287297577 |
| Short name | T717 |
| Test name | |
| Test status | |
| Simulation time | 8154600064 ps |
| CPU time | 960.91 seconds |
| Started | Jun 28 08:01:45 PM PDT 24 |
| Finished | Jun 28 08:17:47 PM PDT 24 |
| Peak memory | 615048 kb |
| Host | smart-1e5b7316-1ea3-4290-adc3-d3ab57004be8 |
| User | root |
| Command | /workspace/default/simv +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=ast_clk_outs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled= 1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3287297577 -assert nopo stproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_ast_clk_outputs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co verage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_ast_clk_outputs.3287297577 |
| Directory | /workspace/0.chip_sw_ast_clk_outputs/latest |
| Test location | /workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_lc.3422711278 |
| Short name | T1230 |
| Test name | |
| Test status | |
| Simulation time | 12340363664 ps |
| CPU time | 932.07 seconds |
| Started | Jun 28 08:01:32 PM PDT 24 |
| Finished | Jun 28 08:17:06 PM PDT 24 |
| Peak memory | 619156 kb |
| Host | smart-065d8fb0-0ee9-48a9-b717-93e22184586f |
| User | root |
| Command | /workspace/default/simv +chip_clock_source=ChipClockSourceExternal48Mhz +sw_build_device=sim_dv +sw_images=clkmgr_external_clk_src_for_lc_test:1:new_r ules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim .tcl +ntb_random_seed=3422711278 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_transition_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_clkmgr_external_clk_src_for_lc.3422711278 |
| Directory | /workspace/0.chip_sw_clkmgr_external_clk_src_for_lc/latest |
| Test location | /workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_fast_dev.3374603571 |
| Short name | T1227 |
| Test name | |
| Test status | |
| Simulation time | 3689608176 ps |
| CPU time | 726.17 seconds |
| Started | Jun 28 08:07:41 PM PDT 24 |
| Finished | Jun 28 08:19:49 PM PDT 24 |
| Peak memory | 610844 kb |
| Host | smart-34ab8aff-4719-4d73-94a3-f5f51469d024 |
| User | root |
| Command | /workspace/default/simv +chip_clock_source=ChipClockSourceExternal96Mhz +calibrate_usb_clk=1 +src_dec_state=DecLcStDev +sw_build_device=sim_dv +sw_ima ges=clkmgr_external_clk_src_for_sw_fast_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3374603571 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ =chip_sw_lc_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_c lkmgr_external_clk_src_for_sw_fast_dev.3374603571 |
| Directory | /workspace/0.chip_sw_clkmgr_external_clk_src_for_sw_fast_dev/latest |
| Test location | /workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_fast_rma.2932832925 |
| Short name | T1123 |
| Test name | |
| Test status | |
| Simulation time | 4628126510 ps |
| CPU time | 651.54 seconds |
| Started | Jun 28 08:00:23 PM PDT 24 |
| Finished | Jun 28 08:11:16 PM PDT 24 |
| Peak memory | 610756 kb |
| Host | smart-8f7492c8-e160-42d4-aaab-3407251e05f2 |
| User | root |
| Command | /workspace/default/simv +chip_clock_source=ChipClockSourceExternal96Mhz +calibrate_usb_clk=1 +src_dec_state=DecLcStRma +sw_build_device=sim_dv +sw_ima ges=clkmgr_external_clk_src_for_sw_fast_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2932832925 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ =chip_sw_lc_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_c lkmgr_external_clk_src_for_sw_fast_rma.2932832925 |
| Directory | /workspace/0.chip_sw_clkmgr_external_clk_src_for_sw_fast_rma/latest |
| Test location | /workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0.624994433 |
| Short name | T417 |
| Test name | |
| Test status | |
| Simulation time | 4202102360 ps |
| CPU time | 649.94 seconds |
| Started | Jun 28 08:00:53 PM PDT 24 |
| Finished | Jun 28 08:11:44 PM PDT 24 |
| Peak memory | 608608 kb |
| Host | smart-110b2469-5fca-4b0d-ad19-b114dc83d179 |
| User | root |
| Command | /workspace/default/simv +chip_clock_source=ChipClockSourceExternal96Mhz +calibrate_usb_clk=1 +src_dec_state=DecLcStTestUnlocked0 +sw_build_device=sim_ dv +sw_images=clkmgr_external_clk_src_for_sw_fast_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=624994433 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM _TEST_SEQ=chip_sw_lc_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0. chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0.624994433 |
| Directory | /workspace/0.chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0/latest |
| Test location | /workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_slow_dev.195110657 |
| Short name | T1300 |
| Test name | |
| Test status | |
| Simulation time | 4644159070 ps |
| CPU time | 618.68 seconds |
| Started | Jun 28 08:01:19 PM PDT 24 |
| Finished | Jun 28 08:11:40 PM PDT 24 |
| Peak memory | 610868 kb |
| Host | smart-5a4f9ae3-27c7-4e2c-94b0-0028a497c828 |
| User | root |
| Command | /workspace/default/simv +chip_clock_source=ChipClockSourceExternal48Mhz +calibrate_usb_clk=1 +src_dec_state=DecLcStDev +sw_build_device=sim_dv +sw_ima ges=clkmgr_external_clk_src_for_sw_slow_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=195110657 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ= chip_sw_lc_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_cl kmgr_external_clk_src_for_sw_slow_dev.195110657 |
| Directory | /workspace/0.chip_sw_clkmgr_external_clk_src_for_sw_slow_dev/latest |
| Test location | /workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_slow_rma.363009092 |
| Short name | T1148 |
| Test name | |
| Test status | |
| Simulation time | 4810867634 ps |
| CPU time | 515.87 seconds |
| Started | Jun 28 08:02:13 PM PDT 24 |
| Finished | Jun 28 08:10:50 PM PDT 24 |
| Peak memory | 610880 kb |
| Host | smart-be4bfed0-fd76-4ab1-8627-8ebfee69d9b8 |
| User | root |
| Command | /workspace/default/simv +chip_clock_source=ChipClockSourceExternal48Mhz +calibrate_usb_clk=1 +src_dec_state=DecLcStRma +sw_build_device=sim_dv +sw_ima ges=clkmgr_external_clk_src_for_sw_slow_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=363009092 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ= chip_sw_lc_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_cl kmgr_external_clk_src_for_sw_slow_rma.363009092 |
| Directory | /workspace/0.chip_sw_clkmgr_external_clk_src_for_sw_slow_rma/latest |
| Test location | /workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0.3697656341 |
| Short name | T1207 |
| Test name | |
| Test status | |
| Simulation time | 4801450314 ps |
| CPU time | 701.99 seconds |
| Started | Jun 28 08:04:32 PM PDT 24 |
| Finished | Jun 28 08:16:16 PM PDT 24 |
| Peak memory | 610848 kb |
| Host | smart-352e0bd9-a77b-41cf-8ec5-b8606a4e4668 |
| User | root |
| Command | /workspace/default/simv +chip_clock_source=ChipClockSourceExternal48Mhz +calibrate_usb_clk=1 +src_dec_state=DecLcStTestUnlocked0 +sw_build_device=sim_ dv +sw_images=clkmgr_external_clk_src_for_sw_slow_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3697656341 -assert nopostproc +UVM_TESTNAME=chip_base_test +UV M_TEST_SEQ=chip_sw_lc_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0 .chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0.3697656341 |
| Directory | /workspace/0.chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0/latest |
| Test location | /workspace/coverage/default/0.chip_sw_clkmgr_jitter.2740083005 |
| Short name | T992 |
| Test name | |
| Test status | |
| Simulation time | 2867192671 ps |
| CPU time | 260.99 seconds |
| Started | Jun 28 08:03:21 PM PDT 24 |
| Finished | Jun 28 08:07:43 PM PDT 24 |
| Peak memory | 607052 kb |
| Host | smart-2641a639-9517-4bdb-9e4a-76494249fd74 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_jitter_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2740083005 -assert nopostproc +UVM_TESTNAME =chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 0.chip_sw_clkmgr_jitter.2740083005 |
| Directory | /workspace/0.chip_sw_clkmgr_jitter/latest |
| Test location | /workspace/coverage/default/0.chip_sw_clkmgr_jitter_frequency.4016359999 |
| Short name | T855 |
| Test name | |
| Test status | |
| Simulation time | 3250967436 ps |
| CPU time | 361.3 seconds |
| Started | Jun 28 08:01:54 PM PDT 24 |
| Finished | Jun 28 08:07:56 PM PDT 24 |
| Peak memory | 607132 kb |
| Host | smart-1a43cd29-a339-4724-8ae4-f4d9e014568d |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_jitter_frequency_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4016359999 -assert nopostproc +UV M_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -c m_log /dev/null -cm_name 0.chip_sw_clkmgr_jitter_frequency.4016359999 |
| Directory | /workspace/0.chip_sw_clkmgr_jitter_frequency/latest |
| Test location | /workspace/coverage/default/0.chip_sw_clkmgr_jitter_reduced_freq.4139550535 |
| Short name | T1175 |
| Test name | |
| Test status | |
| Simulation time | 3140141683 ps |
| CPU time | 166.9 seconds |
| Started | Jun 28 08:02:23 PM PDT 24 |
| Finished | Jun 28 08:05:12 PM PDT 24 |
| Peak memory | 609176 kb |
| Host | smart-c1ab7306-ad57-4fc6-ba38-690080c29a51 |
| User | root |
| Command | /workspace/default/simv +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=clkmgr_jitter_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4139550535 -assert nop ostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def ault.vdb -cm_log /dev/null -cm_name 0.chip_sw_clkmgr_jitter_reduced_freq.4139550535 |
| Directory | /workspace/0.chip_sw_clkmgr_jitter_reduced_freq/latest |
| Test location | /workspace/coverage/default/0.chip_sw_clkmgr_off_aes_trans.2637087793 |
| Short name | T958 |
| Test name | |
| Test status | |
| Simulation time | 5615583066 ps |
| CPU time | 552.22 seconds |
| Started | Jun 28 08:04:40 PM PDT 24 |
| Finished | Jun 28 08:13:53 PM PDT 24 |
| Peak memory | 609192 kb |
| Host | smart-c5c2230b-6a0d-401c-be6b-3392aef33b4f |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_off_aes_trans_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2637087793 -assert nopostproc +UVM_T ESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l og /dev/null -cm_name 0.chip_sw_clkmgr_off_aes_trans.2637087793 |
| Directory | /workspace/0.chip_sw_clkmgr_off_aes_trans/latest |
| Test location | /workspace/coverage/default/0.chip_sw_clkmgr_off_hmac_trans.681065740 |
| Short name | T1161 |
| Test name | |
| Test status | |
| Simulation time | 5438225050 ps |
| CPU time | 493.56 seconds |
| Started | Jun 28 08:00:54 PM PDT 24 |
| Finished | Jun 28 08:09:08 PM PDT 24 |
| Peak memory | 609188 kb |
| Host | smart-876b1dce-fa04-4583-be0e-a610ee6ec412 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_off_hmac_trans_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=681065740 -assert nopostproc +UVM_T ESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l og /dev/null -cm_name 0.chip_sw_clkmgr_off_hmac_trans.681065740 |
| Directory | /workspace/0.chip_sw_clkmgr_off_hmac_trans/latest |
| Test location | /workspace/coverage/default/0.chip_sw_clkmgr_off_kmac_trans.2929547393 |
| Short name | T946 |
| Test name | |
| Test status | |
| Simulation time | 5886197344 ps |
| CPU time | 609.13 seconds |
| Started | Jun 28 08:01:24 PM PDT 24 |
| Finished | Jun 28 08:11:34 PM PDT 24 |
| Peak memory | 609192 kb |
| Host | smart-af026c22-89be-4614-aab9-bf81dad1c2fa |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_off_kmac_trans_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2929547393 -assert nopostproc +UVM_ TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_ log /dev/null -cm_name 0.chip_sw_clkmgr_off_kmac_trans.2929547393 |
| Directory | /workspace/0.chip_sw_clkmgr_off_kmac_trans/latest |
| Test location | /workspace/coverage/default/0.chip_sw_clkmgr_off_otbn_trans.3515691201 |
| Short name | T1028 |
| Test name | |
| Test status | |
| Simulation time | 4588955800 ps |
| CPU time | 471.29 seconds |
| Started | Jun 28 08:04:29 PM PDT 24 |
| Finished | Jun 28 08:12:21 PM PDT 24 |
| Peak memory | 609188 kb |
| Host | smart-44740669-d1e7-406a-9764-6d54413339b5 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_off_otbn_trans_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3515691201 -assert nopostproc +UVM_ TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_ log /dev/null -cm_name 0.chip_sw_clkmgr_off_otbn_trans.3515691201 |
| Directory | /workspace/0.chip_sw_clkmgr_off_otbn_trans/latest |
| Test location | /workspace/coverage/default/0.chip_sw_clkmgr_off_peri.1656341967 |
| Short name | T397 |
| Test name | |
| Test status | |
| Simulation time | 12614630916 ps |
| CPU time | 1823.37 seconds |
| Started | Jun 28 08:04:15 PM PDT 24 |
| Finished | Jun 28 08:34:40 PM PDT 24 |
| Peak memory | 609168 kb |
| Host | smart-82c1c448-7a8f-454f-8daa-6fedb823d184 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=30_000_000 +sw_build_device=sim_dv +sw_images=clkmgr_off_peri_test:1:new_rules,test_rom:0 +cdc_instrumenta tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1656341967 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/ coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_clkmgr_off_peri.1656341967 |
| Directory | /workspace/0.chip_sw_clkmgr_off_peri/latest |
| Test location | /workspace/coverage/default/0.chip_sw_clkmgr_reset_frequency.2502439524 |
| Short name | T1289 |
| Test name | |
| Test status | |
| Simulation time | 3623954780 ps |
| CPU time | 418.05 seconds |
| Started | Jun 28 08:00:14 PM PDT 24 |
| Finished | Jun 28 08:07:13 PM PDT 24 |
| Peak memory | 609188 kb |
| Host | smart-fd4bf339-35dc-49ed-8344-46a80f8781ec |
| User | root |
| Command | /workspace/default/simv +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=clkmgr_reset_frequency_test:1:new_rules,test_rom:0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2502439524 -a ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov erage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_clkmgr_reset_frequency.2502439524 |
| Directory | /workspace/0.chip_sw_clkmgr_reset_frequency/latest |
| Test location | /workspace/coverage/default/0.chip_sw_clkmgr_sleep_frequency.2669639601 |
| Short name | T1292 |
| Test name | |
| Test status | |
| Simulation time | 4880704000 ps |
| CPU time | 677.76 seconds |
| Started | Jun 28 08:02:21 PM PDT 24 |
| Finished | Jun 28 08:13:40 PM PDT 24 |
| Peak memory | 607788 kb |
| Host | smart-936a1405-ede5-4347-beaa-1d812c560aab |
| User | root |
| Command | /workspace/default/simv +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=clkmgr_sleep_frequency_test:1:new_rules,test_rom:0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2669639601 -a ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov erage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_clkmgr_sleep_frequency.2669639601 |
| Directory | /workspace/0.chip_sw_clkmgr_sleep_frequency/latest |
| Test location | /workspace/coverage/default/0.chip_sw_clkmgr_smoketest.1950908349 |
| Short name | T896 |
| Test name | |
| Test status | |
| Simulation time | 2845229270 ps |
| CPU time | 175.86 seconds |
| Started | Jun 28 08:02:03 PM PDT 24 |
| Finished | Jun 28 08:04:59 PM PDT 24 |
| Peak memory | 606300 kb |
| Host | smart-4260560c-9cd3-44b4-a7b3-52accab0f10e |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1950908349 -assert nopostproc +UVM_TESTNAME=c hip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n ull -cm_name 0.chip_sw_clkmgr_smoketest.1950908349 |
| Directory | /workspace/0.chip_sw_clkmgr_smoketest/latest |
| Test location | /workspace/coverage/default/0.chip_sw_coremark.756058088 |
| Short name | T1213 |
| Test name | |
| Test status | |
| Simulation time | 71446574120 ps |
| CPU time | 12960.6 seconds |
| Started | Jun 28 08:01:56 PM PDT 24 |
| Finished | Jun 28 11:37:59 PM PDT 24 |
| Peak memory | 608156 kb |
| Host | smart-7cfbce29-569d-46d0-9995-e2f14bdd08c5 |
| User | root |
| Command | /workspace/default/simv +en_uart_logger=1 +sw_test_timeout_ns=200_000_000 +sw_build_device=sim_dv +sw_images=coremark_test:1:new_rules,test_rom:0 +cdc _instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see d=756058088 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_coremark.756058088 |
| Directory | /workspace/0.chip_sw_coremark/latest |
| Test location | /workspace/coverage/default/0.chip_sw_csrng_edn_concurrency.4151419420 |
| Short name | T866 |
| Test name | |
| Test status | |
| Simulation time | 15798077864 ps |
| CPU time | 4156.4 seconds |
| Started | Jun 28 08:04:44 PM PDT 24 |
| Finished | Jun 28 09:14:03 PM PDT 24 |
| Peak memory | 608460 kb |
| Host | smart-07fd60ea-40e3-483b-b384-4a1be5e0635c |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=140_000_000 +rng_srate_value_min=15 +rng_srate_value_max=20 +accelerate_cold_power_up_time=3 +accelerate_r egulators_power_up_time=2 +sw_build_device=sim_dv +sw_images=csrng_edn_concurrency_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4151419420 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd b -cm_log /dev/null -cm_name 0.chip_sw_csrng_edn_concurrency.4151419420 |
| Directory | /workspace/0.chip_sw_csrng_edn_concurrency/latest |
| Test location | /workspace/coverage/default/0.chip_sw_csrng_fuse_en_sw_app_read_test.1447288197 |
| Short name | T947 |
| Test name | |
| Test status | |
| Simulation time | 3709460578 ps |
| CPU time | 367.67 seconds |
| Started | Jun 28 08:04:59 PM PDT 24 |
| Finished | Jun 28 08:11:08 PM PDT 24 |
| Peak memory | 609184 kb |
| Host | smart-e94deb1e-82e7-45bf-9ede-8859ae85d864 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=15_000_000 +sw_build_device=sim_dv +sw_images=csrng_fuse_en_sw_app_read:1:new_rules,test_rom:0 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14472 88197 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_entropy_src_fuse_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_csrng_fuse_en_sw_app_read_test.1447288197 |
| Directory | /workspace/0.chip_sw_csrng_fuse_en_sw_app_read_test/latest |
| Test location | /workspace/coverage/default/0.chip_sw_csrng_kat_test.4066685810 |
| Short name | T948 |
| Test name | |
| Test status | |
| Simulation time | 2782299320 ps |
| CPU time | 285.63 seconds |
| Started | Jun 28 08:03:54 PM PDT 24 |
| Finished | Jun 28 08:08:42 PM PDT 24 |
| Peak memory | 607104 kb |
| Host | smart-d4be7c96-5b4d-45d1-a733-592013142b57 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=csrng_kat_test:1:new_rules,test_rom:0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4066685810 -asse rt nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera ge/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_csrng_kat_test.4066685810 |
| Directory | /workspace/0.chip_sw_csrng_kat_test/latest |
| Test location | /workspace/coverage/default/0.chip_sw_csrng_lc_hw_debug_en_test.3426914617 |
| Short name | T1147 |
| Test name | |
| Test status | |
| Simulation time | 5669666299 ps |
| CPU time | 689.34 seconds |
| Started | Jun 28 08:05:53 PM PDT 24 |
| Finished | Jun 28 08:17:24 PM PDT 24 |
| Peak memory | 609516 kb |
| Host | smart-e3aacf98-3fa0-4679-aec1-1d2424038058 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=15_000_000 +rng_srate_value_min=15 +use_otp_image=OtpTypeLcStTestUnlocked0 +sw_build_device=sim_dv +sw_ima ges=csrng_lc_hw_debug_en_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3426914617 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_csrng_ lc_hw_debug_en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_csr ng_lc_hw_debug_en_test.3426914617 |
| Directory | /workspace/0.chip_sw_csrng_lc_hw_debug_en_test/latest |
| Test location | /workspace/coverage/default/0.chip_sw_csrng_smoketest.3693762463 |
| Short name | T968 |
| Test name | |
| Test status | |
| Simulation time | 2447882120 ps |
| CPU time | 278.66 seconds |
| Started | Jun 28 08:02:14 PM PDT 24 |
| Finished | Jun 28 08:06:53 PM PDT 24 |
| Peak memory | 607128 kb |
| Host | smart-edf3c2dc-6b91-48c8-b9d0-864cc34c0128 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=csrng_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3693762463 -assert nopostproc +UVM_TESTNAME=ch ip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu ll -cm_name 0.chip_sw_csrng_smoketest.3693762463 |
| Directory | /workspace/0.chip_sw_csrng_smoketest/latest |
| Test location | /workspace/coverage/default/0.chip_sw_data_integrity_escalation.1416249787 |
| Short name | T277 |
| Test name | |
| Test status | |
| Simulation time | 5689529048 ps |
| CPU time | 940.53 seconds |
| Started | Jun 28 08:01:25 PM PDT 24 |
| Finished | Jun 28 08:17:08 PM PDT 24 |
| Peak memory | 609272 kb |
| Host | smart-d4571140-d400-4a3d-9531-608e392788fb |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=data_integrity_escalation_reset_test:1:new_rules,test_ro m:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=1416249787 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_data_integrity_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_data_integrity_escalation.1416249787 |
| Directory | /workspace/0.chip_sw_data_integrity_escalation/latest |
| Test location | /workspace/coverage/default/0.chip_sw_edn_auto_mode.650019590 |
| Short name | T1129 |
| Test name | |
| Test status | |
| Simulation time | 3709664240 ps |
| CPU time | 669.6 seconds |
| Started | Jun 28 08:05:53 PM PDT 24 |
| Finished | Jun 28 08:17:04 PM PDT 24 |
| Peak memory | 609300 kb |
| Host | smart-5aa1ebad-cbf9-40b2-9053-1131390af5a8 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +rng_srate_value=5 +accelerate_cold_power_up_time=3 +accelerate_regulators_power_up_time=2 +sw_ build_device=sim_dv +sw_images=edn_auto_mode:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=650019590 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ= chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_edn_a uto_mode.650019590 |
| Directory | /workspace/0.chip_sw_edn_auto_mode/latest |
| Test location | /workspace/coverage/default/0.chip_sw_edn_kat.2205978889 |
| Short name | T1023 |
| Test name | |
| Test status | |
| Simulation time | 3064015416 ps |
| CPU time | 751.59 seconds |
| Started | Jun 28 08:04:06 PM PDT 24 |
| Finished | Jun 28 08:16:39 PM PDT 24 |
| Peak memory | 614544 kb |
| Host | smart-2ea06e0c-7896-4a07-8faa-5fa3eae3f3cd |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +rng_srate_value=5 +disable_assert_edn_output_diff_from_prev=1 +accelerate_cold_power_up_time=3 +accelerate_regulators_power_up_time=2 +sw_build_device=sim_dv +sw_images=edn_kat:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2205978889 -assert nopostproc +UVM _TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm _log /dev/null -cm_name 0.chip_sw_edn_kat.2205978889 |
| Directory | /workspace/0.chip_sw_edn_kat/latest |
| Test location | /workspace/coverage/default/0.chip_sw_edn_sw_mode.3130406435 |
| Short name | T120 |
| Test name | |
| Test status | |
| Simulation time | 7786768118 ps |
| CPU time | 1857.21 seconds |
| Started | Jun 28 08:04:41 PM PDT 24 |
| Finished | Jun 28 08:35:39 PM PDT 24 |
| Peak memory | 609180 kb |
| Host | smart-52141883-5c45-4ec8-85c1-907859910644 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=edn_sw_mode:1:new_rules,test_rom:0 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3130406435 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/ default.vdb -cm_log /dev/null -cm_name 0.chip_sw_edn_sw_mode.3130406435 |
| Directory | /workspace/0.chip_sw_edn_sw_mode/latest |
| Test location | /workspace/coverage/default/0.chip_sw_entropy_src_ast_rng_req.590170990 |
| Short name | T1105 |
| Test name | |
| Test status | |
| Simulation time | 2502027156 ps |
| CPU time | 223.62 seconds |
| Started | Jun 28 08:02:02 PM PDT 24 |
| Finished | Jun 28 08:05:46 PM PDT 24 |
| Peak memory | 609196 kb |
| Host | smart-19568743-4c70-416e-95eb-c58762a8bea0 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=15_000_000 +sw_build_device=sim_dv +sw_images=entropy_src_ast_rng_req_test:1:new_rules,test_rom:0 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59 0170990 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_entropy_src_ast_rng_req.590170990 |
| Directory | /workspace/0.chip_sw_entropy_src_ast_rng_req/latest |
| Test location | /workspace/coverage/default/0.chip_sw_entropy_src_csrng.2900069483 |
| Short name | T323 |
| Test name | |
| Test status | |
| Simulation time | 6582782790 ps |
| CPU time | 1621.81 seconds |
| Started | Jun 28 08:01:32 PM PDT 24 |
| Finished | Jun 28 08:28:35 PM PDT 24 |
| Peak memory | 608144 kb |
| Host | smart-f3a76282-45fa-4d4a-b706-6fb70931b6e9 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=50_000_000 +rng_srate_value_min=15 +rng_srate_value_max=30 +sw_build_device=sim_dv +sw_images=entropy_src_ csrng_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2900069483 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_entropy_src_csrng.2900069483 |
| Directory | /workspace/0.chip_sw_entropy_src_csrng/latest |
| Test location | /workspace/coverage/default/0.chip_sw_entropy_src_kat_test.994661981 |
| Short name | T876 |
| Test name | |
| Test status | |
| Simulation time | 2996225740 ps |
| CPU time | 268.89 seconds |
| Started | Jun 28 08:04:25 PM PDT 24 |
| Finished | Jun 28 08:08:56 PM PDT 24 |
| Peak memory | 609176 kb |
| Host | smart-c611f8a3-6aa5-40b7-951a-d71ca728d070 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=entropy_src_kat_test:1:new_rules,test_rom:0 +cdc_instrumenta tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=994661981 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/c overage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_entropy_src_kat_test.994661981 |
| Directory | /workspace/0.chip_sw_entropy_src_kat_test/latest |
| Test location | /workspace/coverage/default/0.chip_sw_entropy_src_smoketest.1130075157 |
| Short name | T1258 |
| Test name | |
| Test status | |
| Simulation time | 3876309788 ps |
| CPU time | 633.03 seconds |
| Started | Jun 28 08:06:46 PM PDT 24 |
| Finished | Jun 28 08:17:21 PM PDT 24 |
| Peak memory | 609180 kb |
| Host | smart-b6166a4d-96ed-4395-b494-43910fe93d4a |
| User | root |
| Command | /workspace/default/simv +rng_srate_value_min=15 +rng_srate_value_max=30 +sw_build_device=sim_dv +sw_images=entropy_src_smoketest:1:new_rules,test_rom: 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand om_seed=1130075157 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_entropy_src_smoketest.1130075157 |
| Directory | /workspace/0.chip_sw_entropy_src_smoketest/latest |
| Test location | /workspace/coverage/default/0.chip_sw_example_concurrency.1771439987 |
| Short name | T1095 |
| Test name | |
| Test status | |
| Simulation time | 3102644458 ps |
| CPU time | 296.8 seconds |
| Started | Jun 28 08:04:19 PM PDT 24 |
| Finished | Jun 28 08:09:17 PM PDT 24 |
| Peak memory | 607232 kb |
| Host | smart-dbeab956-7e49-4888-9ab8-cecfb233830c |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=example_concurrency_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1771439987 -assert nopostproc +UVM_TE STNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo g /dev/null -cm_name 0.chip_sw_example_concurrency.1771439987 |
| Directory | /workspace/0.chip_sw_example_concurrency/latest |
| Test location | /workspace/coverage/default/0.chip_sw_example_flash.424272585 |
| Short name | T923 |
| Test name | |
| Test status | |
| Simulation time | 2612908416 ps |
| CPU time | 235.37 seconds |
| Started | Jun 28 08:05:06 PM PDT 24 |
| Finished | Jun 28 08:09:03 PM PDT 24 |
| Peak memory | 609180 kb |
| Host | smart-6b898c4b-f2f0-4ff5-8992-366413dbbecc |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=example_test_from_flash:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=424272585 -assert nopostproc +UVM_TEST NAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_example_flash.424272585 |
| Directory | /workspace/0.chip_sw_example_flash/latest |
| Test location | /workspace/coverage/default/0.chip_sw_example_manufacturer.4126010672 |
| Short name | T1108 |
| Test name | |
| Test status | |
| Simulation time | 2574834312 ps |
| CPU time | 186.52 seconds |
| Started | Jun 28 08:03:03 PM PDT 24 |
| Finished | Jun 28 08:06:10 PM PDT 24 |
| Peak memory | 607128 kb |
| Host | smart-dcb66ecd-dc94-40f1-8748-7463dc1743f7 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=example_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4126010672 -assert nopostproc +UVM_TESTNAME=chip_ base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_example_manufacturer.4126010672 |
| Directory | /workspace/0.chip_sw_example_manufacturer/latest |
| Test location | /workspace/coverage/default/0.chip_sw_example_rom.568750640 |
| Short name | T1308 |
| Test name | |
| Test status | |
| Simulation time | 2428486680 ps |
| CPU time | 150.55 seconds |
| Started | Jun 28 07:59:29 PM PDT 24 |
| Finished | Jun 28 08:02:01 PM PDT 24 |
| Peak memory | 606764 kb |
| Host | smart-190b3c9b-6ddf-4bbb-80aa-a4e1e9817b8d |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:test_in_rom:new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=568750640 -assert nopostproc +UVM_TESTN AME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log / dev/null -cm_name 0.chip_sw_example_rom.568750640 |
| Directory | /workspace/0.chip_sw_example_rom/latest |
| Test location | /workspace/coverage/default/0.chip_sw_flash_crash_alert.73278555 |
| Short name | T429 |
| Test name | |
| Test status | |
| Simulation time | 6299903956 ps |
| CPU time | 737.72 seconds |
| Started | Jun 28 08:07:22 PM PDT 24 |
| Finished | Jun 28 08:19:43 PM PDT 24 |
| Peak memory | 609332 kb |
| Host | smart-aa612b14-2dbf-42c0-91cb-86ffdb9d6d7f |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=8_000_000 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1: new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tool s/sim.tcl +ntb_random_seed=73278555 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_flash_host_gnt_err_inj_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_flash_crash_alert.73278555 |
| Directory | /workspace/0.chip_sw_flash_crash_alert/latest |
| Test location | /workspace/coverage/default/0.chip_sw_flash_ctrl_access.2664545305 |
| Short name | T1068 |
| Test name | |
| Test status | |
| Simulation time | 6186591048 ps |
| CPU time | 1283.39 seconds |
| Started | Jun 28 07:59:49 PM PDT 24 |
| Finished | Jun 28 08:21:14 PM PDT 24 |
| Peak memory | 607124 kb |
| Host | smart-32ca29e8-7c10-4a80-95b0-3435728c6cb6 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=flash_ctrl_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2664545305 -assert nopostproc +UVM_TESTNAME=ch ip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu ll -cm_name 0.chip_sw_flash_ctrl_access.2664545305 |
| Directory | /workspace/0.chip_sw_flash_ctrl_access/latest |
| Test location | /workspace/coverage/default/0.chip_sw_flash_ctrl_access_jitter_en.283311933 |
| Short name | T313 |
| Test name | |
| Test status | |
| Simulation time | 6084811651 ps |
| CPU time | 1014.43 seconds |
| Started | Jun 28 07:59:47 PM PDT 24 |
| Finished | Jun 28 08:16:43 PM PDT 24 |
| Peak memory | 609176 kb |
| Host | smart-7a09cbb9-2c22-4380-917c-be1ea44e214a |
| User | root |
| Command | /workspace/default/simv +en_jitter=1 +sw_build_device=sim_dv +sw_images=flash_ctrl_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=283311933 -assert nopostproc +UVM _TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm _log /dev/null -cm_name 0.chip_sw_flash_ctrl_access_jitter_en.283311933 |
| Directory | /workspace/0.chip_sw_flash_ctrl_access_jitter_en/latest |
| Test location | /workspace/coverage/default/0.chip_sw_flash_ctrl_access_jitter_en_reduced_freq.3759374275 |
| Short name | T1111 |
| Test name | |
| Test status | |
| Simulation time | 7025718842 ps |
| CPU time | 1293.22 seconds |
| Started | Jun 28 08:08:47 PM PDT 24 |
| Finished | Jun 28 08:30:21 PM PDT 24 |
| Peak memory | 609200 kb |
| Host | smart-ab2cd374-7244-4be2-a840-19ef9f08cc0e |
| User | root |
| Command | /workspace/default/simv +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=flash_ctrl_test:1:new_rules,test_rom:0 +cdc_instrumentati on_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3759374275 - assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co verage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_flash_ctrl_access_jitter_en_reduced_freq.3759374275 |
| Directory | /workspace/0.chip_sw_flash_ctrl_access_jitter_en_reduced_freq/latest |
| Test location | /workspace/coverage/default/0.chip_sw_flash_ctrl_clock_freqs.2557700001 |
| Short name | T1178 |
| Test name | |
| Test status | |
| Simulation time | 5770807127 ps |
| CPU time | 1207.36 seconds |
| Started | Jun 28 08:01:12 PM PDT 24 |
| Finished | Jun 28 08:21:22 PM PDT 24 |
| Peak memory | 609188 kb |
| Host | smart-68214176-1174-4302-8fde-e10aee928f1d |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=flash_ctrl_clock_freqs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2557700001 -assert nopostproc +UVM _TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm _log /dev/null -cm_name 0.chip_sw_flash_ctrl_clock_freqs.2557700001 |
| Directory | /workspace/0.chip_sw_flash_ctrl_clock_freqs/latest |
| Test location | /workspace/coverage/default/0.chip_sw_flash_ctrl_idle_low_power.1105077114 |
| Short name | T902 |
| Test name | |
| Test status | |
| Simulation time | 3157762936 ps |
| CPU time | 403.57 seconds |
| Started | Jun 28 08:01:15 PM PDT 24 |
| Finished | Jun 28 08:08:02 PM PDT 24 |
| Peak memory | 609256 kb |
| Host | smart-fd2f8b85-33d6-49b6-b4a2-37a818f97c57 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=flash_ctrl_idle_low_power_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1105077114 -assert nopostproc + UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_flash_ctrl_idle_low_power.1105077114 |
| Directory | /workspace/0.chip_sw_flash_ctrl_idle_low_power/latest |
| Test location | /workspace/coverage/default/0.chip_sw_flash_ctrl_lc_rw_en.1152382280 |
| Short name | T233 |
| Test name | |
| Test status | |
| Simulation time | 5314047496 ps |
| CPU time | 389.29 seconds |
| Started | Jun 28 08:02:43 PM PDT 24 |
| Finished | Jun 28 08:09:14 PM PDT 24 |
| Peak memory | 609192 kb |
| Host | smart-732d4bb8-4949-426b-88f7-df9817ecdef2 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=flash_ctrl_lc_rw_en_test:1:new_rules,test_rom:0 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11 52382280 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_flash_ctrl_lc_rw_en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_flash_ctrl_lc_rw_en.1152382280 |
| Directory | /workspace/0.chip_sw_flash_ctrl_lc_rw_en/latest |
| Test location | /workspace/coverage/default/0.chip_sw_flash_ctrl_mem_protection.2075180865 |
| Short name | T1172 |
| Test name | |
| Test status | |
| Simulation time | 5572249292 ps |
| CPU time | 1094.91 seconds |
| Started | Jun 28 08:03:27 PM PDT 24 |
| Finished | Jun 28 08:21:44 PM PDT 24 |
| Peak memory | 607576 kb |
| Host | smart-c013cbb7-ba4e-48c5-a99c-9eaedcb02faa |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=flash_ctrl_mem_protection_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2075180865 -assert nopostproc + UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_flash_ctrl_mem_protection.2075180865 |
| Directory | /workspace/0.chip_sw_flash_ctrl_mem_protection/latest |
| Test location | /workspace/coverage/default/0.chip_sw_flash_ctrl_ops.2257104979 |
| Short name | T362 |
| Test name | |
| Test status | |
| Simulation time | 3698387456 ps |
| CPU time | 695.34 seconds |
| Started | Jun 28 08:06:55 PM PDT 24 |
| Finished | Jun 28 08:18:31 PM PDT 24 |
| Peak memory | 607696 kb |
| Host | smart-d988e98d-1f6c-4cf2-a874-d3046afb9906 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=50_000_000 +sw_build_device=sim_dv +sw_images=flash_ctrl_ops_test:1:new_rules,test_rom:0 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2257104979 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/c overage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_flash_ctrl_ops.2257104979 |
| Directory | /workspace/0.chip_sw_flash_ctrl_ops/latest |
| Test location | /workspace/coverage/default/0.chip_sw_flash_ctrl_ops_jitter_en_reduced_freq.782442407 |
| Short name | T361 |
| Test name | |
| Test status | |
| Simulation time | 5378398238 ps |
| CPU time | 820.85 seconds |
| Started | Jun 28 08:02:33 PM PDT 24 |
| Finished | Jun 28 08:16:16 PM PDT 24 |
| Peak memory | 609180 kb |
| Host | smart-713be98f-e776-4fbe-9a27-73bc8a03ee24 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=50_000_000 +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=flash_ctrl_ops_test:1:new_ rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si m.tcl +ntb_random_seed=782442407 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_flash_ctrl_ops_jitter_en_reduced_freq.782442407 |
| Directory | /workspace/0.chip_sw_flash_ctrl_ops_jitter_en_reduced_freq/latest |
| Test location | /workspace/coverage/default/0.chip_sw_flash_ctrl_write_clear.1431411466 |
| Short name | T1240 |
| Test name | |
| Test status | |
| Simulation time | 3472385286 ps |
| CPU time | 254.01 seconds |
| Started | Jun 28 08:01:57 PM PDT 24 |
| Finished | Jun 28 08:06:11 PM PDT 24 |
| Peak memory | 609184 kb |
| Host | smart-587e3088-9785-4559-a197-862b81f2b06f |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=8_000_000 +sw_build_device=sim_dv +sw_images=flash_ctrl_write_clear_test:1:new_rules,test_rom:0 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1431411 466 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_flash_ctrl_write_clear.1431411466 |
| Directory | /workspace/0.chip_sw_flash_ctrl_write_clear/latest |
| Test location | /workspace/coverage/default/0.chip_sw_flash_init_reduced_freq.3529266978 |
| Short name | T229 |
| Test name | |
| Test status | |
| Simulation time | 18789759048 ps |
| CPU time | 2216.37 seconds |
| Started | Jun 28 08:08:08 PM PDT 24 |
| Finished | Jun 28 08:45:07 PM PDT 24 |
| Peak memory | 610748 kb |
| Host | smart-b2308d97-75d6-4c40-b3ec-091cd1ce2325 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=25_000_000 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=flash_init_test:0:test_in_rom:new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=3529266978 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_flash_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_flash_init_reduced_freq.3529266978 |
| Directory | /workspace/0.chip_sw_flash_init_reduced_freq/latest |
| Test location | /workspace/coverage/default/0.chip_sw_flash_scrambling_smoketest.2516288326 |
| Short name | T1235 |
| Test name | |
| Test status | |
| Simulation time | 2668119216 ps |
| CPU time | 211.97 seconds |
| Started | Jun 28 08:05:24 PM PDT 24 |
| Finished | Jun 28 08:08:58 PM PDT 24 |
| Peak memory | 607612 kb |
| Host | smart-44056939-1d1b-4571-b553-f8df041777cd |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=flash_scrambling_smoketest:1:new_rules,flash_scrambling_smoket est_otp_img_rma:4,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=2516288326 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_flash_scrambling_smoketest.2516288326 |
| Directory | /workspace/0.chip_sw_flash_scrambling_smoketest/latest |
| Test location | /workspace/coverage/default/0.chip_sw_gpio_smoketest.2351342836 |
| Short name | T1198 |
| Test name | |
| Test status | |
| Simulation time | 3114502957 ps |
| CPU time | 346.61 seconds |
| Started | Jun 28 08:05:05 PM PDT 24 |
| Finished | Jun 28 08:10:54 PM PDT 24 |
| Peak memory | 607888 kb |
| Host | smart-4dac4a61-3ccc-48bc-be90-f2f27b1ea40b |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=gpio_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2351342836 -assert nopostproc +UVM_TESTNAME=chi p_base_test +UVM_TEST_SEQ=chip_sw_gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 0.chip_sw_gpio_smoketest.2351342836 |
| Directory | /workspace/0.chip_sw_gpio_smoketest/latest |
| Test location | /workspace/coverage/default/0.chip_sw_hmac_enc.3809053969 |
| Short name | T1058 |
| Test name | |
| Test status | |
| Simulation time | 2346383900 ps |
| CPU time | 202.19 seconds |
| Started | Jun 28 08:02:54 PM PDT 24 |
| Finished | Jun 28 08:06:18 PM PDT 24 |
| Peak memory | 607128 kb |
| Host | smart-0b91822d-a74a-4030-938c-1daae1ec167a |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=hmac_enc_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3809053969 -assert nopostproc +UVM_TESTNAME=chip _base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_hmac_enc.3809053969 |
| Directory | /workspace/0.chip_sw_hmac_enc/latest |
| Test location | /workspace/coverage/default/0.chip_sw_hmac_enc_jitter_en.3057480979 |
| Short name | T92 |
| Test name | |
| Test status | |
| Simulation time | 2642267132 ps |
| CPU time | 229.85 seconds |
| Started | Jun 28 08:00:32 PM PDT 24 |
| Finished | Jun 28 08:04:23 PM PDT 24 |
| Peak memory | 607108 kb |
| Host | smart-fe9b1546-169e-4da2-912c-f4ab6486f494 |
| User | root |
| Command | /workspace/default/simv +en_jitter=1 +sw_build_device=sim_dv +sw_images=hmac_enc_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3057480979 -assert nopostproc +UVM_ TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_ log /dev/null -cm_name 0.chip_sw_hmac_enc_jitter_en.3057480979 |
| Directory | /workspace/0.chip_sw_hmac_enc_jitter_en/latest |
| Test location | /workspace/coverage/default/0.chip_sw_hmac_enc_jitter_en_reduced_freq.2317289295 |
| Short name | T1183 |
| Test name | |
| Test status | |
| Simulation time | 3488972801 ps |
| CPU time | 256.42 seconds |
| Started | Jun 28 08:09:33 PM PDT 24 |
| Finished | Jun 28 08:13:50 PM PDT 24 |
| Peak memory | 609160 kb |
| Host | smart-e8b5ec9b-f315-4667-bd07-c5502381c75e |
| User | root |
| Command | /workspace/default/simv +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=hmac_enc_test:1:new_rules,test_rom:0 +cdc_instrumentation _enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2317289295 -as sert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove rage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_hmac_enc_jitter_en_reduced_freq.2317289295 |
| Directory | /workspace/0.chip_sw_hmac_enc_jitter_en_reduced_freq/latest |
| Test location | /workspace/coverage/default/0.chip_sw_hmac_multistream.1663293629 |
| Short name | T670 |
| Test name | |
| Test status | |
| Simulation time | 8520917128 ps |
| CPU time | 2236.24 seconds |
| Started | Jun 28 08:02:59 PM PDT 24 |
| Finished | Jun 28 08:40:17 PM PDT 24 |
| Peak memory | 609240 kb |
| Host | smart-499beffb-ff68-470e-bf53-8c49cbea5ec4 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=hmac_multistream_functest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1663293629 -assert nopostproc +UVM_T ESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l og /dev/null -cm_name 0.chip_sw_hmac_multistream.1663293629 |
| Directory | /workspace/0.chip_sw_hmac_multistream/latest |
| Test location | /workspace/coverage/default/0.chip_sw_hmac_oneshot.758445547 |
| Short name | T894 |
| Test name | |
| Test status | |
| Simulation time | 2803865748 ps |
| CPU time | 281.8 seconds |
| Started | Jun 28 08:00:51 PM PDT 24 |
| Finished | Jun 28 08:05:34 PM PDT 24 |
| Peak memory | 607140 kb |
| Host | smart-18fc0090-cbf6-4223-9f86-75716beacda3 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=hmac_functest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=758445547 -assert nopostproc +UVM_TESTNAME=chip_ base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_hmac_oneshot.758445547 |
| Directory | /workspace/0.chip_sw_hmac_oneshot/latest |
| Test location | /workspace/coverage/default/0.chip_sw_hmac_smoketest.2596684003 |
| Short name | T671 |
| Test name | |
| Test status | |
| Simulation time | 3124722440 ps |
| CPU time | 366.89 seconds |
| Started | Jun 28 08:02:22 PM PDT 24 |
| Finished | Jun 28 08:08:30 PM PDT 24 |
| Peak memory | 607124 kb |
| Host | smart-f10b0eaa-9a77-4b28-bc83-9dcb7aa174ed |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=hmac_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2596684003 -assert nopostproc +UVM_TESTNAME=chi p_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul l -cm_name 0.chip_sw_hmac_smoketest.2596684003 |
| Directory | /workspace/0.chip_sw_hmac_smoketest/latest |
| Test location | /workspace/coverage/default/0.chip_sw_i2c_device_tx_rx.1610728558 |
| Short name | T331 |
| Test name | |
| Test status | |
| Simulation time | 3661705908 ps |
| CPU time | 614.34 seconds |
| Started | Jun 28 08:04:29 PM PDT 24 |
| Finished | Jun 28 08:14:45 PM PDT 24 |
| Peak memory | 609320 kb |
| Host | smart-bdf68d01-6799-406e-92d0-f847eb773ba9 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=i2c_device_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1610728558 -assert nopostproc +UVM_TESTN AME=chip_base_test +UVM_TEST_SEQ=chip_sw_i2c_device_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v db -cm_log /dev/null -cm_name 0.chip_sw_i2c_device_tx_rx.1610728558 |
| Directory | /workspace/0.chip_sw_i2c_device_tx_rx/latest |
| Test location | /workspace/coverage/default/0.chip_sw_i2c_host_tx_rx_idx2.2775587911 |
| Short name | T1069 |
| Test name | |
| Test status | |
| Simulation time | 4615630860 ps |
| CPU time | 785.15 seconds |
| Started | Jun 28 08:05:43 PM PDT 24 |
| Finished | Jun 28 08:18:49 PM PDT 24 |
| Peak memory | 608288 kb |
| Host | smart-f7486b12-856a-4af4-be6e-a74225c74de7 |
| User | root |
| Command | /workspace/default/simv +i2c_idx=2 +sw_build_device=sim_dv +sw_images=i2c_host_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2775587911 -assert nopostproc + UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_i2c_host_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de fault.vdb -cm_log /dev/null -cm_name 0.chip_sw_i2c_host_tx_rx_idx2.2775587911 |
| Directory | /workspace/0.chip_sw_i2c_host_tx_rx_idx2/latest |
| Test location | /workspace/coverage/default/0.chip_sw_inject_scramble_seed.3658354876 |
| Short name | T1051 |
| Test name | |
| Test status | |
| Simulation time | 64636283491 ps |
| CPU time | 13156.1 seconds |
| Started | Jun 28 08:01:55 PM PDT 24 |
| Finished | Jun 28 11:41:14 PM PDT 24 |
| Peak memory | 623964 kb |
| Host | smart-d983a84b-36cf-47d8-a3aa-9f147c839c0d |
| User | root |
| Command | /workspace/default/simv +lc_at_prod=1 +flash_program_latency=5 +sw_test_timeout_ns=150_000_000 +sw_build_device=sim_dv +sw_images=inject_scramble_seed :1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=3658354876 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_inject_scramble_seed_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_inject_scramble_seed.3658354876 |
| Directory | /workspace/0.chip_sw_inject_scramble_seed/latest |
| Test location | /workspace/coverage/default/0.chip_sw_keymgr_key_derivation.3141469472 |
| Short name | T1166 |
| Test name | |
| Test status | |
| Simulation time | 6501941712 ps |
| CPU time | 1013.67 seconds |
| Started | Jun 28 08:00:49 PM PDT 24 |
| Finished | Jun 28 08:17:45 PM PDT 24 |
| Peak memory | 615948 kb |
| Host | smart-5a258fbf-0032-4aff-824c-28ff54f12a30 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=20_000_000 +sw_build_device=sim_dv +sw_images=keymgr_key_derivation_test:1:new_rules,test_rom:0 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3141 469472 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_keymgr_key_derivation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_keymgr_key_derivation.3141469472 |
| Directory | /workspace/0.chip_sw_keymgr_key_derivation/latest |
| Test location | /workspace/coverage/default/0.chip_sw_keymgr_key_derivation_jitter_en.943304939 |
| Short name | T1165 |
| Test name | |
| Test status | |
| Simulation time | 6744395199 ps |
| CPU time | 1266.54 seconds |
| Started | Jun 28 08:03:44 PM PDT 24 |
| Finished | Jun 28 08:24:54 PM PDT 24 |
| Peak memory | 615948 kb |
| Host | smart-6da5b3af-7ae5-43f2-bd9b-5d4de8a1d3ce |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=20_000_000 +en_jitter=1 +sw_build_device=sim_dv +sw_images=keymgr_key_derivation_test:1:new_rules,test_rom :0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=943304939 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_keymgr_key_derivation_vseq +en_cov=1 -cm line+cond+fsm+tg l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_keymgr_key_derivation_jitter_en.943304939 |
| Directory | /workspace/0.chip_sw_keymgr_key_derivation_jitter_en/latest |
| Test location | /workspace/coverage/default/0.chip_sw_keymgr_key_derivation_jitter_en_reduced_freq.3137696747 |
| Short name | T1164 |
| Test name | |
| Test status | |
| Simulation time | 9011652173 ps |
| CPU time | 1599.88 seconds |
| Started | Jun 28 08:09:46 PM PDT 24 |
| Finished | Jun 28 08:36:28 PM PDT 24 |
| Peak memory | 614424 kb |
| Host | smart-44cbdbad-ba07-4ae3-9047-9964a3c3f640 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=20_000_000 +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=keymgr_key_derivation_test :1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=3137696747 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_keymgr_key_derivation_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_keymgr_key_derivation_jitter_en _reduced_freq.3137696747 |
| Directory | /workspace/0.chip_sw_keymgr_key_derivation_jitter_en_reduced_freq/latest |
| Test location | /workspace/coverage/default/0.chip_sw_keymgr_key_derivation_prod.204584471 |
| Short name | T1015 |
| Test name | |
| Test status | |
| Simulation time | 9632315586 ps |
| CPU time | 1670.4 seconds |
| Started | Jun 28 07:59:39 PM PDT 24 |
| Finished | Jun 28 08:27:31 PM PDT 24 |
| Peak memory | 615708 kb |
| Host | smart-4a07f406-90ae-4160-b244-ffc18e84b1bf |
| User | root |
| Command | /workspace/default/simv +lc_at_prod=1 +sw_test_timeout_ns=20_000_000 +sw_build_device=sim_dv +sw_images=keymgr_key_derivation_test:1:new_rules,test_ro m:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=204584471 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_keymgr_key_derivation_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_keymgr_key_derivation_prod.204584471 |
| Directory | /workspace/0.chip_sw_keymgr_key_derivation_prod/latest |
| Test location | /workspace/coverage/default/0.chip_sw_keymgr_sideload_kmac.3513508504 |
| Short name | T210 |
| Test name | |
| Test status | |
| Simulation time | 7369993216 ps |
| CPU time | 1076 seconds |
| Started | Jun 28 08:01:03 PM PDT 24 |
| Finished | Jun 28 08:19:01 PM PDT 24 |
| Peak memory | 609260 kb |
| Host | smart-dd25cde2-2524-4a3d-af8e-185d0f887b9f |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=20_000_000 +sw_build_device=sim_dv +sw_images=keymgr_sideload_kmac_test:1:new_rules,test_rom:0 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35135 08504 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_keymgr_sideload_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_keymgr_sideload_kmac.3513508504 |
| Directory | /workspace/0.chip_sw_keymgr_sideload_kmac/latest |
| Test location | /workspace/coverage/default/0.chip_sw_keymgr_sideload_otbn.4095576664 |
| Short name | T221 |
| Test name | |
| Test status | |
| Simulation time | 18006867084 ps |
| CPU time | 4686.79 seconds |
| Started | Jun 28 08:01:31 PM PDT 24 |
| Finished | Jun 28 09:19:39 PM PDT 24 |
| Peak memory | 609240 kb |
| Host | smart-5801a279-0710-4f02-9342-e006fa0274e8 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=20_000_000 +sw_build_device=sim_dv +sw_images=keymgr_sideload_otbn_test:1:new_rules,test_rom:0 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40955 76664 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_keymgr_sideload_otbn.4095576664 |
| Directory | /workspace/0.chip_sw_keymgr_sideload_otbn/latest |
| Test location | /workspace/coverage/default/0.chip_sw_kmac_app_rom.2034961208 |
| Short name | T408 |
| Test name | |
| Test status | |
| Simulation time | 2879707704 ps |
| CPU time | 277.03 seconds |
| Started | Jun 28 08:03:50 PM PDT 24 |
| Finished | Jun 28 08:08:29 PM PDT 24 |
| Peak memory | 607112 kb |
| Host | smart-caa2cf59-7511-45b9-86f7-9a859549df1c |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=kmac_app_rom_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2034961208 -assert nopostproc +UVM_TESTNAME= chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/ null -cm_name 0.chip_sw_kmac_app_rom.2034961208 |
| Directory | /workspace/0.chip_sw_kmac_app_rom/latest |
| Test location | /workspace/coverage/default/0.chip_sw_kmac_entropy.1064136398 |
| Short name | T432 |
| Test name | |
| Test status | |
| Simulation time | 2471373700 ps |
| CPU time | 334.68 seconds |
| Started | Jun 28 07:59:51 PM PDT 24 |
| Finished | Jun 28 08:05:27 PM PDT 24 |
| Peak memory | 607128 kb |
| Host | smart-f4aedc87-9cce-439e-9112-c375f5ed01fc |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=kmac_entropy_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1064136398 -assert nopostproc +UVM_TESTNAME= chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/ null -cm_name 0.chip_sw_kmac_entropy.1064136398 |
| Directory | /workspace/0.chip_sw_kmac_entropy/latest |
| Test location | /workspace/coverage/default/0.chip_sw_kmac_idle.2776452493 |
| Short name | T1195 |
| Test name | |
| Test status | |
| Simulation time | 3161204800 ps |
| CPU time | 183.4 seconds |
| Started | Jun 28 08:02:30 PM PDT 24 |
| Finished | Jun 28 08:05:35 PM PDT 24 |
| Peak memory | 607124 kb |
| Host | smart-872ceaae-86ff-430b-adac-32c4454eaf88 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=kmac_idle_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2776452493 -assert nopostproc +UVM_TESTNAME=chi p_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul l -cm_name 0.chip_sw_kmac_idle.2776452493 |
| Directory | /workspace/0.chip_sw_kmac_idle/latest |
| Test location | /workspace/coverage/default/0.chip_sw_kmac_mode_cshake.680904980 |
| Short name | T942 |
| Test name | |
| Test status | |
| Simulation time | 3021187964 ps |
| CPU time | 262.04 seconds |
| Started | Jun 28 08:00:42 PM PDT 24 |
| Finished | Jun 28 08:05:06 PM PDT 24 |
| Peak memory | 609180 kb |
| Host | smart-64dcf0c4-8a7d-4d92-8e22-65fa9f5d561e |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=kmac_mode_cshake_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=680904980 -assert nopostproc +UVM_TESTNA ME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 0.chip_sw_kmac_mode_cshake.680904980 |
| Directory | /workspace/0.chip_sw_kmac_mode_cshake/latest |
| Test location | /workspace/coverage/default/0.chip_sw_kmac_mode_kmac.1391788322 |
| Short name | T1018 |
| Test name | |
| Test status | |
| Simulation time | 2941028180 ps |
| CPU time | 263.16 seconds |
| Started | Jun 28 07:59:33 PM PDT 24 |
| Finished | Jun 28 08:03:58 PM PDT 24 |
| Peak memory | 609164 kb |
| Host | smart-9ba336fb-0da3-4441-a659-8043ecbe624a |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=kmac_mode_kmac_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1391788322 -assert nopostproc +UVM_TESTNAM E=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 0.chip_sw_kmac_mode_kmac.1391788322 |
| Directory | /workspace/0.chip_sw_kmac_mode_kmac/latest |
| Test location | /workspace/coverage/default/0.chip_sw_kmac_mode_kmac_jitter_en.705431708 |
| Short name | T861 |
| Test name | |
| Test status | |
| Simulation time | 2809161505 ps |
| CPU time | 278.88 seconds |
| Started | Jun 28 08:02:59 PM PDT 24 |
| Finished | Jun 28 08:07:39 PM PDT 24 |
| Peak memory | 607112 kb |
| Host | smart-8ff58248-8705-4c45-a31f-baa1d02d9cbb |
| User | root |
| Command | /workspace/default/simv +en_jitter=1 +sw_build_device=sim_dv +sw_images=kmac_mode_kmac_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=705431708 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_kmac_mode_kmac_jitter_en.705431708 |
| Directory | /workspace/0.chip_sw_kmac_mode_kmac_jitter_en/latest |
| Test location | /workspace/coverage/default/0.chip_sw_kmac_mode_kmac_jitter_en_reduced_freq.2778184846 |
| Short name | T1093 |
| Test name | |
| Test status | |
| Simulation time | 3089421764 ps |
| CPU time | 274.45 seconds |
| Started | Jun 28 08:03:19 PM PDT 24 |
| Finished | Jun 28 08:07:54 PM PDT 24 |
| Peak memory | 607092 kb |
| Host | smart-689470cf-50b1-474d-9859-c3b611d19bd1 |
| User | root |
| Command | /workspace/default/simv +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=kmac_mode_kmac_test:1:new_rules,test_rom:0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27781848 46 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac e/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_kmac_mode_kmac_jitter_en_reduced_freq.2778184846 |
| Directory | /workspace/0.chip_sw_kmac_mode_kmac_jitter_en_reduced_freq/latest |
| Test location | /workspace/coverage/default/0.chip_sw_kmac_smoketest.4279772807 |
| Short name | T1202 |
| Test name | |
| Test status | |
| Simulation time | 2545334890 ps |
| CPU time | 309.73 seconds |
| Started | Jun 28 08:06:42 PM PDT 24 |
| Finished | Jun 28 08:11:55 PM PDT 24 |
| Peak memory | 607128 kb |
| Host | smart-bc7780a9-0925-498f-bd70-208008eb0366 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=kmac_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4279772807 -assert nopostproc +UVM_TESTNAME=chi p_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul l -cm_name 0.chip_sw_kmac_smoketest.4279772807 |
| Directory | /workspace/0.chip_sw_kmac_smoketest/latest |
| Test location | /workspace/coverage/default/0.chip_sw_lc_ctrl_otp_hw_cfg0.3286438538 |
| Short name | T869 |
| Test name | |
| Test status | |
| Simulation time | 2661033656 ps |
| CPU time | 275.66 seconds |
| Started | Jun 28 08:00:32 PM PDT 24 |
| Finished | Jun 28 08:05:10 PM PDT 24 |
| Peak memory | 609188 kb |
| Host | smart-05bef398-98ae-458b-937b-94f86d78558b |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=lc_ctrl_otp_hw_cfg0_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3286438538 -assert nopostproc +UVM_TE STNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo g /dev/null -cm_name 0.chip_sw_lc_ctrl_otp_hw_cfg0.3286438538 |
| Directory | /workspace/0.chip_sw_lc_ctrl_otp_hw_cfg0/latest |
| Test location | /workspace/coverage/default/0.chip_sw_lc_ctrl_rand_to_scrap.3308566000 |
| Short name | T61 |
| Test name | |
| Test status | |
| Simulation time | 3362393575 ps |
| CPU time | 177.5 seconds |
| Started | Jun 28 08:04:07 PM PDT 24 |
| Finished | Jun 28 08:07:07 PM PDT 24 |
| Peak memory | 617516 kb |
| Host | smart-2fdde188-2f3e-458e-8e5d-ee47ee6e7e38 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=lc_ctrl_scrap_test:1:new_rules,test_rom:0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33085660 00 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_scrap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_lc_ctrl_rand_to_scrap.3308566000 |
| Directory | /workspace/0.chip_sw_lc_ctrl_rand_to_scrap/latest |
| Test location | /workspace/coverage/default/0.chip_sw_lc_ctrl_raw_to_scrap.1523444847 |
| Short name | T645 |
| Test name | |
| Test status | |
| Simulation time | 3507847059 ps |
| CPU time | 147.73 seconds |
| Started | Jun 28 08:05:36 PM PDT 24 |
| Finished | Jun 28 08:08:04 PM PDT 24 |
| Peak memory | 617560 kb |
| Host | smart-4a7faf73-bada-431d-9921-f1445319ecb2 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +src_dec_state=DecLcStRaw +sw_build_device=sim_dv +sw_images=lc_ctrl_scrap_test:1:new_rules ,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1523444847 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_scrap_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_lc_ctrl_raw_to_scrap.1523444847 |
| Directory | /workspace/0.chip_sw_lc_ctrl_raw_to_scrap/latest |
| Test location | /workspace/coverage/default/0.chip_sw_lc_ctrl_test_locked0_to_scrap.2154931296 |
| Short name | T168 |
| Test name | |
| Test status | |
| Simulation time | 2721261814 ps |
| CPU time | 137.92 seconds |
| Started | Jun 28 08:05:32 PM PDT 24 |
| Finished | Jun 28 08:07:51 PM PDT 24 |
| Peak memory | 617572 kb |
| Host | smart-7384539d-dbd3-4266-a39a-f6727d676852 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +src_dec_state=DecLcStTestLocked0 +sw_build_device=sim_dv +sw_images=lc_ctrl_scrap_test:1:n ew_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2154931296 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_scrap_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_lc_ctrl_test_locked0_to_scrap.2154931296 |
| Directory | /workspace/0.chip_sw_lc_ctrl_test_locked0_to_scrap/latest |
| Test location | /workspace/coverage/default/0.chip_sw_lc_ctrl_transition.3975100404 |
| Short name | T1154 |
| Test name | |
| Test status | |
| Simulation time | 12728269549 ps |
| CPU time | 1089.94 seconds |
| Started | Jun 28 08:04:15 PM PDT 24 |
| Finished | Jun 28 08:22:26 PM PDT 24 |
| Peak memory | 621312 kb |
| Host | smart-de415b67-8144-4af2-973e-b6f3cba71c3e |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=lc_ctrl_transition_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3975100404 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_transition_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau lt.vdb -cm_log /dev/null -cm_name 0.chip_sw_lc_ctrl_transition.3975100404 |
| Directory | /workspace/0.chip_sw_lc_ctrl_transition/latest |
| Test location | /workspace/coverage/default/0.chip_sw_lc_ctrl_volatile_raw_unlock.1152846488 |
| Short name | T285 |
| Test name | |
| Test status | |
| Simulation time | 2579566376 ps |
| CPU time | 105.83 seconds |
| Started | Jun 28 08:06:33 PM PDT 24 |
| Finished | Jun 28 08:08:21 PM PDT 24 |
| Peak memory | 615956 kb |
| Host | smart-47ebd149-d921-4d35-8ae9-e70839bc763c |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStRaw +exp_volatile_raw_unlock_en=0 +sw_build_device=sim_dv +sw_images=lc_ctrl_volatile_raw_unlock_tes t:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/ tools/sim.tcl +ntb_random_seed=1152846488 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_volatile_raw_unlock_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_lc_ctrl_volatile_raw_unlock.1152846488 |
| Directory | /workspace/0.chip_sw_lc_ctrl_volatile_raw_unlock/latest |
| Test location | /workspace/coverage/default/0.chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz.4077111167 |
| Short name | T265 |
| Test name | |
| Test status | |
| Simulation time | 2352581705 ps |
| CPU time | 112.17 seconds |
| Started | Jun 28 08:05:44 PM PDT 24 |
| Finished | Jun 28 08:07:37 PM PDT 24 |
| Peak memory | 614432 kb |
| Host | smart-a1a107ed-5268-4f92-8fbc-f32e7802cb97 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStRaw +chip_clock_source=ChipClockSourceExternal48Mhz +exp_volatile_raw_unlock_en=0 +sw_build_device=s im_dv +sw_images=lc_ctrl_volatile_raw_unlock_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4077111167 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TES T_SEQ=chip_sw_lc_volatile_raw_unlock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz.4077111167 |
| Directory | /workspace/0.chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz/latest |
| Test location | /workspace/coverage/default/0.chip_sw_lc_walkthrough_prod.2525705131 |
| Short name | T228 |
| Test name | |
| Test status | |
| Simulation time | 49100050200 ps |
| CPU time | 5841.45 seconds |
| Started | Jun 28 08:04:06 PM PDT 24 |
| Finished | Jun 28 09:41:29 PM PDT 24 |
| Peak memory | 615004 kb |
| Host | smart-58744c64-9d3f-4598-83a2-81e9fe221334 |
| User | root |
| Command | /workspace/default/simv +flash_program_latency=5 +use_otp_image=OtpTypeLcStRaw +dest_dec_state=DecLcStProd +sw_test_timeout_ns=200_000_000 +sw_build_d evice=sim_dv +sw_images=lc_walkthrough_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2525705131 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ= chip_sw_lc_walkthrough_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chi p_sw_lc_walkthrough_prod.2525705131 |
| Directory | /workspace/0.chip_sw_lc_walkthrough_prod/latest |
| Test location | /workspace/coverage/default/0.chip_sw_lc_walkthrough_prodend.1903862696 |
| Short name | T390 |
| Test name | |
| Test status | |
| Simulation time | 9405139378 ps |
| CPU time | 1264.42 seconds |
| Started | Jun 28 08:05:37 PM PDT 24 |
| Finished | Jun 28 08:26:43 PM PDT 24 |
| Peak memory | 617692 kb |
| Host | smart-a07faf36-f246-4dfe-9074-6e5f75ba233a |
| User | root |
| Command | /workspace/default/simv +flash_program_latency=5 +use_otp_image=OtpTypeLcStRaw +dest_dec_state=DecLcStProdEnd +sw_build_device=sim_dv +sw_images=lc_wa lkthrough_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1903862696 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_walkthrough_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_lc_walkthrough_prodend.1903862696 |
| Directory | /workspace/0.chip_sw_lc_walkthrough_prodend/latest |
| Test location | /workspace/coverage/default/0.chip_sw_lc_walkthrough_rma.2392977636 |
| Short name | T230 |
| Test name | |
| Test status | |
| Simulation time | 47573057630 ps |
| CPU time | 5007.42 seconds |
| Started | Jun 28 08:08:25 PM PDT 24 |
| Finished | Jun 28 09:31:54 PM PDT 24 |
| Peak memory | 618032 kb |
| Host | smart-5eb8cc34-cf21-48ca-8ab7-b61340806f87 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStRaw +dest_dec_state=DecLcStRma +flash_program_latency=5 +sw_test_timeout_ns=200_000_000 +sw_build_de vice=sim_dv +sw_images=lc_walkthrough_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2392977636 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=c hip_sw_lc_walkthrough_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip _sw_lc_walkthrough_rma.2392977636 |
| Directory | /workspace/0.chip_sw_lc_walkthrough_rma/latest |
| Test location | /workspace/coverage/default/0.chip_sw_lc_walkthrough_testunlocks.2383839747 |
| Short name | T167 |
| Test name | |
| Test status | |
| Simulation time | 31209478595 ps |
| CPU time | 2686.11 seconds |
| Started | Jun 28 08:05:27 PM PDT 24 |
| Finished | Jun 28 08:50:15 PM PDT 24 |
| Peak memory | 623560 kb |
| Host | smart-75acf8e9-8e47-454e-868a-ba050184a366 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStRaw +dest_dec_state=DecLcStTestUnlock7 +sw_build_device=sim_dv +sw_images=lc_walkthrough_testunlocks _test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=2383839747 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_walkthrough_testunlocks_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_lc_walkthrough_testun locks.2383839747 |
| Directory | /workspace/0.chip_sw_lc_walkthrough_testunlocks/latest |
| Test location | /workspace/coverage/default/0.chip_sw_otbn_ecdsa_op_irq_jitter_en.2159129746 |
| Short name | T144 |
| Test name | |
| Test status | |
| Simulation time | 18920957492 ps |
| CPU time | 4040.65 seconds |
| Started | Jun 28 08:08:15 PM PDT 24 |
| Finished | Jun 28 09:15:36 PM PDT 24 |
| Peak memory | 609312 kb |
| Host | smart-fc96c525-1bb4-42bd-b9e2-36dc56022320 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=33_000_000 +rng_srate_value=30 +en_jitter=1 +sw_build_device=sim_dv +sw_images=otbn_ecdsa_op_irq_test:1:ne w_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/ sim.tcl +ntb_random_seed=2159129746 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tg l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_otbn_ecdsa_op_irq_jitter_en.2159129746 |
| Directory | /workspace/0.chip_sw_otbn_ecdsa_op_irq_jitter_en/latest |
| Test location | /workspace/coverage/default/0.chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq.1002678145 |
| Short name | T1307 |
| Test name | |
| Test status | |
| Simulation time | 25117098733 ps |
| CPU time | 4408.42 seconds |
| Started | Jun 28 08:09:08 PM PDT 24 |
| Finished | Jun 28 09:22:38 PM PDT 24 |
| Peak memory | 608184 kb |
| Host | smart-46c5a741-eb92-47e2-a143-d52f9a4c96b6 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=33_000_000 +rng_srate_value=30 +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=otbn_e cdsa_op_irq_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/ repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1002678145 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_otbn_ecdsa_op_irq_jitter_en_redu ced_freq.1002678145 |
| Directory | /workspace/0.chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq/latest |
| Test location | /workspace/coverage/default/0.chip_sw_otbn_mem_scramble.1188821123 |
| Short name | T1057 |
| Test name | |
| Test status | |
| Simulation time | 3997212616 ps |
| CPU time | 445.96 seconds |
| Started | Jun 28 08:06:40 PM PDT 24 |
| Finished | Jun 28 08:14:08 PM PDT 24 |
| Peak memory | 609184 kb |
| Host | smart-0579a489-8947-4e32-9d51-7a41c740ed18 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=15_000_000 +en_scb_tl_err_chk=0 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=otbn _mem_scramble_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1188821123 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_otbn_mem_scramble.1188821123 |
| Directory | /workspace/0.chip_sw_otbn_mem_scramble/latest |
| Test location | /workspace/coverage/default/0.chip_sw_otbn_randomness.3739476437 |
| Short name | T1075 |
| Test name | |
| Test status | |
| Simulation time | 5953321628 ps |
| CPU time | 1016.81 seconds |
| Started | Jun 28 08:06:20 PM PDT 24 |
| Finished | Jun 28 08:23:19 PM PDT 24 |
| Peak memory | 609396 kb |
| Host | smart-cb363b39-fc59-485a-b95f-632bd1d533f1 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +rng_srate_value=30 +sw_build_device=sim_dv +sw_images=otbn_randomness_test:1:new_rules,test_ro m:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=3739476437 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_otbn_randomness.3739476437 |
| Directory | /workspace/0.chip_sw_otbn_randomness/latest |
| Test location | /workspace/coverage/default/0.chip_sw_otbn_smoketest.1012246716 |
| Short name | T915 |
| Test name | |
| Test status | |
| Simulation time | 6783865866 ps |
| CPU time | 1570.14 seconds |
| Started | Jun 28 08:04:06 PM PDT 24 |
| Finished | Jun 28 08:30:17 PM PDT 24 |
| Peak memory | 606800 kb |
| Host | smart-77ad5603-a806-4fdd-abdf-d6cca3e6511d |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=otbn_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1012246716 -assert nopostproc +UVM_TESTNAME=chi p_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul l -cm_name 0.chip_sw_otbn_smoketest.1012246716 |
| Directory | /workspace/0.chip_sw_otbn_smoketest/latest |
| Test location | /workspace/coverage/default/0.chip_sw_otp_ctrl_dai_lock.456952078 |
| Short name | T1076 |
| Test name | |
| Test status | |
| Simulation time | 27351793880 ps |
| CPU time | 6175.82 seconds |
| Started | Jun 28 08:00:32 PM PDT 24 |
| Finished | Jun 28 09:43:29 PM PDT 24 |
| Peak memory | 609196 kb |
| Host | smart-5c1681c8-fc9e-4a98-91a4-7d39d33b0e00 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=30_000_000 +sw_build_device=sim_dv +sw_images=otp_ctrl_mem_access_test:1:new_rules,test_rom:0 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=456952 078 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_otp_ctrl_dai_lock.456952078 |
| Directory | /workspace/0.chip_sw_otp_ctrl_dai_lock/latest |
| Test location | /workspace/coverage/default/0.chip_sw_otp_ctrl_ecc_error_vendor_test.1499146130 |
| Short name | T981 |
| Test name | |
| Test status | |
| Simulation time | 2832512828 ps |
| CPU time | 267.53 seconds |
| Started | Jun 28 07:58:46 PM PDT 24 |
| Finished | Jun 28 08:03:15 PM PDT 24 |
| Peak memory | 609184 kb |
| Host | smart-3a902ffb-b71b-46d3-af31-4154b86ace96 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=otp_ctrl_vendor_test_ecc_error_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1499146130 -assert nopostp roc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_otp_ctrl_vendor_test_ecc_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_otp_ctrl_ecc_error_vendor_test.1499146130 |
| Directory | /workspace/0.chip_sw_otp_ctrl_ecc_error_vendor_test/latest |
| Test location | /workspace/coverage/default/0.chip_sw_otp_ctrl_lc_signals_dev.3379448837 |
| Short name | T937 |
| Test name | |
| Test status | |
| Simulation time | 8822210912 ps |
| CPU time | 1615.78 seconds |
| Started | Jun 28 08:04:22 PM PDT 24 |
| Finished | Jun 28 08:31:19 PM PDT 24 |
| Peak memory | 609184 kb |
| Host | smart-db5e7920-8afc-40bb-86d2-f7bc45d7b2de |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStDev +otp_clear_secret2=1 +sw_build_device=sim_dv +sw_images=otp_ctrl_lc_signals_test:1:new_rules,tes t_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +nt b_random_seed=3379448837 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_otp_ctrl_lc_signals_dev.3379448837 |
| Directory | /workspace/0.chip_sw_otp_ctrl_lc_signals_dev/latest |
| Test location | /workspace/coverage/default/0.chip_sw_otp_ctrl_lc_signals_prod.3108265813 |
| Short name | T1284 |
| Test name | |
| Test status | |
| Simulation time | 7963715136 ps |
| CPU time | 1368.99 seconds |
| Started | Jun 28 08:04:16 PM PDT 24 |
| Finished | Jun 28 08:27:07 PM PDT 24 |
| Peak memory | 609180 kb |
| Host | smart-461485a3-69b5-4b49-81a7-0984de2cb6eb |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStProd +otp_clear_secret2=1 +sw_build_device=sim_dv +sw_images=otp_ctrl_lc_signals_test:1:new_rules,te st_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n tb_random_seed=3108265813 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_otp_ctrl_lc_signals_prod.3108265813 |
| Directory | /workspace/0.chip_sw_otp_ctrl_lc_signals_prod/latest |
| Test location | /workspace/coverage/default/0.chip_sw_otp_ctrl_lc_signals_rma.1462533249 |
| Short name | T104 |
| Test name | |
| Test status | |
| Simulation time | 8266590168 ps |
| CPU time | 1277.46 seconds |
| Started | Jun 28 08:03:06 PM PDT 24 |
| Finished | Jun 28 08:24:25 PM PDT 24 |
| Peak memory | 608244 kb |
| Host | smart-8e4aef84-13cb-4a2d-ba5a-bfdf5c4b995d |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStRma +otp_clear_secret2=1 +sw_build_device=sim_dv +sw_images=otp_ctrl_lc_signals_test:1:new_rules,tes t_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +nt b_random_seed=1462533249 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_otp_ctrl_lc_signals_rma.1462533249 |
| Directory | /workspace/0.chip_sw_otp_ctrl_lc_signals_rma/latest |
| Test location | /workspace/coverage/default/0.chip_sw_otp_ctrl_lc_signals_test_unlocked0.1145914270 |
| Short name | T1132 |
| Test name | |
| Test status | |
| Simulation time | 4808720240 ps |
| CPU time | 739.07 seconds |
| Started | Jun 28 08:06:38 PM PDT 24 |
| Finished | Jun 28 08:19:00 PM PDT 24 |
| Peak memory | 609300 kb |
| Host | smart-6c34c27a-15fc-4321-b383-032e227ce172 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStTestUnlocked0 +otp_clear_secret2=1 +sw_build_device=sim_dv +sw_images=otp_ctrl_lc_signals_test:1:new _rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/s im.tcl +ntb_random_seed=1145914270 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_otp_ctrl_lc_signals_test_unlocked0.1145914270 |
| Directory | /workspace/0.chip_sw_otp_ctrl_lc_signals_test_unlocked0/latest |
| Test location | /workspace/coverage/default/0.chip_sw_otp_ctrl_smoketest.2199624831 |
| Short name | T1080 |
| Test name | |
| Test status | |
| Simulation time | 3515949194 ps |
| CPU time | 363.26 seconds |
| Started | Jun 28 08:04:17 PM PDT 24 |
| Finished | Jun 28 08:10:22 PM PDT 24 |
| Peak memory | 609172 kb |
| Host | smart-bb026b24-f2a3-455f-89ff-1964f70f11bb |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=otp_ctrl_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2199624831 -assert nopostproc +UVM_TESTNAME =chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 0.chip_sw_otp_ctrl_smoketest.2199624831 |
| Directory | /workspace/0.chip_sw_otp_ctrl_smoketest/latest |
| Test location | /workspace/coverage/default/0.chip_sw_pattgen_ios.1360372996 |
| Short name | T346 |
| Test name | |
| Test status | |
| Simulation time | 2679117430 ps |
| CPU time | 354.77 seconds |
| Started | Jun 28 07:58:59 PM PDT 24 |
| Finished | Jun 28 08:04:55 PM PDT 24 |
| Peak memory | 607672 kb |
| Host | smart-2545c3f2-1d09-4578-a75d-e05266807cfa |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=5_000_000 +sw_build_device=sim_dv +sw_images=pattgen_ios_test:1:new_rules,test_rom:0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1360372996 -ass ert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_patt_ios_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/c overage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pattgen_ios.1360372996 |
| Directory | /workspace/0.chip_sw_pattgen_ios/latest |
| Test location | /workspace/coverage/default/0.chip_sw_power_sleep_load.2959816063 |
| Short name | T665 |
| Test name | |
| Test status | |
| Simulation time | 4112952112 ps |
| CPU time | 363.76 seconds |
| Started | Jun 28 08:02:42 PM PDT 24 |
| Finished | Jun 28 08:08:47 PM PDT 24 |
| Peak memory | 606800 kb |
| Host | smart-c4d87af2-aace-4f01-8ced-5799b86b68b7 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=chip_power_sleep_load:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2959816063 -assert nopostproc +UVM_TESTN AME=chip_base_test +UVM_TEST_SEQ=chip_sw_power_sleep_load_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v db -cm_log /dev/null -cm_name 0.chip_sw_power_sleep_load.2959816063 |
| Directory | /workspace/0.chip_sw_power_sleep_load/latest |
| Test location | /workspace/coverage/default/0.chip_sw_pwrmgr_all_reset_reqs.1271256595 |
| Short name | T1242 |
| Test name | |
| Test status | |
| Simulation time | 9155729569 ps |
| CPU time | 1505.76 seconds |
| Started | Jun 28 08:04:19 PM PDT 24 |
| Finished | Jun 28 08:29:26 PM PDT 24 |
| Peak memory | 609276 kb |
| Host | smart-2087808e-a7e3-439f-a2d7-154dd69fb013 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=50_000_000 +sw_build_device=sim_dv +sw_images=pwrmgr_all_reset_reqs_test:1:new_rules,test_rom:0 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1271 256595 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_deep_sleep_all_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_all_reset_reqs.1271256595 |
| Directory | /workspace/0.chip_sw_pwrmgr_all_reset_reqs/latest |
| Test location | /workspace/coverage/default/0.chip_sw_pwrmgr_b2b_sleep_reset_req.2127056698 |
| Short name | T1008 |
| Test name | |
| Test status | |
| Simulation time | 27093458400 ps |
| CPU time | 2398.32 seconds |
| Started | Jun 28 08:00:55 PM PDT 24 |
| Finished | Jun 28 08:40:55 PM PDT 24 |
| Peak memory | 609260 kb |
| Host | smart-915f225e-676c-4d88-ba08-1bd847cf5e46 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=35_000_000 +sw_build_device=sim_dv +sw_images=pwrmgr_b2b_sleep_reset_test:1:new_rules,test_rom:0 +cdc_inst rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=212 7056698 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_repeat_reset_wkup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_b2b_sleep_reset_req.2127056698 |
| Directory | /workspace/0.chip_sw_pwrmgr_b2b_sleep_reset_req/latest |
| Test location | /workspace/coverage/default/0.chip_sw_pwrmgr_deep_sleep_all_reset_reqs.2432106650 |
| Short name | T262 |
| Test name | |
| Test status | |
| Simulation time | 13640881788 ps |
| CPU time | 1797.82 seconds |
| Started | Jun 28 08:05:51 PM PDT 24 |
| Finished | Jun 28 08:35:51 PM PDT 24 |
| Peak memory | 609376 kb |
| Host | smart-3d9908e3-2c0f-4481-a3b6-dd1b2287aeef |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=50_000_000 +sw_build_device=sim_dv +sw_images=pwrmgr_deep_sleep_all_reset_reqs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=2432106650 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_deep_sleep_all_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_deep_sleep_all_reset_reqs.2432106650 |
| Directory | /workspace/0.chip_sw_pwrmgr_deep_sleep_all_reset_reqs/latest |
| Test location | /workspace/coverage/default/0.chip_sw_pwrmgr_deep_sleep_all_wake_ups.2127232474 |
| Short name | T97 |
| Test name | |
| Test status | |
| Simulation time | 22386880604 ps |
| CPU time | 2238.33 seconds |
| Started | Jun 28 08:04:37 PM PDT 24 |
| Finished | Jun 28 08:41:56 PM PDT 24 |
| Peak memory | 608476 kb |
| Host | smart-202756e2-1516-4e2c-8004-99c7e15d93d6 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=pwrmgr_deep_sleep_all_wake_ups:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 2127232474 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_pwrmgr_deep_sleep_all_wake_ups_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_deep_sleep_all_wake_ups.2127232474 |
| Directory | /workspace/0.chip_sw_pwrmgr_deep_sleep_all_wake_ups/latest |
| Test location | /workspace/coverage/default/0.chip_sw_pwrmgr_deep_sleep_por_reset.1815283822 |
| Short name | T20 |
| Test name | |
| Test status | |
| Simulation time | 7145419082 ps |
| CPU time | 822.49 seconds |
| Started | Jun 28 08:04:38 PM PDT 24 |
| Finished | Jun 28 08:18:21 PM PDT 24 |
| Peak memory | 609256 kb |
| Host | smart-96126ea0-ed31-4147-b03e-a164a1ddc866 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_deep_sleep_por_reset_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1815283822 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sleep_por_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage /default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_deep_sleep_por_reset.1815283822 |
| Directory | /workspace/0.chip_sw_pwrmgr_deep_sleep_por_reset/latest |
| Test location | /workspace/coverage/default/0.chip_sw_pwrmgr_main_power_glitch_reset.3448473635 |
| Short name | T987 |
| Test name | |
| Test status | |
| Simulation time | 4049313714 ps |
| CPU time | 401.47 seconds |
| Started | Jun 28 08:02:37 PM PDT 24 |
| Finished | Jun 28 08:09:20 PM PDT 24 |
| Peak memory | 615028 kb |
| Host | smart-17211a9d-a2d7-476e-84a4-9e0765ba8780 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=pwrmgr_main_power_glitch_test:1:new_rules,test_rom:0 +cd c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se ed=3448473635 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_main_power_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_main_power_glitch_reset.3448473635 |
| Directory | /workspace/0.chip_sw_pwrmgr_main_power_glitch_reset/latest |
| Test location | /workspace/coverage/default/0.chip_sw_pwrmgr_normal_sleep_all_reset_reqs.984245452 |
| Short name | T1205 |
| Test name | |
| Test status | |
| Simulation time | 12813070336 ps |
| CPU time | 1722.88 seconds |
| Started | Jun 28 08:06:03 PM PDT 24 |
| Finished | Jun 28 08:34:47 PM PDT 24 |
| Peak memory | 609376 kb |
| Host | smart-3b80762c-54ee-41ad-af2f-45d368d14e04 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_normal_sleep_all_reset_reqs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=984245452 -assert nopo stproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_deep_sleep_all_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_normal_sleep_all_reset_reqs.984245452 |
| Directory | /workspace/0.chip_sw_pwrmgr_normal_sleep_all_reset_reqs/latest |
| Test location | /workspace/coverage/default/0.chip_sw_pwrmgr_normal_sleep_all_wake_ups.2288998275 |
| Short name | T96 |
| Test name | |
| Test status | |
| Simulation time | 7251595674 ps |
| CPU time | 369.92 seconds |
| Started | Jun 28 08:02:42 PM PDT 24 |
| Finished | Jun 28 08:08:54 PM PDT 24 |
| Peak memory | 608008 kb |
| Host | smart-fa94b4f3-974a-4a57-bb8f-8f82c037d902 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_normal_sleep_all_wake_ups:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2288998275 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_pwrmgr_deep_sleep_all_wake_ups_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_normal_sleep_all_wake_ups.2288998275 |
| Directory | /workspace/0.chip_sw_pwrmgr_normal_sleep_all_wake_ups/latest |
| Test location | /workspace/coverage/default/0.chip_sw_pwrmgr_normal_sleep_por_reset.3188151807 |
| Short name | T1160 |
| Test name | |
| Test status | |
| Simulation time | 5311515787 ps |
| CPU time | 584.41 seconds |
| Started | Jun 28 08:04:15 PM PDT 24 |
| Finished | Jun 28 08:14:00 PM PDT 24 |
| Peak memory | 609216 kb |
| Host | smart-4f58c5be-0549-4735-be02-bd03e91da980 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_normal_sleep_por_reset_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3188151807 -assert nopostpr oc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sleep_por_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera ge/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_normal_sleep_por_reset.3188151807 |
| Directory | /workspace/0.chip_sw_pwrmgr_normal_sleep_por_reset/latest |
| Test location | /workspace/coverage/default/0.chip_sw_pwrmgr_random_sleep_all_reset_reqs.2188438140 |
| Short name | T906 |
| Test name | |
| Test status | |
| Simulation time | 22966644952 ps |
| CPU time | 2636.22 seconds |
| Started | Jun 28 08:03:29 PM PDT 24 |
| Finished | Jun 28 08:47:27 PM PDT 24 |
| Peak memory | 609008 kb |
| Host | smart-63ef6350-0dac-47a8-8098-8c86d13b5d0d |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=50_000_000 +sw_build_device=sim_dv +sw_images=pwrmgr_random_sleep_all_reset_reqs_test:1:new_rules,test_rom :0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=2188438140 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_deep_sleep_all_reset_vseq +en_cov=1 -cm line+cond+fsm+tg l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_random_sleep_all_reset_reqs.2188438140 |
| Directory | /workspace/0.chip_sw_pwrmgr_random_sleep_all_reset_reqs/latest |
| Test location | /workspace/coverage/default/0.chip_sw_pwrmgr_random_sleep_all_wake_ups.815975842 |
| Short name | T3 |
| Test name | |
| Test status | |
| Simulation time | 24416690904 ps |
| CPU time | 1794.14 seconds |
| Started | Jun 28 08:04:30 PM PDT 24 |
| Finished | Jun 28 08:34:25 PM PDT 24 |
| Peak memory | 608484 kb |
| Host | smart-f8356f10-a48c-42dc-aa62-d3370ddc6cca |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +do_random=1 +sw_build_device=sim_dv +sw_images=pwrmgr_random_sleep_all_wake_ups:1:new_rules,te st_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n tb_random_seed=815975842 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_pwrmgr_deep_sleep_all_wake_ups_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_random_sleep_all_wake_ups.815975842 |
| Directory | /workspace/0.chip_sw_pwrmgr_random_sleep_all_wake_ups/latest |
| Test location | /workspace/coverage/default/0.chip_sw_pwrmgr_random_sleep_power_glitch_reset.262857390 |
| Short name | T944 |
| Test name | |
| Test status | |
| Simulation time | 34799929148 ps |
| CPU time | 3438.93 seconds |
| Started | Jun 28 08:05:08 PM PDT 24 |
| Finished | Jun 28 09:02:29 PM PDT 24 |
| Peak memory | 610408 kb |
| Host | smart-9fe31fd7-364f-4484-a6cd-ae02e349a7bc |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_test_timeout_ns=24_000_000 +sw_build_device=sim_dv +sw_images=pwrmgr_random_sleep_power _glitch_reset_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=262857390 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_random_power_glitc h_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_random_sl eep_power_glitch_reset.262857390 |
| Directory | /workspace/0.chip_sw_pwrmgr_random_sleep_power_glitch_reset/latest |
| Test location | /workspace/coverage/default/0.chip_sw_pwrmgr_sleep_disabled.2584781784 |
| Short name | T1186 |
| Test name | |
| Test status | |
| Simulation time | 3109281752 ps |
| CPU time | 237.99 seconds |
| Started | Jun 28 08:05:30 PM PDT 24 |
| Finished | Jun 28 08:09:29 PM PDT 24 |
| Peak memory | 609164 kb |
| Host | smart-9e6d6da6-28fd-475c-9f10-196718e6713e |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_sleep_disabled_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2584781784 -assert nopostproc +UVM_ TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_ log /dev/null -cm_name 0.chip_sw_pwrmgr_sleep_disabled.2584781784 |
| Directory | /workspace/0.chip_sw_pwrmgr_sleep_disabled/latest |
| Test location | /workspace/coverage/default/0.chip_sw_pwrmgr_sleep_power_glitch_reset.223223816 |
| Short name | T978 |
| Test name | |
| Test status | |
| Simulation time | 5817638170 ps |
| CPU time | 548.04 seconds |
| Started | Jun 28 08:03:59 PM PDT 24 |
| Finished | Jun 28 08:13:09 PM PDT 24 |
| Peak memory | 615508 kb |
| Host | smart-af85ae9e-09a7-4c5d-a96e-ed8ef23d18b7 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=pwrmgr_sleep_power_glitch_test:1:new_rules,test_rom:0 +c dc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_s eed=223223816 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_main_power_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_sleep_power_glitch_reset.223223816 |
| Directory | /workspace/0.chip_sw_pwrmgr_sleep_power_glitch_reset/latest |
| Test location | /workspace/coverage/default/0.chip_sw_pwrmgr_sleep_wake_5_bug.4139503208 |
| Short name | T1104 |
| Test name | |
| Test status | |
| Simulation time | 5438460006 ps |
| CPU time | 549.62 seconds |
| Started | Jun 28 08:01:32 PM PDT 24 |
| Finished | Jun 28 08:10:43 PM PDT 24 |
| Peak memory | 608460 kb |
| Host | smart-142319f9-2a1d-4bcd-94ff-217a41203278 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +do_random=1 +sw_build_device=sim_dv +sw_images=pwrmgr_sleep_wake_5_bug_test:1:new_rules,test_r om:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r andom_seed=4139503208 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_sleep_wake_5_bug.4139503208 |
| Directory | /workspace/0.chip_sw_pwrmgr_sleep_wake_5_bug/latest |
| Test location | /workspace/coverage/default/0.chip_sw_pwrmgr_smoketest.3132906675 |
| Short name | T1177 |
| Test name | |
| Test status | |
| Simulation time | 4874420398 ps |
| CPU time | 394.76 seconds |
| Started | Jun 28 08:03:40 PM PDT 24 |
| Finished | Jun 28 08:10:16 PM PDT 24 |
| Peak memory | 609256 kb |
| Host | smart-10ce21c7-2de8-42d4-94b6-3a5efb576959 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=10000000 +sw_build_device=sim_dv +sw_images=pwrmgr_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3132906675 -asse rt nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera ge/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_smoketest.3132906675 |
| Directory | /workspace/0.chip_sw_pwrmgr_smoketest/latest |
| Test location | /workspace/coverage/default/0.chip_sw_pwrmgr_sysrst_ctrl_reset.3221734107 |
| Short name | T1282 |
| Test name | |
| Test status | |
| Simulation time | 8160469238 ps |
| CPU time | 1230.33 seconds |
| Started | Jun 28 08:04:19 PM PDT 24 |
| Finished | Jun 28 08:24:50 PM PDT 24 |
| Peak memory | 608268 kb |
| Host | smart-030e99c3-7aa1-443d-8fb5-7377a0224c10 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_sysrst_ctrl_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3221734107 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_sysrst_ctrl_reset.3221734107 |
| Directory | /workspace/0.chip_sw_pwrmgr_sysrst_ctrl_reset/latest |
| Test location | /workspace/coverage/default/0.chip_sw_pwrmgr_usb_clk_disabled_when_active.424460981 |
| Short name | T387 |
| Test name | |
| Test status | |
| Simulation time | 4070791792 ps |
| CPU time | 498.84 seconds |
| Started | Jun 28 08:08:26 PM PDT 24 |
| Finished | Jun 28 08:16:46 PM PDT 24 |
| Peak memory | 609156 kb |
| Host | smart-781d76fd-cd13-43e7-abe2-431ef4047c92 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_usb_clk_disabled_when_active_test:1:new_rules,test_rom:0 +cdc_instrumentation_enable d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=424460981 -assert nop ostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def ault.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_usb_clk_disabled_when_active.424460981 |
| Directory | /workspace/0.chip_sw_pwrmgr_usb_clk_disabled_when_active/latest |
| Test location | /workspace/coverage/default/0.chip_sw_pwrmgr_usbdev_smoketest.3900837231 |
| Short name | T1159 |
| Test name | |
| Test status | |
| Simulation time | 5359311628 ps |
| CPU time | 424.76 seconds |
| Started | Jun 28 08:04:22 PM PDT 24 |
| Finished | Jun 28 08:11:28 PM PDT 24 |
| Peak memory | 607972 kb |
| Host | smart-7d719784-e72a-41cf-be62-95375b8ea6d5 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_usbdev_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3900837231 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_usbdev_smoketest.3900837231 |
| Directory | /workspace/0.chip_sw_pwrmgr_usbdev_smoketest/latest |
| Test location | /workspace/coverage/default/0.chip_sw_pwrmgr_wdog_reset.3899857690 |
| Short name | T898 |
| Test name | |
| Test status | |
| Simulation time | 5036367598 ps |
| CPU time | 410.61 seconds |
| Started | Jun 28 08:06:40 PM PDT 24 |
| Finished | Jun 28 08:13:33 PM PDT 24 |
| Peak memory | 609176 kb |
| Host | smart-c7c606c7-5c52-4f85-b2fd-0573be7fb4a7 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=pwrmgr_wdog_reset_reqs_test:1:new_rules,test_rom:0 +cdc_inst rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=389 9857690 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_wdog_reset.3899857690 |
| Directory | /workspace/0.chip_sw_pwrmgr_wdog_reset/latest |
| Test location | /workspace/coverage/default/0.chip_sw_rom_ctrl_integrity_check.3023178445 |
| Short name | T406 |
| Test name | |
| Test status | |
| Simulation time | 8094833173 ps |
| CPU time | 737.64 seconds |
| Started | Jun 28 08:01:13 PM PDT 24 |
| Finished | Jun 28 08:13:34 PM PDT 24 |
| Peak memory | 607984 kb |
| Host | smart-61f889c2-c4ce-4e41-b4e4-0b8d1360bcd2 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=rom_ctrl_integrity_check_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3023178445 -assert nopostproc +U VM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_ctrl_integrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co verage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_rom_ctrl_integrity_check.3023178445 |
| Directory | /workspace/0.chip_sw_rom_ctrl_integrity_check/latest |
| Test location | /workspace/coverage/default/0.chip_sw_rstmgr_alert_info.3705584724 |
| Short name | T152 |
| Test name | |
| Test status | |
| Simulation time | 13443499728 ps |
| CPU time | 2374.89 seconds |
| Started | Jun 28 08:02:37 PM PDT 24 |
| Finished | Jun 28 08:42:14 PM PDT 24 |
| Peak memory | 608536 kb |
| Host | smart-561bc086-8cba-481d-bef4-43974f239c86 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=30_000_000 +en_scb_tl_err_chk=0 +sw_build_device=sim_dv +sw_images=rstmgr_alert_info_test:1:new_rules,test _rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb _random_seed=3705584724 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_rstmgr_alert_info.3705584724 |
| Directory | /workspace/0.chip_sw_rstmgr_alert_info/latest |
| Test location | /workspace/coverage/default/0.chip_sw_rstmgr_cpu_info.3367177247 |
| Short name | T259 |
| Test name | |
| Test status | |
| Simulation time | 5681971496 ps |
| CPU time | 569.63 seconds |
| Started | Jun 28 08:05:19 PM PDT 24 |
| Finished | Jun 28 08:14:52 PM PDT 24 |
| Peak memory | 607216 kb |
| Host | smart-78d171af-6f8a-4de6-93b7-5f9a3865d700 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=rstmgr_cpu_info_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3367177247 -assert nopostproc +UVM_TESTNA ME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 0.chip_sw_rstmgr_cpu_info.3367177247 |
| Directory | /workspace/0.chip_sw_rstmgr_cpu_info/latest |
| Test location | /workspace/coverage/default/0.chip_sw_rstmgr_rst_cnsty_escalation.1638372738 |
| Short name | T715 |
| Test name | |
| Test status | |
| Simulation time | 5275446440 ps |
| CPU time | 688.52 seconds |
| Started | Jun 28 08:04:31 PM PDT 24 |
| Finished | Jun 28 08:16:01 PM PDT 24 |
| Peak memory | 639580 kb |
| Host | smart-d5fccdc3-aa6d-47d2-b9cf-6c877ae19914 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 1638372738 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rstmgr_cnsty_fault_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_rstmgr_rst_cnsty_escalation.1638372738 |
| Directory | /workspace/0.chip_sw_rstmgr_rst_cnsty_escalation/latest |
| Test location | /workspace/coverage/default/0.chip_sw_rstmgr_smoketest.2055260166 |
| Short name | T972 |
| Test name | |
| Test status | |
| Simulation time | 2714834196 ps |
| CPU time | 270.6 seconds |
| Started | Jun 28 08:03:42 PM PDT 24 |
| Finished | Jun 28 08:08:14 PM PDT 24 |
| Peak memory | 607136 kb |
| Host | smart-ffbb252b-be4d-491b-aa5b-4ef85c68384f |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=rstmgr_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2055260166 -assert nopostproc +UVM_TESTNAME=c hip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n ull -cm_name 0.chip_sw_rstmgr_smoketest.2055260166 |
| Directory | /workspace/0.chip_sw_rstmgr_smoketest/latest |
| Test location | /workspace/coverage/default/0.chip_sw_rstmgr_sw_req.3820638355 |
| Short name | T188 |
| Test name | |
| Test status | |
| Simulation time | 3713399608 ps |
| CPU time | 473.67 seconds |
| Started | Jun 28 08:05:14 PM PDT 24 |
| Finished | Jun 28 08:13:10 PM PDT 24 |
| Peak memory | 607140 kb |
| Host | smart-9cb2ddc0-fcb0-4830-950a-977a7293418c |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=rstmgr_sw_req_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3820638355 -assert nopostproc +UVM_TESTNAME =chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 0.chip_sw_rstmgr_sw_req.3820638355 |
| Directory | /workspace/0.chip_sw_rstmgr_sw_req/latest |
| Test location | /workspace/coverage/default/0.chip_sw_rstmgr_sw_rst.4225890882 |
| Short name | T1268 |
| Test name | |
| Test status | |
| Simulation time | 2478087688 ps |
| CPU time | 241.31 seconds |
| Started | Jun 28 08:07:19 PM PDT 24 |
| Finished | Jun 28 08:11:22 PM PDT 24 |
| Peak memory | 609092 kb |
| Host | smart-799aeb42-ef34-467b-8920-5ce06429c728 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=rstmgr_sw_rst_ctrl_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4225890882 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_rstmgr_sw_rst.4225890882 |
| Directory | /workspace/0.chip_sw_rstmgr_sw_rst/latest |
| Test location | /workspace/coverage/default/0.chip_sw_rv_core_ibex_icache_invalidate.200146263 |
| Short name | T173 |
| Test name | |
| Test status | |
| Simulation time | 2874939748 ps |
| CPU time | 257.41 seconds |
| Started | Jun 28 08:00:38 PM PDT 24 |
| Finished | Jun 28 08:04:58 PM PDT 24 |
| Peak memory | 609308 kb |
| Host | smart-127425ab-c4f5-4c23-9636-e6b5dd8af08e |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=rv_core_ibex_icache_invalidate_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=200146263 -assert nopostpr oc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rv_core_ibex_icache_invalidate_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_rv_core_ibex_icache_invalidate.200146263 |
| Directory | /workspace/0.chip_sw_rv_core_ibex_icache_invalidate/latest |
| Test location | /workspace/coverage/default/0.chip_sw_rv_core_ibex_rnd.1967268685 |
| Short name | T929 |
| Test name | |
| Test status | |
| Simulation time | 5872543912 ps |
| CPU time | 1034.81 seconds |
| Started | Jun 28 08:05:07 PM PDT 24 |
| Finished | Jun 28 08:22:23 PM PDT 24 |
| Peak memory | 609180 kb |
| Host | smart-9094a054-0d70-4f87-b6c6-53d78b179254 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=20_000_000 +rng_srate_value_max=32 +sw_build_device=sim_dv +sw_images=rv_core_ibex_rnd_test:1:new_rules,te st_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n tb_random_seed=1967268685 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_rv_core_ibex_rnd.1967268685 |
| Directory | /workspace/0.chip_sw_rv_core_ibex_rnd/latest |
| Test location | /workspace/coverage/default/0.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted.3579750852 |
| Short name | T76 |
| Test name | |
| Test status | |
| Simulation time | 3440613384 ps |
| CPU time | 426.52 seconds |
| Started | Jun 28 08:02:54 PM PDT 24 |
| Finished | Jun 28 08:10:02 PM PDT 24 |
| Peak memory | 614884 kb |
| Host | smart-79070db0-7486-4b85-97cb-45d6e0eab901 |
| User | root |
| Command | /workspace/default/simv +use_jtag_dmi=1 +sw_build_device=sim_dv +sw_images=rv_dm_ndm_reset_req_when_cpu_halted_rma:1:new_rules,test_rom:0 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=357975 0852 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rv_dm_ndm_reset_when_cpu_halted_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted.3579750852 |
| Directory | /workspace/0.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted/latest |
| Test location | /workspace/coverage/default/0.chip_sw_rv_plic_smoketest.828578841 |
| Short name | T1239 |
| Test name | |
| Test status | |
| Simulation time | 2822506812 ps |
| CPU time | 271.3 seconds |
| Started | Jun 28 08:02:27 PM PDT 24 |
| Finished | Jun 28 08:07:00 PM PDT 24 |
| Peak memory | 606232 kb |
| Host | smart-22516ab8-1278-4566-aaf9-910087689887 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=rv_plic_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=828578841 -assert nopostproc +UVM_TESTNAME=c hip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n ull -cm_name 0.chip_sw_rv_plic_smoketest.828578841 |
| Directory | /workspace/0.chip_sw_rv_plic_smoketest/latest |
| Test location | /workspace/coverage/default/0.chip_sw_rv_timer_irq.1974005878 |
| Short name | T95 |
| Test name | |
| Test status | |
| Simulation time | 3407791186 ps |
| CPU time | 269.47 seconds |
| Started | Jun 28 08:08:29 PM PDT 24 |
| Finished | Jun 28 08:13:00 PM PDT 24 |
| Peak memory | 606272 kb |
| Host | smart-29cfda1f-7fba-4b0d-b32c-cc062368bb44 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=rv_timer_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1974005878 -assert nopostproc +UVM_TESTNAME =chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 0.chip_sw_rv_timer_irq.1974005878 |
| Directory | /workspace/0.chip_sw_rv_timer_irq/latest |
| Test location | /workspace/coverage/default/0.chip_sw_rv_timer_smoketest.1280975890 |
| Short name | T250 |
| Test name | |
| Test status | |
| Simulation time | 3114761012 ps |
| CPU time | 332.43 seconds |
| Started | Jun 28 08:03:36 PM PDT 24 |
| Finished | Jun 28 08:09:11 PM PDT 24 |
| Peak memory | 609188 kb |
| Host | smart-b833bc37-e919-4189-acf7-706ecac453e3 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=rv_timer_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1280975890 -assert nopostproc +UVM_TESTNAME =chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 0.chip_sw_rv_timer_smoketest.1280975890 |
| Directory | /workspace/0.chip_sw_rv_timer_smoketest/latest |
| Test location | /workspace/coverage/default/0.chip_sw_sensor_ctrl_status.1245820715 |
| Short name | T1209 |
| Test name | |
| Test status | |
| Simulation time | 2355115400 ps |
| CPU time | 171.31 seconds |
| Started | Jun 28 08:02:16 PM PDT 24 |
| Finished | Jun 28 08:05:09 PM PDT 24 |
| Peak memory | 608408 kb |
| Host | smart-a153c88b-33ce-4f57-9a6c-230218abb473 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=40_000_000 +sw_build_device=sim_dv +sw_images=sensor_ctrl_status_test:1:new_rules,test_rom:0 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1245820 715 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sensor_ctrl_status_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_sensor_ctrl_status.1245820715 |
| Directory | /workspace/0.chip_sw_sensor_ctrl_status/latest |
| Test location | /workspace/coverage/default/0.chip_sw_sleep_pin_retention.120444937 |
| Short name | T11 |
| Test name | |
| Test status | |
| Simulation time | 3182338460 ps |
| CPU time | 212.89 seconds |
| Started | Jun 28 08:03:36 PM PDT 24 |
| Finished | Jun 28 08:07:11 PM PDT 24 |
| Peak memory | 607104 kb |
| Host | smart-d45b62fa-e61a-49df-841a-0a0deecaf178 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=sleep_pin_retention_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=120444937 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sleep_pin_retention_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defa ult.vdb -cm_log /dev/null -cm_name 0.chip_sw_sleep_pin_retention.120444937 |
| Directory | /workspace/0.chip_sw_sleep_pin_retention/latest |
| Test location | /workspace/coverage/default/0.chip_sw_sleep_pwm_pulses.276698295 |
| Short name | T1014 |
| Test name | |
| Test status | |
| Simulation time | 8132153596 ps |
| CPU time | 1529.55 seconds |
| Started | Jun 28 08:06:38 PM PDT 24 |
| Finished | Jun 28 08:32:11 PM PDT 24 |
| Peak memory | 608348 kb |
| Host | smart-b606f25c-6c8e-4a2e-8a00-3de5c1e4f590 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=sleep_pwm_pulses_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=276698295 -assert nopostproc +UVM_TESTNA ME=chip_base_test +UVM_TEST_SEQ=chip_sw_pwm_pulses_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_ log /dev/null -cm_name 0.chip_sw_sleep_pwm_pulses.276698295 |
| Directory | /workspace/0.chip_sw_sleep_pwm_pulses/latest |
| Test location | /workspace/coverage/default/0.chip_sw_sleep_sram_ret_contents_no_scramble.2488084170 |
| Short name | T514 |
| Test name | |
| Test status | |
| Simulation time | 8634297932 ps |
| CPU time | 550.34 seconds |
| Started | Jun 28 08:04:31 PM PDT 24 |
| Finished | Jun 28 08:13:43 PM PDT 24 |
| Peak memory | 609260 kb |
| Host | smart-f025a059-75cc-4455-925f-1231f977a2ff |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=20_000_000 +en_scb_tl_err_chk=0 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=sram _ctrl_sleep_sram_ret_contents_no_scramble_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2488084170 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_S EQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_sl eep_sram_ret_contents_no_scramble.2488084170 |
| Directory | /workspace/0.chip_sw_sleep_sram_ret_contents_no_scramble/latest |
| Test location | /workspace/coverage/default/0.chip_sw_sleep_sram_ret_contents_scramble.3913921973 |
| Short name | T965 |
| Test name | |
| Test status | |
| Simulation time | 8747359804 ps |
| CPU time | 624.51 seconds |
| Started | Jun 28 08:01:45 PM PDT 24 |
| Finished | Jun 28 08:12:11 PM PDT 24 |
| Peak memory | 609264 kb |
| Host | smart-d5d38496-b825-4215-8637-99d0a780fc18 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=20_000_000 +en_scb_tl_err_chk=0 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=sram _ctrl_sleep_sram_ret_contents_scramble_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3913921973 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ= chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_sleep _sram_ret_contents_scramble.3913921973 |
| Directory | /workspace/0.chip_sw_sleep_sram_ret_contents_scramble/latest |
| Test location | /workspace/coverage/default/0.chip_sw_spi_device_pass_through.3312547105 |
| Short name | T25 |
| Test name | |
| Test status | |
| Simulation time | 7011852581 ps |
| CPU time | 893.63 seconds |
| Started | Jun 28 08:00:45 PM PDT 24 |
| Finished | Jun 28 08:15:41 PM PDT 24 |
| Peak memory | 624256 kb |
| Host | smart-806fbf99-0580-4b76-a5f7-85c0f3329534 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=spi_passthrough_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3312547105 -assert nopostproc +UVM_TESTNA ME=chip_base_test +UVM_TEST_SEQ=chip_sw_spi_passthrough_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_spi_device_pass_through.3312547105 |
| Directory | /workspace/0.chip_sw_spi_device_pass_through/latest |
| Test location | /workspace/coverage/default/0.chip_sw_spi_device_tpm.713163161 |
| Short name | T50 |
| Test name | |
| Test status | |
| Simulation time | 3250084878 ps |
| CPU time | 412.19 seconds |
| Started | Jun 28 07:59:51 PM PDT 24 |
| Finished | Jun 28 08:06:45 PM PDT 24 |
| Peak memory | 616556 kb |
| Host | smart-618ba542-dd79-478c-a8ee-0d7f47e47215 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=spi_device_tpm_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=713163161 -assert nopostproc +UVM_TE STNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_spi_device_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 0.chip_sw_spi_device_tpm.713163161 |
| Directory | /workspace/0.chip_sw_spi_device_tpm/latest |
| Test location | /workspace/coverage/default/0.chip_sw_sram_ctrl_execution_main.3766784375 |
| Short name | T305 |
| Test name | |
| Test status | |
| Simulation time | 7857805138 ps |
| CPU time | 960.07 seconds |
| Started | Jun 28 08:04:13 PM PDT 24 |
| Finished | Jun 28 08:20:15 PM PDT 24 |
| Peak memory | 609156 kb |
| Host | smart-2b79d58f-3d78-4f3d-b249-26ec8165dcfc |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=sram_ctrl_execution_main_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3766784375 -assert nopostproc +U VM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sram_ctrl_execution_main_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co verage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_sram_ctrl_execution_main.3766784375 |
| Directory | /workspace/0.chip_sw_sram_ctrl_execution_main/latest |
| Test location | /workspace/coverage/default/0.chip_sw_sram_ctrl_scrambled_access.2157747241 |
| Short name | T614 |
| Test name | |
| Test status | |
| Simulation time | 4192831922 ps |
| CPU time | 612.79 seconds |
| Started | Jun 28 08:01:50 PM PDT 24 |
| Finished | Jun 28 08:12:04 PM PDT 24 |
| Peak memory | 607300 kb |
| Host | smart-8fbce720-698e-430c-8106-92513906bd49 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=12_000_000 +en_scb_tl_err_chk=0 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=sram _ctrl_scrambled_access_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2157747241 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sram_ctr l_scrambled_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw _sram_ctrl_scrambled_access.2157747241 |
| Directory | /workspace/0.chip_sw_sram_ctrl_scrambled_access/latest |
| Test location | /workspace/coverage/default/0.chip_sw_sram_ctrl_scrambled_access_jitter_en.2665170656 |
| Short name | T1281 |
| Test name | |
| Test status | |
| Simulation time | 3941506938 ps |
| CPU time | 414.36 seconds |
| Started | Jun 28 08:01:57 PM PDT 24 |
| Finished | Jun 28 08:08:53 PM PDT 24 |
| Peak memory | 608528 kb |
| Host | smart-c4fc7212-faf2-4ad8-bf1e-a8eb433ca92d |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=12_000_000 +bypass_alert_ready_to_end_check=1 +en_jitter=1 +en_scb_tl_err_chk=0 +sw_build_device=sim_dv +s w_images=sram_ctrl_scrambled_access_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2665170656 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chi p_sw_sram_ctrl_scrambled_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n ame 0.chip_sw_sram_ctrl_scrambled_access_jitter_en.2665170656 |
| Directory | /workspace/0.chip_sw_sram_ctrl_scrambled_access_jitter_en/latest |
| Test location | /workspace/coverage/default/0.chip_sw_sram_ctrl_smoketest.4031599981 |
| Short name | T1036 |
| Test name | |
| Test status | |
| Simulation time | 3471559076 ps |
| CPU time | 287.38 seconds |
| Started | Jun 28 08:03:11 PM PDT 24 |
| Finished | Jun 28 08:08:00 PM PDT 24 |
| Peak memory | 609152 kb |
| Host | smart-66d05693-d58b-4d8f-bf5e-8214921e42a4 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=sram_ctrl_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4031599981 -assert nopostproc +UVM_TESTNAM E=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 0.chip_sw_sram_ctrl_smoketest.4031599981 |
| Directory | /workspace/0.chip_sw_sram_ctrl_smoketest/latest |
| Test location | /workspace/coverage/default/0.chip_sw_sysrst_ctrl_ec_rst_l.2220509508 |
| Short name | T1133 |
| Test name | |
| Test status | |
| Simulation time | 20851509800 ps |
| CPU time | 3423.5 seconds |
| Started | Jun 28 08:05:59 PM PDT 24 |
| Finished | Jun 28 09:03:04 PM PDT 24 |
| Peak memory | 609176 kb |
| Host | smart-6b4769a0-e4f9-4d85-ab6f-293ef29f62e1 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=sysrst_ctrl_ec_rst_l_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2220509508 -assert nopostproc +UVM_T ESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_ec_rst_l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/d efault.vdb -cm_log /dev/null -cm_name 0.chip_sw_sysrst_ctrl_ec_rst_l.2220509508 |
| Directory | /workspace/0.chip_sw_sysrst_ctrl_ec_rst_l/latest |
| Test location | /workspace/coverage/default/0.chip_sw_sysrst_ctrl_in_irq.4049793181 |
| Short name | T200 |
| Test name | |
| Test status | |
| Simulation time | 5062948404 ps |
| CPU time | 617.21 seconds |
| Started | Jun 28 08:05:52 PM PDT 24 |
| Finished | Jun 28 08:16:13 PM PDT 24 |
| Peak memory | 612484 kb |
| Host | smart-fcc02f1a-2050-4f28-b424-2ecad87399e9 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=sysrst_ctrl_in_irq_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4049793181 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_in_irq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau lt.vdb -cm_log /dev/null -cm_name 0.chip_sw_sysrst_ctrl_in_irq.4049793181 |
| Directory | /workspace/0.chip_sw_sysrst_ctrl_in_irq/latest |
| Test location | /workspace/coverage/default/0.chip_sw_sysrst_ctrl_inputs.699913836 |
| Short name | T179 |
| Test name | |
| Test status | |
| Simulation time | 2955165126 ps |
| CPU time | 232.93 seconds |
| Started | Jun 28 08:04:06 PM PDT 24 |
| Finished | Jun 28 08:08:01 PM PDT 24 |
| Peak memory | 610856 kb |
| Host | smart-c600cadb-03b4-460a-98d5-d4533d160af4 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=sysrst_ctrl_inputs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=699913836 -assert nopostproc +UVM_TEST NAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_inputs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul t.vdb -cm_log /dev/null -cm_name 0.chip_sw_sysrst_ctrl_inputs.699913836 |
| Directory | /workspace/0.chip_sw_sysrst_ctrl_inputs/latest |
| Test location | /workspace/coverage/default/0.chip_sw_sysrst_ctrl_outputs.3939270584 |
| Short name | T87 |
| Test name | |
| Test status | |
| Simulation time | 3289323588 ps |
| CPU time | 350.51 seconds |
| Started | Jun 28 08:06:55 PM PDT 24 |
| Finished | Jun 28 08:12:47 PM PDT 24 |
| Peak memory | 607040 kb |
| Host | smart-9eb3aebc-6d32-43b0-bd24-521ae80a568e |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=sysrst_ctrl_outputs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3939270584 -assert nopostproc +UVM_TE STNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_outputs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def ault.vdb -cm_log /dev/null -cm_name 0.chip_sw_sysrst_ctrl_outputs.3939270584 |
| Directory | /workspace/0.chip_sw_sysrst_ctrl_outputs/latest |
| Test location | /workspace/coverage/default/0.chip_sw_sysrst_ctrl_reset.2895257351 |
| Short name | T202 |
| Test name | |
| Test status | |
| Simulation time | 24810342992 ps |
| CPU time | 1928.38 seconds |
| Started | Jun 28 08:06:30 PM PDT 24 |
| Finished | Jun 28 08:38:40 PM PDT 24 |
| Peak memory | 612928 kb |
| Host | smart-741d6674-fa7c-4e58-b704-2c7b2474b0dd |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=36_000_000 +sw_build_device=sim_dv +sw_images=sysrst_ctrl_reset_test:1:new_rules,test_rom:0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28952573 51 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_sysrst_ctrl_reset.2895257351 |
| Directory | /workspace/0.chip_sw_sysrst_ctrl_reset/latest |
| Test location | /workspace/coverage/default/0.chip_sw_sysrst_ctrl_ulp_z3_wakeup.2180243083 |
| Short name | T47 |
| Test name | |
| Test status | |
| Simulation time | 6142919128 ps |
| CPU time | 418.93 seconds |
| Started | Jun 28 08:08:07 PM PDT 24 |
| Finished | Jun 28 08:15:07 PM PDT 24 |
| Peak memory | 608284 kb |
| Host | smart-0f9cb086-630d-4a81-885c-5afa1ee31006 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=sysrst_ctrl_ulp_z3_wakeup_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2180243083 -assert nopostproc + UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_ulp_z3_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/ coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_sysrst_ctrl_ulp_z3_wakeup.2180243083 |
| Directory | /workspace/0.chip_sw_sysrst_ctrl_ulp_z3_wakeup/latest |
| Test location | /workspace/coverage/default/0.chip_sw_uart_rand_baudrate.1001166756 |
| Short name | T1052 |
| Test name | |
| Test status | |
| Simulation time | 3814906968 ps |
| CPU time | 529.57 seconds |
| Started | Jun 28 08:04:10 PM PDT 24 |
| Finished | Jun 28 08:13:01 PM PDT 24 |
| Peak memory | 618588 kb |
| Host | smart-ad4eb34b-c0f3-4daf-ba31-264e902eaf07 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=1001166756 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_uart_rand_baudrate.1001166756 |
| Directory | /workspace/0.chip_sw_uart_rand_baudrate/latest |
| Test location | /workspace/coverage/default/0.chip_sw_uart_smoketest.297442420 |
| Short name | T1138 |
| Test name | |
| Test status | |
| Simulation time | 3343277000 ps |
| CPU time | 234.35 seconds |
| Started | Jun 28 08:03:43 PM PDT 24 |
| Finished | Jun 28 08:07:38 PM PDT 24 |
| Peak memory | 610680 kb |
| Host | smart-d3070e40-e4a4-4beb-9ca2-73ef002e73be |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=uart_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=297442420 -assert nopostproc +UVM_TESTNAME=chip _base_test +UVM_TEST_SEQ=chip_sw_uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 0.chip_sw_uart_smoketest.297442420 |
| Directory | /workspace/0.chip_sw_uart_smoketest/latest |
| Test location | /workspace/coverage/default/0.chip_sw_uart_tx_rx.1433766415 |
| Short name | T1226 |
| Test name | |
| Test status | |
| Simulation time | 4035742308 ps |
| CPU time | 590.89 seconds |
| Started | Jun 28 07:59:16 PM PDT 24 |
| Finished | Jun 28 08:09:10 PM PDT 24 |
| Peak memory | 615872 kb |
| Host | smart-33558dbc-eeec-43fb-97f3-7e21b449bce5 |
| User | root |
| Command | /workspace/default/simv +uart_idx=0 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1433766415 -a ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_uart_tx_rx.1433766415 |
| Directory | /workspace/0.chip_sw_uart_tx_rx/latest |
| Test location | /workspace/coverage/default/0.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.1423043848 |
| Short name | T884 |
| Test name | |
| Test status | |
| Simulation time | 4296470896 ps |
| CPU time | 578.14 seconds |
| Started | Jun 28 07:59:22 PM PDT 24 |
| Finished | Jun 28 08:09:02 PM PDT 24 |
| Peak memory | 618192 kb |
| Host | smart-3a0eddaa-b7af-4be7-afea-f025d707d7fa |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +chip_clock_source=ChipClockSourceExternal48Mhz +sw_build_device=sim_dv +s w_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1423043848 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_b audrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_uart_tx_rx _alt_clk_freq_low_speed.1423043848 |
| Directory | /workspace/0.chip_sw_uart_tx_rx_alt_clk_freq_low_speed/latest |
| Test location | /workspace/coverage/default/0.chip_sw_uart_tx_rx_bootstrap.928782164 |
| Short name | T1305 |
| Test name | |
| Test status | |
| Simulation time | 78275369720 ps |
| CPU time | 13371.1 seconds |
| Started | Jun 28 07:58:55 PM PDT 24 |
| Finished | Jun 28 11:41:49 PM PDT 24 |
| Peak memory | 633444 kb |
| Host | smart-e0e001c6-d544-45d7-a635-227f47b19357 |
| User | root |
| Command | /workspace/default/simv +use_spi_load_bootstrap=1 +calibrate_usb_clk=1 +test_timeout_ns=160_000_000 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test :1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=928782164 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_uart_tx_rx_bootstrap.928782164 |
| Directory | /workspace/0.chip_sw_uart_tx_rx_bootstrap/latest |
| Test location | /workspace/coverage/default/0.chip_sw_uart_tx_rx_idx1.2288454334 |
| Short name | T1156 |
| Test name | |
| Test status | |
| Simulation time | 4149168040 ps |
| CPU time | 572.11 seconds |
| Started | Jun 28 07:59:03 PM PDT 24 |
| Finished | Jun 28 08:08:36 PM PDT 24 |
| Peak memory | 615888 kb |
| Host | smart-9e064c2d-422b-417c-a0b7-ca768f6421df |
| User | root |
| Command | /workspace/default/simv +uart_idx=1 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2288454334 -a ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_uart_tx_rx_idx1.2288454334 |
| Directory | /workspace/0.chip_sw_uart_tx_rx_idx1/latest |
| Test location | /workspace/coverage/default/0.chip_sw_uart_tx_rx_idx2.2932414278 |
| Short name | T874 |
| Test name | |
| Test status | |
| Simulation time | 3850649694 ps |
| CPU time | 690.92 seconds |
| Started | Jun 28 08:06:02 PM PDT 24 |
| Finished | Jun 28 08:17:35 PM PDT 24 |
| Peak memory | 615872 kb |
| Host | smart-3cdaea2e-c4cb-486f-8adc-2b267202815f |
| User | root |
| Command | /workspace/default/simv +uart_idx=2 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2932414278 -a ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_uart_tx_rx_idx2.2932414278 |
| Directory | /workspace/0.chip_sw_uart_tx_rx_idx2/latest |
| Test location | /workspace/coverage/default/0.chip_sw_uart_tx_rx_idx3.3051713029 |
| Short name | T1255 |
| Test name | |
| Test status | |
| Simulation time | 3871900824 ps |
| CPU time | 644.43 seconds |
| Started | Jun 28 08:04:10 PM PDT 24 |
| Finished | Jun 28 08:14:56 PM PDT 24 |
| Peak memory | 615904 kb |
| Host | smart-755f2587-2fd8-4b96-89ad-acca9c31f21b |
| User | root |
| Command | /workspace/default/simv +uart_idx=3 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3051713029 -a ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_uart_tx_rx_idx3.3051713029 |
| Directory | /workspace/0.chip_sw_uart_tx_rx_idx3/latest |
| Test location | /workspace/coverage/default/0.chip_sw_usb_ast_clk_calib.2196181059 |
| Short name | T405 |
| Test name | |
| Test status | |
| Simulation time | 3252651028 ps |
| CPU time | 364.27 seconds |
| Started | Jun 28 08:02:51 PM PDT 24 |
| Finished | Jun 28 08:08:57 PM PDT 24 |
| Peak memory | 607908 kb |
| Host | smart-e00fc850-06f5-44be-b3e5-43114ef1d539 |
| User | root |
| Command | /workspace/default/simv +usb_max_drift=1 +usb_fast_sof=1 +sw_build_device=sim_dv +sw_images=ast_usb_clk_calib:1:new_rules,test_rom:0 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2196181059 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_usb_ast_clk_calib_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_usb_ast_clk_calib.2196181059 |
| Directory | /workspace/0.chip_sw_usb_ast_clk_calib/latest |
| Test location | /workspace/coverage/default/0.chip_sw_usbdev_dpi.3427462482 |
| Short name | T142 |
| Test name | |
| Test status | |
| Simulation time | 12377386242 ps |
| CPU time | 3091.83 seconds |
| Started | Jun 28 07:59:51 PM PDT 24 |
| Finished | Jun 28 08:51:25 PM PDT 24 |
| Peak memory | 609172 kb |
| Host | smart-3dd615a2-b541-461d-8405-67a052dd3a9e |
| User | root |
| Command | /workspace/default/simv +uart_idx=0 +calibrate_usb_clk=1 +sw_test_timeout_ns=30_000_000 +sw_build_device=sim_dv +sw_images=usbdev_test:1:new_rules,tes t_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +nt b_random_seed=3427462482 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_usbdev_dpi_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_usbdev_dpi.3427462482 |
| Directory | /workspace/0.chip_sw_usbdev_dpi/latest |
| Test location | /workspace/coverage/default/0.chip_sw_usbdev_pincfg.4243842022 |
| Short name | T71 |
| Test name | |
| Test status | |
| Simulation time | 31821483092 ps |
| CPU time | 7695.3 seconds |
| Started | Jun 28 08:00:24 PM PDT 24 |
| Finished | Jun 28 10:08:42 PM PDT 24 |
| Peak memory | 608096 kb |
| Host | smart-af69b400-bad2-4c70-ae7f-514dc7eadbd4 |
| User | root |
| Command | /workspace/default/simv +uart_idx=0 +calibrate_usb_clk=1 +sw_test_timeout_ns=100_000_000 +sw_build_device=sim_dv +sw_images=usbdev_pincfg_test:1:new_r ules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim .tcl +ntb_random_seed=4243842022 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_usbdev_dpi_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_usbdev_pincfg.4243842022 |
| Directory | /workspace/0.chip_sw_usbdev_pincfg/latest |
| Test location | /workspace/coverage/default/0.chip_sw_usbdev_pullup.1483032765 |
| Short name | T69 |
| Test name | |
| Test status | |
| Simulation time | 3490214464 ps |
| CPU time | 301.85 seconds |
| Started | Jun 28 08:03:07 PM PDT 24 |
| Finished | Jun 28 08:08:11 PM PDT 24 |
| Peak memory | 609144 kb |
| Host | smart-181b472d-4ffe-4647-8b93-5c4997b2beca |
| User | root |
| Command | /workspace/default/simv +uart_idx=0 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=usbdev_pullup_test:1:new_rules,test_rom:0 +cdc_instrumenta tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1483032765 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_usbdev_dpi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work space/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_usbdev_pullup.1483032765 |
| Directory | /workspace/0.chip_sw_usbdev_pullup/latest |
| Test location | /workspace/coverage/default/0.chip_sw_usbdev_setuprx.481498783 |
| Short name | T30 |
| Test name | |
| Test status | |
| Simulation time | 3955487240 ps |
| CPU time | 624.38 seconds |
| Started | Jun 28 08:02:50 PM PDT 24 |
| Finished | Jun 28 08:13:16 PM PDT 24 |
| Peak memory | 609096 kb |
| Host | smart-2c48f34a-18ea-4c23-861e-1ef98e02d527 |
| User | root |
| Command | /workspace/default/simv +uart_idx=0 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=usbdev_setuprx_test:1:new_rules,test_rom:0 +cdc_instrument ation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=481498783 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_usbdev_dpi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work space/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_usbdev_setuprx.481498783 |
| Directory | /workspace/0.chip_sw_usbdev_setuprx/latest |
| Test location | /workspace/coverage/default/0.chip_sw_usbdev_stream.2511944633 |
| Short name | T34 |
| Test name | |
| Test status | |
| Simulation time | 18302150334 ps |
| CPU time | 4287.66 seconds |
| Started | Jun 28 08:01:04 PM PDT 24 |
| Finished | Jun 28 09:12:35 PM PDT 24 |
| Peak memory | 609168 kb |
| Host | smart-f05e92fb-6b05-4951-8d45-1b86ea26c07b |
| User | root |
| Command | /workspace/default/simv +uart_idx=0 +calibrate_usb_clk=1 +sw_test_timeout_ns=60_000_000 +sw_build_device=sim_dv +sw_images=usbdev_stream_test:1:new_ru les,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim. tcl +ntb_random_seed=2511944633 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_usbdev_stream_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_usbdev_stream.2511944633 |
| Directory | /workspace/0.chip_sw_usbdev_stream/latest |
| Test location | /workspace/coverage/default/0.chip_sw_usbdev_vbus.4205145849 |
| Short name | T1083 |
| Test name | |
| Test status | |
| Simulation time | 3261567792 ps |
| CPU time | 311.51 seconds |
| Started | Jun 28 08:02:47 PM PDT 24 |
| Finished | Jun 28 08:08:01 PM PDT 24 |
| Peak memory | 609144 kb |
| Host | smart-91be9b13-27d6-4159-97c8-bb1b5fbaea5d |
| User | root |
| Command | /workspace/default/simv +uart_idx=0 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=usbdev_vbus_test:1:new_rules,test_rom:0 +cdc_instrumentati on_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4205145849 - assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_usbdev_dpi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_usbdev_vbus.4205145849 |
| Directory | /workspace/0.chip_sw_usbdev_vbus/latest |
| Test location | /workspace/coverage/default/0.chip_tap_straps_prod.1376750408 |
| Short name | T1121 |
| Test name | |
| Test status | |
| Simulation time | 3336820939 ps |
| CPU time | 175.75 seconds |
| Started | Jun 28 08:01:00 PM PDT 24 |
| Finished | Jun 28 08:03:58 PM PDT 24 |
| Peak memory | 618488 kb |
| Host | smart-5d6cc8bb-45eb-44a1-b6f0-78bd0f43465a |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStProd +create_jtag_riscv_map=1 +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:test_in_rom :new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1376750408 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_tap_straps_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_tap_straps_prod.1376750408 |
| Directory | /workspace/0.chip_tap_straps_prod/latest |
| Test location | /workspace/coverage/default/0.chip_tap_straps_rma.2217734018 |
| Short name | T1270 |
| Test name | |
| Test status | |
| Simulation time | 7149827059 ps |
| CPU time | 796.68 seconds |
| Started | Jun 28 08:05:12 PM PDT 24 |
| Finished | Jun 28 08:18:30 PM PDT 24 |
| Peak memory | 619980 kb |
| Host | smart-8df3e5da-a53b-4ec5-af31-b6a000277370 |
| User | root |
| Command | /workspace/default/simv +create_jtag_riscv_map=1 +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:test_in_rom:new_rules +cdc_instrumentation _enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2217734018 -as sert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_tap_straps_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/c overage/default.vdb -cm_log /dev/null -cm_name 0.chip_tap_straps_rma.2217734018 |
| Directory | /workspace/0.chip_tap_straps_rma/latest |
| Test location | /workspace/coverage/default/0.chip_tap_straps_testunlock0.1533474401 |
| Short name | T63 |
| Test name | |
| Test status | |
| Simulation time | 2326217031 ps |
| CPU time | 127.86 seconds |
| Started | Jun 28 08:01:13 PM PDT 24 |
| Finished | Jun 28 08:03:24 PM PDT 24 |
| Peak memory | 620064 kb |
| Host | smart-4086a141-20d6-4e7b-b71e-898e578ff4a0 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStTestUnlocked0 +create_jtag_riscv_map=1 +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:te st_in_rom:new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1533474401 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_tap_straps_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_tap_straps_testunlock0.1533474401 |
| Directory | /workspace/0.chip_tap_straps_testunlock0/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_asm_init_dev.3166908422 |
| Short name | T905 |
| Test name | |
| Test status | |
| Simulation time | 15017012295 ps |
| CPU time | 4915.07 seconds |
| Started | Jun 28 08:06:04 PM PDT 24 |
| Finished | Jun 28 09:28:00 PM PDT 24 |
| Peak memory | 607892 kb |
| Host | smart-b4ff3e4a-78e3-44d9-bab0-5d3dbf55a3f3 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeCustom +sw_test_timeout_ns=20000000 +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_prod _key_0:1:ot_flash_binary,otp_img_e2e_bootstrap_entry_dev:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3166908422 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_S EQ=chip_sw_rom_e2e_asm_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_asm_init_dev.3166908422 |
| Directory | /workspace/0.rom_e2e_asm_init_dev/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_asm_init_prod.1217911708 |
| Short name | T883 |
| Test name | |
| Test status | |
| Simulation time | 15808315960 ps |
| CPU time | 4487.62 seconds |
| Started | Jun 28 08:05:49 PM PDT 24 |
| Finished | Jun 28 09:20:38 PM PDT 24 |
| Peak memory | 607888 kb |
| Host | smart-abdab4f5-c0f2-439b-a59e-474ff849638f |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeCustom +sw_test_timeout_ns=20000000 +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_prod _key_0:1:ot_flash_binary,otp_img_e2e_bootstrap_entry_prod:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1217911708 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_ SEQ=chip_sw_rom_e2e_asm_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_asm_init_prod.1217911708 |
| Directory | /workspace/0.rom_e2e_asm_init_prod/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_asm_init_rma.3119599089 |
| Short name | T1218 |
| Test name | |
| Test status | |
| Simulation time | 14911942578 ps |
| CPU time | 4044.99 seconds |
| Started | Jun 28 08:06:31 PM PDT 24 |
| Finished | Jun 28 09:13:58 PM PDT 24 |
| Peak memory | 607264 kb |
| Host | smart-01027ce9-eb3f-4d01-ae68-9eb6afa916aa |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeCustom +sw_test_timeout_ns=20000000 +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_prod _key_0:1:ot_flash_binary,otp_img_e2e_bootstrap_entry_rma:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3119599089 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_S EQ=chip_sw_rom_e2e_asm_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_asm_init_rma.3119599089 |
| Directory | /workspace/0.rom_e2e_asm_init_rma/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_asm_init_test_unlocked0.1697399930 |
| Short name | T53 |
| Test name | |
| Test status | |
| Simulation time | 11608357591 ps |
| CPU time | 3645.43 seconds |
| Started | Jun 28 08:07:06 PM PDT 24 |
| Finished | Jun 28 09:07:52 PM PDT 24 |
| Peak memory | 607524 kb |
| Host | smart-2d81b0b0-461d-4084-9f5b-a815b06cd1ad |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeCustom +sw_test_timeout_ns=410_000_000 +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_p rod_key_0:1:ot_flash_binary,otp_img_e2e_bootstrap_entry_test_unlocked0:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY =UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1697399930 -assert nopostproc +UVM_TESTNAME=chip_base_te st +UVM_TEST_SEQ=chip_sw_rom_e2e_asm_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/ null -cm_name 0.rom_e2e_asm_init_test_unlocked0.1697399930 |
| Directory | /workspace/0.rom_e2e_asm_init_test_unlocked0/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_bad_b_good_prod.3162433270 |
| Short name | T382 |
| Test name | |
| Test status | |
| Simulation time | 24418178460 ps |
| CPU time | 6426.53 seconds |
| Started | Jun 28 08:14:27 PM PDT 24 |
| Finished | Jun 28 10:01:35 PM PDT 24 |
| Peak memory | 608368 kb |
| Host | smart-385c1e98-651f-4b39-abf6-e326c2a97b4d |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_corrupted:1: ot_flash_binary:signed:fake_ecdsa_prod_key_0,empty_test_slot_b_fake_ecdsa_prod_key_0:2:ot_flash_binary,otp_img_boot_policy_valid_prod:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=3162433270 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_boot_policy_valid_a_bad_b_good_prod.3162433270 |
| Directory | /workspace/0.rom_e2e_boot_policy_valid_a_bad_b_good_prod/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_bad_b_good_prod_end.2817986084 |
| Short name | T270 |
| Test name | |
| Test status | |
| Simulation time | 24248851940 ps |
| CPU time | 6877.34 seconds |
| Started | Jun 28 08:11:01 PM PDT 24 |
| Finished | Jun 28 10:05:40 PM PDT 24 |
| Peak memory | 608452 kb |
| Host | smart-e516911c-6feb-4e19-8e55-48c9157abf4e |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_corrupted:1: ot_flash_binary:signed:fake_ecdsa_prod_key_0,empty_test_slot_b_fake_ecdsa_prod_key_0:2:ot_flash_binary,otp_img_boot_policy_valid_prod_end:4,mask_r om:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r andom_seed=2817986084 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_boot_policy_valid_a_bad_b_good_prod_end.2817986084 |
| Directory | /workspace/0.rom_e2e_boot_policy_valid_a_bad_b_good_prod_end/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_bad_b_good_rma.3342362669 |
| Short name | T383 |
| Test name | |
| Test status | |
| Simulation time | 23342299916 ps |
| CPU time | 7219.27 seconds |
| Started | Jun 28 08:14:27 PM PDT 24 |
| Finished | Jun 28 10:14:48 PM PDT 24 |
| Peak memory | 608360 kb |
| Host | smart-8bb94dbc-d9b2-48ad-93ec-9b2960021a9c |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_corrupted:1: ot_flash_binary:signed:fake_ecdsa_prod_key_0,empty_test_slot_b_fake_ecdsa_prod_key_0:2:ot_flash_binary,otp_img_boot_policy_valid_rma:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=3342362669 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_boot_policy_valid_a_bad_b_good_rma.3342362669 |
| Directory | /workspace/0.rom_e2e_boot_policy_valid_a_bad_b_good_rma/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0.3984446509 |
| Short name | T1158 |
| Test name | |
| Test status | |
| Simulation time | 17870432082 ps |
| CPU time | 5279.31 seconds |
| Started | Jun 28 08:09:06 PM PDT 24 |
| Finished | Jun 28 09:37:07 PM PDT 24 |
| Peak memory | 608360 kb |
| Host | smart-a33fb3de-fa95-459a-9c6b-5abdd89d5d0a |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=410_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_corrupted:1: ot_flash_binary:signed:fake_ecdsa_prod_key_0,empty_test_slot_b_fake_ecdsa_prod_key_0:2:ot_flash_binary,otp_img_boot_policy_valid_test_unlocked0:4, mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3984446509 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0.3984446509 |
| Directory | /workspace/0.rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_bad_dev.1658308599 |
| Short name | T920 |
| Test name | |
| Test status | |
| Simulation time | 15171282362 ps |
| CPU time | 4663.43 seconds |
| Started | Jun 28 08:07:42 PM PDT 24 |
| Finished | Jun 28 09:25:27 PM PDT 24 |
| Peak memory | 608328 kb |
| Host | smart-29477d5d-95cc-421a-b925-5e966281ab6c |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_p rod_key_0:1:ot_flash_binary,empty_test_slot_b_corrupted:2:ot_flash_binary:signed:fake_ecdsa_prod_key_0,otp_img_boot_policy_valid_dev:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=1658308599 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_boot_policy_valid_a_good_b_bad_dev.1658308599 |
| Directory | /workspace/0.rom_e2e_boot_policy_valid_a_good_b_bad_dev/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_bad_prod.566767324 |
| Short name | T953 |
| Test name | |
| Test status | |
| Simulation time | 16025980344 ps |
| CPU time | 3947.73 seconds |
| Started | Jun 28 08:09:26 PM PDT 24 |
| Finished | Jun 28 09:15:16 PM PDT 24 |
| Peak memory | 608348 kb |
| Host | smart-2f9cd686-92f8-4817-bcac-297e9aa97dcf |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_p rod_key_0:1:ot_flash_binary,empty_test_slot_b_corrupted:2:ot_flash_binary:signed:fake_ecdsa_prod_key_0,otp_img_boot_policy_valid_prod:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=566767324 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_boot_policy_valid_a_good_b_bad_prod.566767324 |
| Directory | /workspace/0.rom_e2e_boot_policy_valid_a_good_b_bad_prod/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_bad_prod_end.2457152403 |
| Short name | T261 |
| Test name | |
| Test status | |
| Simulation time | 15712940404 ps |
| CPU time | 4223.88 seconds |
| Started | Jun 28 08:08:19 PM PDT 24 |
| Finished | Jun 28 09:18:44 PM PDT 24 |
| Peak memory | 607324 kb |
| Host | smart-28e2bf2a-f18c-41a1-927a-4a8b18dafa4a |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_p rod_key_0:1:ot_flash_binary,empty_test_slot_b_corrupted:2:ot_flash_binary:signed:fake_ecdsa_prod_key_0,otp_img_boot_policy_valid_prod_end:4,mask_r om:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r andom_seed=2457152403 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_boot_policy_valid_a_good_b_bad_prod_end.2457152403 |
| Directory | /workspace/0.rom_e2e_boot_policy_valid_a_good_b_bad_prod_end/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_bad_rma.1906567768 |
| Short name | T1190 |
| Test name | |
| Test status | |
| Simulation time | 14714948120 ps |
| CPU time | 3989.45 seconds |
| Started | Jun 28 08:08:38 PM PDT 24 |
| Finished | Jun 28 09:15:09 PM PDT 24 |
| Peak memory | 608140 kb |
| Host | smart-6c3e63b4-60b3-434f-abe5-224251cb779b |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_p rod_key_0:1:ot_flash_binary,empty_test_slot_b_corrupted:2:ot_flash_binary:signed:fake_ecdsa_prod_key_0,otp_img_boot_policy_valid_rma:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=1906567768 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_boot_policy_valid_a_good_b_bad_rma.1906567768 |
| Directory | /workspace/0.rom_e2e_boot_policy_valid_a_good_b_bad_rma/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0.1516286109 |
| Short name | T1081 |
| Test name | |
| Test status | |
| Simulation time | 11069515792 ps |
| CPU time | 3856.96 seconds |
| Started | Jun 28 08:08:10 PM PDT 24 |
| Finished | Jun 28 09:12:28 PM PDT 24 |
| Peak memory | 608332 kb |
| Host | smart-6d3730b1-dc78-4b52-9bf9-d7e3dbe5fbbd |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=410_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_p rod_key_0:1:ot_flash_binary,empty_test_slot_b_corrupted:2:ot_flash_binary:signed:fake_ecdsa_prod_key_0,otp_img_boot_policy_valid_test_unlocked0:4, mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1516286109 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0.1516286109 |
| Directory | /workspace/0.rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_good_dev.3574142547 |
| Short name | T1263 |
| Test name | |
| Test status | |
| Simulation time | 15406784680 ps |
| CPU time | 5192.7 seconds |
| Started | Jun 28 08:08:14 PM PDT 24 |
| Finished | Jun 28 09:34:48 PM PDT 24 |
| Peak memory | 608056 kb |
| Host | smart-fe345b3d-fbc2-46af-ab6c-1459718a85fc |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_p rod_key_0:1:ot_flash_binary,empty_test_slot_b_fake_ecdsa_prod_key_0:2:ot_flash_binary,otp_img_boot_policy_valid_dev:4,mask_rom:0 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3574142547 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/c overage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_boot_policy_valid_a_good_b_good_dev.3574142547 |
| Directory | /workspace/0.rom_e2e_boot_policy_valid_a_good_b_good_dev/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_good_prod.3176492939 |
| Short name | T918 |
| Test name | |
| Test status | |
| Simulation time | 14988812932 ps |
| CPU time | 3948.81 seconds |
| Started | Jun 28 08:11:46 PM PDT 24 |
| Finished | Jun 28 09:17:43 PM PDT 24 |
| Peak memory | 608292 kb |
| Host | smart-ab6e72ea-0bc9-4fc5-8887-bb6a15e5b0d4 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_p rod_key_0:1:ot_flash_binary,empty_test_slot_b_fake_ecdsa_prod_key_0:2:ot_flash_binary,otp_img_boot_policy_valid_prod:4,mask_rom:0 +cdc_instrumenta tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3176492939 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/ coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_boot_policy_valid_a_good_b_good_prod.3176492939 |
| Directory | /workspace/0.rom_e2e_boot_policy_valid_a_good_b_good_prod/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_good_prod_end.2553749177 |
| Short name | T1252 |
| Test name | |
| Test status | |
| Simulation time | 15498375640 ps |
| CPU time | 4097.24 seconds |
| Started | Jun 28 08:09:24 PM PDT 24 |
| Finished | Jun 28 09:17:44 PM PDT 24 |
| Peak memory | 608100 kb |
| Host | smart-74b9c0b4-ed5a-4c1e-871c-ad44e366ca60 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_p rod_key_0:1:ot_flash_binary,empty_test_slot_b_fake_ecdsa_prod_key_0:2:ot_flash_binary,otp_img_boot_policy_valid_prod_end:4,mask_rom:0 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=255374 9177 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_boot_policy_valid_a_good_b_good_prod_end.2553749177 |
| Directory | /workspace/0.rom_e2e_boot_policy_valid_a_good_b_good_prod_end/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_good_rma.2244340218 |
| Short name | T421 |
| Test name | |
| Test status | |
| Simulation time | 14497661000 ps |
| CPU time | 4010.16 seconds |
| Started | Jun 28 08:12:03 PM PDT 24 |
| Finished | Jun 28 09:18:55 PM PDT 24 |
| Peak memory | 608276 kb |
| Host | smart-c9a0ff58-7774-4951-9341-02e971739be0 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_p rod_key_0:1:ot_flash_binary,empty_test_slot_b_fake_ecdsa_prod_key_0:2:ot_flash_binary,otp_img_boot_policy_valid_rma:4,mask_rom:0 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2244340218 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/c overage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_boot_policy_valid_a_good_b_good_rma.2244340218 |
| Directory | /workspace/0.rom_e2e_boot_policy_valid_a_good_b_good_rma/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0.1882292226 |
| Short name | T1303 |
| Test name | |
| Test status | |
| Simulation time | 11178785326 ps |
| CPU time | 3474.9 seconds |
| Started | Jun 28 08:11:29 PM PDT 24 |
| Finished | Jun 28 09:09:26 PM PDT 24 |
| Peak memory | 608280 kb |
| Host | smart-87f1f4dd-af32-4c93-9642-760bb3e97739 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=410_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_p rod_key_0:1:ot_flash_binary,empty_test_slot_b_fake_ecdsa_prod_key_0:2:ot_flash_binary,otp_img_boot_policy_valid_test_unlocked0:4,mask_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 1882292226 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0.1882292226 |
| Directory | /workspace/0.rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_jtag_inject_dev.3293593424 |
| Short name | T1025 |
| Test name | |
| Test status | |
| Simulation time | 32094346509 ps |
| CPU time | 2849.09 seconds |
| Started | Jun 28 08:07:37 PM PDT 24 |
| Finished | Jun 28 08:55:08 PM PDT 24 |
| Peak memory | 618672 kb |
| Host | smart-42d914a6-12f3-4dfc-8d87-b769c6b19d5c |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=40_000_000 +use_jtag_dmi=1 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=img_dev_exec_di sabled:4,sram_program:5,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3293593424 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_e2e_jtag_inject_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_jtag_inject_dev.3293593424 |
| Directory | /workspace/0.rom_e2e_jtag_inject_dev/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_jtag_inject_test_unlocked0.2450307575 |
| Short name | T254 |
| Test name | |
| Test status | |
| Simulation time | 27776680461 ps |
| CPU time | 2526.11 seconds |
| Started | Jun 28 08:02:54 PM PDT 24 |
| Finished | Jun 28 08:45:02 PM PDT 24 |
| Peak memory | 618156 kb |
| Host | smart-a9fa612a-4fae-4826-ac6c-176be3a87919 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=40_000_000 +use_jtag_dmi=1 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=img_test_unlock ed0_exec_disabled:4,sram_program:5,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2450307575 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_e2e_jtag_ inject_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_jtag_inject _test_unlocked0.2450307575 |
| Directory | /workspace/0.rom_e2e_jtag_inject_test_unlocked0/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_keymgr_init_rom_ext_invalid_meas.3385064608 |
| Short name | T928 |
| Test name | |
| Test status | |
| Simulation time | 14865522498 ps |
| CPU time | 4593.54 seconds |
| Started | Jun 28 08:07:44 PM PDT 24 |
| Finished | Jun 28 09:24:19 PM PDT 24 |
| Peak memory | 608136 kb |
| Host | smart-232d812a-a9e0-46b5-949f-ceedd5ef3df7 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=40_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=rom_e2e_keymgr_init_otp_invalid _meas:1:new_rules,otp_img_keymgr_otp_invalid_meas:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3385064608 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip _sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_keymgr_in it_rom_ext_invalid_meas.3385064608 |
| Directory | /workspace/0.rom_e2e_keymgr_init_rom_ext_invalid_meas/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_keymgr_init_rom_ext_meas.2892512350 |
| Short name | T1070 |
| Test name | |
| Test status | |
| Simulation time | 14973820028 ps |
| CPU time | 4467.9 seconds |
| Started | Jun 28 08:07:43 PM PDT 24 |
| Finished | Jun 28 09:22:12 PM PDT 24 |
| Peak memory | 607236 kb |
| Host | smart-1d8f0dbb-0f3a-46ad-a223-47ac99f0c0cd |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=40_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=rom_e2e_keymgr_init_otp_meas:1: new_rules,otp_img_keymgr_otp_meas:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2892512350 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_keymgr_init_rom_ext_meas.2892512350 |
| Directory | /workspace/0.rom_e2e_keymgr_init_rom_ext_meas/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_keymgr_init_rom_ext_no_meas.862623097 |
| Short name | T1125 |
| Test name | |
| Test status | |
| Simulation time | 14876231952 ps |
| CPU time | 3947.51 seconds |
| Started | Jun 28 08:07:39 PM PDT 24 |
| Finished | Jun 28 09:13:28 PM PDT 24 |
| Peak memory | 607412 kb |
| Host | smart-d0755fb5-92d6-4961-a517-621212d73b4a |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=40_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=rom_e2e_keymgr_init_otp_no_meas :1:new_rules,otp_img_keymgr_otp_no_meas:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=862623097 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_keymgr_init_rom_ext_ no_meas.862623097 |
| Directory | /workspace/0.rom_e2e_keymgr_init_rom_ext_no_meas/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_shutdown_exception_c.2892519762 |
| Short name | T1157 |
| Test name | |
| Test status | |
| Simulation time | 14704983373 ps |
| CPU time | 3377.26 seconds |
| Started | Jun 28 08:07:43 PM PDT 24 |
| Finished | Jun 28 09:04:02 PM PDT 24 |
| Peak memory | 607992 kb |
| Host | smart-9a27edcf-7cc1-4534-90a4-b6064f291101 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=40000000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=rom_e2e_shutdown_exception_c:1:ne w_rules,otp_img_secret2_locked_rma:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2892519762 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_e2e_shu tdown_exception_c_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_ shutdown_exception_c.2892519762 |
| Directory | /workspace/0.rom_e2e_shutdown_exception_c/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_smoke.389028981 |
| Short name | T872 |
| Test name | |
| Test status | |
| Simulation time | 15007255316 ps |
| CPU time | 4251.13 seconds |
| Started | Jun 28 08:06:27 PM PDT 24 |
| Finished | Jun 28 09:17:20 PM PDT 24 |
| Peak memory | 607244 kb |
| Host | smart-5831d1cb-dd9d-4323-879b-5e038a6fefb4 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=40000000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=rom_e2e_smoke:1:new_rules,otp_img _secret2_locked_rma:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_to p/hw/dv/tools/sim.tcl +ntb_random_seed=389028981 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_smoke.389028981 |
| Directory | /workspace/0.rom_e2e_smoke/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_static_critical.2880818393 |
| Short name | T1030 |
| Test name | |
| Test status | |
| Simulation time | 16894389916 ps |
| CPU time | 4458.76 seconds |
| Started | Jun 28 08:06:58 PM PDT 24 |
| Finished | Jun 28 09:21:19 PM PDT 24 |
| Peak memory | 607260 kb |
| Host | smart-c74f82b6-f194-4086-8c1d-f8ae65f780a1 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=40000000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=rom_e2e_static_critical:1:new_rul es,otp_img_secret2_locked_rma:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2880818393 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_static_critical.2880818393 |
| Directory | /workspace/0.rom_e2e_static_critical/latest |
| Test location | /workspace/coverage/default/0.rom_keymgr_functest.3293791740 |
| Short name | T1013 |
| Test name | |
| Test status | |
| Simulation time | 4610807416 ps |
| CPU time | 533.01 seconds |
| Started | Jun 28 08:01:38 PM PDT 24 |
| Finished | Jun 28 08:10:33 PM PDT 24 |
| Peak memory | 609188 kb |
| Host | smart-986011a5-089f-478b-b233-1c446f9a3af3 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=10_000_000 +sw_build_device=sim_dv +sw_images=keymgr_functest:1:new_rules,test_rom:0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3293791740 -ass ert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 0.rom_keymgr_functest.3293791740 |
| Directory | /workspace/0.rom_keymgr_functest/latest |
| Test location | /workspace/coverage/default/0.rom_volatile_raw_unlock.1452334033 |
| Short name | T1266 |
| Test name | |
| Test status | |
| Simulation time | 2672524425 ps |
| CPU time | 117.31 seconds |
| Started | Jun 28 08:02:51 PM PDT 24 |
| Finished | Jun 28 08:04:50 PM PDT 24 |
| Peak memory | 614444 kb |
| Host | smart-a84364f8-e7af-40ef-a781-33b4837f91e5 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=200_000_000 +use_otp_image=OtpTypeLcStRaw +chip_clock_source=ChipClockSourceExternal48Mhz +rom_prod_mode=1 +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_test_key_0:1:ot_flash_binary,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1452334033 -assert nopostproc +UVM_ TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_volatile_raw_unlock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag e/default.vdb -cm_log /dev/null -cm_name 0.rom_volatile_raw_unlock.1452334033 |
| Directory | /workspace/0.rom_volatile_raw_unlock/latest |
| Test location | /workspace/coverage/default/1.chip_jtag_csr_rw.1313043376 |
| Short name | T195 |
| Test name | |
| Test status | |
| Simulation time | 11205263271 ps |
| CPU time | 1398.95 seconds |
| Started | Jun 28 07:59:08 PM PDT 24 |
| Finished | Jun 28 08:22:30 PM PDT 24 |
| Peak memory | 607380 kb |
| Host | smart-987c30dd-e8df-489a-89c0-98004b2aab5d |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +csr_rw +create_jtag_riscv_map=1 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1313043376 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_T EST_SEQ=chip_jtag_csr_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.c hip_jtag_csr_rw.1313043376 |
| Directory | /workspace/1.chip_jtag_csr_rw/latest |
| Test location | /workspace/coverage/default/1.chip_jtag_mem_access.491937453 |
| Short name | T77 |
| Test name | |
| Test status | |
| Simulation time | 14009298888 ps |
| CPU time | 1951.02 seconds |
| Started | Jun 28 07:58:05 PM PDT 24 |
| Finished | Jun 28 08:30:37 PM PDT 24 |
| Peak memory | 607332 kb |
| Host | smart-4f023a35-1fa9-4725-991e-60535e365f7c |
| User | root |
| Command | /workspace/default/simv +create_jtag_riscv_map=1 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=491937453 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_jtag_m em_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_jtag_mem_access.491937453 |
| Directory | /workspace/1.chip_jtag_mem_access/latest |
| Test location | /workspace/coverage/default/1.chip_sival_flash_info_access.1087864130 |
| Short name | T360 |
| Test name | |
| Test status | |
| Simulation time | 2960175008 ps |
| CPU time | 334.78 seconds |
| Started | Jun 28 08:06:22 PM PDT 24 |
| Finished | Jun 28 08:11:58 PM PDT 24 |
| Peak memory | 609172 kb |
| Host | smart-259ff336-116e-409d-92c6-64fac49d965d |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStTestUnlocked0 +sw_build_device=sim_dv +sw_images=flash_ctrl_info_access_lc:1:new_rules,test_rom:0 +c dc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_s eed=1087864130 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sival_flash_info_access.1087864130 |
| Directory | /workspace/1.chip_sival_flash_info_access/latest |
| Test location | /workspace/coverage/default/1.chip_sw_adc_ctrl_sleep_debug_cable_wakeup.3427295794 |
| Short name | T1261 |
| Test name | |
| Test status | |
| Simulation time | 19961328840 ps |
| CPU time | 704.43 seconds |
| Started | Jun 28 08:06:27 PM PDT 24 |
| Finished | Jun 28 08:18:13 PM PDT 24 |
| Peak memory | 617496 kb |
| Host | smart-4fd989ab-be65-4261-849a-2eed4aa9fa91 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=adc_ctrl_sleep_debug_cable_wakeup_test:1:new_rules,test_rom: 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand om_seed=3427295794 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_adc_ctrl_sleep_debug_cable_wakeup_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_adc_ctrl_sleep_debug_cable_wakeup.3427295794 |
| Directory | /workspace/1.chip_sw_adc_ctrl_sleep_debug_cable_wakeup/latest |
| Test location | /workspace/coverage/default/1.chip_sw_aes_enc.2739954695 |
| Short name | T264 |
| Test name | |
| Test status | |
| Simulation time | 3300615648 ps |
| CPU time | 272.9 seconds |
| Started | Jun 28 08:04:48 PM PDT 24 |
| Finished | Jun 28 08:09:22 PM PDT 24 |
| Peak memory | 609176 kb |
| Host | smart-c1fb7989-9550-47d4-80c7-4c8368174213 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=22_000_000 +sw_build_device=sim_dv +sw_images=aes_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2739954695 -asser t nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag e/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_aes_enc.2739954695 |
| Directory | /workspace/1.chip_sw_aes_enc/latest |
| Test location | /workspace/coverage/default/1.chip_sw_aes_enc_jitter_en.1606209688 |
| Short name | T1088 |
| Test name | |
| Test status | |
| Simulation time | 2991917223 ps |
| CPU time | 263.84 seconds |
| Started | Jun 28 08:11:18 PM PDT 24 |
| Finished | Jun 28 08:15:42 PM PDT 24 |
| Peak memory | 607120 kb |
| Host | smart-29774058-c9a4-45be-b191-12227899b132 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=26_000_000 +en_jitter=1 +sw_build_device=sim_dv +sw_images=aes_smoketest:1:new_rules,test_rom:0 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1606 209688 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work space/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_aes_enc_jitter_en.1606209688 |
| Directory | /workspace/1.chip_sw_aes_enc_jitter_en/latest |
| Test location | /workspace/coverage/default/1.chip_sw_aes_enc_jitter_en_reduced_freq.247849587 |
| Short name | T864 |
| Test name | |
| Test status | |
| Simulation time | 2853393550 ps |
| CPU time | 236.54 seconds |
| Started | Jun 28 08:08:44 PM PDT 24 |
| Finished | Jun 28 08:12:42 PM PDT 24 |
| Peak memory | 609192 kb |
| Host | smart-12bfa067-3a7f-4d0c-8e97-fbfedaf9189e |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=26_000_000 +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=aes_smoketest:1:new_rules, test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=247849587 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_aes_enc_jitter_en_reduced_freq.247849587 |
| Directory | /workspace/1.chip_sw_aes_enc_jitter_en_reduced_freq/latest |
| Test location | /workspace/coverage/default/1.chip_sw_aes_entropy.753207889 |
| Short name | T990 |
| Test name | |
| Test status | |
| Simulation time | 3067041182 ps |
| CPU time | 200.86 seconds |
| Started | Jun 28 08:10:45 PM PDT 24 |
| Finished | Jun 28 08:14:08 PM PDT 24 |
| Peak memory | 607100 kb |
| Host | smart-f75bd924-749a-45aa-8d2b-cc06a0c67611 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=15_000_000 +sw_build_device=sim_dv +sw_images=aes_entropy_test:1:new_rules,test_rom:0 +cdc_instrumentation _enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=753207889 -ass ert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_aes_entropy.753207889 |
| Directory | /workspace/1.chip_sw_aes_entropy/latest |
| Test location | /workspace/coverage/default/1.chip_sw_aes_idle.2921194210 |
| Short name | T283 |
| Test name | |
| Test status | |
| Simulation time | 3123499516 ps |
| CPU time | 277.39 seconds |
| Started | Jun 28 08:08:18 PM PDT 24 |
| Finished | Jun 28 08:12:56 PM PDT 24 |
| Peak memory | 607616 kb |
| Host | smart-e65afe68-3e8b-47f6-af71-0b66bdf020a6 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=25_000_000 +sw_build_device=sim_dv +sw_images=aes_idle_test:1:new_rules,test_rom:0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2921194210 -asser t nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag e/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_aes_idle.2921194210 |
| Directory | /workspace/1.chip_sw_aes_idle/latest |
| Test location | /workspace/coverage/default/1.chip_sw_aes_masking_off.2134670741 |
| Short name | T631 |
| Test name | |
| Test status | |
| Simulation time | 3047179414 ps |
| CPU time | 418.18 seconds |
| Started | Jun 28 08:09:16 PM PDT 24 |
| Finished | Jun 28 08:16:17 PM PDT 24 |
| Peak memory | 608384 kb |
| Host | smart-e1b1aded-8008-4c60-ac67-6e905bc98bbb |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=aes_masking_off_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2134670741 -assert nopostproc +UVM_TESTNA ME=chip_base_test +UVM_TEST_SEQ=chip_sw_aes_masking_off_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_aes_masking_off.2134670741 |
| Directory | /workspace/1.chip_sw_aes_masking_off/latest |
| Test location | /workspace/coverage/default/1.chip_sw_aes_smoketest.1043586261 |
| Short name | T1219 |
| Test name | |
| Test status | |
| Simulation time | 3295655720 ps |
| CPU time | 280.56 seconds |
| Started | Jun 28 08:11:51 PM PDT 24 |
| Finished | Jun 28 08:16:36 PM PDT 24 |
| Peak memory | 607132 kb |
| Host | smart-4d669d43-e1a3-4f11-8eb8-6d0eca864da1 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=aes_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1043586261 -assert nopostproc +UVM_TESTNAME=chip _base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_aes_smoketest.1043586261 |
| Directory | /workspace/1.chip_sw_aes_smoketest/latest |
| Test location | /workspace/coverage/default/1.chip_sw_alert_handler_entropy.1839226104 |
| Short name | T81 |
| Test name | |
| Test status | |
| Simulation time | 3033626496 ps |
| CPU time | 336.73 seconds |
| Started | Jun 28 08:05:50 PM PDT 24 |
| Finished | Jun 28 08:11:28 PM PDT 24 |
| Peak memory | 607488 kb |
| Host | smart-fb168172-7e6f-4271-a7df-8437bb729f65 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=alert_handler_entropy_test:1:new_rules,test_ro m:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=1839226104 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_alert_handler_entropy.1839226104 |
| Directory | /workspace/1.chip_sw_alert_handler_entropy/latest |
| Test location | /workspace/coverage/default/1.chip_sw_alert_handler_escalation.1442014493 |
| Short name | T1260 |
| Test name | |
| Test status | |
| Simulation time | 4792954280 ps |
| CPU time | 509.79 seconds |
| Started | Jun 28 08:07:25 PM PDT 24 |
| Finished | Jun 28 08:15:57 PM PDT 24 |
| Peak memory | 617268 kb |
| Host | smart-5163f682-ec19-4058-8f0b-67caf110d457 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=alert_handler_escalation_test:1:new_rules,test _rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb _random_seed=1442014493 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_alert_handler_escalation_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_alert_handler_escalation.1442014493 |
| Directory | /workspace/1.chip_sw_alert_handler_escalation/latest |
| Test location | /workspace/coverage/default/1.chip_sw_alert_handler_lpg_clkoff.3052851766 |
| Short name | T240 |
| Test name | |
| Test status | |
| Simulation time | 5310002426 ps |
| CPU time | 1222.39 seconds |
| Started | Jun 28 08:08:36 PM PDT 24 |
| Finished | Jun 28 08:29:00 PM PDT 24 |
| Peak memory | 608148 kb |
| Host | smart-24db4f5a-de73-469d-b412-9a03d4fcde1b |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +sw_build_device=sim_dv +sw_images=alert_handler_lpg_clkoff_test:1:new_rules,test_r om:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r andom_seed=3052851766 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_alert_handler_lpg_clkoff_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_alert_handler_lpg_clkoff.3052851766 |
| Directory | /workspace/1.chip_sw_alert_handler_lpg_clkoff/latest |
| Test location | /workspace/coverage/default/1.chip_sw_alert_handler_lpg_reset_toggle.898338778 |
| Short name | T205 |
| Test name | |
| Test status | |
| Simulation time | 7668083912 ps |
| CPU time | 1858.3 seconds |
| Started | Jun 28 08:07:53 PM PDT 24 |
| Finished | Jun 28 08:38:53 PM PDT 24 |
| Peak memory | 608116 kb |
| Host | smart-52e1db1d-8531-4f7c-a916-0ec93a142522 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +sw_build_device=sim_dv +sw_images=alert_handler_lpg_reset_toggle_test:1:new_rules, test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=898338778 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_alert_handler_shorten_ping_wait_cycle_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_alert_handler_lpg_reset_toggle.898338778 |
| Directory | /workspace/1.chip_sw_alert_handler_lpg_reset_toggle/latest |
| Test location | /workspace/coverage/default/1.chip_sw_alert_handler_lpg_sleep_mode_pings.289317447 |
| Short name | T1232 |
| Test name | |
| Test status | |
| Simulation time | 13003603082 ps |
| CPU time | 1752.43 seconds |
| Started | Jun 28 08:02:49 PM PDT 24 |
| Finished | Jun 28 08:32:03 PM PDT 24 |
| Peak memory | 608896 kb |
| Host | smart-3e86b09d-39f7-4e87-a814-077a43fd7b54 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=alert_handler _lpg_sleep_mode_pings_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=289317447 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_alert_hand ler_shorten_ping_wait_cycle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_alert_handler_lpg_sleep_mode_pings.289317447 |
| Directory | /workspace/1.chip_sw_alert_handler_lpg_sleep_mode_pings/latest |
| Test location | /workspace/coverage/default/1.chip_sw_alert_handler_ping_ok.2340130395 |
| Short name | T1027 |
| Test name | |
| Test status | |
| Simulation time | 7634237920 ps |
| CPU time | 1673.91 seconds |
| Started | Jun 28 08:09:14 PM PDT 24 |
| Finished | Jun 28 08:37:11 PM PDT 24 |
| Peak memory | 606852 kb |
| Host | smart-6e6e103d-3a17-4fa5-82eb-cbaaaad4189f |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=24000000 +sw_build_device=sim_dv +sw_images=alert_handler_ping_ok_test:1:new_rules,test_rom:0 +c dc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_s eed=2340130395 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_alert_handler_ping_ok.2340130395 |
| Directory | /workspace/1.chip_sw_alert_handler_ping_ok/latest |
| Test location | /workspace/coverage/default/1.chip_sw_alert_handler_ping_timeout.3486845339 |
| Short name | T1118 |
| Test name | |
| Test status | |
| Simulation time | 2516015352 ps |
| CPU time | 250.05 seconds |
| Started | Jun 28 08:11:15 PM PDT 24 |
| Finished | Jun 28 08:15:26 PM PDT 24 |
| Peak memory | 606628 kb |
| Host | smart-871793cd-0a6e-4d0f-a122-40eb8a31a678 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=24000000 +sw_build_device=sim_dv +sw_images=alert_handler_ping_timeout_test:1:new_rules,test_rom :0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=3486845339 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_alert_handler_ping_timeout.3486845339 |
| Directory | /workspace/1.chip_sw_alert_handler_ping_timeout/latest |
| Test location | /workspace/coverage/default/1.chip_sw_alert_test.1502629883 |
| Short name | T57 |
| Test name | |
| Test status | |
| Simulation time | 3567648952 ps |
| CPU time | 333.96 seconds |
| Started | Jun 28 08:11:20 PM PDT 24 |
| Finished | Jun 28 08:16:55 PM PDT 24 |
| Peak memory | 607136 kb |
| Host | smart-2fc9f6b7-f991-4cb9-8a38-e37b2f7c163d |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=alert_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1502629883 -assert nopostproc +UVM_TESTNAME=chip_ba se_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 1.chip_sw_alert_test.1502629883 |
| Directory | /workspace/1.chip_sw_alert_test/latest |
| Test location | /workspace/coverage/default/1.chip_sw_aon_timer_irq.2169582238 |
| Short name | T359 |
| Test name | |
| Test status | |
| Simulation time | 3594313556 ps |
| CPU time | 413.32 seconds |
| Started | Jun 28 08:05:06 PM PDT 24 |
| Finished | Jun 28 08:12:00 PM PDT 24 |
| Peak memory | 609172 kb |
| Host | smart-93aae849-402b-4342-bf31-d25f25b58e23 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=aon_timer_irq_test:1:new_rules,test_rom:0 +cdc_instrumentati on_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2169582238 - assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co verage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_aon_timer_irq.2169582238 |
| Directory | /workspace/1.chip_sw_aon_timer_irq/latest |
| Test location | /workspace/coverage/default/1.chip_sw_aon_timer_sleep_wdog_sleep_pause.1295262534 |
| Short name | T924 |
| Test name | |
| Test status | |
| Simulation time | 6403275612 ps |
| CPU time | 493.61 seconds |
| Started | Jun 28 08:05:28 PM PDT 24 |
| Finished | Jun 28 08:13:43 PM PDT 24 |
| Peak memory | 609248 kb |
| Host | smart-9d561fd2-07bf-408a-a2b9-062966b1b424 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=aon_timer_sleep_wdog_sleep_pause_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=1295262534 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_aon_timer_sleep_wdog_sleep_pause.1295262534 |
| Directory | /workspace/1.chip_sw_aon_timer_sleep_wdog_sleep_pause/latest |
| Test location | /workspace/coverage/default/1.chip_sw_aon_timer_smoketest.3812802386 |
| Short name | T1096 |
| Test name | |
| Test status | |
| Simulation time | 2980274130 ps |
| CPU time | 322.74 seconds |
| Started | Jun 28 08:13:05 PM PDT 24 |
| Finished | Jun 28 08:18:28 PM PDT 24 |
| Peak memory | 609184 kb |
| Host | smart-33664a46-dd9e-4244-b079-d3a9256ac347 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=aon_timer_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3812802386 -assert nopostproc +UVM_TESTNAM E=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 1.chip_sw_aon_timer_smoketest.3812802386 |
| Directory | /workspace/1.chip_sw_aon_timer_smoketest/latest |
| Test location | /workspace/coverage/default/1.chip_sw_aon_timer_wdog_bite_reset.3517680052 |
| Short name | T908 |
| Test name | |
| Test status | |
| Simulation time | 6942191500 ps |
| CPU time | 702.81 seconds |
| Started | Jun 28 08:10:25 PM PDT 24 |
| Finished | Jun 28 08:22:10 PM PDT 24 |
| Peak memory | 609248 kb |
| Host | smart-800e32b5-670b-4915-afc1-b5d1d1a5bc2e |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=aon_timer_wdog_bite_reset_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 3517680052 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_aon_timer_wdog_bite_reset.3517680052 |
| Directory | /workspace/1.chip_sw_aon_timer_wdog_bite_reset/latest |
| Test location | /workspace/coverage/default/1.chip_sw_aon_timer_wdog_lc_escalate.3661046138 |
| Short name | T871 |
| Test name | |
| Test status | |
| Simulation time | 5695650220 ps |
| CPU time | 721.85 seconds |
| Started | Jun 28 08:05:58 PM PDT 24 |
| Finished | Jun 28 08:18:01 PM PDT 24 |
| Peak memory | 608344 kb |
| Host | smart-930c4547-be97-4313-86b2-46d913711389 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=aon_timer_wdog_lc_escalate_test:1:new_rules,test_rom:0 +cdc_ instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed =3661046138 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_aon_timer_wdog_lc_escalate.3661046138 |
| Directory | /workspace/1.chip_sw_aon_timer_wdog_lc_escalate/latest |
| Test location | /workspace/coverage/default/1.chip_sw_ast_clk_outputs.1052753196 |
| Short name | T1245 |
| Test name | |
| Test status | |
| Simulation time | 6619121886 ps |
| CPU time | 900.98 seconds |
| Started | Jun 28 08:11:56 PM PDT 24 |
| Finished | Jun 28 08:26:58 PM PDT 24 |
| Peak memory | 615084 kb |
| Host | smart-0fe10e79-d94f-4ccf-960b-be0f79f11a00 |
| User | root |
| Command | /workspace/default/simv +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=ast_clk_outs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled= 1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1052753196 -assert nopo stproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_ast_clk_outputs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co verage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_ast_clk_outputs.1052753196 |
| Directory | /workspace/1.chip_sw_ast_clk_outputs/latest |
| Test location | /workspace/coverage/default/1.chip_sw_ast_clk_rst_inputs.3199746854 |
| Short name | T107 |
| Test name | |
| Test status | |
| Simulation time | 19110796719 ps |
| CPU time | 3081.13 seconds |
| Started | Jun 28 08:10:22 PM PDT 24 |
| Finished | Jun 28 09:01:45 PM PDT 24 |
| Peak memory | 608216 kb |
| Host | smart-02ff74b8-ef86-453d-9d2e-95e76acdfc65 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=200_000_000 +sw_build_device=sim_dv +sw_images=ast_clk_rst_inputs:1:new_rules,test_rom:0 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3199746854 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_ast_clk_rst_inputs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_ast_clk_rst_inputs.3199746854 |
| Directory | /workspace/1.chip_sw_ast_clk_rst_inputs/latest |
| Test location | /workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_fast_rma.1232631186 |
| Short name | T939 |
| Test name | |
| Test status | |
| Simulation time | 3311518136 ps |
| CPU time | 626.08 seconds |
| Started | Jun 28 08:12:46 PM PDT 24 |
| Finished | Jun 28 08:23:14 PM PDT 24 |
| Peak memory | 610236 kb |
| Host | smart-b59a0791-5586-42ff-8d46-d86484cbc8d1 |
| User | root |
| Command | /workspace/default/simv +chip_clock_source=ChipClockSourceExternal96Mhz +calibrate_usb_clk=1 +src_dec_state=DecLcStRma +sw_build_device=sim_dv +sw_ima ges=clkmgr_external_clk_src_for_sw_fast_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1232631186 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ =chip_sw_lc_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_c lkmgr_external_clk_src_for_sw_fast_rma.1232631186 |
| Directory | /workspace/1.chip_sw_clkmgr_external_clk_src_for_sw_fast_rma/latest |
| Test location | /workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0.1731672671 |
| Short name | T116 |
| Test name | |
| Test status | |
| Simulation time | 3643790800 ps |
| CPU time | 662.25 seconds |
| Started | Jun 28 08:07:06 PM PDT 24 |
| Finished | Jun 28 08:18:09 PM PDT 24 |
| Peak memory | 610972 kb |
| Host | smart-39ba0542-694a-4b80-8fd3-c62f6b8e1a01 |
| User | root |
| Command | /workspace/default/simv +chip_clock_source=ChipClockSourceExternal96Mhz +calibrate_usb_clk=1 +src_dec_state=DecLcStTestUnlocked0 +sw_build_device=sim_ dv +sw_images=clkmgr_external_clk_src_for_sw_fast_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1731672671 -assert nopostproc +UVM_TESTNAME=chip_base_test +UV M_TEST_SEQ=chip_sw_lc_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1 .chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0.1731672671 |
| Directory | /workspace/1.chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0/latest |
| Test location | /workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_slow_dev.331686710 |
| Short name | T115 |
| Test name | |
| Test status | |
| Simulation time | 4878160558 ps |
| CPU time | 845.09 seconds |
| Started | Jun 28 08:09:03 PM PDT 24 |
| Finished | Jun 28 08:23:11 PM PDT 24 |
| Peak memory | 610864 kb |
| Host | smart-cbc50905-1af2-4b48-80c2-f769c36c5d5e |
| User | root |
| Command | /workspace/default/simv +chip_clock_source=ChipClockSourceExternal48Mhz +calibrate_usb_clk=1 +src_dec_state=DecLcStDev +sw_build_device=sim_dv +sw_ima ges=clkmgr_external_clk_src_for_sw_slow_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=331686710 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ= chip_sw_lc_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_cl kmgr_external_clk_src_for_sw_slow_dev.331686710 |
| Directory | /workspace/1.chip_sw_clkmgr_external_clk_src_for_sw_slow_dev/latest |
| Test location | /workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_slow_rma.2580672337 |
| Short name | T394 |
| Test name | |
| Test status | |
| Simulation time | 5279127010 ps |
| CPU time | 695.19 seconds |
| Started | Jun 28 08:14:07 PM PDT 24 |
| Finished | Jun 28 08:25:43 PM PDT 24 |
| Peak memory | 610248 kb |
| Host | smart-19d8e2b9-f092-44e6-88b3-d30104d58397 |
| User | root |
| Command | /workspace/default/simv +chip_clock_source=ChipClockSourceExternal48Mhz +calibrate_usb_clk=1 +src_dec_state=DecLcStRma +sw_build_device=sim_dv +sw_ima ges=clkmgr_external_clk_src_for_sw_slow_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2580672337 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ =chip_sw_lc_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_c lkmgr_external_clk_src_for_sw_slow_rma.2580672337 |
| Directory | /workspace/1.chip_sw_clkmgr_external_clk_src_for_sw_slow_rma/latest |
| Test location | /workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0.1276556241 |
| Short name | T1072 |
| Test name | |
| Test status | |
| Simulation time | 5207655672 ps |
| CPU time | 572.73 seconds |
| Started | Jun 28 08:07:23 PM PDT 24 |
| Finished | Jun 28 08:16:58 PM PDT 24 |
| Peak memory | 610832 kb |
| Host | smart-99c002bd-43b1-4264-a6e1-3909c4e00823 |
| User | root |
| Command | /workspace/default/simv +chip_clock_source=ChipClockSourceExternal48Mhz +calibrate_usb_clk=1 +src_dec_state=DecLcStTestUnlocked0 +sw_build_device=sim_ dv +sw_images=clkmgr_external_clk_src_for_sw_slow_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1276556241 -assert nopostproc +UVM_TESTNAME=chip_base_test +UV M_TEST_SEQ=chip_sw_lc_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1 .chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0.1276556241 |
| Directory | /workspace/1.chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0/latest |
| Test location | /workspace/coverage/default/1.chip_sw_clkmgr_jitter.1269250329 |
| Short name | T994 |
| Test name | |
| Test status | |
| Simulation time | 2302403310 ps |
| CPU time | 213.37 seconds |
| Started | Jun 28 08:08:28 PM PDT 24 |
| Finished | Jun 28 08:12:03 PM PDT 24 |
| Peak memory | 607116 kb |
| Host | smart-14c2df09-be6b-4145-b8e9-f9773fd508e4 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_jitter_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1269250329 -assert nopostproc +UVM_TESTNAME =chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 1.chip_sw_clkmgr_jitter.1269250329 |
| Directory | /workspace/1.chip_sw_clkmgr_jitter/latest |
| Test location | /workspace/coverage/default/1.chip_sw_clkmgr_jitter_frequency.1731758646 |
| Short name | T1053 |
| Test name | |
| Test status | |
| Simulation time | 3919182482 ps |
| CPU time | 396.35 seconds |
| Started | Jun 28 08:09:46 PM PDT 24 |
| Finished | Jun 28 08:16:24 PM PDT 24 |
| Peak memory | 609200 kb |
| Host | smart-9aba0be4-d1e0-419c-a1cd-6aacdf86ecb8 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_jitter_frequency_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1731758646 -assert nopostproc +UV M_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -c m_log /dev/null -cm_name 1.chip_sw_clkmgr_jitter_frequency.1731758646 |
| Directory | /workspace/1.chip_sw_clkmgr_jitter_frequency/latest |
| Test location | /workspace/coverage/default/1.chip_sw_clkmgr_jitter_reduced_freq.1841426578 |
| Short name | T1113 |
| Test name | |
| Test status | |
| Simulation time | 3031661011 ps |
| CPU time | 183.82 seconds |
| Started | Jun 28 08:07:26 PM PDT 24 |
| Finished | Jun 28 08:10:32 PM PDT 24 |
| Peak memory | 609180 kb |
| Host | smart-ab9d21b6-1ad0-4409-92fa-809aa3adf47b |
| User | root |
| Command | /workspace/default/simv +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=clkmgr_jitter_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1841426578 -assert nop ostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def ault.vdb -cm_log /dev/null -cm_name 1.chip_sw_clkmgr_jitter_reduced_freq.1841426578 |
| Directory | /workspace/1.chip_sw_clkmgr_jitter_reduced_freq/latest |
| Test location | /workspace/coverage/default/1.chip_sw_clkmgr_off_aes_trans.3297986675 |
| Short name | T909 |
| Test name | |
| Test status | |
| Simulation time | 4484176500 ps |
| CPU time | 427.21 seconds |
| Started | Jun 28 08:12:26 PM PDT 24 |
| Finished | Jun 28 08:19:37 PM PDT 24 |
| Peak memory | 608676 kb |
| Host | smart-b8b05226-d0f0-497b-973d-60354c663e9d |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_off_aes_trans_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3297986675 -assert nopostproc +UVM_T ESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l og /dev/null -cm_name 1.chip_sw_clkmgr_off_aes_trans.3297986675 |
| Directory | /workspace/1.chip_sw_clkmgr_off_aes_trans/latest |
| Test location | /workspace/coverage/default/1.chip_sw_clkmgr_off_hmac_trans.3330575077 |
| Short name | T1256 |
| Test name | |
| Test status | |
| Simulation time | 4028253464 ps |
| CPU time | 502.95 seconds |
| Started | Jun 28 08:08:36 PM PDT 24 |
| Finished | Jun 28 08:16:59 PM PDT 24 |
| Peak memory | 609184 kb |
| Host | smart-a4b32403-d67d-4e70-b664-10c5394f7201 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_off_hmac_trans_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3330575077 -assert nopostproc +UVM_ TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_ log /dev/null -cm_name 1.chip_sw_clkmgr_off_hmac_trans.3330575077 |
| Directory | /workspace/1.chip_sw_clkmgr_off_hmac_trans/latest |
| Test location | /workspace/coverage/default/1.chip_sw_clkmgr_off_kmac_trans.437896880 |
| Short name | T1290 |
| Test name | |
| Test status | |
| Simulation time | 5237609106 ps |
| CPU time | 530.82 seconds |
| Started | Jun 28 08:05:17 PM PDT 24 |
| Finished | Jun 28 08:14:10 PM PDT 24 |
| Peak memory | 609160 kb |
| Host | smart-fbc5bb66-ff68-4dd0-b9be-6416ea4a6278 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_off_kmac_trans_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=437896880 -assert nopostproc +UVM_T ESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l og /dev/null -cm_name 1.chip_sw_clkmgr_off_kmac_trans.437896880 |
| Directory | /workspace/1.chip_sw_clkmgr_off_kmac_trans/latest |
| Test location | /workspace/coverage/default/1.chip_sw_clkmgr_off_otbn_trans.65574434 |
| Short name | T892 |
| Test name | |
| Test status | |
| Simulation time | 4622562700 ps |
| CPU time | 595.76 seconds |
| Started | Jun 28 08:07:15 PM PDT 24 |
| Finished | Jun 28 08:17:12 PM PDT 24 |
| Peak memory | 609132 kb |
| Host | smart-6421a659-99c9-4ff5-ada6-6fe551c01178 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_off_otbn_trans_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65574434 -assert nopostproc +UVM_TE STNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo g /dev/null -cm_name 1.chip_sw_clkmgr_off_otbn_trans.65574434 |
| Directory | /workspace/1.chip_sw_clkmgr_off_otbn_trans/latest |
| Test location | /workspace/coverage/default/1.chip_sw_clkmgr_off_peri.3932831344 |
| Short name | T986 |
| Test name | |
| Test status | |
| Simulation time | 13089536164 ps |
| CPU time | 1754.9 seconds |
| Started | Jun 28 08:06:33 PM PDT 24 |
| Finished | Jun 28 08:35:49 PM PDT 24 |
| Peak memory | 609196 kb |
| Host | smart-2cfcbc8e-9414-47e7-a167-443f49741a4d |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=30_000_000 +sw_build_device=sim_dv +sw_images=clkmgr_off_peri_test:1:new_rules,test_rom:0 +cdc_instrumenta tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3932831344 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/ coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_clkmgr_off_peri.3932831344 |
| Directory | /workspace/1.chip_sw_clkmgr_off_peri/latest |
| Test location | /workspace/coverage/default/1.chip_sw_clkmgr_reset_frequency.2226626691 |
| Short name | T677 |
| Test name | |
| Test status | |
| Simulation time | 3639937968 ps |
| CPU time | 400.63 seconds |
| Started | Jun 28 08:13:31 PM PDT 24 |
| Finished | Jun 28 08:20:19 PM PDT 24 |
| Peak memory | 606820 kb |
| Host | smart-a00e0e10-e23a-471b-b880-b8c2664eda3d |
| User | root |
| Command | /workspace/default/simv +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=clkmgr_reset_frequency_test:1:new_rules,test_rom:0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2226626691 -a ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov erage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_clkmgr_reset_frequency.2226626691 |
| Directory | /workspace/1.chip_sw_clkmgr_reset_frequency/latest |
| Test location | /workspace/coverage/default/1.chip_sw_clkmgr_sleep_frequency.4242858699 |
| Short name | T1002 |
| Test name | |
| Test status | |
| Simulation time | 4157533634 ps |
| CPU time | 589.29 seconds |
| Started | Jun 28 08:09:16 PM PDT 24 |
| Finished | Jun 28 08:19:07 PM PDT 24 |
| Peak memory | 607480 kb |
| Host | smart-3f23c7de-4572-4f1f-bf6b-cdc97076dc27 |
| User | root |
| Command | /workspace/default/simv +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=clkmgr_sleep_frequency_test:1:new_rules,test_rom:0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4242858699 -a ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov erage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_clkmgr_sleep_frequency.4242858699 |
| Directory | /workspace/1.chip_sw_clkmgr_sleep_frequency/latest |
| Test location | /workspace/coverage/default/1.chip_sw_clkmgr_smoketest.2532801367 |
| Short name | T897 |
| Test name | |
| Test status | |
| Simulation time | 2593180816 ps |
| CPU time | 376.16 seconds |
| Started | Jun 28 08:12:57 PM PDT 24 |
| Finished | Jun 28 08:19:15 PM PDT 24 |
| Peak memory | 607124 kb |
| Host | smart-42a15d81-cd39-42ca-b157-027707475ae7 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2532801367 -assert nopostproc +UVM_TESTNAME=c hip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n ull -cm_name 1.chip_sw_clkmgr_smoketest.2532801367 |
| Directory | /workspace/1.chip_sw_clkmgr_smoketest/latest |
| Test location | /workspace/coverage/default/1.chip_sw_csrng_edn_concurrency.1781415626 |
| Short name | T255 |
| Test name | |
| Test status | |
| Simulation time | 16647592936 ps |
| CPU time | 4070.27 seconds |
| Started | Jun 28 08:11:51 PM PDT 24 |
| Finished | Jun 28 09:19:46 PM PDT 24 |
| Peak memory | 607948 kb |
| Host | smart-3823bf60-86fe-4f20-aae1-7efe841edad2 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=140_000_000 +rng_srate_value_min=15 +rng_srate_value_max=20 +accelerate_cold_power_up_time=3 +accelerate_r egulators_power_up_time=2 +sw_build_device=sim_dv +sw_images=csrng_edn_concurrency_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1781415626 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd b -cm_log /dev/null -cm_name 1.chip_sw_csrng_edn_concurrency.1781415626 |
| Directory | /workspace/1.chip_sw_csrng_edn_concurrency/latest |
| Test location | /workspace/coverage/default/1.chip_sw_csrng_edn_concurrency_reduced_freq.591782509 |
| Short name | T634 |
| Test name | |
| Test status | |
| Simulation time | 28104945603 ps |
| CPU time | 4893.32 seconds |
| Started | Jun 28 08:09:27 PM PDT 24 |
| Finished | Jun 28 09:31:02 PM PDT 24 |
| Peak memory | 609320 kb |
| Host | smart-96418211-c22b-4d17-bb50-e7a655d1d25a |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=360_000_000 +rng_srate_value_min=15 +rng_srate_value_max=20 +cal_sys_clk_70mhz=1 +en_jitter=1 +accelerate_ cold_power_up_time=3 +accelerate_regulators_power_up_time=2 +sw_build_device=sim_dv +sw_images=csrng_edn_concurrency_test:1:new_rules,test_rom:0 + cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_ seed=591782509 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_csrng_edn_concurrency_reduced_freq.591782509 |
| Directory | /workspace/1.chip_sw_csrng_edn_concurrency_reduced_freq/latest |
| Test location | /workspace/coverage/default/1.chip_sw_csrng_fuse_en_sw_app_read_test.934290766 |
| Short name | T1249 |
| Test name | |
| Test status | |
| Simulation time | 4498135208 ps |
| CPU time | 353.57 seconds |
| Started | Jun 28 08:04:43 PM PDT 24 |
| Finished | Jun 28 08:10:37 PM PDT 24 |
| Peak memory | 609192 kb |
| Host | smart-95246730-8878-4830-b23b-a21122796791 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=15_000_000 +sw_build_device=sim_dv +sw_images=csrng_fuse_en_sw_app_read:1:new_rules,test_rom:0 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93429 0766 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_entropy_src_fuse_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_csrng_fuse_en_sw_app_read_test.934290766 |
| Directory | /workspace/1.chip_sw_csrng_fuse_en_sw_app_read_test/latest |
| Test location | /workspace/coverage/default/1.chip_sw_csrng_kat_test.1848808591 |
| Short name | T895 |
| Test name | |
| Test status | |
| Simulation time | 2942269492 ps |
| CPU time | 294.56 seconds |
| Started | Jun 28 08:07:09 PM PDT 24 |
| Finished | Jun 28 08:12:04 PM PDT 24 |
| Peak memory | 607556 kb |
| Host | smart-419bc555-bddf-4e3b-86a3-b98e4f0bdc41 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=csrng_kat_test:1:new_rules,test_rom:0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1848808591 -asse rt nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera ge/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_csrng_kat_test.1848808591 |
| Directory | /workspace/1.chip_sw_csrng_kat_test/latest |
| Test location | /workspace/coverage/default/1.chip_sw_csrng_smoketest.1385394887 |
| Short name | T1007 |
| Test name | |
| Test status | |
| Simulation time | 3387844376 ps |
| CPU time | 231.7 seconds |
| Started | Jun 28 08:13:33 PM PDT 24 |
| Finished | Jun 28 08:17:31 PM PDT 24 |
| Peak memory | 607128 kb |
| Host | smart-711d9fdc-be04-4956-ae3f-a91bde6a394d |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=csrng_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1385394887 -assert nopostproc +UVM_TESTNAME=ch ip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu ll -cm_name 1.chip_sw_csrng_smoketest.1385394887 |
| Directory | /workspace/1.chip_sw_csrng_smoketest/latest |
| Test location | /workspace/coverage/default/1.chip_sw_data_integrity_escalation.2181326246 |
| Short name | T267 |
| Test name | |
| Test status | |
| Simulation time | 4704843910 ps |
| CPU time | 865.07 seconds |
| Started | Jun 28 08:06:47 PM PDT 24 |
| Finished | Jun 28 08:21:14 PM PDT 24 |
| Peak memory | 608480 kb |
| Host | smart-d2a533d2-ffc4-4a78-bf16-6b8b67bb0764 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=data_integrity_escalation_reset_test:1:new_rules,test_ro m:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=2181326246 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_data_integrity_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_data_integrity_escalation.2181326246 |
| Directory | /workspace/1.chip_sw_data_integrity_escalation/latest |
| Test location | /workspace/coverage/default/1.chip_sw_edn_auto_mode.3912129630 |
| Short name | T1278 |
| Test name | |
| Test status | |
| Simulation time | 4735320280 ps |
| CPU time | 1030.39 seconds |
| Started | Jun 28 08:07:35 PM PDT 24 |
| Finished | Jun 28 08:24:47 PM PDT 24 |
| Peak memory | 609308 kb |
| Host | smart-b83c33e5-7e24-4a71-ad96-03616af07455 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +rng_srate_value=5 +accelerate_cold_power_up_time=3 +accelerate_regulators_power_up_time=2 +sw_ build_device=sim_dv +sw_images=edn_auto_mode:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3912129630 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ =chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_edn_ auto_mode.3912129630 |
| Directory | /workspace/1.chip_sw_edn_auto_mode/latest |
| Test location | /workspace/coverage/default/1.chip_sw_edn_boot_mode.2676014077 |
| Short name | T118 |
| Test name | |
| Test status | |
| Simulation time | 3605792760 ps |
| CPU time | 622.39 seconds |
| Started | Jun 28 08:06:16 PM PDT 24 |
| Finished | Jun 28 08:16:39 PM PDT 24 |
| Peak memory | 607848 kb |
| Host | smart-c52afbec-920d-484a-978a-ed3c74812d99 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +rng_srate_value=5 +accelerate_cold_power_up_time=3 +accelerate_regulators_power_up_time=2 +sw_ build_device=sim_dv +sw_images=edn_boot_mode:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2676014077 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ =chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_edn_ boot_mode.2676014077 |
| Directory | /workspace/1.chip_sw_edn_boot_mode/latest |
| Test location | /workspace/coverage/default/1.chip_sw_edn_entropy_reqs.3210207238 |
| Short name | T1220 |
| Test name | |
| Test status | |
| Simulation time | 4998544252 ps |
| CPU time | 1043.88 seconds |
| Started | Jun 28 08:09:01 PM PDT 24 |
| Finished | Jun 28 08:26:29 PM PDT 24 |
| Peak memory | 609316 kb |
| Host | smart-1e1f5f90-2983-478c-800a-bdf117cf82fa |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=15000000 +rng_srate_value_min=15 +rng_srate_value_max=30 +sw_build_device=sim_dv +sw_images=entropy_src_ed n_reqs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3210207238 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_edn_entropy_reqs.3210207238 |
| Directory | /workspace/1.chip_sw_edn_entropy_reqs/latest |
| Test location | /workspace/coverage/default/1.chip_sw_edn_entropy_reqs_jitter.129960052 |
| Short name | T434 |
| Test name | |
| Test status | |
| Simulation time | 6786561538 ps |
| CPU time | 1263.22 seconds |
| Started | Jun 28 08:05:46 PM PDT 24 |
| Finished | Jun 28 08:26:50 PM PDT 24 |
| Peak memory | 608640 kb |
| Host | smart-5484c181-17eb-42ff-bfb4-ea33551f1180 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=15000000 +rng_srate_value_min=15 +rng_srate_value_max=30 +en_jitter=1 +sw_build_device=sim_dv +sw_images=e ntropy_src_edn_reqs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=129960052 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_edn_entropy_reqs_jitter.129960052 |
| Directory | /workspace/1.chip_sw_edn_entropy_reqs_jitter/latest |
| Test location | /workspace/coverage/default/1.chip_sw_edn_kat.3728346734 |
| Short name | T1063 |
| Test name | |
| Test status | |
| Simulation time | 2968535896 ps |
| CPU time | 598.97 seconds |
| Started | Jun 28 08:03:48 PM PDT 24 |
| Finished | Jun 28 08:13:48 PM PDT 24 |
| Peak memory | 614280 kb |
| Host | smart-7a1e3233-317f-4c20-807b-14bf71085886 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +rng_srate_value=5 +disable_assert_edn_output_diff_from_prev=1 +accelerate_cold_power_up_time=3 +accelerate_regulators_power_up_time=2 +sw_build_device=sim_dv +sw_images=edn_kat:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3728346734 -assert nopostproc +UVM _TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm _log /dev/null -cm_name 1.chip_sw_edn_kat.3728346734 |
| Directory | /workspace/1.chip_sw_edn_kat/latest |
| Test location | /workspace/coverage/default/1.chip_sw_edn_sw_mode.1309069019 |
| Short name | T930 |
| Test name | |
| Test status | |
| Simulation time | 8023066440 ps |
| CPU time | 1301.66 seconds |
| Started | Jun 28 08:02:49 PM PDT 24 |
| Finished | Jun 28 08:24:32 PM PDT 24 |
| Peak memory | 607948 kb |
| Host | smart-d9ba0992-9494-4933-b441-1eda69a64472 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=edn_sw_mode:1:new_rules,test_rom:0 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1309069019 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/ default.vdb -cm_log /dev/null -cm_name 1.chip_sw_edn_sw_mode.1309069019 |
| Directory | /workspace/1.chip_sw_edn_sw_mode/latest |
| Test location | /workspace/coverage/default/1.chip_sw_entropy_src_ast_rng_req.1988826235 |
| Short name | T971 |
| Test name | |
| Test status | |
| Simulation time | 2311418660 ps |
| CPU time | 227.21 seconds |
| Started | Jun 28 08:03:35 PM PDT 24 |
| Finished | Jun 28 08:07:24 PM PDT 24 |
| Peak memory | 609184 kb |
| Host | smart-1140cbd4-7652-4593-b527-853cf40d608c |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=15_000_000 +sw_build_device=sim_dv +sw_images=entropy_src_ast_rng_req_test:1:new_rules,test_rom:0 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19 88826235 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_entropy_src_ast_rng_req.1988826235 |
| Directory | /workspace/1.chip_sw_entropy_src_ast_rng_req/latest |
| Test location | /workspace/coverage/default/1.chip_sw_entropy_src_kat_test.1517423196 |
| Short name | T1010 |
| Test name | |
| Test status | |
| Simulation time | 2669191252 ps |
| CPU time | 182.67 seconds |
| Started | Jun 28 08:07:59 PM PDT 24 |
| Finished | Jun 28 08:11:02 PM PDT 24 |
| Peak memory | 609132 kb |
| Host | smart-980fb259-c33e-46a4-b963-711ae7d3e714 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=entropy_src_kat_test:1:new_rules,test_rom:0 +cdc_instrumenta tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1517423196 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/ coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_entropy_src_kat_test.1517423196 |
| Directory | /workspace/1.chip_sw_entropy_src_kat_test/latest |
| Test location | /workspace/coverage/default/1.chip_sw_entropy_src_smoketest.1074184197 |
| Short name | T999 |
| Test name | |
| Test status | |
| Simulation time | 4091953510 ps |
| CPU time | 548.13 seconds |
| Started | Jun 28 08:13:35 PM PDT 24 |
| Finished | Jun 28 08:22:49 PM PDT 24 |
| Peak memory | 609188 kb |
| Host | smart-3263901d-21ce-45d9-be8e-68077f4a91c1 |
| User | root |
| Command | /workspace/default/simv +rng_srate_value_min=15 +rng_srate_value_max=30 +sw_build_device=sim_dv +sw_images=entropy_src_smoketest:1:new_rules,test_rom: 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand om_seed=1074184197 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_entropy_src_smoketest.1074184197 |
| Directory | /workspace/1.chip_sw_entropy_src_smoketest/latest |
| Test location | /workspace/coverage/default/1.chip_sw_example_concurrency.2734816008 |
| Short name | T1087 |
| Test name | |
| Test status | |
| Simulation time | 2722569700 ps |
| CPU time | 297.3 seconds |
| Started | Jun 28 08:03:14 PM PDT 24 |
| Finished | Jun 28 08:08:13 PM PDT 24 |
| Peak memory | 609188 kb |
| Host | smart-c6a3a3ee-4221-4fad-87ac-37e951301c52 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=example_concurrency_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2734816008 -assert nopostproc +UVM_TE STNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo g /dev/null -cm_name 1.chip_sw_example_concurrency.2734816008 |
| Directory | /workspace/1.chip_sw_example_concurrency/latest |
| Test location | /workspace/coverage/default/1.chip_sw_example_flash.3003715266 |
| Short name | T887 |
| Test name | |
| Test status | |
| Simulation time | 3567689404 ps |
| CPU time | 311.2 seconds |
| Started | Jun 28 08:04:12 PM PDT 24 |
| Finished | Jun 28 08:09:24 PM PDT 24 |
| Peak memory | 607336 kb |
| Host | smart-156c710c-be78-4968-9c9d-58df98d86262 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=example_test_from_flash:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3003715266 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_example_flash.3003715266 |
| Directory | /workspace/1.chip_sw_example_flash/latest |
| Test location | /workspace/coverage/default/1.chip_sw_example_manufacturer.3500254971 |
| Short name | T959 |
| Test name | |
| Test status | |
| Simulation time | 2896611900 ps |
| CPU time | 205.85 seconds |
| Started | Jun 28 08:06:55 PM PDT 24 |
| Finished | Jun 28 08:10:23 PM PDT 24 |
| Peak memory | 607124 kb |
| Host | smart-2e775014-d647-4310-ae4d-c479044cd54b |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=example_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3500254971 -assert nopostproc +UVM_TESTNAME=chip_ base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_example_manufacturer.3500254971 |
| Directory | /workspace/1.chip_sw_example_manufacturer/latest |
| Test location | /workspace/coverage/default/1.chip_sw_example_rom.3654150109 |
| Short name | T1210 |
| Test name | |
| Test status | |
| Simulation time | 2306711720 ps |
| CPU time | 127.51 seconds |
| Started | Jun 28 08:03:58 PM PDT 24 |
| Finished | Jun 28 08:06:08 PM PDT 24 |
| Peak memory | 606936 kb |
| Host | smart-13201430-dafe-47dc-a08f-550596ce6f8e |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:test_in_rom:new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3654150109 -assert nopostproc +UVM_TEST NAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_example_rom.3654150109 |
| Directory | /workspace/1.chip_sw_example_rom/latest |
| Test location | /workspace/coverage/default/1.chip_sw_flash_crash_alert.3319532888 |
| Short name | T952 |
| Test name | |
| Test status | |
| Simulation time | 4953479074 ps |
| CPU time | 608.48 seconds |
| Started | Jun 28 08:08:27 PM PDT 24 |
| Finished | Jun 28 08:18:36 PM PDT 24 |
| Peak memory | 608548 kb |
| Host | smart-1b3ecaba-a955-4c3a-b6b9-8d410a78d875 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=8_000_000 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1: new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tool s/sim.tcl +ntb_random_seed=3319532888 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_flash_host_gnt_err_inj_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_flash_crash_alert.3319532888 |
| Directory | /workspace/1.chip_sw_flash_crash_alert/latest |
| Test location | /workspace/coverage/default/1.chip_sw_flash_ctrl_access.1711456034 |
| Short name | T1021 |
| Test name | |
| Test status | |
| Simulation time | 5700354250 ps |
| CPU time | 1095.9 seconds |
| Started | Jun 28 08:03:06 PM PDT 24 |
| Finished | Jun 28 08:21:23 PM PDT 24 |
| Peak memory | 607112 kb |
| Host | smart-edaca51a-c8e8-4a56-b392-10274fc194c1 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=flash_ctrl_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1711456034 -assert nopostproc +UVM_TESTNAME=ch ip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu ll -cm_name 1.chip_sw_flash_ctrl_access.1711456034 |
| Directory | /workspace/1.chip_sw_flash_ctrl_access/latest |
| Test location | /workspace/coverage/default/1.chip_sw_flash_ctrl_access_jitter_en.3960683824 |
| Short name | T111 |
| Test name | |
| Test status | |
| Simulation time | 6539834274 ps |
| CPU time | 1262.24 seconds |
| Started | Jun 28 08:05:45 PM PDT 24 |
| Finished | Jun 28 08:26:48 PM PDT 24 |
| Peak memory | 609172 kb |
| Host | smart-9e0d33b8-9059-468e-a383-3495f5c9f88c |
| User | root |
| Command | /workspace/default/simv +en_jitter=1 +sw_build_device=sim_dv +sw_images=flash_ctrl_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3960683824 -assert nopostproc +UV M_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -c m_log /dev/null -cm_name 1.chip_sw_flash_ctrl_access_jitter_en.3960683824 |
| Directory | /workspace/1.chip_sw_flash_ctrl_access_jitter_en/latest |
| Test location | /workspace/coverage/default/1.chip_sw_flash_ctrl_access_jitter_en_reduced_freq.1737784142 |
| Short name | T882 |
| Test name | |
| Test status | |
| Simulation time | 7233089606 ps |
| CPU time | 1156.32 seconds |
| Started | Jun 28 08:11:03 PM PDT 24 |
| Finished | Jun 28 08:30:21 PM PDT 24 |
| Peak memory | 607668 kb |
| Host | smart-fd59c15d-abf9-4d53-90b3-3e3957262fc4 |
| User | root |
| Command | /workspace/default/simv +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=flash_ctrl_test:1:new_rules,test_rom:0 +cdc_instrumentati on_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1737784142 - assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co verage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_flash_ctrl_access_jitter_en_reduced_freq.1737784142 |
| Directory | /workspace/1.chip_sw_flash_ctrl_access_jitter_en_reduced_freq/latest |
| Test location | /workspace/coverage/default/1.chip_sw_flash_ctrl_clock_freqs.2100587939 |
| Short name | T977 |
| Test name | |
| Test status | |
| Simulation time | 5618620725 ps |
| CPU time | 1178.25 seconds |
| Started | Jun 28 08:06:37 PM PDT 24 |
| Finished | Jun 28 08:26:17 PM PDT 24 |
| Peak memory | 609176 kb |
| Host | smart-00403de4-b9b0-463c-b23b-423f1ccbf7f5 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=flash_ctrl_clock_freqs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2100587939 -assert nopostproc +UVM _TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm _log /dev/null -cm_name 1.chip_sw_flash_ctrl_clock_freqs.2100587939 |
| Directory | /workspace/1.chip_sw_flash_ctrl_clock_freqs/latest |
| Test location | /workspace/coverage/default/1.chip_sw_flash_ctrl_idle_low_power.1691418271 |
| Short name | T927 |
| Test name | |
| Test status | |
| Simulation time | 3383645968 ps |
| CPU time | 427.84 seconds |
| Started | Jun 28 08:06:02 PM PDT 24 |
| Finished | Jun 28 08:13:11 PM PDT 24 |
| Peak memory | 609216 kb |
| Host | smart-cce1535f-61e7-4727-8c20-d35009784f12 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=flash_ctrl_idle_low_power_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1691418271 -assert nopostproc + UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_flash_ctrl_idle_low_power.1691418271 |
| Directory | /workspace/1.chip_sw_flash_ctrl_idle_low_power/latest |
| Test location | /workspace/coverage/default/1.chip_sw_flash_ctrl_mem_protection.332510918 |
| Short name | T1152 |
| Test name | |
| Test status | |
| Simulation time | 5647285736 ps |
| CPU time | 1229.54 seconds |
| Started | Jun 28 08:11:44 PM PDT 24 |
| Finished | Jun 28 08:32:23 PM PDT 24 |
| Peak memory | 609180 kb |
| Host | smart-14553674-9b4b-4e74-a411-1c879d9ace12 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=flash_ctrl_mem_protection_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=332510918 -assert nopostproc +U VM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb - cm_log /dev/null -cm_name 1.chip_sw_flash_ctrl_mem_protection.332510918 |
| Directory | /workspace/1.chip_sw_flash_ctrl_mem_protection/latest |
| Test location | /workspace/coverage/default/1.chip_sw_flash_ctrl_ops.60329002 |
| Short name | T269 |
| Test name | |
| Test status | |
| Simulation time | 3744085350 ps |
| CPU time | 582.49 seconds |
| Started | Jun 28 08:05:58 PM PDT 24 |
| Finished | Jun 28 08:15:43 PM PDT 24 |
| Peak memory | 607704 kb |
| Host | smart-d969bd08-38c1-4a0d-a459-b74cb512ec7f |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=50_000_000 +sw_build_device=sim_dv +sw_images=flash_ctrl_ops_test:1:new_rules,test_rom:0 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60329002 -a ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov erage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_flash_ctrl_ops.60329002 |
| Directory | /workspace/1.chip_sw_flash_ctrl_ops/latest |
| Test location | /workspace/coverage/default/1.chip_sw_flash_ctrl_ops_jitter_en_reduced_freq.985145175 |
| Short name | T363 |
| Test name | |
| Test status | |
| Simulation time | 4986437811 ps |
| CPU time | 633.85 seconds |
| Started | Jun 28 08:08:07 PM PDT 24 |
| Finished | Jun 28 08:18:42 PM PDT 24 |
| Peak memory | 608044 kb |
| Host | smart-760acc9d-264f-45fd-aa4d-ab0e4f9abb05 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=50_000_000 +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=flash_ctrl_ops_test:1:new_ rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si m.tcl +ntb_random_seed=985145175 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_flash_ctrl_ops_jitter_en_reduced_freq.985145175 |
| Directory | /workspace/1.chip_sw_flash_ctrl_ops_jitter_en_reduced_freq/latest |
| Test location | /workspace/coverage/default/1.chip_sw_flash_ctrl_write_clear.4123140168 |
| Short name | T1291 |
| Test name | |
| Test status | |
| Simulation time | 3135948184 ps |
| CPU time | 418.67 seconds |
| Started | Jun 28 08:11:00 PM PDT 24 |
| Finished | Jun 28 08:18:00 PM PDT 24 |
| Peak memory | 607112 kb |
| Host | smart-9d00ede3-8135-42a0-b0b8-5c499577d045 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=8_000_000 +sw_build_device=sim_dv +sw_images=flash_ctrl_write_clear_test:1:new_rules,test_rom:0 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4123140 168 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_flash_ctrl_write_clear.4123140168 |
| Directory | /workspace/1.chip_sw_flash_ctrl_write_clear/latest |
| Test location | /workspace/coverage/default/1.chip_sw_flash_init.524333441 |
| Short name | T226 |
| Test name | |
| Test status | |
| Simulation time | 21960306778 ps |
| CPU time | 2543.41 seconds |
| Started | Jun 28 08:05:09 PM PDT 24 |
| Finished | Jun 28 08:47:34 PM PDT 24 |
| Peak memory | 610548 kb |
| Host | smart-fbace6a7-99f5-4444-ba70-dcf35fa26968 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=25_000_000 +sw_build_device=sim_dv +sw_images=flash_init_test:0:test_in_rom:new_rules +cdc_instrumentation _enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=524333441 -ass ert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_flash_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace /coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_flash_init.524333441 |
| Directory | /workspace/1.chip_sw_flash_init/latest |
| Test location | /workspace/coverage/default/1.chip_sw_flash_init_reduced_freq.2868418750 |
| Short name | T234 |
| Test name | |
| Test status | |
| Simulation time | 26972560770 ps |
| CPU time | 2393.6 seconds |
| Started | Jun 28 08:09:46 PM PDT 24 |
| Finished | Jun 28 08:49:42 PM PDT 24 |
| Peak memory | 610344 kb |
| Host | smart-117237bf-b9f0-459a-8ee0-b0a32f83294b |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=25_000_000 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=flash_init_test:0:test_in_rom:new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=2868418750 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_flash_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_flash_init_reduced_freq.2868418750 |
| Directory | /workspace/1.chip_sw_flash_init_reduced_freq/latest |
| Test location | /workspace/coverage/default/1.chip_sw_flash_scrambling_smoketest.3431473927 |
| Short name | T899 |
| Test name | |
| Test status | |
| Simulation time | 3207697560 ps |
| CPU time | 295.47 seconds |
| Started | Jun 28 08:13:12 PM PDT 24 |
| Finished | Jun 28 08:18:09 PM PDT 24 |
| Peak memory | 606568 kb |
| Host | smart-4727b4d6-3654-42bc-bff4-d3c62a7bf6cb |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=flash_scrambling_smoketest:1:new_rules,flash_scrambling_smoket est_otp_img_rma:4,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=3431473927 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_flash_scrambling_smoketest.3431473927 |
| Directory | /workspace/1.chip_sw_flash_scrambling_smoketest/latest |
| Test location | /workspace/coverage/default/1.chip_sw_gpio_smoketest.1860528825 |
| Short name | T1119 |
| Test name | |
| Test status | |
| Simulation time | 3242605169 ps |
| CPU time | 274.56 seconds |
| Started | Jun 28 08:13:30 PM PDT 24 |
| Finished | Jun 28 08:18:10 PM PDT 24 |
| Peak memory | 607888 kb |
| Host | smart-206d12ab-e4a9-48c2-bed5-c56c463469ae |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=gpio_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1860528825 -assert nopostproc +UVM_TESTNAME=chi p_base_test +UVM_TEST_SEQ=chip_sw_gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 1.chip_sw_gpio_smoketest.1860528825 |
| Directory | /workspace/1.chip_sw_gpio_smoketest/latest |
| Test location | /workspace/coverage/default/1.chip_sw_hmac_enc.1887740447 |
| Short name | T352 |
| Test name | |
| Test status | |
| Simulation time | 3759217774 ps |
| CPU time | 309.82 seconds |
| Started | Jun 28 08:04:25 PM PDT 24 |
| Finished | Jun 28 08:09:37 PM PDT 24 |
| Peak memory | 606316 kb |
| Host | smart-60654da6-4366-411e-9494-d77c0e12ab25 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=hmac_enc_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1887740447 -assert nopostproc +UVM_TESTNAME=chip _base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_hmac_enc.1887740447 |
| Directory | /workspace/1.chip_sw_hmac_enc/latest |
| Test location | /workspace/coverage/default/1.chip_sw_hmac_enc_idle.2816076405 |
| Short name | T1056 |
| Test name | |
| Test status | |
| Simulation time | 3619087608 ps |
| CPU time | 277.5 seconds |
| Started | Jun 28 08:05:44 PM PDT 24 |
| Finished | Jun 28 08:10:22 PM PDT 24 |
| Peak memory | 607132 kb |
| Host | smart-1184dcbc-7241-4e8d-8207-8bf7a071b8f4 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=hmac_enc_idle_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2816076405 -assert nopostproc +UVM_TESTNAME =chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 1.chip_sw_hmac_enc_idle.2816076405 |
| Directory | /workspace/1.chip_sw_hmac_enc_idle/latest |
| Test location | /workspace/coverage/default/1.chip_sw_hmac_enc_jitter_en.4040715047 |
| Short name | T1089 |
| Test name | |
| Test status | |
| Simulation time | 2592287717 ps |
| CPU time | 256.95 seconds |
| Started | Jun 28 08:04:11 PM PDT 24 |
| Finished | Jun 28 08:08:29 PM PDT 24 |
| Peak memory | 609192 kb |
| Host | smart-f5d8c744-59b0-4ba2-9c72-0f1e6b451ca9 |
| User | root |
| Command | /workspace/default/simv +en_jitter=1 +sw_build_device=sim_dv +sw_images=hmac_enc_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4040715047 -assert nopostproc +UVM_ TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_ log /dev/null -cm_name 1.chip_sw_hmac_enc_jitter_en.4040715047 |
| Directory | /workspace/1.chip_sw_hmac_enc_jitter_en/latest |
| Test location | /workspace/coverage/default/1.chip_sw_hmac_enc_jitter_en_reduced_freq.4272369150 |
| Short name | T1043 |
| Test name | |
| Test status | |
| Simulation time | 2991513935 ps |
| CPU time | 243.18 seconds |
| Started | Jun 28 08:08:22 PM PDT 24 |
| Finished | Jun 28 08:12:26 PM PDT 24 |
| Peak memory | 609192 kb |
| Host | smart-6c8ed454-63ed-4a71-8c4b-063d24365ba9 |
| User | root |
| Command | /workspace/default/simv +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=hmac_enc_test:1:new_rules,test_rom:0 +cdc_instrumentation _enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4272369150 -as sert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove rage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_hmac_enc_jitter_en_reduced_freq.4272369150 |
| Directory | /workspace/1.chip_sw_hmac_enc_jitter_en_reduced_freq/latest |
| Test location | /workspace/coverage/default/1.chip_sw_hmac_multistream.2417180803 |
| Short name | T1101 |
| Test name | |
| Test status | |
| Simulation time | 6956275324 ps |
| CPU time | 1763.59 seconds |
| Started | Jun 28 08:05:43 PM PDT 24 |
| Finished | Jun 28 08:35:07 PM PDT 24 |
| Peak memory | 609272 kb |
| Host | smart-97f0cc4f-6db6-444f-815e-27db79fb82ec |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=hmac_multistream_functest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2417180803 -assert nopostproc +UVM_T ESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l og /dev/null -cm_name 1.chip_sw_hmac_multistream.2417180803 |
| Directory | /workspace/1.chip_sw_hmac_multistream/latest |
| Test location | /workspace/coverage/default/1.chip_sw_hmac_oneshot.544228936 |
| Short name | T875 |
| Test name | |
| Test status | |
| Simulation time | 2208219960 ps |
| CPU time | 335.43 seconds |
| Started | Jun 28 08:04:44 PM PDT 24 |
| Finished | Jun 28 08:10:21 PM PDT 24 |
| Peak memory | 607536 kb |
| Host | smart-fd80420e-c7db-45b0-90d5-e8f7d04d0af2 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=hmac_functest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=544228936 -assert nopostproc +UVM_TESTNAME=chip_ base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_hmac_oneshot.544228936 |
| Directory | /workspace/1.chip_sw_hmac_oneshot/latest |
| Test location | /workspace/coverage/default/1.chip_sw_hmac_smoketest.1667293573 |
| Short name | T282 |
| Test name | |
| Test status | |
| Simulation time | 2868724140 ps |
| CPU time | 367.31 seconds |
| Started | Jun 28 08:13:23 PM PDT 24 |
| Finished | Jun 28 08:19:32 PM PDT 24 |
| Peak memory | 606300 kb |
| Host | smart-7433adbc-2add-4bd1-8ab7-41a0a827ba82 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=hmac_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1667293573 -assert nopostproc +UVM_TESTNAME=chi p_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul l -cm_name 1.chip_sw_hmac_smoketest.1667293573 |
| Directory | /workspace/1.chip_sw_hmac_smoketest/latest |
| Test location | /workspace/coverage/default/1.chip_sw_i2c_device_tx_rx.4166717314 |
| Short name | T333 |
| Test name | |
| Test status | |
| Simulation time | 4271399546 ps |
| CPU time | 573.19 seconds |
| Started | Jun 28 08:05:49 PM PDT 24 |
| Finished | Jun 28 08:15:25 PM PDT 24 |
| Peak memory | 607256 kb |
| Host | smart-f7fd78e6-033f-43f0-90f2-45043aa2c663 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=i2c_device_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4166717314 -assert nopostproc +UVM_TESTN AME=chip_base_test +UVM_TEST_SEQ=chip_sw_i2c_device_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v db -cm_log /dev/null -cm_name 1.chip_sw_i2c_device_tx_rx.4166717314 |
| Directory | /workspace/1.chip_sw_i2c_device_tx_rx/latest |
| Test location | /workspace/coverage/default/1.chip_sw_i2c_host_tx_rx.4290590596 |
| Short name | T343 |
| Test name | |
| Test status | |
| Simulation time | 5066410904 ps |
| CPU time | 727.47 seconds |
| Started | Jun 28 08:07:26 PM PDT 24 |
| Finished | Jun 28 08:19:35 PM PDT 24 |
| Peak memory | 608284 kb |
| Host | smart-24c2a915-fa95-4d69-88a7-62053cf1488c |
| User | root |
| Command | /workspace/default/simv +i2c_idx=0 +sw_build_device=sim_dv +sw_images=i2c_host_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4290590596 -assert nopostproc + UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_i2c_host_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de fault.vdb -cm_log /dev/null -cm_name 1.chip_sw_i2c_host_tx_rx.4290590596 |
| Directory | /workspace/1.chip_sw_i2c_host_tx_rx/latest |
| Test location | /workspace/coverage/default/1.chip_sw_i2c_host_tx_rx_idx1.1041407816 |
| Short name | T208 |
| Test name | |
| Test status | |
| Simulation time | 5066491288 ps |
| CPU time | 797.73 seconds |
| Started | Jun 28 08:05:32 PM PDT 24 |
| Finished | Jun 28 08:18:51 PM PDT 24 |
| Peak memory | 607268 kb |
| Host | smart-8bf73d49-0149-48e9-b450-8b1a4774258a |
| User | root |
| Command | /workspace/default/simv +i2c_idx=1 +sw_build_device=sim_dv +sw_images=i2c_host_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1041407816 -assert nopostproc + UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_i2c_host_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de fault.vdb -cm_log /dev/null -cm_name 1.chip_sw_i2c_host_tx_rx_idx1.1041407816 |
| Directory | /workspace/1.chip_sw_i2c_host_tx_rx_idx1/latest |
| Test location | /workspace/coverage/default/1.chip_sw_i2c_host_tx_rx_idx2.825110351 |
| Short name | T327 |
| Test name | |
| Test status | |
| Simulation time | 4588397030 ps |
| CPU time | 720.25 seconds |
| Started | Jun 28 08:05:53 PM PDT 24 |
| Finished | Jun 28 08:17:55 PM PDT 24 |
| Peak memory | 608240 kb |
| Host | smart-c0519e89-1a61-43ac-baba-59c87019dae2 |
| User | root |
| Command | /workspace/default/simv +i2c_idx=2 +sw_build_device=sim_dv +sw_images=i2c_host_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=825110351 -assert nopostproc +U VM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_i2c_host_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def ault.vdb -cm_log /dev/null -cm_name 1.chip_sw_i2c_host_tx_rx_idx2.825110351 |
| Directory | /workspace/1.chip_sw_i2c_host_tx_rx_idx2/latest |
| Test location | /workspace/coverage/default/1.chip_sw_inject_scramble_seed.680421618 |
| Short name | T197 |
| Test name | |
| Test status | |
| Simulation time | 64207808094 ps |
| CPU time | 12777.5 seconds |
| Started | Jun 28 08:04:29 PM PDT 24 |
| Finished | Jun 28 11:37:28 PM PDT 24 |
| Peak memory | 624160 kb |
| Host | smart-2e52ec55-d0d2-49f2-b628-d35f4ba727ea |
| User | root |
| Command | /workspace/default/simv +lc_at_prod=1 +flash_program_latency=5 +sw_test_timeout_ns=150_000_000 +sw_build_device=sim_dv +sw_images=inject_scramble_seed :1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=680421618 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_inject_scramble_seed_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_inject_scramble_seed.680421618 |
| Directory | /workspace/1.chip_sw_inject_scramble_seed/latest |
| Test location | /workspace/coverage/default/1.chip_sw_keymgr_key_derivation.2091936392 |
| Short name | T1215 |
| Test name | |
| Test status | |
| Simulation time | 8788805466 ps |
| CPU time | 1712.23 seconds |
| Started | Jun 28 08:08:15 PM PDT 24 |
| Finished | Jun 28 08:36:49 PM PDT 24 |
| Peak memory | 615640 kb |
| Host | smart-d158dd17-3001-4d4b-a4ac-03c123bc2ceb |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=20_000_000 +sw_build_device=sim_dv +sw_images=keymgr_key_derivation_test:1:new_rules,test_rom:0 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2091 936392 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_keymgr_key_derivation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_keymgr_key_derivation.2091936392 |
| Directory | /workspace/1.chip_sw_keymgr_key_derivation/latest |
| Test location | /workspace/coverage/default/1.chip_sw_keymgr_key_derivation_jitter_en.2939274641 |
| Short name | T219 |
| Test name | |
| Test status | |
| Simulation time | 8838624650 ps |
| CPU time | 1168.17 seconds |
| Started | Jun 28 08:04:34 PM PDT 24 |
| Finished | Jun 28 08:24:03 PM PDT 24 |
| Peak memory | 614392 kb |
| Host | smart-ff05f120-9d28-4259-b0f0-39cc9afea686 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=20_000_000 +en_jitter=1 +sw_build_device=sim_dv +sw_images=keymgr_key_derivation_test:1:new_rules,test_rom :0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=2939274641 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_keymgr_key_derivation_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_keymgr_key_derivation_jitter_en.2939274641 |
| Directory | /workspace/1.chip_sw_keymgr_key_derivation_jitter_en/latest |
| Test location | /workspace/coverage/default/1.chip_sw_keymgr_key_derivation_jitter_en_reduced_freq.1971700503 |
| Short name | T1134 |
| Test name | |
| Test status | |
| Simulation time | 11785890413 ps |
| CPU time | 2206.09 seconds |
| Started | Jun 28 08:11:16 PM PDT 24 |
| Finished | Jun 28 08:48:03 PM PDT 24 |
| Peak memory | 615688 kb |
| Host | smart-535f5bd1-efff-4279-83ae-9cb0d9b79922 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=20_000_000 +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=keymgr_key_derivation_test :1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=1971700503 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_keymgr_key_derivation_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_keymgr_key_derivation_jitter_en _reduced_freq.1971700503 |
| Directory | /workspace/1.chip_sw_keymgr_key_derivation_jitter_en_reduced_freq/latest |
| Test location | /workspace/coverage/default/1.chip_sw_keymgr_key_derivation_prod.516653676 |
| Short name | T220 |
| Test name | |
| Test status | |
| Simulation time | 9369808040 ps |
| CPU time | 1744.83 seconds |
| Started | Jun 28 08:05:05 PM PDT 24 |
| Finished | Jun 28 08:34:11 PM PDT 24 |
| Peak memory | 614308 kb |
| Host | smart-e2443fb4-b763-47a3-a699-5ec1be54f285 |
| User | root |
| Command | /workspace/default/simv +lc_at_prod=1 +sw_test_timeout_ns=20_000_000 +sw_build_device=sim_dv +sw_images=keymgr_key_derivation_test:1:new_rules,test_ro m:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=516653676 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_keymgr_key_derivation_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_keymgr_key_derivation_prod.516653676 |
| Directory | /workspace/1.chip_sw_keymgr_key_derivation_prod/latest |
| Test location | /workspace/coverage/default/1.chip_sw_keymgr_sideload_aes.648984308 |
| Short name | T217 |
| Test name | |
| Test status | |
| Simulation time | 7815419660 ps |
| CPU time | 1934.9 seconds |
| Started | Jun 28 08:05:35 PM PDT 24 |
| Finished | Jun 28 08:37:51 PM PDT 24 |
| Peak memory | 609352 kb |
| Host | smart-ff5dc3ae-44d1-4a21-9a5f-d063a3d5a95b |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=20_000_000 +sw_build_device=sim_dv +sw_images=keymgr_sideload_aes_test:1:new_rules,test_rom:0 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=648984 308 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_keymgr_sideload_aes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_keymgr_sideload_aes.648984308 |
| Directory | /workspace/1.chip_sw_keymgr_sideload_aes/latest |
| Test location | /workspace/coverage/default/1.chip_sw_keymgr_sideload_kmac.3261344809 |
| Short name | T936 |
| Test name | |
| Test status | |
| Simulation time | 8300369004 ps |
| CPU time | 1726.11 seconds |
| Started | Jun 28 08:08:23 PM PDT 24 |
| Finished | Jun 28 08:37:11 PM PDT 24 |
| Peak memory | 609256 kb |
| Host | smart-271d1fca-4a4f-4c66-80ac-fb7d2011308a |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=20_000_000 +sw_build_device=sim_dv +sw_images=keymgr_sideload_kmac_test:1:new_rules,test_rom:0 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32613 44809 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_keymgr_sideload_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_keymgr_sideload_kmac.3261344809 |
| Directory | /workspace/1.chip_sw_keymgr_sideload_kmac/latest |
| Test location | /workspace/coverage/default/1.chip_sw_kmac_app_rom.3789153453 |
| Short name | T1283 |
| Test name | |
| Test status | |
| Simulation time | 3044410500 ps |
| CPU time | 230.02 seconds |
| Started | Jun 28 08:03:47 PM PDT 24 |
| Finished | Jun 28 08:07:38 PM PDT 24 |
| Peak memory | 607132 kb |
| Host | smart-8dd3d2c6-2e54-4c6b-a5f6-69581a5fc05e |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=kmac_app_rom_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3789153453 -assert nopostproc +UVM_TESTNAME= chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/ null -cm_name 1.chip_sw_kmac_app_rom.3789153453 |
| Directory | /workspace/1.chip_sw_kmac_app_rom/latest |
| Test location | /workspace/coverage/default/1.chip_sw_kmac_entropy.3258450570 |
| Short name | T1222 |
| Test name | |
| Test status | |
| Simulation time | 2689743054 ps |
| CPU time | 227.57 seconds |
| Started | Jun 28 08:04:28 PM PDT 24 |
| Finished | Jun 28 08:08:16 PM PDT 24 |
| Peak memory | 607284 kb |
| Host | smart-0f02d368-935b-4386-9e3d-ce4ecabf1cc6 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=kmac_entropy_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3258450570 -assert nopostproc +UVM_TESTNAME= chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/ null -cm_name 1.chip_sw_kmac_entropy.3258450570 |
| Directory | /workspace/1.chip_sw_kmac_entropy/latest |
| Test location | /workspace/coverage/default/1.chip_sw_kmac_mode_cshake.1086450184 |
| Short name | T943 |
| Test name | |
| Test status | |
| Simulation time | 3564383768 ps |
| CPU time | 302.25 seconds |
| Started | Jun 28 08:04:15 PM PDT 24 |
| Finished | Jun 28 08:09:19 PM PDT 24 |
| Peak memory | 609172 kb |
| Host | smart-44298ab8-787f-4bb0-8858-0cf9df4816a8 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=kmac_mode_cshake_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1086450184 -assert nopostproc +UVM_TESTN AME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log / dev/null -cm_name 1.chip_sw_kmac_mode_cshake.1086450184 |
| Directory | /workspace/1.chip_sw_kmac_mode_cshake/latest |
| Test location | /workspace/coverage/default/1.chip_sw_kmac_mode_kmac.3847754841 |
| Short name | T868 |
| Test name | |
| Test status | |
| Simulation time | 2988386656 ps |
| CPU time | 231.31 seconds |
| Started | Jun 28 08:07:52 PM PDT 24 |
| Finished | Jun 28 08:11:44 PM PDT 24 |
| Peak memory | 607364 kb |
| Host | smart-1ce71a5e-8947-48c8-ba9c-2393b5267a9e |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=kmac_mode_kmac_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3847754841 -assert nopostproc +UVM_TESTNAM E=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 1.chip_sw_kmac_mode_kmac.3847754841 |
| Directory | /workspace/1.chip_sw_kmac_mode_kmac/latest |
| Test location | /workspace/coverage/default/1.chip_sw_kmac_mode_kmac_jitter_en.2731424385 |
| Short name | T263 |
| Test name | |
| Test status | |
| Simulation time | 3599617203 ps |
| CPU time | 301.64 seconds |
| Started | Jun 28 08:07:58 PM PDT 24 |
| Finished | Jun 28 08:13:00 PM PDT 24 |
| Peak memory | 609192 kb |
| Host | smart-232a1d25-26ff-4094-a5a8-704a58a556fa |
| User | root |
| Command | /workspace/default/simv +en_jitter=1 +sw_build_device=sim_dv +sw_images=kmac_mode_kmac_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2731424385 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd b -cm_log /dev/null -cm_name 1.chip_sw_kmac_mode_kmac_jitter_en.2731424385 |
| Directory | /workspace/1.chip_sw_kmac_mode_kmac_jitter_en/latest |
| Test location | /workspace/coverage/default/1.chip_sw_kmac_mode_kmac_jitter_en_reduced_freq.2575428586 |
| Short name | T962 |
| Test name | |
| Test status | |
| Simulation time | 3741006297 ps |
| CPU time | 257.29 seconds |
| Started | Jun 28 08:08:24 PM PDT 24 |
| Finished | Jun 28 08:12:42 PM PDT 24 |
| Peak memory | 609180 kb |
| Host | smart-c6e78ad1-660e-4e81-ba66-df13278c356d |
| User | root |
| Command | /workspace/default/simv +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=kmac_mode_kmac_test:1:new_rules,test_rom:0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25754285 86 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac e/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_kmac_mode_kmac_jitter_en_reduced_freq.2575428586 |
| Directory | /workspace/1.chip_sw_kmac_mode_kmac_jitter_en_reduced_freq/latest |
| Test location | /workspace/coverage/default/1.chip_sw_kmac_smoketest.2956578424 |
| Short name | T880 |
| Test name | |
| Test status | |
| Simulation time | 2428219460 ps |
| CPU time | 293.18 seconds |
| Started | Jun 28 08:12:44 PM PDT 24 |
| Finished | Jun 28 08:17:39 PM PDT 24 |
| Peak memory | 607144 kb |
| Host | smart-245d6cd7-3e31-41bc-9a92-f40cf6bfe91a |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=kmac_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2956578424 -assert nopostproc +UVM_TESTNAME=chi p_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul l -cm_name 1.chip_sw_kmac_smoketest.2956578424 |
| Directory | /workspace/1.chip_sw_kmac_smoketest/latest |
| Test location | /workspace/coverage/default/1.chip_sw_lc_ctrl_otp_hw_cfg0.406891445 |
| Short name | T1038 |
| Test name | |
| Test status | |
| Simulation time | 3348158370 ps |
| CPU time | 347.68 seconds |
| Started | Jun 28 08:04:31 PM PDT 24 |
| Finished | Jun 28 08:10:20 PM PDT 24 |
| Peak memory | 609240 kb |
| Host | smart-7bb0e3fb-cd5c-4b7f-9617-f96c07cc9c62 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=lc_ctrl_otp_hw_cfg0_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=406891445 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_lc_ctrl_otp_hw_cfg0.406891445 |
| Directory | /workspace/1.chip_sw_lc_ctrl_otp_hw_cfg0/latest |
| Test location | /workspace/coverage/default/1.chip_sw_lc_ctrl_program_error.1010593563 |
| Short name | T164 |
| Test name | |
| Test status | |
| Simulation time | 4866313574 ps |
| CPU time | 402.53 seconds |
| Started | Jun 28 08:08:21 PM PDT 24 |
| Finished | Jun 28 08:15:05 PM PDT 24 |
| Peak memory | 608716 kb |
| Host | smart-d5c2406e-2af8-4495-920a-6dd497b47b15 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=lc_ctrl_program_error:1:new_rules,test_rom:0 + cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_ seed=1010593563 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_program_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_lc_ctrl_program_error.1010593563 |
| Directory | /workspace/1.chip_sw_lc_ctrl_program_error/latest |
| Test location | /workspace/coverage/default/1.chip_sw_lc_ctrl_rand_to_scrap.2433866647 |
| Short name | T1116 |
| Test name | |
| Test status | |
| Simulation time | 3414051436 ps |
| CPU time | 157.39 seconds |
| Started | Jun 28 08:05:58 PM PDT 24 |
| Finished | Jun 28 08:08:37 PM PDT 24 |
| Peak memory | 617732 kb |
| Host | smart-caa2789d-9f79-4fa9-82ae-64b0fb76a5df |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=lc_ctrl_scrap_test:1:new_rules,test_rom:0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24338666 47 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_scrap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_lc_ctrl_rand_to_scrap.2433866647 |
| Directory | /workspace/1.chip_sw_lc_ctrl_rand_to_scrap/latest |
| Test location | /workspace/coverage/default/1.chip_sw_lc_ctrl_transition.3919524905 |
| Short name | T56 |
| Test name | |
| Test status | |
| Simulation time | 12098635141 ps |
| CPU time | 910.39 seconds |
| Started | Jun 28 08:04:15 PM PDT 24 |
| Finished | Jun 28 08:19:27 PM PDT 24 |
| Peak memory | 621496 kb |
| Host | smart-902f886e-3357-402b-8e00-dc4c21c729ed |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=lc_ctrl_transition_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3919524905 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_transition_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau lt.vdb -cm_log /dev/null -cm_name 1.chip_sw_lc_ctrl_transition.3919524905 |
| Directory | /workspace/1.chip_sw_lc_ctrl_transition/latest |
| Test location | /workspace/coverage/default/1.chip_sw_lc_ctrl_volatile_raw_unlock.132714211 |
| Short name | T643 |
| Test name | |
| Test status | |
| Simulation time | 2831117405 ps |
| CPU time | 139.23 seconds |
| Started | Jun 28 08:05:42 PM PDT 24 |
| Finished | Jun 28 08:08:03 PM PDT 24 |
| Peak memory | 616204 kb |
| Host | smart-e8c8d3b4-a9b5-442b-bb22-b9035dc31fab |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStRaw +exp_volatile_raw_unlock_en=0 +sw_build_device=sim_dv +sw_images=lc_ctrl_volatile_raw_unlock_tes t:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/ tools/sim.tcl +ntb_random_seed=132714211 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_volatile_raw_unlock_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_lc_ctrl_volatile_raw_unlock.132714211 |
| Directory | /workspace/1.chip_sw_lc_ctrl_volatile_raw_unlock/latest |
| Test location | /workspace/coverage/default/1.chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz.2380486162 |
| Short name | T62 |
| Test name | |
| Test status | |
| Simulation time | 2812429019 ps |
| CPU time | 120.77 seconds |
| Started | Jun 28 08:06:28 PM PDT 24 |
| Finished | Jun 28 08:08:30 PM PDT 24 |
| Peak memory | 614432 kb |
| Host | smart-9c105bd9-8ebb-45be-a74e-cac4a165106d |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStRaw +chip_clock_source=ChipClockSourceExternal48Mhz +exp_volatile_raw_unlock_en=0 +sw_build_device=s im_dv +sw_images=lc_ctrl_volatile_raw_unlock_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2380486162 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TES T_SEQ=chip_sw_lc_volatile_raw_unlock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz.2380486162 |
| Directory | /workspace/1.chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz/latest |
| Test location | /workspace/coverage/default/1.chip_sw_lc_walkthrough_dev.545076711 |
| Short name | T227 |
| Test name | |
| Test status | |
| Simulation time | 48026838840 ps |
| CPU time | 5297.13 seconds |
| Started | Jun 28 08:04:57 PM PDT 24 |
| Finished | Jun 28 09:33:16 PM PDT 24 |
| Peak memory | 617064 kb |
| Host | smart-594149b4-55f1-408d-934b-5586cae52375 |
| User | root |
| Command | /workspace/default/simv +flash_program_latency=5 +use_otp_image=OtpTypeLcStRaw +dest_dec_state=DecLcStDev +sw_test_timeout_ns=200_000_000 +sw_build_de vice=sim_dv +sw_images=lc_walkthrough_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=545076711 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=ch ip_sw_lc_walkthrough_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_ sw_lc_walkthrough_dev.545076711 |
| Directory | /workspace/1.chip_sw_lc_walkthrough_dev/latest |
| Test location | /workspace/coverage/default/1.chip_sw_lc_walkthrough_prod.3356642554 |
| Short name | T232 |
| Test name | |
| Test status | |
| Simulation time | 48331076782 ps |
| CPU time | 5345.38 seconds |
| Started | Jun 28 08:06:44 PM PDT 24 |
| Finished | Jun 28 09:35:51 PM PDT 24 |
| Peak memory | 616820 kb |
| Host | smart-c8909bc7-d834-4b3c-a4c9-82c5ed98afc5 |
| User | root |
| Command | /workspace/default/simv +flash_program_latency=5 +use_otp_image=OtpTypeLcStRaw +dest_dec_state=DecLcStProd +sw_test_timeout_ns=200_000_000 +sw_build_d evice=sim_dv +sw_images=lc_walkthrough_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3356642554 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ= chip_sw_lc_walkthrough_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chi p_sw_lc_walkthrough_prod.3356642554 |
| Directory | /workspace/1.chip_sw_lc_walkthrough_prod/latest |
| Test location | /workspace/coverage/default/1.chip_sw_lc_walkthrough_prodend.1475230851 |
| Short name | T1228 |
| Test name | |
| Test status | |
| Simulation time | 10665512768 ps |
| CPU time | 939.34 seconds |
| Started | Jun 28 08:05:21 PM PDT 24 |
| Finished | Jun 28 08:21:04 PM PDT 24 |
| Peak memory | 623604 kb |
| Host | smart-67864d1f-6537-4244-ac38-024fb34dde5c |
| User | root |
| Command | /workspace/default/simv +flash_program_latency=5 +use_otp_image=OtpTypeLcStRaw +dest_dec_state=DecLcStProdEnd +sw_build_device=sim_dv +sw_images=lc_wa lkthrough_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1475230851 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_walkthrough_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_lc_walkthrough_prodend.1475230851 |
| Directory | /workspace/1.chip_sw_lc_walkthrough_prodend/latest |
| Test location | /workspace/coverage/default/1.chip_sw_lc_walkthrough_rma.1468070143 |
| Short name | T223 |
| Test name | |
| Test status | |
| Simulation time | 48846406289 ps |
| CPU time | 5500.28 seconds |
| Started | Jun 28 08:06:55 PM PDT 24 |
| Finished | Jun 28 09:38:38 PM PDT 24 |
| Peak memory | 623640 kb |
| Host | smart-ed8e456e-dcee-42b7-9b18-708385139ed3 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStRaw +dest_dec_state=DecLcStRma +flash_program_latency=5 +sw_test_timeout_ns=200_000_000 +sw_build_de vice=sim_dv +sw_images=lc_walkthrough_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1468070143 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=c hip_sw_lc_walkthrough_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip _sw_lc_walkthrough_rma.1468070143 |
| Directory | /workspace/1.chip_sw_lc_walkthrough_rma/latest |
| Test location | /workspace/coverage/default/1.chip_sw_lc_walkthrough_testunlocks.2457857448 |
| Short name | T1032 |
| Test name | |
| Test status | |
| Simulation time | 31179584744 ps |
| CPU time | 2152.71 seconds |
| Started | Jun 28 08:07:54 PM PDT 24 |
| Finished | Jun 28 08:43:48 PM PDT 24 |
| Peak memory | 617764 kb |
| Host | smart-0daff23b-cd5b-47d1-862c-afcba67eb9f6 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStRaw +dest_dec_state=DecLcStTestUnlock7 +sw_build_device=sim_dv +sw_images=lc_walkthrough_testunlocks _test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=2457857448 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_walkthrough_testunlocks_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_lc_walkthrough_testun locks.2457857448 |
| Directory | /workspace/1.chip_sw_lc_walkthrough_testunlocks/latest |
| Test location | /workspace/coverage/default/1.chip_sw_otbn_ecdsa_op_irq.424597684 |
| Short name | T143 |
| Test name | |
| Test status | |
| Simulation time | 17179683444 ps |
| CPU time | 3829.72 seconds |
| Started | Jun 28 08:06:40 PM PDT 24 |
| Finished | Jun 28 09:10:32 PM PDT 24 |
| Peak memory | 607204 kb |
| Host | smart-baad5a85-bc06-44ff-9d6e-7797ee66560e |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=28_000_000 +rng_srate_value=30 +sw_build_device=sim_dv +sw_images=otbn_ecdsa_op_irq_test:1:new_rules,test_ rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ random_seed=424597684 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_otbn_ecdsa_op_irq.424597684 |
| Directory | /workspace/1.chip_sw_otbn_ecdsa_op_irq/latest |
| Test location | /workspace/coverage/default/1.chip_sw_otbn_ecdsa_op_irq_jitter_en.4227309004 |
| Short name | T1126 |
| Test name | |
| Test status | |
| Simulation time | 18766594940 ps |
| CPU time | 3999.93 seconds |
| Started | Jun 28 08:07:08 PM PDT 24 |
| Finished | Jun 28 09:13:50 PM PDT 24 |
| Peak memory | 609312 kb |
| Host | smart-95d9678e-4bcc-4829-b624-23fb4222fdb2 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=33_000_000 +rng_srate_value=30 +en_jitter=1 +sw_build_device=sim_dv +sw_images=otbn_ecdsa_op_irq_test:1:ne w_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/ sim.tcl +ntb_random_seed=4227309004 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tg l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_otbn_ecdsa_op_irq_jitter_en.4227309004 |
| Directory | /workspace/1.chip_sw_otbn_ecdsa_op_irq_jitter_en/latest |
| Test location | /workspace/coverage/default/1.chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq.3622579181 |
| Short name | T1000 |
| Test name | |
| Test status | |
| Simulation time | 24519262183 ps |
| CPU time | 3790.54 seconds |
| Started | Jun 28 08:08:14 PM PDT 24 |
| Finished | Jun 28 09:11:26 PM PDT 24 |
| Peak memory | 609328 kb |
| Host | smart-fa7929ca-3a2d-456b-82d2-1e07dc95466f |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=33_000_000 +rng_srate_value=30 +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=otbn_e cdsa_op_irq_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/ repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3622579181 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_otbn_ecdsa_op_irq_jitter_en_redu ced_freq.3622579181 |
| Directory | /workspace/1.chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq/latest |
| Test location | /workspace/coverage/default/1.chip_sw_otbn_mem_scramble.2539970103 |
| Short name | T102 |
| Test name | |
| Test status | |
| Simulation time | 3119726392 ps |
| CPU time | 466.03 seconds |
| Started | Jun 28 08:10:49 PM PDT 24 |
| Finished | Jun 28 08:18:36 PM PDT 24 |
| Peak memory | 609172 kb |
| Host | smart-b184cab0-639f-41f6-9012-a48708e2c7dc |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=15_000_000 +en_scb_tl_err_chk=0 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=otbn _mem_scramble_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2539970103 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_otbn_mem_scramble.2539970103 |
| Directory | /workspace/1.chip_sw_otbn_mem_scramble/latest |
| Test location | /workspace/coverage/default/1.chip_sw_otbn_randomness.3726953704 |
| Short name | T982 |
| Test name | |
| Test status | |
| Simulation time | 5449664770 ps |
| CPU time | 958.98 seconds |
| Started | Jun 28 08:11:22 PM PDT 24 |
| Finished | Jun 28 08:27:22 PM PDT 24 |
| Peak memory | 609384 kb |
| Host | smart-a7b407d7-7b0c-4183-8123-8876c836ed15 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +rng_srate_value=30 +sw_build_device=sim_dv +sw_images=otbn_randomness_test:1:new_rules,test_ro m:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=3726953704 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_otbn_randomness.3726953704 |
| Directory | /workspace/1.chip_sw_otbn_randomness/latest |
| Test location | /workspace/coverage/default/1.chip_sw_otbn_smoketest.2144235333 |
| Short name | T1042 |
| Test name | |
| Test status | |
| Simulation time | 5710608480 ps |
| CPU time | 1120.5 seconds |
| Started | Jun 28 08:13:04 PM PDT 24 |
| Finished | Jun 28 08:31:45 PM PDT 24 |
| Peak memory | 607240 kb |
| Host | smart-d15d036d-024a-43e1-b73a-e8ceb3ca6226 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=otbn_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2144235333 -assert nopostproc +UVM_TESTNAME=chi p_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul l -cm_name 1.chip_sw_otbn_smoketest.2144235333 |
| Directory | /workspace/1.chip_sw_otbn_smoketest/latest |
| Test location | /workspace/coverage/default/1.chip_sw_otp_ctrl_ecc_error_vendor_test.1556538451 |
| Short name | T1279 |
| Test name | |
| Test status | |
| Simulation time | 2779731107 ps |
| CPU time | 185.38 seconds |
| Started | Jun 28 08:06:01 PM PDT 24 |
| Finished | Jun 28 08:09:07 PM PDT 24 |
| Peak memory | 609144 kb |
| Host | smart-2e089048-fcc8-421c-9bee-a783be71f43e |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=otp_ctrl_vendor_test_ecc_error_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1556538451 -assert nopostp roc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_otp_ctrl_vendor_test_ecc_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_otp_ctrl_ecc_error_vendor_test.1556538451 |
| Directory | /workspace/1.chip_sw_otp_ctrl_ecc_error_vendor_test/latest |
| Test location | /workspace/coverage/default/1.chip_sw_otp_ctrl_lc_signals_dev.158313442 |
| Short name | T1299 |
| Test name | |
| Test status | |
| Simulation time | 7101114680 ps |
| CPU time | 1238.49 seconds |
| Started | Jun 28 08:03:47 PM PDT 24 |
| Finished | Jun 28 08:24:27 PM PDT 24 |
| Peak memory | 609196 kb |
| Host | smart-f9385276-55d6-44ac-84e5-ba11a2108bc4 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStDev +otp_clear_secret2=1 +sw_build_device=sim_dv +sw_images=otp_ctrl_lc_signals_test:1:new_rules,tes t_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +nt b_random_seed=158313442 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_otp_ctrl_lc_signals_dev.158313442 |
| Directory | /workspace/1.chip_sw_otp_ctrl_lc_signals_dev/latest |
| Test location | /workspace/coverage/default/1.chip_sw_otp_ctrl_lc_signals_prod.2512474561 |
| Short name | T911 |
| Test name | |
| Test status | |
| Simulation time | 6966509928 ps |
| CPU time | 1496.03 seconds |
| Started | Jun 28 08:04:35 PM PDT 24 |
| Finished | Jun 28 08:29:32 PM PDT 24 |
| Peak memory | 609160 kb |
| Host | smart-9338db77-5d11-40aa-ab82-ad1753e29442 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStProd +otp_clear_secret2=1 +sw_build_device=sim_dv +sw_images=otp_ctrl_lc_signals_test:1:new_rules,te st_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n tb_random_seed=2512474561 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_otp_ctrl_lc_signals_prod.2512474561 |
| Directory | /workspace/1.chip_sw_otp_ctrl_lc_signals_prod/latest |
| Test location | /workspace/coverage/default/1.chip_sw_otp_ctrl_lc_signals_rma.2716320890 |
| Short name | T1191 |
| Test name | |
| Test status | |
| Simulation time | 7649530786 ps |
| CPU time | 1279.62 seconds |
| Started | Jun 28 08:05:43 PM PDT 24 |
| Finished | Jun 28 08:27:04 PM PDT 24 |
| Peak memory | 609172 kb |
| Host | smart-14c2f76f-f278-4fd5-9f9d-123cf5503384 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStRma +otp_clear_secret2=1 +sw_build_device=sim_dv +sw_images=otp_ctrl_lc_signals_test:1:new_rules,tes t_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +nt b_random_seed=2716320890 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_otp_ctrl_lc_signals_rma.2716320890 |
| Directory | /workspace/1.chip_sw_otp_ctrl_lc_signals_rma/latest |
| Test location | /workspace/coverage/default/1.chip_sw_otp_ctrl_lc_signals_test_unlocked0.1274456771 |
| Short name | T993 |
| Test name | |
| Test status | |
| Simulation time | 4076111960 ps |
| CPU time | 687.96 seconds |
| Started | Jun 28 08:06:19 PM PDT 24 |
| Finished | Jun 28 08:17:49 PM PDT 24 |
| Peak memory | 609196 kb |
| Host | smart-135743b8-435d-458a-8f9a-01f928252fac |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStTestUnlocked0 +otp_clear_secret2=1 +sw_build_device=sim_dv +sw_images=otp_ctrl_lc_signals_test:1:new _rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/s im.tcl +ntb_random_seed=1274456771 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_otp_ctrl_lc_signals_test_unlocked0.1274456771 |
| Directory | /workspace/1.chip_sw_otp_ctrl_lc_signals_test_unlocked0/latest |
| Test location | /workspace/coverage/default/1.chip_sw_otp_ctrl_smoketest.2503721246 |
| Short name | T1204 |
| Test name | |
| Test status | |
| Simulation time | 3206004720 ps |
| CPU time | 257.25 seconds |
| Started | Jun 28 08:14:06 PM PDT 24 |
| Finished | Jun 28 08:18:24 PM PDT 24 |
| Peak memory | 609176 kb |
| Host | smart-cdb12b1f-93e3-42ab-a428-459ff729e1b7 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=otp_ctrl_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2503721246 -assert nopostproc +UVM_TESTNAME =chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 1.chip_sw_otp_ctrl_smoketest.2503721246 |
| Directory | /workspace/1.chip_sw_otp_ctrl_smoketest/latest |
| Test location | /workspace/coverage/default/1.chip_sw_pattgen_ios.2440982089 |
| Short name | T345 |
| Test name | |
| Test status | |
| Simulation time | 2474135996 ps |
| CPU time | 293.33 seconds |
| Started | Jun 28 08:06:28 PM PDT 24 |
| Finished | Jun 28 08:11:22 PM PDT 24 |
| Peak memory | 607656 kb |
| Host | smart-f3094930-38ef-4797-853c-fb7a7362dfc1 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=5_000_000 +sw_build_device=sim_dv +sw_images=pattgen_ios_test:1:new_rules,test_rom:0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2440982089 -ass ert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_patt_ios_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/c overage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pattgen_ios.2440982089 |
| Directory | /workspace/1.chip_sw_pattgen_ios/latest |
| Test location | /workspace/coverage/default/1.chip_sw_plic_sw_irq.4199358550 |
| Short name | T655 |
| Test name | |
| Test status | |
| Simulation time | 3195934352 ps |
| CPU time | 359.69 seconds |
| Started | Jun 28 08:06:57 PM PDT 24 |
| Finished | Jun 28 08:12:59 PM PDT 24 |
| Peak memory | 607116 kb |
| Host | smart-189c36fb-7710-40e5-95ed-add644f8fe0a |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=plic_sw_irq_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4199358550 -assert nopostproc +UVM_TESTNAME=c hip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n ull -cm_name 1.chip_sw_plic_sw_irq.4199358550 |
| Directory | /workspace/1.chip_sw_plic_sw_irq/latest |
| Test location | /workspace/coverage/default/1.chip_sw_power_idle_load.3497068881 |
| Short name | T1091 |
| Test name | |
| Test status | |
| Simulation time | 5034752984 ps |
| CPU time | 879.73 seconds |
| Started | Jun 28 08:09:07 PM PDT 24 |
| Finished | Jun 28 08:23:48 PM PDT 24 |
| Peak memory | 607908 kb |
| Host | smart-fc6d7f8e-eae0-4475-950b-817674f0c1ff |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=chip_power_idle_load:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3497068881 -assert nopostproc +UVM_TESTNA ME=chip_base_test +UVM_TEST_SEQ=chip_sw_power_idle_load_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_power_idle_load.3497068881 |
| Directory | /workspace/1.chip_sw_power_idle_load/latest |
| Test location | /workspace/coverage/default/1.chip_sw_power_sleep_load.2712266282 |
| Short name | T1285 |
| Test name | |
| Test status | |
| Simulation time | 9616151250 ps |
| CPU time | 482.12 seconds |
| Started | Jun 28 08:10:24 PM PDT 24 |
| Finished | Jun 28 08:18:27 PM PDT 24 |
| Peak memory | 608248 kb |
| Host | smart-f500f97a-4f54-4574-ab68-5be25b09182b |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=chip_power_sleep_load:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2712266282 -assert nopostproc +UVM_TESTN AME=chip_base_test +UVM_TEST_SEQ=chip_sw_power_sleep_load_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v db -cm_log /dev/null -cm_name 1.chip_sw_power_sleep_load.2712266282 |
| Directory | /workspace/1.chip_sw_power_sleep_load/latest |
| Test location | /workspace/coverage/default/1.chip_sw_pwrmgr_all_reset_reqs.1145867487 |
| Short name | T510 |
| Test name | |
| Test status | |
| Simulation time | 8918154904 ps |
| CPU time | 1450.44 seconds |
| Started | Jun 28 08:05:48 PM PDT 24 |
| Finished | Jun 28 08:30:00 PM PDT 24 |
| Peak memory | 609000 kb |
| Host | smart-b70cb247-cd72-43ff-9590-e62a40048249 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=50_000_000 +sw_build_device=sim_dv +sw_images=pwrmgr_all_reset_reqs_test:1:new_rules,test_rom:0 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1145 867487 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_deep_sleep_all_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_all_reset_reqs.1145867487 |
| Directory | /workspace/1.chip_sw_pwrmgr_all_reset_reqs/latest |
| Test location | /workspace/coverage/default/1.chip_sw_pwrmgr_b2b_sleep_reset_req.844585343 |
| Short name | T1144 |
| Test name | |
| Test status | |
| Simulation time | 27034316395 ps |
| CPU time | 2521.08 seconds |
| Started | Jun 28 08:11:18 PM PDT 24 |
| Finished | Jun 28 08:53:22 PM PDT 24 |
| Peak memory | 608204 kb |
| Host | smart-40f09985-0e5e-4895-ba9b-980d07289f69 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=35_000_000 +sw_build_device=sim_dv +sw_images=pwrmgr_b2b_sleep_reset_test:1:new_rules,test_rom:0 +cdc_inst rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=844 585343 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_repeat_reset_wkup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_b2b_sleep_reset_req.844585343 |
| Directory | /workspace/1.chip_sw_pwrmgr_b2b_sleep_reset_req/latest |
| Test location | /workspace/coverage/default/1.chip_sw_pwrmgr_deep_sleep_all_reset_reqs.1708564638 |
| Short name | T916 |
| Test name | |
| Test status | |
| Simulation time | 14021092920 ps |
| CPU time | 1591.23 seconds |
| Started | Jun 28 08:05:21 PM PDT 24 |
| Finished | Jun 28 08:31:56 PM PDT 24 |
| Peak memory | 609004 kb |
| Host | smart-12009067-89eb-4c20-8461-bac041e572bc |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=50_000_000 +sw_build_device=sim_dv +sw_images=pwrmgr_deep_sleep_all_reset_reqs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=1708564638 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_deep_sleep_all_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_deep_sleep_all_reset_reqs.1708564638 |
| Directory | /workspace/1.chip_sw_pwrmgr_deep_sleep_all_reset_reqs/latest |
| Test location | /workspace/coverage/default/1.chip_sw_pwrmgr_deep_sleep_all_wake_ups.2577538039 |
| Short name | T98 |
| Test name | |
| Test status | |
| Simulation time | 24208780264 ps |
| CPU time | 1813.41 seconds |
| Started | Jun 28 08:10:22 PM PDT 24 |
| Finished | Jun 28 08:40:37 PM PDT 24 |
| Peak memory | 608476 kb |
| Host | smart-0c60e6d3-c87a-4ecd-8bf5-5250b0b27b24 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=pwrmgr_deep_sleep_all_wake_ups:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 2577538039 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_pwrmgr_deep_sleep_all_wake_ups_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_deep_sleep_all_wake_ups.2577538039 |
| Directory | /workspace/1.chip_sw_pwrmgr_deep_sleep_all_wake_ups/latest |
| Test location | /workspace/coverage/default/1.chip_sw_pwrmgr_deep_sleep_por_reset.598628676 |
| Short name | T877 |
| Test name | |
| Test status | |
| Simulation time | 9927926040 ps |
| CPU time | 812.36 seconds |
| Started | Jun 28 08:03:55 PM PDT 24 |
| Finished | Jun 28 08:17:30 PM PDT 24 |
| Peak memory | 608360 kb |
| Host | smart-15ec6e21-5d94-464f-a339-e69a1273c026 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_deep_sleep_por_reset_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=598628676 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sleep_por_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/ default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_deep_sleep_por_reset.598628676 |
| Directory | /workspace/1.chip_sw_pwrmgr_deep_sleep_por_reset/latest |
| Test location | /workspace/coverage/default/1.chip_sw_pwrmgr_deep_sleep_power_glitch_reset.62742484 |
| Short name | T1024 |
| Test name | |
| Test status | |
| Simulation time | 7822675560 ps |
| CPU time | 524.84 seconds |
| Started | Jun 28 08:05:51 PM PDT 24 |
| Finished | Jun 28 08:14:37 PM PDT 24 |
| Peak memory | 615400 kb |
| Host | smart-4e633423-b207-4708-aee2-4c7bea312b3d |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=pwrmgr_deep_sleep_power_glitch_test:1:new_rules,test_rom :0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=62742484 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_deep_power_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_deep_sleep_power_glitch_reset.62742484 |
| Directory | /workspace/1.chip_sw_pwrmgr_deep_sleep_power_glitch_reset/latest |
| Test location | /workspace/coverage/default/1.chip_sw_pwrmgr_full_aon_reset.2725011708 |
| Short name | T137 |
| Test name | |
| Test status | |
| Simulation time | 6251605128 ps |
| CPU time | 490.92 seconds |
| Started | Jun 28 08:05:25 PM PDT 24 |
| Finished | Jun 28 08:13:38 PM PDT 24 |
| Peak memory | 609156 kb |
| Host | smart-6fbff66f-55dd-4c54-b817-ce35228525ee |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=rstmgr_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2725011708 -assert nopostproc +UVM_TESTNAME=c hip_base_test +UVM_TEST_SEQ=chip_sw_full_aon_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_ log /dev/null -cm_name 1.chip_sw_pwrmgr_full_aon_reset.2725011708 |
| Directory | /workspace/1.chip_sw_pwrmgr_full_aon_reset/latest |
| Test location | /workspace/coverage/default/1.chip_sw_pwrmgr_lowpower_cancel.1501483994 |
| Short name | T336 |
| Test name | |
| Test status | |
| Simulation time | 4244254756 ps |
| CPU time | 377.53 seconds |
| Started | Jun 28 08:10:56 PM PDT 24 |
| Finished | Jun 28 08:17:14 PM PDT 24 |
| Peak memory | 609236 kb |
| Host | smart-9f5a6eb8-a57d-4eea-9351-458afa945280 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_lowpower_cancel_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1501483994 -assert nopostproc +UVM _TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm _log /dev/null -cm_name 1.chip_sw_pwrmgr_lowpower_cancel.1501483994 |
| Directory | /workspace/1.chip_sw_pwrmgr_lowpower_cancel/latest |
| Test location | /workspace/coverage/default/1.chip_sw_pwrmgr_main_power_glitch_reset.197473929 |
| Short name | T1061 |
| Test name | |
| Test status | |
| Simulation time | 5333407165 ps |
| CPU time | 366.41 seconds |
| Started | Jun 28 08:05:47 PM PDT 24 |
| Finished | Jun 28 08:11:55 PM PDT 24 |
| Peak memory | 615396 kb |
| Host | smart-b460ef42-76d7-499f-a287-8754738c0046 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=pwrmgr_main_power_glitch_test:1:new_rules,test_rom:0 +cd c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se ed=197473929 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_main_power_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_main_power_glitch_reset.197473929 |
| Directory | /workspace/1.chip_sw_pwrmgr_main_power_glitch_reset/latest |
| Test location | /workspace/coverage/default/1.chip_sw_pwrmgr_normal_sleep_all_reset_reqs.826568280 |
| Short name | T1102 |
| Test name | |
| Test status | |
| Simulation time | 13090834952 ps |
| CPU time | 1807.67 seconds |
| Started | Jun 28 08:04:39 PM PDT 24 |
| Finished | Jun 28 08:34:49 PM PDT 24 |
| Peak memory | 609408 kb |
| Host | smart-177fc1d5-66f7-459e-b180-c2a6a9df8fd5 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_normal_sleep_all_reset_reqs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=826568280 -assert nopo stproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_deep_sleep_all_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_normal_sleep_all_reset_reqs.826568280 |
| Directory | /workspace/1.chip_sw_pwrmgr_normal_sleep_all_reset_reqs/latest |
| Test location | /workspace/coverage/default/1.chip_sw_pwrmgr_normal_sleep_all_wake_ups.4280149669 |
| Short name | T416 |
| Test name | |
| Test status | |
| Simulation time | 7269727144 ps |
| CPU time | 493.39 seconds |
| Started | Jun 28 08:08:28 PM PDT 24 |
| Finished | Jun 28 08:16:43 PM PDT 24 |
| Peak memory | 608196 kb |
| Host | smart-caab9f23-2b87-4a4f-912a-ecff8e282c7a |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_normal_sleep_all_wake_ups:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4280149669 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_pwrmgr_deep_sleep_all_wake_ups_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_normal_sleep_all_wake_ups.4280149669 |
| Directory | /workspace/1.chip_sw_pwrmgr_normal_sleep_all_wake_ups/latest |
| Test location | /workspace/coverage/default/1.chip_sw_pwrmgr_normal_sleep_por_reset.3299152864 |
| Short name | T1143 |
| Test name | |
| Test status | |
| Simulation time | 6190824840 ps |
| CPU time | 458.15 seconds |
| Started | Jun 28 08:06:06 PM PDT 24 |
| Finished | Jun 28 08:13:45 PM PDT 24 |
| Peak memory | 607352 kb |
| Host | smart-9c05c579-25c3-4a3a-a118-2841209a7468 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_normal_sleep_por_reset_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3299152864 -assert nopostpr oc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sleep_por_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera ge/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_normal_sleep_por_reset.3299152864 |
| Directory | /workspace/1.chip_sw_pwrmgr_normal_sleep_por_reset/latest |
| Test location | /workspace/coverage/default/1.chip_sw_pwrmgr_random_sleep_all_reset_reqs.1828750099 |
| Short name | T89 |
| Test name | |
| Test status | |
| Simulation time | 24233418943 ps |
| CPU time | 2692.43 seconds |
| Started | Jun 28 08:07:37 PM PDT 24 |
| Finished | Jun 28 08:52:31 PM PDT 24 |
| Peak memory | 609376 kb |
| Host | smart-fa179ae1-ba8f-43b3-a0c8-6aece6ea8d3d |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=50_000_000 +sw_build_device=sim_dv +sw_images=pwrmgr_random_sleep_all_reset_reqs_test:1:new_rules,test_rom :0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=1828750099 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_deep_sleep_all_reset_vseq +en_cov=1 -cm line+cond+fsm+tg l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_random_sleep_all_reset_reqs.1828750099 |
| Directory | /workspace/1.chip_sw_pwrmgr_random_sleep_all_reset_reqs/latest |
| Test location | /workspace/coverage/default/1.chip_sw_pwrmgr_random_sleep_all_wake_ups.1508750249 |
| Short name | T10 |
| Test name | |
| Test status | |
| Simulation time | 25375295552 ps |
| CPU time | 1714.99 seconds |
| Started | Jun 28 08:05:33 PM PDT 24 |
| Finished | Jun 28 08:34:09 PM PDT 24 |
| Peak memory | 608492 kb |
| Host | smart-e51af150-89f1-421a-afd3-a940b084bec3 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +do_random=1 +sw_build_device=sim_dv +sw_images=pwrmgr_random_sleep_all_wake_ups:1:new_rules,te st_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n tb_random_seed=1508750249 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_pwrmgr_deep_sleep_all_wake_ups_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_random_sleep_all_wake_ups.1508750249 |
| Directory | /workspace/1.chip_sw_pwrmgr_random_sleep_all_wake_ups/latest |
| Test location | /workspace/coverage/default/1.chip_sw_pwrmgr_random_sleep_power_glitch_reset.3555894433 |
| Short name | T1244 |
| Test name | |
| Test status | |
| Simulation time | 31520037507 ps |
| CPU time | 2886.25 seconds |
| Started | Jun 28 08:05:44 PM PDT 24 |
| Finished | Jun 28 08:53:52 PM PDT 24 |
| Peak memory | 609852 kb |
| Host | smart-27cd01a7-6a86-4733-81dd-7e18da6bcc9a |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_test_timeout_ns=24_000_000 +sw_build_device=sim_dv +sw_images=pwrmgr_random_sleep_power _glitch_reset_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3555894433 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_random_power_glit ch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_random_s leep_power_glitch_reset.3555894433 |
| Directory | /workspace/1.chip_sw_pwrmgr_random_sleep_power_glitch_reset/latest |
| Test location | /workspace/coverage/default/1.chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up.3911690878 |
| Short name | T365 |
| Test name | |
| Test status | |
| Simulation time | 5820224884 ps |
| CPU time | 500.27 seconds |
| Started | Jun 28 08:10:59 PM PDT 24 |
| Finished | Jun 28 08:19:21 PM PDT 24 |
| Peak memory | 609320 kb |
| Host | smart-b336dd9a-8014-44c4-a6a3-73f96c597547 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +do_random=1 +sw_build_device=sim_dv +sw_images=pwrmgr_sensor_ctrl_deep_sleep_wake_up:1:new_rul es,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t cl +ntb_random_seed=3911690878 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_sensor_ctrl_deep_s leep_wake_up.3911690878 |
| Directory | /workspace/1.chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up/latest |
| Test location | /workspace/coverage/default/1.chip_sw_pwrmgr_sleep_disabled.3025282771 |
| Short name | T654 |
| Test name | |
| Test status | |
| Simulation time | 2972050152 ps |
| CPU time | 201.54 seconds |
| Started | Jun 28 08:05:02 PM PDT 24 |
| Finished | Jun 28 08:08:24 PM PDT 24 |
| Peak memory | 609188 kb |
| Host | smart-86bb5454-c16f-4e7d-bdb3-776963ce9752 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_sleep_disabled_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3025282771 -assert nopostproc +UVM_ TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_ log /dev/null -cm_name 1.chip_sw_pwrmgr_sleep_disabled.3025282771 |
| Directory | /workspace/1.chip_sw_pwrmgr_sleep_disabled/latest |
| Test location | /workspace/coverage/default/1.chip_sw_pwrmgr_sleep_power_glitch_reset.3043804508 |
| Short name | T1085 |
| Test name | |
| Test status | |
| Simulation time | 5975780055 ps |
| CPU time | 580.58 seconds |
| Started | Jun 28 08:05:45 PM PDT 24 |
| Finished | Jun 28 08:15:27 PM PDT 24 |
| Peak memory | 615512 kb |
| Host | smart-4e68f310-7101-4add-bac0-bcebfbeed118 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=pwrmgr_sleep_power_glitch_test:1:new_rules,test_rom:0 +c dc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_s eed=3043804508 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_main_power_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_sleep_power_glitch_reset.3043804508 |
| Directory | /workspace/1.chip_sw_pwrmgr_sleep_power_glitch_reset/latest |
| Test location | /workspace/coverage/default/1.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup.2652429133 |
| Short name | T130 |
| Test name | |
| Test status | |
| Simulation time | 5100727560 ps |
| CPU time | 401.1 seconds |
| Started | Jun 28 08:04:29 PM PDT 24 |
| Finished | Jun 28 08:11:11 PM PDT 24 |
| Peak memory | 609208 kb |
| Host | smart-3a29e682-d58e-4f65-a175-1f4244e4345b |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=8_000_000 +sw_build_device=sim_dv +sw_images=sensor_ctrl_wakeup_test:1:new_rules,test_rom:0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26524291 33 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac e/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup.2652429133 |
| Directory | /workspace/1.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup/latest |
| Test location | /workspace/coverage/default/1.chip_sw_pwrmgr_sleep_wake_5_bug.3076080162 |
| Short name | T1162 |
| Test name | |
| Test status | |
| Simulation time | 5687411320 ps |
| CPU time | 419.2 seconds |
| Started | Jun 28 08:08:55 PM PDT 24 |
| Finished | Jun 28 08:15:55 PM PDT 24 |
| Peak memory | 608396 kb |
| Host | smart-fbb809cc-e3ad-4808-b639-97365e7da847 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +do_random=1 +sw_build_device=sim_dv +sw_images=pwrmgr_sleep_wake_5_bug_test:1:new_rules,test_r om:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r andom_seed=3076080162 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_sleep_wake_5_bug.3076080162 |
| Directory | /workspace/1.chip_sw_pwrmgr_sleep_wake_5_bug/latest |
| Test location | /workspace/coverage/default/1.chip_sw_pwrmgr_smoketest.1855210578 |
| Short name | T1233 |
| Test name | |
| Test status | |
| Simulation time | 5324420400 ps |
| CPU time | 374.06 seconds |
| Started | Jun 28 08:14:54 PM PDT 24 |
| Finished | Jun 28 08:21:12 PM PDT 24 |
| Peak memory | 607992 kb |
| Host | smart-98e75497-fffc-4da5-9167-897baaebb54d |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=10000000 +sw_build_device=sim_dv +sw_images=pwrmgr_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1855210578 -asse rt nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera ge/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_smoketest.1855210578 |
| Directory | /workspace/1.chip_sw_pwrmgr_smoketest/latest |
| Test location | /workspace/coverage/default/1.chip_sw_pwrmgr_sysrst_ctrl_reset.3115892647 |
| Short name | T951 |
| Test name | |
| Test status | |
| Simulation time | 6560431456 ps |
| CPU time | 1078.14 seconds |
| Started | Jun 28 08:06:28 PM PDT 24 |
| Finished | Jun 28 08:24:27 PM PDT 24 |
| Peak memory | 608276 kb |
| Host | smart-23e7340a-7f8b-45a5-a545-2d62b6d012db |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_sysrst_ctrl_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3115892647 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_sysrst_ctrl_reset.3115892647 |
| Directory | /workspace/1.chip_sw_pwrmgr_sysrst_ctrl_reset/latest |
| Test location | /workspace/coverage/default/1.chip_sw_pwrmgr_usb_clk_disabled_when_active.2378126032 |
| Short name | T386 |
| Test name | |
| Test status | |
| Simulation time | 5209292356 ps |
| CPU time | 463.08 seconds |
| Started | Jun 28 08:06:31 PM PDT 24 |
| Finished | Jun 28 08:14:15 PM PDT 24 |
| Peak memory | 609244 kb |
| Host | smart-aeed3d94-ef8e-4acc-8ef8-88754962b395 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_usb_clk_disabled_when_active_test:1:new_rules,test_rom:0 +cdc_instrumentation_enable d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2378126032 -assert no postproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de fault.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_usb_clk_disabled_when_active.2378126032 |
| Directory | /workspace/1.chip_sw_pwrmgr_usb_clk_disabled_when_active/latest |
| Test location | /workspace/coverage/default/1.chip_sw_pwrmgr_usbdev_smoketest.232237216 |
| Short name | T1288 |
| Test name | |
| Test status | |
| Simulation time | 5849601906 ps |
| CPU time | 455.44 seconds |
| Started | Jun 28 08:13:17 PM PDT 24 |
| Finished | Jun 28 08:20:54 PM PDT 24 |
| Peak memory | 609240 kb |
| Host | smart-6e057341-262d-4ab1-9c43-64a3f9714a8c |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_usbdev_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=232237216 -assert nopostproc +UVM_TEST NAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_usbdev_smoketest.232237216 |
| Directory | /workspace/1.chip_sw_pwrmgr_usbdev_smoketest/latest |
| Test location | /workspace/coverage/default/1.chip_sw_pwrmgr_wdog_reset.688840469 |
| Short name | T1045 |
| Test name | |
| Test status | |
| Simulation time | 5201504440 ps |
| CPU time | 654.51 seconds |
| Started | Jun 28 08:06:05 PM PDT 24 |
| Finished | Jun 28 08:17:01 PM PDT 24 |
| Peak memory | 609184 kb |
| Host | smart-d643f2c1-fa78-4e51-8e05-0dd233d6f178 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=pwrmgr_wdog_reset_reqs_test:1:new_rules,test_rom:0 +cdc_inst rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=688 840469 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work space/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_wdog_reset.688840469 |
| Directory | /workspace/1.chip_sw_pwrmgr_wdog_reset/latest |
| Test location | /workspace/coverage/default/1.chip_sw_rom_ctrl_integrity_check.788579283 |
| Short name | T1248 |
| Test name | |
| Test status | |
| Simulation time | 8217470796 ps |
| CPU time | 715.87 seconds |
| Started | Jun 28 08:08:07 PM PDT 24 |
| Finished | Jun 28 08:20:04 PM PDT 24 |
| Peak memory | 609228 kb |
| Host | smart-0b891b56-5798-4e62-baf0-81ec54dd29c5 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=rom_ctrl_integrity_check_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=788579283 -assert nopostproc +UV M_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_ctrl_integrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov erage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_rom_ctrl_integrity_check.788579283 |
| Directory | /workspace/1.chip_sw_rom_ctrl_integrity_check/latest |
| Test location | /workspace/coverage/default/1.chip_sw_rstmgr_cpu_info.1706494493 |
| Short name | T243 |
| Test name | |
| Test status | |
| Simulation time | 6756557230 ps |
| CPU time | 819.73 seconds |
| Started | Jun 28 08:06:43 PM PDT 24 |
| Finished | Jun 28 08:20:26 PM PDT 24 |
| Peak memory | 609220 kb |
| Host | smart-b8dda215-ece9-489c-b546-19ac4b598aa5 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=rstmgr_cpu_info_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1706494493 -assert nopostproc +UVM_TESTNA ME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 1.chip_sw_rstmgr_cpu_info.1706494493 |
| Directory | /workspace/1.chip_sw_rstmgr_cpu_info/latest |
| Test location | /workspace/coverage/default/1.chip_sw_rstmgr_rst_cnsty_escalation.2295173795 |
| Short name | T1115 |
| Test name | |
| Test status | |
| Simulation time | 6535230096 ps |
| CPU time | 723.37 seconds |
| Started | Jun 28 08:06:10 PM PDT 24 |
| Finished | Jun 28 08:18:15 PM PDT 24 |
| Peak memory | 639396 kb |
| Host | smart-4601f1fa-3441-4a12-a050-b5d14605fd78 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 2295173795 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rstmgr_cnsty_fault_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_rstmgr_rst_cnsty_escalation.2295173795 |
| Directory | /workspace/1.chip_sw_rstmgr_rst_cnsty_escalation/latest |
| Test location | /workspace/coverage/default/1.chip_sw_rstmgr_smoketest.1448399073 |
| Short name | T955 |
| Test name | |
| Test status | |
| Simulation time | 2580460180 ps |
| CPU time | 332.85 seconds |
| Started | Jun 28 08:14:07 PM PDT 24 |
| Finished | Jun 28 08:19:42 PM PDT 24 |
| Peak memory | 607252 kb |
| Host | smart-8c3e1144-53eb-4b59-90fc-deaaedf64e36 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=rstmgr_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1448399073 -assert nopostproc +UVM_TESTNAME=c hip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n ull -cm_name 1.chip_sw_rstmgr_smoketest.1448399073 |
| Directory | /workspace/1.chip_sw_rstmgr_smoketest/latest |
| Test location | /workspace/coverage/default/1.chip_sw_rstmgr_sw_req.2844137481 |
| Short name | T856 |
| Test name | |
| Test status | |
| Simulation time | 4365556498 ps |
| CPU time | 309.9 seconds |
| Started | Jun 28 08:05:53 PM PDT 24 |
| Finished | Jun 28 08:11:04 PM PDT 24 |
| Peak memory | 606852 kb |
| Host | smart-b07757f4-abb1-4df5-a956-7df7106268dd |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=rstmgr_sw_req_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2844137481 -assert nopostproc +UVM_TESTNAME =chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 1.chip_sw_rstmgr_sw_req.2844137481 |
| Directory | /workspace/1.chip_sw_rstmgr_sw_req/latest |
| Test location | /workspace/coverage/default/1.chip_sw_rstmgr_sw_rst.3393861351 |
| Short name | T976 |
| Test name | |
| Test status | |
| Simulation time | 2709316500 ps |
| CPU time | 245.78 seconds |
| Started | Jun 28 08:07:22 PM PDT 24 |
| Finished | Jun 28 08:11:30 PM PDT 24 |
| Peak memory | 607240 kb |
| Host | smart-a4e733d6-e2d5-4871-85d9-ae81ac4c5bcb |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=rstmgr_sw_rst_ctrl_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3393861351 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_rstmgr_sw_rst.3393861351 |
| Directory | /workspace/1.chip_sw_rstmgr_sw_rst/latest |
| Test location | /workspace/coverage/default/1.chip_sw_rv_core_ibex_address_translation.642902374 |
| Short name | T172 |
| Test name | |
| Test status | |
| Simulation time | 3171669482 ps |
| CPU time | 316.6 seconds |
| Started | Jun 28 08:09:49 PM PDT 24 |
| Finished | Jun 28 08:15:07 PM PDT 24 |
| Peak memory | 609188 kb |
| Host | smart-27bb671a-98f5-4bda-8691-d70bbd3347e8 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=7_000_000 +sw_build_device=sim_dv +sw_images=rv_core_ibex_address_translation_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=642902374 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_rv_core_ibex_address_translation.642902374 |
| Directory | /workspace/1.chip_sw_rv_core_ibex_address_translation/latest |
| Test location | /workspace/coverage/default/1.chip_sw_rv_core_ibex_icache_invalidate.1032432771 |
| Short name | T301 |
| Test name | |
| Test status | |
| Simulation time | 2780466433 ps |
| CPU time | 201.41 seconds |
| Started | Jun 28 08:07:26 PM PDT 24 |
| Finished | Jun 28 08:10:49 PM PDT 24 |
| Peak memory | 609188 kb |
| Host | smart-9bc308eb-0524-46e6-b213-0c9f6710e11c |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=rv_core_ibex_icache_invalidate_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1032432771 -assert nopostp roc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rv_core_ibex_icache_invalidate_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_rv_core_ibex_icache_invalidate.1032432771 |
| Directory | /workspace/1.chip_sw_rv_core_ibex_icache_invalidate/latest |
| Test location | /workspace/coverage/default/1.chip_sw_rv_core_ibex_lockstep_glitch.2306333499 |
| Short name | T385 |
| Test name | |
| Test status | |
| Simulation time | 2805708980 ps |
| CPU time | 164.03 seconds |
| Started | Jun 28 08:07:36 PM PDT 24 |
| Finished | Jun 28 08:10:22 PM PDT 24 |
| Peak memory | 613724 kb |
| Host | smart-8be6edf4-94cd-42c5-9bf3-c860cf7684c3 |
| User | root |
| Command | /workspace/default/simv +disable_assert_final_checks +sw_build_device=sim_dv +sw_images=aes_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2306333499 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rv_core_ibex_lockstep_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_rv_core_ibex_lockstep_glitch.2306333499 |
| Directory | /workspace/1.chip_sw_rv_core_ibex_lockstep_glitch/latest |
| Test location | /workspace/coverage/default/1.chip_sw_rv_core_ibex_nmi_irq.1780604051 |
| Short name | T509 |
| Test name | |
| Test status | |
| Simulation time | 5345325572 ps |
| CPU time | 789.99 seconds |
| Started | Jun 28 08:07:20 PM PDT 24 |
| Finished | Jun 28 08:20:33 PM PDT 24 |
| Peak memory | 609164 kb |
| Host | smart-b25f5e80-e1ea-4a82-bb2a-40cbd4c30134 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=10_000_000 +sw_build_device=sim_dv +sw_images=rv_core_ibex_nmi_irq_test:1:new_rules,test_rom:0 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17806 04051 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_rv_core_ibex_nmi_irq.1780604051 |
| Directory | /workspace/1.chip_sw_rv_core_ibex_nmi_irq/latest |
| Test location | /workspace/coverage/default/1.chip_sw_rv_core_ibex_rnd.3721952605 |
| Short name | T422 |
| Test name | |
| Test status | |
| Simulation time | 5459904722 ps |
| CPU time | 1008.97 seconds |
| Started | Jun 28 08:05:59 PM PDT 24 |
| Finished | Jun 28 08:22:50 PM PDT 24 |
| Peak memory | 609176 kb |
| Host | smart-0345b463-0e35-446c-8cc7-571a2209632c |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=20_000_000 +rng_srate_value_max=32 +sw_build_device=sim_dv +sw_images=rv_core_ibex_rnd_test:1:new_rules,te st_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n tb_random_seed=3721952605 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_rv_core_ibex_rnd.3721952605 |
| Directory | /workspace/1.chip_sw_rv_core_ibex_rnd/latest |
| Test location | /workspace/coverage/default/1.chip_sw_rv_dm_access_after_escalation_reset.3043602894 |
| Short name | T4 |
| Test name | |
| Test status | |
| Simulation time | 4692138028 ps |
| CPU time | 595.73 seconds |
| Started | Jun 28 08:08:56 PM PDT 24 |
| Finished | Jun 28 08:18:53 PM PDT 24 |
| Peak memory | 618112 kb |
| Host | smart-6bd49da3-ae54-4a64-a16e-e0c9a31ad650 |
| User | root |
| Command | /workspace/default/simv +use_jtag_dmi=1 +sw_build_device=sim_dv +sw_images=alert_handler_escalation_test:1:new_rules,test_rom:0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3043602894 -asse rt nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rv_dm_access_after_escalation_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_rv_dm_access_after_escalation_reset.3043602894 |
| Directory | /workspace/1.chip_sw_rv_dm_access_after_escalation_reset/latest |
| Test location | /workspace/coverage/default/1.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted.2891346163 |
| Short name | T237 |
| Test name | |
| Test status | |
| Simulation time | 3935313050 ps |
| CPU time | 601.64 seconds |
| Started | Jun 28 08:06:42 PM PDT 24 |
| Finished | Jun 28 08:16:46 PM PDT 24 |
| Peak memory | 614884 kb |
| Host | smart-20eada62-98fc-4123-a84f-34f935aa727f |
| User | root |
| Command | /workspace/default/simv +use_jtag_dmi=1 +sw_build_device=sim_dv +sw_images=rv_dm_ndm_reset_req_when_cpu_halted_rma:1:new_rules,test_rom:0 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=289134 6163 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rv_dm_ndm_reset_when_cpu_halted_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted.2891346163 |
| Directory | /workspace/1.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted/latest |
| Test location | /workspace/coverage/default/1.chip_sw_rv_plic_smoketest.3294803578 |
| Short name | T893 |
| Test name | |
| Test status | |
| Simulation time | 3208561916 ps |
| CPU time | 202.51 seconds |
| Started | Jun 28 08:14:52 PM PDT 24 |
| Finished | Jun 28 08:18:17 PM PDT 24 |
| Peak memory | 609176 kb |
| Host | smart-4ab467ac-99c0-405e-8303-4b8faa60667b |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=rv_plic_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3294803578 -assert nopostproc +UVM_TESTNAME= chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/ null -cm_name 1.chip_sw_rv_plic_smoketest.3294803578 |
| Directory | /workspace/1.chip_sw_rv_plic_smoketest/latest |
| Test location | /workspace/coverage/default/1.chip_sw_rv_timer_irq.2966123120 |
| Short name | T1237 |
| Test name | |
| Test status | |
| Simulation time | 2748373368 ps |
| CPU time | 234.64 seconds |
| Started | Jun 28 08:05:21 PM PDT 24 |
| Finished | Jun 28 08:09:19 PM PDT 24 |
| Peak memory | 606308 kb |
| Host | smart-4b6f9a1c-28e9-48c6-a96b-09ee46f1ca79 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=rv_timer_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2966123120 -assert nopostproc +UVM_TESTNAME =chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 1.chip_sw_rv_timer_irq.2966123120 |
| Directory | /workspace/1.chip_sw_rv_timer_irq/latest |
| Test location | /workspace/coverage/default/1.chip_sw_rv_timer_smoketest.2822300874 |
| Short name | T1236 |
| Test name | |
| Test status | |
| Simulation time | 3222488584 ps |
| CPU time | 263.7 seconds |
| Started | Jun 28 08:13:44 PM PDT 24 |
| Finished | Jun 28 08:18:10 PM PDT 24 |
| Peak memory | 607252 kb |
| Host | smart-13ec630d-cd7e-40e8-a52e-28a53ed1b386 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=rv_timer_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2822300874 -assert nopostproc +UVM_TESTNAME =chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 1.chip_sw_rv_timer_smoketest.2822300874 |
| Directory | /workspace/1.chip_sw_rv_timer_smoketest/latest |
| Test location | /workspace/coverage/default/1.chip_sw_sensor_ctrl_status.1231227667 |
| Short name | T135 |
| Test name | |
| Test status | |
| Simulation time | 2530249237 ps |
| CPU time | 250.14 seconds |
| Started | Jun 28 08:11:21 PM PDT 24 |
| Finished | Jun 28 08:15:32 PM PDT 24 |
| Peak memory | 607724 kb |
| Host | smart-28e90e12-1986-4f8b-a050-d9cb531e3baf |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=40_000_000 +sw_build_device=sim_dv +sw_images=sensor_ctrl_status_test:1:new_rules,test_rom:0 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1231227 667 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sensor_ctrl_status_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_sensor_ctrl_status.1231227667 |
| Directory | /workspace/1.chip_sw_sensor_ctrl_status/latest |
| Test location | /workspace/coverage/default/1.chip_sw_sleep_pin_wake.1291627885 |
| Short name | T14 |
| Test name | |
| Test status | |
| Simulation time | 3097303992 ps |
| CPU time | 264.25 seconds |
| Started | Jun 28 08:05:14 PM PDT 24 |
| Finished | Jun 28 08:09:41 PM PDT 24 |
| Peak memory | 607716 kb |
| Host | smart-c59d68a7-f12c-4d2d-a1d7-fbd091308644 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStProd +sw_build_device=sim_dv +sw_images=sleep_pin_wake_test:1:new_rules,test_rom:0 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1291627885 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sleep_pin_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_sleep_pin_wake.1291627885 |
| Directory | /workspace/1.chip_sw_sleep_pin_wake/latest |
| Test location | /workspace/coverage/default/1.chip_sw_sleep_pwm_pulses.2923329123 |
| Short name | T1084 |
| Test name | |
| Test status | |
| Simulation time | 9497682620 ps |
| CPU time | 1367.12 seconds |
| Started | Jun 28 08:06:07 PM PDT 24 |
| Finished | Jun 28 08:28:55 PM PDT 24 |
| Peak memory | 607316 kb |
| Host | smart-b0b819ef-503b-456e-95bc-a2f0d169f11c |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=sleep_pwm_pulses_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2923329123 -assert nopostproc +UVM_TESTN AME=chip_base_test +UVM_TEST_SEQ=chip_sw_pwm_pulses_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm _log /dev/null -cm_name 1.chip_sw_sleep_pwm_pulses.2923329123 |
| Directory | /workspace/1.chip_sw_sleep_pwm_pulses/latest |
| Test location | /workspace/coverage/default/1.chip_sw_sleep_sram_ret_contents_no_scramble.660429225 |
| Short name | T414 |
| Test name | |
| Test status | |
| Simulation time | 7314409416 ps |
| CPU time | 655.18 seconds |
| Started | Jun 28 08:09:11 PM PDT 24 |
| Finished | Jun 28 08:20:07 PM PDT 24 |
| Peak memory | 609248 kb |
| Host | smart-bf55b953-3fad-4e21-84fb-8e436e1ab986 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=20_000_000 +en_scb_tl_err_chk=0 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=sram _ctrl_sleep_sram_ret_contents_no_scramble_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=660429225 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SE Q=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_sle ep_sram_ret_contents_no_scramble.660429225 |
| Directory | /workspace/1.chip_sw_sleep_sram_ret_contents_no_scramble/latest |
| Test location | /workspace/coverage/default/1.chip_sw_sleep_sram_ret_contents_scramble.857352575 |
| Short name | T1254 |
| Test name | |
| Test status | |
| Simulation time | 9028361760 ps |
| CPU time | 713.65 seconds |
| Started | Jun 28 08:12:50 PM PDT 24 |
| Finished | Jun 28 08:24:45 PM PDT 24 |
| Peak memory | 608756 kb |
| Host | smart-1cbaefdd-51d8-4d2c-aa11-38193acaa934 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=20_000_000 +en_scb_tl_err_chk=0 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=sram _ctrl_sleep_sram_ret_contents_scramble_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=857352575 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=c hip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_sleep_ sram_ret_contents_scramble.857352575 |
| Directory | /workspace/1.chip_sw_sleep_sram_ret_contents_scramble/latest |
| Test location | /workspace/coverage/default/1.chip_sw_spi_device_pass_through.1299187409 |
| Short name | T24 |
| Test name | |
| Test status | |
| Simulation time | 6211561457 ps |
| CPU time | 702.5 seconds |
| Started | Jun 28 08:04:38 PM PDT 24 |
| Finished | Jun 28 08:16:23 PM PDT 24 |
| Peak memory | 624280 kb |
| Host | smart-6412c703-0fdc-49f6-8ac6-a09033ef1248 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=spi_passthrough_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1299187409 -assert nopostproc +UVM_TESTNA ME=chip_base_test +UVM_TEST_SEQ=chip_sw_spi_passthrough_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_spi_device_pass_through.1299187409 |
| Directory | /workspace/1.chip_sw_spi_device_pass_through/latest |
| Test location | /workspace/coverage/default/1.chip_sw_spi_device_pass_through_collision.885385558 |
| Short name | T191 |
| Test name | |
| Test status | |
| Simulation time | 4836899595 ps |
| CPU time | 583.45 seconds |
| Started | Jun 28 08:05:06 PM PDT 24 |
| Finished | Jun 28 08:14:52 PM PDT 24 |
| Peak memory | 624252 kb |
| Host | smart-1bb79dac-c12f-4932-b5ec-4a884c893238 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=spi_passthrough_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=885385558 -assert nopostproc +UVM_TESTNAM E=chip_base_test +UVM_TEST_SEQ=chip_sw_spi_passthrough_collision_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de fault.vdb -cm_log /dev/null -cm_name 1.chip_sw_spi_device_pass_through_collision.885385558 |
| Directory | /workspace/1.chip_sw_spi_device_pass_through_collision/latest |
| Test location | /workspace/coverage/default/1.chip_sw_spi_device_tpm.2810683354 |
| Short name | T48 |
| Test name | |
| Test status | |
| Simulation time | 3074816306 ps |
| CPU time | 337.95 seconds |
| Started | Jun 28 08:04:16 PM PDT 24 |
| Finished | Jun 28 08:09:55 PM PDT 24 |
| Peak memory | 616500 kb |
| Host | smart-5e164eb0-56d0-40c9-a36c-416e713ec8fe |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=spi_device_tpm_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2810683354 -assert nopostproc +UVM_T ESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_spi_device_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default .vdb -cm_log /dev/null -cm_name 1.chip_sw_spi_device_tpm.2810683354 |
| Directory | /workspace/1.chip_sw_spi_device_tpm/latest |
| Test location | /workspace/coverage/default/1.chip_sw_spi_host_tx_rx.2959694241 |
| Short name | T26 |
| Test name | |
| Test status | |
| Simulation time | 3228079550 ps |
| CPU time | 210.01 seconds |
| Started | Jun 28 08:06:14 PM PDT 24 |
| Finished | Jun 28 08:09:46 PM PDT 24 |
| Peak memory | 607996 kb |
| Host | smart-2c9315a2-654d-40df-8c93-7545f0d494bc |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=spi_host_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2959694241 -assert nopostproc +UVM_TESTNAM E=chip_base_test +UVM_TEST_SEQ=chip_sw_spi_host_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb - cm_log /dev/null -cm_name 1.chip_sw_spi_host_tx_rx.2959694241 |
| Directory | /workspace/1.chip_sw_spi_host_tx_rx/latest |
| Test location | /workspace/coverage/default/1.chip_sw_sram_ctrl_execution_main.3925421605 |
| Short name | T171 |
| Test name | |
| Test status | |
| Simulation time | 6813584588 ps |
| CPU time | 912.83 seconds |
| Started | Jun 28 08:08:32 PM PDT 24 |
| Finished | Jun 28 08:23:46 PM PDT 24 |
| Peak memory | 608252 kb |
| Host | smart-ce109b62-1c17-4694-ad74-01520a21925b |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=sram_ctrl_execution_main_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3925421605 -assert nopostproc +U VM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sram_ctrl_execution_main_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co verage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_sram_ctrl_execution_main.3925421605 |
| Directory | /workspace/1.chip_sw_sram_ctrl_execution_main/latest |
| Test location | /workspace/coverage/default/1.chip_sw_sram_ctrl_scrambled_access.702826290 |
| Short name | T279 |
| Test name | |
| Test status | |
| Simulation time | 5975278900 ps |
| CPU time | 715.95 seconds |
| Started | Jun 28 08:03:55 PM PDT 24 |
| Finished | Jun 28 08:15:54 PM PDT 24 |
| Peak memory | 608832 kb |
| Host | smart-d6ce7c0f-53cf-4732-bdbc-b5a2b1e35d92 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=12_000_000 +en_scb_tl_err_chk=0 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=sram _ctrl_scrambled_access_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=702826290 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sram_ctrl _scrambled_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_ sram_ctrl_scrambled_access.702826290 |
| Directory | /workspace/1.chip_sw_sram_ctrl_scrambled_access/latest |
| Test location | /workspace/coverage/default/1.chip_sw_sram_ctrl_scrambled_access_jitter_en.4177771753 |
| Short name | T280 |
| Test name | |
| Test status | |
| Simulation time | 5560901429 ps |
| CPU time | 783.77 seconds |
| Started | Jun 28 08:11:08 PM PDT 24 |
| Finished | Jun 28 08:24:12 PM PDT 24 |
| Peak memory | 608856 kb |
| Host | smart-d558e73c-1ca4-4052-bde7-f9db44ec7955 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=12_000_000 +bypass_alert_ready_to_end_check=1 +en_jitter=1 +en_scb_tl_err_chk=0 +sw_build_device=sim_dv +s w_images=sram_ctrl_scrambled_access_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4177771753 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chi p_sw_sram_ctrl_scrambled_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n ame 1.chip_sw_sram_ctrl_scrambled_access_jitter_en.4177771753 |
| Directory | /workspace/1.chip_sw_sram_ctrl_scrambled_access_jitter_en/latest |
| Test location | /workspace/coverage/default/1.chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq.331864895 |
| Short name | T112 |
| Test name | |
| Test status | |
| Simulation time | 5791267796 ps |
| CPU time | 632.83 seconds |
| Started | Jun 28 08:11:13 PM PDT 24 |
| Finished | Jun 28 08:21:48 PM PDT 24 |
| Peak memory | 608776 kb |
| Host | smart-65697f9a-5e29-424e-8545-11128f3684c2 |
| User | root |
| Command | /workspace/default/simv +mem_sel=main +sw_test_timeout_ns=12_000_000 +bypass_alert_ready_to_end_check=1 +en_jitter=1 +en_scb_tl_err_chk=0 +cal_sys_clk _70mhz=1 +sw_build_device=sim_dv +sw_images=sram_ctrl_scrambled_access_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=331864895 -assert nopostproc +UVM_TESTNAM E=chip_base_test +UVM_TEST_SEQ=chip_sw_sram_ctrl_scrambled_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/d efault.vdb -cm_log /dev/null -cm_name 1.chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq.331864895 |
| Directory | /workspace/1.chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq/latest |
| Test location | /workspace/coverage/default/1.chip_sw_sram_ctrl_smoketest.3912682200 |
| Short name | T1107 |
| Test name | |
| Test status | |
| Simulation time | 2499755532 ps |
| CPU time | 248.49 seconds |
| Started | Jun 28 08:14:05 PM PDT 24 |
| Finished | Jun 28 08:18:14 PM PDT 24 |
| Peak memory | 607120 kb |
| Host | smart-c22e6e07-172f-461f-9109-b2a4aac30f91 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=sram_ctrl_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3912682200 -assert nopostproc +UVM_TESTNAM E=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 1.chip_sw_sram_ctrl_smoketest.3912682200 |
| Directory | /workspace/1.chip_sw_sram_ctrl_smoketest/latest |
| Test location | /workspace/coverage/default/1.chip_sw_sysrst_ctrl_ec_rst_l.2488899516 |
| Short name | T33 |
| Test name | |
| Test status | |
| Simulation time | 20985648628 ps |
| CPU time | 3853.73 seconds |
| Started | Jun 28 08:05:47 PM PDT 24 |
| Finished | Jun 28 09:10:03 PM PDT 24 |
| Peak memory | 608264 kb |
| Host | smart-e73b0777-b427-4e0e-87ba-155cff71c514 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=sysrst_ctrl_ec_rst_l_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2488899516 -assert nopostproc +UVM_T ESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_ec_rst_l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/d efault.vdb -cm_log /dev/null -cm_name 1.chip_sw_sysrst_ctrl_ec_rst_l.2488899516 |
| Directory | /workspace/1.chip_sw_sysrst_ctrl_ec_rst_l/latest |
| Test location | /workspace/coverage/default/1.chip_sw_sysrst_ctrl_in_irq.1455924996 |
| Short name | T201 |
| Test name | |
| Test status | |
| Simulation time | 5058621040 ps |
| CPU time | 583.96 seconds |
| Started | Jun 28 08:10:39 PM PDT 24 |
| Finished | Jun 28 08:20:26 PM PDT 24 |
| Peak memory | 612508 kb |
| Host | smart-5d159995-1dec-4ed4-96cc-a0e79a625f55 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=sysrst_ctrl_in_irq_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1455924996 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_in_irq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau lt.vdb -cm_log /dev/null -cm_name 1.chip_sw_sysrst_ctrl_in_irq.1455924996 |
| Directory | /workspace/1.chip_sw_sysrst_ctrl_in_irq/latest |
| Test location | /workspace/coverage/default/1.chip_sw_sysrst_ctrl_inputs.157830258 |
| Short name | T1214 |
| Test name | |
| Test status | |
| Simulation time | 2621361660 ps |
| CPU time | 292.49 seconds |
| Started | Jun 28 08:07:03 PM PDT 24 |
| Finished | Jun 28 08:11:57 PM PDT 24 |
| Peak memory | 611960 kb |
| Host | smart-d4162481-8631-4377-830f-8877bf0290b9 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=sysrst_ctrl_inputs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=157830258 -assert nopostproc +UVM_TEST NAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_inputs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul t.vdb -cm_log /dev/null -cm_name 1.chip_sw_sysrst_ctrl_inputs.157830258 |
| Directory | /workspace/1.chip_sw_sysrst_ctrl_inputs/latest |
| Test location | /workspace/coverage/default/1.chip_sw_sysrst_ctrl_outputs.157285449 |
| Short name | T203 |
| Test name | |
| Test status | |
| Simulation time | 4318759240 ps |
| CPU time | 428.14 seconds |
| Started | Jun 28 08:07:33 PM PDT 24 |
| Finished | Jun 28 08:14:42 PM PDT 24 |
| Peak memory | 609172 kb |
| Host | smart-463786b3-0fff-4ce0-afab-105c665ea373 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=sysrst_ctrl_outputs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=157285449 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_outputs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defa ult.vdb -cm_log /dev/null -cm_name 1.chip_sw_sysrst_ctrl_outputs.157285449 |
| Directory | /workspace/1.chip_sw_sysrst_ctrl_outputs/latest |
| Test location | /workspace/coverage/default/1.chip_sw_sysrst_ctrl_ulp_z3_wakeup.1694993668 |
| Short name | T46 |
| Test name | |
| Test status | |
| Simulation time | 6051865432 ps |
| CPU time | 492.23 seconds |
| Started | Jun 28 08:06:21 PM PDT 24 |
| Finished | Jun 28 08:14:35 PM PDT 24 |
| Peak memory | 608376 kb |
| Host | smart-f84c6ce1-5f16-4cd4-8a6c-8e7ab9668b6c |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=sysrst_ctrl_ulp_z3_wakeup_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1694993668 -assert nopostproc + UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_ulp_z3_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/ coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_sysrst_ctrl_ulp_z3_wakeup.1694993668 |
| Directory | /workspace/1.chip_sw_sysrst_ctrl_ulp_z3_wakeup/latest |
| Test location | /workspace/coverage/default/1.chip_sw_uart_rand_baudrate.1409447676 |
| Short name | T1055 |
| Test name | |
| Test status | |
| Simulation time | 3313821542 ps |
| CPU time | 470.48 seconds |
| Started | Jun 28 08:06:26 PM PDT 24 |
| Finished | Jun 28 08:14:17 PM PDT 24 |
| Peak memory | 618556 kb |
| Host | smart-343e9751-4d04-4767-9e9c-22f4f7a500fd |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=1409447676 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_uart_rand_baudrate.1409447676 |
| Directory | /workspace/1.chip_sw_uart_rand_baudrate/latest |
| Test location | /workspace/coverage/default/1.chip_sw_uart_smoketest.2683482819 |
| Short name | T1005 |
| Test name | |
| Test status | |
| Simulation time | 2985227792 ps |
| CPU time | 285.17 seconds |
| Started | Jun 28 08:13:53 PM PDT 24 |
| Finished | Jun 28 08:18:39 PM PDT 24 |
| Peak memory | 609632 kb |
| Host | smart-79d7858a-e2c8-42a4-8fee-e5d22c9242d7 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=uart_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2683482819 -assert nopostproc +UVM_TESTNAME=chi p_base_test +UVM_TEST_SEQ=chip_sw_uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 1.chip_sw_uart_smoketest.2683482819 |
| Directory | /workspace/1.chip_sw_uart_smoketest/latest |
| Test location | /workspace/coverage/default/1.chip_sw_uart_tx_rx_alt_clk_freq.3923803099 |
| Short name | T308 |
| Test name | |
| Test status | |
| Simulation time | 4431294916 ps |
| CPU time | 686.49 seconds |
| Started | Jun 28 08:05:51 PM PDT 24 |
| Finished | Jun 28 08:17:19 PM PDT 24 |
| Peak memory | 617612 kb |
| Host | smart-fb8e7f7b-16be-4e28-ae2a-77c00ed777eb |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=80_000_000 +chip_clock_source=ChipClockSourceExternal96Mhz +calibrate_usb_clk=1 +sw_build_device=sim_dv +s w_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3923803099 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_b audrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_uart_tx_rx _alt_clk_freq.3923803099 |
| Directory | /workspace/1.chip_sw_uart_tx_rx_alt_clk_freq/latest |
| Test location | /workspace/coverage/default/1.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.1432012139 |
| Short name | T995 |
| Test name | |
| Test status | |
| Simulation time | 4866148348 ps |
| CPU time | 492.18 seconds |
| Started | Jun 28 08:04:31 PM PDT 24 |
| Finished | Jun 28 08:12:44 PM PDT 24 |
| Peak memory | 620668 kb |
| Host | smart-d5e1a82f-72de-4190-942e-f1c476875581 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +chip_clock_source=ChipClockSourceExternal48Mhz +sw_build_device=sim_dv +s w_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1432012139 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_b audrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_uart_tx_rx _alt_clk_freq_low_speed.1432012139 |
| Directory | /workspace/1.chip_sw_uart_tx_rx_alt_clk_freq_low_speed/latest |
| Test location | /workspace/coverage/default/1.chip_sw_uart_tx_rx_bootstrap.3185886785 |
| Short name | T138 |
| Test name | |
| Test status | |
| Simulation time | 78394065006 ps |
| CPU time | 13397.7 seconds |
| Started | Jun 28 08:07:07 PM PDT 24 |
| Finished | Jun 28 11:50:28 PM PDT 24 |
| Peak memory | 632388 kb |
| Host | smart-09500585-daad-4722-9b41-2ddfc53c2b8d |
| User | root |
| Command | /workspace/default/simv +use_spi_load_bootstrap=1 +calibrate_usb_clk=1 +test_timeout_ns=160_000_000 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test :1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=3185886785 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_uart_tx_rx_bootstrap.3185886785 |
| Directory | /workspace/1.chip_sw_uart_tx_rx_bootstrap/latest |
| Test location | /workspace/coverage/default/1.chip_sw_uart_tx_rx_idx1.3499121829 |
| Short name | T207 |
| Test name | |
| Test status | |
| Simulation time | 4358786846 ps |
| CPU time | 603.84 seconds |
| Started | Jun 28 08:05:47 PM PDT 24 |
| Finished | Jun 28 08:15:52 PM PDT 24 |
| Peak memory | 615952 kb |
| Host | smart-5bdbae20-6ec8-446b-bd27-7aa72f21b1c8 |
| User | root |
| Command | /workspace/default/simv +uart_idx=1 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3499121829 -a ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_uart_tx_rx_idx1.3499121829 |
| Directory | /workspace/1.chip_sw_uart_tx_rx_idx1/latest |
| Test location | /workspace/coverage/default/1.chip_sw_uart_tx_rx_idx2.3050966133 |
| Short name | T969 |
| Test name | |
| Test status | |
| Simulation time | 4279817680 ps |
| CPU time | 489.26 seconds |
| Started | Jun 28 08:04:26 PM PDT 24 |
| Finished | Jun 28 08:12:37 PM PDT 24 |
| Peak memory | 615856 kb |
| Host | smart-7e656ae4-cb77-4fc8-837b-eadc493fb66c |
| User | root |
| Command | /workspace/default/simv +uart_idx=2 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3050966133 -a ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_uart_tx_rx_idx2.3050966133 |
| Directory | /workspace/1.chip_sw_uart_tx_rx_idx2/latest |
| Test location | /workspace/coverage/default/1.chip_tap_straps_dev.2064552803 |
| Short name | T1074 |
| Test name | |
| Test status | |
| Simulation time | 3343116278 ps |
| CPU time | 194.83 seconds |
| Started | Jun 28 08:05:37 PM PDT 24 |
| Finished | Jun 28 08:08:52 PM PDT 24 |
| Peak memory | 618048 kb |
| Host | smart-903630e3-462b-48ba-84be-871071b6e61d |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStDev +create_jtag_riscv_map=1 +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:test_in_rom: new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=2064552803 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_tap_straps_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_tap_straps_dev.2064552803 |
| Directory | /workspace/1.chip_tap_straps_dev/latest |
| Test location | /workspace/coverage/default/1.chip_tap_straps_prod.953852897 |
| Short name | T1206 |
| Test name | |
| Test status | |
| Simulation time | 14239617748 ps |
| CPU time | 1509.94 seconds |
| Started | Jun 28 08:08:53 PM PDT 24 |
| Finished | Jun 28 08:34:04 PM PDT 24 |
| Peak memory | 620396 kb |
| Host | smart-5df7094f-44e5-4113-b3ab-71f2e7cbf63a |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStProd +create_jtag_riscv_map=1 +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:test_in_rom :new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=953852897 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_tap_straps_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_tap_straps_prod.953852897 |
| Directory | /workspace/1.chip_tap_straps_prod/latest |
| Test location | /workspace/coverage/default/1.chip_tap_straps_rma.1167666931 |
| Short name | T1040 |
| Test name | |
| Test status | |
| Simulation time | 4279632485 ps |
| CPU time | 325.54 seconds |
| Started | Jun 28 08:10:05 PM PDT 24 |
| Finished | Jun 28 08:15:32 PM PDT 24 |
| Peak memory | 619592 kb |
| Host | smart-b3ba7b5a-45be-4650-a91c-660ce5a37924 |
| User | root |
| Command | /workspace/default/simv +create_jtag_riscv_map=1 +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:test_in_rom:new_rules +cdc_instrumentation _enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1167666931 -as sert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_tap_straps_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/c overage/default.vdb -cm_log /dev/null -cm_name 1.chip_tap_straps_rma.1167666931 |
| Directory | /workspace/1.chip_tap_straps_rma/latest |
| Test location | /workspace/coverage/default/1.chip_tap_straps_testunlock0.1484512299 |
| Short name | T67 |
| Test name | |
| Test status | |
| Simulation time | 9325500237 ps |
| CPU time | 1077.16 seconds |
| Started | Jun 28 08:10:34 PM PDT 24 |
| Finished | Jun 28 08:28:32 PM PDT 24 |
| Peak memory | 620332 kb |
| Host | smart-6a89a869-0b0c-4eec-9734-14a1a6785fc5 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStTestUnlocked0 +create_jtag_riscv_map=1 +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:te st_in_rom:new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1484512299 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_tap_straps_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_tap_straps_testunlock0.1484512299 |
| Directory | /workspace/1.chip_tap_straps_testunlock0/latest |
| Test location | /workspace/coverage/default/1.rom_e2e_asm_init_dev.2810408482 |
| Short name | T998 |
| Test name | |
| Test status | |
| Simulation time | 15171841849 ps |
| CPU time | 4825.47 seconds |
| Started | Jun 28 08:17:04 PM PDT 24 |
| Finished | Jun 28 09:37:34 PM PDT 24 |
| Peak memory | 608268 kb |
| Host | smart-4bc88e97-c8d5-4473-b6c4-0d3a2730c730 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeCustom +sw_test_timeout_ns=20000000 +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_prod _key_0:1:ot_flash_binary,otp_img_e2e_bootstrap_entry_dev:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2810408482 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_S EQ=chip_sw_rom_e2e_asm_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_e2e_asm_init_dev.2810408482 |
| Directory | /workspace/1.rom_e2e_asm_init_dev/latest |
| Test location | /workspace/coverage/default/1.rom_e2e_asm_init_prod.2772754253 |
| Short name | T921 |
| Test name | |
| Test status | |
| Simulation time | 15607837560 ps |
| CPU time | 4140.75 seconds |
| Started | Jun 28 08:15:15 PM PDT 24 |
| Finished | Jun 28 09:24:18 PM PDT 24 |
| Peak memory | 607892 kb |
| Host | smart-88fe2230-1870-4e98-8a74-8c1d872acfd1 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeCustom +sw_test_timeout_ns=20000000 +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_prod _key_0:1:ot_flash_binary,otp_img_e2e_bootstrap_entry_prod:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2772754253 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_ SEQ=chip_sw_rom_e2e_asm_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_e2e_asm_init_prod.2772754253 |
| Directory | /workspace/1.rom_e2e_asm_init_prod/latest |
| Test location | /workspace/coverage/default/1.rom_e2e_asm_init_prod_end.1770556212 |
| Short name | T900 |
| Test name | |
| Test status | |
| Simulation time | 15551561528 ps |
| CPU time | 4289.63 seconds |
| Started | Jun 28 08:14:43 PM PDT 24 |
| Finished | Jun 28 09:26:15 PM PDT 24 |
| Peak memory | 608072 kb |
| Host | smart-b8a556e9-0b97-496f-ad7f-6cb477918913 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeCustom +sw_test_timeout_ns=20000000 +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_prod _key_0:1:ot_flash_binary,otp_img_e2e_bootstrap_entry_prod_end:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1770556212 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_T EST_SEQ=chip_sw_rom_e2e_asm_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 1.rom_e2e_asm_init_prod_end.1770556212 |
| Directory | /workspace/1.rom_e2e_asm_init_prod_end/latest |
| Test location | /workspace/coverage/default/1.rom_e2e_asm_init_rma.2677311317 |
| Short name | T287 |
| Test name | |
| Test status | |
| Simulation time | 14841134586 ps |
| CPU time | 3449.03 seconds |
| Started | Jun 28 08:20:34 PM PDT 24 |
| Finished | Jun 28 09:18:05 PM PDT 24 |
| Peak memory | 608208 kb |
| Host | smart-a4a9d4ff-9898-42f4-9b94-f72e959f009b |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeCustom +sw_test_timeout_ns=20000000 +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_prod _key_0:1:ot_flash_binary,otp_img_e2e_bootstrap_entry_rma:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2677311317 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_S EQ=chip_sw_rom_e2e_asm_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_e2e_asm_init_rma.2677311317 |
| Directory | /workspace/1.rom_e2e_asm_init_rma/latest |
| Test location | /workspace/coverage/default/1.rom_e2e_asm_init_test_unlocked0.1707939598 |
| Short name | T1071 |
| Test name | |
| Test status | |
| Simulation time | 11372782069 ps |
| CPU time | 3242.75 seconds |
| Started | Jun 28 08:14:20 PM PDT 24 |
| Finished | Jun 28 09:08:24 PM PDT 24 |
| Peak memory | 607448 kb |
| Host | smart-c9280ec2-f574-4204-b0f3-760d203ef6ae |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeCustom +sw_test_timeout_ns=410_000_000 +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_p rod_key_0:1:ot_flash_binary,otp_img_e2e_bootstrap_entry_test_unlocked0:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY =UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1707939598 -assert nopostproc +UVM_TESTNAME=chip_base_te st +UVM_TEST_SEQ=chip_sw_rom_e2e_asm_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/ null -cm_name 1.rom_e2e_asm_init_test_unlocked0.1707939598 |
| Directory | /workspace/1.rom_e2e_asm_init_test_unlocked0/latest |
| Test location | /workspace/coverage/default/1.rom_e2e_keymgr_init_rom_ext_invalid_meas.1137907664 |
| Short name | T1106 |
| Test name | |
| Test status | |
| Simulation time | 14452350296 ps |
| CPU time | 3804.25 seconds |
| Started | Jun 28 08:16:27 PM PDT 24 |
| Finished | Jun 28 09:19:54 PM PDT 24 |
| Peak memory | 608352 kb |
| Host | smart-f257fcd3-aa31-4bc6-b310-649d0ce36a4a |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=40_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=rom_e2e_keymgr_init_otp_invalid _meas:1:new_rules,otp_img_keymgr_otp_invalid_meas:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1137907664 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip _sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_e2e_keymgr_in it_rom_ext_invalid_meas.1137907664 |
| Directory | /workspace/1.rom_e2e_keymgr_init_rom_ext_invalid_meas/latest |
| Test location | /workspace/coverage/default/1.rom_e2e_keymgr_init_rom_ext_meas.2853203939 |
| Short name | T889 |
| Test name | |
| Test status | |
| Simulation time | 14479880640 ps |
| CPU time | 3670 seconds |
| Started | Jun 28 08:20:04 PM PDT 24 |
| Finished | Jun 28 09:21:15 PM PDT 24 |
| Peak memory | 608456 kb |
| Host | smart-5c1f50d0-6bc7-4577-a98c-b8d19387b507 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=40_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=rom_e2e_keymgr_init_otp_meas:1: new_rules,otp_img_keymgr_otp_meas:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2853203939 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_e2e_keymgr_init_rom_ext_meas.2853203939 |
| Directory | /workspace/1.rom_e2e_keymgr_init_rom_ext_meas/latest |
| Test location | /workspace/coverage/default/1.rom_e2e_keymgr_init_rom_ext_no_meas.3568377991 |
| Short name | T314 |
| Test name | |
| Test status | |
| Simulation time | 14447076892 ps |
| CPU time | 2709.18 seconds |
| Started | Jun 28 08:14:02 PM PDT 24 |
| Finished | Jun 28 08:59:12 PM PDT 24 |
| Peak memory | 607328 kb |
| Host | smart-f2bef61e-a774-4b4d-b0b7-0886ff6707d8 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=40_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=rom_e2e_keymgr_init_otp_no_meas :1:new_rules,otp_img_keymgr_otp_no_meas:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3568377991 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_e2e_keymgr_init_rom_ext _no_meas.3568377991 |
| Directory | /workspace/1.rom_e2e_keymgr_init_rom_ext_no_meas/latest |
| Test location | /workspace/coverage/default/1.rom_e2e_shutdown_exception_c.3023302921 |
| Short name | T1280 |
| Test name | |
| Test status | |
| Simulation time | 14827291436 ps |
| CPU time | 3631.82 seconds |
| Started | Jun 28 08:16:56 PM PDT 24 |
| Finished | Jun 28 09:17:32 PM PDT 24 |
| Peak memory | 608148 kb |
| Host | smart-aac9f40e-857c-44f0-ab32-85494be5fb83 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=40000000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=rom_e2e_shutdown_exception_c:1:ne w_rules,otp_img_secret2_locked_rma:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3023302921 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_e2e_shu tdown_exception_c_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_e2e_ shutdown_exception_c.3023302921 |
| Directory | /workspace/1.rom_e2e_shutdown_exception_c/latest |
| Test location | /workspace/coverage/default/1.rom_e2e_shutdown_output.1704709570 |
| Short name | T51 |
| Test name | |
| Test status | |
| Simulation time | 30422348225 ps |
| CPU time | 4271.99 seconds |
| Started | Jun 28 08:15:29 PM PDT 24 |
| Finished | Jun 28 09:26:42 PM PDT 24 |
| Peak memory | 608288 kb |
| Host | smart-410940d3-390c-4fe7-8881-3a117357b1a7 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=20000000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_unsigned:1:ot_f lash_binary,otp_img_shutdown_output_test_unlocked0:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1704709570 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chi p_sw_rom_e2e_shutdown_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_e2e_shutdown_output.1704709570 |
| Directory | /workspace/1.rom_e2e_shutdown_output/latest |
| Test location | /workspace/coverage/default/1.rom_e2e_smoke.630341464 |
| Short name | T904 |
| Test name | |
| Test status | |
| Simulation time | 15394784468 ps |
| CPU time | 3566.86 seconds |
| Started | Jun 28 08:15:15 PM PDT 24 |
| Finished | Jun 28 09:14:43 PM PDT 24 |
| Peak memory | 607208 kb |
| Host | smart-8f2dd5fe-2a7d-4946-b544-6e8c07b20a91 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=40000000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=rom_e2e_smoke:1:new_rules,otp_img _secret2_locked_rma:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_to p/hw/dv/tools/sim.tcl +ntb_random_seed=630341464 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_e2e_smoke.630341464 |
| Directory | /workspace/1.rom_e2e_smoke/latest |
| Test location | /workspace/coverage/default/1.rom_e2e_static_critical.4242417167 |
| Short name | T925 |
| Test name | |
| Test status | |
| Simulation time | 16727523896 ps |
| CPU time | 3945.87 seconds |
| Started | Jun 28 08:14:54 PM PDT 24 |
| Finished | Jun 28 09:20:45 PM PDT 24 |
| Peak memory | 607392 kb |
| Host | smart-4e2f2892-60bc-4141-821c-5ff43adc9a0d |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=40000000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=rom_e2e_static_critical:1:new_rul es,otp_img_secret2_locked_rma:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4242417167 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_e2e_static_critical.4242417167 |
| Directory | /workspace/1.rom_e2e_static_critical/latest |
| Test location | /workspace/coverage/default/1.rom_keymgr_functest.3836433993 |
| Short name | T289 |
| Test name | |
| Test status | |
| Simulation time | 5508137592 ps |
| CPU time | 681.44 seconds |
| Started | Jun 28 08:11:47 PM PDT 24 |
| Finished | Jun 28 08:23:16 PM PDT 24 |
| Peak memory | 609192 kb |
| Host | smart-726dce9c-c42b-442c-90d6-d21cb9f8c1ba |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=10_000_000 +sw_build_device=sim_dv +sw_images=keymgr_functest:1:new_rules,test_rom:0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3836433993 -ass ert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 1.rom_keymgr_functest.3836433993 |
| Directory | /workspace/1.rom_keymgr_functest/latest |
| Test location | /workspace/coverage/default/1.rom_volatile_raw_unlock.1560028074 |
| Short name | T1179 |
| Test name | |
| Test status | |
| Simulation time | 2331234402 ps |
| CPU time | 122.14 seconds |
| Started | Jun 28 08:12:13 PM PDT 24 |
| Finished | Jun 28 08:14:16 PM PDT 24 |
| Peak memory | 613392 kb |
| Host | smart-be3dadbd-98fd-468f-b3be-94f8a3ce6fe3 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=200_000_000 +use_otp_image=OtpTypeLcStRaw +chip_clock_source=ChipClockSourceExternal48Mhz +rom_prod_mode=1 +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_test_key_0:1:ot_flash_binary,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1560028074 -assert nopostproc +UVM_ TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_volatile_raw_unlock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag e/default.vdb -cm_log /dev/null -cm_name 1.rom_volatile_raw_unlock.1560028074 |
| Directory | /workspace/1.rom_volatile_raw_unlock/latest |
| Test location | /workspace/coverage/default/10.chip_sw_lc_ctrl_transition.123086582 |
| Short name | T886 |
| Test name | |
| Test status | |
| Simulation time | 5855098285 ps |
| CPU time | 406.81 seconds |
| Started | Jun 28 08:25:20 PM PDT 24 |
| Finished | Jun 28 08:32:14 PM PDT 24 |
| Peak memory | 619192 kb |
| Host | smart-ff6e6fc2-7f6d-4219-b22d-1451806157f9 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=lc_ctrl_transition_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=123086582 -assert nopostproc +UVM_TEST NAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_transition_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul t.vdb -cm_log /dev/null -cm_name 10.chip_sw_lc_ctrl_transition.123086582 |
| Directory | /workspace/10.chip_sw_lc_ctrl_transition/latest |
| Test location | /workspace/coverage/default/10.chip_sw_uart_rand_baudrate.3868075049 |
| Short name | T307 |
| Test name | |
| Test status | |
| Simulation time | 8387075328 ps |
| CPU time | 1790.55 seconds |
| Started | Jun 28 08:31:50 PM PDT 24 |
| Finished | Jun 28 09:01:53 PM PDT 24 |
| Peak memory | 617588 kb |
| Host | smart-599840f9-4920-4647-a15d-cf0df9154ba7 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=3868075049 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.chip_sw_uart_rand_baudrate.3868075049 |
| Directory | /workspace/10.chip_sw_uart_rand_baudrate/latest |
| Test location | /workspace/coverage/default/11.chip_sw_lc_ctrl_transition.1116905361 |
| Short name | T1271 |
| Test name | |
| Test status | |
| Simulation time | 9564289458 ps |
| CPU time | 1061.71 seconds |
| Started | Jun 28 08:25:43 PM PDT 24 |
| Finished | Jun 28 08:43:27 PM PDT 24 |
| Peak memory | 620944 kb |
| Host | smart-3e2c32ee-310c-4e49-8f60-0cab82d74c38 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=lc_ctrl_transition_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1116905361 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_transition_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau lt.vdb -cm_log /dev/null -cm_name 11.chip_sw_lc_ctrl_transition.1116905361 |
| Directory | /workspace/11.chip_sw_lc_ctrl_transition/latest |
| Test location | /workspace/coverage/default/11.chip_sw_uart_rand_baudrate.1914613978 |
| Short name | T325 |
| Test name | |
| Test status | |
| Simulation time | 13490860940 ps |
| CPU time | 2466.04 seconds |
| Started | Jun 28 08:27:15 PM PDT 24 |
| Finished | Jun 28 09:08:22 PM PDT 24 |
| Peak memory | 618836 kb |
| Host | smart-d415aa4d-e21d-4700-85e2-8fb6a6065df9 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=1914613978 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.chip_sw_uart_rand_baudrate.1914613978 |
| Directory | /workspace/11.chip_sw_uart_rand_baudrate/latest |
| Test location | /workspace/coverage/default/12.chip_sw_all_escalation_resets.4077856222 |
| Short name | T238 |
| Test name | |
| Test status | |
| Simulation time | 5176231740 ps |
| CPU time | 586.04 seconds |
| Started | Jun 28 08:27:01 PM PDT 24 |
| Finished | Jun 28 08:36:48 PM PDT 24 |
| Peak memory | 615112 kb |
| Host | smart-460b1246-9a27-4248-bb40-bf8fed3a85bb |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 4077856222 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.chip_sw_all_escalation_resets.4077856222 |
| Directory | /workspace/12.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/12.chip_sw_lc_ctrl_transition.763967115 |
| Short name | T1151 |
| Test name | |
| Test status | |
| Simulation time | 6070756850 ps |
| CPU time | 446.24 seconds |
| Started | Jun 28 08:28:14 PM PDT 24 |
| Finished | Jun 28 08:35:43 PM PDT 24 |
| Peak memory | 619200 kb |
| Host | smart-247fc4e2-4032-42f5-8fc9-66fcc17d960b |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=lc_ctrl_transition_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=763967115 -assert nopostproc +UVM_TEST NAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_transition_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul t.vdb -cm_log /dev/null -cm_name 12.chip_sw_lc_ctrl_transition.763967115 |
| Directory | /workspace/12.chip_sw_lc_ctrl_transition/latest |
| Test location | /workspace/coverage/default/12.chip_sw_uart_rand_baudrate.3398011201 |
| Short name | T879 |
| Test name | |
| Test status | |
| Simulation time | 3905512388 ps |
| CPU time | 597.52 seconds |
| Started | Jun 28 08:28:01 PM PDT 24 |
| Finished | Jun 28 08:37:59 PM PDT 24 |
| Peak memory | 618548 kb |
| Host | smart-4b178bca-8eca-4b31-92c8-0a8dbd5cbd3a |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=3398011201 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.chip_sw_uart_rand_baudrate.3398011201 |
| Directory | /workspace/12.chip_sw_uart_rand_baudrate/latest |
| Test location | /workspace/coverage/default/13.chip_sw_alert_handler_lpg_sleep_mode_alerts.2764845837 |
| Short name | T369 |
| Test name | |
| Test status | |
| Simulation time | 3995157368 ps |
| CPU time | 434.77 seconds |
| Started | Jun 28 08:27:19 PM PDT 24 |
| Finished | Jun 28 08:34:35 PM PDT 24 |
| Peak memory | 646952 kb |
| Host | smart-2a762ee9-698d-4047-beb7-4933771ac16e |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2764845837 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.chip_ sw_alert_handler_lpg_sleep_mode_alerts.2764845837 |
| Directory | /workspace/13.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/13.chip_sw_lc_ctrl_transition.524982397 |
| Short name | T957 |
| Test name | |
| Test status | |
| Simulation time | 10264775047 ps |
| CPU time | 834.73 seconds |
| Started | Jun 28 08:26:29 PM PDT 24 |
| Finished | Jun 28 08:40:25 PM PDT 24 |
| Peak memory | 620576 kb |
| Host | smart-8b1d2906-1504-45ee-a097-af3a40061e4a |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=lc_ctrl_transition_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=524982397 -assert nopostproc +UVM_TEST NAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_transition_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul t.vdb -cm_log /dev/null -cm_name 13.chip_sw_lc_ctrl_transition.524982397 |
| Directory | /workspace/13.chip_sw_lc_ctrl_transition/latest |
| Test location | /workspace/coverage/default/13.chip_sw_uart_rand_baudrate.4006708552 |
| Short name | T922 |
| Test name | |
| Test status | |
| Simulation time | 3646470766 ps |
| CPU time | 558.98 seconds |
| Started | Jun 28 08:28:05 PM PDT 24 |
| Finished | Jun 28 08:37:25 PM PDT 24 |
| Peak memory | 618328 kb |
| Host | smart-a134ebcf-ecdf-440e-859d-34e525906ff0 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=4006708552 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.chip_sw_uart_rand_baudrate.4006708552 |
| Directory | /workspace/13.chip_sw_uart_rand_baudrate/latest |
| Test location | /workspace/coverage/default/14.chip_sw_all_escalation_resets.720798641 |
| Short name | T1169 |
| Test name | |
| Test status | |
| Simulation time | 5508245240 ps |
| CPU time | 747.57 seconds |
| Started | Jun 28 08:27:35 PM PDT 24 |
| Finished | Jun 28 08:40:08 PM PDT 24 |
| Peak memory | 643364 kb |
| Host | smart-55430387-c963-4730-bd3b-d85309063b07 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 720798641 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.chip_sw_all_escalation_resets.720798641 |
| Directory | /workspace/14.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/14.chip_sw_lc_ctrl_transition.1238482436 |
| Short name | T950 |
| Test name | |
| Test status | |
| Simulation time | 5287768386 ps |
| CPU time | 449.77 seconds |
| Started | Jun 28 08:28:08 PM PDT 24 |
| Finished | Jun 28 08:35:40 PM PDT 24 |
| Peak memory | 619248 kb |
| Host | smart-066c029a-1856-4fa6-b905-46ba48c6662a |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=lc_ctrl_transition_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1238482436 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_transition_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau lt.vdb -cm_log /dev/null -cm_name 14.chip_sw_lc_ctrl_transition.1238482436 |
| Directory | /workspace/14.chip_sw_lc_ctrl_transition/latest |
| Test location | /workspace/coverage/default/14.chip_sw_uart_rand_baudrate.484305035 |
| Short name | T316 |
| Test name | |
| Test status | |
| Simulation time | 4125664640 ps |
| CPU time | 754.04 seconds |
| Started | Jun 28 08:26:46 PM PDT 24 |
| Finished | Jun 28 08:39:22 PM PDT 24 |
| Peak memory | 618572 kb |
| Host | smart-3cbdbf0f-443c-4582-ae11-3086cd1331f1 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=484305035 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.chip_sw_uart_rand_baudrate.484305035 |
| Directory | /workspace/14.chip_sw_uart_rand_baudrate/latest |
| Test location | /workspace/coverage/default/15.chip_sw_uart_rand_baudrate.4215977502 |
| Short name | T28 |
| Test name | |
| Test status | |
| Simulation time | 4327486882 ps |
| CPU time | 664.2 seconds |
| Started | Jun 28 08:31:41 PM PDT 24 |
| Finished | Jun 28 08:42:57 PM PDT 24 |
| Peak memory | 618860 kb |
| Host | smart-52a3f390-10c5-40c9-9043-34f573a1e8b3 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=4215977502 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.chip_sw_uart_rand_baudrate.4215977502 |
| Directory | /workspace/15.chip_sw_uart_rand_baudrate/latest |
| Test location | /workspace/coverage/default/16.chip_sw_uart_rand_baudrate.3927461476 |
| Short name | T1168 |
| Test name | |
| Test status | |
| Simulation time | 8148825070 ps |
| CPU time | 1354.19 seconds |
| Started | Jun 28 08:28:07 PM PDT 24 |
| Finished | Jun 28 08:50:43 PM PDT 24 |
| Peak memory | 618608 kb |
| Host | smart-3f8460ef-fcbc-4385-95fb-daf2e3f0d4c4 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=3927461476 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.chip_sw_uart_rand_baudrate.3927461476 |
| Directory | /workspace/16.chip_sw_uart_rand_baudrate/latest |
| Test location | /workspace/coverage/default/17.chip_sw_alert_handler_lpg_sleep_mode_alerts.3774956376 |
| Short name | T699 |
| Test name | |
| Test status | |
| Simulation time | 3211732610 ps |
| CPU time | 359.18 seconds |
| Started | Jun 28 08:27:47 PM PDT 24 |
| Finished | Jun 28 08:33:56 PM PDT 24 |
| Peak memory | 642148 kb |
| Host | smart-37912d87-07ab-4f63-8130-fcf9309477b8 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3774956376 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.chip_ sw_alert_handler_lpg_sleep_mode_alerts.3774956376 |
| Directory | /workspace/17.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/18.chip_sw_uart_rand_baudrate.357284887 |
| Short name | T926 |
| Test name | |
| Test status | |
| Simulation time | 9100007284 ps |
| CPU time | 1591.1 seconds |
| Started | Jun 28 08:27:06 PM PDT 24 |
| Finished | Jun 28 08:53:39 PM PDT 24 |
| Peak memory | 618888 kb |
| Host | smart-3622abd3-f371-4e23-bebc-86f28501ba60 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=357284887 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.chip_sw_uart_rand_baudrate.357284887 |
| Directory | /workspace/18.chip_sw_uart_rand_baudrate/latest |
| Test location | /workspace/coverage/default/19.chip_sw_alert_handler_lpg_sleep_mode_alerts.2482124976 |
| Short name | T731 |
| Test name | |
| Test status | |
| Simulation time | 3945439400 ps |
| CPU time | 430.73 seconds |
| Started | Jun 28 08:26:18 PM PDT 24 |
| Finished | Jun 28 08:33:37 PM PDT 24 |
| Peak memory | 647020 kb |
| Host | smart-559f5018-b0f2-4247-b56b-cd0d3df181b7 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2482124976 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.chip_ sw_alert_handler_lpg_sleep_mode_alerts.2482124976 |
| Directory | /workspace/19.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/19.chip_sw_uart_rand_baudrate.2935942864 |
| Short name | T975 |
| Test name | |
| Test status | |
| Simulation time | 3232889700 ps |
| CPU time | 539.38 seconds |
| Started | Jun 28 08:27:12 PM PDT 24 |
| Finished | Jun 28 08:36:13 PM PDT 24 |
| Peak memory | 618612 kb |
| Host | smart-f526c629-621a-4384-b0c6-2262f427b2bc |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=2935942864 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.chip_sw_uart_rand_baudrate.2935942864 |
| Directory | /workspace/19.chip_sw_uart_rand_baudrate/latest |
| Test location | /workspace/coverage/default/2.chip_jtag_mem_access.1393739630 |
| Short name | T55 |
| Test name | |
| Test status | |
| Simulation time | 14066436868 ps |
| CPU time | 1323.08 seconds |
| Started | Jun 28 08:13:33 PM PDT 24 |
| Finished | Jun 28 08:35:43 PM PDT 24 |
| Peak memory | 607288 kb |
| Host | smart-42070f80-ed03-4272-9818-486ec15e8c6e |
| User | root |
| Command | /workspace/default/simv +create_jtag_riscv_map=1 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1393739630 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_jtag_ mem_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_jtag_mem_access.1 393739630 |
| Directory | /workspace/2.chip_jtag_mem_access/latest |
| Test location | /workspace/coverage/default/2.chip_rv_dm_ndm_reset_req.1433531735 |
| Short name | T9 |
| Test name | |
| Test status | |
| Simulation time | 3650709370 ps |
| CPU time | 354.08 seconds |
| Started | Jun 28 08:20:34 PM PDT 24 |
| Finished | Jun 28 08:26:29 PM PDT 24 |
| Peak memory | 617744 kb |
| Host | smart-994e1444-08cd-478c-8fd9-d5651dfae062 |
| User | root |
| Command | /workspace/default/simv +en_scb_tl_err_chk=0 +use_jtag_dmi=1 +sw_build_device=sim_dv +sw_images=rv_dm_ndm_reset_req_rma:1:new_rules,test_rom:0 +cdc_in strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1 433531735 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_rv_dm_ndm_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_rv_dm_ndm_reset_req.1433531735 |
| Directory | /workspace/2.chip_rv_dm_ndm_reset_req/latest |
| Test location | /workspace/coverage/default/2.chip_sival_flash_info_access.1941682035 |
| Short name | T1047 |
| Test name | |
| Test status | |
| Simulation time | 3074476704 ps |
| CPU time | 359.1 seconds |
| Started | Jun 28 08:14:03 PM PDT 24 |
| Finished | Jun 28 08:20:03 PM PDT 24 |
| Peak memory | 609160 kb |
| Host | smart-bd230236-88d1-4f8b-8812-c874e7e81ec5 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStTestUnlocked0 +sw_build_device=sim_dv +sw_images=flash_ctrl_info_access_lc:1:new_rules,test_rom:0 +c dc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_s eed=1941682035 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sival_flash_info_access.1941682035 |
| Directory | /workspace/2.chip_sival_flash_info_access/latest |
| Test location | /workspace/coverage/default/2.chip_sw_adc_ctrl_sleep_debug_cable_wakeup.3766974286 |
| Short name | T349 |
| Test name | |
| Test status | |
| Simulation time | 18977531204 ps |
| CPU time | 464.99 seconds |
| Started | Jun 28 08:19:00 PM PDT 24 |
| Finished | Jun 28 08:26:47 PM PDT 24 |
| Peak memory | 616744 kb |
| Host | smart-253ff254-b33c-4d06-997a-9c22994180dc |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=adc_ctrl_sleep_debug_cable_wakeup_test:1:new_rules,test_rom: 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand om_seed=3766974286 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_adc_ctrl_sleep_debug_cable_wakeup_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_adc_ctrl_sleep_debug_cable_wakeup.3766974286 |
| Directory | /workspace/2.chip_sw_adc_ctrl_sleep_debug_cable_wakeup/latest |
| Test location | /workspace/coverage/default/2.chip_sw_aes_enc.4186486162 |
| Short name | T1302 |
| Test name | |
| Test status | |
| Simulation time | 3212319000 ps |
| CPU time | 312.73 seconds |
| Started | Jun 28 08:18:15 PM PDT 24 |
| Finished | Jun 28 08:23:33 PM PDT 24 |
| Peak memory | 607624 kb |
| Host | smart-172f4788-0724-4abe-be61-d84f1e8ea2d9 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=22_000_000 +sw_build_device=sim_dv +sw_images=aes_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4186486162 -asser t nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag e/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_aes_enc.4186486162 |
| Directory | /workspace/2.chip_sw_aes_enc/latest |
| Test location | /workspace/coverage/default/2.chip_sw_aes_enc_jitter_en.4043516843 |
| Short name | T1181 |
| Test name | |
| Test status | |
| Simulation time | 2901060684 ps |
| CPU time | 300.18 seconds |
| Started | Jun 28 08:19:49 PM PDT 24 |
| Finished | Jun 28 08:24:53 PM PDT 24 |
| Peak memory | 607116 kb |
| Host | smart-b56c6600-07b6-41dc-9f21-18415f94096e |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=26_000_000 +en_jitter=1 +sw_build_device=sim_dv +sw_images=aes_smoketest:1:new_rules,test_rom:0 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4043 516843 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work space/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_aes_enc_jitter_en.4043516843 |
| Directory | /workspace/2.chip_sw_aes_enc_jitter_en/latest |
| Test location | /workspace/coverage/default/2.chip_sw_aes_enc_jitter_en_reduced_freq.1628558023 |
| Short name | T917 |
| Test name | |
| Test status | |
| Simulation time | 2431540408 ps |
| CPU time | 253.74 seconds |
| Started | Jun 28 08:28:06 PM PDT 24 |
| Finished | Jun 28 08:32:21 PM PDT 24 |
| Peak memory | 609176 kb |
| Host | smart-f23f2adf-ef3a-476b-80ee-866923bc33bf |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=26_000_000 +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=aes_smoketest:1:new_rules, test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1628558023 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_aes_enc_jitter_en_reduced_freq.1628558023 |
| Directory | /workspace/2.chip_sw_aes_enc_jitter_en_reduced_freq/latest |
| Test location | /workspace/coverage/default/2.chip_sw_aes_idle.166021938 |
| Short name | T292 |
| Test name | |
| Test status | |
| Simulation time | 2802655674 ps |
| CPU time | 278.02 seconds |
| Started | Jun 28 08:18:57 PM PDT 24 |
| Finished | Jun 28 08:23:36 PM PDT 24 |
| Peak memory | 609180 kb |
| Host | smart-ac7c153c-86de-4018-8847-e7de310910c1 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=25_000_000 +sw_build_device=sim_dv +sw_images=aes_idle_test:1:new_rules,test_rom:0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=166021938 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage /default.vdb -cm_log /dev/null -cm_name 2.chip_sw_aes_idle.166021938 |
| Directory | /workspace/2.chip_sw_aes_idle/latest |
| Test location | /workspace/coverage/default/2.chip_sw_aes_masking_off.4260577622 |
| Short name | T1124 |
| Test name | |
| Test status | |
| Simulation time | 3192055960 ps |
| CPU time | 415.54 seconds |
| Started | Jun 28 08:20:00 PM PDT 24 |
| Finished | Jun 28 08:26:56 PM PDT 24 |
| Peak memory | 607400 kb |
| Host | smart-e8f5bcdc-6ba0-4160-b3d7-75173adfacc8 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=aes_masking_off_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4260577622 -assert nopostproc +UVM_TESTNA ME=chip_base_test +UVM_TEST_SEQ=chip_sw_aes_masking_off_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_aes_masking_off.4260577622 |
| Directory | /workspace/2.chip_sw_aes_masking_off/latest |
| Test location | /workspace/coverage/default/2.chip_sw_aes_smoketest.3682422836 |
| Short name | T878 |
| Test name | |
| Test status | |
| Simulation time | 2826308392 ps |
| CPU time | 221.78 seconds |
| Started | Jun 28 08:22:44 PM PDT 24 |
| Finished | Jun 28 08:26:30 PM PDT 24 |
| Peak memory | 606364 kb |
| Host | smart-f1633374-c58d-48f0-895a-0878aecd47d1 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=aes_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3682422836 -assert nopostproc +UVM_TESTNAME=chip _base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_aes_smoketest.3682422836 |
| Directory | /workspace/2.chip_sw_aes_smoketest/latest |
| Test location | /workspace/coverage/default/2.chip_sw_alert_handler_entropy.1082870194 |
| Short name | T257 |
| Test name | |
| Test status | |
| Simulation time | 3445936272 ps |
| CPU time | 389.67 seconds |
| Started | Jun 28 08:18:30 PM PDT 24 |
| Finished | Jun 28 08:25:05 PM PDT 24 |
| Peak memory | 607916 kb |
| Host | smart-3d293fd4-a273-4ab7-8479-ee9c6dd75204 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=alert_handler_entropy_test:1:new_rules,test_ro m:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=1082870194 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_alert_handler_entropy.1082870194 |
| Directory | /workspace/2.chip_sw_alert_handler_entropy/latest |
| Test location | /workspace/coverage/default/2.chip_sw_alert_handler_escalation.307900424 |
| Short name | T214 |
| Test name | |
| Test status | |
| Simulation time | 6076128652 ps |
| CPU time | 660.15 seconds |
| Started | Jun 28 08:18:35 PM PDT 24 |
| Finished | Jun 28 08:29:38 PM PDT 24 |
| Peak memory | 617324 kb |
| Host | smart-eb270910-4b68-4639-bf6b-561b4212fed0 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=alert_handler_escalation_test:1:new_rules,test _rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb _random_seed=307900424 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_alert_handler_escalation_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_alert_handler_escalation.307900424 |
| Directory | /workspace/2.chip_sw_alert_handler_escalation/latest |
| Test location | /workspace/coverage/default/2.chip_sw_alert_handler_lpg_clkoff.2705578950 |
| Short name | T88 |
| Test name | |
| Test status | |
| Simulation time | 6185556188 ps |
| CPU time | 1281.85 seconds |
| Started | Jun 28 08:18:09 PM PDT 24 |
| Finished | Jun 28 08:39:33 PM PDT 24 |
| Peak memory | 608208 kb |
| Host | smart-39507149-a6b2-444e-882d-cbdb713ba27e |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +sw_build_device=sim_dv +sw_images=alert_handler_lpg_clkoff_test:1:new_rules,test_r om:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r andom_seed=2705578950 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_alert_handler_lpg_clkoff_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_alert_handler_lpg_clkoff.2705578950 |
| Directory | /workspace/2.chip_sw_alert_handler_lpg_clkoff/latest |
| Test location | /workspace/coverage/default/2.chip_sw_alert_handler_lpg_reset_toggle.2656742827 |
| Short name | T974 |
| Test name | |
| Test status | |
| Simulation time | 8383992152 ps |
| CPU time | 1644.61 seconds |
| Started | Jun 28 08:18:36 PM PDT 24 |
| Finished | Jun 28 08:46:03 PM PDT 24 |
| Peak memory | 608088 kb |
| Host | smart-5072093d-2b05-4fed-8a4e-89490b6eecac |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +sw_build_device=sim_dv +sw_images=alert_handler_lpg_reset_toggle_test:1:new_rules, test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2656742827 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_alert_handler_shorten_ping_wait_cycle_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_alert_handler_lpg_reset_togg le.2656742827 |
| Directory | /workspace/2.chip_sw_alert_handler_lpg_reset_toggle/latest |
| Test location | /workspace/coverage/default/2.chip_sw_alert_handler_ping_ok.1034616877 |
| Short name | T1128 |
| Test name | |
| Test status | |
| Simulation time | 7749623580 ps |
| CPU time | 1388.81 seconds |
| Started | Jun 28 08:19:43 PM PDT 24 |
| Finished | Jun 28 08:42:56 PM PDT 24 |
| Peak memory | 608236 kb |
| Host | smart-3077d353-59f8-449b-a6b1-307dd5cbd8f9 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=24000000 +sw_build_device=sim_dv +sw_images=alert_handler_ping_ok_test:1:new_rules,test_rom:0 +c dc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_s eed=1034616877 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_alert_handler_ping_ok.1034616877 |
| Directory | /workspace/2.chip_sw_alert_handler_ping_ok/latest |
| Test location | /workspace/coverage/default/2.chip_sw_alert_handler_ping_timeout.86793016 |
| Short name | T1167 |
| Test name | |
| Test status | |
| Simulation time | 4565262600 ps |
| CPU time | 423.81 seconds |
| Started | Jun 28 08:21:45 PM PDT 24 |
| Finished | Jun 28 08:28:50 PM PDT 24 |
| Peak memory | 606992 kb |
| Host | smart-7036293e-7f3f-43b2-a0a9-22ed196ed9ec |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=24000000 +sw_build_device=sim_dv +sw_images=alert_handler_ping_timeout_test:1:new_rules,test_rom :0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=86793016 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_alert_handler_ping_timeout.86793016 |
| Directory | /workspace/2.chip_sw_alert_handler_ping_timeout/latest |
| Test location | /workspace/coverage/default/2.chip_sw_alert_handler_reverse_ping_in_deep_sleep.4010763651 |
| Short name | T1110 |
| Test name | |
| Test status | |
| Simulation time | 254517261744 ps |
| CPU time | 13532.2 seconds |
| Started | Jun 28 08:19:51 PM PDT 24 |
| Finished | Jun 29 12:05:27 AM PDT 24 |
| Peak memory | 608700 kb |
| Host | smart-8aa57823-6d7a-4e7b-86d1-033afbc7db24 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=300_000_000 +sw_build_device=sim_dv +sw_images=alert_handler_reverse_ping_in_deep_sleep_test:1:n ew_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4010763651 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_alert_handler_reverse_ping_in_deep_sleep.4010763651 |
| Directory | /workspace/2.chip_sw_alert_handler_reverse_ping_in_deep_sleep/latest |
| Test location | /workspace/coverage/default/2.chip_sw_alert_test.3048746062 |
| Short name | T59 |
| Test name | |
| Test status | |
| Simulation time | 3800553344 ps |
| CPU time | 383.59 seconds |
| Started | Jun 28 08:19:48 PM PDT 24 |
| Finished | Jun 28 08:26:15 PM PDT 24 |
| Peak memory | 606500 kb |
| Host | smart-bffe29be-393f-469b-a97d-03f18498b534 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=alert_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3048746062 -assert nopostproc +UVM_TESTNAME=chip_ba se_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 2.chip_sw_alert_test.3048746062 |
| Directory | /workspace/2.chip_sw_alert_test/latest |
| Test location | /workspace/coverage/default/2.chip_sw_all_escalation_resets.4266134108 |
| Short name | T358 |
| Test name | |
| Test status | |
| Simulation time | 4971149824 ps |
| CPU time | 867.6 seconds |
| Started | Jun 28 08:16:27 PM PDT 24 |
| Finished | Jun 28 08:30:57 PM PDT 24 |
| Peak memory | 615136 kb |
| Host | smart-c855da3c-6edf-490a-975c-7eed461bfc85 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 4266134108 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_all_escalation_resets.4266134108 |
| Directory | /workspace/2.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/2.chip_sw_aon_timer_irq.3533674324 |
| Short name | T337 |
| Test name | |
| Test status | |
| Simulation time | 3967508716 ps |
| CPU time | 353.55 seconds |
| Started | Jun 28 08:18:14 PM PDT 24 |
| Finished | Jun 28 08:24:12 PM PDT 24 |
| Peak memory | 607628 kb |
| Host | smart-bc6624c5-43a3-43a6-9383-7948af7b0a04 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=aon_timer_irq_test:1:new_rules,test_rom:0 +cdc_instrumentati on_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3533674324 - assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co verage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_aon_timer_irq.3533674324 |
| Directory | /workspace/2.chip_sw_aon_timer_irq/latest |
| Test location | /workspace/coverage/default/2.chip_sw_aon_timer_sleep_wdog_sleep_pause.4081848973 |
| Short name | T1077 |
| Test name | |
| Test status | |
| Simulation time | 6807090096 ps |
| CPU time | 343.43 seconds |
| Started | Jun 28 08:19:25 PM PDT 24 |
| Finished | Jun 28 08:25:10 PM PDT 24 |
| Peak memory | 609252 kb |
| Host | smart-375c9052-6d84-4b49-8e12-ddd92c918ee0 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=aon_timer_sleep_wdog_sleep_pause_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=4081848973 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_aon_timer_sleep_wdog_sleep_pause.4081848973 |
| Directory | /workspace/2.chip_sw_aon_timer_sleep_wdog_sleep_pause/latest |
| Test location | /workspace/coverage/default/2.chip_sw_aon_timer_smoketest.1859219119 |
| Short name | T1200 |
| Test name | |
| Test status | |
| Simulation time | 2380675312 ps |
| CPU time | 272.49 seconds |
| Started | Jun 28 08:22:48 PM PDT 24 |
| Finished | Jun 28 08:27:26 PM PDT 24 |
| Peak memory | 609180 kb |
| Host | smart-d15e93df-a772-40d3-b5ce-e70372123de4 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=aon_timer_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1859219119 -assert nopostproc +UVM_TESTNAM E=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 2.chip_sw_aon_timer_smoketest.1859219119 |
| Directory | /workspace/2.chip_sw_aon_timer_smoketest/latest |
| Test location | /workspace/coverage/default/2.chip_sw_aon_timer_wdog_bite_reset.1439182152 |
| Short name | T1223 |
| Test name | |
| Test status | |
| Simulation time | 8323954956 ps |
| CPU time | 596.86 seconds |
| Started | Jun 28 08:19:00 PM PDT 24 |
| Finished | Jun 28 08:28:58 PM PDT 24 |
| Peak memory | 609228 kb |
| Host | smart-010d78d5-f75b-46c7-9249-425beaff4e5a |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=aon_timer_wdog_bite_reset_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 1439182152 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_aon_timer_wdog_bite_reset.1439182152 |
| Directory | /workspace/2.chip_sw_aon_timer_wdog_bite_reset/latest |
| Test location | /workspace/coverage/default/2.chip_sw_aon_timer_wdog_lc_escalate.236331203 |
| Short name | T997 |
| Test name | |
| Test status | |
| Simulation time | 6075809552 ps |
| CPU time | 673.15 seconds |
| Started | Jun 28 08:19:18 PM PDT 24 |
| Finished | Jun 28 08:30:33 PM PDT 24 |
| Peak memory | 608380 kb |
| Host | smart-34c2b1b8-32b8-45db-9432-388f26069e7c |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=aon_timer_wdog_lc_escalate_test:1:new_rules,test_rom:0 +cdc_ instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed =236331203 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_aon_timer_wdog_lc_escalate.236331203 |
| Directory | /workspace/2.chip_sw_aon_timer_wdog_lc_escalate/latest |
| Test location | /workspace/coverage/default/2.chip_sw_ast_clk_outputs.843409188 |
| Short name | T1170 |
| Test name | |
| Test status | |
| Simulation time | 7992892410 ps |
| CPU time | 1002.29 seconds |
| Started | Jun 28 08:21:48 PM PDT 24 |
| Finished | Jun 28 08:38:32 PM PDT 24 |
| Peak memory | 615060 kb |
| Host | smart-c2c10fd9-064e-4523-8e27-afde2b4bfc75 |
| User | root |
| Command | /workspace/default/simv +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=ast_clk_outs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled= 1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=843409188 -assert nopos tproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_ast_clk_outputs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov erage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_ast_clk_outputs.843409188 |
| Directory | /workspace/2.chip_sw_ast_clk_outputs/latest |
| Test location | /workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_lc.3601205426 |
| Short name | T1137 |
| Test name | |
| Test status | |
| Simulation time | 6114132224 ps |
| CPU time | 423.56 seconds |
| Started | Jun 28 08:21:01 PM PDT 24 |
| Finished | Jun 28 08:28:16 PM PDT 24 |
| Peak memory | 619176 kb |
| Host | smart-8523932b-f27e-4d1b-b083-3e85bde1ce0e |
| User | root |
| Command | /workspace/default/simv +chip_clock_source=ChipClockSourceExternal48Mhz +sw_build_device=sim_dv +sw_images=clkmgr_external_clk_src_for_lc_test:1:new_r ules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim .tcl +ntb_random_seed=3601205426 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_transition_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_clkmgr_external_clk_src_for_lc.3601205426 |
| Directory | /workspace/2.chip_sw_clkmgr_external_clk_src_for_lc/latest |
| Test location | /workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_fast_dev.1640485667 |
| Short name | T935 |
| Test name | |
| Test status | |
| Simulation time | 4074931740 ps |
| CPU time | 757.01 seconds |
| Started | Jun 28 08:20:46 PM PDT 24 |
| Finished | Jun 28 08:33:28 PM PDT 24 |
| Peak memory | 611972 kb |
| Host | smart-9ed68588-0b6d-43a1-a3f4-6872a8a5f832 |
| User | root |
| Command | /workspace/default/simv +chip_clock_source=ChipClockSourceExternal96Mhz +calibrate_usb_clk=1 +src_dec_state=DecLcStDev +sw_build_device=sim_dv +sw_ima ges=clkmgr_external_clk_src_for_sw_fast_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1640485667 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ =chip_sw_lc_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_c lkmgr_external_clk_src_for_sw_fast_dev.1640485667 |
| Directory | /workspace/2.chip_sw_clkmgr_external_clk_src_for_sw_fast_dev/latest |
| Test location | /workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_fast_rma.2146392592 |
| Short name | T870 |
| Test name | |
| Test status | |
| Simulation time | 4477881306 ps |
| CPU time | 766.88 seconds |
| Started | Jun 28 08:21:02 PM PDT 24 |
| Finished | Jun 28 08:34:00 PM PDT 24 |
| Peak memory | 611912 kb |
| Host | smart-b6073795-1aa6-4ec7-bb01-4fd597e1324b |
| User | root |
| Command | /workspace/default/simv +chip_clock_source=ChipClockSourceExternal96Mhz +calibrate_usb_clk=1 +src_dec_state=DecLcStRma +sw_build_device=sim_dv +sw_ima ges=clkmgr_external_clk_src_for_sw_fast_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2146392592 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ =chip_sw_lc_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_c lkmgr_external_clk_src_for_sw_fast_rma.2146392592 |
| Directory | /workspace/2.chip_sw_clkmgr_external_clk_src_for_sw_fast_rma/latest |
| Test location | /workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0.2158690105 |
| Short name | T1182 |
| Test name | |
| Test status | |
| Simulation time | 4780511384 ps |
| CPU time | 854.78 seconds |
| Started | Jun 28 08:21:57 PM PDT 24 |
| Finished | Jun 28 08:36:13 PM PDT 24 |
| Peak memory | 610848 kb |
| Host | smart-2e10feda-2634-4b1c-9d24-53ff5d3dfb4e |
| User | root |
| Command | /workspace/default/simv +chip_clock_source=ChipClockSourceExternal96Mhz +calibrate_usb_clk=1 +src_dec_state=DecLcStTestUnlocked0 +sw_build_device=sim_ dv +sw_images=clkmgr_external_clk_src_for_sw_fast_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2158690105 -assert nopostproc +UVM_TESTNAME=chip_base_test +UV M_TEST_SEQ=chip_sw_lc_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2 .chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0.2158690105 |
| Directory | /workspace/2.chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0/latest |
| Test location | /workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_slow_dev.2870734583 |
| Short name | T423 |
| Test name | |
| Test status | |
| Simulation time | 4409942600 ps |
| CPU time | 708.4 seconds |
| Started | Jun 28 08:20:58 PM PDT 24 |
| Finished | Jun 28 08:32:58 PM PDT 24 |
| Peak memory | 609616 kb |
| Host | smart-562a66bf-228a-41a7-abcc-66f1955c81b1 |
| User | root |
| Command | /workspace/default/simv +chip_clock_source=ChipClockSourceExternal48Mhz +calibrate_usb_clk=1 +src_dec_state=DecLcStDev +sw_build_device=sim_dv +sw_ima ges=clkmgr_external_clk_src_for_sw_slow_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2870734583 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ =chip_sw_lc_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_c lkmgr_external_clk_src_for_sw_slow_dev.2870734583 |
| Directory | /workspace/2.chip_sw_clkmgr_external_clk_src_for_sw_slow_dev/latest |
| Test location | /workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_slow_rma.4015187290 |
| Short name | T907 |
| Test name | |
| Test status | |
| Simulation time | 4995759778 ps |
| CPU time | 728.09 seconds |
| Started | Jun 28 08:23:45 PM PDT 24 |
| Finished | Jun 28 08:35:54 PM PDT 24 |
| Peak memory | 611008 kb |
| Host | smart-7fb24cc2-2a22-4dd5-8879-4676c753e14d |
| User | root |
| Command | /workspace/default/simv +chip_clock_source=ChipClockSourceExternal48Mhz +calibrate_usb_clk=1 +src_dec_state=DecLcStRma +sw_build_device=sim_dv +sw_ima ges=clkmgr_external_clk_src_for_sw_slow_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4015187290 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ =chip_sw_lc_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_c lkmgr_external_clk_src_for_sw_slow_rma.4015187290 |
| Directory | /workspace/2.chip_sw_clkmgr_external_clk_src_for_sw_slow_rma/latest |
| Test location | /workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0.1009973891 |
| Short name | T114 |
| Test name | |
| Test status | |
| Simulation time | 4443316884 ps |
| CPU time | 652.42 seconds |
| Started | Jun 28 08:20:14 PM PDT 24 |
| Finished | Jun 28 08:31:08 PM PDT 24 |
| Peak memory | 610764 kb |
| Host | smart-1b18d1da-c659-47e1-b86b-ebabee29eb6b |
| User | root |
| Command | /workspace/default/simv +chip_clock_source=ChipClockSourceExternal48Mhz +calibrate_usb_clk=1 +src_dec_state=DecLcStTestUnlocked0 +sw_build_device=sim_ dv +sw_images=clkmgr_external_clk_src_for_sw_slow_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1009973891 -assert nopostproc +UVM_TESTNAME=chip_base_test +UV M_TEST_SEQ=chip_sw_lc_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2 .chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0.1009973891 |
| Directory | /workspace/2.chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0/latest |
| Test location | /workspace/coverage/default/2.chip_sw_clkmgr_jitter.2478205067 |
| Short name | T1193 |
| Test name | |
| Test status | |
| Simulation time | 3340294478 ps |
| CPU time | 201.66 seconds |
| Started | Jun 28 08:20:29 PM PDT 24 |
| Finished | Jun 28 08:23:52 PM PDT 24 |
| Peak memory | 607128 kb |
| Host | smart-092ac86e-b818-4a92-a6fa-aa7c8e42aa63 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_jitter_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2478205067 -assert nopostproc +UVM_TESTNAME =chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 2.chip_sw_clkmgr_jitter.2478205067 |
| Directory | /workspace/2.chip_sw_clkmgr_jitter/latest |
| Test location | /workspace/coverage/default/2.chip_sw_clkmgr_jitter_frequency.2164261472 |
| Short name | T1212 |
| Test name | |
| Test status | |
| Simulation time | 3348119080 ps |
| CPU time | 440.09 seconds |
| Started | Jun 28 08:20:51 PM PDT 24 |
| Finished | Jun 28 08:28:20 PM PDT 24 |
| Peak memory | 609248 kb |
| Host | smart-4722f4e4-7c62-4b1d-9d41-ed1a71564236 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_jitter_frequency_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2164261472 -assert nopostproc +UV M_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -c m_log /dev/null -cm_name 2.chip_sw_clkmgr_jitter_frequency.2164261472 |
| Directory | /workspace/2.chip_sw_clkmgr_jitter_frequency/latest |
| Test location | /workspace/coverage/default/2.chip_sw_clkmgr_jitter_reduced_freq.3742467122 |
| Short name | T857 |
| Test name | |
| Test status | |
| Simulation time | 2866164676 ps |
| CPU time | 195.75 seconds |
| Started | Jun 28 08:23:36 PM PDT 24 |
| Finished | Jun 28 08:26:54 PM PDT 24 |
| Peak memory | 609108 kb |
| Host | smart-277d94e0-ce2b-44e6-a5e8-103441eba0a7 |
| User | root |
| Command | /workspace/default/simv +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=clkmgr_jitter_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3742467122 -assert nop ostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def ault.vdb -cm_log /dev/null -cm_name 2.chip_sw_clkmgr_jitter_reduced_freq.3742467122 |
| Directory | /workspace/2.chip_sw_clkmgr_jitter_reduced_freq/latest |
| Test location | /workspace/coverage/default/2.chip_sw_clkmgr_off_aes_trans.70744297 |
| Short name | T1275 |
| Test name | |
| Test status | |
| Simulation time | 4235319870 ps |
| CPU time | 614.48 seconds |
| Started | Jun 28 08:27:01 PM PDT 24 |
| Finished | Jun 28 08:37:16 PM PDT 24 |
| Peak memory | 609180 kb |
| Host | smart-6636126e-4eab-4181-92ae-483cb251a0e8 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_off_aes_trans_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70744297 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_clkmgr_off_aes_trans.70744297 |
| Directory | /workspace/2.chip_sw_clkmgr_off_aes_trans/latest |
| Test location | /workspace/coverage/default/2.chip_sw_clkmgr_off_hmac_trans.438850963 |
| Short name | T1197 |
| Test name | |
| Test status | |
| Simulation time | 5468169516 ps |
| CPU time | 510.73 seconds |
| Started | Jun 28 08:22:38 PM PDT 24 |
| Finished | Jun 28 08:31:10 PM PDT 24 |
| Peak memory | 609116 kb |
| Host | smart-3948ea71-1e4c-4a3e-940d-2733392f2380 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_off_hmac_trans_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=438850963 -assert nopostproc +UVM_T ESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l og /dev/null -cm_name 2.chip_sw_clkmgr_off_hmac_trans.438850963 |
| Directory | /workspace/2.chip_sw_clkmgr_off_hmac_trans/latest |
| Test location | /workspace/coverage/default/2.chip_sw_clkmgr_off_kmac_trans.330225880 |
| Short name | T1029 |
| Test name | |
| Test status | |
| Simulation time | 4174144264 ps |
| CPU time | 507.54 seconds |
| Started | Jun 28 08:25:43 PM PDT 24 |
| Finished | Jun 28 08:34:13 PM PDT 24 |
| Peak memory | 609192 kb |
| Host | smart-1f3d93a9-091f-4b48-9925-faf686af2836 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_off_kmac_trans_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=330225880 -assert nopostproc +UVM_T ESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l og /dev/null -cm_name 2.chip_sw_clkmgr_off_kmac_trans.330225880 |
| Directory | /workspace/2.chip_sw_clkmgr_off_kmac_trans/latest |
| Test location | /workspace/coverage/default/2.chip_sw_clkmgr_off_otbn_trans.666721171 |
| Short name | T1163 |
| Test name | |
| Test status | |
| Simulation time | 5055062032 ps |
| CPU time | 413.22 seconds |
| Started | Jun 28 08:26:31 PM PDT 24 |
| Finished | Jun 28 08:33:26 PM PDT 24 |
| Peak memory | 609200 kb |
| Host | smart-7941d7e9-c70b-4caa-87b0-4dacb5dbc3b8 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_off_otbn_trans_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=666721171 -assert nopostproc +UVM_T ESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l og /dev/null -cm_name 2.chip_sw_clkmgr_off_otbn_trans.666721171 |
| Directory | /workspace/2.chip_sw_clkmgr_off_otbn_trans/latest |
| Test location | /workspace/coverage/default/2.chip_sw_clkmgr_off_peri.3140212416 |
| Short name | T1201 |
| Test name | |
| Test status | |
| Simulation time | 9761186088 ps |
| CPU time | 1219.14 seconds |
| Started | Jun 28 08:25:45 PM PDT 24 |
| Finished | Jun 28 08:46:07 PM PDT 24 |
| Peak memory | 607292 kb |
| Host | smart-df3a5cf3-97f8-4795-8f06-cdb3198c5d95 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=30_000_000 +sw_build_device=sim_dv +sw_images=clkmgr_off_peri_test:1:new_rules,test_rom:0 +cdc_instrumenta tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3140212416 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/ coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_clkmgr_off_peri.3140212416 |
| Directory | /workspace/2.chip_sw_clkmgr_off_peri/latest |
| Test location | /workspace/coverage/default/2.chip_sw_clkmgr_reset_frequency.34921753 |
| Short name | T298 |
| Test name | |
| Test status | |
| Simulation time | 3778114968 ps |
| CPU time | 585.56 seconds |
| Started | Jun 28 08:22:25 PM PDT 24 |
| Finished | Jun 28 08:32:16 PM PDT 24 |
| Peak memory | 609152 kb |
| Host | smart-fb6278c9-b43e-4f4f-9cc6-4f189efd06dd |
| User | root |
| Command | /workspace/default/simv +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=clkmgr_reset_frequency_test:1:new_rules,test_rom:0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34921753 -ass ert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_clkmgr_reset_frequency.34921753 |
| Directory | /workspace/2.chip_sw_clkmgr_reset_frequency/latest |
| Test location | /workspace/coverage/default/2.chip_sw_clkmgr_sleep_frequency.620421844 |
| Short name | T1185 |
| Test name | |
| Test status | |
| Simulation time | 4729105524 ps |
| CPU time | 797.19 seconds |
| Started | Jun 28 08:26:41 PM PDT 24 |
| Finished | Jun 28 08:40:00 PM PDT 24 |
| Peak memory | 609260 kb |
| Host | smart-65fe4921-8cea-4e47-bf4b-646e23fb26b5 |
| User | root |
| Command | /workspace/default/simv +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=clkmgr_sleep_frequency_test:1:new_rules,test_rom:0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=620421844 -as sert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove rage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_clkmgr_sleep_frequency.620421844 |
| Directory | /workspace/2.chip_sw_clkmgr_sleep_frequency/latest |
| Test location | /workspace/coverage/default/2.chip_sw_clkmgr_smoketest.2353571014 |
| Short name | T1142 |
| Test name | |
| Test status | |
| Simulation time | 2772871792 ps |
| CPU time | 211.03 seconds |
| Started | Jun 28 08:25:09 PM PDT 24 |
| Finished | Jun 28 08:28:44 PM PDT 24 |
| Peak memory | 607132 kb |
| Host | smart-4ffb60d9-d9b9-46e6-83be-fbd7c8da3698 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2353571014 -assert nopostproc +UVM_TESTNAME=c hip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n ull -cm_name 2.chip_sw_clkmgr_smoketest.2353571014 |
| Directory | /workspace/2.chip_sw_clkmgr_smoketest/latest |
| Test location | /workspace/coverage/default/2.chip_sw_csrng_edn_concurrency.3325152479 |
| Short name | T1090 |
| Test name | |
| Test status | |
| Simulation time | 9234785314 ps |
| CPU time | 2166.05 seconds |
| Started | Jun 28 08:19:46 PM PDT 24 |
| Finished | Jun 28 08:55:56 PM PDT 24 |
| Peak memory | 608172 kb |
| Host | smart-0ee9667a-3d4d-4278-905b-9f2c5297ace0 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=140_000_000 +rng_srate_value_min=15 +rng_srate_value_max=20 +accelerate_cold_power_up_time=3 +accelerate_r egulators_power_up_time=2 +sw_build_device=sim_dv +sw_images=csrng_edn_concurrency_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3325152479 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd b -cm_log /dev/null -cm_name 2.chip_sw_csrng_edn_concurrency.3325152479 |
| Directory | /workspace/2.chip_sw_csrng_edn_concurrency/latest |
| Test location | /workspace/coverage/default/2.chip_sw_csrng_fuse_en_sw_app_read_test.2157322715 |
| Short name | T174 |
| Test name | |
| Test status | |
| Simulation time | 5228078932 ps |
| CPU time | 553.4 seconds |
| Started | Jun 28 08:21:04 PM PDT 24 |
| Finished | Jun 28 08:30:27 PM PDT 24 |
| Peak memory | 609156 kb |
| Host | smart-46ff8a2a-c514-473d-9072-a12eb5f8a65c |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=15_000_000 +sw_build_device=sim_dv +sw_images=csrng_fuse_en_sw_app_read:1:new_rules,test_rom:0 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21573 22715 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_entropy_src_fuse_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_csrng_fuse_en_sw_app_read_test.2157322715 |
| Directory | /workspace/2.chip_sw_csrng_fuse_en_sw_app_read_test/latest |
| Test location | /workspace/coverage/default/2.chip_sw_csrng_kat_test.1343743972 |
| Short name | T1221 |
| Test name | |
| Test status | |
| Simulation time | 2629216730 ps |
| CPU time | 267.1 seconds |
| Started | Jun 28 08:19:54 PM PDT 24 |
| Finished | Jun 28 08:24:22 PM PDT 24 |
| Peak memory | 607624 kb |
| Host | smart-2acb13bc-9dbd-4b4d-8eed-40880d79ea32 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=csrng_kat_test:1:new_rules,test_rom:0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1343743972 -asse rt nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera ge/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_csrng_kat_test.1343743972 |
| Directory | /workspace/2.chip_sw_csrng_kat_test/latest |
| Test location | /workspace/coverage/default/2.chip_sw_csrng_lc_hw_debug_en_test.1147565426 |
| Short name | T415 |
| Test name | |
| Test status | |
| Simulation time | 6546644750 ps |
| CPU time | 825.22 seconds |
| Started | Jun 28 08:18:28 PM PDT 24 |
| Finished | Jun 28 08:32:20 PM PDT 24 |
| Peak memory | 608912 kb |
| Host | smart-dfe25c96-7ded-464f-a924-00c7e81d77f2 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=15_000_000 +rng_srate_value_min=15 +use_otp_image=OtpTypeLcStTestUnlocked0 +sw_build_device=sim_dv +sw_ima ges=csrng_lc_hw_debug_en_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1147565426 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_csrng_ lc_hw_debug_en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_csr ng_lc_hw_debug_en_test.1147565426 |
| Directory | /workspace/2.chip_sw_csrng_lc_hw_debug_en_test/latest |
| Test location | /workspace/coverage/default/2.chip_sw_csrng_smoketest.201515656 |
| Short name | T903 |
| Test name | |
| Test status | |
| Simulation time | 3014648266 ps |
| CPU time | 322.12 seconds |
| Started | Jun 28 08:23:08 PM PDT 24 |
| Finished | Jun 28 08:28:37 PM PDT 24 |
| Peak memory | 607104 kb |
| Host | smart-f28c999d-2d45-4a18-af5b-c56e3d4d1ba5 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=csrng_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=201515656 -assert nopostproc +UVM_TESTNAME=chi p_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul l -cm_name 2.chip_sw_csrng_smoketest.201515656 |
| Directory | /workspace/2.chip_sw_csrng_smoketest/latest |
| Test location | /workspace/coverage/default/2.chip_sw_edn_auto_mode.3020061759 |
| Short name | T93 |
| Test name | |
| Test status | |
| Simulation time | 4465855354 ps |
| CPU time | 961.5 seconds |
| Started | Jun 28 08:19:51 PM PDT 24 |
| Finished | Jun 28 08:35:55 PM PDT 24 |
| Peak memory | 609316 kb |
| Host | smart-7816f53b-fbf4-4a02-85c6-3d68a09aed44 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +rng_srate_value=5 +accelerate_cold_power_up_time=3 +accelerate_regulators_power_up_time=2 +sw_ build_device=sim_dv +sw_images=edn_auto_mode:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3020061759 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ =chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_edn_ auto_mode.3020061759 |
| Directory | /workspace/2.chip_sw_edn_auto_mode/latest |
| Test location | /workspace/coverage/default/2.chip_sw_edn_boot_mode.641143871 |
| Short name | T629 |
| Test name | |
| Test status | |
| Simulation time | 3276639800 ps |
| CPU time | 661.15 seconds |
| Started | Jun 28 08:19:57 PM PDT 24 |
| Finished | Jun 28 08:30:59 PM PDT 24 |
| Peak memory | 607788 kb |
| Host | smart-efb01358-7fb1-4aec-a23b-c0cf844200f1 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +rng_srate_value=5 +accelerate_cold_power_up_time=3 +accelerate_regulators_power_up_time=2 +sw_ build_device=sim_dv +sw_images=edn_boot_mode:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=641143871 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ= chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_edn_b oot_mode.641143871 |
| Directory | /workspace/2.chip_sw_edn_boot_mode/latest |
| Test location | /workspace/coverage/default/2.chip_sw_edn_entropy_reqs.2122207754 |
| Short name | T433 |
| Test name | |
| Test status | |
| Simulation time | 6587047980 ps |
| CPU time | 1086.38 seconds |
| Started | Jun 28 08:21:14 PM PDT 24 |
| Finished | Jun 28 08:39:23 PM PDT 24 |
| Peak memory | 609316 kb |
| Host | smart-ef7c1f7c-d8ad-4379-b11c-6c431cd75c46 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=15000000 +rng_srate_value_min=15 +rng_srate_value_max=30 +sw_build_device=sim_dv +sw_images=entropy_src_ed n_reqs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2122207754 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_edn_entropy_reqs.2122207754 |
| Directory | /workspace/2.chip_sw_edn_entropy_reqs/latest |
| Test location | /workspace/coverage/default/2.chip_sw_edn_entropy_reqs_jitter.1059610653 |
| Short name | T1304 |
| Test name | |
| Test status | |
| Simulation time | 6436311223 ps |
| CPU time | 1218.11 seconds |
| Started | Jun 28 08:22:41 PM PDT 24 |
| Finished | Jun 28 08:43:00 PM PDT 24 |
| Peak memory | 609436 kb |
| Host | smart-f871cb0d-d6d1-477f-a1b4-d94ce4e60c79 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=15000000 +rng_srate_value_min=15 +rng_srate_value_max=30 +en_jitter=1 +sw_build_device=sim_dv +sw_images=e ntropy_src_edn_reqs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1059610653 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_edn_entropy_reqs_jitter.1059610653 |
| Directory | /workspace/2.chip_sw_edn_entropy_reqs_jitter/latest |
| Test location | /workspace/coverage/default/2.chip_sw_edn_kat.2185148412 |
| Short name | T1251 |
| Test name | |
| Test status | |
| Simulation time | 3557865900 ps |
| CPU time | 554.18 seconds |
| Started | Jun 28 08:20:46 PM PDT 24 |
| Finished | Jun 28 08:30:07 PM PDT 24 |
| Peak memory | 614280 kb |
| Host | smart-a73bc410-3877-4a4c-99be-5a07f80d9c0c |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +rng_srate_value=5 +disable_assert_edn_output_diff_from_prev=1 +accelerate_cold_power_up_time=3 +accelerate_regulators_power_up_time=2 +sw_build_device=sim_dv +sw_images=edn_kat:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2185148412 -assert nopostproc +UVM _TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm _log /dev/null -cm_name 2.chip_sw_edn_kat.2185148412 |
| Directory | /workspace/2.chip_sw_edn_kat/latest |
| Test location | /workspace/coverage/default/2.chip_sw_edn_sw_mode.1925962898 |
| Short name | T979 |
| Test name | |
| Test status | |
| Simulation time | 6700661000 ps |
| CPU time | 1537 seconds |
| Started | Jun 28 08:20:09 PM PDT 24 |
| Finished | Jun 28 08:45:47 PM PDT 24 |
| Peak memory | 609140 kb |
| Host | smart-61f1ed8c-a714-4d70-ae39-09f122c98b99 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=edn_sw_mode:1:new_rules,test_rom:0 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1925962898 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/ default.vdb -cm_log /dev/null -cm_name 2.chip_sw_edn_sw_mode.1925962898 |
| Directory | /workspace/2.chip_sw_edn_sw_mode/latest |
| Test location | /workspace/coverage/default/2.chip_sw_entropy_src_ast_rng_req.349454856 |
| Short name | T281 |
| Test name | |
| Test status | |
| Simulation time | 3321366696 ps |
| CPU time | 175.05 seconds |
| Started | Jun 28 08:18:33 PM PDT 24 |
| Finished | Jun 28 08:21:33 PM PDT 24 |
| Peak memory | 609176 kb |
| Host | smart-30e6108c-26ca-4f03-a1b9-6aab34ddde06 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=15_000_000 +sw_build_device=sim_dv +sw_images=entropy_src_ast_rng_req_test:1:new_rules,test_rom:0 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34 9454856 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_entropy_src_ast_rng_req.349454856 |
| Directory | /workspace/2.chip_sw_entropy_src_ast_rng_req/latest |
| Test location | /workspace/coverage/default/2.chip_sw_entropy_src_csrng.2143564779 |
| Short name | T324 |
| Test name | |
| Test status | |
| Simulation time | 6005631720 ps |
| CPU time | 1124.81 seconds |
| Started | Jun 28 08:20:24 PM PDT 24 |
| Finished | Jun 28 08:39:10 PM PDT 24 |
| Peak memory | 608104 kb |
| Host | smart-e8602c28-5f91-4bee-bc5e-d1de364cff38 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=50_000_000 +rng_srate_value_min=15 +rng_srate_value_max=30 +sw_build_device=sim_dv +sw_images=entropy_src_ csrng_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2143564779 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_entropy_src_csrng.2143564779 |
| Directory | /workspace/2.chip_sw_entropy_src_csrng/latest |
| Test location | /workspace/coverage/default/2.chip_sw_entropy_src_kat_test.2672424047 |
| Short name | T119 |
| Test name | |
| Test status | |
| Simulation time | 2426780192 ps |
| CPU time | 277.36 seconds |
| Started | Jun 28 08:19:48 PM PDT 24 |
| Finished | Jun 28 08:24:29 PM PDT 24 |
| Peak memory | 609144 kb |
| Host | smart-484eed06-21e6-4df0-8def-7bc66f90d8b4 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=entropy_src_kat_test:1:new_rules,test_rom:0 +cdc_instrumenta tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2672424047 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/ coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_entropy_src_kat_test.2672424047 |
| Directory | /workspace/2.chip_sw_entropy_src_kat_test/latest |
| Test location | /workspace/coverage/default/2.chip_sw_entropy_src_smoketest.995426026 |
| Short name | T1180 |
| Test name | |
| Test status | |
| Simulation time | 3351597336 ps |
| CPU time | 452.2 seconds |
| Started | Jun 28 08:30:41 PM PDT 24 |
| Finished | Jun 28 08:38:15 PM PDT 24 |
| Peak memory | 609320 kb |
| Host | smart-09966e39-2c50-40b7-b08f-31d62988b9cc |
| User | root |
| Command | /workspace/default/simv +rng_srate_value_min=15 +rng_srate_value_max=30 +sw_build_device=sim_dv +sw_images=entropy_src_smoketest:1:new_rules,test_rom: 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand om_seed=995426026 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_entropy_src_smoketest.995426026 |
| Directory | /workspace/2.chip_sw_entropy_src_smoketest/latest |
| Test location | /workspace/coverage/default/2.chip_sw_example_concurrency.2394619652 |
| Short name | T1031 |
| Test name | |
| Test status | |
| Simulation time | 3362141248 ps |
| CPU time | 305.52 seconds |
| Started | Jun 28 08:13:41 PM PDT 24 |
| Finished | Jun 28 08:18:51 PM PDT 24 |
| Peak memory | 609188 kb |
| Host | smart-d730b565-5752-4ad1-8408-d56f63e3fba9 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=example_concurrency_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2394619652 -assert nopostproc +UVM_TE STNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo g /dev/null -cm_name 2.chip_sw_example_concurrency.2394619652 |
| Directory | /workspace/2.chip_sw_example_concurrency/latest |
| Test location | /workspace/coverage/default/2.chip_sw_example_flash.3425284418 |
| Short name | T984 |
| Test name | |
| Test status | |
| Simulation time | 3027351344 ps |
| CPU time | 294.4 seconds |
| Started | Jun 28 08:14:31 PM PDT 24 |
| Finished | Jun 28 08:19:27 PM PDT 24 |
| Peak memory | 609184 kb |
| Host | smart-65591f42-b2a2-4eb0-8fb9-35fb89385e33 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=example_test_from_flash:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3425284418 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_example_flash.3425284418 |
| Directory | /workspace/2.chip_sw_example_flash/latest |
| Test location | /workspace/coverage/default/2.chip_sw_example_manufacturer.2378237950 |
| Short name | T885 |
| Test name | |
| Test status | |
| Simulation time | 2676707172 ps |
| CPU time | 192.75 seconds |
| Started | Jun 28 08:14:34 PM PDT 24 |
| Finished | Jun 28 08:17:48 PM PDT 24 |
| Peak memory | 606460 kb |
| Host | smart-12291548-4816-4822-8586-d4b2119b95f0 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=example_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2378237950 -assert nopostproc +UVM_TESTNAME=chip_ base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_example_manufacturer.2378237950 |
| Directory | /workspace/2.chip_sw_example_manufacturer/latest |
| Test location | /workspace/coverage/default/2.chip_sw_example_rom.4256907733 |
| Short name | T1082 |
| Test name | |
| Test status | |
| Simulation time | 2506421528 ps |
| CPU time | 124.38 seconds |
| Started | Jun 28 08:15:59 PM PDT 24 |
| Finished | Jun 28 08:18:07 PM PDT 24 |
| Peak memory | 607264 kb |
| Host | smart-e6c2cb01-1987-4645-8996-bf19aa16a771 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:test_in_rom:new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4256907733 -assert nopostproc +UVM_TEST NAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_example_rom.4256907733 |
| Directory | /workspace/2.chip_sw_example_rom/latest |
| Test location | /workspace/coverage/default/2.chip_sw_exit_test_unlocked_bootstrap.3390114577 |
| Short name | T146 |
| Test name | |
| Test status | |
| Simulation time | 58440510250 ps |
| CPU time | 10705.8 seconds |
| Started | Jun 28 08:18:29 PM PDT 24 |
| Finished | Jun 28 11:17:02 PM PDT 24 |
| Peak memory | 623256 kb |
| Host | smart-5a49e02d-0547-4922-b8b2-47f99c1abcb7 |
| User | root |
| Command | /workspace/default/simv +flash_program_latency=5 +sw_test_timeout_ns=150_000_000 +sw_build_device=sim_dv +sw_images=exit_test_unlocked_bootstrap:1:new _rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/s im.tcl +ntb_random_seed=3390114577 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_exit_test_unlocked_bootstrap_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_exit_test_unlocked_bootstrap.3390114577 |
| Directory | /workspace/2.chip_sw_exit_test_unlocked_bootstrap/latest |
| Test location | /workspace/coverage/default/2.chip_sw_flash_crash_alert.884849735 |
| Short name | T1067 |
| Test name | |
| Test status | |
| Simulation time | 5731581008 ps |
| CPU time | 807.57 seconds |
| Started | Jun 28 08:21:09 PM PDT 24 |
| Finished | Jun 28 08:34:43 PM PDT 24 |
| Peak memory | 609364 kb |
| Host | smart-660ac626-f0c3-443b-a702-a005e78cdb7b |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=8_000_000 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1: new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tool s/sim.tcl +ntb_random_seed=884849735 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_flash_host_gnt_err_inj_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_flash_crash_alert.884849735 |
| Directory | /workspace/2.chip_sw_flash_crash_alert/latest |
| Test location | /workspace/coverage/default/2.chip_sw_flash_ctrl_access.3087841889 |
| Short name | T967 |
| Test name | |
| Test status | |
| Simulation time | 5462373400 ps |
| CPU time | 1062.61 seconds |
| Started | Jun 28 08:15:38 PM PDT 24 |
| Finished | Jun 28 08:33:22 PM PDT 24 |
| Peak memory | 606680 kb |
| Host | smart-9d8d0171-52b2-48ff-8f5b-c93339b638af |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=flash_ctrl_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3087841889 -assert nopostproc +UVM_TESTNAME=ch ip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu ll -cm_name 2.chip_sw_flash_ctrl_access.3087841889 |
| Directory | /workspace/2.chip_sw_flash_ctrl_access/latest |
| Test location | /workspace/coverage/default/2.chip_sw_flash_ctrl_access_jitter_en.4156299436 |
| Short name | T1216 |
| Test name | |
| Test status | |
| Simulation time | 6288105938 ps |
| CPU time | 1076.16 seconds |
| Started | Jun 28 08:16:42 PM PDT 24 |
| Finished | Jun 28 08:34:39 PM PDT 24 |
| Peak memory | 609156 kb |
| Host | smart-c1c709b6-e9b9-4134-aef4-405945e0038d |
| User | root |
| Command | /workspace/default/simv +en_jitter=1 +sw_build_device=sim_dv +sw_images=flash_ctrl_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4156299436 -assert nopostproc +UV M_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -c m_log /dev/null -cm_name 2.chip_sw_flash_ctrl_access_jitter_en.4156299436 |
| Directory | /workspace/2.chip_sw_flash_ctrl_access_jitter_en/latest |
| Test location | /workspace/coverage/default/2.chip_sw_flash_ctrl_access_jitter_en_reduced_freq.3893708173 |
| Short name | T1114 |
| Test name | |
| Test status | |
| Simulation time | 6964498262 ps |
| CPU time | 1019.27 seconds |
| Started | Jun 28 08:27:48 PM PDT 24 |
| Finished | Jun 28 08:44:56 PM PDT 24 |
| Peak memory | 609200 kb |
| Host | smart-8e01016d-3e48-4b67-8279-b9760a9eb49e |
| User | root |
| Command | /workspace/default/simv +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=flash_ctrl_test:1:new_rules,test_rom:0 +cdc_instrumentati on_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3893708173 - assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co verage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_flash_ctrl_access_jitter_en_reduced_freq.3893708173 |
| Directory | /workspace/2.chip_sw_flash_ctrl_access_jitter_en_reduced_freq/latest |
| Test location | /workspace/coverage/default/2.chip_sw_flash_ctrl_clock_freqs.3003271840 |
| Short name | T1171 |
| Test name | |
| Test status | |
| Simulation time | 5493739905 ps |
| CPU time | 1435.39 seconds |
| Started | Jun 28 08:17:57 PM PDT 24 |
| Finished | Jun 28 08:41:53 PM PDT 24 |
| Peak memory | 609168 kb |
| Host | smart-00e08d9c-a01e-414c-96e4-b8eaa5d1688b |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=flash_ctrl_clock_freqs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3003271840 -assert nopostproc +UVM _TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm _log /dev/null -cm_name 2.chip_sw_flash_ctrl_clock_freqs.3003271840 |
| Directory | /workspace/2.chip_sw_flash_ctrl_clock_freqs/latest |
| Test location | /workspace/coverage/default/2.chip_sw_flash_ctrl_idle_low_power.903524411 |
| Short name | T1259 |
| Test name | |
| Test status | |
| Simulation time | 3390905880 ps |
| CPU time | 333.39 seconds |
| Started | Jun 28 08:17:23 PM PDT 24 |
| Finished | Jun 28 08:22:57 PM PDT 24 |
| Peak memory | 609160 kb |
| Host | smart-e5e12f1a-5b81-4aab-844e-0ba3f86f0570 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=flash_ctrl_idle_low_power_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=903524411 -assert nopostproc +U VM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb - cm_log /dev/null -cm_name 2.chip_sw_flash_ctrl_idle_low_power.903524411 |
| Directory | /workspace/2.chip_sw_flash_ctrl_idle_low_power/latest |
| Test location | /workspace/coverage/default/2.chip_sw_flash_ctrl_lc_rw_en.4110071998 |
| Short name | T1276 |
| Test name | |
| Test status | |
| Simulation time | 3600691400 ps |
| CPU time | 422.79 seconds |
| Started | Jun 28 08:16:13 PM PDT 24 |
| Finished | Jun 28 08:23:17 PM PDT 24 |
| Peak memory | 609176 kb |
| Host | smart-2bcd5ace-c7b5-48d3-8d5e-58f1ef92b90f |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=flash_ctrl_lc_rw_en_test:1:new_rules,test_rom:0 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41 10071998 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_flash_ctrl_lc_rw_en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_flash_ctrl_lc_rw_en.4110071998 |
| Directory | /workspace/2.chip_sw_flash_ctrl_lc_rw_en/latest |
| Test location | /workspace/coverage/default/2.chip_sw_flash_ctrl_mem_protection.1031348823 |
| Short name | T859 |
| Test name | |
| Test status | |
| Simulation time | 5225407152 ps |
| CPU time | 1261.06 seconds |
| Started | Jun 28 08:22:26 PM PDT 24 |
| Finished | Jun 28 08:43:32 PM PDT 24 |
| Peak memory | 607092 kb |
| Host | smart-901b72f9-716f-4d5a-99d1-10b9cce55043 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=flash_ctrl_mem_protection_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1031348823 -assert nopostproc + UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_flash_ctrl_mem_protection.1031348823 |
| Directory | /workspace/2.chip_sw_flash_ctrl_mem_protection/latest |
| Test location | /workspace/coverage/default/2.chip_sw_flash_ctrl_ops.3433309091 |
| Short name | T339 |
| Test name | |
| Test status | |
| Simulation time | 3399895668 ps |
| CPU time | 790.6 seconds |
| Started | Jun 28 08:16:28 PM PDT 24 |
| Finished | Jun 28 08:29:41 PM PDT 24 |
| Peak memory | 609188 kb |
| Host | smart-b520ed87-3a1d-4a2a-b83c-a27908ad02ac |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=50_000_000 +sw_build_device=sim_dv +sw_images=flash_ctrl_ops_test:1:new_rules,test_rom:0 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3433309091 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/c overage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_flash_ctrl_ops.3433309091 |
| Directory | /workspace/2.chip_sw_flash_ctrl_ops/latest |
| Test location | /workspace/coverage/default/2.chip_sw_flash_ctrl_ops_jitter_en.1907150745 |
| Short name | T342 |
| Test name | |
| Test status | |
| Simulation time | 4242510894 ps |
| CPU time | 793.55 seconds |
| Started | Jun 28 08:15:57 PM PDT 24 |
| Finished | Jun 28 08:29:13 PM PDT 24 |
| Peak memory | 607696 kb |
| Host | smart-87d9b345-44eb-4b67-94c2-6dd3007954db |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=50_000_000 +en_jitter=1 +sw_build_device=sim_dv +sw_images=flash_ctrl_ops_test:1:new_rules,test_rom:0 +cdc _instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see d=1907150745 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_flash_ctrl_ops_jitter_en.1907150745 |
| Directory | /workspace/2.chip_sw_flash_ctrl_ops_jitter_en/latest |
| Test location | /workspace/coverage/default/2.chip_sw_flash_ctrl_ops_jitter_en_reduced_freq.3592212268 |
| Short name | T338 |
| Test name | |
| Test status | |
| Simulation time | 5701765193 ps |
| CPU time | 738.27 seconds |
| Started | Jun 28 08:23:36 PM PDT 24 |
| Finished | Jun 28 08:35:56 PM PDT 24 |
| Peak memory | 609104 kb |
| Host | smart-52bed8f7-c915-490a-9f54-e8d4266aa77a |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=50_000_000 +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=flash_ctrl_ops_test:1:new_ rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si m.tcl +ntb_random_seed=3592212268 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_flash_ctrl_ops_jitter_en_reduced_freq.3592212268 |
| Directory | /workspace/2.chip_sw_flash_ctrl_ops_jitter_en_reduced_freq/latest |
| Test location | /workspace/coverage/default/2.chip_sw_flash_ctrl_write_clear.4280292126 |
| Short name | T1059 |
| Test name | |
| Test status | |
| Simulation time | 3179494580 ps |
| CPU time | 431.24 seconds |
| Started | Jun 28 08:22:01 PM PDT 24 |
| Finished | Jun 28 08:29:14 PM PDT 24 |
| Peak memory | 607120 kb |
| Host | smart-7f8748f4-4cca-47fa-b68e-161a749cfdb6 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=8_000_000 +sw_build_device=sim_dv +sw_images=flash_ctrl_write_clear_test:1:new_rules,test_rom:0 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4280292 126 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_flash_ctrl_write_clear.4280292126 |
| Directory | /workspace/2.chip_sw_flash_ctrl_write_clear/latest |
| Test location | /workspace/coverage/default/2.chip_sw_flash_init_reduced_freq.3947226210 |
| Short name | T166 |
| Test name | |
| Test status | |
| Simulation time | 24033619846 ps |
| CPU time | 2068.68 seconds |
| Started | Jun 28 08:21:42 PM PDT 24 |
| Finished | Jun 28 08:56:13 PM PDT 24 |
| Peak memory | 609580 kb |
| Host | smart-89638844-b107-4e7e-bb68-5563de7367c6 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=25_000_000 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=flash_init_test:0:test_in_rom:new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=3947226210 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_flash_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_flash_init_reduced_freq.3947226210 |
| Directory | /workspace/2.chip_sw_flash_init_reduced_freq/latest |
| Test location | /workspace/coverage/default/2.chip_sw_flash_scrambling_smoketest.635712215 |
| Short name | T891 |
| Test name | |
| Test status | |
| Simulation time | 2469372464 ps |
| CPU time | 184.44 seconds |
| Started | Jun 28 08:26:26 PM PDT 24 |
| Finished | Jun 28 08:29:33 PM PDT 24 |
| Peak memory | 607324 kb |
| Host | smart-d8155f3b-3ffc-4e06-b354-7cb61093ee67 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=flash_scrambling_smoketest:1:new_rules,flash_scrambling_smoket est_otp_img_rma:4,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=635712215 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_flash_scrambling_smoketest.635712215 |
| Directory | /workspace/2.chip_sw_flash_scrambling_smoketest/latest |
| Test location | /workspace/coverage/default/2.chip_sw_gpio_smoketest.2190603107 |
| Short name | T37 |
| Test name | |
| Test status | |
| Simulation time | 2810246473 ps |
| CPU time | 387.38 seconds |
| Started | Jun 28 08:24:00 PM PDT 24 |
| Finished | Jun 28 08:30:30 PM PDT 24 |
| Peak memory | 607596 kb |
| Host | smart-9d31fffc-3627-47a9-9d70-6f95c19ab436 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=gpio_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2190603107 -assert nopostproc +UVM_TESTNAME=chi p_base_test +UVM_TEST_SEQ=chip_sw_gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 2.chip_sw_gpio_smoketest.2190603107 |
| Directory | /workspace/2.chip_sw_gpio_smoketest/latest |
| Test location | /workspace/coverage/default/2.chip_sw_hmac_enc.2133219398 |
| Short name | T297 |
| Test name | |
| Test status | |
| Simulation time | 3805426232 ps |
| CPU time | 304.52 seconds |
| Started | Jun 28 08:19:11 PM PDT 24 |
| Finished | Jun 28 08:24:17 PM PDT 24 |
| Peak memory | 607080 kb |
| Host | smart-c976dfbc-ffe9-4d62-a6e3-e700afd56399 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=hmac_enc_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2133219398 -assert nopostproc +UVM_TESTNAME=chip _base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_hmac_enc.2133219398 |
| Directory | /workspace/2.chip_sw_hmac_enc/latest |
| Test location | /workspace/coverage/default/2.chip_sw_hmac_enc_idle.1718031277 |
| Short name | T934 |
| Test name | |
| Test status | |
| Simulation time | 2881987756 ps |
| CPU time | 401.49 seconds |
| Started | Jun 28 08:19:21 PM PDT 24 |
| Finished | Jun 28 08:26:05 PM PDT 24 |
| Peak memory | 607120 kb |
| Host | smart-69e5a74c-2f9c-4a56-bb45-26e837794358 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=hmac_enc_idle_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1718031277 -assert nopostproc +UVM_TESTNAME =chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 2.chip_sw_hmac_enc_idle.1718031277 |
| Directory | /workspace/2.chip_sw_hmac_enc_idle/latest |
| Test location | /workspace/coverage/default/2.chip_sw_hmac_enc_jitter_en.3800247195 |
| Short name | T341 |
| Test name | |
| Test status | |
| Simulation time | 3066392974 ps |
| CPU time | 278 seconds |
| Started | Jun 28 08:20:00 PM PDT 24 |
| Finished | Jun 28 08:24:38 PM PDT 24 |
| Peak memory | 609180 kb |
| Host | smart-47cd65dd-379f-464a-a72c-da0fa8cc206d |
| User | root |
| Command | /workspace/default/simv +en_jitter=1 +sw_build_device=sim_dv +sw_images=hmac_enc_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3800247195 -assert nopostproc +UVM_ TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_ log /dev/null -cm_name 2.chip_sw_hmac_enc_jitter_en.3800247195 |
| Directory | /workspace/2.chip_sw_hmac_enc_jitter_en/latest |
| Test location | /workspace/coverage/default/2.chip_sw_hmac_enc_jitter_en_reduced_freq.2033254413 |
| Short name | T1295 |
| Test name | |
| Test status | |
| Simulation time | 3510889039 ps |
| CPU time | 270.62 seconds |
| Started | Jun 28 08:22:23 PM PDT 24 |
| Finished | Jun 28 08:27:00 PM PDT 24 |
| Peak memory | 607392 kb |
| Host | smart-0f408693-f192-43ad-855c-fd769309c0d6 |
| User | root |
| Command | /workspace/default/simv +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=hmac_enc_test:1:new_rules,test_rom:0 +cdc_instrumentation _enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2033254413 -as sert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove rage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_hmac_enc_jitter_en_reduced_freq.2033254413 |
| Directory | /workspace/2.chip_sw_hmac_enc_jitter_en_reduced_freq/latest |
| Test location | /workspace/coverage/default/2.chip_sw_hmac_multistream.4065592737 |
| Short name | T1231 |
| Test name | |
| Test status | |
| Simulation time | 6589358650 ps |
| CPU time | 1726.33 seconds |
| Started | Jun 28 08:20:03 PM PDT 24 |
| Finished | Jun 28 08:48:50 PM PDT 24 |
| Peak memory | 609244 kb |
| Host | smart-18a78084-bd46-45ca-8e88-d095e0650f86 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=hmac_multistream_functest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4065592737 -assert nopostproc +UVM_T ESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l og /dev/null -cm_name 2.chip_sw_hmac_multistream.4065592737 |
| Directory | /workspace/2.chip_sw_hmac_multistream/latest |
| Test location | /workspace/coverage/default/2.chip_sw_hmac_oneshot.3619207639 |
| Short name | T983 |
| Test name | |
| Test status | |
| Simulation time | 2774192502 ps |
| CPU time | 369.51 seconds |
| Started | Jun 28 08:22:30 PM PDT 24 |
| Finished | Jun 28 08:28:42 PM PDT 24 |
| Peak memory | 607240 kb |
| Host | smart-cebcde06-97de-46b2-9fee-aee3d483f2a5 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=hmac_functest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3619207639 -assert nopostproc +UVM_TESTNAME=chip _base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_hmac_oneshot.3619207639 |
| Directory | /workspace/2.chip_sw_hmac_oneshot/latest |
| Test location | /workspace/coverage/default/2.chip_sw_hmac_smoketest.3408695146 |
| Short name | T1234 |
| Test name | |
| Test status | |
| Simulation time | 3471835284 ps |
| CPU time | 385.19 seconds |
| Started | Jun 28 08:23:22 PM PDT 24 |
| Finished | Jun 28 08:29:52 PM PDT 24 |
| Peak memory | 607136 kb |
| Host | smart-b489cab2-fe62-4ff1-a0f5-7f50cc6126db |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=hmac_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3408695146 -assert nopostproc +UVM_TESTNAME=chi p_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul l -cm_name 2.chip_sw_hmac_smoketest.3408695146 |
| Directory | /workspace/2.chip_sw_hmac_smoketest/latest |
| Test location | /workspace/coverage/default/2.chip_sw_i2c_device_tx_rx.306905686 |
| Short name | T332 |
| Test name | |
| Test status | |
| Simulation time | 3836077860 ps |
| CPU time | 611.02 seconds |
| Started | Jun 28 08:15:12 PM PDT 24 |
| Finished | Jun 28 08:25:24 PM PDT 24 |
| Peak memory | 609368 kb |
| Host | smart-49fc0ee4-7b8d-4a98-996d-234573d4292d |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=i2c_device_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=306905686 -assert nopostproc +UVM_TESTNA ME=chip_base_test +UVM_TEST_SEQ=chip_sw_i2c_device_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd b -cm_log /dev/null -cm_name 2.chip_sw_i2c_device_tx_rx.306905686 |
| Directory | /workspace/2.chip_sw_i2c_device_tx_rx/latest |
| Test location | /workspace/coverage/default/2.chip_sw_i2c_host_tx_rx.4305167 |
| Short name | T206 |
| Test name | |
| Test status | |
| Simulation time | 5020872740 ps |
| CPU time | 896.13 seconds |
| Started | Jun 28 08:15:17 PM PDT 24 |
| Finished | Jun 28 08:30:14 PM PDT 24 |
| Peak memory | 608276 kb |
| Host | smart-0e966c98-4765-41e9-adb0-1665bc2e5677 |
| User | root |
| Command | /workspace/default/simv +i2c_idx=0 +sw_build_device=sim_dv +sw_images=i2c_host_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4305167 -assert nopostproc +UVM _TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_i2c_host_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau lt.vdb -cm_log /dev/null -cm_name 2.chip_sw_i2c_host_tx_rx.4305167 |
| Directory | /workspace/2.chip_sw_i2c_host_tx_rx/latest |
| Test location | /workspace/coverage/default/2.chip_sw_i2c_host_tx_rx_idx1.1322714264 |
| Short name | T326 |
| Test name | |
| Test status | |
| Simulation time | 5137943068 ps |
| CPU time | 1125.47 seconds |
| Started | Jun 28 08:16:01 PM PDT 24 |
| Finished | Jun 28 08:34:50 PM PDT 24 |
| Peak memory | 608284 kb |
| Host | smart-df13d301-f6ce-49b3-8991-89526c9715d4 |
| User | root |
| Command | /workspace/default/simv +i2c_idx=1 +sw_build_device=sim_dv +sw_images=i2c_host_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1322714264 -assert nopostproc + UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_i2c_host_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de fault.vdb -cm_log /dev/null -cm_name 2.chip_sw_i2c_host_tx_rx_idx1.1322714264 |
| Directory | /workspace/2.chip_sw_i2c_host_tx_rx_idx1/latest |
| Test location | /workspace/coverage/default/2.chip_sw_i2c_host_tx_rx_idx2.2595049798 |
| Short name | T328 |
| Test name | |
| Test status | |
| Simulation time | 5391875476 ps |
| CPU time | 955.66 seconds |
| Started | Jun 28 08:15:58 PM PDT 24 |
| Finished | Jun 28 08:31:58 PM PDT 24 |
| Peak memory | 608256 kb |
| Host | smart-64e0604b-eb4a-41e5-99c0-d8a60eeb6873 |
| User | root |
| Command | /workspace/default/simv +i2c_idx=2 +sw_build_device=sim_dv +sw_images=i2c_host_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2595049798 -assert nopostproc + UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_i2c_host_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de fault.vdb -cm_log /dev/null -cm_name 2.chip_sw_i2c_host_tx_rx_idx2.2595049798 |
| Directory | /workspace/2.chip_sw_i2c_host_tx_rx_idx2/latest |
| Test location | /workspace/coverage/default/2.chip_sw_inject_scramble_seed.2893264023 |
| Short name | T198 |
| Test name | |
| Test status | |
| Simulation time | 64564722095 ps |
| CPU time | 12199.8 seconds |
| Started | Jun 28 08:16:57 PM PDT 24 |
| Finished | Jun 28 11:40:24 PM PDT 24 |
| Peak memory | 624164 kb |
| Host | smart-c5cae779-1b65-4a03-a6ac-15fdf7c47243 |
| User | root |
| Command | /workspace/default/simv +lc_at_prod=1 +flash_program_latency=5 +sw_test_timeout_ns=150_000_000 +sw_build_device=sim_dv +sw_images=inject_scramble_seed :1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=2893264023 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_inject_scramble_seed_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_inject_scramble_seed.2893264023 |
| Directory | /workspace/2.chip_sw_inject_scramble_seed/latest |
| Test location | /workspace/coverage/default/2.chip_sw_keymgr_key_derivation.1101826686 |
| Short name | T218 |
| Test name | |
| Test status | |
| Simulation time | 12753306680 ps |
| CPU time | 2511.83 seconds |
| Started | Jun 28 08:20:43 PM PDT 24 |
| Finished | Jun 28 09:02:38 PM PDT 24 |
| Peak memory | 614376 kb |
| Host | smart-c12962f9-d03a-45ff-9acc-5eedb99fcd1c |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=20_000_000 +sw_build_device=sim_dv +sw_images=keymgr_key_derivation_test:1:new_rules,test_rom:0 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1101 826686 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_keymgr_key_derivation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_keymgr_key_derivation.1101826686 |
| Directory | /workspace/2.chip_sw_keymgr_key_derivation/latest |
| Test location | /workspace/coverage/default/2.chip_sw_keymgr_key_derivation_jitter_en.3527759047 |
| Short name | T1092 |
| Test name | |
| Test status | |
| Simulation time | 12792791100 ps |
| CPU time | 2202.77 seconds |
| Started | Jun 28 08:21:53 PM PDT 24 |
| Finished | Jun 28 08:58:37 PM PDT 24 |
| Peak memory | 615572 kb |
| Host | smart-ffe6726b-51de-49ed-87da-b020e77c7c92 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=20_000_000 +en_jitter=1 +sw_build_device=sim_dv +sw_images=keymgr_key_derivation_test:1:new_rules,test_rom :0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=3527759047 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_keymgr_key_derivation_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_keymgr_key_derivation_jitter_en.3527759047 |
| Directory | /workspace/2.chip_sw_keymgr_key_derivation_jitter_en/latest |
| Test location | /workspace/coverage/default/2.chip_sw_keymgr_key_derivation_jitter_en_reduced_freq.1940971253 |
| Short name | T90 |
| Test name | |
| Test status | |
| Simulation time | 9849403270 ps |
| CPU time | 1666.17 seconds |
| Started | Jun 28 08:22:38 PM PDT 24 |
| Finished | Jun 28 08:50:26 PM PDT 24 |
| Peak memory | 615604 kb |
| Host | smart-4238df21-bc4d-4a20-86c8-9e8ec5a8eec4 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=20_000_000 +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=keymgr_key_derivation_test :1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=1940971253 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_keymgr_key_derivation_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_keymgr_key_derivation_jitter_en _reduced_freq.1940971253 |
| Directory | /workspace/2.chip_sw_keymgr_key_derivation_jitter_en_reduced_freq/latest |
| Test location | /workspace/coverage/default/2.chip_sw_keymgr_key_derivation_prod.2933872264 |
| Short name | T1066 |
| Test name | |
| Test status | |
| Simulation time | 12305755080 ps |
| CPU time | 2360.37 seconds |
| Started | Jun 28 08:19:39 PM PDT 24 |
| Finished | Jun 28 08:59:03 PM PDT 24 |
| Peak memory | 615680 kb |
| Host | smart-92cf0dd3-20f2-4a7e-9df4-885879d97818 |
| User | root |
| Command | /workspace/default/simv +lc_at_prod=1 +sw_test_timeout_ns=20_000_000 +sw_build_device=sim_dv +sw_images=keymgr_key_derivation_test:1:new_rules,test_ro m:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=2933872264 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_keymgr_key_derivation_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_keymgr_key_derivation_prod.2933872264 |
| Directory | /workspace/2.chip_sw_keymgr_key_derivation_prod/latest |
| Test location | /workspace/coverage/default/2.chip_sw_keymgr_sideload_aes.2005645443 |
| Short name | T215 |
| Test name | |
| Test status | |
| Simulation time | 13732426828 ps |
| CPU time | 2708.09 seconds |
| Started | Jun 28 08:22:53 PM PDT 24 |
| Finished | Jun 28 09:08:07 PM PDT 24 |
| Peak memory | 609352 kb |
| Host | smart-28ec23eb-970d-454e-bbe6-815b040a8204 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=20_000_000 +sw_build_device=sim_dv +sw_images=keymgr_sideload_aes_test:1:new_rules,test_rom:0 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=200564 5443 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_keymgr_sideload_aes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_keymgr_sideload_aes.2005645443 |
| Directory | /workspace/2.chip_sw_keymgr_sideload_aes/latest |
| Test location | /workspace/coverage/default/2.chip_sw_keymgr_sideload_kmac.2656425352 |
| Short name | T960 |
| Test name | |
| Test status | |
| Simulation time | 9856744996 ps |
| CPU time | 2408.24 seconds |
| Started | Jun 28 08:19:25 PM PDT 24 |
| Finished | Jun 28 08:59:35 PM PDT 24 |
| Peak memory | 609252 kb |
| Host | smart-e7e17443-906f-43fb-ab2e-5905dc937ce1 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=20_000_000 +sw_build_device=sim_dv +sw_images=keymgr_sideload_kmac_test:1:new_rules,test_rom:0 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26564 25352 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_keymgr_sideload_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_keymgr_sideload_kmac.2656425352 |
| Directory | /workspace/2.chip_sw_keymgr_sideload_kmac/latest |
| Test location | /workspace/coverage/default/2.chip_sw_keymgr_sideload_otbn.2694216550 |
| Short name | T222 |
| Test name | |
| Test status | |
| Simulation time | 15281705856 ps |
| CPU time | 4240.37 seconds |
| Started | Jun 28 08:21:09 PM PDT 24 |
| Finished | Jun 28 09:31:57 PM PDT 24 |
| Peak memory | 609284 kb |
| Host | smart-333eb0c7-31c3-40cf-9241-12b220d4ab58 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=20_000_000 +sw_build_device=sim_dv +sw_images=keymgr_sideload_otbn_test:1:new_rules,test_rom:0 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26942 16550 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_keymgr_sideload_otbn.2694216550 |
| Directory | /workspace/2.chip_sw_keymgr_sideload_otbn/latest |
| Test location | /workspace/coverage/default/2.chip_sw_kmac_app_rom.2554271190 |
| Short name | T407 |
| Test name | |
| Test status | |
| Simulation time | 2192444176 ps |
| CPU time | 170.31 seconds |
| Started | Jun 28 08:20:17 PM PDT 24 |
| Finished | Jun 28 08:23:08 PM PDT 24 |
| Peak memory | 607128 kb |
| Host | smart-1fd9368c-7f4c-4cb6-8b59-90f9b82949bb |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=kmac_app_rom_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2554271190 -assert nopostproc +UVM_TESTNAME= chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/ null -cm_name 2.chip_sw_kmac_app_rom.2554271190 |
| Directory | /workspace/2.chip_sw_kmac_app_rom/latest |
| Test location | /workspace/coverage/default/2.chip_sw_kmac_entropy.3814545633 |
| Short name | T431 |
| Test name | |
| Test status | |
| Simulation time | 2976952830 ps |
| CPU time | 257.05 seconds |
| Started | Jun 28 08:17:35 PM PDT 24 |
| Finished | Jun 28 08:21:55 PM PDT 24 |
| Peak memory | 607128 kb |
| Host | smart-80018e69-8c21-489e-9d5b-4db70be2ad63 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=kmac_entropy_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3814545633 -assert nopostproc +UVM_TESTNAME= chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/ null -cm_name 2.chip_sw_kmac_entropy.3814545633 |
| Directory | /workspace/2.chip_sw_kmac_entropy/latest |
| Test location | /workspace/coverage/default/2.chip_sw_kmac_idle.702175548 |
| Short name | T945 |
| Test name | |
| Test status | |
| Simulation time | 2488375622 ps |
| CPU time | 253.6 seconds |
| Started | Jun 28 08:26:16 PM PDT 24 |
| Finished | Jun 28 08:30:40 PM PDT 24 |
| Peak memory | 607124 kb |
| Host | smart-3d1e3c11-1e84-44c5-9c7a-6b61c16f8358 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=kmac_idle_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=702175548 -assert nopostproc +UVM_TESTNAME=chip _base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_kmac_idle.702175548 |
| Directory | /workspace/2.chip_sw_kmac_idle/latest |
| Test location | /workspace/coverage/default/2.chip_sw_kmac_mode_cshake.1111384742 |
| Short name | T412 |
| Test name | |
| Test status | |
| Simulation time | 2403496862 ps |
| CPU time | 333.6 seconds |
| Started | Jun 28 08:19:09 PM PDT 24 |
| Finished | Jun 28 08:24:44 PM PDT 24 |
| Peak memory | 607280 kb |
| Host | smart-8e407e1e-5d71-4d14-9b32-36cb13873203 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=kmac_mode_cshake_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1111384742 -assert nopostproc +UVM_TESTN AME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log / dev/null -cm_name 2.chip_sw_kmac_mode_cshake.1111384742 |
| Directory | /workspace/2.chip_sw_kmac_mode_cshake/latest |
| Test location | /workspace/coverage/default/2.chip_sw_kmac_mode_kmac.3031753807 |
| Short name | T1274 |
| Test name | |
| Test status | |
| Simulation time | 2815578392 ps |
| CPU time | 228.97 seconds |
| Started | Jun 28 08:20:09 PM PDT 24 |
| Finished | Jun 28 08:23:59 PM PDT 24 |
| Peak memory | 607240 kb |
| Host | smart-7c1c5602-c0e8-40be-b48a-60efe8cec6e8 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=kmac_mode_kmac_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3031753807 -assert nopostproc +UVM_TESTNAM E=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 2.chip_sw_kmac_mode_kmac.3031753807 |
| Directory | /workspace/2.chip_sw_kmac_mode_kmac/latest |
| Test location | /workspace/coverage/default/2.chip_sw_kmac_mode_kmac_jitter_en.1973884533 |
| Short name | T1048 |
| Test name | |
| Test status | |
| Simulation time | 2912661259 ps |
| CPU time | 343.35 seconds |
| Started | Jun 28 08:22:34 PM PDT 24 |
| Finished | Jun 28 08:28:18 PM PDT 24 |
| Peak memory | 609092 kb |
| Host | smart-6bb68881-c654-441d-9eea-6ea9db9eb5ce |
| User | root |
| Command | /workspace/default/simv +en_jitter=1 +sw_build_device=sim_dv +sw_images=kmac_mode_kmac_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1973884533 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd b -cm_log /dev/null -cm_name 2.chip_sw_kmac_mode_kmac_jitter_en.1973884533 |
| Directory | /workspace/2.chip_sw_kmac_mode_kmac_jitter_en/latest |
| Test location | /workspace/coverage/default/2.chip_sw_kmac_mode_kmac_jitter_en_reduced_freq.1045062605 |
| Short name | T1009 |
| Test name | |
| Test status | |
| Simulation time | 3079707509 ps |
| CPU time | 290.8 seconds |
| Started | Jun 28 08:23:01 PM PDT 24 |
| Finished | Jun 28 08:27:56 PM PDT 24 |
| Peak memory | 609180 kb |
| Host | smart-f7817ace-6eaf-4185-8e72-847115908302 |
| User | root |
| Command | /workspace/default/simv +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=kmac_mode_kmac_test:1:new_rules,test_rom:0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10450626 05 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac e/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_kmac_mode_kmac_jitter_en_reduced_freq.1045062605 |
| Directory | /workspace/2.chip_sw_kmac_mode_kmac_jitter_en_reduced_freq/latest |
| Test location | /workspace/coverage/default/2.chip_sw_kmac_smoketest.1739262320 |
| Short name | T105 |
| Test name | |
| Test status | |
| Simulation time | 2669065500 ps |
| CPU time | 243.99 seconds |
| Started | Jun 28 08:23:30 PM PDT 24 |
| Finished | Jun 28 08:27:35 PM PDT 24 |
| Peak memory | 607124 kb |
| Host | smart-0b57457c-94ae-4356-8c60-c8ed3a3b2507 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=kmac_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1739262320 -assert nopostproc +UVM_TESTNAME=chi p_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul l -cm_name 2.chip_sw_kmac_smoketest.1739262320 |
| Directory | /workspace/2.chip_sw_kmac_smoketest/latest |
| Test location | /workspace/coverage/default/2.chip_sw_lc_ctrl_otp_hw_cfg0.689214050 |
| Short name | T1079 |
| Test name | |
| Test status | |
| Simulation time | 2766812168 ps |
| CPU time | 384.57 seconds |
| Started | Jun 28 08:17:00 PM PDT 24 |
| Finished | Jun 28 08:23:29 PM PDT 24 |
| Peak memory | 609192 kb |
| Host | smart-053932be-cc88-4c85-9047-b1a82678daff |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=lc_ctrl_otp_hw_cfg0_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=689214050 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_lc_ctrl_otp_hw_cfg0.689214050 |
| Directory | /workspace/2.chip_sw_lc_ctrl_otp_hw_cfg0/latest |
| Test location | /workspace/coverage/default/2.chip_sw_lc_ctrl_program_error.1559447736 |
| Short name | T165 |
| Test name | |
| Test status | |
| Simulation time | 4691168240 ps |
| CPU time | 467.53 seconds |
| Started | Jun 28 08:27:15 PM PDT 24 |
| Finished | Jun 28 08:35:04 PM PDT 24 |
| Peak memory | 608500 kb |
| Host | smart-8334c2af-0624-47c7-aebc-8fcd25c62f64 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=lc_ctrl_program_error:1:new_rules,test_rom:0 + cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_ seed=1559447736 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_program_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_lc_ctrl_program_error.1559447736 |
| Directory | /workspace/2.chip_sw_lc_ctrl_program_error/latest |
| Test location | /workspace/coverage/default/2.chip_sw_lc_ctrl_rand_to_scrap.4040966718 |
| Short name | T644 |
| Test name | |
| Test status | |
| Simulation time | 3461864652 ps |
| CPU time | 158.58 seconds |
| Started | Jun 28 08:16:58 PM PDT 24 |
| Finished | Jun 28 08:19:40 PM PDT 24 |
| Peak memory | 617588 kb |
| Host | smart-6d3230ba-1840-4424-9a5a-9a291f786297 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=lc_ctrl_scrap_test:1:new_rules,test_rom:0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40409667 18 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_scrap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_lc_ctrl_rand_to_scrap.4040966718 |
| Directory | /workspace/2.chip_sw_lc_ctrl_rand_to_scrap/latest |
| Test location | /workspace/coverage/default/2.chip_sw_lc_ctrl_transition.3844750829 |
| Short name | T1265 |
| Test name | |
| Test status | |
| Simulation time | 11246029548 ps |
| CPU time | 1196.5 seconds |
| Started | Jun 28 08:16:51 PM PDT 24 |
| Finished | Jun 28 08:36:49 PM PDT 24 |
| Peak memory | 622200 kb |
| Host | smart-adf61b38-ff2b-4238-a89d-5dcb59a6e8c6 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=lc_ctrl_transition_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3844750829 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_transition_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau lt.vdb -cm_log /dev/null -cm_name 2.chip_sw_lc_ctrl_transition.3844750829 |
| Directory | /workspace/2.chip_sw_lc_ctrl_transition/latest |
| Test location | /workspace/coverage/default/2.chip_sw_lc_ctrl_volatile_raw_unlock.1335372959 |
| Short name | T1112 |
| Test name | |
| Test status | |
| Simulation time | 2802136865 ps |
| CPU time | 129.54 seconds |
| Started | Jun 28 08:16:35 PM PDT 24 |
| Finished | Jun 28 08:18:46 PM PDT 24 |
| Peak memory | 615960 kb |
| Host | smart-3659390b-039c-4e57-bd6b-b7b48d903361 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStRaw +exp_volatile_raw_unlock_en=0 +sw_build_device=sim_dv +sw_images=lc_ctrl_volatile_raw_unlock_tes t:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/ tools/sim.tcl +ntb_random_seed=1335372959 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_volatile_raw_unlock_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_lc_ctrl_volatile_raw_unlock.1335372959 |
| Directory | /workspace/2.chip_sw_lc_ctrl_volatile_raw_unlock/latest |
| Test location | /workspace/coverage/default/2.chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz.901792875 |
| Short name | T158 |
| Test name | |
| Test status | |
| Simulation time | 2392420040 ps |
| CPU time | 109.06 seconds |
| Started | Jun 28 08:17:53 PM PDT 24 |
| Finished | Jun 28 08:19:44 PM PDT 24 |
| Peak memory | 614436 kb |
| Host | smart-84e00d22-ec8f-40ca-ae43-1004e609d2af |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStRaw +chip_clock_source=ChipClockSourceExternal48Mhz +exp_volatile_raw_unlock_en=0 +sw_build_device=s im_dv +sw_images=lc_ctrl_volatile_raw_unlock_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=901792875 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST _SEQ=chip_sw_lc_volatile_raw_unlock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 2.chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz.901792875 |
| Directory | /workspace/2.chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz/latest |
| Test location | /workspace/coverage/default/2.chip_sw_lc_walkthrough_dev.1657478650 |
| Short name | T225 |
| Test name | |
| Test status | |
| Simulation time | 49820556912 ps |
| CPU time | 5862 seconds |
| Started | Jun 28 08:17:18 PM PDT 24 |
| Finished | Jun 28 09:55:02 PM PDT 24 |
| Peak memory | 617344 kb |
| Host | smart-955be1d6-c094-492e-abff-97227d4801e2 |
| User | root |
| Command | /workspace/default/simv +flash_program_latency=5 +use_otp_image=OtpTypeLcStRaw +dest_dec_state=DecLcStDev +sw_test_timeout_ns=200_000_000 +sw_build_de vice=sim_dv +sw_images=lc_walkthrough_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1657478650 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=c hip_sw_lc_walkthrough_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip _sw_lc_walkthrough_dev.1657478650 |
| Directory | /workspace/2.chip_sw_lc_walkthrough_dev/latest |
| Test location | /workspace/coverage/default/2.chip_sw_lc_walkthrough_prod.362154746 |
| Short name | T1277 |
| Test name | |
| Test status | |
| Simulation time | 50063856664 ps |
| CPU time | 5629.47 seconds |
| Started | Jun 28 08:16:39 PM PDT 24 |
| Finished | Jun 28 09:50:32 PM PDT 24 |
| Peak memory | 616340 kb |
| Host | smart-7b994122-26e9-4836-aaa8-7e9184fa14a2 |
| User | root |
| Command | /workspace/default/simv +flash_program_latency=5 +use_otp_image=OtpTypeLcStRaw +dest_dec_state=DecLcStProd +sw_test_timeout_ns=200_000_000 +sw_build_d evice=sim_dv +sw_images=lc_walkthrough_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=362154746 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=c hip_sw_lc_walkthrough_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip _sw_lc_walkthrough_prod.362154746 |
| Directory | /workspace/2.chip_sw_lc_walkthrough_prod/latest |
| Test location | /workspace/coverage/default/2.chip_sw_lc_walkthrough_rma.4240400539 |
| Short name | T231 |
| Test name | |
| Test status | |
| Simulation time | 49013041450 ps |
| CPU time | 5428.21 seconds |
| Started | Jun 28 08:16:37 PM PDT 24 |
| Finished | Jun 28 09:47:06 PM PDT 24 |
| Peak memory | 623724 kb |
| Host | smart-78015205-76d0-47c4-b431-043eb176b41b |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStRaw +dest_dec_state=DecLcStRma +flash_program_latency=5 +sw_test_timeout_ns=200_000_000 +sw_build_de vice=sim_dv +sw_images=lc_walkthrough_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4240400539 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=c hip_sw_lc_walkthrough_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip _sw_lc_walkthrough_rma.4240400539 |
| Directory | /workspace/2.chip_sw_lc_walkthrough_rma/latest |
| Test location | /workspace/coverage/default/2.chip_sw_lc_walkthrough_testunlocks.3882675309 |
| Short name | T954 |
| Test name | |
| Test status | |
| Simulation time | 22303630646 ps |
| CPU time | 1839.2 seconds |
| Started | Jun 28 08:17:10 PM PDT 24 |
| Finished | Jun 28 08:47:53 PM PDT 24 |
| Peak memory | 617744 kb |
| Host | smart-55236e5e-7ac3-444e-99ce-a15b7842b47a |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStRaw +dest_dec_state=DecLcStTestUnlock7 +sw_build_device=sim_dv +sw_images=lc_walkthrough_testunlocks _test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=3882675309 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_walkthrough_testunlocks_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_lc_walkthrough_testun locks.3882675309 |
| Directory | /workspace/2.chip_sw_lc_walkthrough_testunlocks/latest |
| Test location | /workspace/coverage/default/2.chip_sw_otbn_ecdsa_op_irq.909602465 |
| Short name | T1243 |
| Test name | |
| Test status | |
| Simulation time | 17127594998 ps |
| CPU time | 3735.36 seconds |
| Started | Jun 28 08:19:15 PM PDT 24 |
| Finished | Jun 28 09:21:32 PM PDT 24 |
| Peak memory | 609284 kb |
| Host | smart-60ad689c-23f6-4ac4-98f8-b2ad03932b11 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=28_000_000 +rng_srate_value=30 +sw_build_device=sim_dv +sw_images=otbn_ecdsa_op_irq_test:1:new_rules,test_ rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ random_seed=909602465 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_otbn_ecdsa_op_irq.909602465 |
| Directory | /workspace/2.chip_sw_otbn_ecdsa_op_irq/latest |
| Test location | /workspace/coverage/default/2.chip_sw_otbn_ecdsa_op_irq_jitter_en.3673713277 |
| Short name | T1100 |
| Test name | |
| Test status | |
| Simulation time | 19122959313 ps |
| CPU time | 3552.11 seconds |
| Started | Jun 28 08:17:41 PM PDT 24 |
| Finished | Jun 28 09:16:56 PM PDT 24 |
| Peak memory | 609332 kb |
| Host | smart-7b339c26-0c03-459f-94aa-2e11f34da700 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=33_000_000 +rng_srate_value=30 +en_jitter=1 +sw_build_device=sim_dv +sw_images=otbn_ecdsa_op_irq_test:1:ne w_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/ sim.tcl +ntb_random_seed=3673713277 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tg l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_otbn_ecdsa_op_irq_jitter_en.3673713277 |
| Directory | /workspace/2.chip_sw_otbn_ecdsa_op_irq_jitter_en/latest |
| Test location | /workspace/coverage/default/2.chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq.1406368996 |
| Short name | T1247 |
| Test name | |
| Test status | |
| Simulation time | 24461670818 ps |
| CPU time | 4255.58 seconds |
| Started | Jun 28 08:21:26 PM PDT 24 |
| Finished | Jun 28 09:32:24 PM PDT 24 |
| Peak memory | 609316 kb |
| Host | smart-8d4db8af-223e-4725-b370-dd13f7224d88 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=33_000_000 +rng_srate_value=30 +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=otbn_e cdsa_op_irq_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/ repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1406368996 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_otbn_ecdsa_op_irq_jitter_en_redu ced_freq.1406368996 |
| Directory | /workspace/2.chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq/latest |
| Test location | /workspace/coverage/default/2.chip_sw_otbn_mem_scramble.1039085738 |
| Short name | T275 |
| Test name | |
| Test status | |
| Simulation time | 3759721180 ps |
| CPU time | 591.87 seconds |
| Started | Jun 28 08:18:42 PM PDT 24 |
| Finished | Jun 28 08:28:35 PM PDT 24 |
| Peak memory | 609152 kb |
| Host | smart-3e8b55b0-726c-45e3-926b-12daa9e1ada0 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=15_000_000 +en_scb_tl_err_chk=0 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=otbn _mem_scramble_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1039085738 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_otbn_mem_scramble.1039085738 |
| Directory | /workspace/2.chip_sw_otbn_mem_scramble/latest |
| Test location | /workspace/coverage/default/2.chip_sw_otbn_randomness.3768237166 |
| Short name | T318 |
| Test name | |
| Test status | |
| Simulation time | 6031036564 ps |
| CPU time | 888.32 seconds |
| Started | Jun 28 08:17:31 PM PDT 24 |
| Finished | Jun 28 08:32:21 PM PDT 24 |
| Peak memory | 608180 kb |
| Host | smart-bf1d54dc-f9f6-4eaf-8c1d-0c60658c1a73 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +rng_srate_value=30 +sw_build_device=sim_dv +sw_images=otbn_randomness_test:1:new_rules,test_ro m:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=3768237166 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_otbn_randomness.3768237166 |
| Directory | /workspace/2.chip_sw_otbn_randomness/latest |
| Test location | /workspace/coverage/default/2.chip_sw_otbn_smoketest.2525348042 |
| Short name | T101 |
| Test name | |
| Test status | |
| Simulation time | 7805984092 ps |
| CPU time | 1412.59 seconds |
| Started | Jun 28 08:23:06 PM PDT 24 |
| Finished | Jun 28 08:46:46 PM PDT 24 |
| Peak memory | 607264 kb |
| Host | smart-a2423641-b840-4229-81c8-e72f4324a225 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=otbn_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2525348042 -assert nopostproc +UVM_TESTNAME=chi p_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul l -cm_name 2.chip_sw_otbn_smoketest.2525348042 |
| Directory | /workspace/2.chip_sw_otbn_smoketest/latest |
| Test location | /workspace/coverage/default/2.chip_sw_otp_ctrl_ecc_error_vendor_test.1262358779 |
| Short name | T933 |
| Test name | |
| Test status | |
| Simulation time | 3138517504 ps |
| CPU time | 262.8 seconds |
| Started | Jun 28 08:17:01 PM PDT 24 |
| Finished | Jun 28 08:21:28 PM PDT 24 |
| Peak memory | 609148 kb |
| Host | smart-cd8392c7-604c-460e-b881-a2fdaeac03f2 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=otp_ctrl_vendor_test_ecc_error_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1262358779 -assert nopostp roc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_otp_ctrl_vendor_test_ecc_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_otp_ctrl_ecc_error_vendor_test.1262358779 |
| Directory | /workspace/2.chip_sw_otp_ctrl_ecc_error_vendor_test/latest |
| Test location | /workspace/coverage/default/2.chip_sw_otp_ctrl_lc_signals_dev.3423896417 |
| Short name | T1120 |
| Test name | |
| Test status | |
| Simulation time | 9162928422 ps |
| CPU time | 1366.67 seconds |
| Started | Jun 28 08:15:39 PM PDT 24 |
| Finished | Jun 28 08:38:26 PM PDT 24 |
| Peak memory | 608216 kb |
| Host | smart-952b0b34-aaf5-4a48-a340-f7f351fc1333 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStDev +otp_clear_secret2=1 +sw_build_device=sim_dv +sw_images=otp_ctrl_lc_signals_test:1:new_rules,tes t_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +nt b_random_seed=3423896417 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_otp_ctrl_lc_signals_dev.3423896417 |
| Directory | /workspace/2.chip_sw_otp_ctrl_lc_signals_dev/latest |
| Test location | /workspace/coverage/default/2.chip_sw_otp_ctrl_lc_signals_prod.3285235432 |
| Short name | T211 |
| Test name | |
| Test status | |
| Simulation time | 8010360144 ps |
| CPU time | 1300.35 seconds |
| Started | Jun 28 08:18:24 PM PDT 24 |
| Finished | Jun 28 08:40:13 PM PDT 24 |
| Peak memory | 609296 kb |
| Host | smart-dfbcc44e-eb43-4b88-af05-82acb8f1e365 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStProd +otp_clear_secret2=1 +sw_build_device=sim_dv +sw_images=otp_ctrl_lc_signals_test:1:new_rules,te st_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n tb_random_seed=3285235432 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_otp_ctrl_lc_signals_prod.3285235432 |
| Directory | /workspace/2.chip_sw_otp_ctrl_lc_signals_prod/latest |
| Test location | /workspace/coverage/default/2.chip_sw_otp_ctrl_lc_signals_rma.4172787337 |
| Short name | T213 |
| Test name | |
| Test status | |
| Simulation time | 8018963772 ps |
| CPU time | 1382.17 seconds |
| Started | Jun 28 08:20:57 PM PDT 24 |
| Finished | Jun 28 08:44:11 PM PDT 24 |
| Peak memory | 609188 kb |
| Host | smart-8a6e89af-a49e-4d61-a162-c4150feeb9e9 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStRma +otp_clear_secret2=1 +sw_build_device=sim_dv +sw_images=otp_ctrl_lc_signals_test:1:new_rules,tes t_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +nt b_random_seed=4172787337 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_otp_ctrl_lc_signals_rma.4172787337 |
| Directory | /workspace/2.chip_sw_otp_ctrl_lc_signals_rma/latest |
| Test location | /workspace/coverage/default/2.chip_sw_otp_ctrl_lc_signals_test_unlocked0.1394424577 |
| Short name | T1004 |
| Test name | |
| Test status | |
| Simulation time | 4314694096 ps |
| CPU time | 739.28 seconds |
| Started | Jun 28 08:16:56 PM PDT 24 |
| Finished | Jun 28 08:29:19 PM PDT 24 |
| Peak memory | 609196 kb |
| Host | smart-7000db54-57c9-40af-8b14-00ae03c449c4 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStTestUnlocked0 +otp_clear_secret2=1 +sw_build_device=sim_dv +sw_images=otp_ctrl_lc_signals_test:1:new _rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/s im.tcl +ntb_random_seed=1394424577 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_otp_ctrl_lc_signals_test_unlocked0.1394424577 |
| Directory | /workspace/2.chip_sw_otp_ctrl_lc_signals_test_unlocked0/latest |
| Test location | /workspace/coverage/default/2.chip_sw_otp_ctrl_smoketest.1787282273 |
| Short name | T392 |
| Test name | |
| Test status | |
| Simulation time | 2912997540 ps |
| CPU time | 332.72 seconds |
| Started | Jun 28 08:23:10 PM PDT 24 |
| Finished | Jun 28 08:28:52 PM PDT 24 |
| Peak memory | 609184 kb |
| Host | smart-7f586684-0c5b-48ac-9159-a1feca103fe3 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=otp_ctrl_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1787282273 -assert nopostproc +UVM_TESTNAME =chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 2.chip_sw_otp_ctrl_smoketest.1787282273 |
| Directory | /workspace/2.chip_sw_otp_ctrl_smoketest/latest |
| Test location | /workspace/coverage/default/2.chip_sw_plic_sw_irq.3940603942 |
| Short name | T1192 |
| Test name | |
| Test status | |
| Simulation time | 3525415600 ps |
| CPU time | 335.36 seconds |
| Started | Jun 28 08:20:13 PM PDT 24 |
| Finished | Jun 28 08:25:49 PM PDT 24 |
| Peak memory | 607300 kb |
| Host | smart-f9f71482-cce4-42f3-a7d7-d5bc622dc096 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=plic_sw_irq_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3940603942 -assert nopostproc +UVM_TESTNAME=c hip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n ull -cm_name 2.chip_sw_plic_sw_irq.3940603942 |
| Directory | /workspace/2.chip_sw_plic_sw_irq/latest |
| Test location | /workspace/coverage/default/2.chip_sw_power_idle_load.3647591953 |
| Short name | T668 |
| Test name | |
| Test status | |
| Simulation time | 4783797128 ps |
| CPU time | 724.92 seconds |
| Started | Jun 28 08:23:11 PM PDT 24 |
| Finished | Jun 28 08:35:27 PM PDT 24 |
| Peak memory | 608180 kb |
| Host | smart-79ed241e-bd4a-455b-a13e-2bd34f1e8551 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=chip_power_idle_load:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3647591953 -assert nopostproc +UVM_TESTNA ME=chip_base_test +UVM_TEST_SEQ=chip_sw_power_idle_load_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_power_idle_load.3647591953 |
| Directory | /workspace/2.chip_sw_power_idle_load/latest |
| Test location | /workspace/coverage/default/2.chip_sw_power_sleep_load.4112228126 |
| Short name | T178 |
| Test name | |
| Test status | |
| Simulation time | 4132689280 ps |
| CPU time | 486.23 seconds |
| Started | Jun 28 08:24:49 PM PDT 24 |
| Finished | Jun 28 08:32:58 PM PDT 24 |
| Peak memory | 608084 kb |
| Host | smart-b163ab28-9d84-4973-8b3b-8cd300d1fc51 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=chip_power_sleep_load:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4112228126 -assert nopostproc +UVM_TESTN AME=chip_base_test +UVM_TEST_SEQ=chip_sw_power_sleep_load_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v db -cm_log /dev/null -cm_name 2.chip_sw_power_sleep_load.4112228126 |
| Directory | /workspace/2.chip_sw_power_sleep_load/latest |
| Test location | /workspace/coverage/default/2.chip_sw_pwrmgr_all_reset_reqs.2980896272 |
| Short name | T1294 |
| Test name | |
| Test status | |
| Simulation time | 10675769516 ps |
| CPU time | 1475.44 seconds |
| Started | Jun 28 08:16:46 PM PDT 24 |
| Finished | Jun 28 08:41:22 PM PDT 24 |
| Peak memory | 608952 kb |
| Host | smart-b3851a74-371e-4f4e-8abb-911c0270ca01 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=50_000_000 +sw_build_device=sim_dv +sw_images=pwrmgr_all_reset_reqs_test:1:new_rules,test_rom:0 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2980 896272 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_deep_sleep_all_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_all_reset_reqs.2980896272 |
| Directory | /workspace/2.chip_sw_pwrmgr_all_reset_reqs/latest |
| Test location | /workspace/coverage/default/2.chip_sw_pwrmgr_b2b_sleep_reset_req.3265194111 |
| Short name | T1257 |
| Test name | |
| Test status | |
| Simulation time | 25878315217 ps |
| CPU time | 2283.74 seconds |
| Started | Jun 28 08:26:59 PM PDT 24 |
| Finished | Jun 28 09:05:04 PM PDT 24 |
| Peak memory | 609256 kb |
| Host | smart-afe6f33c-90a9-431a-bc4b-98ab868d772e |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=35_000_000 +sw_build_device=sim_dv +sw_images=pwrmgr_b2b_sleep_reset_test:1:new_rules,test_rom:0 +cdc_inst rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=326 5194111 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_repeat_reset_wkup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_b2b_sleep_reset_req.3265194111 |
| Directory | /workspace/2.chip_sw_pwrmgr_b2b_sleep_reset_req/latest |
| Test location | /workspace/coverage/default/2.chip_sw_pwrmgr_deep_sleep_all_reset_reqs.2888080868 |
| Short name | T1041 |
| Test name | |
| Test status | |
| Simulation time | 12184992880 ps |
| CPU time | 1334.21 seconds |
| Started | Jun 28 08:17:19 PM PDT 24 |
| Finished | Jun 28 08:39:34 PM PDT 24 |
| Peak memory | 609344 kb |
| Host | smart-c8e7b807-41ce-47ed-bf03-8224a6d3dfde |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=50_000_000 +sw_build_device=sim_dv +sw_images=pwrmgr_deep_sleep_all_reset_reqs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=2888080868 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_deep_sleep_all_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_deep_sleep_all_reset_reqs.2888080868 |
| Directory | /workspace/2.chip_sw_pwrmgr_deep_sleep_all_reset_reqs/latest |
| Test location | /workspace/coverage/default/2.chip_sw_pwrmgr_deep_sleep_por_reset.3207805687 |
| Short name | T1189 |
| Test name | |
| Test status | |
| Simulation time | 8860922376 ps |
| CPU time | 780.34 seconds |
| Started | Jun 28 08:17:25 PM PDT 24 |
| Finished | Jun 28 08:30:27 PM PDT 24 |
| Peak memory | 609184 kb |
| Host | smart-2a64bda6-2c4f-46d4-89de-71e9ff6483ed |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_deep_sleep_por_reset_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3207805687 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sleep_por_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage /default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_deep_sleep_por_reset.3207805687 |
| Directory | /workspace/2.chip_sw_pwrmgr_deep_sleep_por_reset/latest |
| Test location | /workspace/coverage/default/2.chip_sw_pwrmgr_deep_sleep_power_glitch_reset.1401042690 |
| Short name | T1287 |
| Test name | |
| Test status | |
| Simulation time | 6300784224 ps |
| CPU time | 522.66 seconds |
| Started | Jun 28 08:17:25 PM PDT 24 |
| Finished | Jun 28 08:26:08 PM PDT 24 |
| Peak memory | 615152 kb |
| Host | smart-89cee3bf-d3f0-47e0-b841-2781d83b2058 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=pwrmgr_deep_sleep_power_glitch_test:1:new_rules,test_rom :0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=1401042690 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_deep_power_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_deep_sleep_power_glitch_reset.1401042690 |
| Directory | /workspace/2.chip_sw_pwrmgr_deep_sleep_power_glitch_reset/latest |
| Test location | /workspace/coverage/default/2.chip_sw_pwrmgr_full_aon_reset.307814516 |
| Short name | T136 |
| Test name | |
| Test status | |
| Simulation time | 8559983762 ps |
| CPU time | 581.07 seconds |
| Started | Jun 28 08:16:30 PM PDT 24 |
| Finished | Jun 28 08:26:12 PM PDT 24 |
| Peak memory | 609192 kb |
| Host | smart-39b65990-3530-4221-b051-783b59d8a08e |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=rstmgr_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=307814516 -assert nopostproc +UVM_TESTNAME=ch ip_base_test +UVM_TEST_SEQ=chip_sw_full_aon_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l og /dev/null -cm_name 2.chip_sw_pwrmgr_full_aon_reset.307814516 |
| Directory | /workspace/2.chip_sw_pwrmgr_full_aon_reset/latest |
| Test location | /workspace/coverage/default/2.chip_sw_pwrmgr_main_power_glitch_reset.611449532 |
| Short name | T991 |
| Test name | |
| Test status | |
| Simulation time | 4797185884 ps |
| CPU time | 407.2 seconds |
| Started | Jun 28 08:17:44 PM PDT 24 |
| Finished | Jun 28 08:24:33 PM PDT 24 |
| Peak memory | 615328 kb |
| Host | smart-fd9bf163-c91e-40dc-94b0-df8fb4433b6d |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=pwrmgr_main_power_glitch_test:1:new_rules,test_rom:0 +cd c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se ed=611449532 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_main_power_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_main_power_glitch_reset.611449532 |
| Directory | /workspace/2.chip_sw_pwrmgr_main_power_glitch_reset/latest |
| Test location | /workspace/coverage/default/2.chip_sw_pwrmgr_normal_sleep_all_reset_reqs.1268997868 |
| Short name | T938 |
| Test name | |
| Test status | |
| Simulation time | 13674414521 ps |
| CPU time | 1721.03 seconds |
| Started | Jun 28 08:17:37 PM PDT 24 |
| Finished | Jun 28 08:46:20 PM PDT 24 |
| Peak memory | 609012 kb |
| Host | smart-3f5028e1-2d70-427d-a4d3-5023a766eaa8 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_normal_sleep_all_reset_reqs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1268997868 -assert nop ostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_deep_sleep_all_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_normal_sleep_all_reset_reqs.1268997868 |
| Directory | /workspace/2.chip_sw_pwrmgr_normal_sleep_all_reset_reqs/latest |
| Test location | /workspace/coverage/default/2.chip_sw_pwrmgr_normal_sleep_all_wake_ups.243499813 |
| Short name | T2 |
| Test name | |
| Test status | |
| Simulation time | 7296817172 ps |
| CPU time | 423.97 seconds |
| Started | Jun 28 08:27:39 PM PDT 24 |
| Finished | Jun 28 08:34:51 PM PDT 24 |
| Peak memory | 608232 kb |
| Host | smart-446e5c79-fec8-4369-843c-b41cddbf5013 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_normal_sleep_all_wake_ups:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=243499813 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_pwrmgr_deep_sleep_all_wake_ups_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work space/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_normal_sleep_all_wake_ups.243499813 |
| Directory | /workspace/2.chip_sw_pwrmgr_normal_sleep_all_wake_ups/latest |
| Test location | /workspace/coverage/default/2.chip_sw_pwrmgr_normal_sleep_por_reset.224169796 |
| Short name | T189 |
| Test name | |
| Test status | |
| Simulation time | 7654807848 ps |
| CPU time | 788.43 seconds |
| Started | Jun 28 08:16:55 PM PDT 24 |
| Finished | Jun 28 08:30:06 PM PDT 24 |
| Peak memory | 609160 kb |
| Host | smart-cdd3ddbd-881d-4fb0-8cc5-ead5629c0c65 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_normal_sleep_por_reset_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=224169796 -assert nopostpro c +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sleep_por_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag e/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_normal_sleep_por_reset.224169796 |
| Directory | /workspace/2.chip_sw_pwrmgr_normal_sleep_por_reset/latest |
| Test location | /workspace/coverage/default/2.chip_sw_pwrmgr_random_sleep_all_reset_reqs.2407355359 |
| Short name | T988 |
| Test name | |
| Test status | |
| Simulation time | 22610310326 ps |
| CPU time | 2068.15 seconds |
| Started | Jun 28 08:17:03 PM PDT 24 |
| Finished | Jun 28 08:51:36 PM PDT 24 |
| Peak memory | 608996 kb |
| Host | smart-5df1c276-f11d-4767-a654-2a79a3755b93 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=50_000_000 +sw_build_device=sim_dv +sw_images=pwrmgr_random_sleep_all_reset_reqs_test:1:new_rules,test_rom :0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=2407355359 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_deep_sleep_all_reset_vseq +en_cov=1 -cm line+cond+fsm+tg l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_random_sleep_all_reset_reqs.2407355359 |
| Directory | /workspace/2.chip_sw_pwrmgr_random_sleep_all_reset_reqs/latest |
| Test location | /workspace/coverage/default/2.chip_sw_pwrmgr_random_sleep_all_wake_ups.106522242 |
| Short name | T91 |
| Test name | |
| Test status | |
| Simulation time | 23745749688 ps |
| CPU time | 1907.06 seconds |
| Started | Jun 28 08:21:59 PM PDT 24 |
| Finished | Jun 28 08:53:48 PM PDT 24 |
| Peak memory | 608720 kb |
| Host | smart-2cb32a4f-6403-41e9-ac27-94ac3102b20e |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +do_random=1 +sw_build_device=sim_dv +sw_images=pwrmgr_random_sleep_all_wake_ups:1:new_rules,te st_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n tb_random_seed=106522242 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_pwrmgr_deep_sleep_all_wake_ups_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_random_sleep_all_wake_ups.106522242 |
| Directory | /workspace/2.chip_sw_pwrmgr_random_sleep_all_wake_ups/latest |
| Test location | /workspace/coverage/default/2.chip_sw_pwrmgr_random_sleep_power_glitch_reset.3405525088 |
| Short name | T252 |
| Test name | |
| Test status | |
| Simulation time | 39575566704 ps |
| CPU time | 3483.03 seconds |
| Started | Jun 28 08:16:26 PM PDT 24 |
| Finished | Jun 28 09:14:31 PM PDT 24 |
| Peak memory | 610080 kb |
| Host | smart-17b4424e-805c-4eb1-9ecf-f6a3a71b5123 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_test_timeout_ns=24_000_000 +sw_build_device=sim_dv +sw_images=pwrmgr_random_sleep_power _glitch_reset_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3405525088 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_random_power_glit ch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_random_s leep_power_glitch_reset.3405525088 |
| Directory | /workspace/2.chip_sw_pwrmgr_random_sleep_power_glitch_reset/latest |
| Test location | /workspace/coverage/default/2.chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up.3417391806 |
| Short name | T364 |
| Test name | |
| Test status | |
| Simulation time | 6461603550 ps |
| CPU time | 442.17 seconds |
| Started | Jun 28 08:21:02 PM PDT 24 |
| Finished | Jun 28 08:28:35 PM PDT 24 |
| Peak memory | 609332 kb |
| Host | smart-df4bbf09-a9e1-4330-b2f1-4219891756a4 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +do_random=1 +sw_build_device=sim_dv +sw_images=pwrmgr_sensor_ctrl_deep_sleep_wake_up:1:new_rul es,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t cl +ntb_random_seed=3417391806 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_sensor_ctrl_deep_s leep_wake_up.3417391806 |
| Directory | /workspace/2.chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up/latest |
| Test location | /workspace/coverage/default/2.chip_sw_pwrmgr_sleep_disabled.2723163318 |
| Short name | T653 |
| Test name | |
| Test status | |
| Simulation time | 2845176876 ps |
| CPU time | 280.4 seconds |
| Started | Jun 28 08:17:27 PM PDT 24 |
| Finished | Jun 28 08:22:08 PM PDT 24 |
| Peak memory | 607332 kb |
| Host | smart-020c8b37-f90c-4523-a337-1f6387717e1b |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_sleep_disabled_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2723163318 -assert nopostproc +UVM_ TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_ log /dev/null -cm_name 2.chip_sw_pwrmgr_sleep_disabled.2723163318 |
| Directory | /workspace/2.chip_sw_pwrmgr_sleep_disabled/latest |
| Test location | /workspace/coverage/default/2.chip_sw_pwrmgr_sleep_power_glitch_reset.4097966955 |
| Short name | T1034 |
| Test name | |
| Test status | |
| Simulation time | 6102505800 ps |
| CPU time | 689.41 seconds |
| Started | Jun 28 08:18:18 PM PDT 24 |
| Finished | Jun 28 08:29:56 PM PDT 24 |
| Peak memory | 615220 kb |
| Host | smart-b5f4d924-e2be-4b19-8043-f9f6fe399044 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=pwrmgr_sleep_power_glitch_test:1:new_rules,test_rom:0 +c dc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_s eed=4097966955 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_main_power_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_sleep_power_glitch_reset.4097966955 |
| Directory | /workspace/2.chip_sw_pwrmgr_sleep_power_glitch_reset/latest |
| Test location | /workspace/coverage/default/2.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup.3686548018 |
| Short name | T122 |
| Test name | |
| Test status | |
| Simulation time | 5584034604 ps |
| CPU time | 520.06 seconds |
| Started | Jun 28 08:20:32 PM PDT 24 |
| Finished | Jun 28 08:29:14 PM PDT 24 |
| Peak memory | 609244 kb |
| Host | smart-baeffb5e-5767-4eac-b27e-f33e599145f5 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=8_000_000 +sw_build_device=sim_dv +sw_images=sensor_ctrl_wakeup_test:1:new_rules,test_rom:0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36865480 18 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac e/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup.3686548018 |
| Directory | /workspace/2.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup/latest |
| Test location | /workspace/coverage/default/2.chip_sw_pwrmgr_sleep_wake_5_bug.3161888960 |
| Short name | T941 |
| Test name | |
| Test status | |
| Simulation time | 5616314970 ps |
| CPU time | 523.69 seconds |
| Started | Jun 28 08:21:44 PM PDT 24 |
| Finished | Jun 28 08:30:28 PM PDT 24 |
| Peak memory | 609244 kb |
| Host | smart-57a6a60b-f6f6-45c1-9ba9-cb168fbf4a7f |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +do_random=1 +sw_build_device=sim_dv +sw_images=pwrmgr_sleep_wake_5_bug_test:1:new_rules,test_r om:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r andom_seed=3161888960 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_sleep_wake_5_bug.3161888960 |
| Directory | /workspace/2.chip_sw_pwrmgr_sleep_wake_5_bug/latest |
| Test location | /workspace/coverage/default/2.chip_sw_pwrmgr_smoketest.1567355369 |
| Short name | T1309 |
| Test name | |
| Test status | |
| Simulation time | 5668392930 ps |
| CPU time | 483.65 seconds |
| Started | Jun 28 08:29:00 PM PDT 24 |
| Finished | Jun 28 08:37:28 PM PDT 24 |
| Peak memory | 609240 kb |
| Host | smart-9e92ccfe-1c13-4562-9f11-4827f69cd527 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=10000000 +sw_build_device=sim_dv +sw_images=pwrmgr_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1567355369 -asse rt nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera ge/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_smoketest.1567355369 |
| Directory | /workspace/2.chip_sw_pwrmgr_smoketest/latest |
| Test location | /workspace/coverage/default/2.chip_sw_pwrmgr_sysrst_ctrl_reset.144465129 |
| Short name | T1241 |
| Test name | |
| Test status | |
| Simulation time | 6913425496 ps |
| CPU time | 886.38 seconds |
| Started | Jun 28 08:17:52 PM PDT 24 |
| Finished | Jun 28 08:32:39 PM PDT 24 |
| Peak memory | 608408 kb |
| Host | smart-3d877ea0-cef9-4bd5-b54f-592670d7e7d3 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_sysrst_ctrl_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=144465129 -assert nopostproc +UVM_TEST NAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb - cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_sysrst_ctrl_reset.144465129 |
| Directory | /workspace/2.chip_sw_pwrmgr_sysrst_ctrl_reset/latest |
| Test location | /workspace/coverage/default/2.chip_sw_pwrmgr_usb_clk_disabled_when_active.1314807643 |
| Short name | T1203 |
| Test name | |
| Test status | |
| Simulation time | 5354525240 ps |
| CPU time | 413.98 seconds |
| Started | Jun 28 08:17:16 PM PDT 24 |
| Finished | Jun 28 08:24:11 PM PDT 24 |
| Peak memory | 607192 kb |
| Host | smart-31df6c07-79e5-4c0e-95fa-cff39db42be2 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_usb_clk_disabled_when_active_test:1:new_rules,test_rom:0 +cdc_instrumentation_enable d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1314807643 -assert no postproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de fault.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_usb_clk_disabled_when_active.1314807643 |
| Directory | /workspace/2.chip_sw_pwrmgr_usb_clk_disabled_when_active/latest |
| Test location | /workspace/coverage/default/2.chip_sw_pwrmgr_usbdev_smoketest.1163701333 |
| Short name | T404 |
| Test name | |
| Test status | |
| Simulation time | 5783258524 ps |
| CPU time | 451.82 seconds |
| Started | Jun 28 08:24:16 PM PDT 24 |
| Finished | Jun 28 08:31:54 PM PDT 24 |
| Peak memory | 607900 kb |
| Host | smart-b30a56e8-8c1b-4d42-bb04-ce8155ac4e98 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_usbdev_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1163701333 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_usbdev_smoketest.1163701333 |
| Directory | /workspace/2.chip_sw_pwrmgr_usbdev_smoketest/latest |
| Test location | /workspace/coverage/default/2.chip_sw_pwrmgr_wdog_reset.1809561189 |
| Short name | T1044 |
| Test name | |
| Test status | |
| Simulation time | 4993667882 ps |
| CPU time | 734.24 seconds |
| Started | Jun 28 08:18:15 PM PDT 24 |
| Finished | Jun 28 08:30:36 PM PDT 24 |
| Peak memory | 609184 kb |
| Host | smart-1da42a94-323a-4d6e-96fc-49542462df94 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=pwrmgr_wdog_reset_reqs_test:1:new_rules,test_rom:0 +cdc_inst rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=180 9561189 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_wdog_reset.1809561189 |
| Directory | /workspace/2.chip_sw_pwrmgr_wdog_reset/latest |
| Test location | /workspace/coverage/default/2.chip_sw_rom_ctrl_integrity_check.2210646420 |
| Short name | T409 |
| Test name | |
| Test status | |
| Simulation time | 9982898637 ps |
| CPU time | 590.67 seconds |
| Started | Jun 28 08:19:57 PM PDT 24 |
| Finished | Jun 28 08:29:49 PM PDT 24 |
| Peak memory | 609172 kb |
| Host | smart-28043cf6-723a-41a9-b844-2e6a6d4b359e |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=rom_ctrl_integrity_check_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2210646420 -assert nopostproc +U VM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_ctrl_integrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co verage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_rom_ctrl_integrity_check.2210646420 |
| Directory | /workspace/2.chip_sw_rom_ctrl_integrity_check/latest |
| Test location | /workspace/coverage/default/2.chip_sw_rstmgr_cpu_info.2299184888 |
| Short name | T242 |
| Test name | |
| Test status | |
| Simulation time | 6164873920 ps |
| CPU time | 867.75 seconds |
| Started | Jun 28 08:17:25 PM PDT 24 |
| Finished | Jun 28 08:31:54 PM PDT 24 |
| Peak memory | 609276 kb |
| Host | smart-43272ed5-e5f4-4cea-ba36-f8f1583f3ef0 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=rstmgr_cpu_info_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2299184888 -assert nopostproc +UVM_TESTNA ME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 2.chip_sw_rstmgr_cpu_info.2299184888 |
| Directory | /workspace/2.chip_sw_rstmgr_cpu_info/latest |
| Test location | /workspace/coverage/default/2.chip_sw_rstmgr_rst_cnsty_escalation.3003817889 |
| Short name | T315 |
| Test name | |
| Test status | |
| Simulation time | 5239120200 ps |
| CPU time | 645.81 seconds |
| Started | Jun 28 08:14:05 PM PDT 24 |
| Finished | Jun 28 08:24:52 PM PDT 24 |
| Peak memory | 639388 kb |
| Host | smart-ddb5eb1f-e3f3-4ae9-a432-001a018daf26 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 3003817889 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rstmgr_cnsty_fault_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_rstmgr_rst_cnsty_escalation.3003817889 |
| Directory | /workspace/2.chip_sw_rstmgr_rst_cnsty_escalation/latest |
| Test location | /workspace/coverage/default/2.chip_sw_rstmgr_smoketest.1611731263 |
| Short name | T949 |
| Test name | |
| Test status | |
| Simulation time | 3078582920 ps |
| CPU time | 189.15 seconds |
| Started | Jun 28 08:23:02 PM PDT 24 |
| Finished | Jun 28 08:26:16 PM PDT 24 |
| Peak memory | 607292 kb |
| Host | smart-2e4dac69-7982-4479-a0e7-07e7c50d065b |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=rstmgr_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1611731263 -assert nopostproc +UVM_TESTNAME=c hip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n ull -cm_name 2.chip_sw_rstmgr_smoketest.1611731263 |
| Directory | /workspace/2.chip_sw_rstmgr_smoketest/latest |
| Test location | /workspace/coverage/default/2.chip_sw_rstmgr_sw_req.188027856 |
| Short name | T970 |
| Test name | |
| Test status | |
| Simulation time | 3423465800 ps |
| CPU time | 421.44 seconds |
| Started | Jun 28 08:16:23 PM PDT 24 |
| Finished | Jun 28 08:23:25 PM PDT 24 |
| Peak memory | 607144 kb |
| Host | smart-81e690e5-c863-4ff5-9e8e-6063ac99a62b |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=rstmgr_sw_req_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=188027856 -assert nopostproc +UVM_TESTNAME= chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/ null -cm_name 2.chip_sw_rstmgr_sw_req.188027856 |
| Directory | /workspace/2.chip_sw_rstmgr_sw_req/latest |
| Test location | /workspace/coverage/default/2.chip_sw_rstmgr_sw_rst.2880847219 |
| Short name | T381 |
| Test name | |
| Test status | |
| Simulation time | 2241715880 ps |
| CPU time | 284.65 seconds |
| Started | Jun 28 08:18:55 PM PDT 24 |
| Finished | Jun 28 08:23:41 PM PDT 24 |
| Peak memory | 609180 kb |
| Host | smart-e4afa8b7-e2cd-4a67-b72f-6c2900f84d31 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=rstmgr_sw_rst_ctrl_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2880847219 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_rstmgr_sw_rst.2880847219 |
| Directory | /workspace/2.chip_sw_rstmgr_sw_rst/latest |
| Test location | /workspace/coverage/default/2.chip_sw_rv_core_ibex_address_translation.3184278564 |
| Short name | T303 |
| Test name | |
| Test status | |
| Simulation time | 2922318120 ps |
| CPU time | 310.46 seconds |
| Started | Jun 28 08:23:40 PM PDT 24 |
| Finished | Jun 28 08:28:53 PM PDT 24 |
| Peak memory | 609148 kb |
| Host | smart-2d6e4e49-797b-4003-a342-1759db5fafeb |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=7_000_000 +sw_build_device=sim_dv +sw_images=rv_core_ibex_address_translation_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=3184278564 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_rv_core_ibex_address_translation.3184278564 |
| Directory | /workspace/2.chip_sw_rv_core_ibex_address_translation/latest |
| Test location | /workspace/coverage/default/2.chip_sw_rv_core_ibex_icache_invalidate.4198827421 |
| Short name | T42 |
| Test name | |
| Test status | |
| Simulation time | 2762367918 ps |
| CPU time | 306.97 seconds |
| Started | Jun 28 08:24:30 PM PDT 24 |
| Finished | Jun 28 08:29:44 PM PDT 24 |
| Peak memory | 609148 kb |
| Host | smart-5e06b869-64c5-4b8d-b7e9-bc998c5986c7 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=rv_core_ibex_icache_invalidate_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4198827421 -assert nopostp roc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rv_core_ibex_icache_invalidate_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_rv_core_ibex_icache_invalidate.4198827421 |
| Directory | /workspace/2.chip_sw_rv_core_ibex_icache_invalidate/latest |
| Test location | /workspace/coverage/default/2.chip_sw_rv_core_ibex_nmi_irq.2659103665 |
| Short name | T508 |
| Test name | |
| Test status | |
| Simulation time | 4680508888 ps |
| CPU time | 987.62 seconds |
| Started | Jun 28 08:19:14 PM PDT 24 |
| Finished | Jun 28 08:35:42 PM PDT 24 |
| Peak memory | 609148 kb |
| Host | smart-ab134da5-b8da-42a9-a808-0c35a7308f03 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=10_000_000 +sw_build_device=sim_dv +sw_images=rv_core_ibex_nmi_irq_test:1:new_rules,test_rom:0 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26591 03665 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_rv_core_ibex_nmi_irq.2659103665 |
| Directory | /workspace/2.chip_sw_rv_core_ibex_nmi_irq/latest |
| Test location | /workspace/coverage/default/2.chip_sw_rv_core_ibex_rnd.251209253 |
| Short name | T1153 |
| Test name | |
| Test status | |
| Simulation time | 6104921100 ps |
| CPU time | 977.57 seconds |
| Started | Jun 28 08:18:12 PM PDT 24 |
| Finished | Jun 28 08:34:33 PM PDT 24 |
| Peak memory | 609180 kb |
| Host | smart-667e673e-dea9-4c62-bf90-ff85cd17194a |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=20_000_000 +rng_srate_value_max=32 +sw_build_device=sim_dv +sw_images=rv_core_ibex_rnd_test:1:new_rules,te st_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n tb_random_seed=251209253 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_rv_core_ibex_rnd.251209253 |
| Directory | /workspace/2.chip_sw_rv_core_ibex_rnd/latest |
| Test location | /workspace/coverage/default/2.chip_sw_rv_dm_access_after_escalation_reset.2166149164 |
| Short name | T641 |
| Test name | |
| Test status | |
| Simulation time | 5299306374 ps |
| CPU time | 603.5 seconds |
| Started | Jun 28 08:27:23 PM PDT 24 |
| Finished | Jun 28 08:37:28 PM PDT 24 |
| Peak memory | 618072 kb |
| Host | smart-da72c741-534b-4444-964b-643529eaaf77 |
| User | root |
| Command | /workspace/default/simv +use_jtag_dmi=1 +sw_build_device=sim_dv +sw_images=alert_handler_escalation_test:1:new_rules,test_rom:0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2166149164 -asse rt nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rv_dm_access_after_escalation_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_rv_dm_access_after_escalation_reset.2166149164 |
| Directory | /workspace/2.chip_sw_rv_dm_access_after_escalation_reset/latest |
| Test location | /workspace/coverage/default/2.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted.1938868769 |
| Short name | T236 |
| Test name | |
| Test status | |
| Simulation time | 4491056664 ps |
| CPU time | 471.75 seconds |
| Started | Jun 28 08:21:15 PM PDT 24 |
| Finished | Jun 28 08:29:09 PM PDT 24 |
| Peak memory | 614864 kb |
| Host | smart-396e6e4f-350e-4988-81ca-8eb1a8eba5c4 |
| User | root |
| Command | /workspace/default/simv +use_jtag_dmi=1 +sw_build_device=sim_dv +sw_images=rv_dm_ndm_reset_req_when_cpu_halted_rma:1:new_rules,test_rom:0 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=193886 8769 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rv_dm_ndm_reset_when_cpu_halted_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted.1938868769 |
| Directory | /workspace/2.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted/latest |
| Test location | /workspace/coverage/default/2.chip_sw_rv_plic_smoketest.1751143770 |
| Short name | T910 |
| Test name | |
| Test status | |
| Simulation time | 3195572484 ps |
| CPU time | 274.57 seconds |
| Started | Jun 28 08:25:33 PM PDT 24 |
| Finished | Jun 28 08:30:08 PM PDT 24 |
| Peak memory | 609184 kb |
| Host | smart-385854f4-dd07-43dc-b21a-2e860ee84791 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=rv_plic_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1751143770 -assert nopostproc +UVM_TESTNAME= chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/ null -cm_name 2.chip_sw_rv_plic_smoketest.1751143770 |
| Directory | /workspace/2.chip_sw_rv_plic_smoketest/latest |
| Test location | /workspace/coverage/default/2.chip_sw_rv_timer_irq.3958123769 |
| Short name | T251 |
| Test name | |
| Test status | |
| Simulation time | 3140531572 ps |
| CPU time | 232.05 seconds |
| Started | Jun 28 08:17:57 PM PDT 24 |
| Finished | Jun 28 08:21:50 PM PDT 24 |
| Peak memory | 607124 kb |
| Host | smart-d609abe5-8e90-4106-b818-7057ce4e08f4 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=rv_timer_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3958123769 -assert nopostproc +UVM_TESTNAME =chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 2.chip_sw_rv_timer_irq.3958123769 |
| Directory | /workspace/2.chip_sw_rv_timer_irq/latest |
| Test location | /workspace/coverage/default/2.chip_sw_rv_timer_smoketest.1954745879 |
| Short name | T1097 |
| Test name | |
| Test status | |
| Simulation time | 2571617658 ps |
| CPU time | 250.1 seconds |
| Started | Jun 28 08:23:38 PM PDT 24 |
| Finished | Jun 28 08:27:50 PM PDT 24 |
| Peak memory | 609188 kb |
| Host | smart-07665959-ea3b-4cf9-b693-31af2dc12a19 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=rv_timer_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1954745879 -assert nopostproc +UVM_TESTNAME =chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 2.chip_sw_rv_timer_smoketest.1954745879 |
| Directory | /workspace/2.chip_sw_rv_timer_smoketest/latest |
| Test location | /workspace/coverage/default/2.chip_sw_sensor_ctrl_alert.3624216548 |
| Short name | T129 |
| Test name | |
| Test status | |
| Simulation time | 9065490440 ps |
| CPU time | 1225.39 seconds |
| Started | Jun 28 08:21:33 PM PDT 24 |
| Finished | Jun 28 08:41:59 PM PDT 24 |
| Peak memory | 609148 kb |
| Host | smart-62211c6f-95e5-4340-8fed-06fdd7d63239 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=40_000_000 +sw_build_device=sim_dv +sw_images=sensor_ctrl_alert_test:1:new_rules,test_rom:0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36242165 48 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac e/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_sensor_ctrl_alert.3624216548 |
| Directory | /workspace/2.chip_sw_sensor_ctrl_alert/latest |
| Test location | /workspace/coverage/default/2.chip_sw_sensor_ctrl_status.3156442694 |
| Short name | T350 |
| Test name | |
| Test status | |
| Simulation time | 3351120728 ps |
| CPU time | 360.88 seconds |
| Started | Jun 28 08:20:16 PM PDT 24 |
| Finished | Jun 28 08:26:18 PM PDT 24 |
| Peak memory | 608656 kb |
| Host | smart-e1211ca2-5af7-47dd-b8c3-1e9be88762c5 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=40_000_000 +sw_build_device=sim_dv +sw_images=sensor_ctrl_status_test:1:new_rules,test_rom:0 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3156442 694 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sensor_ctrl_status_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_sensor_ctrl_status.3156442694 |
| Directory | /workspace/2.chip_sw_sensor_ctrl_status/latest |
| Test location | /workspace/coverage/default/2.chip_sw_sleep_pin_retention.1584293017 |
| Short name | T13 |
| Test name | |
| Test status | |
| Simulation time | 3079610200 ps |
| CPU time | 346.79 seconds |
| Started | Jun 28 08:15:25 PM PDT 24 |
| Finished | Jun 28 08:21:15 PM PDT 24 |
| Peak memory | 607188 kb |
| Host | smart-57f122e2-d389-43b4-bfb5-2c626185b3ee |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=sleep_pin_retention_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1584293017 -assert nopostproc +UVM_TE STNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sleep_pin_retention_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def ault.vdb -cm_log /dev/null -cm_name 2.chip_sw_sleep_pin_retention.1584293017 |
| Directory | /workspace/2.chip_sw_sleep_pin_retention/latest |
| Test location | /workspace/coverage/default/2.chip_sw_sleep_pwm_pulses.3668448138 |
| Short name | T1196 |
| Test name | |
| Test status | |
| Simulation time | 8552124108 ps |
| CPU time | 1382.19 seconds |
| Started | Jun 28 08:18:31 PM PDT 24 |
| Finished | Jun 28 08:41:38 PM PDT 24 |
| Peak memory | 608352 kb |
| Host | smart-18612cc1-b58c-4de9-964f-ffecdd55dd25 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=sleep_pwm_pulses_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3668448138 -assert nopostproc +UVM_TESTN AME=chip_base_test +UVM_TEST_SEQ=chip_sw_pwm_pulses_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm _log /dev/null -cm_name 2.chip_sw_sleep_pwm_pulses.3668448138 |
| Directory | /workspace/2.chip_sw_sleep_pwm_pulses/latest |
| Test location | /workspace/coverage/default/2.chip_sw_sleep_sram_ret_contents_no_scramble.4264780020 |
| Short name | T912 |
| Test name | |
| Test status | |
| Simulation time | 7057491452 ps |
| CPU time | 596.41 seconds |
| Started | Jun 28 08:20:30 PM PDT 24 |
| Finished | Jun 28 08:30:27 PM PDT 24 |
| Peak memory | 609248 kb |
| Host | smart-474aba83-8ca4-4f3e-b828-656e93aa6f93 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=20_000_000 +en_scb_tl_err_chk=0 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=sram _ctrl_sleep_sram_ret_contents_no_scramble_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4264780020 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_S EQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_sl eep_sram_ret_contents_no_scramble.4264780020 |
| Directory | /workspace/2.chip_sw_sleep_sram_ret_contents_no_scramble/latest |
| Test location | /workspace/coverage/default/2.chip_sw_sleep_sram_ret_contents_scramble.2108508714 |
| Short name | T989 |
| Test name | |
| Test status | |
| Simulation time | 7723273560 ps |
| CPU time | 823.75 seconds |
| Started | Jun 28 08:26:02 PM PDT 24 |
| Finished | Jun 28 08:39:53 PM PDT 24 |
| Peak memory | 609248 kb |
| Host | smart-9b330904-5654-49aa-9a58-55a7cdcf6609 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=20_000_000 +en_scb_tl_err_chk=0 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=sram _ctrl_sleep_sram_ret_contents_scramble_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2108508714 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ= chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_sleep _sram_ret_contents_scramble.2108508714 |
| Directory | /workspace/2.chip_sw_sleep_sram_ret_contents_scramble/latest |
| Test location | /workspace/coverage/default/2.chip_sw_spi_device_pass_through.539460755 |
| Short name | T193 |
| Test name | |
| Test status | |
| Simulation time | 7619185503 ps |
| CPU time | 986.68 seconds |
| Started | Jun 28 08:16:19 PM PDT 24 |
| Finished | Jun 28 08:32:48 PM PDT 24 |
| Peak memory | 624212 kb |
| Host | smart-2bdf15fc-511d-4551-85a9-882a80130843 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=spi_passthrough_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=539460755 -assert nopostproc +UVM_TESTNAM E=chip_base_test +UVM_TEST_SEQ=chip_sw_spi_passthrough_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_spi_device_pass_through.539460755 |
| Directory | /workspace/2.chip_sw_spi_device_pass_through/latest |
| Test location | /workspace/coverage/default/2.chip_sw_spi_device_pass_through_collision.52990052 |
| Short name | T192 |
| Test name | |
| Test status | |
| Simulation time | 4882125918 ps |
| CPU time | 614.97 seconds |
| Started | Jun 28 08:16:36 PM PDT 24 |
| Finished | Jun 28 08:26:52 PM PDT 24 |
| Peak memory | 624284 kb |
| Host | smart-887fdc25-e59a-4edf-91a9-fb3e68b82c36 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=spi_passthrough_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52990052 -assert nopostproc +UVM_TESTNAME =chip_base_test +UVM_TEST_SEQ=chip_sw_spi_passthrough_collision_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def ault.vdb -cm_log /dev/null -cm_name 2.chip_sw_spi_device_pass_through_collision.52990052 |
| Directory | /workspace/2.chip_sw_spi_device_pass_through_collision/latest |
| Test location | /workspace/coverage/default/2.chip_sw_spi_device_tpm.2747084058 |
| Short name | T49 |
| Test name | |
| Test status | |
| Simulation time | 3863420947 ps |
| CPU time | 383.8 seconds |
| Started | Jun 28 08:16:00 PM PDT 24 |
| Finished | Jun 28 08:22:28 PM PDT 24 |
| Peak memory | 622136 kb |
| Host | smart-0751ec97-2558-473a-91d8-3120978b2c31 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=spi_device_tpm_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2747084058 -assert nopostproc +UVM_T ESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_spi_device_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default .vdb -cm_log /dev/null -cm_name 2.chip_sw_spi_device_tpm.2747084058 |
| Directory | /workspace/2.chip_sw_spi_device_tpm/latest |
| Test location | /workspace/coverage/default/2.chip_sw_sram_ctrl_execution_main.3445361442 |
| Short name | T304 |
| Test name | |
| Test status | |
| Simulation time | 7611137428 ps |
| CPU time | 1015.94 seconds |
| Started | Jun 28 08:27:04 PM PDT 24 |
| Finished | Jun 28 08:44:01 PM PDT 24 |
| Peak memory | 608184 kb |
| Host | smart-ba04e67d-588c-494b-99d1-f9733a96d913 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=sram_ctrl_execution_main_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3445361442 -assert nopostproc +U VM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sram_ctrl_execution_main_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co verage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_sram_ctrl_execution_main.3445361442 |
| Directory | /workspace/2.chip_sw_sram_ctrl_execution_main/latest |
| Test location | /workspace/coverage/default/2.chip_sw_sram_ctrl_scrambled_access.1218803030 |
| Short name | T169 |
| Test name | |
| Test status | |
| Simulation time | 4084888462 ps |
| CPU time | 646.87 seconds |
| Started | Jun 28 08:24:57 PM PDT 24 |
| Finished | Jun 28 08:35:46 PM PDT 24 |
| Peak memory | 608192 kb |
| Host | smart-5799b234-33cf-456f-ade0-a1322dbb6366 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=12_000_000 +en_scb_tl_err_chk=0 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=sram _ctrl_scrambled_access_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1218803030 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sram_ctr l_scrambled_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw _sram_ctrl_scrambled_access.1218803030 |
| Directory | /workspace/2.chip_sw_sram_ctrl_scrambled_access/latest |
| Test location | /workspace/coverage/default/2.chip_sw_sram_ctrl_scrambled_access_jitter_en.2208226340 |
| Short name | T276 |
| Test name | |
| Test status | |
| Simulation time | 5484704107 ps |
| CPU time | 654.58 seconds |
| Started | Jun 28 08:22:43 PM PDT 24 |
| Finished | Jun 28 08:33:40 PM PDT 24 |
| Peak memory | 608816 kb |
| Host | smart-54da525b-7a04-4ddf-bcb8-321a454dcdd7 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=12_000_000 +bypass_alert_ready_to_end_check=1 +en_jitter=1 +en_scb_tl_err_chk=0 +sw_build_device=sim_dv +s w_images=sram_ctrl_scrambled_access_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2208226340 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chi p_sw_sram_ctrl_scrambled_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n ame 2.chip_sw_sram_ctrl_scrambled_access_jitter_en.2208226340 |
| Directory | /workspace/2.chip_sw_sram_ctrl_scrambled_access_jitter_en/latest |
| Test location | /workspace/coverage/default/2.chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq.886208913 |
| Short name | T1146 |
| Test name | |
| Test status | |
| Simulation time | 4466677277 ps |
| CPU time | 764.15 seconds |
| Started | Jun 28 08:21:43 PM PDT 24 |
| Finished | Jun 28 08:34:29 PM PDT 24 |
| Peak memory | 607500 kb |
| Host | smart-4505e5aa-1694-46c8-871a-ee97a5d9dbaf |
| User | root |
| Command | /workspace/default/simv +mem_sel=main +sw_test_timeout_ns=12_000_000 +bypass_alert_ready_to_end_check=1 +en_jitter=1 +en_scb_tl_err_chk=0 +cal_sys_clk _70mhz=1 +sw_build_device=sim_dv +sw_images=sram_ctrl_scrambled_access_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=886208913 -assert nopostproc +UVM_TESTNAM E=chip_base_test +UVM_TEST_SEQ=chip_sw_sram_ctrl_scrambled_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/d efault.vdb -cm_log /dev/null -cm_name 2.chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq.886208913 |
| Directory | /workspace/2.chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq/latest |
| Test location | /workspace/coverage/default/2.chip_sw_sram_ctrl_smoketest.2873918349 |
| Short name | T964 |
| Test name | |
| Test status | |
| Simulation time | 2659874644 ps |
| CPU time | 287.32 seconds |
| Started | Jun 28 08:22:53 PM PDT 24 |
| Finished | Jun 28 08:27:46 PM PDT 24 |
| Peak memory | 607248 kb |
| Host | smart-76fba3bb-3af0-49b2-9a05-fe1243f04d1d |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=sram_ctrl_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2873918349 -assert nopostproc +UVM_TESTNAM E=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 2.chip_sw_sram_ctrl_smoketest.2873918349 |
| Directory | /workspace/2.chip_sw_sram_ctrl_smoketest/latest |
| Test location | /workspace/coverage/default/2.chip_sw_sysrst_ctrl_ec_rst_l.109383771 |
| Short name | T32 |
| Test name | |
| Test status | |
| Simulation time | 20940612066 ps |
| CPU time | 3820.34 seconds |
| Started | Jun 28 08:18:01 PM PDT 24 |
| Finished | Jun 28 09:21:42 PM PDT 24 |
| Peak memory | 608280 kb |
| Host | smart-3816cfdf-fe77-41f1-9637-1ce57263af74 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=sysrst_ctrl_ec_rst_l_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=109383771 -assert nopostproc +UVM_TE STNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_ec_rst_l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de fault.vdb -cm_log /dev/null -cm_name 2.chip_sw_sysrst_ctrl_ec_rst_l.109383771 |
| Directory | /workspace/2.chip_sw_sysrst_ctrl_ec_rst_l/latest |
| Test location | /workspace/coverage/default/2.chip_sw_sysrst_ctrl_in_irq.1410269448 |
| Short name | T199 |
| Test name | |
| Test status | |
| Simulation time | 3949616318 ps |
| CPU time | 689.4 seconds |
| Started | Jun 28 08:19:17 PM PDT 24 |
| Finished | Jun 28 08:30:50 PM PDT 24 |
| Peak memory | 612296 kb |
| Host | smart-938d1330-9a99-4479-a19e-86dfc444f704 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=sysrst_ctrl_in_irq_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1410269448 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_in_irq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau lt.vdb -cm_log /dev/null -cm_name 2.chip_sw_sysrst_ctrl_in_irq.1410269448 |
| Directory | /workspace/2.chip_sw_sysrst_ctrl_in_irq/latest |
| Test location | /workspace/coverage/default/2.chip_sw_sysrst_ctrl_inputs.801661510 |
| Short name | T1194 |
| Test name | |
| Test status | |
| Simulation time | 3209769156 ps |
| CPU time | 311.66 seconds |
| Started | Jun 28 08:17:36 PM PDT 24 |
| Finished | Jun 28 08:22:52 PM PDT 24 |
| Peak memory | 610840 kb |
| Host | smart-3bbdcda9-52a9-4f92-9087-8e8aebb377d2 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=sysrst_ctrl_inputs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=801661510 -assert nopostproc +UVM_TEST NAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_inputs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul t.vdb -cm_log /dev/null -cm_name 2.chip_sw_sysrst_ctrl_inputs.801661510 |
| Directory | /workspace/2.chip_sw_sysrst_ctrl_inputs/latest |
| Test location | /workspace/coverage/default/2.chip_sw_sysrst_ctrl_outputs.1006672580 |
| Short name | T204 |
| Test name | |
| Test status | |
| Simulation time | 3852076800 ps |
| CPU time | 430.55 seconds |
| Started | Jun 28 08:18:45 PM PDT 24 |
| Finished | Jun 28 08:25:57 PM PDT 24 |
| Peak memory | 609184 kb |
| Host | smart-57f538fe-b2fb-4964-b206-e2a68f9749ad |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=sysrst_ctrl_outputs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1006672580 -assert nopostproc +UVM_TE STNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_outputs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def ault.vdb -cm_log /dev/null -cm_name 2.chip_sw_sysrst_ctrl_outputs.1006672580 |
| Directory | /workspace/2.chip_sw_sysrst_ctrl_outputs/latest |
| Test location | /workspace/coverage/default/2.chip_sw_sysrst_ctrl_reset.324178661 |
| Short name | T1272 |
| Test name | |
| Test status | |
| Simulation time | 24392304808 ps |
| CPU time | 1787.96 seconds |
| Started | Jun 28 08:16:55 PM PDT 24 |
| Finished | Jun 28 08:46:47 PM PDT 24 |
| Peak memory | 612856 kb |
| Host | smart-23fe832a-d0b1-486f-a9b5-23c7f559d54a |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=36_000_000 +sw_build_device=sim_dv +sw_images=sysrst_ctrl_reset_test:1:new_rules,test_rom:0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32417866 1 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_sysrst_ctrl_reset.324178661 |
| Directory | /workspace/2.chip_sw_sysrst_ctrl_reset/latest |
| Test location | /workspace/coverage/default/2.chip_sw_sysrst_ctrl_ulp_z3_wakeup.2128098694 |
| Short name | T45 |
| Test name | |
| Test status | |
| Simulation time | 5804489840 ps |
| CPU time | 677.91 seconds |
| Started | Jun 28 08:18:25 PM PDT 24 |
| Finished | Jun 28 08:29:52 PM PDT 24 |
| Peak memory | 608368 kb |
| Host | smart-084a7b72-87ea-4809-9448-7aa95af0a4c7 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=sysrst_ctrl_ulp_z3_wakeup_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2128098694 -assert nopostproc + UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_ulp_z3_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/ coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_sysrst_ctrl_ulp_z3_wakeup.2128098694 |
| Directory | /workspace/2.chip_sw_sysrst_ctrl_ulp_z3_wakeup/latest |
| Test location | /workspace/coverage/default/2.chip_sw_uart_rand_baudrate.2889356586 |
| Short name | T1174 |
| Test name | |
| Test status | |
| Simulation time | 12942532380 ps |
| CPU time | 2824.97 seconds |
| Started | Jun 28 08:14:48 PM PDT 24 |
| Finished | Jun 28 09:01:56 PM PDT 24 |
| Peak memory | 618616 kb |
| Host | smart-df92df12-6f38-43d6-9b64-49b29419434e |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=2889356586 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_uart_rand_baudrate.2889356586 |
| Directory | /workspace/2.chip_sw_uart_rand_baudrate/latest |
| Test location | /workspace/coverage/default/2.chip_sw_uart_smoketest.1432860077 |
| Short name | T1001 |
| Test name | |
| Test status | |
| Simulation time | 2759922964 ps |
| CPU time | 200.14 seconds |
| Started | Jun 28 08:25:22 PM PDT 24 |
| Finished | Jun 28 08:28:48 PM PDT 24 |
| Peak memory | 609948 kb |
| Host | smart-64341f4f-8e74-47b7-a08f-7e41e00b44aa |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=uart_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1432860077 -assert nopostproc +UVM_TESTNAME=chi p_base_test +UVM_TEST_SEQ=chip_sw_uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 2.chip_sw_uart_smoketest.1432860077 |
| Directory | /workspace/2.chip_sw_uart_smoketest/latest |
| Test location | /workspace/coverage/default/2.chip_sw_uart_tx_rx.3251789559 |
| Short name | T966 |
| Test name | |
| Test status | |
| Simulation time | 3920791830 ps |
| CPU time | 681.56 seconds |
| Started | Jun 28 08:16:33 PM PDT 24 |
| Finished | Jun 28 08:27:56 PM PDT 24 |
| Peak memory | 615860 kb |
| Host | smart-509d8a4e-8b22-49e7-81d0-8b4abad6dd3b |
| User | root |
| Command | /workspace/default/simv +uart_idx=0 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3251789559 -a ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_uart_tx_rx.3251789559 |
| Directory | /workspace/2.chip_sw_uart_tx_rx/latest |
| Test location | /workspace/coverage/default/2.chip_sw_uart_tx_rx_alt_clk_freq.1271216471 |
| Short name | T1026 |
| Test name | |
| Test status | |
| Simulation time | 4652906597 ps |
| CPU time | 723.55 seconds |
| Started | Jun 28 08:15:54 PM PDT 24 |
| Finished | Jun 28 08:28:01 PM PDT 24 |
| Peak memory | 617928 kb |
| Host | smart-d3349f70-f14a-44a2-94af-c34366014315 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=80_000_000 +chip_clock_source=ChipClockSourceExternal96Mhz +calibrate_usb_clk=1 +sw_build_device=sim_dv +s w_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1271216471 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_b audrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_uart_tx_rx _alt_clk_freq.1271216471 |
| Directory | /workspace/2.chip_sw_uart_tx_rx_alt_clk_freq/latest |
| Test location | /workspace/coverage/default/2.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.4034701349 |
| Short name | T1012 |
| Test name | |
| Test status | |
| Simulation time | 4178170208 ps |
| CPU time | 519.49 seconds |
| Started | Jun 28 08:19:14 PM PDT 24 |
| Finished | Jun 28 08:27:55 PM PDT 24 |
| Peak memory | 618676 kb |
| Host | smart-29c4dc61-3f74-4a18-9514-1ea591a3aac8 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +chip_clock_source=ChipClockSourceExternal48Mhz +sw_build_device=sim_dv +s w_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4034701349 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_b audrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_uart_tx_rx _alt_clk_freq_low_speed.4034701349 |
| Directory | /workspace/2.chip_sw_uart_tx_rx_alt_clk_freq_low_speed/latest |
| Test location | /workspace/coverage/default/2.chip_sw_uart_tx_rx_bootstrap.3889459738 |
| Short name | T196 |
| Test name | |
| Test status | |
| Simulation time | 78897230024 ps |
| CPU time | 14965.6 seconds |
| Started | Jun 28 08:17:02 PM PDT 24 |
| Finished | Jun 29 12:26:34 AM PDT 24 |
| Peak memory | 640496 kb |
| Host | smart-97e34b00-fe7d-4b01-8a1f-154096c42a99 |
| User | root |
| Command | /workspace/default/simv +use_spi_load_bootstrap=1 +calibrate_usb_clk=1 +test_timeout_ns=160_000_000 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test :1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=3889459738 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_uart_tx_rx_bootstrap.3889459738 |
| Directory | /workspace/2.chip_sw_uart_tx_rx_bootstrap/latest |
| Test location | /workspace/coverage/default/2.chip_sw_uart_tx_rx_idx1.2896081577 |
| Short name | T996 |
| Test name | |
| Test status | |
| Simulation time | 4742889458 ps |
| CPU time | 781.54 seconds |
| Started | Jun 28 08:15:08 PM PDT 24 |
| Finished | Jun 28 08:28:11 PM PDT 24 |
| Peak memory | 624040 kb |
| Host | smart-64b29148-a984-4e47-91d9-8e388bc93b2a |
| User | root |
| Command | /workspace/default/simv +uart_idx=1 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2896081577 -a ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_uart_tx_rx_idx1.2896081577 |
| Directory | /workspace/2.chip_sw_uart_tx_rx_idx1/latest |
| Test location | /workspace/coverage/default/2.chip_sw_uart_tx_rx_idx2.3222567065 |
| Short name | T103 |
| Test name | |
| Test status | |
| Simulation time | 3946402160 ps |
| CPU time | 690.42 seconds |
| Started | Jun 28 08:16:28 PM PDT 24 |
| Finished | Jun 28 08:28:00 PM PDT 24 |
| Peak memory | 615860 kb |
| Host | smart-a0207fc9-d0ce-48e7-b367-f29f1a3b17bd |
| User | root |
| Command | /workspace/default/simv +uart_idx=2 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3222567065 -a ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_uart_tx_rx_idx2.3222567065 |
| Directory | /workspace/2.chip_sw_uart_tx_rx_idx2/latest |
| Test location | /workspace/coverage/default/2.chip_sw_uart_tx_rx_idx3.2081782937 |
| Short name | T353 |
| Test name | |
| Test status | |
| Simulation time | 4936662020 ps |
| CPU time | 681.61 seconds |
| Started | Jun 28 08:15:18 PM PDT 24 |
| Finished | Jun 28 08:26:41 PM PDT 24 |
| Peak memory | 615884 kb |
| Host | smart-c1b14141-ca60-49af-9df4-364aa7056b92 |
| User | root |
| Command | /workspace/default/simv +uart_idx=3 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2081782937 -a ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_uart_tx_rx_idx3.2081782937 |
| Directory | /workspace/2.chip_sw_uart_tx_rx_idx3/latest |
| Test location | /workspace/coverage/default/2.chip_tap_straps_dev.3007430613 |
| Short name | T94 |
| Test name | |
| Test status | |
| Simulation time | 10503271211 ps |
| CPU time | 1204.6 seconds |
| Started | Jun 28 08:21:30 PM PDT 24 |
| Finished | Jun 28 08:41:36 PM PDT 24 |
| Peak memory | 620368 kb |
| Host | smart-64ea0f7c-f3f1-490e-a799-22c6887fce2b |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStDev +create_jtag_riscv_map=1 +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:test_in_rom: new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=3007430613 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_tap_straps_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_tap_straps_dev.3007430613 |
| Directory | /workspace/2.chip_tap_straps_dev/latest |
| Test location | /workspace/coverage/default/2.chip_tap_straps_prod.685789304 |
| Short name | T1149 |
| Test name | |
| Test status | |
| Simulation time | 3101486627 ps |
| CPU time | 171.09 seconds |
| Started | Jun 28 08:20:29 PM PDT 24 |
| Finished | Jun 28 08:23:21 PM PDT 24 |
| Peak memory | 618428 kb |
| Host | smart-8ad003a6-0964-4148-8052-0275dc7e0ab5 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStProd +create_jtag_riscv_map=1 +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:test_in_rom :new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=685789304 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_tap_straps_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_tap_straps_prod.685789304 |
| Directory | /workspace/2.chip_tap_straps_prod/latest |
| Test location | /workspace/coverage/default/2.rom_e2e_asm_init_dev.3274739581 |
| Short name | T1140 |
| Test name | |
| Test status | |
| Simulation time | 15726653279 ps |
| CPU time | 3198.07 seconds |
| Started | Jun 28 08:26:53 PM PDT 24 |
| Finished | Jun 28 09:20:12 PM PDT 24 |
| Peak memory | 607188 kb |
| Host | smart-eb64ddca-ab57-4240-bb05-23a5c7cc24c4 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeCustom +sw_test_timeout_ns=20000000 +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_prod _key_0:1:ot_flash_binary,otp_img_e2e_bootstrap_entry_dev:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3274739581 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_S EQ=chip_sw_rom_e2e_asm_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_e2e_asm_init_dev.3274739581 |
| Directory | /workspace/2.rom_e2e_asm_init_dev/latest |
| Test location | /workspace/coverage/default/2.rom_e2e_asm_init_prod.3248034553 |
| Short name | T985 |
| Test name | |
| Test status | |
| Simulation time | 15518223822 ps |
| CPU time | 3670.19 seconds |
| Started | Jun 28 08:27:31 PM PDT 24 |
| Finished | Jun 28 09:28:45 PM PDT 24 |
| Peak memory | 607268 kb |
| Host | smart-f688cd5e-fb09-45d0-9c24-03a2130d5ceb |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeCustom +sw_test_timeout_ns=20000000 +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_prod _key_0:1:ot_flash_binary,otp_img_e2e_bootstrap_entry_prod:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3248034553 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_ SEQ=chip_sw_rom_e2e_asm_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_e2e_asm_init_prod.3248034553 |
| Directory | /workspace/2.rom_e2e_asm_init_prod/latest |
| Test location | /workspace/coverage/default/2.rom_e2e_asm_init_prod_end.3245978456 |
| Short name | T272 |
| Test name | |
| Test status | |
| Simulation time | 15765731830 ps |
| CPU time | 3724.79 seconds |
| Started | Jun 28 08:27:21 PM PDT 24 |
| Finished | Jun 28 09:29:27 PM PDT 24 |
| Peak memory | 607884 kb |
| Host | smart-03fadba5-14d9-4af2-a62a-49308bd97b46 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeCustom +sw_test_timeout_ns=20000000 +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_prod _key_0:1:ot_flash_binary,otp_img_e2e_bootstrap_entry_prod_end:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3245978456 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_T EST_SEQ=chip_sw_rom_e2e_asm_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 2.rom_e2e_asm_init_prod_end.3245978456 |
| Directory | /workspace/2.rom_e2e_asm_init_prod_end/latest |
| Test location | /workspace/coverage/default/2.rom_e2e_asm_init_rma.2042461034 |
| Short name | T863 |
| Test name | |
| Test status | |
| Simulation time | 15129050000 ps |
| CPU time | 3749.11 seconds |
| Started | Jun 28 08:26:00 PM PDT 24 |
| Finished | Jun 28 09:28:33 PM PDT 24 |
| Peak memory | 607180 kb |
| Host | smart-57d4f5ce-9ea0-404f-ada1-a744d999b3da |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeCustom +sw_test_timeout_ns=20000000 +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_prod _key_0:1:ot_flash_binary,otp_img_e2e_bootstrap_entry_rma:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2042461034 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_S EQ=chip_sw_rom_e2e_asm_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_e2e_asm_init_rma.2042461034 |
| Directory | /workspace/2.rom_e2e_asm_init_rma/latest |
| Test location | /workspace/coverage/default/2.rom_e2e_asm_init_test_unlocked0.3125412994 |
| Short name | T1264 |
| Test name | |
| Test status | |
| Simulation time | 10999196669 ps |
| CPU time | 2651.13 seconds |
| Started | Jun 28 08:26:58 PM PDT 24 |
| Finished | Jun 28 09:11:11 PM PDT 24 |
| Peak memory | 608416 kb |
| Host | smart-94a1cded-64e1-4574-a268-3bfdd4a594bf |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeCustom +sw_test_timeout_ns=410_000_000 +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_p rod_key_0:1:ot_flash_binary,otp_img_e2e_bootstrap_entry_test_unlocked0:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY =UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3125412994 -assert nopostproc +UVM_TESTNAME=chip_base_te st +UVM_TEST_SEQ=chip_sw_rom_e2e_asm_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/ null -cm_name 2.rom_e2e_asm_init_test_unlocked0.3125412994 |
| Directory | /workspace/2.rom_e2e_asm_init_test_unlocked0/latest |
| Test location | /workspace/coverage/default/2.rom_e2e_keymgr_init_rom_ext_invalid_meas.2314557150 |
| Short name | T1046 |
| Test name | |
| Test status | |
| Simulation time | 15069930464 ps |
| CPU time | 3306.33 seconds |
| Started | Jun 28 08:28:39 PM PDT 24 |
| Finished | Jun 28 09:24:00 PM PDT 24 |
| Peak memory | 607304 kb |
| Host | smart-b63f5a8d-aefc-4c3e-ba5b-b11f8083c121 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=40_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=rom_e2e_keymgr_init_otp_invalid _meas:1:new_rules,otp_img_keymgr_otp_invalid_meas:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2314557150 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip _sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_e2e_keymgr_in it_rom_ext_invalid_meas.2314557150 |
| Directory | /workspace/2.rom_e2e_keymgr_init_rom_ext_invalid_meas/latest |
| Test location | /workspace/coverage/default/2.rom_e2e_keymgr_init_rom_ext_meas.4097244843 |
| Short name | T881 |
| Test name | |
| Test status | |
| Simulation time | 15287426392 ps |
| CPU time | 3555.79 seconds |
| Started | Jun 28 08:29:04 PM PDT 24 |
| Finished | Jun 28 09:28:42 PM PDT 24 |
| Peak memory | 608348 kb |
| Host | smart-11990737-c32f-42be-b315-24dbef6b3dee |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=40_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=rom_e2e_keymgr_init_otp_meas:1: new_rules,otp_img_keymgr_otp_meas:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4097244843 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_e2e_keymgr_init_rom_ext_meas.4097244843 |
| Directory | /workspace/2.rom_e2e_keymgr_init_rom_ext_meas/latest |
| Test location | /workspace/coverage/default/2.rom_e2e_keymgr_init_rom_ext_no_meas.2967043622 |
| Short name | T1049 |
| Test name | |
| Test status | |
| Simulation time | 14424924200 ps |
| CPU time | 3978.17 seconds |
| Started | Jun 28 08:28:45 PM PDT 24 |
| Finished | Jun 28 09:35:23 PM PDT 24 |
| Peak memory | 608052 kb |
| Host | smart-5638f78d-cbf8-48a2-be73-3933e9685475 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=40_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=rom_e2e_keymgr_init_otp_no_meas :1:new_rules,otp_img_keymgr_otp_no_meas:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2967043622 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_e2e_keymgr_init_rom_ext _no_meas.2967043622 |
| Directory | /workspace/2.rom_e2e_keymgr_init_rom_ext_no_meas/latest |
| Test location | /workspace/coverage/default/2.rom_e2e_shutdown_exception_c.1976590687 |
| Short name | T1037 |
| Test name | |
| Test status | |
| Simulation time | 15077692654 ps |
| CPU time | 3771.54 seconds |
| Started | Jun 28 08:28:14 PM PDT 24 |
| Finished | Jun 28 09:31:09 PM PDT 24 |
| Peak memory | 607272 kb |
| Host | smart-4ababffe-78ce-4fd7-9b27-a03ce085a08e |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=40000000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=rom_e2e_shutdown_exception_c:1:ne w_rules,otp_img_secret2_locked_rma:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1976590687 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_e2e_shu tdown_exception_c_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_e2e_ shutdown_exception_c.1976590687 |
| Directory | /workspace/2.rom_e2e_shutdown_exception_c/latest |
| Test location | /workspace/coverage/default/2.rom_e2e_shutdown_output.4077817458 |
| Short name | T52 |
| Test name | |
| Test status | |
| Simulation time | 26430747720 ps |
| CPU time | 3477.98 seconds |
| Started | Jun 28 08:29:52 PM PDT 24 |
| Finished | Jun 28 09:28:03 PM PDT 24 |
| Peak memory | 609512 kb |
| Host | smart-9100a8ac-73e8-440f-8510-6cccd011bbf4 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=20000000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_unsigned:1:ot_f lash_binary,otp_img_shutdown_output_test_unlocked0:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4077817458 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chi p_sw_rom_e2e_shutdown_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_e2e_shutdown_output.4077817458 |
| Directory | /workspace/2.rom_e2e_shutdown_output/latest |
| Test location | /workspace/coverage/default/2.rom_e2e_smoke.1605099745 |
| Short name | T1187 |
| Test name | |
| Test status | |
| Simulation time | 14519760328 ps |
| CPU time | 4642.51 seconds |
| Started | Jun 28 08:26:08 PM PDT 24 |
| Finished | Jun 28 09:43:41 PM PDT 24 |
| Peak memory | 607928 kb |
| Host | smart-309a6949-ac25-4434-b291-6596bbd6a879 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=40000000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=rom_e2e_smoke:1:new_rules,otp_img _secret2_locked_rma:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_to p/hw/dv/tools/sim.tcl +ntb_random_seed=1605099745 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_e2e_smoke.1605099745 |
| Directory | /workspace/2.rom_e2e_smoke/latest |
| Test location | /workspace/coverage/default/2.rom_e2e_static_critical.3528083 |
| Short name | T913 |
| Test name | |
| Test status | |
| Simulation time | 17443210820 ps |
| CPU time | 3655.55 seconds |
| Started | Jun 28 08:28:45 PM PDT 24 |
| Finished | Jun 28 09:30:01 PM PDT 24 |
| Peak memory | 607264 kb |
| Host | smart-1536ebb5-3c58-4165-96fe-a7c1e2f89e8e |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=40000000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=rom_e2e_static_critical:1:new_rul es,otp_img_secret2_locked_rma:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3528083 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_e2e_static_critical.3528083 |
| Directory | /workspace/2.rom_e2e_static_critical/latest |
| Test location | /workspace/coverage/default/2.rom_keymgr_functest.2722908599 |
| Short name | T1086 |
| Test name | |
| Test status | |
| Simulation time | 3994237164 ps |
| CPU time | 474.03 seconds |
| Started | Jun 28 08:22:39 PM PDT 24 |
| Finished | Jun 28 08:30:35 PM PDT 24 |
| Peak memory | 609204 kb |
| Host | smart-0bebb119-3367-4bb5-aae4-cf2d0848eb92 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=10_000_000 +sw_build_device=sim_dv +sw_images=keymgr_functest:1:new_rules,test_rom:0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2722908599 -ass ert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 2.rom_keymgr_functest.2722908599 |
| Directory | /workspace/2.rom_keymgr_functest/latest |
| Test location | /workspace/coverage/default/2.rom_volatile_raw_unlock.3186616232 |
| Short name | T646 |
| Test name | |
| Test status | |
| Simulation time | 2677670533 ps |
| CPU time | 117.7 seconds |
| Started | Jun 28 08:30:17 PM PDT 24 |
| Finished | Jun 28 08:32:21 PM PDT 24 |
| Peak memory | 613404 kb |
| Host | smart-c484b0bf-b9ec-4914-8ada-8684f3d90d9f |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=200_000_000 +use_otp_image=OtpTypeLcStRaw +chip_clock_source=ChipClockSourceExternal48Mhz +rom_prod_mode=1 +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_test_key_0:1:ot_flash_binary,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3186616232 -assert nopostproc +UVM_ TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_volatile_raw_unlock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag e/default.vdb -cm_log /dev/null -cm_name 2.rom_volatile_raw_unlock.3186616232 |
| Directory | /workspace/2.rom_volatile_raw_unlock/latest |
| Test location | /workspace/coverage/default/20.chip_sw_alert_handler_lpg_sleep_mode_alerts.3962183323 |
| Short name | T718 |
| Test name | |
| Test status | |
| Simulation time | 3874011192 ps |
| CPU time | 395.05 seconds |
| Started | Jun 28 08:27:07 PM PDT 24 |
| Finished | Jun 28 08:33:43 PM PDT 24 |
| Peak memory | 646912 kb |
| Host | smart-ec484a25-bc2c-4d53-99c6-7d4466ad3661 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3962183323 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.chip_ sw_alert_handler_lpg_sleep_mode_alerts.3962183323 |
| Directory | /workspace/20.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/20.chip_sw_all_escalation_resets.326538491 |
| Short name | T754 |
| Test name | |
| Test status | |
| Simulation time | 5563746480 ps |
| CPU time | 571.24 seconds |
| Started | Jun 28 08:29:24 PM PDT 24 |
| Finished | Jun 28 08:39:03 PM PDT 24 |
| Peak memory | 643428 kb |
| Host | smart-fae81f2b-df0a-4dbc-b52b-bfc8beb1832e |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 326538491 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.chip_sw_all_escalation_resets.326538491 |
| Directory | /workspace/20.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/21.chip_sw_all_escalation_resets.1901039950 |
| Short name | T1035 |
| Test name | |
| Test status | |
| Simulation time | 6457063750 ps |
| CPU time | 884.53 seconds |
| Started | Jun 28 08:26:56 PM PDT 24 |
| Finished | Jun 28 08:41:41 PM PDT 24 |
| Peak memory | 617268 kb |
| Host | smart-29cc40fe-bb4e-42e1-b434-ed9ba5f7ca14 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 1901039950 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.chip_sw_all_escalation_resets.1901039950 |
| Directory | /workspace/21.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/23.chip_sw_all_escalation_resets.1785976869 |
| Short name | T681 |
| Test name | |
| Test status | |
| Simulation time | 4814966224 ps |
| CPU time | 564.49 seconds |
| Started | Jun 28 08:27:24 PM PDT 24 |
| Finished | Jun 28 08:36:50 PM PDT 24 |
| Peak memory | 647840 kb |
| Host | smart-29a5fe3a-c951-444a-a8e0-79480a30b359 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 1785976869 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.chip_sw_all_escalation_resets.1785976869 |
| Directory | /workspace/23.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/25.chip_sw_alert_handler_lpg_sleep_mode_alerts.1115404265 |
| Short name | T685 |
| Test name | |
| Test status | |
| Simulation time | 3621113600 ps |
| CPU time | 414.64 seconds |
| Started | Jun 28 08:27:22 PM PDT 24 |
| Finished | Jun 28 08:34:18 PM PDT 24 |
| Peak memory | 642612 kb |
| Host | smart-5c136377-0adb-47b0-aefa-b351b40ce9f2 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1115404265 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.chip_ sw_alert_handler_lpg_sleep_mode_alerts.1115404265 |
| Directory | /workspace/25.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/26.chip_sw_alert_handler_lpg_sleep_mode_alerts.3441121490 |
| Short name | T698 |
| Test name | |
| Test status | |
| Simulation time | 4243914120 ps |
| CPU time | 469.95 seconds |
| Started | Jun 28 08:30:22 PM PDT 24 |
| Finished | Jun 28 08:38:18 PM PDT 24 |
| Peak memory | 642140 kb |
| Host | smart-0d2e4301-2f8b-48f1-aa4f-8a97096eb558 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3441121490 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.chip_ sw_alert_handler_lpg_sleep_mode_alerts.3441121490 |
| Directory | /workspace/26.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/28.chip_sw_alert_handler_lpg_sleep_mode_alerts.656987623 |
| Short name | T727 |
| Test name | |
| Test status | |
| Simulation time | 3621708022 ps |
| CPU time | 434.54 seconds |
| Started | Jun 28 08:28:10 PM PDT 24 |
| Finished | Jun 28 08:35:27 PM PDT 24 |
| Peak memory | 642460 kb |
| Host | smart-40c64267-f9b9-4a2d-9cd1-d367c70e05be |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=656987623 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all _escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.chip_s w_alert_handler_lpg_sleep_mode_alerts.656987623 |
| Directory | /workspace/28.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/29.chip_sw_alert_handler_lpg_sleep_mode_alerts.3431309850 |
| Short name | T753 |
| Test name | |
| Test status | |
| Simulation time | 4060246056 ps |
| CPU time | 492.82 seconds |
| Started | Jun 28 08:28:10 PM PDT 24 |
| Finished | Jun 28 08:36:26 PM PDT 24 |
| Peak memory | 646992 kb |
| Host | smart-caf47332-08d4-415f-b6f5-c8e541c85345 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3431309850 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.chip_ sw_alert_handler_lpg_sleep_mode_alerts.3431309850 |
| Directory | /workspace/29.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/3.chip_sw_all_escalation_resets.3275729245 |
| Short name | T775 |
| Test name | |
| Test status | |
| Simulation time | 5896789076 ps |
| CPU time | 844.21 seconds |
| Started | Jun 28 08:24:09 PM PDT 24 |
| Finished | Jun 28 08:38:20 PM PDT 24 |
| Peak memory | 643424 kb |
| Host | smart-25826449-a2b5-4e06-a8c9-8d6bdc8c3360 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 3275729245 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.chip_sw_all_escalation_resets.3275729245 |
| Directory | /workspace/3.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/3.chip_sw_aon_timer_sleep_wdog_sleep_pause.1456890144 |
| Short name | T873 |
| Test name | |
| Test status | |
| Simulation time | 7202601080 ps |
| CPU time | 474.09 seconds |
| Started | Jun 28 08:24:33 PM PDT 24 |
| Finished | Jun 28 08:32:33 PM PDT 24 |
| Peak memory | 609268 kb |
| Host | smart-cdf68350-315a-4f8a-9866-a704fd5e867e |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=aon_timer_sleep_wdog_sleep_pause_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=1456890144 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.chip_sw_aon_timer_sleep_wdog_sleep_pause.1456890144 |
| Directory | /workspace/3.chip_sw_aon_timer_sleep_wdog_sleep_pause/latest |
| Test location | /workspace/coverage/default/3.chip_sw_csrng_edn_concurrency.162524100 |
| Short name | T956 |
| Test name | |
| Test status | |
| Simulation time | 9918959454 ps |
| CPU time | 2335.35 seconds |
| Started | Jun 28 08:25:04 PM PDT 24 |
| Finished | Jun 28 09:04:03 PM PDT 24 |
| Peak memory | 608416 kb |
| Host | smart-2ad6cb18-ecf4-4c39-ad04-06074adfd74c |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=140_000_000 +rng_srate_value_min=15 +rng_srate_value_max=20 +accelerate_cold_power_up_time=3 +accelerate_r egulators_power_up_time=2 +sw_build_device=sim_dv +sw_images=csrng_edn_concurrency_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=162524100 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.chip_sw_csrng_edn_concurrency.162524100 |
| Directory | /workspace/3.chip_sw_csrng_edn_concurrency/latest |
| Test location | /workspace/coverage/default/3.chip_sw_data_integrity_escalation.2201022696 |
| Short name | T1065 |
| Test name | |
| Test status | |
| Simulation time | 5605846614 ps |
| CPU time | 623.58 seconds |
| Started | Jun 28 08:23:14 PM PDT 24 |
| Finished | Jun 28 08:33:48 PM PDT 24 |
| Peak memory | 608476 kb |
| Host | smart-7c97ad05-6dd7-4920-8b0f-af56ee3517a4 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=data_integrity_escalation_reset_test:1:new_rules,test_ro m:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=2201022696 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_data_integrity_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.chip_sw_data_integrity_escalation.2201022696 |
| Directory | /workspace/3.chip_sw_data_integrity_escalation/latest |
| Test location | /workspace/coverage/default/3.chip_sw_lc_ctrl_transition.2773421521 |
| Short name | T1176 |
| Test name | |
| Test status | |
| Simulation time | 6813570068 ps |
| CPU time | 493.39 seconds |
| Started | Jun 28 08:25:16 PM PDT 24 |
| Finished | Jun 28 08:33:36 PM PDT 24 |
| Peak memory | 619188 kb |
| Host | smart-ad57076d-ea6a-4a39-853e-3355a68d12bf |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=lc_ctrl_transition_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2773421521 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_transition_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau lt.vdb -cm_log /dev/null -cm_name 3.chip_sw_lc_ctrl_transition.2773421521 |
| Directory | /workspace/3.chip_sw_lc_ctrl_transition/latest |
| Test location | /workspace/coverage/default/3.chip_sw_sensor_ctrl_alert.3624032352 |
| Short name | T123 |
| Test name | |
| Test status | |
| Simulation time | 6799465182 ps |
| CPU time | 853.26 seconds |
| Started | Jun 28 08:24:01 PM PDT 24 |
| Finished | Jun 28 08:38:17 PM PDT 24 |
| Peak memory | 608256 kb |
| Host | smart-cdeda3bc-7770-4089-9859-29d47aa54acf |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=40_000_000 +sw_build_device=sim_dv +sw_images=sensor_ctrl_alert_test:1:new_rules,test_rom:0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36240323 52 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac e/coverage/default.vdb -cm_log /dev/null -cm_name 3.chip_sw_sensor_ctrl_alert.3624032352 |
| Directory | /workspace/3.chip_sw_sensor_ctrl_alert/latest |
| Test location | /workspace/coverage/default/3.chip_sw_uart_rand_baudrate.4216811107 |
| Short name | T29 |
| Test name | |
| Test status | |
| Simulation time | 4029479620 ps |
| CPU time | 661.11 seconds |
| Started | Jun 28 08:23:53 PM PDT 24 |
| Finished | Jun 28 08:34:56 PM PDT 24 |
| Peak memory | 618892 kb |
| Host | smart-837dce51-aa7a-46f5-8b91-526c690ab5b5 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=4216811107 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.chip_sw_uart_rand_baudrate.4216811107 |
| Directory | /workspace/3.chip_sw_uart_rand_baudrate/latest |
| Test location | /workspace/coverage/default/3.chip_sw_uart_tx_rx.391538564 |
| Short name | T961 |
| Test name | |
| Test status | |
| Simulation time | 4439131700 ps |
| CPU time | 677.86 seconds |
| Started | Jun 28 08:24:38 PM PDT 24 |
| Finished | Jun 28 08:36:01 PM PDT 24 |
| Peak memory | 623984 kb |
| Host | smart-2608003a-46cc-47e5-bda6-264501035f4d |
| User | root |
| Command | /workspace/default/simv +uart_idx=0 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=391538564 -as sert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac e/coverage/default.vdb -cm_log /dev/null -cm_name 3.chip_sw_uart_tx_rx.391538564 |
| Directory | /workspace/3.chip_sw_uart_tx_rx/latest |
| Test location | /workspace/coverage/default/3.chip_sw_uart_tx_rx_alt_clk_freq.3108945756 |
| Short name | T1050 |
| Test name | |
| Test status | |
| Simulation time | 3530375261 ps |
| CPU time | 517.98 seconds |
| Started | Jun 28 08:27:10 PM PDT 24 |
| Finished | Jun 28 08:35:50 PM PDT 24 |
| Peak memory | 617620 kb |
| Host | smart-9f3c5ffa-2e00-4e08-82c3-2152e69abf1c |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=80_000_000 +chip_clock_source=ChipClockSourceExternal96Mhz +calibrate_usb_clk=1 +sw_build_device=sim_dv +s w_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3108945756 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_b audrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.chip_sw_uart_tx_rx _alt_clk_freq.3108945756 |
| Directory | /workspace/3.chip_sw_uart_tx_rx_alt_clk_freq/latest |
| Test location | /workspace/coverage/default/3.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.2728214514 |
| Short name | T1094 |
| Test name | |
| Test status | |
| Simulation time | 3817783946 ps |
| CPU time | 493.95 seconds |
| Started | Jun 28 08:27:22 PM PDT 24 |
| Finished | Jun 28 08:35:38 PM PDT 24 |
| Peak memory | 617608 kb |
| Host | smart-f317aa6e-e892-4820-8ad5-86d3b5dc027d |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +chip_clock_source=ChipClockSourceExternal48Mhz +sw_build_device=sim_dv +s w_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2728214514 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_b audrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.chip_sw_uart_tx_rx _alt_clk_freq_low_speed.2728214514 |
| Directory | /workspace/3.chip_sw_uart_tx_rx_alt_clk_freq_low_speed/latest |
| Test location | /workspace/coverage/default/3.chip_sw_uart_tx_rx_idx1.1718923934 |
| Short name | T1136 |
| Test name | |
| Test status | |
| Simulation time | 4454548136 ps |
| CPU time | 686.56 seconds |
| Started | Jun 28 08:22:57 PM PDT 24 |
| Finished | Jun 28 08:34:28 PM PDT 24 |
| Peak memory | 615888 kb |
| Host | smart-9579ccb9-597a-4275-8107-667233659269 |
| User | root |
| Command | /workspace/default/simv +uart_idx=1 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1718923934 -a ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/default.vdb -cm_log /dev/null -cm_name 3.chip_sw_uart_tx_rx_idx1.1718923934 |
| Directory | /workspace/3.chip_sw_uart_tx_rx_idx1/latest |
| Test location | /workspace/coverage/default/3.chip_sw_uart_tx_rx_idx2.2468958235 |
| Short name | T1022 |
| Test name | |
| Test status | |
| Simulation time | 4944495020 ps |
| CPU time | 572.57 seconds |
| Started | Jun 28 08:24:18 PM PDT 24 |
| Finished | Jun 28 08:33:58 PM PDT 24 |
| Peak memory | 624044 kb |
| Host | smart-7ba759b4-ff18-4412-a9cc-7628daa98187 |
| User | root |
| Command | /workspace/default/simv +uart_idx=2 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2468958235 -a ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/default.vdb -cm_log /dev/null -cm_name 3.chip_sw_uart_tx_rx_idx2.2468958235 |
| Directory | /workspace/3.chip_sw_uart_tx_rx_idx2/latest |
| Test location | /workspace/coverage/default/3.chip_sw_uart_tx_rx_idx3.3636744622 |
| Short name | T1298 |
| Test name | |
| Test status | |
| Simulation time | 3815986910 ps |
| CPU time | 598.14 seconds |
| Started | Jun 28 08:23:51 PM PDT 24 |
| Finished | Jun 28 08:33:51 PM PDT 24 |
| Peak memory | 615884 kb |
| Host | smart-645c2b5a-6323-45f9-ac70-163e74e5129d |
| User | root |
| Command | /workspace/default/simv +uart_idx=3 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3636744622 -a ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/default.vdb -cm_log /dev/null -cm_name 3.chip_sw_uart_tx_rx_idx3.3636744622 |
| Directory | /workspace/3.chip_sw_uart_tx_rx_idx3/latest |
| Test location | /workspace/coverage/default/3.chip_tap_straps_dev.1001356656 |
| Short name | T1150 |
| Test name | |
| Test status | |
| Simulation time | 17993730702 ps |
| CPU time | 1895.57 seconds |
| Started | Jun 28 08:23:12 PM PDT 24 |
| Finished | Jun 28 08:54:58 PM PDT 24 |
| Peak memory | 618224 kb |
| Host | smart-e1b0c9a1-be9b-4ed7-bf69-4e424b26a0c7 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStDev +create_jtag_riscv_map=1 +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:test_in_rom: new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=1001356656 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_tap_straps_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.chip_tap_straps_dev.1001356656 |
| Directory | /workspace/3.chip_tap_straps_dev/latest |
| Test location | /workspace/coverage/default/3.chip_tap_straps_prod.1863599695 |
| Short name | T68 |
| Test name | |
| Test status | |
| Simulation time | 7987020089 ps |
| CPU time | 793.15 seconds |
| Started | Jun 28 08:22:35 PM PDT 24 |
| Finished | Jun 28 08:35:49 PM PDT 24 |
| Peak memory | 620324 kb |
| Host | smart-b4bb4e39-3efe-43c3-90e8-5b31b74ba736 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStProd +create_jtag_riscv_map=1 +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:test_in_rom :new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1863599695 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_tap_straps_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.chip_tap_straps_prod.1863599695 |
| Directory | /workspace/3.chip_tap_straps_prod/latest |
| Test location | /workspace/coverage/default/3.chip_tap_straps_testunlock0.795328974 |
| Short name | T65 |
| Test name | |
| Test status | |
| Simulation time | 4350535533 ps |
| CPU time | 352.73 seconds |
| Started | Jun 28 08:23:10 PM PDT 24 |
| Finished | Jun 28 08:29:11 PM PDT 24 |
| Peak memory | 620348 kb |
| Host | smart-b5db3e10-fb27-46aa-a9c5-48ff59d7f9c9 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStTestUnlocked0 +create_jtag_riscv_map=1 +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:te st_in_rom:new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=795328974 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_tap_straps_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.chip_tap_straps_testunlock0.795328974 |
| Directory | /workspace/3.chip_tap_straps_testunlock0/latest |
| Test location | /workspace/coverage/default/30.chip_sw_alert_handler_lpg_sleep_mode_alerts.1657823402 |
| Short name | T368 |
| Test name | |
| Test status | |
| Simulation time | 3887567912 ps |
| CPU time | 383.47 seconds |
| Started | Jun 28 08:26:51 PM PDT 24 |
| Finished | Jun 28 08:33:15 PM PDT 24 |
| Peak memory | 642212 kb |
| Host | smart-0505075e-7952-42fe-b80b-448ed192d3c1 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1657823402 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.chip_ sw_alert_handler_lpg_sleep_mode_alerts.1657823402 |
| Directory | /workspace/30.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/31.chip_sw_all_escalation_resets.1209692598 |
| Short name | T749 |
| Test name | |
| Test status | |
| Simulation time | 4761339960 ps |
| CPU time | 659.02 seconds |
| Started | Jun 28 08:28:21 PM PDT 24 |
| Finished | Jun 28 08:39:22 PM PDT 24 |
| Peak memory | 643456 kb |
| Host | smart-97084866-0ac4-4d4d-b0a6-f490e093d464 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 1209692598 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.chip_sw_all_escalation_resets.1209692598 |
| Directory | /workspace/31.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/32.chip_sw_alert_handler_lpg_sleep_mode_alerts.2212471899 |
| Short name | T695 |
| Test name | |
| Test status | |
| Simulation time | 3933139156 ps |
| CPU time | 398.93 seconds |
| Started | Jun 28 08:29:42 PM PDT 24 |
| Finished | Jun 28 08:36:31 PM PDT 24 |
| Peak memory | 647328 kb |
| Host | smart-2bc390bc-d8b6-4aec-98d8-3e229f71989c |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2212471899 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.chip_ sw_alert_handler_lpg_sleep_mode_alerts.2212471899 |
| Directory | /workspace/32.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/34.chip_sw_all_escalation_resets.2393304124 |
| Short name | T1297 |
| Test name | |
| Test status | |
| Simulation time | 4991424068 ps |
| CPU time | 628.35 seconds |
| Started | Jun 28 08:29:15 PM PDT 24 |
| Finished | Jun 28 08:39:58 PM PDT 24 |
| Peak memory | 643440 kb |
| Host | smart-3738246d-f9b7-4b5b-a169-42da3ed6191b |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 2393304124 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.chip_sw_all_escalation_resets.2393304124 |
| Directory | /workspace/34.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/35.chip_sw_alert_handler_lpg_sleep_mode_alerts.4050068781 |
| Short name | T729 |
| Test name | |
| Test status | |
| Simulation time | 3316761384 ps |
| CPU time | 416.13 seconds |
| Started | Jun 28 08:29:45 PM PDT 24 |
| Finished | Jun 28 08:36:52 PM PDT 24 |
| Peak memory | 647024 kb |
| Host | smart-36d89844-c7b9-4e29-b9e5-80a8d8bf1be1 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4050068781 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.chip_ sw_alert_handler_lpg_sleep_mode_alerts.4050068781 |
| Directory | /workspace/35.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/36.chip_sw_alert_handler_lpg_sleep_mode_alerts.2122396574 |
| Short name | T771 |
| Test name | |
| Test status | |
| Simulation time | 3462942192 ps |
| CPU time | 368.37 seconds |
| Started | Jun 28 08:29:38 PM PDT 24 |
| Finished | Jun 28 08:35:57 PM PDT 24 |
| Peak memory | 647168 kb |
| Host | smart-5551faaf-1acd-4e4e-8447-498d78042214 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2122396574 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.chip_ sw_alert_handler_lpg_sleep_mode_alerts.2122396574 |
| Directory | /workspace/36.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/37.chip_sw_all_escalation_resets.4148647303 |
| Short name | T1003 |
| Test name | |
| Test status | |
| Simulation time | 5715637320 ps |
| CPU time | 654.44 seconds |
| Started | Jun 28 08:27:20 PM PDT 24 |
| Finished | Jun 28 08:38:16 PM PDT 24 |
| Peak memory | 643304 kb |
| Host | smart-c87698f4-f5ec-44f0-bc16-720396bd8637 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 4148647303 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.chip_sw_all_escalation_resets.4148647303 |
| Directory | /workspace/37.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/38.chip_sw_alert_handler_lpg_sleep_mode_alerts.1594735976 |
| Short name | T669 |
| Test name | |
| Test status | |
| Simulation time | 3634062450 ps |
| CPU time | 397.59 seconds |
| Started | Jun 28 08:31:48 PM PDT 24 |
| Finished | Jun 28 08:38:38 PM PDT 24 |
| Peak memory | 646968 kb |
| Host | smart-d314e45d-d8e8-4a18-8847-d80ca83825d0 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1594735976 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.chip_ sw_alert_handler_lpg_sleep_mode_alerts.1594735976 |
| Directory | /workspace/38.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/39.chip_sw_alert_handler_lpg_sleep_mode_alerts.2072404056 |
| Short name | T694 |
| Test name | |
| Test status | |
| Simulation time | 4170878168 ps |
| CPU time | 393.75 seconds |
| Started | Jun 28 08:28:26 PM PDT 24 |
| Finished | Jun 28 08:35:01 PM PDT 24 |
| Peak memory | 646968 kb |
| Host | smart-90ceee75-9819-4ea5-b20c-286fb7aec996 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2072404056 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.chip_ sw_alert_handler_lpg_sleep_mode_alerts.2072404056 |
| Directory | /workspace/39.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/39.chip_sw_all_escalation_resets.1764668031 |
| Short name | T1109 |
| Test name | |
| Test status | |
| Simulation time | 6135045892 ps |
| CPU time | 666.06 seconds |
| Started | Jun 28 08:30:30 PM PDT 24 |
| Finished | Jun 28 08:41:43 PM PDT 24 |
| Peak memory | 643320 kb |
| Host | smart-516247fc-e611-45d1-a484-2721c0955db5 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 1764668031 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.chip_sw_all_escalation_resets.1764668031 |
| Directory | /workspace/39.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/4.chip_sw_alert_handler_lpg_sleep_mode_alerts.4185886994 |
| Short name | T693 |
| Test name | |
| Test status | |
| Simulation time | 4297951118 ps |
| CPU time | 590.92 seconds |
| Started | Jun 28 08:26:07 PM PDT 24 |
| Finished | Jun 28 08:36:09 PM PDT 24 |
| Peak memory | 642500 kb |
| Host | smart-1acb1d5a-fe5a-4883-a7a0-ce48a44a4ec8 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4185886994 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.chip_s w_alert_handler_lpg_sleep_mode_alerts.4185886994 |
| Directory | /workspace/4.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/4.chip_sw_aon_timer_sleep_wdog_sleep_pause.1763793072 |
| Short name | T1286 |
| Test name | |
| Test status | |
| Simulation time | 7182701396 ps |
| CPU time | 616.39 seconds |
| Started | Jun 28 08:23:48 PM PDT 24 |
| Finished | Jun 28 08:34:06 PM PDT 24 |
| Peak memory | 609260 kb |
| Host | smart-3a96664d-448a-49f5-9dd1-7e2b784591f1 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=aon_timer_sleep_wdog_sleep_pause_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=1763793072 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.chip_sw_aon_timer_sleep_wdog_sleep_pause.1763793072 |
| Directory | /workspace/4.chip_sw_aon_timer_sleep_wdog_sleep_pause/latest |
| Test location | /workspace/coverage/default/4.chip_sw_csrng_edn_concurrency.3455524990 |
| Short name | T628 |
| Test name | |
| Test status | |
| Simulation time | 17902870004 ps |
| CPU time | 4110.92 seconds |
| Started | Jun 28 08:23:39 PM PDT 24 |
| Finished | Jun 28 09:32:12 PM PDT 24 |
| Peak memory | 608456 kb |
| Host | smart-35d5a6d8-ef3e-4bab-bc1e-28f87e2f1e57 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=140_000_000 +rng_srate_value_min=15 +rng_srate_value_max=20 +accelerate_cold_power_up_time=3 +accelerate_r egulators_power_up_time=2 +sw_build_device=sim_dv +sw_images=csrng_edn_concurrency_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3455524990 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd b -cm_log /dev/null -cm_name 4.chip_sw_csrng_edn_concurrency.3455524990 |
| Directory | /workspace/4.chip_sw_csrng_edn_concurrency/latest |
| Test location | /workspace/coverage/default/4.chip_sw_data_integrity_escalation.820925678 |
| Short name | T278 |
| Test name | |
| Test status | |
| Simulation time | 4905573944 ps |
| CPU time | 738.01 seconds |
| Started | Jun 28 08:26:13 PM PDT 24 |
| Finished | Jun 28 08:38:41 PM PDT 24 |
| Peak memory | 609272 kb |
| Host | smart-b6cc9245-8a93-42ec-9087-ae58c60ceea6 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=data_integrity_escalation_reset_test:1:new_rules,test_ro m:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=820925678 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_data_integrity_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.chip_sw_data_integrity_escalation.820925678 |
| Directory | /workspace/4.chip_sw_data_integrity_escalation/latest |
| Test location | /workspace/coverage/default/4.chip_sw_lc_ctrl_transition.782023483 |
| Short name | T180 |
| Test name | |
| Test status | |
| Simulation time | 5281620711 ps |
| CPU time | 500.41 seconds |
| Started | Jun 28 08:25:33 PM PDT 24 |
| Finished | Jun 28 08:33:54 PM PDT 24 |
| Peak memory | 618996 kb |
| Host | smart-f5949c71-37c2-45e5-bf77-ff660df2e185 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=lc_ctrl_transition_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=782023483 -assert nopostproc +UVM_TEST NAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_transition_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul t.vdb -cm_log /dev/null -cm_name 4.chip_sw_lc_ctrl_transition.782023483 |
| Directory | /workspace/4.chip_sw_lc_ctrl_transition/latest |
| Test location | /workspace/coverage/default/4.chip_sw_sensor_ctrl_alert.3788103244 |
| Short name | T124 |
| Test name | |
| Test status | |
| Simulation time | 7335709264 ps |
| CPU time | 728.38 seconds |
| Started | Jun 28 08:23:32 PM PDT 24 |
| Finished | Jun 28 08:35:41 PM PDT 24 |
| Peak memory | 608920 kb |
| Host | smart-16138bd6-dbc5-49e7-a187-4580af841944 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=40_000_000 +sw_build_device=sim_dv +sw_images=sensor_ctrl_alert_test:1:new_rules,test_rom:0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37881032 44 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac e/coverage/default.vdb -cm_log /dev/null -cm_name 4.chip_sw_sensor_ctrl_alert.3788103244 |
| Directory | /workspace/4.chip_sw_sensor_ctrl_alert/latest |
| Test location | /workspace/coverage/default/4.chip_sw_uart_rand_baudrate.2877971973 |
| Short name | T1099 |
| Test name | |
| Test status | |
| Simulation time | 13013605010 ps |
| CPU time | 2559.35 seconds |
| Started | Jun 28 08:25:55 PM PDT 24 |
| Finished | Jun 28 09:08:38 PM PDT 24 |
| Peak memory | 618324 kb |
| Host | smart-7ff40e32-4595-43da-9ef2-daadc7208362 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=2877971973 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.chip_sw_uart_rand_baudrate.2877971973 |
| Directory | /workspace/4.chip_sw_uart_rand_baudrate/latest |
| Test location | /workspace/coverage/default/4.chip_sw_uart_tx_rx.1819245602 |
| Short name | T306 |
| Test name | |
| Test status | |
| Simulation time | 4386636280 ps |
| CPU time | 674.98 seconds |
| Started | Jun 28 08:23:12 PM PDT 24 |
| Finished | Jun 28 08:34:37 PM PDT 24 |
| Peak memory | 615836 kb |
| Host | smart-60ff6424-cb97-4be0-94a4-fb0593875331 |
| User | root |
| Command | /workspace/default/simv +uart_idx=0 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1819245602 -a ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/default.vdb -cm_log /dev/null -cm_name 4.chip_sw_uart_tx_rx.1819245602 |
| Directory | /workspace/4.chip_sw_uart_tx_rx/latest |
| Test location | /workspace/coverage/default/4.chip_sw_uart_tx_rx_alt_clk_freq.834938706 |
| Short name | T1130 |
| Test name | |
| Test status | |
| Simulation time | 4238599652 ps |
| CPU time | 731.24 seconds |
| Started | Jun 28 08:23:35 PM PDT 24 |
| Finished | Jun 28 08:35:49 PM PDT 24 |
| Peak memory | 620408 kb |
| Host | smart-92ac7335-ae27-4dd9-8eb9-d81a1d9c9c24 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=80_000_000 +chip_clock_source=ChipClockSourceExternal96Mhz +calibrate_usb_clk=1 +sw_build_device=sim_dv +s w_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=834938706 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_ba udrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.chip_sw_uart_tx_rx_ alt_clk_freq.834938706 |
| Directory | /workspace/4.chip_sw_uart_tx_rx_alt_clk_freq/latest |
| Test location | /workspace/coverage/default/4.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.191675543 |
| Short name | T1141 |
| Test name | |
| Test status | |
| Simulation time | 13285472283 ps |
| CPU time | 1619.17 seconds |
| Started | Jun 28 08:24:43 PM PDT 24 |
| Finished | Jun 28 08:51:44 PM PDT 24 |
| Peak memory | 617644 kb |
| Host | smart-42c54f5f-ffaf-4a7e-8f3f-437268475bd2 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +chip_clock_source=ChipClockSourceExternal48Mhz +sw_build_device=sim_dv +s w_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=191675543 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_ba udrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.chip_sw_uart_tx_rx_ alt_clk_freq_low_speed.191675543 |
| Directory | /workspace/4.chip_sw_uart_tx_rx_alt_clk_freq_low_speed/latest |
| Test location | /workspace/coverage/default/4.chip_sw_uart_tx_rx_idx1.3779609548 |
| Short name | T329 |
| Test name | |
| Test status | |
| Simulation time | 4604337812 ps |
| CPU time | 569.83 seconds |
| Started | Jun 28 08:24:54 PM PDT 24 |
| Finished | Jun 28 08:34:26 PM PDT 24 |
| Peak memory | 615860 kb |
| Host | smart-21a1c475-1e18-483e-b5b9-b3b6a474ef97 |
| User | root |
| Command | /workspace/default/simv +uart_idx=1 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3779609548 -a ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/default.vdb -cm_log /dev/null -cm_name 4.chip_sw_uart_tx_rx_idx1.3779609548 |
| Directory | /workspace/4.chip_sw_uart_tx_rx_idx1/latest |
| Test location | /workspace/coverage/default/4.chip_sw_uart_tx_rx_idx2.543630675 |
| Short name | T1016 |
| Test name | |
| Test status | |
| Simulation time | 4086870152 ps |
| CPU time | 655.6 seconds |
| Started | Jun 28 08:23:27 PM PDT 24 |
| Finished | Jun 28 08:34:24 PM PDT 24 |
| Peak memory | 615836 kb |
| Host | smart-096dcb66-0a29-4fe5-a9c5-9fa0bf9db597 |
| User | root |
| Command | /workspace/default/simv +uart_idx=2 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=543630675 -as sert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac e/coverage/default.vdb -cm_log /dev/null -cm_name 4.chip_sw_uart_tx_rx_idx2.543630675 |
| Directory | /workspace/4.chip_sw_uart_tx_rx_idx2/latest |
| Test location | /workspace/coverage/default/4.chip_sw_uart_tx_rx_idx3.3479411425 |
| Short name | T1135 |
| Test name | |
| Test status | |
| Simulation time | 4674505716 ps |
| CPU time | 631.5 seconds |
| Started | Jun 28 08:24:59 PM PDT 24 |
| Finished | Jun 28 08:35:33 PM PDT 24 |
| Peak memory | 624044 kb |
| Host | smart-bb289967-8b62-4af4-a9c6-ce1927c98c18 |
| User | root |
| Command | /workspace/default/simv +uart_idx=3 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3479411425 -a ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/default.vdb -cm_log /dev/null -cm_name 4.chip_sw_uart_tx_rx_idx3.3479411425 |
| Directory | /workspace/4.chip_sw_uart_tx_rx_idx3/latest |
| Test location | /workspace/coverage/default/4.chip_tap_straps_dev.787360158 |
| Short name | T418 |
| Test name | |
| Test status | |
| Simulation time | 2682257675 ps |
| CPU time | 163.37 seconds |
| Started | Jun 28 08:23:34 PM PDT 24 |
| Finished | Jun 28 08:26:18 PM PDT 24 |
| Peak memory | 617992 kb |
| Host | smart-4e74ada8-45a9-4a25-8a0d-fa00b3e3217e |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStDev +create_jtag_riscv_map=1 +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:test_in_rom: new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=787360158 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_tap_straps_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.chip_tap_straps_dev.787360158 |
| Directory | /workspace/4.chip_tap_straps_dev/latest |
| Test location | /workspace/coverage/default/4.chip_tap_straps_rma.763387424 |
| Short name | T66 |
| Test name | |
| Test status | |
| Simulation time | 3862725160 ps |
| CPU time | 264.9 seconds |
| Started | Jun 28 08:23:56 PM PDT 24 |
| Finished | Jun 28 08:28:23 PM PDT 24 |
| Peak memory | 620044 kb |
| Host | smart-20057a63-68c1-4e37-ac1e-8f91c68e31d4 |
| User | root |
| Command | /workspace/default/simv +create_jtag_riscv_map=1 +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:test_in_rom:new_rules +cdc_instrumentation _enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=763387424 -ass ert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_tap_straps_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co verage/default.vdb -cm_log /dev/null -cm_name 4.chip_tap_straps_rma.763387424 |
| Directory | /workspace/4.chip_tap_straps_rma/latest |
| Test location | /workspace/coverage/default/4.chip_tap_straps_testunlock0.50808419 |
| Short name | T973 |
| Test name | |
| Test status | |
| Simulation time | 3736343795 ps |
| CPU time | 306.41 seconds |
| Started | Jun 28 08:24:31 PM PDT 24 |
| Finished | Jun 28 08:29:44 PM PDT 24 |
| Peak memory | 619584 kb |
| Host | smart-e47f6ba8-b7bf-491d-9387-c7045db29ac2 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStTestUnlocked0 +create_jtag_riscv_map=1 +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:te st_in_rom:new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=50808419 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_tap_straps_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.chip_tap_straps_testunlock0.50808419 |
| Directory | /workspace/4.chip_tap_straps_testunlock0/latest |
| Test location | /workspace/coverage/default/43.chip_sw_alert_handler_lpg_sleep_mode_alerts.3170860728 |
| Short name | T723 |
| Test name | |
| Test status | |
| Simulation time | 3503566650 ps |
| CPU time | 495.44 seconds |
| Started | Jun 28 08:33:58 PM PDT 24 |
| Finished | Jun 28 08:42:22 PM PDT 24 |
| Peak memory | 642224 kb |
| Host | smart-a75c8cfe-d02e-4e81-b428-6cb41cf94c29 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3170860728 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.chip_ sw_alert_handler_lpg_sleep_mode_alerts.3170860728 |
| Directory | /workspace/43.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/43.chip_sw_all_escalation_resets.498260857 |
| Short name | T1122 |
| Test name | |
| Test status | |
| Simulation time | 5728074372 ps |
| CPU time | 822.63 seconds |
| Started | Jun 28 08:29:10 PM PDT 24 |
| Finished | Jun 28 08:43:11 PM PDT 24 |
| Peak memory | 643296 kb |
| Host | smart-abedeacb-e947-4c25-92b4-602067dcce81 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 498260857 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.chip_sw_all_escalation_resets.498260857 |
| Directory | /workspace/43.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/44.chip_sw_alert_handler_lpg_sleep_mode_alerts.2306817318 |
| Short name | T742 |
| Test name | |
| Test status | |
| Simulation time | 3426345910 ps |
| CPU time | 452.95 seconds |
| Started | Jun 28 08:33:30 PM PDT 24 |
| Finished | Jun 28 08:41:06 PM PDT 24 |
| Peak memory | 642196 kb |
| Host | smart-cb4b2324-a3df-4537-8f64-0a8d7c843465 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2306817318 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.chip_ sw_alert_handler_lpg_sleep_mode_alerts.2306817318 |
| Directory | /workspace/44.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/44.chip_sw_all_escalation_resets.1520523476 |
| Short name | T690 |
| Test name | |
| Test status | |
| Simulation time | 5929296808 ps |
| CPU time | 752.31 seconds |
| Started | Jun 28 08:28:52 PM PDT 24 |
| Finished | Jun 28 08:41:49 PM PDT 24 |
| Peak memory | 647968 kb |
| Host | smart-495a04e8-ec71-4b03-af2f-4a3df8f9bff2 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 1520523476 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.chip_sw_all_escalation_resets.1520523476 |
| Directory | /workspace/44.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/45.chip_sw_alert_handler_lpg_sleep_mode_alerts.3505190621 |
| Short name | T752 |
| Test name | |
| Test status | |
| Simulation time | 4429825788 ps |
| CPU time | 482.61 seconds |
| Started | Jun 28 08:29:08 PM PDT 24 |
| Finished | Jun 28 08:37:30 PM PDT 24 |
| Peak memory | 647292 kb |
| Host | smart-73b28d15-328d-47ad-a69a-68ef37cc20c8 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3505190621 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.chip_ sw_alert_handler_lpg_sleep_mode_alerts.3505190621 |
| Directory | /workspace/45.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/45.chip_sw_all_escalation_resets.2752085232 |
| Short name | T765 |
| Test name | |
| Test status | |
| Simulation time | 4989594680 ps |
| CPU time | 847 seconds |
| Started | Jun 28 08:30:46 PM PDT 24 |
| Finished | Jun 28 08:44:56 PM PDT 24 |
| Peak memory | 643504 kb |
| Host | smart-942c9937-3c18-4ef2-a8a6-516d1a8143eb |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 2752085232 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.chip_sw_all_escalation_resets.2752085232 |
| Directory | /workspace/45.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/46.chip_sw_alert_handler_lpg_sleep_mode_alerts.1016622505 |
| Short name | T667 |
| Test name | |
| Test status | |
| Simulation time | 4183101816 ps |
| CPU time | 478.84 seconds |
| Started | Jun 28 08:28:49 PM PDT 24 |
| Finished | Jun 28 08:37:08 PM PDT 24 |
| Peak memory | 647168 kb |
| Host | smart-e11d9538-acc3-4fe6-922b-c5fa5b7c9628 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1016622505 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.chip_ sw_alert_handler_lpg_sleep_mode_alerts.1016622505 |
| Directory | /workspace/46.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/47.chip_sw_all_escalation_resets.2123824733 |
| Short name | T701 |
| Test name | |
| Test status | |
| Simulation time | 4348398776 ps |
| CPU time | 618.68 seconds |
| Started | Jun 28 08:30:47 PM PDT 24 |
| Finished | Jun 28 08:41:08 PM PDT 24 |
| Peak memory | 643528 kb |
| Host | smart-bd72f32b-9a45-44ba-98b5-32d041566b5d |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 2123824733 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.chip_sw_all_escalation_resets.2123824733 |
| Directory | /workspace/47.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/48.chip_sw_alert_handler_lpg_sleep_mode_alerts.541676990 |
| Short name | T697 |
| Test name | |
| Test status | |
| Simulation time | 3401005438 ps |
| CPU time | 411.55 seconds |
| Started | Jun 28 08:29:55 PM PDT 24 |
| Finished | Jun 28 08:36:59 PM PDT 24 |
| Peak memory | 647280 kb |
| Host | smart-a2c48ea6-b908-44fc-bc6f-f2a0c6b22c71 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=541676990 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all _escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.chip_s w_alert_handler_lpg_sleep_mode_alerts.541676990 |
| Directory | /workspace/48.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/49.chip_sw_alert_handler_lpg_sleep_mode_alerts.3010408832 |
| Short name | T738 |
| Test name | |
| Test status | |
| Simulation time | 3351468050 ps |
| CPU time | 364.31 seconds |
| Started | Jun 28 08:29:51 PM PDT 24 |
| Finished | Jun 28 08:36:08 PM PDT 24 |
| Peak memory | 642508 kb |
| Host | smart-2de65ceb-1c05-4b8e-b825-f76986199e07 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3010408832 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.chip_ sw_alert_handler_lpg_sleep_mode_alerts.3010408832 |
| Directory | /workspace/49.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/5.chip_sw_all_escalation_resets.2637200047 |
| Short name | T739 |
| Test name | |
| Test status | |
| Simulation time | 5042032280 ps |
| CPU time | 644.66 seconds |
| Started | Jun 28 08:24:44 PM PDT 24 |
| Finished | Jun 28 08:35:30 PM PDT 24 |
| Peak memory | 643376 kb |
| Host | smart-0348bedd-ff26-402e-9f5b-ab8746e34c89 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 2637200047 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.chip_sw_all_escalation_resets.2637200047 |
| Directory | /workspace/5.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/5.chip_sw_csrng_edn_concurrency.2314003549 |
| Short name | T1103 |
| Test name | |
| Test status | |
| Simulation time | 19781791628 ps |
| CPU time | 4148.93 seconds |
| Started | Jun 28 08:25:41 PM PDT 24 |
| Finished | Jun 28 09:34:51 PM PDT 24 |
| Peak memory | 608472 kb |
| Host | smart-579cbec9-1f2a-4c63-8c32-dde675186eaa |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=140_000_000 +rng_srate_value_min=15 +rng_srate_value_max=20 +accelerate_cold_power_up_time=3 +accelerate_r egulators_power_up_time=2 +sw_build_device=sim_dv +sw_images=csrng_edn_concurrency_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2314003549 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd b -cm_log /dev/null -cm_name 5.chip_sw_csrng_edn_concurrency.2314003549 |
| Directory | /workspace/5.chip_sw_csrng_edn_concurrency/latest |
| Test location | /workspace/coverage/default/5.chip_sw_data_integrity_escalation.506527952 |
| Short name | T1060 |
| Test name | |
| Test status | |
| Simulation time | 5873153920 ps |
| CPU time | 680.32 seconds |
| Started | Jun 28 08:25:12 PM PDT 24 |
| Finished | Jun 28 08:36:37 PM PDT 24 |
| Peak memory | 609248 kb |
| Host | smart-158869ba-494f-49e7-8c37-7c28ff4da546 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=data_integrity_escalation_reset_test:1:new_rules,test_ro m:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=506527952 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_data_integrity_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.chip_sw_data_integrity_escalation.506527952 |
| Directory | /workspace/5.chip_sw_data_integrity_escalation/latest |
| Test location | /workspace/coverage/default/5.chip_sw_lc_ctrl_transition.1983527190 |
| Short name | T865 |
| Test name | |
| Test status | |
| Simulation time | 6752252761 ps |
| CPU time | 434.96 seconds |
| Started | Jun 28 08:25:36 PM PDT 24 |
| Finished | Jun 28 08:32:53 PM PDT 24 |
| Peak memory | 619008 kb |
| Host | smart-c1ff6d1c-657b-460c-88ee-d44fb58e7561 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=lc_ctrl_transition_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1983527190 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_transition_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau lt.vdb -cm_log /dev/null -cm_name 5.chip_sw_lc_ctrl_transition.1983527190 |
| Directory | /workspace/5.chip_sw_lc_ctrl_transition/latest |
| Test location | /workspace/coverage/default/5.chip_sw_uart_rand_baudrate.3064125264 |
| Short name | T914 |
| Test name | |
| Test status | |
| Simulation time | 4167899488 ps |
| CPU time | 531.16 seconds |
| Started | Jun 28 08:24:09 PM PDT 24 |
| Finished | Jun 28 08:33:07 PM PDT 24 |
| Peak memory | 618864 kb |
| Host | smart-859581f1-7022-497f-95ab-ac76ce1560ca |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=3064125264 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.chip_sw_uart_rand_baudrate.3064125264 |
| Directory | /workspace/5.chip_sw_uart_rand_baudrate/latest |
| Test location | /workspace/coverage/default/50.chip_sw_alert_handler_lpg_sleep_mode_alerts.1848408507 |
| Short name | T761 |
| Test name | |
| Test status | |
| Simulation time | 3684245946 ps |
| CPU time | 378.78 seconds |
| Started | Jun 28 08:29:17 PM PDT 24 |
| Finished | Jun 28 08:35:49 PM PDT 24 |
| Peak memory | 646900 kb |
| Host | smart-fbde8e7c-9614-4791-994d-614582764598 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1848408507 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.chip_ sw_alert_handler_lpg_sleep_mode_alerts.1848408507 |
| Directory | /workspace/50.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/50.chip_sw_all_escalation_resets.4163658714 |
| Short name | T702 |
| Test name | |
| Test status | |
| Simulation time | 6444767194 ps |
| CPU time | 830.43 seconds |
| Started | Jun 28 08:29:12 PM PDT 24 |
| Finished | Jun 28 08:43:20 PM PDT 24 |
| Peak memory | 648208 kb |
| Host | smart-71b5a078-791c-4d45-a921-32f953f66a1a |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 4163658714 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.chip_sw_all_escalation_resets.4163658714 |
| Directory | /workspace/50.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/51.chip_sw_all_escalation_resets.1491089377 |
| Short name | T704 |
| Test name | |
| Test status | |
| Simulation time | 5332876364 ps |
| CPU time | 571.13 seconds |
| Started | Jun 28 08:29:15 PM PDT 24 |
| Finished | Jun 28 08:39:01 PM PDT 24 |
| Peak memory | 643348 kb |
| Host | smart-6ce5fdff-960f-491c-bb28-6d0fc6bf092c |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 1491089377 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.chip_sw_all_escalation_resets.1491089377 |
| Directory | /workspace/51.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/54.chip_sw_alert_handler_lpg_sleep_mode_alerts.3290059718 |
| Short name | T733 |
| Test name | |
| Test status | |
| Simulation time | 3015129228 ps |
| CPU time | 325.16 seconds |
| Started | Jun 28 08:28:28 PM PDT 24 |
| Finished | Jun 28 08:33:54 PM PDT 24 |
| Peak memory | 646908 kb |
| Host | smart-97e7fc48-fcfc-42aa-aeda-290ede1413e5 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3290059718 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.chip_ sw_alert_handler_lpg_sleep_mode_alerts.3290059718 |
| Directory | /workspace/54.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/55.chip_sw_all_escalation_resets.3325170819 |
| Short name | T1306 |
| Test name | |
| Test status | |
| Simulation time | 5585874040 ps |
| CPU time | 701.43 seconds |
| Started | Jun 28 08:29:46 PM PDT 24 |
| Finished | Jun 28 08:41:38 PM PDT 24 |
| Peak memory | 647760 kb |
| Host | smart-0d0b9d0d-0c22-47df-a1a9-60b1baf26873 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 3325170819 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.chip_sw_all_escalation_resets.3325170819 |
| Directory | /workspace/55.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/57.chip_sw_all_escalation_resets.3497089236 |
| Short name | T1224 |
| Test name | |
| Test status | |
| Simulation time | 4316094560 ps |
| CPU time | 585.97 seconds |
| Started | Jun 28 08:29:21 PM PDT 24 |
| Finished | Jun 28 08:39:17 PM PDT 24 |
| Peak memory | 615104 kb |
| Host | smart-a90593fd-e1d0-4af7-abc8-efd62d160ded |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 3497089236 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.chip_sw_all_escalation_resets.3497089236 |
| Directory | /workspace/57.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/59.chip_sw_alert_handler_lpg_sleep_mode_alerts.2216351575 |
| Short name | T635 |
| Test name | |
| Test status | |
| Simulation time | 3673101500 ps |
| CPU time | 412.15 seconds |
| Started | Jun 28 08:30:02 PM PDT 24 |
| Finished | Jun 28 08:37:04 PM PDT 24 |
| Peak memory | 647116 kb |
| Host | smart-374a6930-0e68-4ac6-a3f5-b89a76f458d6 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2216351575 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.chip_ sw_alert_handler_lpg_sleep_mode_alerts.2216351575 |
| Directory | /workspace/59.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/59.chip_sw_all_escalation_resets.3455328432 |
| Short name | T371 |
| Test name | |
| Test status | |
| Simulation time | 5361723506 ps |
| CPU time | 708.04 seconds |
| Started | Jun 28 08:30:30 PM PDT 24 |
| Finished | Jun 28 08:42:24 PM PDT 24 |
| Peak memory | 647856 kb |
| Host | smart-b7dbb97d-c69d-48d0-97b3-9e65582e5319 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 3455328432 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.chip_sw_all_escalation_resets.3455328432 |
| Directory | /workspace/59.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/6.chip_sw_alert_handler_lpg_sleep_mode_alerts.3771832249 |
| Short name | T773 |
| Test name | |
| Test status | |
| Simulation time | 4294926470 ps |
| CPU time | 407.85 seconds |
| Started | Jun 28 08:26:01 PM PDT 24 |
| Finished | Jun 28 08:32:53 PM PDT 24 |
| Peak memory | 647184 kb |
| Host | smart-2cc66d21-fabf-4b09-96c4-34bfd4e81d4e |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3771832249 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.chip_s w_alert_handler_lpg_sleep_mode_alerts.3771832249 |
| Directory | /workspace/6.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/6.chip_sw_all_escalation_resets.3742127744 |
| Short name | T293 |
| Test name | |
| Test status | |
| Simulation time | 5635317832 ps |
| CPU time | 678.03 seconds |
| Started | Jun 28 08:26:27 PM PDT 24 |
| Finished | Jun 28 08:37:47 PM PDT 24 |
| Peak memory | 643372 kb |
| Host | smart-0547cb16-eb80-465e-a586-b16abd79d135 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 3742127744 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.chip_sw_all_escalation_resets.3742127744 |
| Directory | /workspace/6.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/6.chip_sw_csrng_edn_concurrency.4100078392 |
| Short name | T963 |
| Test name | |
| Test status | |
| Simulation time | 11446709920 ps |
| CPU time | 2547.85 seconds |
| Started | Jun 28 08:25:39 PM PDT 24 |
| Finished | Jun 28 09:08:08 PM PDT 24 |
| Peak memory | 608432 kb |
| Host | smart-7c4f58c0-9778-49f4-a8d1-3d74f927700f |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=140_000_000 +rng_srate_value_min=15 +rng_srate_value_max=20 +accelerate_cold_power_up_time=3 +accelerate_r egulators_power_up_time=2 +sw_build_device=sim_dv +sw_images=csrng_edn_concurrency_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4100078392 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd b -cm_log /dev/null -cm_name 6.chip_sw_csrng_edn_concurrency.4100078392 |
| Directory | /workspace/6.chip_sw_csrng_edn_concurrency/latest |
| Test location | /workspace/coverage/default/6.chip_sw_lc_ctrl_transition.2606631208 |
| Short name | T890 |
| Test name | |
| Test status | |
| Simulation time | 11960146892 ps |
| CPU time | 872.34 seconds |
| Started | Jun 28 08:25:46 PM PDT 24 |
| Finished | Jun 28 08:40:21 PM PDT 24 |
| Peak memory | 622272 kb |
| Host | smart-3b9f2789-3052-4594-b495-935a4a0916ba |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=lc_ctrl_transition_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2606631208 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_transition_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau lt.vdb -cm_log /dev/null -cm_name 6.chip_sw_lc_ctrl_transition.2606631208 |
| Directory | /workspace/6.chip_sw_lc_ctrl_transition/latest |
| Test location | /workspace/coverage/default/6.chip_sw_uart_rand_baudrate.2483292999 |
| Short name | T1117 |
| Test name | |
| Test status | |
| Simulation time | 3960513534 ps |
| CPU time | 577.87 seconds |
| Started | Jun 28 08:26:08 PM PDT 24 |
| Finished | Jun 28 08:35:56 PM PDT 24 |
| Peak memory | 618556 kb |
| Host | smart-115da849-4dba-485d-8097-056f905f65d4 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=2483292999 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.chip_sw_uart_rand_baudrate.2483292999 |
| Directory | /workspace/6.chip_sw_uart_rand_baudrate/latest |
| Test location | /workspace/coverage/default/60.chip_sw_alert_handler_lpg_sleep_mode_alerts.699895420 |
| Short name | T743 |
| Test name | |
| Test status | |
| Simulation time | 4069404730 ps |
| CPU time | 442.61 seconds |
| Started | Jun 28 08:30:18 PM PDT 24 |
| Finished | Jun 28 08:37:47 PM PDT 24 |
| Peak memory | 646924 kb |
| Host | smart-9cbeb790-57ab-4eb6-b6a1-e707959ebfb6 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=699895420 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all _escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.chip_s w_alert_handler_lpg_sleep_mode_alerts.699895420 |
| Directory | /workspace/60.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/60.chip_sw_all_escalation_resets.3596280018 |
| Short name | T691 |
| Test name | |
| Test status | |
| Simulation time | 5175476492 ps |
| CPU time | 746.67 seconds |
| Started | Jun 28 08:30:41 PM PDT 24 |
| Finished | Jun 28 08:43:09 PM PDT 24 |
| Peak memory | 647992 kb |
| Host | smart-dbc634df-bf5b-4528-85da-a8f8939cd553 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 3596280018 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.chip_sw_all_escalation_resets.3596280018 |
| Directory | /workspace/60.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/61.chip_sw_alert_handler_lpg_sleep_mode_alerts.3586084147 |
| Short name | T678 |
| Test name | |
| Test status | |
| Simulation time | 2938656748 ps |
| CPU time | 286.3 seconds |
| Started | Jun 28 08:32:04 PM PDT 24 |
| Finished | Jun 28 08:36:58 PM PDT 24 |
| Peak memory | 647044 kb |
| Host | smart-cb041538-a14a-4fad-8391-550e718ae769 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3586084147 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.chip_ sw_alert_handler_lpg_sleep_mode_alerts.3586084147 |
| Directory | /workspace/61.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/62.chip_sw_alert_handler_lpg_sleep_mode_alerts.1982213357 |
| Short name | T419 |
| Test name | |
| Test status | |
| Simulation time | 4341787880 ps |
| CPU time | 338.07 seconds |
| Started | Jun 28 08:32:00 PM PDT 24 |
| Finished | Jun 28 08:37:48 PM PDT 24 |
| Peak memory | 647268 kb |
| Host | smart-ca42528a-50ac-4c3f-b12b-87f6cf6aa387 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1982213357 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.chip_ sw_alert_handler_lpg_sleep_mode_alerts.1982213357 |
| Directory | /workspace/62.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/63.chip_sw_alert_handler_lpg_sleep_mode_alerts.2650565779 |
| Short name | T1225 |
| Test name | |
| Test status | |
| Simulation time | 4175091840 ps |
| CPU time | 547.64 seconds |
| Started | Jun 28 08:31:18 PM PDT 24 |
| Finished | Jun 28 08:40:44 PM PDT 24 |
| Peak memory | 642148 kb |
| Host | smart-26448da0-58b1-4512-bd36-8a60d6f8e401 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2650565779 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.chip_ sw_alert_handler_lpg_sleep_mode_alerts.2650565779 |
| Directory | /workspace/63.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/63.chip_sw_all_escalation_resets.564578044 |
| Short name | T709 |
| Test name | |
| Test status | |
| Simulation time | 4788126000 ps |
| CPU time | 495.08 seconds |
| Started | Jun 28 08:31:30 PM PDT 24 |
| Finished | Jun 28 08:40:00 PM PDT 24 |
| Peak memory | 615148 kb |
| Host | smart-6bc75b6a-a2a1-4fd8-bbec-9d0b7f8decda |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 564578044 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.chip_sw_all_escalation_resets.564578044 |
| Directory | /workspace/63.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/64.chip_sw_alert_handler_lpg_sleep_mode_alerts.1328068604 |
| Short name | T719 |
| Test name | |
| Test status | |
| Simulation time | 3675719236 ps |
| CPU time | 413.56 seconds |
| Started | Jun 28 08:33:14 PM PDT 24 |
| Finished | Jun 28 08:40:15 PM PDT 24 |
| Peak memory | 646888 kb |
| Host | smart-dd04a0c7-5877-44bd-a6c9-3c19b1481a35 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1328068604 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.chip_ sw_alert_handler_lpg_sleep_mode_alerts.1328068604 |
| Directory | /workspace/64.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/64.chip_sw_all_escalation_resets.1956913101 |
| Short name | T744 |
| Test name | |
| Test status | |
| Simulation time | 4648187744 ps |
| CPU time | 516.3 seconds |
| Started | Jun 28 08:30:46 PM PDT 24 |
| Finished | Jun 28 08:39:24 PM PDT 24 |
| Peak memory | 643512 kb |
| Host | smart-a2939c26-df2c-4b9f-9706-bc64c3da2fd5 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 1956913101 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.chip_sw_all_escalation_resets.1956913101 |
| Directory | /workspace/64.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/65.chip_sw_alert_handler_lpg_sleep_mode_alerts.3539158948 |
| Short name | T311 |
| Test name | |
| Test status | |
| Simulation time | 3658681620 ps |
| CPU time | 471.82 seconds |
| Started | Jun 28 08:31:22 PM PDT 24 |
| Finished | Jun 28 08:39:32 PM PDT 24 |
| Peak memory | 647188 kb |
| Host | smart-e27327e1-e370-43aa-8644-51d4ff649edd |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3539158948 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.chip_ sw_alert_handler_lpg_sleep_mode_alerts.3539158948 |
| Directory | /workspace/65.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/65.chip_sw_all_escalation_resets.1771801247 |
| Short name | T1269 |
| Test name | |
| Test status | |
| Simulation time | 5597913946 ps |
| CPU time | 621.88 seconds |
| Started | Jun 28 08:30:52 PM PDT 24 |
| Finished | Jun 28 08:41:16 PM PDT 24 |
| Peak memory | 643900 kb |
| Host | smart-78b72b3a-bac6-4204-ae7f-e54836909bfa |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 1771801247 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.chip_sw_all_escalation_resets.1771801247 |
| Directory | /workspace/65.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/66.chip_sw_alert_handler_lpg_sleep_mode_alerts.1778570616 |
| Short name | T393 |
| Test name | |
| Test status | |
| Simulation time | 4314678476 ps |
| CPU time | 413.39 seconds |
| Started | Jun 28 08:33:03 PM PDT 24 |
| Finished | Jun 28 08:40:04 PM PDT 24 |
| Peak memory | 647596 kb |
| Host | smart-619a9162-64d4-4d6a-b3f3-8186d2b70ef9 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1778570616 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.chip_ sw_alert_handler_lpg_sleep_mode_alerts.1778570616 |
| Directory | /workspace/66.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/66.chip_sw_all_escalation_resets.2287565228 |
| Short name | T161 |
| Test name | |
| Test status | |
| Simulation time | 4579955828 ps |
| CPU time | 590.86 seconds |
| Started | Jun 28 08:30:45 PM PDT 24 |
| Finished | Jun 28 08:40:38 PM PDT 24 |
| Peak memory | 617284 kb |
| Host | smart-76b300da-1565-4214-839d-355e484a5b9f |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 2287565228 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.chip_sw_all_escalation_resets.2287565228 |
| Directory | /workspace/66.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/67.chip_sw_alert_handler_lpg_sleep_mode_alerts.2778926982 |
| Short name | T766 |
| Test name | |
| Test status | |
| Simulation time | 3544243676 ps |
| CPU time | 386.81 seconds |
| Started | Jun 28 08:31:06 PM PDT 24 |
| Finished | Jun 28 08:37:38 PM PDT 24 |
| Peak memory | 647108 kb |
| Host | smart-08072c60-f67a-4f21-ad85-c3303db092bd |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2778926982 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.chip_ sw_alert_handler_lpg_sleep_mode_alerts.2778926982 |
| Directory | /workspace/67.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/67.chip_sw_all_escalation_resets.4046381713 |
| Short name | T770 |
| Test name | |
| Test status | |
| Simulation time | 5644072720 ps |
| CPU time | 621.18 seconds |
| Started | Jun 28 08:31:14 PM PDT 24 |
| Finished | Jun 28 08:41:52 PM PDT 24 |
| Peak memory | 647996 kb |
| Host | smart-183f9d77-0796-466e-8766-82d290f2cad1 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 4046381713 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.chip_sw_all_escalation_resets.4046381713 |
| Directory | /workspace/67.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/68.chip_sw_all_escalation_resets.3902067496 |
| Short name | T391 |
| Test name | |
| Test status | |
| Simulation time | 5775503826 ps |
| CPU time | 716.94 seconds |
| Started | Jun 28 08:32:14 PM PDT 24 |
| Finished | Jun 28 08:44:14 PM PDT 24 |
| Peak memory | 647920 kb |
| Host | smart-5042cd00-64ab-4d37-8b34-9d168301c631 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 3902067496 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.chip_sw_all_escalation_resets.3902067496 |
| Directory | /workspace/68.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/69.chip_sw_alert_handler_lpg_sleep_mode_alerts.2172182477 |
| Short name | T756 |
| Test name | |
| Test status | |
| Simulation time | 4368100888 ps |
| CPU time | 520.48 seconds |
| Started | Jun 28 08:31:45 PM PDT 24 |
| Finished | Jun 28 08:40:36 PM PDT 24 |
| Peak memory | 647036 kb |
| Host | smart-d54864ec-707b-4ded-bc8e-8ffb8286a145 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2172182477 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.chip_ sw_alert_handler_lpg_sleep_mode_alerts.2172182477 |
| Directory | /workspace/69.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/69.chip_sw_all_escalation_resets.1735649773 |
| Short name | T5 |
| Test name | |
| Test status | |
| Simulation time | 5776881688 ps |
| CPU time | 822.68 seconds |
| Started | Jun 28 08:31:53 PM PDT 24 |
| Finished | Jun 28 08:45:47 PM PDT 24 |
| Peak memory | 615148 kb |
| Host | smart-07ba9337-0f57-4618-bf39-00b0d1192e7a |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 1735649773 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.chip_sw_all_escalation_resets.1735649773 |
| Directory | /workspace/69.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/7.chip_sw_alert_handler_lpg_sleep_mode_alerts.3671647664 |
| Short name | T239 |
| Test name | |
| Test status | |
| Simulation time | 3327516322 ps |
| CPU time | 329.55 seconds |
| Started | Jun 28 08:28:15 PM PDT 24 |
| Finished | Jun 28 08:33:47 PM PDT 24 |
| Peak memory | 642176 kb |
| Host | smart-886f385f-3a17-4c5e-a5a0-56acb579620c |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3671647664 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.chip_s w_alert_handler_lpg_sleep_mode_alerts.3671647664 |
| Directory | /workspace/7.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/7.chip_sw_all_escalation_resets.1432711855 |
| Short name | T296 |
| Test name | |
| Test status | |
| Simulation time | 5946894184 ps |
| CPU time | 583.22 seconds |
| Started | Jun 28 08:26:03 PM PDT 24 |
| Finished | Jun 28 08:35:54 PM PDT 24 |
| Peak memory | 643428 kb |
| Host | smart-5d0f9d22-2dd9-42a1-95db-2de9730073b7 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 1432711855 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.chip_sw_all_escalation_resets.1432711855 |
| Directory | /workspace/7.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/7.chip_sw_csrng_edn_concurrency.66492317 |
| Short name | T633 |
| Test name | |
| Test status | |
| Simulation time | 25706432888 ps |
| CPU time | 5629.04 seconds |
| Started | Jun 28 08:26:26 PM PDT 24 |
| Finished | Jun 28 10:00:19 PM PDT 24 |
| Peak memory | 608396 kb |
| Host | smart-ea8addeb-3794-4421-9034-bfaa54fb4521 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=140_000_000 +rng_srate_value_min=15 +rng_srate_value_max=20 +accelerate_cold_power_up_time=3 +accelerate_r egulators_power_up_time=2 +sw_build_device=sim_dv +sw_images=csrng_edn_concurrency_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66492317 -assert nopostproc + UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.chip_sw_csrng_edn_concurrency.66492317 |
| Directory | /workspace/7.chip_sw_csrng_edn_concurrency/latest |
| Test location | /workspace/coverage/default/7.chip_sw_lc_ctrl_transition.3056801542 |
| Short name | T858 |
| Test name | |
| Test status | |
| Simulation time | 10498901215 ps |
| CPU time | 783.71 seconds |
| Started | Jun 28 08:25:40 PM PDT 24 |
| Finished | Jun 28 08:38:46 PM PDT 24 |
| Peak memory | 620608 kb |
| Host | smart-15b1070d-5cae-42b2-9e52-0e28fc1b4649 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=lc_ctrl_transition_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3056801542 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_transition_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau lt.vdb -cm_log /dev/null -cm_name 7.chip_sw_lc_ctrl_transition.3056801542 |
| Directory | /workspace/7.chip_sw_lc_ctrl_transition/latest |
| Test location | /workspace/coverage/default/7.chip_sw_uart_rand_baudrate.1583174532 |
| Short name | T1139 |
| Test name | |
| Test status | |
| Simulation time | 3796872760 ps |
| CPU time | 643.74 seconds |
| Started | Jun 28 08:26:00 PM PDT 24 |
| Finished | Jun 28 08:36:49 PM PDT 24 |
| Peak memory | 618608 kb |
| Host | smart-aeb3afcf-16c8-493a-b16f-3cc84892b448 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=1583174532 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.chip_sw_uart_rand_baudrate.1583174532 |
| Directory | /workspace/7.chip_sw_uart_rand_baudrate/latest |
| Test location | /workspace/coverage/default/70.chip_sw_alert_handler_lpg_sleep_mode_alerts.2325823289 |
| Short name | T778 |
| Test name | |
| Test status | |
| Simulation time | 3988621898 ps |
| CPU time | 454.21 seconds |
| Started | Jun 28 08:31:39 PM PDT 24 |
| Finished | Jun 28 08:39:25 PM PDT 24 |
| Peak memory | 646984 kb |
| Host | smart-0879cd58-1807-4de9-b4cc-9d7374320b34 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2325823289 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.chip_ sw_alert_handler_lpg_sleep_mode_alerts.2325823289 |
| Directory | /workspace/70.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/70.chip_sw_all_escalation_resets.4171889169 |
| Short name | T299 |
| Test name | |
| Test status | |
| Simulation time | 5725695220 ps |
| CPU time | 581.11 seconds |
| Started | Jun 28 08:33:58 PM PDT 24 |
| Finished | Jun 28 08:43:48 PM PDT 24 |
| Peak memory | 643752 kb |
| Host | smart-118b588c-2971-4663-89f7-68f470648204 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 4171889169 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.chip_sw_all_escalation_resets.4171889169 |
| Directory | /workspace/70.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/71.chip_sw_alert_handler_lpg_sleep_mode_alerts.4050278434 |
| Short name | T768 |
| Test name | |
| Test status | |
| Simulation time | 3299054772 ps |
| CPU time | 378.47 seconds |
| Started | Jun 28 08:31:15 PM PDT 24 |
| Finished | Jun 28 08:37:50 PM PDT 24 |
| Peak memory | 642364 kb |
| Host | smart-f40d3b91-b024-4108-aad7-e378046cfccf |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4050278434 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.chip_ sw_alert_handler_lpg_sleep_mode_alerts.4050278434 |
| Directory | /workspace/71.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/72.chip_sw_alert_handler_lpg_sleep_mode_alerts.347028553 |
| Short name | T741 |
| Test name | |
| Test status | |
| Simulation time | 3775732792 ps |
| CPU time | 435.76 seconds |
| Started | Jun 28 08:32:39 PM PDT 24 |
| Finished | Jun 28 08:39:57 PM PDT 24 |
| Peak memory | 647020 kb |
| Host | smart-d02853e0-6c3f-44db-8c02-753a074f0c61 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=347028553 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all _escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.chip_s w_alert_handler_lpg_sleep_mode_alerts.347028553 |
| Directory | /workspace/72.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/72.chip_sw_all_escalation_resets.2390736733 |
| Short name | T736 |
| Test name | |
| Test status | |
| Simulation time | 4336818312 ps |
| CPU time | 588.66 seconds |
| Started | Jun 28 08:30:32 PM PDT 24 |
| Finished | Jun 28 08:40:27 PM PDT 24 |
| Peak memory | 647928 kb |
| Host | smart-4aac3d3e-15d0-4d16-a7da-4b8e1d799551 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 2390736733 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.chip_sw_all_escalation_resets.2390736733 |
| Directory | /workspace/72.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/73.chip_sw_alert_handler_lpg_sleep_mode_alerts.3348703761 |
| Short name | T777 |
| Test name | |
| Test status | |
| Simulation time | 3841799152 ps |
| CPU time | 392.72 seconds |
| Started | Jun 28 08:31:49 PM PDT 24 |
| Finished | Jun 28 08:38:33 PM PDT 24 |
| Peak memory | 646864 kb |
| Host | smart-c2976fca-d5b0-45d2-a1c0-84d4b4891409 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3348703761 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.chip_ sw_alert_handler_lpg_sleep_mode_alerts.3348703761 |
| Directory | /workspace/73.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/73.chip_sw_all_escalation_resets.4231865711 |
| Short name | T367 |
| Test name | |
| Test status | |
| Simulation time | 5035740840 ps |
| CPU time | 561.51 seconds |
| Started | Jun 28 08:30:17 PM PDT 24 |
| Finished | Jun 28 08:39:45 PM PDT 24 |
| Peak memory | 643440 kb |
| Host | smart-bbb0e471-92b2-4c7e-9ec2-70b1afcf3662 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 4231865711 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.chip_sw_all_escalation_resets.4231865711 |
| Directory | /workspace/73.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/74.chip_sw_alert_handler_lpg_sleep_mode_alerts.742345032 |
| Short name | T746 |
| Test name | |
| Test status | |
| Simulation time | 3689464216 ps |
| CPU time | 550.49 seconds |
| Started | Jun 28 08:30:57 PM PDT 24 |
| Finished | Jun 28 08:40:10 PM PDT 24 |
| Peak memory | 646936 kb |
| Host | smart-0c7274c5-9f1c-48d0-88bc-469a0657f182 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=742345032 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all _escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.chip_s w_alert_handler_lpg_sleep_mode_alerts.742345032 |
| Directory | /workspace/74.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/74.chip_sw_all_escalation_resets.3261953661 |
| Short name | T712 |
| Test name | |
| Test status | |
| Simulation time | 6136580200 ps |
| CPU time | 609.8 seconds |
| Started | Jun 28 08:31:19 PM PDT 24 |
| Finished | Jun 28 08:41:47 PM PDT 24 |
| Peak memory | 647888 kb |
| Host | smart-897ab2f0-43ba-4d27-90ff-297c0a0da252 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 3261953661 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.chip_sw_all_escalation_resets.3261953661 |
| Directory | /workspace/74.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/75.chip_sw_alert_handler_lpg_sleep_mode_alerts.3701880901 |
| Short name | T310 |
| Test name | |
| Test status | |
| Simulation time | 3663418230 ps |
| CPU time | 364.12 seconds |
| Started | Jun 28 08:38:18 PM PDT 24 |
| Finished | Jun 28 08:44:33 PM PDT 24 |
| Peak memory | 647152 kb |
| Host | smart-62421ed9-f1e9-4408-8ac0-338ab3c6af3c |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3701880901 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.chip_ sw_alert_handler_lpg_sleep_mode_alerts.3701880901 |
| Directory | /workspace/75.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/75.chip_sw_all_escalation_resets.907413001 |
| Short name | T209 |
| Test name | |
| Test status | |
| Simulation time | 6061174452 ps |
| CPU time | 702.55 seconds |
| Started | Jun 28 08:37:59 PM PDT 24 |
| Finished | Jun 28 08:49:44 PM PDT 24 |
| Peak memory | 643312 kb |
| Host | smart-a58d695d-d37f-42d4-8f83-044c725f6493 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 907413001 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.chip_sw_all_escalation_resets.907413001 |
| Directory | /workspace/75.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/76.chip_sw_alert_handler_lpg_sleep_mode_alerts.555241165 |
| Short name | T372 |
| Test name | |
| Test status | |
| Simulation time | 3368660270 ps |
| CPU time | 431.14 seconds |
| Started | Jun 28 08:31:48 PM PDT 24 |
| Finished | Jun 28 08:39:10 PM PDT 24 |
| Peak memory | 647008 kb |
| Host | smart-9505220e-c060-4d84-a384-6cd85fa0388d |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=555241165 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all _escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.chip_s w_alert_handler_lpg_sleep_mode_alerts.555241165 |
| Directory | /workspace/76.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/77.chip_sw_alert_handler_lpg_sleep_mode_alerts.46308106 |
| Short name | T396 |
| Test name | |
| Test status | |
| Simulation time | 3242880536 ps |
| CPU time | 316.82 seconds |
| Started | Jun 28 08:38:29 PM PDT 24 |
| Finished | Jun 28 08:43:53 PM PDT 24 |
| Peak memory | 646904 kb |
| Host | smart-7806ebdb-ae79-4376-92b4-df6a4ee34419 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46308106 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_ escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.chip_sw _alert_handler_lpg_sleep_mode_alerts.46308106 |
| Directory | /workspace/77.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/77.chip_sw_all_escalation_resets.3875740785 |
| Short name | T1188 |
| Test name | |
| Test status | |
| Simulation time | 4457237052 ps |
| CPU time | 528.88 seconds |
| Started | Jun 28 08:37:10 PM PDT 24 |
| Finished | Jun 28 08:46:10 PM PDT 24 |
| Peak memory | 643416 kb |
| Host | smart-8411c9a5-6e86-4464-a4cc-427dea41851d |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 3875740785 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.chip_sw_all_escalation_resets.3875740785 |
| Directory | /workspace/77.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/78.chip_sw_alert_handler_lpg_sleep_mode_alerts.1919560452 |
| Short name | T1246 |
| Test name | |
| Test status | |
| Simulation time | 3658508968 ps |
| CPU time | 399.06 seconds |
| Started | Jun 28 08:31:31 PM PDT 24 |
| Finished | Jun 28 08:38:25 PM PDT 24 |
| Peak memory | 616724 kb |
| Host | smart-3ed5a90f-fccd-4322-9f3c-9ba1c88cfdd8 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1919560452 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.chip_ sw_alert_handler_lpg_sleep_mode_alerts.1919560452 |
| Directory | /workspace/78.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/79.chip_sw_alert_handler_lpg_sleep_mode_alerts.257129264 |
| Short name | T388 |
| Test name | |
| Test status | |
| Simulation time | 3851834460 ps |
| CPU time | 525.89 seconds |
| Started | Jun 28 08:32:00 PM PDT 24 |
| Finished | Jun 28 08:40:55 PM PDT 24 |
| Peak memory | 642396 kb |
| Host | smart-b2e0bfef-d01b-4017-962f-9dcd55935d50 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=257129264 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all _escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.chip_s w_alert_handler_lpg_sleep_mode_alerts.257129264 |
| Directory | /workspace/79.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/8.chip_sw_alert_handler_lpg_sleep_mode_alerts.981112506 |
| Short name | T666 |
| Test name | |
| Test status | |
| Simulation time | 4333622320 ps |
| CPU time | 489.03 seconds |
| Started | Jun 28 08:25:43 PM PDT 24 |
| Finished | Jun 28 08:33:54 PM PDT 24 |
| Peak memory | 647268 kb |
| Host | smart-9ceeadc2-16cc-4923-a22b-9ad37c949d5e |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=981112506 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all _escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.chip_sw _alert_handler_lpg_sleep_mode_alerts.981112506 |
| Directory | /workspace/8.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/8.chip_sw_all_escalation_resets.3111883022 |
| Short name | T711 |
| Test name | |
| Test status | |
| Simulation time | 4932034296 ps |
| CPU time | 754.97 seconds |
| Started | Jun 28 08:25:50 PM PDT 24 |
| Finished | Jun 28 08:38:26 PM PDT 24 |
| Peak memory | 615144 kb |
| Host | smart-5c1d5a34-0a7b-4b5a-bb8d-af4e2e278a1a |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 3111883022 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.chip_sw_all_escalation_resets.3111883022 |
| Directory | /workspace/8.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/8.chip_sw_csrng_edn_concurrency.650064616 |
| Short name | T1033 |
| Test name | |
| Test status | |
| Simulation time | 22180935488 ps |
| CPU time | 5259.62 seconds |
| Started | Jun 28 08:25:30 PM PDT 24 |
| Finished | Jun 28 09:53:12 PM PDT 24 |
| Peak memory | 608196 kb |
| Host | smart-3da46582-8ae2-449b-8067-8fd050255dd6 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=140_000_000 +rng_srate_value_min=15 +rng_srate_value_max=20 +accelerate_cold_power_up_time=3 +accelerate_r egulators_power_up_time=2 +sw_build_device=sim_dv +sw_images=csrng_edn_concurrency_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=650064616 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.chip_sw_csrng_edn_concurrency.650064616 |
| Directory | /workspace/8.chip_sw_csrng_edn_concurrency/latest |
| Test location | /workspace/coverage/default/8.chip_sw_lc_ctrl_transition.314355593 |
| Short name | T1267 |
| Test name | |
| Test status | |
| Simulation time | 5255177762 ps |
| CPU time | 651.7 seconds |
| Started | Jun 28 08:26:30 PM PDT 24 |
| Finished | Jun 28 08:37:23 PM PDT 24 |
| Peak memory | 618972 kb |
| Host | smart-d6112275-c77a-4025-b022-01bfc73e466c |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=lc_ctrl_transition_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=314355593 -assert nopostproc +UVM_TEST NAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_transition_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul t.vdb -cm_log /dev/null -cm_name 8.chip_sw_lc_ctrl_transition.314355593 |
| Directory | /workspace/8.chip_sw_lc_ctrl_transition/latest |
| Test location | /workspace/coverage/default/8.chip_sw_uart_rand_baudrate.658662805 |
| Short name | T1217 |
| Test name | |
| Test status | |
| Simulation time | 4131727208 ps |
| CPU time | 702.46 seconds |
| Started | Jun 28 08:25:48 PM PDT 24 |
| Finished | Jun 28 08:37:32 PM PDT 24 |
| Peak memory | 618592 kb |
| Host | smart-de4ecd54-54c8-47e7-a206-8712e7a35632 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=658662805 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.chip_sw_uart_rand_baudrate.658662805 |
| Directory | /workspace/8.chip_sw_uart_rand_baudrate/latest |
| Test location | /workspace/coverage/default/80.chip_sw_alert_handler_lpg_sleep_mode_alerts.3321980314 |
| Short name | T430 |
| Test name | |
| Test status | |
| Simulation time | 3494869800 ps |
| CPU time | 411.49 seconds |
| Started | Jun 28 08:31:31 PM PDT 24 |
| Finished | Jun 28 08:38:37 PM PDT 24 |
| Peak memory | 647000 kb |
| Host | smart-96093238-ddbe-4fcf-9e58-7c42fb1d4ca6 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3321980314 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 80.chip_ sw_alert_handler_lpg_sleep_mode_alerts.3321980314 |
| Directory | /workspace/80.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/80.chip_sw_all_escalation_resets.4091957846 |
| Short name | T1019 |
| Test name | |
| Test status | |
| Simulation time | 5882180176 ps |
| CPU time | 651.29 seconds |
| Started | Jun 28 08:32:58 PM PDT 24 |
| Finished | Jun 28 08:43:53 PM PDT 24 |
| Peak memory | 643384 kb |
| Host | smart-313974eb-8013-484c-b5f0-6f171f0fe085 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 4091957846 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 80.chip_sw_all_escalation_resets.4091957846 |
| Directory | /workspace/80.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/81.chip_sw_alert_handler_lpg_sleep_mode_alerts.3347281779 |
| Short name | T748 |
| Test name | |
| Test status | |
| Simulation time | 3651644096 ps |
| CPU time | 405.45 seconds |
| Started | Jun 28 08:33:26 PM PDT 24 |
| Finished | Jun 28 08:40:13 PM PDT 24 |
| Peak memory | 647064 kb |
| Host | smart-c4bcfac0-6389-4fdb-9546-d5e55d86bf11 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3347281779 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 81.chip_ sw_alert_handler_lpg_sleep_mode_alerts.3347281779 |
| Directory | /workspace/81.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/81.chip_sw_all_escalation_resets.1873469126 |
| Short name | T1199 |
| Test name | |
| Test status | |
| Simulation time | 5868441258 ps |
| CPU time | 676.15 seconds |
| Started | Jun 28 08:31:28 PM PDT 24 |
| Finished | Jun 28 08:43:01 PM PDT 24 |
| Peak memory | 647788 kb |
| Host | smart-0eb1d309-d4cb-48a9-8e80-23e97e4ff6a5 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 1873469126 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 81.chip_sw_all_escalation_resets.1873469126 |
| Directory | /workspace/81.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/82.chip_sw_alert_handler_lpg_sleep_mode_alerts.3150988386 |
| Short name | T1078 |
| Test name | |
| Test status | |
| Simulation time | 3966798400 ps |
| CPU time | 447.29 seconds |
| Started | Jun 28 08:31:59 PM PDT 24 |
| Finished | Jun 28 08:39:36 PM PDT 24 |
| Peak memory | 646960 kb |
| Host | smart-3872d003-51ff-41c1-8a29-903b08905372 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3150988386 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 82.chip_ sw_alert_handler_lpg_sleep_mode_alerts.3150988386 |
| Directory | /workspace/82.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/82.chip_sw_all_escalation_resets.1708084783 |
| Short name | T260 |
| Test name | |
| Test status | |
| Simulation time | 4248116680 ps |
| CPU time | 406.5 seconds |
| Started | Jun 28 08:33:40 PM PDT 24 |
| Finished | Jun 28 08:40:34 PM PDT 24 |
| Peak memory | 643412 kb |
| Host | smart-ce7b3185-dcea-46e8-8e9b-7eaa745dcc18 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 1708084783 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 82.chip_sw_all_escalation_resets.1708084783 |
| Directory | /workspace/82.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/83.chip_sw_alert_handler_lpg_sleep_mode_alerts.1823792242 |
| Short name | T751 |
| Test name | |
| Test status | |
| Simulation time | 3512823708 ps |
| CPU time | 382.21 seconds |
| Started | Jun 28 08:31:50 PM PDT 24 |
| Finished | Jun 28 08:38:23 PM PDT 24 |
| Peak memory | 647036 kb |
| Host | smart-72b559de-d151-4952-b87e-3f0ff386dff4 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1823792242 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 83.chip_ sw_alert_handler_lpg_sleep_mode_alerts.1823792242 |
| Directory | /workspace/83.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/83.chip_sw_all_escalation_resets.3825610711 |
| Short name | T160 |
| Test name | |
| Test status | |
| Simulation time | 4772930484 ps |
| CPU time | 736.01 seconds |
| Started | Jun 28 08:33:55 PM PDT 24 |
| Finished | Jun 28 08:46:20 PM PDT 24 |
| Peak memory | 617324 kb |
| Host | smart-7fd2eec8-6988-4bf0-9182-74b995e722bb |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 3825610711 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 83.chip_sw_all_escalation_resets.3825610711 |
| Directory | /workspace/83.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/84.chip_sw_alert_handler_lpg_sleep_mode_alerts.3959215233 |
| Short name | T1155 |
| Test name | |
| Test status | |
| Simulation time | 4070217256 ps |
| CPU time | 398.93 seconds |
| Started | Jun 28 08:31:58 PM PDT 24 |
| Finished | Jun 28 08:38:47 PM PDT 24 |
| Peak memory | 646828 kb |
| Host | smart-23b6e3c9-a2fd-49e1-9777-c35b046ed178 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3959215233 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 84.chip_ sw_alert_handler_lpg_sleep_mode_alerts.3959215233 |
| Directory | /workspace/84.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/85.chip_sw_alert_handler_lpg_sleep_mode_alerts.2556066250 |
| Short name | T411 |
| Test name | |
| Test status | |
| Simulation time | 3751319458 ps |
| CPU time | 355.55 seconds |
| Started | Jun 28 08:33:46 PM PDT 24 |
| Finished | Jun 28 08:39:52 PM PDT 24 |
| Peak memory | 646960 kb |
| Host | smart-d253a831-75a9-40bb-9d11-0d11f2121418 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2556066250 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 85.chip_ sw_alert_handler_lpg_sleep_mode_alerts.2556066250 |
| Directory | /workspace/85.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/85.chip_sw_all_escalation_resets.398219833 |
| Short name | T300 |
| Test name | |
| Test status | |
| Simulation time | 5368865932 ps |
| CPU time | 744.39 seconds |
| Started | Jun 28 08:32:30 PM PDT 24 |
| Finished | Jun 28 08:44:57 PM PDT 24 |
| Peak memory | 647788 kb |
| Host | smart-c61399fc-f283-47b4-8636-c2871fd724db |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 398219833 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 85.chip_sw_all_escalation_resets.398219833 |
| Directory | /workspace/85.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/86.chip_sw_alert_handler_lpg_sleep_mode_alerts.304769779 |
| Short name | T740 |
| Test name | |
| Test status | |
| Simulation time | 4180922050 ps |
| CPU time | 475.26 seconds |
| Started | Jun 28 08:31:39 PM PDT 24 |
| Finished | Jun 28 08:39:46 PM PDT 24 |
| Peak memory | 646964 kb |
| Host | smart-77ec7311-ef0f-4830-9eed-01599c03d19a |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=304769779 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all _escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 86.chip_s w_alert_handler_lpg_sleep_mode_alerts.304769779 |
| Directory | /workspace/86.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/86.chip_sw_all_escalation_resets.3731876717 |
| Short name | T769 |
| Test name | |
| Test status | |
| Simulation time | 5236358924 ps |
| CPU time | 524.9 seconds |
| Started | Jun 28 08:33:40 PM PDT 24 |
| Finished | Jun 28 08:42:32 PM PDT 24 |
| Peak memory | 648020 kb |
| Host | smart-933459ff-711b-4778-9366-283a746d8f14 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 3731876717 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 86.chip_sw_all_escalation_resets.3731876717 |
| Directory | /workspace/86.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/87.chip_sw_alert_handler_lpg_sleep_mode_alerts.4023450837 |
| Short name | T244 |
| Test name | |
| Test status | |
| Simulation time | 4158267716 ps |
| CPU time | 422.74 seconds |
| Started | Jun 28 08:31:49 PM PDT 24 |
| Finished | Jun 28 08:39:03 PM PDT 24 |
| Peak memory | 646988 kb |
| Host | smart-719c381f-089a-4a88-b95f-ab269a213fe4 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4023450837 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 87.chip_ sw_alert_handler_lpg_sleep_mode_alerts.4023450837 |
| Directory | /workspace/87.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/87.chip_sw_all_escalation_resets.574391645 |
| Short name | T357 |
| Test name | |
| Test status | |
| Simulation time | 5361205570 ps |
| CPU time | 664.16 seconds |
| Started | Jun 28 08:32:23 PM PDT 24 |
| Finished | Jun 28 08:43:31 PM PDT 24 |
| Peak memory | 643372 kb |
| Host | smart-ea1ff48b-9469-4e04-8d6f-cf202b8b42b3 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 574391645 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 87.chip_sw_all_escalation_resets.574391645 |
| Directory | /workspace/87.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/88.chip_sw_alert_handler_lpg_sleep_mode_alerts.3333100174 |
| Short name | T734 |
| Test name | |
| Test status | |
| Simulation time | 3042733640 ps |
| CPU time | 413.12 seconds |
| Started | Jun 28 08:32:57 PM PDT 24 |
| Finished | Jun 28 08:39:53 PM PDT 24 |
| Peak memory | 647020 kb |
| Host | smart-cfebe693-84c7-42f2-9b01-74e0adc7d4ba |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3333100174 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 88.chip_ sw_alert_handler_lpg_sleep_mode_alerts.3333100174 |
| Directory | /workspace/88.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/88.chip_sw_all_escalation_resets.3790061952 |
| Short name | T370 |
| Test name | |
| Test status | |
| Simulation time | 4741861090 ps |
| CPU time | 542.84 seconds |
| Started | Jun 28 08:34:34 PM PDT 24 |
| Finished | Jun 28 08:43:56 PM PDT 24 |
| Peak memory | 643436 kb |
| Host | smart-351ab6f0-e2ec-4bd9-9cc2-eccb253eba3d |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 3790061952 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 88.chip_sw_all_escalation_resets.3790061952 |
| Directory | /workspace/88.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/89.chip_sw_alert_handler_lpg_sleep_mode_alerts.101143994 |
| Short name | T684 |
| Test name | |
| Test status | |
| Simulation time | 4074301818 ps |
| CPU time | 476.27 seconds |
| Started | Jun 28 08:31:59 PM PDT 24 |
| Finished | Jun 28 08:40:06 PM PDT 24 |
| Peak memory | 647428 kb |
| Host | smart-ad607085-57de-4660-8b27-c1f6e269051f |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=101143994 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all _escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 89.chip_s w_alert_handler_lpg_sleep_mode_alerts.101143994 |
| Directory | /workspace/89.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/89.chip_sw_all_escalation_resets.1671686325 |
| Short name | T688 |
| Test name | |
| Test status | |
| Simulation time | 5889514540 ps |
| CPU time | 715.73 seconds |
| Started | Jun 28 08:31:50 PM PDT 24 |
| Finished | Jun 28 08:43:57 PM PDT 24 |
| Peak memory | 648036 kb |
| Host | smart-e79dc6e2-a553-458a-9161-0204fe076c5a |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 1671686325 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 89.chip_sw_all_escalation_resets.1671686325 |
| Directory | /workspace/89.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/9.chip_sw_alert_handler_lpg_sleep_mode_alerts.66231888 |
| Short name | T1229 |
| Test name | |
| Test status | |
| Simulation time | 3669014548 ps |
| CPU time | 459.62 seconds |
| Started | Jun 28 08:26:34 PM PDT 24 |
| Finished | Jun 28 08:34:17 PM PDT 24 |
| Peak memory | 642156 kb |
| Host | smart-d9e4659a-cc03-420a-98c5-4212c19721b1 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66231888 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_ escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.chip_sw_ alert_handler_lpg_sleep_mode_alerts.66231888 |
| Directory | /workspace/9.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/9.chip_sw_all_escalation_resets.1704068829 |
| Short name | T85 |
| Test name | |
| Test status | |
| Simulation time | 5583910984 ps |
| CPU time | 660.79 seconds |
| Started | Jun 28 08:28:49 PM PDT 24 |
| Finished | Jun 28 08:40:12 PM PDT 24 |
| Peak memory | 644048 kb |
| Host | smart-289abf62-4006-4b6c-acb2-b43a899c6601 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 1704068829 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.chip_sw_all_escalation_resets.1704068829 |
| Directory | /workspace/9.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/9.chip_sw_csrng_edn_concurrency.3813358102 |
| Short name | T940 |
| Test name | |
| Test status | |
| Simulation time | 8851747666 ps |
| CPU time | 2060.93 seconds |
| Started | Jun 28 08:29:04 PM PDT 24 |
| Finished | Jun 28 09:03:47 PM PDT 24 |
| Peak memory | 608428 kb |
| Host | smart-ad353c06-9af5-4cf6-ad92-7f4e6f89555b |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=140_000_000 +rng_srate_value_min=15 +rng_srate_value_max=20 +accelerate_cold_power_up_time=3 +accelerate_r egulators_power_up_time=2 +sw_build_device=sim_dv +sw_images=csrng_edn_concurrency_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3813358102 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd b -cm_log /dev/null -cm_name 9.chip_sw_csrng_edn_concurrency.3813358102 |
| Directory | /workspace/9.chip_sw_csrng_edn_concurrency/latest |
| Test location | /workspace/coverage/default/9.chip_sw_lc_ctrl_transition.537848380 |
| Short name | T888 |
| Test name | |
| Test status | |
| Simulation time | 7106557905 ps |
| CPU time | 556.98 seconds |
| Started | Jun 28 08:27:59 PM PDT 24 |
| Finished | Jun 28 08:37:17 PM PDT 24 |
| Peak memory | 619152 kb |
| Host | smart-3c5c59a3-3a8a-4c62-9719-e802c24e79dd |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=lc_ctrl_transition_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=537848380 -assert nopostproc +UVM_TEST NAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_transition_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul t.vdb -cm_log /dev/null -cm_name 9.chip_sw_lc_ctrl_transition.537848380 |
| Directory | /workspace/9.chip_sw_lc_ctrl_transition/latest |
| Test location | /workspace/coverage/default/9.chip_sw_uart_rand_baudrate.3418855431 |
| Short name | T294 |
| Test name | |
| Test status | |
| Simulation time | 8464484500 ps |
| CPU time | 1850.04 seconds |
| Started | Jun 28 08:31:34 PM PDT 24 |
| Finished | Jun 28 09:02:38 PM PDT 24 |
| Peak memory | 618308 kb |
| Host | smart-82e07ebb-d050-4872-9dc3-e2beb8953f4d |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=3418855431 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.chip_sw_uart_rand_baudrate.3418855431 |
| Directory | /workspace/9.chip_sw_uart_rand_baudrate/latest |
| Test location | /workspace/coverage/default/90.chip_sw_all_escalation_resets.1758816666 |
| Short name | T356 |
| Test name | |
| Test status | |
| Simulation time | 5335563608 ps |
| CPU time | 715.36 seconds |
| Started | Jun 28 08:32:49 PM PDT 24 |
| Finished | Jun 28 08:44:46 PM PDT 24 |
| Peak memory | 643224 kb |
| Host | smart-3f260a94-ba0c-41eb-bfb6-ef45fed66740 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 1758816666 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 90.chip_sw_all_escalation_resets.1758816666 |
| Directory | /workspace/90.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/91.chip_sw_all_escalation_resets.3400499240 |
| Short name | T710 |
| Test name | |
| Test status | |
| Simulation time | 5950360166 ps |
| CPU time | 681.91 seconds |
| Started | Jun 28 08:34:43 PM PDT 24 |
| Finished | Jun 28 08:46:26 PM PDT 24 |
| Peak memory | 615096 kb |
| Host | smart-0418e03b-2f22-4909-a7e6-38fba9b4868e |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 3400499240 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 91.chip_sw_all_escalation_resets.3400499240 |
| Directory | /workspace/91.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/93.chip_sw_all_escalation_resets.2049009559 |
| Short name | T758 |
| Test name | |
| Test status | |
| Simulation time | 6160442640 ps |
| CPU time | 700.73 seconds |
| Started | Jun 28 08:32:00 PM PDT 24 |
| Finished | Jun 28 08:43:50 PM PDT 24 |
| Peak memory | 643548 kb |
| Host | smart-de4ff429-30fb-453e-8e65-7a3f320ece60 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 2049009559 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 93.chip_sw_all_escalation_resets.2049009559 |
| Directory | /workspace/93.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/94.chip_sw_all_escalation_resets.3202881875 |
| Short name | T772 |
| Test name | |
| Test status | |
| Simulation time | 4480705534 ps |
| CPU time | 605.23 seconds |
| Started | Jun 28 08:32:27 PM PDT 24 |
| Finished | Jun 28 08:42:34 PM PDT 24 |
| Peak memory | 643320 kb |
| Host | smart-9d6354f5-cffc-40ad-8048-af8681687efc |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 3202881875 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 94.chip_sw_all_escalation_resets.3202881875 |
| Directory | /workspace/94.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/95.chip_sw_all_escalation_resets.187209572 |
| Short name | T716 |
| Test name | |
| Test status | |
| Simulation time | 5638400348 ps |
| CPU time | 909.33 seconds |
| Started | Jun 28 08:32:32 PM PDT 24 |
| Finished | Jun 28 08:47:44 PM PDT 24 |
| Peak memory | 643384 kb |
| Host | smart-d9ff9134-59aa-4687-85c1-69009f295a37 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 187209572 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 95.chip_sw_all_escalation_resets.187209572 |
| Directory | /workspace/95.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/96.chip_sw_all_escalation_resets.1292037062 |
| Short name | T271 |
| Test name | |
| Test status | |
| Simulation time | 5221567740 ps |
| CPU time | 747.42 seconds |
| Started | Jun 28 08:33:25 PM PDT 24 |
| Finished | Jun 28 08:45:55 PM PDT 24 |
| Peak memory | 643436 kb |
| Host | smart-818da276-2775-48ac-9e5e-331369e71076 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 1292037062 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 96.chip_sw_all_escalation_resets.1292037062 |
| Directory | /workspace/96.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/97.chip_sw_all_escalation_resets.1394873472 |
| Short name | T1062 |
| Test name | |
| Test status | |
| Simulation time | 4981945464 ps |
| CPU time | 609.66 seconds |
| Started | Jun 28 08:32:47 PM PDT 24 |
| Finished | Jun 28 08:42:58 PM PDT 24 |
| Peak memory | 615112 kb |
| Host | smart-f3ef2f58-beb5-45b1-ad34-9773da939dd2 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 1394873472 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 97.chip_sw_all_escalation_resets.1394873472 |
| Directory | /workspace/97.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/98.chip_sw_all_escalation_resets.2519151808 |
| Short name | T1296 |
| Test name | |
| Test status | |
| Simulation time | 5109550928 ps |
| CPU time | 660.73 seconds |
| Started | Jun 28 08:32:30 PM PDT 24 |
| Finished | Jun 28 08:43:33 PM PDT 24 |
| Peak memory | 643404 kb |
| Host | smart-218c3be9-ebdc-4638-b515-a33de5335396 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 2519151808 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 98.chip_sw_all_escalation_resets.2519151808 |
| Directory | /workspace/98.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/99.chip_sw_all_escalation_resets.4043129185 |
| Short name | T732 |
| Test name | |
| Test status | |
| Simulation time | 4372701896 ps |
| CPU time | 689.58 seconds |
| Started | Jun 28 08:34:48 PM PDT 24 |
| Finished | Jun 28 08:46:39 PM PDT 24 |
| Peak memory | 643400 kb |
| Host | smart-f5f2d436-5efa-4101-91a7-8e9c307c90aa |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 4043129185 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 99.chip_sw_all_escalation_resets.4043129185 |
| Directory | /workspace/99.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/pad_ctrl_test_mode/1.chip_padctrl_attributes.499330735 |
| Short name | T181 |
| Test name | |
| Test status | |
| Simulation time | 5663487548 ps |
| CPU time | 284.74 seconds |
| Started | Jun 28 08:53:16 PM PDT 24 |
| Finished | Jun 28 08:58:11 PM PDT 24 |
| Peak memory | 642400 kb |
| Host | smart-3cab3ebc-68a0-47d1-9ecc-11423d54f291 |
| User | root |
| Command | /workspace/pad_ctrl_test_mode/simv +use_otp_image=OtpTypeLcStProd +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=499330735 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TES T_SEQ=chip_padctrl_attributes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/pad_ctrl_test_mode.vdb -cm_log /dev/n ull -cm_name 1.chip_padctrl_attributes.499330735 |
| Directory | /workspace/1.chip_padctrl_attributes/latest |
| Test location | /workspace/coverage/pad_ctrl_test_mode/2.chip_padctrl_attributes.218621436 |
| Short name | T41 |
| Test name | |
| Test status | |
| Simulation time | 4537187110 ps |
| CPU time | 285.35 seconds |
| Started | Jun 28 08:53:17 PM PDT 24 |
| Finished | Jun 28 08:58:13 PM PDT 24 |
| Peak memory | 640392 kb |
| Host | smart-3d0c04e3-1fa5-4908-8a8e-ac95181d29a0 |
| User | root |
| Command | /workspace/pad_ctrl_test_mode/simv +use_otp_image=OtpTypeLcStProd +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=218621436 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TES T_SEQ=chip_padctrl_attributes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/pad_ctrl_test_mode.vdb -cm_log /dev/n ull -cm_name 2.chip_padctrl_attributes.218621436 |
| Directory | /workspace/2.chip_padctrl_attributes/latest |
| Test location | /workspace/coverage/pad_ctrl_test_mode/4.chip_padctrl_attributes.824620571 |
| Short name | T185 |
| Test name | |
| Test status | |
| Simulation time | 4564047046 ps |
| CPU time | 302.53 seconds |
| Started | Jun 28 08:53:16 PM PDT 24 |
| Finished | Jun 28 08:58:30 PM PDT 24 |
| Peak memory | 640312 kb |
| Host | smart-6a1f263e-f0fa-4ca9-8576-9f2837cbd764 |
| User | root |
| Command | /workspace/pad_ctrl_test_mode/simv +use_otp_image=OtpTypeLcStProd +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=824620571 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TES T_SEQ=chip_padctrl_attributes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/pad_ctrl_test_mode.vdb -cm_log /dev/n ull -cm_name 4.chip_padctrl_attributes.824620571 |
| Directory | /workspace/4.chip_padctrl_attributes/latest |
| Test location | /workspace/coverage/pad_ctrl_test_mode/5.chip_padctrl_attributes.3646409706 |
| Short name | T40 |
| Test name | |
| Test status | |
| Simulation time | 4724322208 ps |
| CPU time | 267.99 seconds |
| Started | Jun 28 08:53:19 PM PDT 24 |
| Finished | Jun 28 08:57:57 PM PDT 24 |
| Peak memory | 640272 kb |
| Host | smart-e28d3afe-36ad-41a7-afee-68ca46ba6c9e |
| User | root |
| Command | /workspace/pad_ctrl_test_mode/simv +use_otp_image=OtpTypeLcStProd +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3646409706 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TE ST_SEQ=chip_padctrl_attributes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/pad_ctrl_test_mode.vdb -cm_log /dev/ null -cm_name 5.chip_padctrl_attributes.3646409706 |
| Directory | /workspace/5.chip_padctrl_attributes/latest |
| Test location | /workspace/coverage/pad_ctrl_test_mode/6.chip_padctrl_attributes.2142305716 |
| Short name | T182 |
| Test name | |
| Test status | |
| Simulation time | 5763266333 ps |
| CPU time | 276.21 seconds |
| Started | Jun 28 08:53:18 PM PDT 24 |
| Finished | Jun 28 08:58:05 PM PDT 24 |
| Peak memory | 656696 kb |
| Host | smart-dc699900-59a2-44ab-bb79-8df78d3c1ef2 |
| User | root |
| Command | /workspace/pad_ctrl_test_mode/simv +use_otp_image=OtpTypeLcStProd +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2142305716 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TE ST_SEQ=chip_padctrl_attributes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/pad_ctrl_test_mode.vdb -cm_log /dev/ null -cm_name 6.chip_padctrl_attributes.2142305716 |
| Directory | /workspace/6.chip_padctrl_attributes/latest |
| Test location | /workspace/coverage/pad_ctrl_test_mode/7.chip_padctrl_attributes.1831059956 |
| Short name | T187 |
| Test name | |
| Test status | |
| Simulation time | 5322256407 ps |
| CPU time | 276.89 seconds |
| Started | Jun 28 08:53:17 PM PDT 24 |
| Finished | Jun 28 08:58:05 PM PDT 24 |
| Peak memory | 640312 kb |
| Host | smart-a4dda1d1-99d2-4cff-b771-473e61b66ecd |
| User | root |
| Command | /workspace/pad_ctrl_test_mode/simv +use_otp_image=OtpTypeLcStProd +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1831059956 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TE ST_SEQ=chip_padctrl_attributes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/pad_ctrl_test_mode.vdb -cm_log /dev/ null -cm_name 7.chip_padctrl_attributes.1831059956 |
| Directory | /workspace/7.chip_padctrl_attributes/latest |
| Test location | /workspace/coverage/pad_ctrl_test_mode/8.chip_padctrl_attributes.2779484947 |
| Short name | T186 |
| Test name | |
| Test status | |
| Simulation time | 4530074138 ps |
| CPU time | 255.35 seconds |
| Started | Jun 28 08:53:17 PM PDT 24 |
| Finished | Jun 28 08:57:44 PM PDT 24 |
| Peak memory | 640240 kb |
| Host | smart-86c5e08c-9232-43c5-8e2b-9be0d4c2e6f7 |
| User | root |
| Command | /workspace/pad_ctrl_test_mode/simv +use_otp_image=OtpTypeLcStProd +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2779484947 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TE ST_SEQ=chip_padctrl_attributes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/pad_ctrl_test_mode.vdb -cm_log /dev/ null -cm_name 8.chip_padctrl_attributes.2779484947 |
| Directory | /workspace/8.chip_padctrl_attributes/latest |
| Test location | /workspace/coverage/pad_ctrl_test_mode/9.chip_padctrl_attributes.10551965 |
| Short name | T184 |
| Test name | |
| Test status | |
| Simulation time | 4530934680 ps |
| CPU time | 247.01 seconds |
| Started | Jun 28 08:53:19 PM PDT 24 |
| Finished | Jun 28 08:57:36 PM PDT 24 |
| Peak memory | 641580 kb |
| Host | smart-0b6de6da-7f79-436b-973c-5dec916b6edf |
| User | root |
| Command | /workspace/pad_ctrl_test_mode/simv +use_otp_image=OtpTypeLcStProd +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10551965 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST _SEQ=chip_padctrl_attributes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/pad_ctrl_test_mode.vdb -cm_log /dev/nu ll -cm_name 9.chip_padctrl_attributes.10551965 |
| Directory | /workspace/9.chip_padctrl_attributes/latest |
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