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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
96.02 95.45 93.64 95.54 94.43 97.53 99.54


Total test records in report: 2884
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T202 /workspace/coverage/default/2.chip_sw_alert_handler_escalation.310904747 Jun 29 07:57:08 PM PDT 24 Jun 29 08:05:50 PM PDT 24 5559059776 ps
T310 /workspace/coverage/default/1.chip_sw_i2c_device_tx_rx.500998421 Jun 29 07:41:43 PM PDT 24 Jun 29 07:52:14 PM PDT 24 4277842344 ps
T690 /workspace/coverage/default/49.chip_sw_all_escalation_resets.1842820342 Jun 29 08:10:04 PM PDT 24 Jun 29 08:22:04 PM PDT 24 4960289964 ps
T116 /workspace/coverage/default/0.chip_sw_csrng_lc_hw_debug_en_test.3792304859 Jun 29 07:41:27 PM PDT 24 Jun 29 07:51:11 PM PDT 24 6718965591 ps
T870 /workspace/coverage/default/2.chip_sw_flash_ctrl_idle_low_power.1198895839 Jun 29 08:00:48 PM PDT 24 Jun 29 08:09:40 PM PDT 24 3678010784 ps
T871 /workspace/coverage/default/1.chip_sw_keymgr_key_derivation.2734451588 Jun 29 07:47:55 PM PDT 24 Jun 29 08:30:59 PM PDT 24 12759420784 ps
T872 /workspace/coverage/default/1.rom_e2e_keymgr_init_rom_ext_no_meas.2875590101 Jun 29 07:56:50 PM PDT 24 Jun 29 08:56:12 PM PDT 24 14817763336 ps
T639 /workspace/coverage/default/2.chip_sw_rv_dm_access_after_escalation_reset.2009288882 Jun 29 08:00:17 PM PDT 24 Jun 29 08:10:08 PM PDT 24 5777578369 ps
T152 /workspace/coverage/default/2.chip_jtag_mem_access.545579291 Jun 29 07:52:39 PM PDT 24 Jun 29 08:15:20 PM PDT 24 13200190754 ps
T65 /workspace/coverage/default/1.chip_tap_straps_testunlock0.3761482226 Jun 29 07:49:15 PM PDT 24 Jun 29 07:54:07 PM PDT 24 4549469966 ps
T645 /workspace/coverage/default/1.chip_sw_lc_ctrl_volatile_raw_unlock.3636317535 Jun 29 07:43:03 PM PDT 24 Jun 29 07:45:01 PM PDT 24 2194118700 ps
T873 /workspace/coverage/default/2.chip_sw_pwrmgr_wdog_reset.1065907020 Jun 29 07:58:02 PM PDT 24 Jun 29 08:11:24 PM PDT 24 4664587856 ps
T190 /workspace/coverage/default/2.chip_sw_i2c_host_tx_rx.1708682951 Jun 29 07:54:29 PM PDT 24 Jun 29 08:07:55 PM PDT 24 4942275334 ps
T688 /workspace/coverage/default/85.chip_sw_alert_handler_lpg_sleep_mode_alerts.780710888 Jun 29 08:13:43 PM PDT 24 Jun 29 08:20:09 PM PDT 24 3734591610 ps
T744 /workspace/coverage/default/87.chip_sw_alert_handler_lpg_sleep_mode_alerts.283620786 Jun 29 08:13:38 PM PDT 24 Jun 29 08:20:40 PM PDT 24 3660254130 ps
T874 /workspace/coverage/default/0.chip_sw_flash_ctrl_write_clear.3777531631 Jun 29 07:41:19 PM PDT 24 Jun 29 07:47:14 PM PDT 24 3017987348 ps
T153 /workspace/coverage/default/1.chip_jtag_mem_access.4012035443 Jun 29 07:42:16 PM PDT 24 Jun 29 08:10:01 PM PDT 24 13951594098 ps
T351 /workspace/coverage/default/83.chip_sw_alert_handler_lpg_sleep_mode_alerts.3974385600 Jun 29 08:14:30 PM PDT 24 Jun 29 08:22:02 PM PDT 24 3892470288 ps
T149 /workspace/coverage/default/0.chip_sw_spi_device_pass_through_collision.1931104028 Jun 29 07:39:23 PM PDT 24 Jun 29 07:49:26 PM PDT 24 4464595505 ps
T180 /workspace/coverage/default/2.chip_sw_flash_init.2897438318 Jun 29 07:54:25 PM PDT 24 Jun 29 08:36:52 PM PDT 24 24062841760 ps
T150 /workspace/coverage/default/1.chip_sw_spi_device_pass_through_collision.3264625290 Jun 29 07:47:25 PM PDT 24 Jun 29 07:55:11 PM PDT 24 4652808140 ps
T875 /workspace/coverage/default/0.chip_sw_otp_ctrl_lc_signals_prod.1376740253 Jun 29 07:39:42 PM PDT 24 Jun 29 07:59:51 PM PDT 24 8591743170 ps
T174 /workspace/coverage/default/0.chip_sw_otp_ctrl_escalation.1689991033 Jun 29 07:39:47 PM PDT 24 Jun 29 07:50:56 PM PDT 24 5644437682 ps
T712 /workspace/coverage/default/29.chip_sw_alert_handler_lpg_sleep_mode_alerts.3774627890 Jun 29 08:09:34 PM PDT 24 Jun 29 08:18:11 PM PDT 24 3324453400 ps
T876 /workspace/coverage/default/0.chip_sw_aes_enc.656357715 Jun 29 07:44:36 PM PDT 24 Jun 29 07:48:59 PM PDT 24 3286403580 ps
T345 /workspace/coverage/default/0.chip_sw_flash_rma_unlocked.826844577 Jun 29 07:36:54 PM PDT 24 Jun 29 09:09:01 PM PDT 24 43651502324 ps
T877 /workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_lc.588291594 Jun 29 07:49:51 PM PDT 24 Jun 29 07:59:56 PM PDT 24 7645263711 ps
T705 /workspace/coverage/default/82.chip_sw_alert_handler_lpg_sleep_mode_alerts.2583003899 Jun 29 08:13:47 PM PDT 24 Jun 29 08:21:36 PM PDT 24 4031517120 ps
T211 /workspace/coverage/default/0.chip_sw_flash_init_reduced_freq.3379580062 Jun 29 07:38:38 PM PDT 24 Jun 29 08:18:07 PM PDT 24 17797443039 ps
T346 /workspace/coverage/default/2.chip_sw_flash_rma_unlocked.3770450305 Jun 29 07:54:02 PM PDT 24 Jun 29 09:30:41 PM PDT 24 44431927211 ps
T878 /workspace/coverage/default/0.chip_sw_hmac_enc_idle.3611169838 Jun 29 07:39:20 PM PDT 24 Jun 29 07:44:29 PM PDT 24 2924421012 ps
T235 /workspace/coverage/default/64.chip_sw_alert_handler_lpg_sleep_mode_alerts.3635061307 Jun 29 08:14:11 PM PDT 24 Jun 29 08:21:47 PM PDT 24 4486564580 ps
T879 /workspace/coverage/default/4.chip_sw_uart_tx_rx_idx3.2095697141 Jun 29 08:06:16 PM PDT 24 Jun 29 08:15:48 PM PDT 24 4310018956 ps
T205 /workspace/coverage/default/0.chip_sw_keymgr_sideload_otbn.2820157061 Jun 29 07:39:47 PM PDT 24 Jun 29 08:54:21 PM PDT 24 15029058200 ps
T880 /workspace/coverage/default/2.chip_sw_aon_timer_wdog_bite_reset.3190307715 Jun 29 07:57:32 PM PDT 24 Jun 29 08:14:54 PM PDT 24 10326113566 ps
T160 /workspace/coverage/default/2.chip_sw_sysrst_ctrl_inputs.2385077730 Jun 29 07:57:22 PM PDT 24 Jun 29 08:01:54 PM PDT 24 3049120311 ps
T134 /workspace/coverage/default/2.chip_sw_sensor_ctrl_status.2359592598 Jun 29 07:59:00 PM PDT 24 Jun 29 08:03:18 PM PDT 24 2390430908 ps
T881 /workspace/coverage/default/2.chip_sw_pwrmgr_deep_sleep_por_reset.4261190233 Jun 29 07:56:31 PM PDT 24 Jun 29 08:05:15 PM PDT 24 8211481320 ps
T312 /workspace/coverage/default/0.chip_sw_pwrmgr_lowpower_cancel.848446537 Jun 29 07:41:02 PM PDT 24 Jun 29 07:47:08 PM PDT 24 3843405788 ps
T671 /workspace/coverage/default/2.chip_sw_rv_core_ibex_nmi_irq.4045245341 Jun 29 07:59:19 PM PDT 24 Jun 29 08:12:52 PM PDT 24 4173992160 ps
T882 /workspace/coverage/default/0.chip_sw_keymgr_key_derivation.649210365 Jun 29 07:39:35 PM PDT 24 Jun 29 08:22:16 PM PDT 24 10776017798 ps
T883 /workspace/coverage/default/0.chip_sw_pwrmgr_sleep_wake_5_bug.400136965 Jun 29 07:40:13 PM PDT 24 Jun 29 07:49:24 PM PDT 24 7629716480 ps
T329 /workspace/coverage/default/0.chip_sw_hmac_enc.1692186772 Jun 29 07:37:05 PM PDT 24 Jun 29 07:41:36 PM PDT 24 2745987160 ps
T302 /workspace/coverage/default/19.chip_sw_uart_rand_baudrate.867225084 Jun 29 08:09:14 PM PDT 24 Jun 29 08:52:56 PM PDT 24 13034199940 ps
T740 /workspace/coverage/default/5.chip_sw_alert_handler_lpg_sleep_mode_alerts.2029842467 Jun 29 08:05:18 PM PDT 24 Jun 29 08:12:09 PM PDT 24 4265406050 ps
T169 /workspace/coverage/default/2.chip_sw_alert_handler_reverse_ping_in_deep_sleep.574932885 Jun 29 07:58:38 PM PDT 24 Jun 29 11:24:19 PM PDT 24 255853728720 ps
T59 /workspace/coverage/default/0.chip_sw_alert_test.2544648161 Jun 29 07:43:20 PM PDT 24 Jun 29 07:49:29 PM PDT 24 3152037300 ps
T884 /workspace/coverage/default/1.rom_e2e_asm_init_dev.509060595 Jun 29 07:54:54 PM PDT 24 Jun 29 09:08:50 PM PDT 24 15921693518 ps
T885 /workspace/coverage/default/0.chip_sw_pwrmgr_sysrst_ctrl_reset.4269837005 Jun 29 07:39:07 PM PDT 24 Jun 29 08:00:57 PM PDT 24 7558273227 ps
T723 /workspace/coverage/default/61.chip_sw_all_escalation_resets.1491773679 Jun 29 08:10:46 PM PDT 24 Jun 29 08:24:17 PM PDT 24 5704800958 ps
T204 /workspace/coverage/default/1.chip_sw_keymgr_sideload_aes.349953703 Jun 29 07:48:05 PM PDT 24 Jun 29 08:12:17 PM PDT 24 7950140664 ps
T886 /workspace/coverage/default/2.chip_sw_hmac_oneshot.4235677547 Jun 29 07:58:16 PM PDT 24 Jun 29 08:05:19 PM PDT 24 3750768008 ps
T660 /workspace/coverage/default/2.chip_sw_plic_sw_irq.810675297 Jun 29 08:00:45 PM PDT 24 Jun 29 08:06:59 PM PDT 24 3033467468 ps
T322 /workspace/coverage/default/0.chip_sw_pattgen_ios.2320193182 Jun 29 07:39:36 PM PDT 24 Jun 29 07:43:57 PM PDT 24 2648127000 ps
T303 /workspace/coverage/default/15.chip_sw_uart_rand_baudrate.2809965568 Jun 29 08:07:04 PM PDT 24 Jun 29 08:33:38 PM PDT 24 8486270808 ps
T121 /workspace/coverage/default/1.chip_sw_sensor_ctrl_alert.1014409494 Jun 29 07:48:14 PM PDT 24 Jun 29 07:58:09 PM PDT 24 5750657180 ps
T725 /workspace/coverage/default/68.chip_sw_alert_handler_lpg_sleep_mode_alerts.2042925568 Jun 29 08:12:44 PM PDT 24 Jun 29 08:20:35 PM PDT 24 3364930324 ps
T9 /workspace/coverage/default/0.chip_sw_sleep_pin_retention.2830015827 Jun 29 07:42:45 PM PDT 24 Jun 29 07:48:43 PM PDT 24 3406304840 ps
T251 /workspace/coverage/default/2.chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq.3488215410 Jun 29 08:01:13 PM PDT 24 Jun 29 08:11:54 PM PDT 24 5588035894 ps
T392 /workspace/coverage/default/2.chip_sw_pwrmgr_deep_sleep_power_glitch_reset.1376925114 Jun 29 07:55:39 PM PDT 24 Jun 29 08:02:34 PM PDT 24 6563982374 ps
T393 /workspace/coverage/default/2.chip_sw_uart_tx_rx.4218928941 Jun 29 07:53:49 PM PDT 24 Jun 29 08:07:18 PM PDT 24 5083488658 ps
T394 /workspace/coverage/default/1.chip_sw_aon_timer_wdog_lc_escalate.1553063837 Jun 29 07:43:20 PM PDT 24 Jun 29 07:54:07 PM PDT 24 5496647740 ps
T395 /workspace/coverage/default/0.rom_e2e_asm_init_test_unlocked0.1351709846 Jun 29 07:44:48 PM PDT 24 Jun 29 08:38:48 PM PDT 24 11058493670 ps
T396 /workspace/coverage/default/2.chip_sw_otbn_smoketest.313582828 Jun 29 08:02:19 PM PDT 24 Jun 29 08:39:41 PM PDT 24 10778424956 ps
T397 /workspace/coverage/default/10.chip_sw_lc_ctrl_transition.528608975 Jun 29 08:06:16 PM PDT 24 Jun 29 08:19:52 PM PDT 24 9685602208 ps
T398 /workspace/coverage/default/2.chip_sw_flash_ctrl_mem_protection.1600007620 Jun 29 08:05:12 PM PDT 24 Jun 29 08:26:24 PM PDT 24 6250798500 ps
T399 /workspace/coverage/default/43.chip_sw_alert_handler_lpg_sleep_mode_alerts.733030775 Jun 29 08:09:59 PM PDT 24 Jun 29 08:17:16 PM PDT 24 3027735594 ps
T208 /workspace/coverage/default/2.chip_sw_lc_walkthrough_dev.285349702 Jun 29 07:55:50 PM PDT 24 Jun 29 09:31:01 PM PDT 24 49861733480 ps
T66 /workspace/coverage/default/1.chip_tap_straps_rma.784532627 Jun 29 07:50:07 PM PDT 24 Jun 29 07:59:59 PM PDT 24 6271567494 ps
T279 /workspace/coverage/default/49.chip_sw_alert_handler_lpg_sleep_mode_alerts.1966848300 Jun 29 08:11:15 PM PDT 24 Jun 29 08:18:27 PM PDT 24 3133968384 ps
T887 /workspace/coverage/default/1.chip_sw_keymgr_key_derivation_prod.2401076487 Jun 29 07:46:29 PM PDT 24 Jun 29 08:14:27 PM PDT 24 10520755160 ps
T888 /workspace/coverage/default/34.chip_sw_alert_handler_lpg_sleep_mode_alerts.615355078 Jun 29 08:09:57 PM PDT 24 Jun 29 08:18:05 PM PDT 24 3804880956 ps
T889 /workspace/coverage/default/2.chip_sw_clkmgr_off_kmac_trans.853754646 Jun 29 07:59:55 PM PDT 24 Jun 29 08:07:37 PM PDT 24 4882448800 ps
T890 /workspace/coverage/default/7.chip_sw_csrng_edn_concurrency.3486454078 Jun 29 08:06:05 PM PDT 24 Jun 29 10:10:26 PM PDT 24 35185982708 ps
T891 /workspace/coverage/default/3.chip_sw_uart_tx_rx.1693212596 Jun 29 08:03:04 PM PDT 24 Jun 29 08:13:52 PM PDT 24 4421244604 ps
T718 /workspace/coverage/default/16.chip_sw_all_escalation_resets.135378099 Jun 29 08:07:25 PM PDT 24 Jun 29 08:17:20 PM PDT 24 5749900000 ps
T41 /workspace/coverage/default/2.chip_sw_spi_host_tx_rx.1079276720 Jun 29 07:55:24 PM PDT 24 Jun 29 08:00:43 PM PDT 24 2674426800 ps
T188 /workspace/coverage/default/1.chip_sw_rv_core_ibex_address_translation.2738195101 Jun 29 07:50:20 PM PDT 24 Jun 29 07:55:00 PM PDT 24 2821801692 ps
T892 /workspace/coverage/default/0.chip_sw_entropy_src_ast_rng_req.3978738503 Jun 29 07:38:25 PM PDT 24 Jun 29 07:43:37 PM PDT 24 2385409182 ps
T108 /workspace/coverage/default/0.chip_sw_csrng_edn_concurrency_reduced_freq.210093800 Jun 29 07:45:14 PM PDT 24 Jun 29 10:25:13 PM PDT 24 55623873088 ps
T893 /workspace/coverage/default/2.chip_sw_lc_walkthrough_prodend.136763417 Jun 29 07:56:19 PM PDT 24 Jun 29 08:13:11 PM PDT 24 8998584168 ps
T252 /workspace/coverage/default/0.chip_sw_data_integrity_escalation.428271711 Jun 29 07:41:29 PM PDT 24 Jun 29 07:54:56 PM PDT 24 5703958612 ps
T10 /workspace/coverage/default/1.chip_sw_sleep_pin_retention.1559646039 Jun 29 07:42:52 PM PDT 24 Jun 29 07:50:37 PM PDT 24 4005025650 ps
T894 /workspace/coverage/default/8.chip_sw_lc_ctrl_transition.3255201508 Jun 29 08:06:48 PM PDT 24 Jun 29 08:24:41 PM PDT 24 9973936889 ps
T646 /workspace/coverage/default/0.rom_volatile_raw_unlock.1258527833 Jun 29 07:42:12 PM PDT 24 Jun 29 07:44:09 PM PDT 24 2291109954 ps
T386 /workspace/coverage/default/98.chip_sw_all_escalation_resets.1789691997 Jun 29 08:14:39 PM PDT 24 Jun 29 08:26:11 PM PDT 24 6175984660 ps
T280 /workspace/coverage/default/32.chip_sw_alert_handler_lpg_sleep_mode_alerts.2283139196 Jun 29 08:08:56 PM PDT 24 Jun 29 08:16:48 PM PDT 24 3851439716 ps
T895 /workspace/coverage/default/0.chip_sw_example_concurrency.1218753369 Jun 29 07:38:50 PM PDT 24 Jun 29 07:42:43 PM PDT 24 3294866200 ps
T896 /workspace/coverage/default/3.chip_sw_uart_rand_baudrate.856757054 Jun 29 08:03:57 PM PDT 24 Jun 29 08:16:46 PM PDT 24 4584634968 ps
T264 /workspace/coverage/default/1.chip_sw_rv_core_ibex_icache_invalidate.3762567310 Jun 29 07:51:34 PM PDT 24 Jun 29 07:54:56 PM PDT 24 2318761000 ps
T897 /workspace/coverage/default/0.chip_sw_hmac_oneshot.1403068770 Jun 29 07:38:59 PM PDT 24 Jun 29 07:44:39 PM PDT 24 3312209086 ps
T711 /workspace/coverage/default/28.chip_sw_alert_handler_lpg_sleep_mode_alerts.1623531316 Jun 29 08:08:30 PM PDT 24 Jun 29 08:15:10 PM PDT 24 4039401848 ps
T719 /workspace/coverage/default/55.chip_sw_alert_handler_lpg_sleep_mode_alerts.4145134653 Jun 29 08:10:43 PM PDT 24 Jun 29 08:16:47 PM PDT 24 3702491056 ps
T898 /workspace/coverage/default/1.chip_sw_aes_masking_off.2619670547 Jun 29 07:44:00 PM PDT 24 Jun 29 07:48:40 PM PDT 24 3536779394 ps
T751 /workspace/coverage/default/4.chip_sw_all_escalation_resets.15656359 Jun 29 08:05:01 PM PDT 24 Jun 29 08:18:32 PM PDT 24 6193274338 ps
T335 /workspace/coverage/default/37.chip_sw_all_escalation_resets.3741872749 Jun 29 08:09:24 PM PDT 24 Jun 29 08:19:04 PM PDT 24 4502848634 ps
T694 /workspace/coverage/default/23.chip_sw_alert_handler_lpg_sleep_mode_alerts.1196819450 Jun 29 08:07:11 PM PDT 24 Jun 29 08:12:56 PM PDT 24 3367881720 ps
T35 /workspace/coverage/default/2.chip_sw_gpio.2786171915 Jun 29 07:54:14 PM PDT 24 Jun 29 08:01:59 PM PDT 24 3583010464 ps
T650 /workspace/coverage/default/50.chip_sw_all_escalation_resets.2585163368 Jun 29 08:09:26 PM PDT 24 Jun 29 08:19:34 PM PDT 24 4944061560 ps
T209 /workspace/coverage/default/0.chip_sw_flash_init.4293808922 Jun 29 07:38:25 PM PDT 24 Jun 29 08:07:14 PM PDT 24 18738447784 ps
T761 /workspace/coverage/default/56.chip_sw_alert_handler_lpg_sleep_mode_alerts.1231279756 Jun 29 08:11:06 PM PDT 24 Jun 29 08:17:56 PM PDT 24 3613496624 ps
T899 /workspace/coverage/default/0.rom_e2e_asm_init_prod.3899137295 Jun 29 07:45:17 PM PDT 24 Jun 29 08:53:12 PM PDT 24 15554153850 ps
T210 /workspace/coverage/default/0.chip_sw_lc_walkthrough_dev.581909962 Jun 29 07:39:32 PM PDT 24 Jun 29 09:07:51 PM PDT 24 49081354977 ps
T296 /workspace/coverage/default/2.chip_sw_rstmgr_alert_info.846460994 Jun 29 07:57:12 PM PDT 24 Jun 29 08:32:20 PM PDT 24 15234875888 ps
T643 /workspace/coverage/default/3.chip_tap_straps_dev.1864283242 Jun 29 08:02:19 PM PDT 24 Jun 29 08:18:58 PM PDT 24 9164233116 ps
T745 /workspace/coverage/default/61.chip_sw_alert_handler_lpg_sleep_mode_alerts.2215164005 Jun 29 08:12:25 PM PDT 24 Jun 29 08:18:19 PM PDT 24 3813613274 ps
T148 /workspace/coverage/default/0.chip_sw_spi_device_pass_through.3701675615 Jun 29 07:38:41 PM PDT 24 Jun 29 07:52:23 PM PDT 24 7260716774 ps
T716 /workspace/coverage/default/89.chip_sw_alert_handler_lpg_sleep_mode_alerts.2567068275 Jun 29 08:13:54 PM PDT 24 Jun 29 08:21:53 PM PDT 24 4507429200 ps
T900 /workspace/coverage/default/1.chip_sw_lc_ctrl_otp_hw_cfg0.2711202799 Jun 29 07:44:17 PM PDT 24 Jun 29 07:48:30 PM PDT 24 3042302820 ps
T901 /workspace/coverage/default/0.chip_sw_lc_walkthrough_prodend.2101674328 Jun 29 07:39:00 PM PDT 24 Jun 29 07:53:35 PM PDT 24 8066858137 ps
T306 /workspace/coverage/default/0.chip_sw_uart_tx_rx_idx1.1192150036 Jun 29 07:37:17 PM PDT 24 Jun 29 07:46:24 PM PDT 24 4082333126 ps
T902 /workspace/coverage/default/1.chip_sw_csrng_smoketest.2679183862 Jun 29 07:52:32 PM PDT 24 Jun 29 07:57:25 PM PDT 24 2757038190 ps
T903 /workspace/coverage/default/0.chip_sw_flash_ctrl_mem_protection.1671303708 Jun 29 07:44:29 PM PDT 24 Jun 29 08:05:18 PM PDT 24 5445523480 ps
T904 /workspace/coverage/default/1.chip_sw_kmac_mode_cshake.4003439376 Jun 29 07:46:38 PM PDT 24 Jun 29 07:51:25 PM PDT 24 2525746598 ps
T304 /workspace/coverage/default/2.chip_sw_i2c_host_tx_rx_idx2.3920734878 Jun 29 07:56:02 PM PDT 24 Jun 29 08:09:10 PM PDT 24 4876084734 ps
T293 /workspace/coverage/default/2.chip_sw_i2c_host_tx_rx_idx1.1692672029 Jun 29 07:54:10 PM PDT 24 Jun 29 08:09:33 PM PDT 24 4481415602 ps
T905 /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0.4176295028 Jun 29 07:43:34 PM PDT 24 Jun 29 08:35:41 PM PDT 24 11336285368 ps
T769 /workspace/coverage/default/8.chip_sw_alert_handler_lpg_sleep_mode_alerts.3227394658 Jun 29 08:06:06 PM PDT 24 Jun 29 08:12:59 PM PDT 24 3896195392 ps
T906 /workspace/coverage/default/2.chip_sw_clkmgr_off_otbn_trans.4097351566 Jun 29 07:59:27 PM PDT 24 Jun 29 08:08:54 PM PDT 24 5672779220 ps
T752 /workspace/coverage/default/1.chip_sw_all_escalation_resets.1496644852 Jun 29 07:43:06 PM PDT 24 Jun 29 07:54:05 PM PDT 24 5056512860 ps
T907 /workspace/coverage/default/2.rom_e2e_asm_init_rma.3396944141 Jun 29 08:13:48 PM PDT 24 Jun 29 09:25:18 PM PDT 24 15043033839 ps
T908 /workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_slow_dev.3215489948 Jun 29 07:48:32 PM PDT 24 Jun 29 07:59:28 PM PDT 24 4303095512 ps
T383 /workspace/coverage/default/2.chip_sw_rom_ctrl_integrity_check.492826557 Jun 29 07:58:46 PM PDT 24 Jun 29 08:06:38 PM PDT 24 9641994326 ps
T909 /workspace/coverage/default/1.chip_sw_flash_ctrl_write_clear.1354245784 Jun 29 07:50:31 PM PDT 24 Jun 29 07:56:34 PM PDT 24 2584391400 ps
T43 /workspace/coverage/default/2.chip_sw_sysrst_ctrl_ulp_z3_wakeup.3513751950 Jun 29 07:56:04 PM PDT 24 Jun 29 08:01:03 PM PDT 24 5949564766 ps
T370 /workspace/coverage/default/2.chip_sw_csrng_lc_hw_debug_en_test.1105064070 Jun 29 07:59:17 PM PDT 24 Jun 29 08:12:34 PM PDT 24 6549318140 ps
T910 /workspace/coverage/default/4.chip_sw_uart_tx_rx.410356677 Jun 29 08:04:54 PM PDT 24 Jun 29 08:16:06 PM PDT 24 4345559056 ps
T307 /workspace/coverage/default/14.chip_sw_uart_rand_baudrate.2041373995 Jun 29 08:06:52 PM PDT 24 Jun 29 08:15:45 PM PDT 24 3668639182 ps
T156 /workspace/coverage/default/0.chip_sw_inject_scramble_seed.2298678643 Jun 29 07:36:42 PM PDT 24 Jun 29 10:58:25 PM PDT 24 65426291752 ps
T911 /workspace/coverage/default/0.chip_tap_straps_testunlock0.1486566793 Jun 29 07:40:32 PM PDT 24 Jun 29 07:42:58 PM PDT 24 2686775037 ps
T85 /workspace/coverage/default/13.chip_sw_all_escalation_resets.3668400139 Jun 29 08:06:58 PM PDT 24 Jun 29 08:17:48 PM PDT 24 5229848180 ps
T912 /workspace/coverage/default/1.chip_sw_sram_ctrl_smoketest.2754546932 Jun 29 07:53:15 PM PDT 24 Jun 29 07:58:31 PM PDT 24 3013200168 ps
T71 /workspace/coverage/default/0.chip_sw_usbdev_aon_pullup.750717036 Jun 29 07:36:27 PM PDT 24 Jun 29 07:42:51 PM PDT 24 3899786932 ps
T913 /workspace/coverage/default/1.chip_sw_pwrmgr_sysrst_ctrl_reset.643165848 Jun 29 07:42:01 PM PDT 24 Jun 29 08:04:31 PM PDT 24 6802297605 ps
T377 /workspace/coverage/default/2.chip_sw_clkmgr_off_peri.3441503536 Jun 29 07:59:58 PM PDT 24 Jun 29 08:16:32 PM PDT 24 9355797904 ps
T914 /workspace/coverage/default/1.chip_sw_otp_ctrl_lc_signals_prod.2898793529 Jun 29 07:48:04 PM PDT 24 Jun 29 08:06:27 PM PDT 24 6895962840 ps
T915 /workspace/coverage/default/1.chip_sw_csrng_lc_hw_debug_en_test.4224207162 Jun 29 07:45:31 PM PDT 24 Jun 29 07:56:38 PM PDT 24 7603750980 ps
T916 /workspace/coverage/default/50.chip_sw_alert_handler_lpg_sleep_mode_alerts.3653162477 Jun 29 08:10:39 PM PDT 24 Jun 29 08:17:11 PM PDT 24 3238347782 ps
T917 /workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0.3536353555 Jun 29 08:00:10 PM PDT 24 Jun 29 08:11:52 PM PDT 24 4565078000 ps
T647 /workspace/coverage/default/1.chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz.15640720 Jun 29 07:44:48 PM PDT 24 Jun 29 07:46:46 PM PDT 24 2802709869 ps
T918 /workspace/coverage/default/0.chip_sw_otp_ctrl_lc_signals_rma.490259674 Jun 29 07:39:42 PM PDT 24 Jun 29 07:58:13 PM PDT 24 8655173892 ps
T378 /workspace/coverage/default/1.chip_sw_clkmgr_off_peri.2931436037 Jun 29 07:48:29 PM PDT 24 Jun 29 08:10:03 PM PDT 24 10793052568 ps
T919 /workspace/coverage/default/2.chip_sw_kmac_mode_kmac_jitter_en.3192139551 Jun 29 07:58:54 PM PDT 24 Jun 29 08:04:25 PM PDT 24 3200494663 ps
T920 /workspace/coverage/default/9.chip_sw_csrng_edn_concurrency.3658983633 Jun 29 08:06:50 PM PDT 24 Jun 29 09:26:03 PM PDT 24 20413842638 ps
T330 /workspace/coverage/default/0.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.822980154 Jun 29 07:39:21 PM PDT 24 Jun 29 08:11:27 PM PDT 24 13249184143 ps
T921 /workspace/coverage/default/1.chip_sw_example_flash.1118946011 Jun 29 07:39:58 PM PDT 24 Jun 29 07:44:23 PM PDT 24 3233093820 ps
T31 /workspace/coverage/default/1.chip_sw_sysrst_ctrl_ec_rst_l.558083588 Jun 29 07:44:34 PM PDT 24 Jun 29 08:43:28 PM PDT 24 21209311943 ps
T384 /workspace/coverage/default/2.chip_sw_kmac_app_rom.4134812589 Jun 29 07:58:36 PM PDT 24 Jun 29 08:02:43 PM PDT 24 2260109950 ps
T213 /workspace/coverage/default/1.chip_sw_flash_ctrl_lc_rw_en.3777306395 Jun 29 07:40:49 PM PDT 24 Jun 29 07:51:36 PM PDT 24 5324510952 ps
T922 /workspace/coverage/default/7.chip_sw_uart_rand_baudrate.929173458 Jun 29 08:05:40 PM PDT 24 Jun 29 08:16:29 PM PDT 24 4028915342 ps
T331 /workspace/coverage/default/4.chip_sw_uart_tx_rx_idx1.3292670475 Jun 29 08:04:18 PM PDT 24 Jun 29 08:14:17 PM PDT 24 3991461132 ps
T923 /workspace/coverage/default/2.chip_sw_gpio_smoketest.1827870690 Jun 29 08:05:58 PM PDT 24 Jun 29 08:10:13 PM PDT 24 2699023615 ps
T924 /workspace/coverage/default/1.chip_sw_flash_ctrl_access_jitter_en_reduced_freq.3925820934 Jun 29 07:51:33 PM PDT 24 Jun 29 08:10:58 PM PDT 24 7381618110 ps
T925 /workspace/coverage/default/2.chip_sw_flash_ctrl_write_clear.349334662 Jun 29 08:00:56 PM PDT 24 Jun 29 08:08:27 PM PDT 24 3082432310 ps
T657 /workspace/coverage/default/1.chip_sw_pwrmgr_sleep_disabled.4183011645 Jun 29 07:44:10 PM PDT 24 Jun 29 07:48:16 PM PDT 24 3051823384 ps
T926 /workspace/coverage/default/0.chip_sw_aes_entropy.3753178241 Jun 29 07:46:51 PM PDT 24 Jun 29 07:51:09 PM PDT 24 3168480870 ps
T343 /workspace/coverage/default/2.chip_sw_hmac_enc_jitter_en_reduced_freq.50435007 Jun 29 08:01:27 PM PDT 24 Jun 29 08:07:04 PM PDT 24 3360734753 ps
T325 /workspace/coverage/default/43.chip_sw_all_escalation_resets.3318870413 Jun 29 08:10:45 PM PDT 24 Jun 29 08:19:51 PM PDT 24 5096458844 ps
T338 /workspace/coverage/default/96.chip_sw_all_escalation_resets.2137948047 Jun 29 08:13:47 PM PDT 24 Jun 29 08:21:07 PM PDT 24 4313393380 ps
T161 /workspace/coverage/default/0.chip_sw_sysrst_ctrl_outputs.3220527880 Jun 29 07:39:35 PM PDT 24 Jun 29 07:44:27 PM PDT 24 3781687248 ps
T265 /workspace/coverage/default/2.chip_sw_rv_core_ibex_address_translation.2171082639 Jun 29 08:01:39 PM PDT 24 Jun 29 08:06:12 PM PDT 24 2776679062 ps
T927 /workspace/coverage/default/1.chip_sw_gpio_smoketest.4205484685 Jun 29 07:55:03 PM PDT 24 Jun 29 08:00:03 PM PDT 24 3080290181 ps
T928 /workspace/coverage/default/1.chip_sw_clkmgr_jitter.3028135102 Jun 29 07:48:03 PM PDT 24 Jun 29 07:50:55 PM PDT 24 2440152429 ps
T166 /workspace/coverage/default/0.chip_plic_all_irqs_10.1677499675 Jun 29 07:42:51 PM PDT 24 Jun 29 07:52:40 PM PDT 24 4281372072 ps
T212 /workspace/coverage/default/1.chip_sw_lc_walkthrough_rma.1068464439 Jun 29 07:41:12 PM PDT 24 Jun 29 09:05:54 PM PDT 24 45709871868 ps
T46 /workspace/coverage/default/1.chip_sw_spi_device_tpm.957652738 Jun 29 07:41:14 PM PDT 24 Jun 29 07:46:43 PM PDT 24 3570526306 ps
T755 /workspace/coverage/default/78.chip_sw_all_escalation_resets.309479367 Jun 29 08:12:38 PM PDT 24 Jun 29 08:22:27 PM PDT 24 5031454148 ps
T929 /workspace/coverage/default/0.chip_sw_lc_walkthrough_testunlocks.3871846100 Jun 29 07:37:57 PM PDT 24 Jun 29 08:24:43 PM PDT 24 27434217173 ps
T930 /workspace/coverage/default/1.chip_sw_pwrmgr_wdog_reset.3478120344 Jun 29 07:43:54 PM PDT 24 Jun 29 07:49:50 PM PDT 24 3491599320 ps
T763 /workspace/coverage/default/40.chip_sw_alert_handler_lpg_sleep_mode_alerts.1289979333 Jun 29 08:09:10 PM PDT 24 Jun 29 08:15:51 PM PDT 24 3911515488 ps
T372 /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0.1558198188 Jun 29 07:42:34 PM PDT 24 Jun 29 09:04:18 PM PDT 24 18251630796 ps
T931 /workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0.2573825986 Jun 29 07:37:49 PM PDT 24 Jun 29 07:48:33 PM PDT 24 4060569346 ps
T734 /workspace/coverage/default/32.chip_sw_all_escalation_resets.4244111542 Jun 29 08:09:13 PM PDT 24 Jun 29 08:23:50 PM PDT 24 5168711726 ps
T932 /workspace/coverage/default/2.chip_sw_flash_ctrl_access_jitter_en_reduced_freq.2501510368 Jun 29 08:02:01 PM PDT 24 Jun 29 08:23:30 PM PDT 24 7396147425 ps
T933 /workspace/coverage/default/0.chip_sw_kmac_smoketest.2707397030 Jun 29 07:39:13 PM PDT 24 Jun 29 07:43:54 PM PDT 24 2749845824 ps
T934 /workspace/coverage/default/2.rom_e2e_static_critical.2305462607 Jun 29 08:06:12 PM PDT 24 Jun 29 09:15:55 PM PDT 24 16899361668 ps
T298 /workspace/coverage/default/1.chip_sw_entropy_src_csrng.3471565195 Jun 29 07:45:25 PM PDT 24 Jun 29 08:10:17 PM PDT 24 7487207850 ps
T935 /workspace/coverage/default/1.chip_sw_kmac_mode_kmac_jitter_en.1463588916 Jun 29 07:46:52 PM PDT 24 Jun 29 07:50:52 PM PDT 24 2751020769 ps
T936 /workspace/coverage/default/0.chip_sw_sram_ctrl_smoketest.574461000 Jun 29 07:41:10 PM PDT 24 Jun 29 07:44:46 PM PDT 24 3130581640 ps
T937 /workspace/coverage/default/0.chip_sw_entropy_src_smoketest.528190780 Jun 29 07:41:23 PM PDT 24 Jun 29 07:53:54 PM PDT 24 4438364440 ps
T332 /workspace/coverage/default/2.chip_sw_pattgen_ios.560934222 Jun 29 07:53:10 PM PDT 24 Jun 29 07:58:55 PM PDT 24 3151910192 ps
T938 /workspace/coverage/default/0.chip_sw_example_manufacturer.2694255600 Jun 29 07:38:12 PM PDT 24 Jun 29 07:41:35 PM PDT 24 2594550144 ps
T758 /workspace/coverage/default/42.chip_sw_alert_handler_lpg_sleep_mode_alerts.3368992563 Jun 29 08:09:40 PM PDT 24 Jun 29 08:16:51 PM PDT 24 3717301504 ps
T939 /workspace/coverage/default/2.chip_sw_otp_ctrl_lc_signals_rma.2184091032 Jun 29 07:55:26 PM PDT 24 Jun 29 08:16:05 PM PDT 24 8072239484 ps
T220 /workspace/coverage/default/0.chip_sw_all_escalation_resets.2877012506 Jun 29 07:43:28 PM PDT 24 Jun 29 07:56:23 PM PDT 24 5078848588 ps
T135 /workspace/coverage/default/0.chip_sw_sensor_ctrl_status.3153836537 Jun 29 07:39:51 PM PDT 24 Jun 29 07:43:35 PM PDT 24 2710440686 ps
T940 /workspace/coverage/default/1.chip_sw_uart_tx_rx_alt_clk_freq.556479794 Jun 29 07:41:18 PM PDT 24 Jun 29 08:09:31 PM PDT 24 8034849186 ps
T124 /workspace/coverage/default/3.chip_sw_sensor_ctrl_alert.1449382156 Jun 29 08:03:21 PM PDT 24 Jun 29 08:13:52 PM PDT 24 5292217680 ps
T60 /workspace/coverage/default/2.chip_sw_alert_test.3389606554 Jun 29 07:57:21 PM PDT 24 Jun 29 08:05:25 PM PDT 24 2863498500 ps
T941 /workspace/coverage/default/0.chip_sw_aes_masking_off.19508339 Jun 29 07:39:18 PM PDT 24 Jun 29 07:44:47 PM PDT 24 2830520623 ps
T216 /workspace/coverage/default/0.chip_sw_lc_walkthrough_prod.2993191961 Jun 29 07:41:44 PM PDT 24 Jun 29 09:26:05 PM PDT 24 47992962734 ps
T942 /workspace/coverage/default/0.chip_sw_aon_timer_smoketest.1083544719 Jun 29 07:44:51 PM PDT 24 Jun 29 07:48:54 PM PDT 24 2252119424 ps
T288 /workspace/coverage/default/0.chip_plic_all_irqs_20.1331138773 Jun 29 07:38:31 PM PDT 24 Jun 29 07:51:00 PM PDT 24 5070554700 ps
T232 /workspace/coverage/default/0.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted.3027558522 Jun 29 07:40:13 PM PDT 24 Jun 29 07:48:09 PM PDT 24 4242840748 ps
T253 /workspace/coverage/default/0.chip_sw_otbn_mem_scramble.843500530 Jun 29 07:39:55 PM PDT 24 Jun 29 07:47:23 PM PDT 24 4060721218 ps
T943 /workspace/coverage/default/0.chip_sw_flash_ctrl_access_jitter_en_reduced_freq.3970044125 Jun 29 07:40:56 PM PDT 24 Jun 29 08:04:12 PM PDT 24 7201283161 ps
T944 /workspace/coverage/default/0.chip_sw_hmac_smoketest.4241323295 Jun 29 07:39:48 PM PDT 24 Jun 29 07:46:08 PM PDT 24 3184518378 ps
T945 /workspace/coverage/default/2.rom_e2e_keymgr_init_rom_ext_no_meas.3836557466 Jun 29 08:07:04 PM PDT 24 Jun 29 09:18:02 PM PDT 24 14727511076 ps
T946 /workspace/coverage/default/0.chip_sw_pwrmgr_random_sleep_power_glitch_reset.2988192615 Jun 29 07:38:33 PM PDT 24 Jun 29 08:47:09 PM PDT 24 40931817436 ps
T122 /workspace/coverage/default/2.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup.2307998600 Jun 29 08:00:19 PM PDT 24 Jun 29 08:08:55 PM PDT 24 5384057260 ps
T754 /workspace/coverage/default/58.chip_sw_alert_handler_lpg_sleep_mode_alerts.952144246 Jun 29 08:11:55 PM PDT 24 Jun 29 08:17:37 PM PDT 24 3637826300 ps
T214 /workspace/coverage/default/2.chip_sw_flash_ctrl_lc_rw_en.2209867691 Jun 29 07:54:59 PM PDT 24 Jun 29 08:02:44 PM PDT 24 5457273745 ps
T947 /workspace/coverage/default/1.rom_e2e_keymgr_init_rom_ext_invalid_meas.2126394832 Jun 29 08:03:55 PM PDT 24 Jun 29 09:00:59 PM PDT 24 14876919100 ps
T217 /workspace/coverage/default/1.chip_sw_lc_walkthrough_dev.1964836485 Jun 29 07:41:51 PM PDT 24 Jun 29 09:17:23 PM PDT 24 46960441552 ps
T736 /workspace/coverage/default/6.chip_sw_alert_handler_lpg_sleep_mode_alerts.3434529830 Jun 29 08:05:33 PM PDT 24 Jun 29 08:12:44 PM PDT 24 3667087000 ps
T948 /workspace/coverage/default/2.chip_sw_kmac_smoketest.1123022114 Jun 29 08:02:49 PM PDT 24 Jun 29 08:07:21 PM PDT 24 3307120934 ps
T949 /workspace/coverage/default/1.chip_sw_clkmgr_jitter_reduced_freq.1398343158 Jun 29 07:51:44 PM PDT 24 Jun 29 07:55:04 PM PDT 24 3539735607 ps
T367 /workspace/coverage/default/0.chip_sw_rstmgr_sw_rst.1567623525 Jun 29 07:39:44 PM PDT 24 Jun 29 07:42:37 PM PDT 24 2821122728 ps
T308 /workspace/coverage/default/0.chip_sw_i2c_host_tx_rx.2505750378 Jun 29 07:38:20 PM PDT 24 Jun 29 07:52:12 PM PDT 24 5547866140 ps
T445 /workspace/coverage/default/2.chip_sw_alert_handler_lpg_clkoff.2278513636 Jun 29 07:59:03 PM PDT 24 Jun 29 08:33:22 PM PDT 24 8227991522 ps
T328 /workspace/coverage/default/1.chip_sw_sensor_ctrl_status.3649401190 Jun 29 07:48:06 PM PDT 24 Jun 29 07:52:34 PM PDT 24 3229462979 ps
T950 /workspace/coverage/default/2.chip_sw_pwrmgr_random_sleep_power_glitch_reset.984951110 Jun 29 07:57:58 PM PDT 24 Jun 29 08:56:17 PM PDT 24 34162950588 ps
T951 /workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_fast_dev.691374463 Jun 29 07:48:55 PM PDT 24 Jun 29 08:01:27 PM PDT 24 4109726474 ps
T178 /workspace/coverage/default/1.chip_sw_lc_ctrl_program_error.1991202349 Jun 29 07:49:43 PM PDT 24 Jun 29 07:58:01 PM PDT 24 4747011044 ps
T658 /workspace/coverage/default/2.chip_sw_pwrmgr_sleep_disabled.3471929669 Jun 29 07:56:34 PM PDT 24 Jun 29 08:01:51 PM PDT 24 3496173228 ps
T737 /workspace/coverage/default/24.chip_sw_alert_handler_lpg_sleep_mode_alerts.1363949125 Jun 29 08:09:02 PM PDT 24 Jun 29 08:15:14 PM PDT 24 3689822120 ps
T952 /workspace/coverage/default/0.chip_sw_clkmgr_jitter_reduced_freq.158461398 Jun 29 07:39:49 PM PDT 24 Jun 29 07:43:32 PM PDT 24 2535072573 ps
T215 /workspace/coverage/default/2.chip_sw_flash_init_reduced_freq.2264813070 Jun 29 08:01:42 PM PDT 24 Jun 29 08:36:02 PM PDT 24 22240916350 ps
T179 /workspace/coverage/default/2.chip_sw_lc_ctrl_program_error.3389152802 Jun 29 07:59:55 PM PDT 24 Jun 29 08:08:13 PM PDT 24 4997673008 ps
T953 /workspace/coverage/default/2.chip_sw_keymgr_key_derivation_prod.1255850737 Jun 29 07:58:12 PM PDT 24 Jun 29 08:40:40 PM PDT 24 12808413224 ps
T954 /workspace/coverage/default/2.chip_sw_pwrmgr_normal_sleep_all_reset_reqs.1253507479 Jun 29 07:56:19 PM PDT 24 Jun 29 08:19:37 PM PDT 24 13053965214 ps
T955 /workspace/coverage/default/0.chip_sw_edn_kat.1002520681 Jun 29 07:39:42 PM PDT 24 Jun 29 07:49:48 PM PDT 24 2853296534 ps
T956 /workspace/coverage/default/1.chip_sw_power_idle_load.1910921210 Jun 29 07:52:36 PM PDT 24 Jun 29 08:06:44 PM PDT 24 4150848904 ps
T741 /workspace/coverage/default/29.chip_sw_all_escalation_resets.1863361965 Jun 29 08:09:47 PM PDT 24 Jun 29 08:20:29 PM PDT 24 4457073066 ps
T713 /workspace/coverage/default/57.chip_sw_alert_handler_lpg_sleep_mode_alerts.3985877964 Jun 29 08:14:44 PM PDT 24 Jun 29 08:20:24 PM PDT 24 2923383704 ps
T448 /workspace/coverage/default/1.chip_sw_edn_boot_mode.10606427 Jun 29 07:45:35 PM PDT 24 Jun 29 07:56:30 PM PDT 24 3395926224 ps
T266 /workspace/coverage/default/0.chip_sw_rv_core_ibex_icache_invalidate.2938458773 Jun 29 07:39:00 PM PDT 24 Jun 29 07:43:57 PM PDT 24 2528048390 ps
T957 /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_bad_dev.547154245 Jun 29 07:44:15 PM PDT 24 Jun 29 08:50:10 PM PDT 24 15505856000 ps
T309 /workspace/coverage/default/1.chip_sw_i2c_host_tx_rx.308803164 Jun 29 07:41:26 PM PDT 24 Jun 29 07:55:27 PM PDT 24 4916691100 ps
T683 /workspace/coverage/default/51.chip_sw_all_escalation_resets.2175525015 Jun 29 08:15:43 PM PDT 24 Jun 29 08:29:26 PM PDT 24 5157202230 ps
T958 /workspace/coverage/default/2.chip_sw_uart_tx_rx_idx1.3770843411 Jun 29 07:54:16 PM PDT 24 Jun 29 08:07:33 PM PDT 24 3962529560 ps
T374 /workspace/coverage/default/1.chip_sw_rv_core_ibex_lockstep_glitch.3774098627 Jun 29 07:50:50 PM PDT 24 Jun 29 07:55:21 PM PDT 24 2365656830 ps
T730 /workspace/coverage/default/1.chip_sw_alert_handler_lpg_sleep_mode_alerts.3191387176 Jun 29 07:45:05 PM PDT 24 Jun 29 07:52:37 PM PDT 24 3870538968 ps
T959 /workspace/coverage/default/2.chip_sw_aon_timer_sleep_wdog_sleep_pause.3641846475 Jun 29 07:56:51 PM PDT 24 Jun 29 08:04:17 PM PDT 24 6972424028 ps
T960 /workspace/coverage/default/4.chip_sw_uart_tx_rx_alt_clk_freq.2185553366 Jun 29 08:04:33 PM PDT 24 Jun 29 08:15:13 PM PDT 24 4201293104 ps
T961 /workspace/coverage/default/0.chip_sw_uart_smoketest.696794985 Jun 29 07:42:35 PM PDT 24 Jun 29 07:47:07 PM PDT 24 3140798726 ps
T254 /workspace/coverage/default/3.chip_sw_data_integrity_escalation.2912472645 Jun 29 08:03:31 PM PDT 24 Jun 29 08:18:41 PM PDT 24 5257724436 ps
T962 /workspace/coverage/default/26.chip_sw_alert_handler_lpg_sleep_mode_alerts.3968408663 Jun 29 08:08:07 PM PDT 24 Jun 29 08:14:53 PM PDT 24 3340046792 ps
T963 /workspace/coverage/default/1.chip_sw_aes_smoketest.2096931930 Jun 29 07:59:19 PM PDT 24 Jun 29 08:03:54 PM PDT 24 2238428536 ps
T964 /workspace/coverage/default/1.chip_sw_flash_ctrl_idle_low_power.3991098061 Jun 29 07:45:27 PM PDT 24 Jun 29 07:51:37 PM PDT 24 3975362592 ps
T965 /workspace/coverage/default/1.chip_sw_uart_tx_rx_idx2.3025700831 Jun 29 07:42:44 PM PDT 24 Jun 29 07:54:39 PM PDT 24 4902934790 ps
T373 /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_bad_b_good_prod_end.2704686919 Jun 29 07:46:04 PM PDT 24 Jun 29 09:26:32 PM PDT 24 24456642680 ps
T691 /workspace/coverage/default/83.chip_sw_all_escalation_resets.2389955944 Jun 29 08:13:37 PM PDT 24 Jun 29 08:25:13 PM PDT 24 5749535264 ps
T33 /workspace/coverage/default/0.chip_sw_usbdev_dpi.972077375 Jun 29 07:37:49 PM PDT 24 Jun 29 08:31:16 PM PDT 24 12357635910 ps
T966 /workspace/coverage/default/1.chip_sw_clkmgr_jitter_frequency.716082213 Jun 29 07:50:18 PM PDT 24 Jun 29 07:56:08 PM PDT 24 3938367500 ps
T967 /workspace/coverage/default/1.chip_sw_pwrmgr_sleep_wake_5_bug.2326725653 Jun 29 07:49:50 PM PDT 24 Jun 29 07:58:41 PM PDT 24 6112977650 ps
T221 /workspace/coverage/default/63.chip_sw_all_escalation_resets.3525892219 Jun 29 08:12:01 PM PDT 24 Jun 29 08:22:17 PM PDT 24 5611040452 ps
T352 /workspace/coverage/default/31.chip_sw_all_escalation_resets.2582919296 Jun 29 08:08:09 PM PDT 24 Jun 29 08:22:08 PM PDT 24 5555036506 ps
T968 /workspace/coverage/default/0.chip_sw_uart_tx_rx_bootstrap.3163003697 Jun 29 07:39:46 PM PDT 24 Jun 29 11:39:01 PM PDT 24 78136469364 ps
T969 /workspace/coverage/default/2.chip_sw_sram_ctrl_scrambled_access_jitter_en.1283897895 Jun 29 08:01:24 PM PDT 24 Jun 29 08:12:04 PM PDT 24 5142213950 ps
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