| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
| 96.02 | 95.45 | 93.64 | 95.54 | 94.43 | 97.53 | 99.54 |
| T2765 | /workspace/coverage/cover_reg_top/51.xbar_stress_all_with_rand_reset.2602284299 | Jun 29 08:23:40 PM PDT 24 | Jun 29 08:25:21 PM PDT 24 | 357705694 ps | ||
| T2766 | /workspace/coverage/cover_reg_top/0.xbar_smoke.2013314603 | Jun 29 08:07:36 PM PDT 24 | Jun 29 08:07:44 PM PDT 24 | 51000072 ps | ||
| T2767 | /workspace/coverage/cover_reg_top/38.xbar_random.3415486969 | Jun 29 08:21:21 PM PDT 24 | Jun 29 08:22:59 PM PDT 24 | 2314022233 ps | ||
| T2768 | /workspace/coverage/cover_reg_top/97.xbar_error_and_unmapped_addr.679433439 | Jun 29 08:31:09 PM PDT 24 | Jun 29 08:31:57 PM PDT 24 | 1159167205 ps | ||
| T2769 | /workspace/coverage/cover_reg_top/6.xbar_access_same_device.3012006099 | Jun 29 08:12:28 PM PDT 24 | Jun 29 08:12:37 PM PDT 24 | 27209432 ps | ||
| T2770 | /workspace/coverage/cover_reg_top/87.xbar_stress_all.3065892316 | Jun 29 08:29:33 PM PDT 24 | Jun 29 08:34:56 PM PDT 24 | 8790321507 ps | ||
| T2771 | /workspace/coverage/cover_reg_top/2.xbar_access_same_device_slow_rsp.104886187 | Jun 29 08:09:51 PM PDT 24 | Jun 29 08:37:53 PM PDT 24 | 88140621728 ps | ||
| T2772 | /workspace/coverage/cover_reg_top/53.xbar_smoke_slow_rsp.2448386503 | Jun 29 08:24:02 PM PDT 24 | Jun 29 08:25:51 PM PDT 24 | 6129690844 ps | ||
| T2773 | /workspace/coverage/cover_reg_top/13.xbar_smoke_slow_rsp.3800621536 | Jun 29 08:15:26 PM PDT 24 | Jun 29 08:16:31 PM PDT 24 | 4279516654 ps | ||
| T2774 | /workspace/coverage/cover_reg_top/47.xbar_access_same_device_slow_rsp.4052274584 | Jun 29 08:22:57 PM PDT 24 | Jun 29 08:31:15 PM PDT 24 | 26256951649 ps | ||
| T2775 | /workspace/coverage/cover_reg_top/33.xbar_smoke_slow_rsp.3022910349 | Jun 29 08:20:25 PM PDT 24 | Jun 29 08:21:53 PM PDT 24 | 5100824419 ps | ||
| T2776 | /workspace/coverage/cover_reg_top/3.xbar_random_large_delays.2761153408 | Jun 29 08:10:33 PM PDT 24 | Jun 29 08:26:20 PM PDT 24 | 89850900453 ps | ||
| T2777 | /workspace/coverage/cover_reg_top/29.xbar_stress_all_with_reset_error.2135817702 | Jun 29 08:19:44 PM PDT 24 | Jun 29 08:29:34 PM PDT 24 | 4897432323 ps | ||
| T2778 | /workspace/coverage/cover_reg_top/86.xbar_error_and_unmapped_addr.1146171229 | Jun 29 08:29:12 PM PDT 24 | Jun 29 08:29:28 PM PDT 24 | 113971691 ps | ||
| T2779 | /workspace/coverage/cover_reg_top/18.xbar_stress_all_with_error.1665730458 | Jun 29 08:17:02 PM PDT 24 | Jun 29 08:24:50 PM PDT 24 | 12555848837 ps | ||
| T2780 | /workspace/coverage/cover_reg_top/53.xbar_access_same_device.2629229427 | Jun 29 08:24:05 PM PDT 24 | Jun 29 08:25:29 PM PDT 24 | 808230562 ps | ||
| T2781 | /workspace/coverage/cover_reg_top/65.xbar_access_same_device.1425154265 | Jun 29 08:25:43 PM PDT 24 | Jun 29 08:26:09 PM PDT 24 | 545449751 ps | ||
| T2782 | /workspace/coverage/cover_reg_top/14.xbar_error_random.2305138172 | Jun 29 08:15:54 PM PDT 24 | Jun 29 08:16:03 PM PDT 24 | 64887239 ps | ||
| T2783 | /workspace/coverage/cover_reg_top/36.xbar_stress_all_with_rand_reset.3368332861 | Jun 29 08:21:07 PM PDT 24 | Jun 29 08:27:46 PM PDT 24 | 6387796038 ps | ||
| T2784 | /workspace/coverage/cover_reg_top/32.xbar_error_and_unmapped_addr.1667718793 | Jun 29 08:20:19 PM PDT 24 | Jun 29 08:20:42 PM PDT 24 | 204277079 ps | ||
| T2785 | /workspace/coverage/cover_reg_top/61.xbar_smoke_slow_rsp.2901976199 | Jun 29 08:25:14 PM PDT 24 | Jun 29 08:26:48 PM PDT 24 | 5433543630 ps | ||
| T654 | /workspace/coverage/cover_reg_top/29.xbar_stress_all_with_error.1488833529 | Jun 29 08:19:56 PM PDT 24 | Jun 29 08:23:39 PM PDT 24 | 2753116734 ps | ||
| T2786 | /workspace/coverage/cover_reg_top/96.xbar_stress_all_with_reset_error.3462759769 | Jun 29 08:30:53 PM PDT 24 | Jun 29 08:44:16 PM PDT 24 | 17331837687 ps | ||
| T2787 | /workspace/coverage/cover_reg_top/98.xbar_same_source.6518621 | Jun 29 08:31:10 PM PDT 24 | Jun 29 08:32:27 PM PDT 24 | 2515204781 ps | ||
| T2788 | /workspace/coverage/cover_reg_top/53.xbar_smoke_large_delays.3443449116 | Jun 29 08:24:04 PM PDT 24 | Jun 29 08:25:33 PM PDT 24 | 7871213862 ps | ||
| T2789 | /workspace/coverage/cover_reg_top/35.xbar_same_source.3951277879 | Jun 29 08:20:49 PM PDT 24 | Jun 29 08:21:33 PM PDT 24 | 1453596162 ps | ||
| T2790 | /workspace/coverage/cover_reg_top/4.chip_csr_rw.3395483686 | Jun 29 08:11:47 PM PDT 24 | Jun 29 08:16:45 PM PDT 24 | 3825596348 ps | ||
| T2791 | /workspace/coverage/cover_reg_top/56.xbar_smoke_zero_delays.3761429660 | Jun 29 08:24:25 PM PDT 24 | Jun 29 08:24:31 PM PDT 24 | 44253272 ps | ||
| T2792 | /workspace/coverage/cover_reg_top/57.xbar_stress_all_with_reset_error.1825454935 | Jun 29 08:24:38 PM PDT 24 | Jun 29 08:26:54 PM PDT 24 | 397926174 ps | ||
| T2793 | /workspace/coverage/cover_reg_top/29.xbar_same_source.2597234536 | Jun 29 08:19:44 PM PDT 24 | Jun 29 08:19:53 PM PDT 24 | 177849183 ps | ||
| T2794 | /workspace/coverage/cover_reg_top/46.xbar_smoke_zero_delays.3150616992 | Jun 29 08:22:43 PM PDT 24 | Jun 29 08:22:50 PM PDT 24 | 41450049 ps | ||
| T2795 | /workspace/coverage/cover_reg_top/90.xbar_access_same_device_slow_rsp.3289818899 | Jun 29 08:29:59 PM PDT 24 | Jun 29 08:52:26 PM PDT 24 | 81874487010 ps | ||
| T2796 | /workspace/coverage/cover_reg_top/82.xbar_stress_all_with_rand_reset.994963184 | Jun 29 08:28:31 PM PDT 24 | Jun 29 08:29:58 PM PDT 24 | 122875132 ps | ||
| T2797 | /workspace/coverage/cover_reg_top/17.xbar_smoke.2767256707 | Jun 29 08:16:30 PM PDT 24 | Jun 29 08:16:40 PM PDT 24 | 202242919 ps | ||
| T2798 | /workspace/coverage/cover_reg_top/35.xbar_stress_all_with_reset_error.4057488684 | Jun 29 08:21:00 PM PDT 24 | Jun 29 08:26:19 PM PDT 24 | 1509683289 ps | ||
| T2799 | /workspace/coverage/cover_reg_top/79.xbar_access_same_device.296817638 | Jun 29 08:28:02 PM PDT 24 | Jun 29 08:28:53 PM PDT 24 | 1044293611 ps | ||
| T2800 | /workspace/coverage/cover_reg_top/56.xbar_smoke.560477718 | Jun 29 08:24:22 PM PDT 24 | Jun 29 08:24:30 PM PDT 24 | 152970096 ps | ||
| T2801 | /workspace/coverage/cover_reg_top/9.xbar_access_same_device_slow_rsp.3262250589 | Jun 29 08:13:55 PM PDT 24 | Jun 29 08:42:09 PM PDT 24 | 90485341400 ps | ||
| T2802 | /workspace/coverage/cover_reg_top/58.xbar_smoke_zero_delays.1760300112 | Jun 29 08:24:39 PM PDT 24 | Jun 29 08:24:46 PM PDT 24 | 51456593 ps | ||
| T2803 | /workspace/coverage/cover_reg_top/4.xbar_unmapped_addr.3707398708 | Jun 29 08:11:16 PM PDT 24 | Jun 29 08:12:08 PM PDT 24 | 999769052 ps | ||
| T2804 | /workspace/coverage/cover_reg_top/69.xbar_error_random.1877543398 | Jun 29 08:26:23 PM PDT 24 | Jun 29 08:26:30 PM PDT 24 | 33583345 ps | ||
| T2805 | /workspace/coverage/cover_reg_top/49.xbar_random_slow_rsp.2140358426 | Jun 29 08:23:16 PM PDT 24 | Jun 29 08:32:40 PM PDT 24 | 31117841662 ps | ||
| T2806 | /workspace/coverage/cover_reg_top/20.xbar_stress_all_with_rand_reset.1047794426 | Jun 29 08:17:36 PM PDT 24 | Jun 29 08:18:48 PM PDT 24 | 147095339 ps | ||
| T2807 | /workspace/coverage/cover_reg_top/54.xbar_smoke.3413494274 | Jun 29 08:24:07 PM PDT 24 | Jun 29 08:24:14 PM PDT 24 | 40154600 ps | ||
| T2808 | /workspace/coverage/cover_reg_top/63.xbar_error_and_unmapped_addr.740906751 | Jun 29 08:25:27 PM PDT 24 | Jun 29 08:26:31 PM PDT 24 | 1455331487 ps | ||
| T2809 | /workspace/coverage/cover_reg_top/22.xbar_error_random.775044480 | Jun 29 08:17:57 PM PDT 24 | Jun 29 08:18:26 PM PDT 24 | 747248816 ps | ||
| T2810 | /workspace/coverage/cover_reg_top/2.chip_csr_bit_bash.224663736 | Jun 29 08:09:27 PM PDT 24 | Jun 29 08:23:39 PM PDT 24 | 6724635335 ps | ||
| T2811 | /workspace/coverage/cover_reg_top/88.xbar_error_random.2981255165 | Jun 29 08:29:33 PM PDT 24 | Jun 29 08:29:56 PM PDT 24 | 604525019 ps | ||
| T2812 | /workspace/coverage/cover_reg_top/51.xbar_access_same_device_slow_rsp.2456681454 | Jun 29 08:23:39 PM PDT 24 | Jun 29 08:55:45 PM PDT 24 | 104779352236 ps | ||
| T2813 | /workspace/coverage/cover_reg_top/23.xbar_error_and_unmapped_addr.800175957 | Jun 29 08:18:18 PM PDT 24 | Jun 29 08:18:27 PM PDT 24 | 135766026 ps | ||
| T2814 | /workspace/coverage/cover_reg_top/67.xbar_same_source.24676999 | Jun 29 08:26:07 PM PDT 24 | Jun 29 08:26:39 PM PDT 24 | 431314747 ps | ||
| T2815 | /workspace/coverage/cover_reg_top/28.chip_tl_errors.1489231634 | Jun 29 08:19:14 PM PDT 24 | Jun 29 08:20:56 PM PDT 24 | 2808941140 ps | ||
| T2816 | /workspace/coverage/cover_reg_top/26.xbar_smoke.3246920502 | Jun 29 08:18:45 PM PDT 24 | Jun 29 08:18:58 PM PDT 24 | 268974137 ps | ||
| T2817 | /workspace/coverage/cover_reg_top/79.xbar_random_large_delays.177934458 | Jun 29 08:28:05 PM PDT 24 | Jun 29 08:37:21 PM PDT 24 | 50302678065 ps | ||
| T2818 | /workspace/coverage/cover_reg_top/59.xbar_access_same_device_slow_rsp.434843933 | Jun 29 08:24:54 PM PDT 24 | Jun 29 08:37:52 PM PDT 24 | 43254030134 ps | ||
| T2819 | /workspace/coverage/cover_reg_top/79.xbar_stress_all_with_rand_reset.1625354096 | Jun 29 08:28:08 PM PDT 24 | Jun 29 08:36:48 PM PDT 24 | 5048294052 ps | ||
| T2820 | /workspace/coverage/cover_reg_top/71.xbar_stress_all_with_reset_error.2121604785 | Jun 29 08:26:48 PM PDT 24 | Jun 29 08:29:10 PM PDT 24 | 385934155 ps | ||
| T2821 | /workspace/coverage/cover_reg_top/77.xbar_random_slow_rsp.2774419078 | Jun 29 08:27:49 PM PDT 24 | Jun 29 08:35:46 PM PDT 24 | 28249957839 ps | ||
| T2822 | /workspace/coverage/cover_reg_top/0.xbar_access_same_device.3920716006 | Jun 29 08:07:48 PM PDT 24 | Jun 29 08:08:04 PM PDT 24 | 191275872 ps | ||
| T2823 | /workspace/coverage/cover_reg_top/51.xbar_smoke_slow_rsp.3749303272 | Jun 29 08:23:30 PM PDT 24 | Jun 29 08:24:46 PM PDT 24 | 4531164815 ps | ||
| T2824 | /workspace/coverage/cover_reg_top/28.xbar_unmapped_addr.1499706618 | Jun 29 08:19:29 PM PDT 24 | Jun 29 08:19:56 PM PDT 24 | 223477465 ps | ||
| T2825 | /workspace/coverage/cover_reg_top/81.xbar_smoke_large_delays.1626173869 | Jun 29 08:28:23 PM PDT 24 | Jun 29 08:30:06 PM PDT 24 | 9485133955 ps | ||
| T2826 | /workspace/coverage/cover_reg_top/41.xbar_unmapped_addr.3396665372 | Jun 29 08:21:59 PM PDT 24 | Jun 29 08:22:32 PM PDT 24 | 249847966 ps | ||
| T2827 | /workspace/coverage/cover_reg_top/98.xbar_access_same_device_slow_rsp.1533165564 | Jun 29 08:31:14 PM PDT 24 | Jun 29 08:43:25 PM PDT 24 | 42086201012 ps | ||
| T129 | /workspace/coverage/cover_reg_top/3.chip_csr_hw_reset.1728818914 | Jun 29 08:10:56 PM PDT 24 | Jun 29 08:16:00 PM PDT 24 | 5043671569 ps | ||
| T2828 | /workspace/coverage/cover_reg_top/34.xbar_access_same_device.301991010 | Jun 29 08:20:34 PM PDT 24 | Jun 29 08:21:54 PM PDT 24 | 1673035526 ps | ||
| T2829 | /workspace/coverage/cover_reg_top/60.xbar_smoke_large_delays.2845526045 | Jun 29 08:24:57 PM PDT 24 | Jun 29 08:26:30 PM PDT 24 | 8464076462 ps | ||
| T2830 | /workspace/coverage/cover_reg_top/76.xbar_random_zero_delays.519088914 | Jun 29 08:27:27 PM PDT 24 | Jun 29 08:28:08 PM PDT 24 | 383458265 ps | ||
| T2831 | /workspace/coverage/cover_reg_top/20.xbar_smoke_slow_rsp.4241463186 | Jun 29 08:17:33 PM PDT 24 | Jun 29 08:18:51 PM PDT 24 | 4478293257 ps | ||
| T2832 | /workspace/coverage/cover_reg_top/64.xbar_unmapped_addr.3334785031 | Jun 29 08:25:45 PM PDT 24 | Jun 29 08:26:25 PM PDT 24 | 854564000 ps | ||
| T2833 | /workspace/coverage/cover_reg_top/92.xbar_stress_all_with_error.3461354865 | Jun 29 08:30:22 PM PDT 24 | Jun 29 08:35:44 PM PDT 24 | 7586620732 ps | ||
| T2834 | /workspace/coverage/cover_reg_top/26.xbar_stress_all_with_error.215574994 | Jun 29 08:19:05 PM PDT 24 | Jun 29 08:24:26 PM PDT 24 | 4182863266 ps | ||
| T2835 | /workspace/coverage/cover_reg_top/71.xbar_smoke_slow_rsp.455287323 | Jun 29 08:26:49 PM PDT 24 | Jun 29 08:27:46 PM PDT 24 | 3100083242 ps | ||
| T2836 | /workspace/coverage/cover_reg_top/56.xbar_random_large_delays.3641653767 | Jun 29 08:24:23 PM PDT 24 | Jun 29 08:38:11 PM PDT 24 | 75753278054 ps | ||
| T2837 | /workspace/coverage/cover_reg_top/77.xbar_random_zero_delays.1227699575 | Jun 29 08:27:49 PM PDT 24 | Jun 29 08:28:39 PM PDT 24 | 478854590 ps | ||
| T2838 | /workspace/coverage/cover_reg_top/56.xbar_random_slow_rsp.3254844297 | Jun 29 08:24:21 PM PDT 24 | Jun 29 08:39:21 PM PDT 24 | 52449250906 ps | ||
| T2839 | /workspace/coverage/cover_reg_top/1.xbar_smoke.1088529539 | Jun 29 08:08:36 PM PDT 24 | Jun 29 08:08:43 PM PDT 24 | 41465481 ps | ||
| T131 | /workspace/coverage/cover_reg_top/1.chip_csr_hw_reset.3610084045 | Jun 29 08:09:10 PM PDT 24 | Jun 29 08:17:01 PM PDT 24 | 6450296272 ps | ||
| T2840 | /workspace/coverage/cover_reg_top/0.xbar_random.30746046 | Jun 29 08:07:41 PM PDT 24 | Jun 29 08:09:04 PM PDT 24 | 1705300477 ps | ||
| T2841 | /workspace/coverage/cover_reg_top/39.xbar_smoke_zero_delays.3858375022 | Jun 29 08:21:29 PM PDT 24 | Jun 29 08:21:37 PM PDT 24 | 55850000 ps | ||
| T2842 | /workspace/coverage/cover_reg_top/25.xbar_same_source.2234884717 | Jun 29 08:18:34 PM PDT 24 | Jun 29 08:19:49 PM PDT 24 | 2258889923 ps | ||
| T2843 | /workspace/coverage/cover_reg_top/50.xbar_unmapped_addr.3314309457 | Jun 29 08:23:21 PM PDT 24 | Jun 29 08:23:30 PM PDT 24 | 40639558 ps | ||
| T2844 | /workspace/coverage/cover_reg_top/49.xbar_error_random.2849230559 | Jun 29 08:23:13 PM PDT 24 | Jun 29 08:24:03 PM PDT 24 | 1490986212 ps | ||
| T2845 | /workspace/coverage/cover_reg_top/5.xbar_random_zero_delays.2998155417 | Jun 29 08:12:00 PM PDT 24 | Jun 29 08:12:24 PM PDT 24 | 226718501 ps | ||
| T2846 | /workspace/coverage/cover_reg_top/91.xbar_unmapped_addr.641469979 | Jun 29 08:30:05 PM PDT 24 | Jun 29 08:30:29 PM PDT 24 | 462693977 ps | ||
| T2847 | /workspace/coverage/cover_reg_top/64.xbar_random.2344409907 | Jun 29 08:25:49 PM PDT 24 | Jun 29 08:26:20 PM PDT 24 | 909338642 ps | ||
| T2848 | /workspace/coverage/cover_reg_top/75.xbar_random_large_delays.1417433982 | Jun 29 08:27:21 PM PDT 24 | Jun 29 08:45:50 PM PDT 24 | 106025922417 ps | ||
| T2849 | /workspace/coverage/cover_reg_top/58.xbar_error_and_unmapped_addr.3996809765 | Jun 29 08:24:45 PM PDT 24 | Jun 29 08:25:01 PM PDT 24 | 347443763 ps | ||
| T2850 | /workspace/coverage/cover_reg_top/66.xbar_access_same_device_slow_rsp.806880597 | Jun 29 08:25:53 PM PDT 24 | Jun 29 08:41:51 PM PDT 24 | 54974857420 ps | ||
| T2851 | /workspace/coverage/cover_reg_top/21.xbar_access_same_device_slow_rsp.2846104118 | Jun 29 08:17:45 PM PDT 24 | Jun 29 08:43:18 PM PDT 24 | 88039194937 ps | ||
| T2852 | /workspace/coverage/cover_reg_top/45.xbar_smoke_slow_rsp.638018871 | Jun 29 08:22:33 PM PDT 24 | Jun 29 08:24:08 PM PDT 24 | 5094085563 ps | ||
| T2853 | /workspace/coverage/cover_reg_top/35.xbar_random.2503213505 | Jun 29 08:20:49 PM PDT 24 | Jun 29 08:20:56 PM PDT 24 | 32413503 ps | ||
| T2854 | /workspace/coverage/cover_reg_top/46.xbar_random_zero_delays.1118517183 | Jun 29 08:22:43 PM PDT 24 | Jun 29 08:23:14 PM PDT 24 | 311681765 ps | ||
| T2855 | /workspace/coverage/cover_reg_top/33.xbar_random_large_delays.3316065719 | Jun 29 08:20:41 PM PDT 24 | Jun 29 08:26:17 PM PDT 24 | 33170351267 ps | ||
| T442 | /workspace/coverage/cover_reg_top/9.chip_csr_rw.3910651987 | Jun 29 08:14:14 PM PDT 24 | Jun 29 08:25:07 PM PDT 24 | 6556218362 ps | ||
| T2856 | /workspace/coverage/cover_reg_top/15.xbar_stress_all_with_reset_error.3303764561 | Jun 29 08:16:13 PM PDT 24 | Jun 29 08:18:50 PM PDT 24 | 472151927 ps | ||
| T2857 | /workspace/coverage/cover_reg_top/89.xbar_smoke.3075359447 | Jun 29 08:29:40 PM PDT 24 | Jun 29 08:29:50 PM PDT 24 | 218153935 ps | ||
| T2858 | /workspace/coverage/cover_reg_top/80.xbar_stress_all_with_rand_reset.771646633 | Jun 29 08:28:21 PM PDT 24 | Jun 29 08:30:53 PM PDT 24 | 306375259 ps | ||
| T2859 | /workspace/coverage/cover_reg_top/44.xbar_error_and_unmapped_addr.1932746543 | Jun 29 08:22:27 PM PDT 24 | Jun 29 08:22:47 PM PDT 24 | 145702924 ps | ||
| T2860 | /workspace/coverage/cover_reg_top/88.xbar_random.343604673 | Jun 29 08:29:34 PM PDT 24 | Jun 29 08:29:57 PM PDT 24 | 219382001 ps | ||
| T2861 | /workspace/coverage/cover_reg_top/77.xbar_access_same_device.4057398879 | Jun 29 08:27:49 PM PDT 24 | Jun 29 08:27:57 PM PDT 24 | 89048765 ps | ||
| T2862 | /workspace/coverage/cover_reg_top/18.xbar_error_random.3661190769 | Jun 29 08:16:54 PM PDT 24 | Jun 29 08:17:33 PM PDT 24 | 372434940 ps | ||
| T2863 | /workspace/coverage/cover_reg_top/71.xbar_stress_all_with_error.839911872 | Jun 29 08:26:48 PM PDT 24 | Jun 29 08:34:31 PM PDT 24 | 12596417509 ps | ||
| T2864 | /workspace/coverage/cover_reg_top/32.xbar_error_random.2746237221 | Jun 29 08:20:16 PM PDT 24 | Jun 29 08:21:09 PM PDT 24 | 1436835676 ps | ||
| T2865 | /workspace/coverage/cover_reg_top/5.xbar_stress_all.4148143954 | Jun 29 08:12:11 PM PDT 24 | Jun 29 08:19:28 PM PDT 24 | 10956280246 ps | ||
| T2866 | /workspace/coverage/cover_reg_top/73.xbar_smoke_large_delays.572085318 | Jun 29 08:27:05 PM PDT 24 | Jun 29 08:28:26 PM PDT 24 | 8007778950 ps | ||
| T2867 | /workspace/coverage/cover_reg_top/76.xbar_access_same_device_slow_rsp.2808354677 | Jun 29 08:27:34 PM PDT 24 | Jun 29 08:33:21 PM PDT 24 | 18716950591 ps | ||
| T2868 | /workspace/coverage/cover_reg_top/28.xbar_access_same_device_slow_rsp.2204567377 | Jun 29 08:19:26 PM PDT 24 | Jun 29 08:53:33 PM PDT 24 | 115399483334 ps | ||
| T2869 | /workspace/coverage/cover_reg_top/70.xbar_random.1132761886 | Jun 29 08:26:31 PM PDT 24 | Jun 29 08:27:56 PM PDT 24 | 2277057723 ps | ||
| T2870 | /workspace/coverage/cover_reg_top/90.xbar_smoke.1083787946 | Jun 29 08:29:51 PM PDT 24 | Jun 29 08:30:01 PM PDT 24 | 206546178 ps | ||
| T2871 | /workspace/coverage/cover_reg_top/60.xbar_smoke.233197511 | Jun 29 08:24:54 PM PDT 24 | Jun 29 08:25:03 PM PDT 24 | 52037349 ps | ||
| T2872 | /workspace/coverage/cover_reg_top/92.xbar_stress_all_with_reset_error.1880879332 | Jun 29 08:30:13 PM PDT 24 | Jun 29 08:32:10 PM PDT 24 | 456971226 ps | ||
| T2873 | /workspace/coverage/cover_reg_top/4.chip_csr_aliasing.1111156500 | Jun 29 08:10:52 PM PDT 24 | Jun 29 09:29:16 PM PDT 24 | 32107232395 ps | ||
| T2874 | /workspace/coverage/cover_reg_top/57.xbar_access_same_device_slow_rsp.3594004979 | Jun 29 08:24:48 PM PDT 24 | Jun 29 08:33:57 PM PDT 24 | 30860808528 ps | ||
| T2875 | /workspace/coverage/cover_reg_top/22.xbar_random_large_delays.2588008167 | Jun 29 08:17:54 PM PDT 24 | Jun 29 08:20:26 PM PDT 24 | 12715103052 ps | ||
| T2876 | /workspace/coverage/cover_reg_top/76.xbar_smoke.1730452909 | Jun 29 08:27:28 PM PDT 24 | Jun 29 08:27:37 PM PDT 24 | 224437722 ps | ||
| T2877 | /workspace/coverage/cover_reg_top/1.xbar_stress_all_with_reset_error.400070637 | Jun 29 08:09:08 PM PDT 24 | Jun 29 08:11:44 PM PDT 24 | 421450905 ps | ||
| T2878 | /workspace/coverage/cover_reg_top/0.chip_rv_dm_lc_disabled.1809506379 | Jun 29 08:07:35 PM PDT 24 | Jun 29 08:14:28 PM PDT 24 | 8284244786 ps | ||
| T2879 | /workspace/coverage/cover_reg_top/95.xbar_smoke.4147722070 | Jun 29 08:30:38 PM PDT 24 | Jun 29 08:30:49 PM PDT 24 | 204932536 ps | ||
| T2880 | /workspace/coverage/cover_reg_top/93.xbar_smoke.526884971 | Jun 29 08:30:12 PM PDT 24 | Jun 29 08:30:18 PM PDT 24 | 43601118 ps | ||
| T2881 | /workspace/coverage/cover_reg_top/69.xbar_access_same_device_slow_rsp.3238587131 | Jun 29 08:26:24 PM PDT 24 | Jun 29 08:43:36 PM PDT 24 | 62887156369 ps | ||
| T2882 | /workspace/coverage/cover_reg_top/32.xbar_random.871628093 | Jun 29 08:20:21 PM PDT 24 | Jun 29 08:20:58 PM PDT 24 | 422028761 ps | ||
| T2883 | /workspace/coverage/cover_reg_top/96.xbar_error_random.1718297070 | Jun 29 08:30:55 PM PDT 24 | Jun 29 08:31:47 PM PDT 24 | 1340358795 ps | ||
| T2884 | /workspace/coverage/cover_reg_top/44.xbar_smoke_zero_delays.371226219 | Jun 29 08:22:26 PM PDT 24 | Jun 29 08:22:34 PM PDT 24 | 52260015 ps | ||
| T36 | /workspace/coverage/pad_ctrl_test_mode/8.chip_padctrl_attributes.3755987799 | Jun 29 08:31:27 PM PDT 24 | Jun 29 08:35:57 PM PDT 24 | 5456771586 ps | ||
| T37 | /workspace/coverage/pad_ctrl_test_mode/3.chip_padctrl_attributes.3660832365 | Jun 29 08:31:27 PM PDT 24 | Jun 29 08:35:41 PM PDT 24 | 5232976584 ps | ||
| T38 | /workspace/coverage/pad_ctrl_test_mode/0.chip_padctrl_attributes.2461266009 | Jun 29 08:31:28 PM PDT 24 | Jun 29 08:34:51 PM PDT 24 | 3734639658 ps | ||
| T139 | /workspace/coverage/pad_ctrl_test_mode/5.chip_padctrl_attributes.2180374241 | Jun 29 08:31:32 PM PDT 24 | Jun 29 08:35:41 PM PDT 24 | 4777138974 ps | ||
| T140 | /workspace/coverage/pad_ctrl_test_mode/4.chip_padctrl_attributes.300353921 | Jun 29 08:31:28 PM PDT 24 | Jun 29 08:35:39 PM PDT 24 | 5451898585 ps | ||
| T141 | /workspace/coverage/pad_ctrl_test_mode/1.chip_padctrl_attributes.1366525154 | Jun 29 08:31:28 PM PDT 24 | Jun 29 08:35:17 PM PDT 24 | 4168220232 ps | ||
| T142 | /workspace/coverage/pad_ctrl_test_mode/2.chip_padctrl_attributes.140082897 | Jun 29 08:31:25 PM PDT 24 | Jun 29 08:34:19 PM PDT 24 | 4467828363 ps | ||
| T143 | /workspace/coverage/pad_ctrl_test_mode/7.chip_padctrl_attributes.917542695 | Jun 29 08:31:28 PM PDT 24 | Jun 29 08:36:05 PM PDT 24 | 5684389990 ps | ||
| T144 | /workspace/coverage/pad_ctrl_test_mode/9.chip_padctrl_attributes.2485069699 | Jun 29 08:31:33 PM PDT 24 | Jun 29 08:35:56 PM PDT 24 | 5340143152 ps | ||
| T145 | /workspace/coverage/pad_ctrl_test_mode/6.chip_padctrl_attributes.1676048048 | Jun 29 08:31:28 PM PDT 24 | Jun 29 08:34:36 PM PDT 24 | 4280010904 ps |
| Test location | /workspace/coverage/default/1.chip_sw_alert_handler_reverse_ping_in_deep_sleep.877338670 |
| Short name | T16 |
| Test name | |
| Test status | |
| Simulation time | 254406154258 ps |
| CPU time | 12980.6 seconds |
| Started | Jun 29 07:44:17 PM PDT 24 |
| Finished | Jun 29 11:20:40 PM PDT 24 |
| Peak memory | 608500 kb |
| Host | smart-2762e095-a3f8-43c3-945b-869420e28ab8 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=300_000_000 +sw_build_device=sim_dv +sw_images=alert_handler_reverse_ping_in_deep_sleep_test:1:n ew_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=877338670 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tg l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_alert_handler_reverse_ping_in_deep_sleep.877338670 |
| Directory | /workspace/1.chip_sw_alert_handler_reverse_ping_in_deep_sleep/latest |
| Test location | /workspace/coverage/cover_reg_top/11.chip_same_csr_outstanding.1572878336 |
| Short name | T136 |
| Test name | |
| Test status | |
| Simulation time | 28975063082 ps |
| CPU time | 2966.79 seconds |
| Started | Jun 29 08:14:38 PM PDT 24 |
| Finished | Jun 29 09:04:06 PM PDT 24 |
| Peak memory | 592352 kb |
| Host | smart-cea23598-4f51-4bce-a977-0a6fbb1dfff9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +run_same_csr_outstanding +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1572878336 -assert nopostproc +UVM_TE STNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb - cm_log /dev/null -cm_name 11.chip_same_csr_outstanding.1572878336 |
| Directory | /workspace/11.chip_same_csr_outstanding/latest |
| Test location | /workspace/coverage/default/1.chip_plic_all_irqs_20.2848502594 |
| Short name | T104 |
| Test name | |
| Test status | |
| Simulation time | 4487999564 ps |
| CPU time | 756.77 seconds |
| Started | Jun 29 07:48:07 PM PDT 24 |
| Finished | Jun 29 08:00:44 PM PDT 24 |
| Peak memory | 609172 kb |
| Host | smart-7ed39fc6-ab25-444f-8953-91385930f7cc |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=plic_all_irqs_test_20:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2848502594 -assert nopostproc +UVM_TESTN AME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log / dev/null -cm_name 1.chip_plic_all_irqs_20.2848502594 |
| Directory | /workspace/1.chip_plic_all_irqs_20/latest |
| Test location | /workspace/coverage/cover_reg_top/25.xbar_stress_all_with_rand_reset.2069220409 |
| Short name | T117 |
| Test name | |
| Test status | |
| Simulation time | 2640045790 ps |
| CPU time | 280.58 seconds |
| Started | Jun 29 08:18:44 PM PDT 24 |
| Finished | Jun 29 08:23:26 PM PDT 24 |
| Peak memory | 576516 kb |
| Host | smart-3e9bbdae-acc9-4c2c-a275-11d06fbef9da |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2069220409 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.xbar_stress_all _with_rand_reset.2069220409 |
| Directory | /workspace/25.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/60.xbar_access_same_device_slow_rsp.234350832 |
| Short name | T773 |
| Test name | |
| Test status | |
| Simulation time | 131766156570 ps |
| CPU time | 2247.55 seconds |
| Started | Jun 29 08:25:04 PM PDT 24 |
| Finished | Jun 29 09:02:32 PM PDT 24 |
| Peak memory | 574452 kb |
| Host | smart-e9ca867c-8acb-4670-9329-51f6742348f9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=234350832 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 60.xbar_access_same_d evice_slow_rsp.234350832 |
| Directory | /workspace/60.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/pad_ctrl_test_mode/8.chip_padctrl_attributes.3755987799 |
| Short name | T36 |
| Test name | |
| Test status | |
| Simulation time | 5456771586 ps |
| CPU time | 270.03 seconds |
| Started | Jun 29 08:31:27 PM PDT 24 |
| Finished | Jun 29 08:35:57 PM PDT 24 |
| Peak memory | 640304 kb |
| Host | smart-332133f8-7cf5-4186-bd4b-761fc33634ec |
| User | root |
| Command | /workspace/pad_ctrl_test_mode/simv +use_otp_image=OtpTypeLcStProd +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3755987799 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TE ST_SEQ=chip_padctrl_attributes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/pad_ctrl_test_mode.vdb -cm_log /dev/ null -cm_name 8.chip_padctrl_attributes.3755987799 |
| Directory | /workspace/8.chip_padctrl_attributes/latest |
| Test location | /workspace/coverage/cover_reg_top/63.xbar_access_same_device_slow_rsp.986888901 |
| Short name | T775 |
| Test name | |
| Test status | |
| Simulation time | 99039008612 ps |
| CPU time | 1813.53 seconds |
| Started | Jun 29 08:25:28 PM PDT 24 |
| Finished | Jun 29 08:55:42 PM PDT 24 |
| Peak memory | 574444 kb |
| Host | smart-b097be5b-9425-4a93-861d-70938913f3ef |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=986888901 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 63.xbar_access_same_d evice_slow_rsp.986888901 |
| Directory | /workspace/63.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/default/0.chip_sw_keymgr_key_derivation_prod.1008232664 |
| Short name | T40 |
| Test name | |
| Test status | |
| Simulation time | 8752678984 ps |
| CPU time | 1875.67 seconds |
| Started | Jun 29 07:39:51 PM PDT 24 |
| Finished | Jun 29 08:11:09 PM PDT 24 |
| Peak memory | 615672 kb |
| Host | smart-a06d682b-cc73-4606-8b0e-3f1cce45868f |
| User | root |
| Command | /workspace/default/simv +lc_at_prod=1 +sw_test_timeout_ns=20_000_000 +sw_build_device=sim_dv +sw_images=keymgr_key_derivation_test:1:new_rules,test_ro m:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=1008232664 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_keymgr_key_derivation_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_keymgr_key_derivation_prod.1008232664 |
| Directory | /workspace/0.chip_sw_keymgr_key_derivation_prod/latest |
| Test location | /workspace/coverage/cover_reg_top/34.xbar_access_same_device_slow_rsp.1562959968 |
| Short name | T474 |
| Test name | |
| Test status | |
| Simulation time | 97149822274 ps |
| CPU time | 1760.79 seconds |
| Started | Jun 29 08:20:44 PM PDT 24 |
| Finished | Jun 29 08:50:05 PM PDT 24 |
| Peak memory | 575520 kb |
| Host | smart-7aa1290d-f78c-4aa6-888d-836314feed29 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1562959968 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.xbar_access_same_ device_slow_rsp.1562959968 |
| Directory | /workspace/34.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/default/1.chip_sw_sleep_pin_mio_dio_val.2195897089 |
| Short name | T19 |
| Test name | |
| Test status | |
| Simulation time | 3020671447 ps |
| CPU time | 235.31 seconds |
| Started | Jun 29 07:42:05 PM PDT 24 |
| Finished | Jun 29 07:46:01 PM PDT 24 |
| Peak memory | 608236 kb |
| Host | smart-8e62b114-7ee9-4576-a0b6-8eabdfb01135 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStProd +sw_build_device=sim_dv +sw_images=sleep_pin_mio_dio_val_test:1:new_rules,test_rom:0 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2195 897089 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sleep_pin_mio_dio_val_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_sleep_pin_mio_dio_val.2195897089 |
| Directory | /workspace/1.chip_sw_sleep_pin_mio_dio_val/latest |
| Test location | /workspace/coverage/cover_reg_top/85.xbar_access_same_device_slow_rsp.1190197186 |
| Short name | T781 |
| Test name | |
| Test status | |
| Simulation time | 52495571646 ps |
| CPU time | 895.78 seconds |
| Started | Jun 29 08:29:01 PM PDT 24 |
| Finished | Jun 29 08:43:58 PM PDT 24 |
| Peak memory | 574412 kb |
| Host | smart-17b05788-bac6-4ac7-99f0-0120b8dfd08b |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1190197186 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 85.xbar_access_same_ device_slow_rsp.1190197186 |
| Directory | /workspace/85.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/default/2.chip_sw_lc_walkthrough_testunlocks.4115525501 |
| Short name | T62 |
| Test name | |
| Test status | |
| Simulation time | 29487875650 ps |
| CPU time | 2511.38 seconds |
| Started | Jun 29 07:55:49 PM PDT 24 |
| Finished | Jun 29 08:37:41 PM PDT 24 |
| Peak memory | 623548 kb |
| Host | smart-827b46eb-3278-45cd-bb51-664eee248e9b |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStRaw +dest_dec_state=DecLcStTestUnlock7 +sw_build_device=sim_dv +sw_images=lc_walkthrough_testunlocks _test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=4115525501 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_walkthrough_testunlocks_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_lc_walkthrough_testun locks.4115525501 |
| Directory | /workspace/2.chip_sw_lc_walkthrough_testunlocks/latest |
| Test location | /workspace/coverage/default/1.chip_sw_alert_test.407874422 |
| Short name | T58 |
| Test name | |
| Test status | |
| Simulation time | 3421770420 ps |
| CPU time | 298.75 seconds |
| Started | Jun 29 07:46:30 PM PDT 24 |
| Finished | Jun 29 07:51:29 PM PDT 24 |
| Peak memory | 607500 kb |
| Host | smart-c548a771-480f-44e1-85b2-bc5480948324 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=alert_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=407874422 -assert nopostproc +UVM_TESTNAME=chip_bas e_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm _name 1.chip_sw_alert_test.407874422 |
| Directory | /workspace/1.chip_sw_alert_test/latest |
| Test location | /workspace/coverage/cover_reg_top/42.xbar_stress_all_with_error.1420324854 |
| Short name | T524 |
| Test name | |
| Test status | |
| Simulation time | 11744365922 ps |
| CPU time | 424.01 seconds |
| Started | Jun 29 08:22:13 PM PDT 24 |
| Finished | Jun 29 08:29:17 PM PDT 24 |
| Peak memory | 574748 kb |
| Host | smart-303f1a75-7254-42d9-8a55-dad959b61a2b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1420324854 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.xbar_stress_all_with_error.1420324854 |
| Directory | /workspace/42.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/default/0.chip_plic_all_irqs_0.1377640755 |
| Short name | T290 |
| Test name | |
| Test status | |
| Simulation time | 5868243476 ps |
| CPU time | 1167.44 seconds |
| Started | Jun 29 07:42:40 PM PDT 24 |
| Finished | Jun 29 08:02:09 PM PDT 24 |
| Peak memory | 606720 kb |
| Host | smart-eaef1d48-45d8-495d-ac47-e56e64c26940 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=plic_all_irqs_test_0:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1377640755 -assert nopostproc +UVM_TESTNA ME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 0.chip_plic_all_irqs_0.1377640755 |
| Directory | /workspace/0.chip_plic_all_irqs_0/latest |
| Test location | /workspace/coverage/default/1.chip_sw_pwrmgr_deep_sleep_all_wake_ups.2419949325 |
| Short name | T2 |
| Test name | |
| Test status | |
| Simulation time | 23267933898 ps |
| CPU time | 1419.62 seconds |
| Started | Jun 29 07:51:39 PM PDT 24 |
| Finished | Jun 29 08:15:19 PM PDT 24 |
| Peak memory | 608676 kb |
| Host | smart-3ef450b3-d156-4462-908b-4c020eb038cf |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=pwrmgr_deep_sleep_all_wake_ups:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 2419949325 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_pwrmgr_deep_sleep_all_wake_ups_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_deep_sleep_all_wake_ups.2419949325 |
| Directory | /workspace/1.chip_sw_pwrmgr_deep_sleep_all_wake_ups/latest |
| Test location | /workspace/coverage/default/0.chip_sw_rv_core_ibex_address_translation.1596152227 |
| Short name | T186 |
| Test name | |
| Test status | |
| Simulation time | 2819127950 ps |
| CPU time | 322.66 seconds |
| Started | Jun 29 07:41:37 PM PDT 24 |
| Finished | Jun 29 07:47:00 PM PDT 24 |
| Peak memory | 607796 kb |
| Host | smart-c0176b86-4980-4943-81b0-61ced0863453 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=7_000_000 +sw_build_device=sim_dv +sw_images=rv_core_ibex_address_translation_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=1596152227 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_rv_core_ibex_address_translation.1596152227 |
| Directory | /workspace/0.chip_sw_rv_core_ibex_address_translation/latest |
| Test location | /workspace/coverage/cover_reg_top/40.xbar_access_same_device_slow_rsp.3420153831 |
| Short name | T789 |
| Test name | |
| Test status | |
| Simulation time | 120231123627 ps |
| CPU time | 2019.73 seconds |
| Started | Jun 29 08:21:51 PM PDT 24 |
| Finished | Jun 29 08:55:32 PM PDT 24 |
| Peak memory | 575500 kb |
| Host | smart-e2ecdb5e-7432-4563-a2e6-79f8389a34c0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3420153831 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.xbar_access_same_ device_slow_rsp.3420153831 |
| Directory | /workspace/40.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_asm_init_prod_end.3746653523 |
| Short name | T52 |
| Test name | |
| Test status | |
| Simulation time | 15948153160 ps |
| CPU time | 4215.22 seconds |
| Started | Jun 29 07:45:49 PM PDT 24 |
| Finished | Jun 29 08:56:06 PM PDT 24 |
| Peak memory | 608148 kb |
| Host | smart-146475fc-a714-4d75-b3c3-e4a6886ea5c9 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeCustom +sw_test_timeout_ns=20000000 +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_prod _key_0:1:ot_flash_binary,otp_img_e2e_bootstrap_entry_prod_end:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3746653523 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_T EST_SEQ=chip_sw_rom_e2e_asm_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 0.rom_e2e_asm_init_prod_end.3746653523 |
| Directory | /workspace/0.rom_e2e_asm_init_prod_end/latest |
| Test location | /workspace/coverage/cover_reg_top/22.chip_tl_errors.3730658646 |
| Short name | T520 |
| Test name | |
| Test status | |
| Simulation time | 4038281504 ps |
| CPU time | 352.34 seconds |
| Started | Jun 29 08:17:59 PM PDT 24 |
| Finished | Jun 29 08:23:52 PM PDT 24 |
| Peak memory | 603636 kb |
| Host | smart-363eba0c-86da-4305-9ce3-5e099f7dafb4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3730658646 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.chip_tl_errors.3730658646 |
| Directory | /workspace/22.chip_tl_errors/latest |
| Test location | /workspace/coverage/default/1.chip_sw_keymgr_sideload_kmac.1575204411 |
| Short name | T197 |
| Test name | |
| Test status | |
| Simulation time | 5803661416 ps |
| CPU time | 1158.93 seconds |
| Started | Jun 29 07:45:59 PM PDT 24 |
| Finished | Jun 29 08:05:19 PM PDT 24 |
| Peak memory | 609264 kb |
| Host | smart-18329fd3-a226-43ef-b6d5-2eec8ceda28d |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=20_000_000 +sw_build_device=sim_dv +sw_images=keymgr_sideload_kmac_test:1:new_rules,test_rom:0 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15752 04411 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_keymgr_sideload_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_keymgr_sideload_kmac.1575204411 |
| Directory | /workspace/1.chip_sw_keymgr_sideload_kmac/latest |
| Test location | /workspace/coverage/default/0.chip_sw_gpio.1755264002 |
| Short name | T25 |
| Test name | |
| Test status | |
| Simulation time | 3893751348 ps |
| CPU time | 407.2 seconds |
| Started | Jun 29 07:39:16 PM PDT 24 |
| Finished | Jun 29 07:46:05 PM PDT 24 |
| Peak memory | 607140 kb |
| Host | smart-319d80f2-1b92-46e0-b743-8b6e2631df24 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=gpio_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1755264002 -assert nopostproc +UVM_TESTNAME=chip_bas e_test +UVM_TEST_SEQ=chip_sw_gpio_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm _name 0.chip_sw_gpio.1755264002 |
| Directory | /workspace/0.chip_sw_gpio/latest |
| Test location | /workspace/coverage/cover_reg_top/75.xbar_access_same_device_slow_rsp.399440053 |
| Short name | T528 |
| Test name | |
| Test status | |
| Simulation time | 69640573831 ps |
| CPU time | 1290.79 seconds |
| Started | Jun 29 08:27:26 PM PDT 24 |
| Finished | Jun 29 08:48:58 PM PDT 24 |
| Peak memory | 575472 kb |
| Host | smart-2aa8da3e-cb05-4a38-b072-d85015f09e7c |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=399440053 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 75.xbar_access_same_d evice_slow_rsp.399440053 |
| Directory | /workspace/75.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/default/2.chip_sw_spi_device_pass_through.4100349205 |
| Short name | T22 |
| Test name | |
| Test status | |
| Simulation time | 6863917983 ps |
| CPU time | 752.2 seconds |
| Started | Jun 29 07:53:53 PM PDT 24 |
| Finished | Jun 29 08:06:26 PM PDT 24 |
| Peak memory | 624232 kb |
| Host | smart-e8db6a6a-815f-4ba9-b192-6df121d3c1ea |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=spi_passthrough_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4100349205 -assert nopostproc +UVM_TESTNA ME=chip_base_test +UVM_TEST_SEQ=chip_sw_spi_passthrough_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_spi_device_pass_through.4100349205 |
| Directory | /workspace/2.chip_sw_spi_device_pass_through/latest |
| Test location | /workspace/coverage/default/0.chip_plic_all_irqs_10.1677499675 |
| Short name | T166 |
| Test name | |
| Test status | |
| Simulation time | 4281372072 ps |
| CPU time | 588.86 seconds |
| Started | Jun 29 07:42:51 PM PDT 24 |
| Finished | Jun 29 07:52:40 PM PDT 24 |
| Peak memory | 609176 kb |
| Host | smart-181ce5bf-07bb-4625-98b5-1a2804d0c4d3 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=plic_all_irqs_test_10:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1677499675 -assert nopostproc +UVM_TESTN AME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log / dev/null -cm_name 0.chip_plic_all_irqs_10.1677499675 |
| Directory | /workspace/0.chip_plic_all_irqs_10/latest |
| Test location | /workspace/coverage/default/10.chip_sw_all_escalation_resets.842828985 |
| Short name | T63 |
| Test name | |
| Test status | |
| Simulation time | 5664831388 ps |
| CPU time | 964.41 seconds |
| Started | Jun 29 08:07:58 PM PDT 24 |
| Finished | Jun 29 08:24:03 PM PDT 24 |
| Peak memory | 643684 kb |
| Host | smart-cf8d1a68-3e6b-4276-b3b1-0205ecb2c244 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 842828985 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.chip_sw_all_escalation_resets.842828985 |
| Directory | /workspace/10.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/cover_reg_top/71.xbar_access_same_device_slow_rsp.1953121934 |
| Short name | T475 |
| Test name | |
| Test status | |
| Simulation time | 144650653809 ps |
| CPU time | 2615.64 seconds |
| Started | Jun 29 08:26:47 PM PDT 24 |
| Finished | Jun 29 09:10:23 PM PDT 24 |
| Peak memory | 575516 kb |
| Host | smart-847f9f78-d60c-4c58-a1e6-b9647af3925c |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1953121934 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 71.xbar_access_same_ device_slow_rsp.1953121934 |
| Directory | /workspace/71.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/default/0.chip_jtag_csr_rw.2336238962 |
| Short name | T72 |
| Test name | |
| Test status | |
| Simulation time | 12470680438 ps |
| CPU time | 1314.32 seconds |
| Started | Jun 29 07:30:30 PM PDT 24 |
| Finished | Jun 29 07:52:25 PM PDT 24 |
| Peak memory | 602012 kb |
| Host | smart-04a9a4a2-d4a5-4982-9c80-f35ed10a603e |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +csr_rw +create_jtag_riscv_map=1 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2336238962 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_T EST_SEQ=chip_jtag_csr_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.c hip_jtag_csr_rw.2336238962 |
| Directory | /workspace/0.chip_jtag_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/54.xbar_access_same_device.4179437928 |
| Short name | T562 |
| Test name | |
| Test status | |
| Simulation time | 2036440419 ps |
| CPU time | 103.17 seconds |
| Started | Jun 29 08:24:05 PM PDT 24 |
| Finished | Jun 29 08:25:49 PM PDT 24 |
| Peak memory | 575292 kb |
| Host | smart-f0b57310-a6b3-4db1-bb81-e56b04d1cfc2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4179437928 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 54.xbar_access_same_device .4179437928 |
| Directory | /workspace/54.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/98.xbar_access_same_device.3986349645 |
| Short name | T771 |
| Test name | |
| Test status | |
| Simulation time | 1993472291 ps |
| CPU time | 91.66 seconds |
| Started | Jun 29 08:31:10 PM PDT 24 |
| Finished | Jun 29 08:32:41 PM PDT 24 |
| Peak memory | 575368 kb |
| Host | smart-6fc82ba6-2094-42d7-ad23-b6fa50527e2f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3986349645 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 98.xbar_access_same_device .3986349645 |
| Directory | /workspace/98.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/89.xbar_random.2817103595 |
| Short name | T368 |
| Test name | |
| Test status | |
| Simulation time | 551769723 ps |
| CPU time | 50.09 seconds |
| Started | Jun 29 08:29:40 PM PDT 24 |
| Finished | Jun 29 08:30:30 PM PDT 24 |
| Peak memory | 574240 kb |
| Host | smart-bf2e6697-c96c-4c0e-a97f-25238be972d9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2817103595 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 89.xbar_random.2817103595 |
| Directory | /workspace/89.xbar_random/latest |
| Test location | /workspace/coverage/default/4.chip_sw_csrng_edn_concurrency.3471100114 |
| Short name | T15 |
| Test name | |
| Test status | |
| Simulation time | 8684452660 ps |
| CPU time | 2219.39 seconds |
| Started | Jun 29 08:05:08 PM PDT 24 |
| Finished | Jun 29 08:42:08 PM PDT 24 |
| Peak memory | 608212 kb |
| Host | smart-05e43d14-634b-429c-afb2-eca434478e80 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=140_000_000 +rng_srate_value_min=15 +rng_srate_value_max=20 +sw_build_device=sim_dv +sw_images=csrng_edn_c oncurrency_test:1:new_rules,test_rom:0 +accelerate_cold_power_up_time=3 +accelerate_regulators_power_up_time=2 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3471100114 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd b -cm_log /dev/null -cm_name 4.chip_sw_csrng_edn_concurrency.3471100114 |
| Directory | /workspace/4.chip_sw_csrng_edn_concurrency/latest |
| Test location | /workspace/coverage/cover_reg_top/2.chip_csr_hw_reset.27594618 |
| Short name | T130 |
| Test name | |
| Test status | |
| Simulation time | 7642349797 ps |
| CPU time | 435.27 seconds |
| Started | Jun 29 08:09:59 PM PDT 24 |
| Finished | Jun 29 08:17:15 PM PDT 24 |
| Peak memory | 660588 kb |
| Host | smart-8bdbf50b-e58f-4112-b01e-8798bcf872a9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27594618 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_co mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.chip_csr_hw_res et.27594618 |
| Directory | /workspace/2.chip_csr_hw_reset/latest |
| Test location | /workspace/coverage/default/1.chip_sw_lc_walkthrough_prod.2840991928 |
| Short name | T176 |
| Test name | |
| Test status | |
| Simulation time | 46927488300 ps |
| CPU time | 5620.3 seconds |
| Started | Jun 29 07:42:28 PM PDT 24 |
| Finished | Jun 29 09:16:10 PM PDT 24 |
| Peak memory | 617868 kb |
| Host | smart-1ff9ec0a-1d96-42f1-9e2d-b3cedb04ea09 |
| User | root |
| Command | /workspace/default/simv +flash_program_latency=5 +use_otp_image=OtpTypeLcStRaw +dest_dec_state=DecLcStProd +sw_test_timeout_ns=200_000_000 +sw_build_d evice=sim_dv +sw_images=lc_walkthrough_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2840991928 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ= chip_sw_lc_walkthrough_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chi p_sw_lc_walkthrough_prod.2840991928 |
| Directory | /workspace/1.chip_sw_lc_walkthrough_prod/latest |
| Test location | /workspace/coverage/default/2.chip_sw_sysrst_ctrl_reset.2764072366 |
| Short name | T29 |
| Test name | |
| Test status | |
| Simulation time | 22415217128 ps |
| CPU time | 1601.91 seconds |
| Started | Jun 29 07:56:55 PM PDT 24 |
| Finished | Jun 29 08:23:37 PM PDT 24 |
| Peak memory | 612372 kb |
| Host | smart-51a42c73-cb62-4e52-8654-5390df4b794d |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=36_000_000 +sw_build_device=sim_dv +sw_images=sysrst_ctrl_reset_test:1:new_rules,test_rom:0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27640723 66 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_sysrst_ctrl_reset.2764072366 |
| Directory | /workspace/2.chip_sw_sysrst_ctrl_reset/latest |
| Test location | /workspace/coverage/default/0.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup.3703906782 |
| Short name | T127 |
| Test name | |
| Test status | |
| Simulation time | 4580452924 ps |
| CPU time | 366.27 seconds |
| Started | Jun 29 07:38:22 PM PDT 24 |
| Finished | Jun 29 07:44:29 PM PDT 24 |
| Peak memory | 609248 kb |
| Host | smart-852661fe-5c20-49de-9f2a-6f8e5fd50d8e |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=8_000_000 +sw_build_device=sim_dv +sw_images=sensor_ctrl_wakeup_test:1:new_rules,test_rom:0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37039067 82 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac e/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup.3703906782 |
| Directory | /workspace/0.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup/latest |
| Test location | /workspace/coverage/default/2.chip_sw_sleep_pin_mio_dio_val.2242646354 |
| Short name | T21 |
| Test name | |
| Test status | |
| Simulation time | 2544146301 ps |
| CPU time | 281.43 seconds |
| Started | Jun 29 07:53:29 PM PDT 24 |
| Finished | Jun 29 07:58:10 PM PDT 24 |
| Peak memory | 608276 kb |
| Host | smart-8a375a7f-3e16-4807-b140-237397beb50b |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStProd +sw_build_device=sim_dv +sw_images=sleep_pin_mio_dio_val_test:1:new_rules,test_rom:0 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2242 646354 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sleep_pin_mio_dio_val_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_sleep_pin_mio_dio_val.2242646354 |
| Directory | /workspace/2.chip_sw_sleep_pin_mio_dio_val/latest |
| Test location | /workspace/coverage/cover_reg_top/94.xbar_random_large_delays.3531622157 |
| Short name | T488 |
| Test name | |
| Test status | |
| Simulation time | 57258055799 ps |
| CPU time | 581.48 seconds |
| Started | Jun 29 08:30:30 PM PDT 24 |
| Finished | Jun 29 08:40:11 PM PDT 24 |
| Peak memory | 575432 kb |
| Host | smart-005f190f-fbfa-42a6-bf1c-7e176d5af308 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3531622157 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 94.xbar_random_large_delays.3531622157 |
| Directory | /workspace/94.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/default/2.chip_sw_alert_handler_lpg_sleep_mode_pings.2269127382 |
| Short name | T79 |
| Test name | |
| Test status | |
| Simulation time | 10632481178 ps |
| CPU time | 1371.65 seconds |
| Started | Jun 29 07:59:45 PM PDT 24 |
| Finished | Jun 29 08:22:37 PM PDT 24 |
| Peak memory | 608896 kb |
| Host | smart-5f2c4564-20f1-42cd-9af6-0e678e1e4f2d |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=alert_handler _lpg_sleep_mode_pings_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2269127382 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_alert_han dler_shorten_ping_wait_cycle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_alert_handler_lpg_sleep_mode_pings.2269127382 |
| Directory | /workspace/2.chip_sw_alert_handler_lpg_sleep_mode_pings/latest |
| Test location | /workspace/coverage/default/0.chip_sw_flash_rma_unlocked.826844577 |
| Short name | T345 |
| Test name | |
| Test status | |
| Simulation time | 43651502324 ps |
| CPU time | 5525.66 seconds |
| Started | Jun 29 07:36:54 PM PDT 24 |
| Finished | Jun 29 09:09:01 PM PDT 24 |
| Peak memory | 615020 kb |
| Host | smart-35796624-f38a-4a28-a36c-ac4601d283f5 |
| User | root |
| Command | /workspace/default/simv +flash_program_latency=5 +sw_test_timeout_ns=150_000_000 +sw_build_device=sim_dv +sw_images=flash_rma_unlocked_test:0:test_in_ rom:new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t cl +ntb_random_seed=826844577 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_flash_rma_unlocked_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_flash_rma_unlocked.826844577 |
| Directory | /workspace/0.chip_sw_flash_rma_unlocked/latest |
| Test location | /workspace/coverage/cover_reg_top/9.chip_tl_errors.1004159014 |
| Short name | T627 |
| Test name | |
| Test status | |
| Simulation time | 5386281265 ps |
| CPU time | 463.98 seconds |
| Started | Jun 29 08:13:46 PM PDT 24 |
| Finished | Jun 29 08:21:31 PM PDT 24 |
| Peak memory | 596476 kb |
| Host | smart-b90bbf70-e614-4d33-8dcf-08f0c4efe9f4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1004159014 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.chip_tl_errors.1004159014 |
| Directory | /workspace/9.chip_tl_errors/latest |
| Test location | /workspace/coverage/default/4.chip_sw_data_integrity_escalation.2011761892 |
| Short name | T218 |
| Test name | |
| Test status | |
| Simulation time | 6319272060 ps |
| CPU time | 965.25 seconds |
| Started | Jun 29 08:04:12 PM PDT 24 |
| Finished | Jun 29 08:20:18 PM PDT 24 |
| Peak memory | 609272 kb |
| Host | smart-6bf5d420-545d-4b24-b283-50b26489949a |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=data_integrity_escalation_reset_test:1:new_rules,test_ro m:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=2011761892 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_data_integrity_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.chip_sw_data_integrity_escalation.2011761892 |
| Directory | /workspace/4.chip_sw_data_integrity_escalation/latest |
| Test location | /workspace/coverage/default/0.chip_sw_sleep_pin_mio_dio_val.3358225539 |
| Short name | T20 |
| Test name | |
| Test status | |
| Simulation time | 2582128178 ps |
| CPU time | 256.05 seconds |
| Started | Jun 29 07:39:18 PM PDT 24 |
| Finished | Jun 29 07:43:34 PM PDT 24 |
| Peak memory | 608288 kb |
| Host | smart-f2821ca2-f6e5-4920-ac61-8d54e43912f2 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStProd +sw_build_device=sim_dv +sw_images=sleep_pin_mio_dio_val_test:1:new_rules,test_rom:0 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3358 225539 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sleep_pin_mio_dio_val_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_sleep_pin_mio_dio_val.3358225539 |
| Directory | /workspace/0.chip_sw_sleep_pin_mio_dio_val/latest |
| Test location | /workspace/coverage/default/0.chip_sw_otp_ctrl_escalation.1689991033 |
| Short name | T174 |
| Test name | |
| Test status | |
| Simulation time | 5644437682 ps |
| CPU time | 668.02 seconds |
| Started | Jun 29 07:39:47 PM PDT 24 |
| Finished | Jun 29 07:50:56 PM PDT 24 |
| Peak memory | 608932 kb |
| Host | smart-c73132f1-a52a-4e82-b887-6656c0398182 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 1689991033 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_otp_ctrl_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_otp_ctrl_escalation.1689991033 |
| Directory | /workspace/0.chip_sw_otp_ctrl_escalation/latest |
| Test location | /workspace/coverage/default/0.chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq.3269340551 |
| Short name | T112 |
| Test name | |
| Test status | |
| Simulation time | 4715486598 ps |
| CPU time | 467.1 seconds |
| Started | Jun 29 07:44:40 PM PDT 24 |
| Finished | Jun 29 07:52:28 PM PDT 24 |
| Peak memory | 608476 kb |
| Host | smart-e13bfa9a-3c8c-4150-9dbc-e49cf122361e |
| User | root |
| Command | /workspace/default/simv +mem_sel=main +sw_test_timeout_ns=12_000_000 +bypass_alert_ready_to_end_check=1 +en_jitter=1 +en_scb_tl_err_chk=0 +cal_sys_clk _70mhz=1 +sw_build_device=sim_dv +sw_images=sram_ctrl_scrambled_access_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3269340551 -assert nopostproc +UVM_TESTNA ME=chip_base_test +UVM_TEST_SEQ=chip_sw_sram_ctrl_scrambled_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/ default.vdb -cm_log /dev/null -cm_name 0.chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq.3269340551 |
| Directory | /workspace/0.chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq/latest |
| Test location | /workspace/coverage/cover_reg_top/25.xbar_stress_all.201771606 |
| Short name | T437 |
| Test name | |
| Test status | |
| Simulation time | 14240013923 ps |
| CPU time | 631.31 seconds |
| Started | Jun 29 08:18:47 PM PDT 24 |
| Finished | Jun 29 08:29:19 PM PDT 24 |
| Peak memory | 575644 kb |
| Host | smart-038b2d55-520d-45e7-b1a4-77d5ed458299 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=201771606 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.xbar_stress_all.201771606 |
| Directory | /workspace/25.xbar_stress_all/latest |
| Test location | /workspace/coverage/default/0.chip_sw_rstmgr_cpu_info.3763947448 |
| Short name | T219 |
| Test name | |
| Test status | |
| Simulation time | 7176311844 ps |
| CPU time | 803.07 seconds |
| Started | Jun 29 07:39:08 PM PDT 24 |
| Finished | Jun 29 07:52:31 PM PDT 24 |
| Peak memory | 608004 kb |
| Host | smart-5dd1dd98-fe2d-4d9e-91b2-de20a557955a |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=rstmgr_cpu_info_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3763947448 -assert nopostproc +UVM_TESTNA ME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 0.chip_sw_rstmgr_cpu_info.3763947448 |
| Directory | /workspace/0.chip_sw_rstmgr_cpu_info/latest |
| Test location | /workspace/coverage/default/0.chip_sw_sleep_pin_retention.2830015827 |
| Short name | T9 |
| Test name | |
| Test status | |
| Simulation time | 3406304840 ps |
| CPU time | 357.84 seconds |
| Started | Jun 29 07:42:45 PM PDT 24 |
| Finished | Jun 29 07:48:43 PM PDT 24 |
| Peak memory | 607980 kb |
| Host | smart-a9d668e2-3df0-43a5-abe4-63b154d766d4 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=sleep_pin_retention_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2830015827 -assert nopostproc +UVM_TE STNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sleep_pin_retention_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def ault.vdb -cm_log /dev/null -cm_name 0.chip_sw_sleep_pin_retention.2830015827 |
| Directory | /workspace/0.chip_sw_sleep_pin_retention/latest |
| Test location | /workspace/coverage/cover_reg_top/93.xbar_stress_all_with_rand_reset.1658999166 |
| Short name | T462 |
| Test name | |
| Test status | |
| Simulation time | 9458955545 ps |
| CPU time | 1164.46 seconds |
| Started | Jun 29 08:30:25 PM PDT 24 |
| Finished | Jun 29 08:49:50 PM PDT 24 |
| Peak memory | 575500 kb |
| Host | smart-d41692ad-41e0-4e1c-9d9b-e72d53be7e9f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1658999166 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 93.xbar_stress_all _with_rand_reset.1658999166 |
| Directory | /workspace/93.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/1.chip_sw_edn_entropy_reqs_jitter.4041345422 |
| Short name | T109 |
| Test name | |
| Test status | |
| Simulation time | 6472224785 ps |
| CPU time | 1094.63 seconds |
| Started | Jun 29 07:53:42 PM PDT 24 |
| Finished | Jun 29 08:11:57 PM PDT 24 |
| Peak memory | 608620 kb |
| Host | smart-9b647ff1-0599-42c7-bf6f-02c5d213c543 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=15000000 +rng_srate_value_min=15 +rng_srate_value_max=30 +en_jitter=1 +sw_build_device=sim_dv +sw_images=e ntropy_src_edn_reqs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4041345422 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_edn_entropy_reqs_jitter.4041345422 |
| Directory | /workspace/1.chip_sw_edn_entropy_reqs_jitter/latest |
| Test location | /workspace/coverage/default/69.chip_sw_all_escalation_resets.2484131590 |
| Short name | T80 |
| Test name | |
| Test status | |
| Simulation time | 5174063540 ps |
| CPU time | 577.38 seconds |
| Started | Jun 29 08:12:14 PM PDT 24 |
| Finished | Jun 29 08:21:51 PM PDT 24 |
| Peak memory | 648536 kb |
| Host | smart-a848a8cc-0280-4098-ad8d-5d60f2ced349 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 2484131590 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.chip_sw_all_escalation_resets.2484131590 |
| Directory | /workspace/69.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/cover_reg_top/47.xbar_same_source.1072863604 |
| Short name | T73 |
| Test name | |
| Test status | |
| Simulation time | 2559797300 ps |
| CPU time | 83.73 seconds |
| Started | Jun 29 08:22:57 PM PDT 24 |
| Finished | Jun 29 08:24:21 PM PDT 24 |
| Peak memory | 575332 kb |
| Host | smart-85597982-8ac3-401e-b004-517f211602c6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1072863604 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.xbar_same_source.1072863604 |
| Directory | /workspace/47.xbar_same_source/latest |
| Test location | /workspace/coverage/default/22.chip_sw_alert_handler_lpg_sleep_mode_alerts.1778876384 |
| Short name | T356 |
| Test name | |
| Test status | |
| Simulation time | 4191808508 ps |
| CPU time | 377.24 seconds |
| Started | Jun 29 08:08:28 PM PDT 24 |
| Finished | Jun 29 08:14:46 PM PDT 24 |
| Peak memory | 646956 kb |
| Host | smart-830e9654-5460-4895-b9fa-eadf05c2c640 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1778876384 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.chip_ sw_alert_handler_lpg_sleep_mode_alerts.1778876384 |
| Directory | /workspace/22.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/1.chip_sw_flash_ctrl_lc_rw_en.3777306395 |
| Short name | T213 |
| Test name | |
| Test status | |
| Simulation time | 5324510952 ps |
| CPU time | 645.61 seconds |
| Started | Jun 29 07:40:49 PM PDT 24 |
| Finished | Jun 29 07:51:36 PM PDT 24 |
| Peak memory | 609184 kb |
| Host | smart-b92e11f9-afd3-4721-97dd-c758faa6485e |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=flash_ctrl_lc_rw_en_test:1:new_rules,test_rom:0 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37 77306395 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_flash_ctrl_lc_rw_en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_flash_ctrl_lc_rw_en.3777306395 |
| Directory | /workspace/1.chip_sw_flash_ctrl_lc_rw_en/latest |
| Test location | /workspace/coverage/cover_reg_top/56.xbar_stress_all_with_rand_reset.2592524947 |
| Short name | T455 |
| Test name | |
| Test status | |
| Simulation time | 6086452682 ps |
| CPU time | 702.62 seconds |
| Started | Jun 29 08:24:30 PM PDT 24 |
| Finished | Jun 29 08:36:13 PM PDT 24 |
| Peak memory | 576468 kb |
| Host | smart-62825891-578a-4dfa-9128-7c9bcaf5d004 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2592524947 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 56.xbar_stress_all _with_rand_reset.2592524947 |
| Directory | /workspace/56.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/23.chip_sw_all_escalation_resets.702091528 |
| Short name | T224 |
| Test name | |
| Test status | |
| Simulation time | 5131407680 ps |
| CPU time | 772.2 seconds |
| Started | Jun 29 08:09:22 PM PDT 24 |
| Finished | Jun 29 08:22:14 PM PDT 24 |
| Peak memory | 643360 kb |
| Host | smart-8885c0a0-75fb-4833-baa3-f75f3f2ab3b8 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 702091528 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.chip_sw_all_escalation_resets.702091528 |
| Directory | /workspace/23.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/cover_reg_top/19.chip_same_csr_outstanding.2534292579 |
| Short name | T390 |
| Test name | |
| Test status | |
| Simulation time | 29243930460 ps |
| CPU time | 3799.11 seconds |
| Started | Jun 29 08:17:00 PM PDT 24 |
| Finished | Jun 29 09:20:20 PM PDT 24 |
| Peak memory | 591844 kb |
| Host | smart-a09af1a2-ba90-41c1-bf37-fcde943f00ed |
| User | root |
| Command | /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +run_same_csr_outstanding +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2534292579 -assert nopostproc +UVM_TE STNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb - cm_log /dev/null -cm_name 19.chip_same_csr_outstanding.2534292579 |
| Directory | /workspace/19.chip_same_csr_outstanding/latest |
| Test location | /workspace/coverage/default/0.chip_sw_csrng_lc_hw_debug_en_test.3792304859 |
| Short name | T116 |
| Test name | |
| Test status | |
| Simulation time | 6718965591 ps |
| CPU time | 583.77 seconds |
| Started | Jun 29 07:41:27 PM PDT 24 |
| Finished | Jun 29 07:51:11 PM PDT 24 |
| Peak memory | 609240 kb |
| Host | smart-4ed8c8c0-ed77-4b7d-a847-694630f0a6a5 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=15_000_000 +rng_srate_value_min=15 +use_otp_image=OtpTypeLcStTestUnlocked0 +sw_build_device=sim_dv +sw_ima ges=csrng_lc_hw_debug_en_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3792304859 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_csrng_ lc_hw_debug_en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_csr ng_lc_hw_debug_en_test.3792304859 |
| Directory | /workspace/0.chip_sw_csrng_lc_hw_debug_en_test/latest |
| Test location | /workspace/coverage/default/2.chip_sw_flash_ctrl_ops_jitter_en.2320381896 |
| Short name | T111 |
| Test name | |
| Test status | |
| Simulation time | 4429794896 ps |
| CPU time | 812.44 seconds |
| Started | Jun 29 07:54:21 PM PDT 24 |
| Finished | Jun 29 08:07:54 PM PDT 24 |
| Peak memory | 609156 kb |
| Host | smart-9bc11716-371b-4ec3-949d-6e82b4e0a932 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=50_000_000 +en_jitter=1 +sw_build_device=sim_dv +sw_images=flash_ctrl_ops_test:1:new_rules,test_rom:0 +cdc _instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see d=2320381896 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_flash_ctrl_ops_jitter_en.2320381896 |
| Directory | /workspace/2.chip_sw_flash_ctrl_ops_jitter_en/latest |
| Test location | /workspace/coverage/cover_reg_top/29.chip_tl_errors.2637419077 |
| Short name | T555 |
| Test name | |
| Test status | |
| Simulation time | 3622826744 ps |
| CPU time | 263.42 seconds |
| Started | Jun 29 08:19:29 PM PDT 24 |
| Finished | Jun 29 08:23:53 PM PDT 24 |
| Peak memory | 602508 kb |
| Host | smart-4e7ed13f-fdcc-4648-8335-1a59127b80c6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2637419077 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.chip_tl_errors.2637419077 |
| Directory | /workspace/29.chip_tl_errors/latest |
| Test location | /workspace/coverage/default/1.chip_tap_straps_testunlock0.3761482226 |
| Short name | T65 |
| Test name | |
| Test status | |
| Simulation time | 4549469966 ps |
| CPU time | 292.26 seconds |
| Started | Jun 29 07:49:15 PM PDT 24 |
| Finished | Jun 29 07:54:07 PM PDT 24 |
| Peak memory | 620396 kb |
| Host | smart-fb3adc74-5a13-4539-880d-45646459958e |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStTestUnlocked0 +create_jtag_riscv_map=1 +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:te st_in_rom:new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3761482226 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_tap_straps_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_tap_straps_testunlock0.3761482226 |
| Directory | /workspace/1.chip_tap_straps_testunlock0/latest |
| Test location | /workspace/coverage/default/2.chip_sw_sensor_ctrl_alert.371059492 |
| Short name | T119 |
| Test name | |
| Test status | |
| Simulation time | 8896437874 ps |
| CPU time | 1265.23 seconds |
| Started | Jun 29 08:00:06 PM PDT 24 |
| Finished | Jun 29 08:21:12 PM PDT 24 |
| Peak memory | 609188 kb |
| Host | smart-e3c3a6e4-29c0-4041-8053-9a791fa547a3 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=40_000_000 +sw_build_device=sim_dv +sw_images=sensor_ctrl_alert_test:1:new_rules,test_rom:0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37105949 2 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace /coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_sensor_ctrl_alert.371059492 |
| Directory | /workspace/2.chip_sw_sensor_ctrl_alert/latest |
| Test location | /workspace/coverage/default/2.chip_jtag_csr_rw.615944440 |
| Short name | T57 |
| Test name | |
| Test status | |
| Simulation time | 9097965140 ps |
| CPU time | 1088.77 seconds |
| Started | Jun 29 07:52:41 PM PDT 24 |
| Finished | Jun 29 08:10:50 PM PDT 24 |
| Peak memory | 601796 kb |
| Host | smart-ea030f0d-11a3-4f84-94b9-f38f25494729 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +csr_rw +create_jtag_riscv_map=1 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=615944440 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TE ST_SEQ=chip_jtag_csr_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.ch ip_jtag_csr_rw.615944440 |
| Directory | /workspace/2.chip_jtag_csr_rw/latest |
| Test location | /workspace/coverage/default/0.chip_sw_sleep_pin_wake.220624408 |
| Short name | T13 |
| Test name | |
| Test status | |
| Simulation time | 6232158520 ps |
| CPU time | 393.94 seconds |
| Started | Jun 29 07:39:25 PM PDT 24 |
| Finished | Jun 29 07:46:00 PM PDT 24 |
| Peak memory | 608200 kb |
| Host | smart-4e8e18d6-b04b-4b47-b079-df522b68ab88 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStProd +sw_build_device=sim_dv +sw_images=sleep_pin_wake_test:1:new_rules,test_rom:0 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=220624408 - assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sleep_pin_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_sleep_pin_wake.220624408 |
| Directory | /workspace/0.chip_sw_sleep_pin_wake/latest |
| Test location | /workspace/coverage/default/2.chip_plic_all_irqs_0.2752682144 |
| Short name | T291 |
| Test name | |
| Test status | |
| Simulation time | 6774982922 ps |
| CPU time | 1418.94 seconds |
| Started | Jun 29 07:59:16 PM PDT 24 |
| Finished | Jun 29 08:22:56 PM PDT 24 |
| Peak memory | 607132 kb |
| Host | smart-5c5a7fab-b841-457e-b831-b5cef07ff53f |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=plic_all_irqs_test_0:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2752682144 -assert nopostproc +UVM_TESTNA ME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 2.chip_plic_all_irqs_0.2752682144 |
| Directory | /workspace/2.chip_plic_all_irqs_0/latest |
| Test location | /workspace/coverage/default/2.chip_sw_sleep_pin_wake.2281748658 |
| Short name | T12 |
| Test name | |
| Test status | |
| Simulation time | 6399105412 ps |
| CPU time | 558.95 seconds |
| Started | Jun 29 07:54:15 PM PDT 24 |
| Finished | Jun 29 08:03:35 PM PDT 24 |
| Peak memory | 608324 kb |
| Host | smart-cb0cd459-1ed5-4f1a-b9a7-6ab37fe15c60 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStProd +sw_build_device=sim_dv +sw_images=sleep_pin_wake_test:1:new_rules,test_rom:0 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2281748658 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sleep_pin_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_sleep_pin_wake.2281748658 |
| Directory | /workspace/2.chip_sw_sleep_pin_wake/latest |
| Test location | /workspace/coverage/default/1.chip_sw_sleep_pin_wake.1694826360 |
| Short name | T8 |
| Test name | |
| Test status | |
| Simulation time | 3643612276 ps |
| CPU time | 251.22 seconds |
| Started | Jun 29 07:42:41 PM PDT 24 |
| Finished | Jun 29 07:46:53 PM PDT 24 |
| Peak memory | 608220 kb |
| Host | smart-49ab9dc0-07d8-4e8f-a69c-6956f53ddab0 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStProd +sw_build_device=sim_dv +sw_images=sleep_pin_wake_test:1:new_rules,test_rom:0 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1694826360 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sleep_pin_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_sleep_pin_wake.1694826360 |
| Directory | /workspace/1.chip_sw_sleep_pin_wake/latest |
| Test location | /workspace/coverage/default/0.chip_sw_pwrmgr_normal_sleep_all_reset_reqs.1643255766 |
| Short name | T90 |
| Test name | |
| Test status | |
| Simulation time | 10492540215 ps |
| CPU time | 1442.71 seconds |
| Started | Jun 29 07:47:03 PM PDT 24 |
| Finished | Jun 29 08:11:06 PM PDT 24 |
| Peak memory | 609024 kb |
| Host | smart-2008156f-61e3-41b6-86b0-e65fc37b80b0 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_normal_sleep_all_reset_reqs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1643255766 -assert nop ostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_deep_sleep_all_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_normal_sleep_all_reset_reqs.1643255766 |
| Directory | /workspace/0.chip_sw_pwrmgr_normal_sleep_all_reset_reqs/latest |
| Test location | /workspace/coverage/cover_reg_top/71.xbar_stress_all_with_rand_reset.1796963386 |
| Short name | T585 |
| Test name | |
| Test status | |
| Simulation time | 10461415061 ps |
| CPU time | 632.99 seconds |
| Started | Jun 29 08:26:51 PM PDT 24 |
| Finished | Jun 29 08:37:25 PM PDT 24 |
| Peak memory | 576524 kb |
| Host | smart-121ef00e-7ccb-4bc3-b57f-feeaea0b234b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1796963386 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 71.xbar_stress_all _with_rand_reset.1796963386 |
| Directory | /workspace/71.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/0.chip_plic_all_irqs_20.1331138773 |
| Short name | T288 |
| Test name | |
| Test status | |
| Simulation time | 5070554700 ps |
| CPU time | 748.41 seconds |
| Started | Jun 29 07:38:31 PM PDT 24 |
| Finished | Jun 29 07:51:00 PM PDT 24 |
| Peak memory | 609180 kb |
| Host | smart-c0ed366a-12c1-4957-9f9c-bf6c1d4bcffd |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=plic_all_irqs_test_20:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1331138773 -assert nopostproc +UVM_TESTN AME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log / dev/null -cm_name 0.chip_plic_all_irqs_20.1331138773 |
| Directory | /workspace/0.chip_plic_all_irqs_20/latest |
| Test location | /workspace/coverage/cover_reg_top/8.chip_tl_errors.125160156 |
| Short name | T557 |
| Test name | |
| Test status | |
| Simulation time | 4584043885 ps |
| CPU time | 446.57 seconds |
| Started | Jun 29 08:13:24 PM PDT 24 |
| Finished | Jun 29 08:20:51 PM PDT 24 |
| Peak memory | 597492 kb |
| Host | smart-1d8319ee-9bea-4002-bcd3-f815c0d3981d |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=125160156 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.chip_tl_errors.125160156 |
| Directory | /workspace/8.chip_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/86.xbar_stress_all_with_rand_reset.4037549441 |
| Short name | T420 |
| Test name | |
| Test status | |
| Simulation time | 9555296368 ps |
| CPU time | 665.23 seconds |
| Started | Jun 29 08:29:17 PM PDT 24 |
| Finished | Jun 29 08:40:22 PM PDT 24 |
| Peak memory | 576524 kb |
| Host | smart-4d6de333-c4d2-4838-914f-af83cc4bd105 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4037549441 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 86.xbar_stress_all _with_rand_reset.4037549441 |
| Directory | /workspace/86.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_fast_dev.2085783097 |
| Short name | T56 |
| Test name | |
| Test status | |
| Simulation time | 3436708200 ps |
| CPU time | 584.87 seconds |
| Started | Jun 29 07:59:14 PM PDT 24 |
| Finished | Jun 29 08:08:59 PM PDT 24 |
| Peak memory | 611916 kb |
| Host | smart-2d23a478-219d-4cd7-bab2-dc4cd6aaaf62 |
| User | root |
| Command | /workspace/default/simv +chip_clock_source=ChipClockSourceExternal96Mhz +calibrate_usb_clk=1 +src_dec_state=DecLcStDev +sw_build_device=sim_dv +sw_ima ges=clkmgr_external_clk_src_for_sw_fast_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2085783097 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ =chip_sw_lc_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_c lkmgr_external_clk_src_for_sw_fast_dev.2085783097 |
| Directory | /workspace/2.chip_sw_clkmgr_external_clk_src_for_sw_fast_dev/latest |
| Test location | /workspace/coverage/cover_reg_top/9.xbar_stress_all_with_rand_reset.3316980701 |
| Short name | T821 |
| Test name | |
| Test status | |
| Simulation time | 5540821548 ps |
| CPU time | 394.8 seconds |
| Started | Jun 29 08:14:05 PM PDT 24 |
| Finished | Jun 29 08:20:40 PM PDT 24 |
| Peak memory | 576512 kb |
| Host | smart-7fbe5adf-be6a-48dd-9a8f-c6e73a3fca8d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3316980701 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.xbar_stress_all_ with_rand_reset.3316980701 |
| Directory | /workspace/9.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/0.chip_sw_lc_ctrl_test_locked0_to_scrap.3348427452 |
| Short name | T5 |
| Test name | |
| Test status | |
| Simulation time | 3466783248 ps |
| CPU time | 163 seconds |
| Started | Jun 29 07:40:26 PM PDT 24 |
| Finished | Jun 29 07:43:10 PM PDT 24 |
| Peak memory | 617548 kb |
| Host | smart-13b8686d-776a-4626-ab18-c18c4a49416d |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +src_dec_state=DecLcStTestLocked0 +sw_build_device=sim_dv +sw_images=lc_ctrl_scrap_test:1:n ew_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3348427452 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_scrap_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_lc_ctrl_test_locked0_to_scrap.3348427452 |
| Directory | /workspace/0.chip_sw_lc_ctrl_test_locked0_to_scrap/latest |
| Test location | /workspace/coverage/default/2.chip_sw_flash_rma_unlocked.3770450305 |
| Short name | T346 |
| Test name | |
| Test status | |
| Simulation time | 44431927211 ps |
| CPU time | 5797.69 seconds |
| Started | Jun 29 07:54:02 PM PDT 24 |
| Finished | Jun 29 09:30:41 PM PDT 24 |
| Peak memory | 622988 kb |
| Host | smart-1a836b89-9e7c-49f0-9e46-77f60d9c29ac |
| User | root |
| Command | /workspace/default/simv +flash_program_latency=5 +sw_test_timeout_ns=150_000_000 +sw_build_device=sim_dv +sw_images=flash_rma_unlocked_test:0:test_in_ rom:new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t cl +ntb_random_seed=3770450305 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_flash_rma_unlocked_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_flash_rma_unlocked.3770450305 |
| Directory | /workspace/2.chip_sw_flash_rma_unlocked/latest |
| Test location | /workspace/coverage/default/0.chip_sw_usbdev_aon_pullup.750717036 |
| Short name | T71 |
| Test name | |
| Test status | |
| Simulation time | 3899786932 ps |
| CPU time | 383.33 seconds |
| Started | Jun 29 07:36:27 PM PDT 24 |
| Finished | Jun 29 07:42:51 PM PDT 24 |
| Peak memory | 609140 kb |
| Host | smart-f0ce68ef-5aaa-4707-a350-e60d420b7d62 |
| User | root |
| Command | /workspace/default/simv +uart_idx=0 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=usbdev_aon_pullup_test:1:new_rules,test_rom:0 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=750717 036 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_usbdev_dpi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_usbdev_aon_pullup.750717036 |
| Directory | /workspace/0.chip_sw_usbdev_aon_pullup/latest |
| Test location | /workspace/coverage/default/0.chip_sw_spi_device_pass_through_collision.1931104028 |
| Short name | T149 |
| Test name | |
| Test status | |
| Simulation time | 4464595505 ps |
| CPU time | 601.56 seconds |
| Started | Jun 29 07:39:23 PM PDT 24 |
| Finished | Jun 29 07:49:26 PM PDT 24 |
| Peak memory | 624288 kb |
| Host | smart-52fb1781-76c4-47f8-85e9-fca0fd2e596f |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=spi_passthrough_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1931104028 -assert nopostproc +UVM_TESTNA ME=chip_base_test +UVM_TEST_SEQ=chip_sw_spi_passthrough_collision_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/d efault.vdb -cm_log /dev/null -cm_name 0.chip_sw_spi_device_pass_through_collision.1931104028 |
| Directory | /workspace/0.chip_sw_spi_device_pass_through_collision/latest |
| Test location | /workspace/coverage/default/2.chip_sw_spi_host_tx_rx.1079276720 |
| Short name | T41 |
| Test name | |
| Test status | |
| Simulation time | 2674426800 ps |
| CPU time | 318.23 seconds |
| Started | Jun 29 07:55:24 PM PDT 24 |
| Finished | Jun 29 08:00:43 PM PDT 24 |
| Peak memory | 607180 kb |
| Host | smart-85c68687-9e69-4d92-925b-c52db7a146d9 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=spi_host_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1079276720 -assert nopostproc +UVM_TESTNAM E=chip_base_test +UVM_TEST_SEQ=chip_sw_spi_host_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb - cm_log /dev/null -cm_name 2.chip_sw_spi_host_tx_rx.1079276720 |
| Directory | /workspace/2.chip_sw_spi_host_tx_rx/latest |
| Test location | /workspace/coverage/cover_reg_top/0.chip_tl_errors.2970509550 |
| Short name | T663 |
| Test name | |
| Test status | |
| Simulation time | 4548234424 ps |
| CPU time | 500.48 seconds |
| Started | Jun 29 08:07:29 PM PDT 24 |
| Finished | Jun 29 08:15:50 PM PDT 24 |
| Peak memory | 603612 kb |
| Host | smart-b8049e43-b998-466d-99c8-f8484e005f15 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2970509550 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.chip_tl_errors.2970509550 |
| Directory | /workspace/0.chip_tl_errors/latest |
| Test location | /workspace/coverage/default/0.chip_rv_dm_ndm_reset_req.2565293332 |
| Short name | T7 |
| Test name | |
| Test status | |
| Simulation time | 3908000360 ps |
| CPU time | 575.16 seconds |
| Started | Jun 29 07:39:14 PM PDT 24 |
| Finished | Jun 29 07:48:50 PM PDT 24 |
| Peak memory | 617508 kb |
| Host | smart-b87b07f0-3631-4e2a-b934-c63e23a228fd |
| User | root |
| Command | /workspace/default/simv +en_scb_tl_err_chk=0 +use_jtag_dmi=1 +sw_build_device=sim_dv +sw_images=rv_dm_ndm_reset_req_rma:1:new_rules,test_rom:0 +cdc_in strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2 565293332 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_rv_dm_ndm_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_rv_dm_ndm_reset_req.2565293332 |
| Directory | /workspace/0.chip_rv_dm_ndm_reset_req/latest |
| Test location | /workspace/coverage/default/0.chip_sw_sensor_ctrl_alert.3709976788 |
| Short name | T123 |
| Test name | |
| Test status | |
| Simulation time | 5239739376 ps |
| CPU time | 566 seconds |
| Started | Jun 29 07:39:32 PM PDT 24 |
| Finished | Jun 29 07:48:59 PM PDT 24 |
| Peak memory | 609176 kb |
| Host | smart-e81e290d-a35f-46cf-a1f4-71b4fef7146d |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=40_000_000 +sw_build_device=sim_dv +sw_images=sensor_ctrl_alert_test:1:new_rules,test_rom:0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37099767 88 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac e/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_sensor_ctrl_alert.3709976788 |
| Directory | /workspace/0.chip_sw_sensor_ctrl_alert/latest |
| Test location | /workspace/coverage/default/3.chip_sw_sensor_ctrl_alert.1449382156 |
| Short name | T124 |
| Test name | |
| Test status | |
| Simulation time | 5292217680 ps |
| CPU time | 630.77 seconds |
| Started | Jun 29 08:03:21 PM PDT 24 |
| Finished | Jun 29 08:13:52 PM PDT 24 |
| Peak memory | 609180 kb |
| Host | smart-a2f877d1-cf7d-47bd-9f6e-614a44a07cda |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=40_000_000 +sw_build_device=sim_dv +sw_images=sensor_ctrl_alert_test:1:new_rules,test_rom:0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14493821 56 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac e/coverage/default.vdb -cm_log /dev/null -cm_name 3.chip_sw_sensor_ctrl_alert.1449382156 |
| Directory | /workspace/3.chip_sw_sensor_ctrl_alert/latest |
| Test location | /workspace/coverage/cover_reg_top/47.xbar_stress_all_with_reset_error.1351098715 |
| Short name | T655 |
| Test name | |
| Test status | |
| Simulation time | 3603042860 ps |
| CPU time | 573.44 seconds |
| Started | Jun 29 08:23:06 PM PDT 24 |
| Finished | Jun 29 08:32:40 PM PDT 24 |
| Peak memory | 576524 kb |
| Host | smart-8bcf6e32-ecb3-4f68-b497-aaf3cfdfeb98 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1351098715 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.xbar_stress_al l_with_reset_error.1351098715 |
| Directory | /workspace/47.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/default/0.chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up.752511594 |
| Short name | T6 |
| Test name | |
| Test status | |
| Simulation time | 6975947738 ps |
| CPU time | 630.16 seconds |
| Started | Jun 29 07:39:15 PM PDT 24 |
| Finished | Jun 29 07:49:46 PM PDT 24 |
| Peak memory | 609328 kb |
| Host | smart-c1d4bb5c-c556-4960-8dce-1aae69bbbe54 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +do_random=1 +sw_build_device=sim_dv +sw_images=pwrmgr_sensor_ctrl_deep_sleep_wake_up:1:new_rul es,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t cl +ntb_random_seed=752511594 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_sensor_ctrl_deep_sl eep_wake_up.752511594 |
| Directory | /workspace/0.chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up/latest |
| Test location | /workspace/coverage/pad_ctrl_test_mode/3.chip_padctrl_attributes.3660832365 |
| Short name | T37 |
| Test name | |
| Test status | |
| Simulation time | 5232976584 ps |
| CPU time | 253.94 seconds |
| Started | Jun 29 08:31:27 PM PDT 24 |
| Finished | Jun 29 08:35:41 PM PDT 24 |
| Peak memory | 640292 kb |
| Host | smart-a7184ed2-74ed-4bd1-bd97-a99bbb9b8f5a |
| User | root |
| Command | /workspace/pad_ctrl_test_mode/simv +use_otp_image=OtpTypeLcStProd +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3660832365 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TE ST_SEQ=chip_padctrl_attributes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/pad_ctrl_test_mode.vdb -cm_log /dev/ null -cm_name 3.chip_padctrl_attributes.3660832365 |
| Directory | /workspace/3.chip_padctrl_attributes/latest |
| Test location | /workspace/coverage/default/1.chip_plic_all_irqs_0.2454090054 |
| Short name | T294 |
| Test name | |
| Test status | |
| Simulation time | 5463043704 ps |
| CPU time | 1336.72 seconds |
| Started | Jun 29 07:48:13 PM PDT 24 |
| Finished | Jun 29 08:10:31 PM PDT 24 |
| Peak memory | 607752 kb |
| Host | smart-a30dcfb5-9972-4fdf-835f-7ded3020a588 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=plic_all_irqs_test_0:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2454090054 -assert nopostproc +UVM_TESTNA ME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 1.chip_plic_all_irqs_0.2454090054 |
| Directory | /workspace/1.chip_plic_all_irqs_0/latest |
| Test location | /workspace/coverage/default/2.chip_sw_otp_ctrl_vendor_test_csr_access.2831707324 |
| Short name | T170 |
| Test name | |
| Test status | |
| Simulation time | 2719116369 ps |
| CPU time | 187.96 seconds |
| Started | Jun 29 07:55:39 PM PDT 24 |
| Finished | Jun 29 07:58:47 PM PDT 24 |
| Peak memory | 616292 kb |
| Host | smart-2406d020-9714-4996-9a80-5cd53289c2c0 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=otp_ctrl_vendor_test_csr_access_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2831707324 -assert nopost proc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_otp_ctrl_vendor_test_csr_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_otp_ctrl_vendor_test_csr_access.2831707324 |
| Directory | /workspace/2.chip_sw_otp_ctrl_vendor_test_csr_access/latest |
| Test location | /workspace/coverage/default/2.chip_plic_all_irqs_20.1244676883 |
| Short name | T297 |
| Test name | |
| Test status | |
| Simulation time | 4941984484 ps |
| CPU time | 703.57 seconds |
| Started | Jun 29 08:00:29 PM PDT 24 |
| Finished | Jun 29 08:12:13 PM PDT 24 |
| Peak memory | 609168 kb |
| Host | smart-dd4a1e5b-6c6f-4f24-bac5-6e0e08fa17a3 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=plic_all_irqs_test_20:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1244676883 -assert nopostproc +UVM_TESTN AME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log / dev/null -cm_name 2.chip_plic_all_irqs_20.1244676883 |
| Directory | /workspace/2.chip_plic_all_irqs_20/latest |
| Test location | /workspace/coverage/cover_reg_top/32.xbar_stress_all_with_rand_reset.1064633228 |
| Short name | T828 |
| Test name | |
| Test status | |
| Simulation time | 2646164747 ps |
| CPU time | 411.17 seconds |
| Started | Jun 29 08:20:18 PM PDT 24 |
| Finished | Jun 29 08:27:10 PM PDT 24 |
| Peak memory | 575508 kb |
| Host | smart-9fc4c7a2-b614-4bc8-a258-3b67c56474c7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1064633228 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.xbar_stress_all _with_rand_reset.1064633228 |
| Directory | /workspace/32.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/92.xbar_stress_all_with_rand_reset.3621789059 |
| Short name | T1470 |
| Test name | |
| Test status | |
| Simulation time | 4609088049 ps |
| CPU time | 572.59 seconds |
| Started | Jun 29 08:30:15 PM PDT 24 |
| Finished | Jun 29 08:39:49 PM PDT 24 |
| Peak memory | 575512 kb |
| Host | smart-32f2df35-05ea-480a-9ef7-db7947fd649b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3621789059 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 92.xbar_stress_all _with_rand_reset.3621789059 |
| Directory | /workspace/92.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/4.chip_csr_hw_reset.3368174167 |
| Short name | T128 |
| Test name | |
| Test status | |
| Simulation time | 7089237696 ps |
| CPU time | 456.69 seconds |
| Started | Jun 29 08:11:56 PM PDT 24 |
| Finished | Jun 29 08:19:33 PM PDT 24 |
| Peak memory | 658960 kb |
| Host | smart-bb62ca14-1928-4dbe-b14a-cbbb7db811f6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3368174167 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.chip_csr_hw_r eset.3368174167 |
| Directory | /workspace/4.chip_csr_hw_reset/latest |
| Test location | /workspace/coverage/default/1.chip_sw_flash_rma_unlocked.427493626 |
| Short name | T1067 |
| Test name | |
| Test status | |
| Simulation time | 44920164082 ps |
| CPU time | 5432.47 seconds |
| Started | Jun 29 07:45:19 PM PDT 24 |
| Finished | Jun 29 09:15:53 PM PDT 24 |
| Peak memory | 623888 kb |
| Host | smart-97ae36b2-149b-41cf-aba4-c176f12e7a5f |
| User | root |
| Command | /workspace/default/simv +flash_program_latency=5 +sw_test_timeout_ns=150_000_000 +sw_build_device=sim_dv +sw_images=flash_rma_unlocked_test:0:test_in_ rom:new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t cl +ntb_random_seed=427493626 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_flash_rma_unlocked_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_flash_rma_unlocked.427493626 |
| Directory | /workspace/1.chip_sw_flash_rma_unlocked/latest |
| Test location | /workspace/coverage/default/1.chip_sw_uart_tx_rx.2117083574 |
| Short name | T301 |
| Test name | |
| Test status | |
| Simulation time | 4656001500 ps |
| CPU time | 685.59 seconds |
| Started | Jun 29 07:42:10 PM PDT 24 |
| Finished | Jun 29 07:53:36 PM PDT 24 |
| Peak memory | 615832 kb |
| Host | smart-4b736a4c-7805-4ab3-bcf5-3cbfdfcc92d3 |
| User | root |
| Command | /workspace/default/simv +uart_idx=0 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2117083574 -a ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_uart_tx_rx.2117083574 |
| Directory | /workspace/1.chip_sw_uart_tx_rx/latest |
| Test location | /workspace/coverage/default/0.chip_sw_power_sleep_load.3898469108 |
| Short name | T666 |
| Test name | |
| Test status | |
| Simulation time | 4625596088 ps |
| CPU time | 512.01 seconds |
| Started | Jun 29 07:42:44 PM PDT 24 |
| Finished | Jun 29 07:51:16 PM PDT 24 |
| Peak memory | 608004 kb |
| Host | smart-184116f1-9de4-464b-89f8-1125a696d6e0 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=chip_power_sleep_load:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3898469108 -assert nopostproc +UVM_TESTN AME=chip_base_test +UVM_TEST_SEQ=chip_sw_power_sleep_load_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v db -cm_log /dev/null -cm_name 0.chip_sw_power_sleep_load.3898469108 |
| Directory | /workspace/0.chip_sw_power_sleep_load/latest |
| Test location | /workspace/coverage/cover_reg_top/14.chip_tl_errors.14232550 |
| Short name | T578 |
| Test name | |
| Test status | |
| Simulation time | 4121763999 ps |
| CPU time | 404.26 seconds |
| Started | Jun 29 08:15:31 PM PDT 24 |
| Finished | Jun 29 08:22:15 PM PDT 24 |
| Peak memory | 597536 kb |
| Host | smart-e535c77a-3489-4114-b6c1-e84d594a037c |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14232550 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.chip_tl_errors.14232550 |
| Directory | /workspace/14.chip_tl_errors/latest |
| Test location | /workspace/coverage/default/1.chip_sw_ast_clk_rst_inputs.1873033056 |
| Short name | T107 |
| Test name | |
| Test status | |
| Simulation time | 14937589740 ps |
| CPU time | 2432.22 seconds |
| Started | Jun 29 07:51:50 PM PDT 24 |
| Finished | Jun 29 08:32:25 PM PDT 24 |
| Peak memory | 608192 kb |
| Host | smart-f0c188c0-e1ca-4e6c-8ee4-1170a9636558 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=200_000_000 +sw_build_device=sim_dv +sw_images=ast_clk_rst_inputs:1:new_rules,test_rom:0 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1873033056 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_ast_clk_rst_inputs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_ast_clk_rst_inputs.1873033056 |
| Directory | /workspace/1.chip_sw_ast_clk_rst_inputs/latest |
| Test location | /workspace/coverage/default/0.chip_sw_uart_tx_rx_idx2.4211741259 |
| Short name | T1051 |
| Test name | |
| Test status | |
| Simulation time | 4364571426 ps |
| CPU time | 654.58 seconds |
| Started | Jun 29 07:41:19 PM PDT 24 |
| Finished | Jun 29 07:52:16 PM PDT 24 |
| Peak memory | 617204 kb |
| Host | smart-f3465fd1-090c-4676-9f20-f57637baf94d |
| User | root |
| Command | /workspace/default/simv +uart_idx=2 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4211741259 -a ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_uart_tx_rx_idx2.4211741259 |
| Directory | /workspace/0.chip_sw_uart_tx_rx_idx2/latest |
| Test location | /workspace/coverage/default/0.chip_sw_uart_tx_rx_alt_clk_freq.1340550365 |
| Short name | T1037 |
| Test name | |
| Test status | |
| Simulation time | 13127714627 ps |
| CPU time | 3620.73 seconds |
| Started | Jun 29 07:42:37 PM PDT 24 |
| Finished | Jun 29 08:42:59 PM PDT 24 |
| Peak memory | 617620 kb |
| Host | smart-e91259c8-5a3f-4685-a41e-099bff5e7053 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=80_000_000 +chip_clock_source=ChipClockSourceExternal96Mhz +calibrate_usb_clk=1 +sw_build_device=sim_dv +s w_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1340550365 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_b audrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_uart_tx_rx _alt_clk_freq.1340550365 |
| Directory | /workspace/0.chip_sw_uart_tx_rx_alt_clk_freq/latest |
| Test location | /workspace/coverage/default/1.chip_plic_all_irqs_10.2442662829 |
| Short name | T167 |
| Test name | |
| Test status | |
| Simulation time | 3444642088 ps |
| CPU time | 635.88 seconds |
| Started | Jun 29 07:47:53 PM PDT 24 |
| Finished | Jun 29 07:58:29 PM PDT 24 |
| Peak memory | 609180 kb |
| Host | smart-bd2365b9-44c6-45e3-b95f-2801cae78c24 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=plic_all_irqs_test_10:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2442662829 -assert nopostproc +UVM_TESTN AME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log / dev/null -cm_name 1.chip_plic_all_irqs_10.2442662829 |
| Directory | /workspace/1.chip_plic_all_irqs_10/latest |
| Test location | /workspace/coverage/default/0.chip_sw_sram_ctrl_execution_main.3641557042 |
| Short name | T185 |
| Test name | |
| Test status | |
| Simulation time | 8193536097 ps |
| CPU time | 1069.94 seconds |
| Started | Jun 29 07:40:30 PM PDT 24 |
| Finished | Jun 29 07:58:22 PM PDT 24 |
| Peak memory | 608204 kb |
| Host | smart-e9c480f4-b7c1-4a5b-88de-372b3a791097 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=sram_ctrl_execution_main_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3641557042 -assert nopostproc +U VM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sram_ctrl_execution_main_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co verage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_sram_ctrl_execution_main.3641557042 |
| Directory | /workspace/0.chip_sw_sram_ctrl_execution_main/latest |
| Test location | /workspace/coverage/cover_reg_top/64.xbar_stress_all_with_rand_reset.185721235 |
| Short name | T479 |
| Test name | |
| Test status | |
| Simulation time | 2663375556 ps |
| CPU time | 431.07 seconds |
| Started | Jun 29 08:25:45 PM PDT 24 |
| Finished | Jun 29 08:32:57 PM PDT 24 |
| Peak memory | 574464 kb |
| Host | smart-5904be7c-b6b5-4114-a52e-8bc9d2cc8ad9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=185721235 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_res et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 64.xbar_stress_all_ with_rand_reset.185721235 |
| Directory | /workspace/64.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/1.chip_same_csr_outstanding.1488952188 |
| Short name | T361 |
| Test name | |
| Test status | |
| Simulation time | 17638878277 ps |
| CPU time | 2252.69 seconds |
| Started | Jun 29 08:08:27 PM PDT 24 |
| Finished | Jun 29 08:46:01 PM PDT 24 |
| Peak memory | 591504 kb |
| Host | smart-51daeecf-6e1f-403a-a43e-dba86fa65189 |
| User | root |
| Command | /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +run_same_csr_outstanding +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1488952188 -assert nopostproc +UVM_TE STNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb - cm_log /dev/null -cm_name 1.chip_same_csr_outstanding.1488952188 |
| Directory | /workspace/1.chip_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/88.xbar_stress_all.1340620555 |
| Short name | T1715 |
| Test name | |
| Test status | |
| Simulation time | 2373229193 ps |
| CPU time | 198.11 seconds |
| Started | Jun 29 08:29:43 PM PDT 24 |
| Finished | Jun 29 08:33:02 PM PDT 24 |
| Peak memory | 575520 kb |
| Host | smart-2ffd7ba9-1903-4254-93f3-a160f7cdea17 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1340620555 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 88.xbar_stress_all.1340620555 |
| Directory | /workspace/88.xbar_stress_all/latest |
| Test location | /workspace/coverage/default/14.chip_sw_all_escalation_resets.1626658774 |
| Short name | T100 |
| Test name | |
| Test status | |
| Simulation time | 4998977962 ps |
| CPU time | 541.87 seconds |
| Started | Jun 29 08:07:13 PM PDT 24 |
| Finished | Jun 29 08:16:16 PM PDT 24 |
| Peak memory | 643476 kb |
| Host | smart-e9c59c15-6998-4523-a4c4-57902e1edf7a |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 1626658774 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.chip_sw_all_escalation_resets.1626658774 |
| Directory | /workspace/14.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/cover_reg_top/14.xbar_stress_all_with_rand_reset.2159963289 |
| Short name | T814 |
| Test name | |
| Test status | |
| Simulation time | 3179925864 ps |
| CPU time | 476.88 seconds |
| Started | Jun 29 08:15:54 PM PDT 24 |
| Finished | Jun 29 08:23:51 PM PDT 24 |
| Peak memory | 575516 kb |
| Host | smart-5d2b0eb8-b819-4169-9a92-fdbae302e9e0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2159963289 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.xbar_stress_all _with_rand_reset.2159963289 |
| Directory | /workspace/14.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/16.chip_tl_errors.598494401 |
| Short name | T665 |
| Test name | |
| Test status | |
| Simulation time | 3402515570 ps |
| CPU time | 200.93 seconds |
| Started | Jun 29 08:16:09 PM PDT 24 |
| Finished | Jun 29 08:19:30 PM PDT 24 |
| Peak memory | 603656 kb |
| Host | smart-9380651f-28aa-46f1-9eac-e78d3f892c74 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=598494401 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.chip_tl_errors.598494401 |
| Directory | /workspace/16.chip_tl_errors/latest |
| Test location | /workspace/coverage/default/0.chip_sw_lc_walkthrough_dev.581909962 |
| Short name | T210 |
| Test name | |
| Test status | |
| Simulation time | 49081354977 ps |
| CPU time | 5298.54 seconds |
| Started | Jun 29 07:39:32 PM PDT 24 |
| Finished | Jun 29 09:07:51 PM PDT 24 |
| Peak memory | 617388 kb |
| Host | smart-b0e2c08f-b91e-4d0d-a8c9-0a859889ca90 |
| User | root |
| Command | /workspace/default/simv +flash_program_latency=5 +use_otp_image=OtpTypeLcStRaw +dest_dec_state=DecLcStDev +sw_test_timeout_ns=200_000_000 +sw_build_de vice=sim_dv +sw_images=lc_walkthrough_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=581909962 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=ch ip_sw_lc_walkthrough_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_ sw_lc_walkthrough_dev.581909962 |
| Directory | /workspace/0.chip_sw_lc_walkthrough_dev/latest |
| Test location | /workspace/coverage/default/0.chip_sw_usbdev_config_host.1680332517 |
| Short name | T32 |
| Test name | |
| Test status | |
| Simulation time | 7851949400 ps |
| CPU time | 2185.59 seconds |
| Started | Jun 29 07:39:56 PM PDT 24 |
| Finished | Jun 29 08:16:23 PM PDT 24 |
| Peak memory | 609184 kb |
| Host | smart-04c4cbd5-c25a-48ea-af27-d9e09099955b |
| User | root |
| Command | /workspace/default/simv +uart_idx=0 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=usbdev_config_host_test:1:new_rules,test_rom:0 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16803 32517 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_usbdev_dpi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_usbdev_config_host.1680332517 |
| Directory | /workspace/0.chip_sw_usbdev_config_host/latest |
| Test location | /workspace/coverage/cover_reg_top/6.xbar_stress_all_with_rand_reset.1141514515 |
| Short name | T795 |
| Test name | |
| Test status | |
| Simulation time | 4078719370 ps |
| CPU time | 507.42 seconds |
| Started | Jun 29 08:12:41 PM PDT 24 |
| Finished | Jun 29 08:21:09 PM PDT 24 |
| Peak memory | 575516 kb |
| Host | smart-caeb8ab2-4812-45cc-b7b9-fda2d484cb9b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1141514515 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.xbar_stress_all_ with_rand_reset.1141514515 |
| Directory | /workspace/6.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/1.chip_sw_keymgr_sideload_aes.349953703 |
| Short name | T204 |
| Test name | |
| Test status | |
| Simulation time | 7950140664 ps |
| CPU time | 1452.03 seconds |
| Started | Jun 29 07:48:05 PM PDT 24 |
| Finished | Jun 29 08:12:17 PM PDT 24 |
| Peak memory | 609248 kb |
| Host | smart-18ec7ce9-a31b-487a-a4c1-669792c2a8c3 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=20_000_000 +sw_build_device=sim_dv +sw_images=keymgr_sideload_aes_test:1:new_rules,test_rom:0 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=349953 703 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_keymgr_sideload_aes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_keymgr_sideload_aes.349953703 |
| Directory | /workspace/1.chip_sw_keymgr_sideload_aes/latest |
| Test location | /workspace/coverage/default/1.chip_sw_otp_ctrl_vendor_test_csr_access.644677276 |
| Short name | T171 |
| Test name | |
| Test status | |
| Simulation time | 2374769854 ps |
| CPU time | 99.13 seconds |
| Started | Jun 29 07:40:19 PM PDT 24 |
| Finished | Jun 29 07:41:59 PM PDT 24 |
| Peak memory | 615644 kb |
| Host | smart-1529ff80-b73f-4e98-953b-eb6fd007b89d |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=otp_ctrl_vendor_test_csr_access_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=644677276 -assert nopostp roc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_otp_ctrl_vendor_test_csr_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_otp_ctrl_vendor_test_csr_access.644677276 |
| Directory | /workspace/1.chip_sw_otp_ctrl_vendor_test_csr_access/latest |
| Test location | /workspace/coverage/cover_reg_top/69.xbar_access_same_device.3083818331 |
| Short name | T471 |
| Test name | |
| Test status | |
| Simulation time | 3803142542 ps |
| CPU time | 165.61 seconds |
| Started | Jun 29 08:26:23 PM PDT 24 |
| Finished | Jun 29 08:29:09 PM PDT 24 |
| Peak memory | 575440 kb |
| Host | smart-c7d3681c-ed54-4014-a005-2fd36c43f63d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3083818331 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 69.xbar_access_same_device .3083818331 |
| Directory | /workspace/69.xbar_access_same_device/latest |
| Test location | /workspace/coverage/default/0.chip_sw_entropy_src_csrng.3447053603 |
| Short name | T300 |
| Test name | |
| Test status | |
| Simulation time | 6404247600 ps |
| CPU time | 1298.87 seconds |
| Started | Jun 29 07:39:52 PM PDT 24 |
| Finished | Jun 29 08:01:32 PM PDT 24 |
| Peak memory | 608104 kb |
| Host | smart-8f1f2e58-12fb-4269-a547-c6ba068ac2f7 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=50_000_000 +rng_srate_value_min=15 +rng_srate_value_max=30 +sw_build_device=sim_dv +sw_images=entropy_src_ csrng_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3447053603 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_entropy_src_csrng.3447053603 |
| Directory | /workspace/0.chip_sw_entropy_src_csrng/latest |
| Test location | /workspace/coverage/default/0.chip_sw_flash_ctrl_ops.4060746858 |
| Short name | T342 |
| Test name | |
| Test status | |
| Simulation time | 4086274792 ps |
| CPU time | 710.37 seconds |
| Started | Jun 29 07:38:22 PM PDT 24 |
| Finished | Jun 29 07:50:13 PM PDT 24 |
| Peak memory | 609196 kb |
| Host | smart-6a6fbb63-6d61-4b62-9e70-f1b150e68fc5 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=50_000_000 +sw_build_device=sim_dv +sw_images=flash_ctrl_ops_test:1:new_rules,test_rom:0 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4060746858 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/c overage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_flash_ctrl_ops.4060746858 |
| Directory | /workspace/0.chip_sw_flash_ctrl_ops/latest |
| Test location | /workspace/coverage/default/72.chip_sw_all_escalation_resets.437897404 |
| Short name | T39 |
| Test name | |
| Test status | |
| Simulation time | 5328897786 ps |
| CPU time | 621.46 seconds |
| Started | Jun 29 08:12:57 PM PDT 24 |
| Finished | Jun 29 08:23:19 PM PDT 24 |
| Peak memory | 643404 kb |
| Host | smart-d9e61dfb-dbb2-4d9a-84f7-ce6555cb2890 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 437897404 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.chip_sw_all_escalation_resets.437897404 |
| Directory | /workspace/72.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/0.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted.3027558522 |
| Short name | T232 |
| Test name | |
| Test status | |
| Simulation time | 4242840748 ps |
| CPU time | 475.66 seconds |
| Started | Jun 29 07:40:13 PM PDT 24 |
| Finished | Jun 29 07:48:09 PM PDT 24 |
| Peak memory | 617696 kb |
| Host | smart-31638297-017b-4b6d-8896-57de04624a69 |
| User | root |
| Command | /workspace/default/simv +use_jtag_dmi=1 +sw_build_device=sim_dv +sw_images=rv_dm_ndm_reset_req_when_cpu_halted_rma:1:new_rules,test_rom:0 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=302755 8522 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rv_dm_ndm_reset_when_cpu_halted_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted.3027558522 |
| Directory | /workspace/0.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted/latest |
| Test location | /workspace/coverage/default/2.chip_sw_rv_dm_access_after_escalation_reset.2009288882 |
| Short name | T639 |
| Test name | |
| Test status | |
| Simulation time | 5777578369 ps |
| CPU time | 590.66 seconds |
| Started | Jun 29 08:00:17 PM PDT 24 |
| Finished | Jun 29 08:10:08 PM PDT 24 |
| Peak memory | 618028 kb |
| Host | smart-f3ceee2c-bb27-4d6e-b2a0-e4f930848aeb |
| User | root |
| Command | /workspace/default/simv +use_jtag_dmi=1 +sw_build_device=sim_dv +sw_images=alert_handler_escalation_test:1:new_rules,test_rom:0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2009288882 -asse rt nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rv_dm_access_after_escalation_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_rv_dm_access_after_escalation_reset.2009288882 |
| Directory | /workspace/2.chip_sw_rv_dm_access_after_escalation_reset/latest |
| Test location | /workspace/coverage/default/0.chip_sw_i2c_host_tx_rx_idx2.2658078116 |
| Short name | T321 |
| Test name | |
| Test status | |
| Simulation time | 4979321372 ps |
| CPU time | 910.64 seconds |
| Started | Jun 29 07:38:44 PM PDT 24 |
| Finished | Jun 29 07:53:56 PM PDT 24 |
| Peak memory | 608280 kb |
| Host | smart-3bd56d72-83e4-4122-ba13-df5842512060 |
| User | root |
| Command | /workspace/default/simv +i2c_idx=2 +sw_build_device=sim_dv +sw_images=i2c_host_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2658078116 -assert nopostproc + UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_i2c_host_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de fault.vdb -cm_log /dev/null -cm_name 0.chip_sw_i2c_host_tx_rx_idx2.2658078116 |
| Directory | /workspace/0.chip_sw_i2c_host_tx_rx_idx2/latest |
| Test location | /workspace/coverage/cover_reg_top/33.xbar_stress_all_with_rand_reset.825224884 |
| Short name | T2319 |
| Test name | |
| Test status | |
| Simulation time | 6838605128 ps |
| CPU time | 614.6 seconds |
| Started | Jun 29 08:20:34 PM PDT 24 |
| Finished | Jun 29 08:30:49 PM PDT 24 |
| Peak memory | 576512 kb |
| Host | smart-80197a48-d315-4da4-a93d-f3927711588e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=825224884 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_res et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.xbar_stress_all_ with_rand_reset.825224884 |
| Directory | /workspace/33.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/54.xbar_stress_all_with_rand_reset.1186298893 |
| Short name | T824 |
| Test name | |
| Test status | |
| Simulation time | 92677308 ps |
| CPU time | 89.77 seconds |
| Started | Jun 29 08:24:23 PM PDT 24 |
| Finished | Jun 29 08:25:53 PM PDT 24 |
| Peak memory | 575464 kb |
| Host | smart-d50fa76c-1941-457c-86e7-e093a1821ad2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1186298893 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 54.xbar_stress_all _with_rand_reset.1186298893 |
| Directory | /workspace/54.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/0.chip_sw_alert_handler_lpg_sleep_mode_alerts.82073501 |
| Short name | T680 |
| Test name | |
| Test status | |
| Simulation time | 3880939816 ps |
| CPU time | 413.18 seconds |
| Started | Jun 29 07:47:06 PM PDT 24 |
| Finished | Jun 29 07:54:00 PM PDT 24 |
| Peak memory | 647104 kb |
| Host | smart-a2c65a0d-83d7-4426-9599-fdedc135e146 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82073501 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_ escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_ alert_handler_lpg_sleep_mode_alerts.82073501 |
| Directory | /workspace/0.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/0.chip_sw_all_escalation_resets.2877012506 |
| Short name | T220 |
| Test name | |
| Test status | |
| Simulation time | 5078848588 ps |
| CPU time | 774.71 seconds |
| Started | Jun 29 07:43:28 PM PDT 24 |
| Finished | Jun 29 07:56:23 PM PDT 24 |
| Peak memory | 643720 kb |
| Host | smart-a2647b2b-3985-4c0a-ba86-6efceaf1e5f8 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 2877012506 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_all_escalation_resets.2877012506 |
| Directory | /workspace/0.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/1.chip_sw_alert_handler_lpg_sleep_mode_alerts.3191387176 |
| Short name | T730 |
| Test name | |
| Test status | |
| Simulation time | 3870538968 ps |
| CPU time | 451.51 seconds |
| Started | Jun 29 07:45:05 PM PDT 24 |
| Finished | Jun 29 07:52:37 PM PDT 24 |
| Peak memory | 647352 kb |
| Host | smart-673a450a-3fb7-4738-b0bb-b95fd6e14ef0 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3191387176 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_s w_alert_handler_lpg_sleep_mode_alerts.3191387176 |
| Directory | /workspace/1.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/1.chip_sw_all_escalation_resets.1496644852 |
| Short name | T752 |
| Test name | |
| Test status | |
| Simulation time | 5056512860 ps |
| CPU time | 658.49 seconds |
| Started | Jun 29 07:43:06 PM PDT 24 |
| Finished | Jun 29 07:54:05 PM PDT 24 |
| Peak memory | 643372 kb |
| Host | smart-bd758640-e201-460d-82c7-6a0496cd152c |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 1496644852 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_all_escalation_resets.1496644852 |
| Directory | /workspace/1.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/11.chip_sw_alert_handler_lpg_sleep_mode_alerts.2958504300 |
| Short name | T257 |
| Test name | |
| Test status | |
| Simulation time | 4097158720 ps |
| CPU time | 437.18 seconds |
| Started | Jun 29 08:07:40 PM PDT 24 |
| Finished | Jun 29 08:14:58 PM PDT 24 |
| Peak memory | 642140 kb |
| Host | smart-76d8911a-0c5d-44b4-a0de-c0d41ea25d51 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2958504300 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.chip_ sw_alert_handler_lpg_sleep_mode_alerts.2958504300 |
| Directory | /workspace/11.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/12.chip_sw_alert_handler_lpg_sleep_mode_alerts.3156921846 |
| Short name | T748 |
| Test name | |
| Test status | |
| Simulation time | 3723375042 ps |
| CPU time | 467.4 seconds |
| Started | Jun 29 08:06:25 PM PDT 24 |
| Finished | Jun 29 08:14:13 PM PDT 24 |
| Peak memory | 646944 kb |
| Host | smart-8ab3f542-d5be-4e95-87ee-b2297fc5062b |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3156921846 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.chip_ sw_alert_handler_lpg_sleep_mode_alerts.3156921846 |
| Directory | /workspace/12.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/12.chip_sw_all_escalation_resets.3093823646 |
| Short name | T198 |
| Test name | |
| Test status | |
| Simulation time | 6154050730 ps |
| CPU time | 667.44 seconds |
| Started | Jun 29 08:06:19 PM PDT 24 |
| Finished | Jun 29 08:17:27 PM PDT 24 |
| Peak memory | 643496 kb |
| Host | smart-393902a1-832b-400c-822a-85c17dcefa26 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 3093823646 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.chip_sw_all_escalation_resets.3093823646 |
| Directory | /workspace/12.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/13.chip_sw_alert_handler_lpg_sleep_mode_alerts.4127812471 |
| Short name | T83 |
| Test name | |
| Test status | |
| Simulation time | 4010171792 ps |
| CPU time | 421.03 seconds |
| Started | Jun 29 08:06:29 PM PDT 24 |
| Finished | Jun 29 08:13:30 PM PDT 24 |
| Peak memory | 646952 kb |
| Host | smart-02f0b9e3-5d2d-48ef-9a8c-57cf6e5d9453 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4127812471 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.chip_ sw_alert_handler_lpg_sleep_mode_alerts.4127812471 |
| Directory | /workspace/13.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/13.chip_sw_all_escalation_resets.3668400139 |
| Short name | T85 |
| Test name | |
| Test status | |
| Simulation time | 5229848180 ps |
| CPU time | 649.71 seconds |
| Started | Jun 29 08:06:58 PM PDT 24 |
| Finished | Jun 29 08:17:48 PM PDT 24 |
| Peak memory | 644108 kb |
| Host | smart-a79c7489-b5fb-458d-ae85-05e584b8f9f2 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 3668400139 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.chip_sw_all_escalation_resets.3668400139 |
| Directory | /workspace/13.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/14.chip_sw_alert_handler_lpg_sleep_mode_alerts.1487493650 |
| Short name | T710 |
| Test name | |
| Test status | |
| Simulation time | 4286357800 ps |
| CPU time | 471.12 seconds |
| Started | Jun 29 08:07:19 PM PDT 24 |
| Finished | Jun 29 08:15:11 PM PDT 24 |
| Peak memory | 647132 kb |
| Host | smart-a7983cbf-0c37-49a9-9895-944ddce632ce |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1487493650 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.chip_ sw_alert_handler_lpg_sleep_mode_alerts.1487493650 |
| Directory | /workspace/14.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/15.chip_sw_alert_handler_lpg_sleep_mode_alerts.2082775675 |
| Short name | T693 |
| Test name | |
| Test status | |
| Simulation time | 3578577720 ps |
| CPU time | 351.22 seconds |
| Started | Jun 29 08:06:59 PM PDT 24 |
| Finished | Jun 29 08:12:51 PM PDT 24 |
| Peak memory | 647204 kb |
| Host | smart-1b2be5c7-8d03-40b3-8e60-743e5cd9fc66 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2082775675 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.chip_ sw_alert_handler_lpg_sleep_mode_alerts.2082775675 |
| Directory | /workspace/15.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/15.chip_sw_all_escalation_resets.2078831621 |
| Short name | T684 |
| Test name | |
| Test status | |
| Simulation time | 5175488600 ps |
| CPU time | 653.03 seconds |
| Started | Jun 29 08:07:03 PM PDT 24 |
| Finished | Jun 29 08:17:57 PM PDT 24 |
| Peak memory | 643328 kb |
| Host | smart-32f315fb-b944-47e6-86e0-bc7767219b3f |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 2078831621 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.chip_sw_all_escalation_resets.2078831621 |
| Directory | /workspace/15.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/16.chip_sw_all_escalation_resets.135378099 |
| Short name | T718 |
| Test name | |
| Test status | |
| Simulation time | 5749900000 ps |
| CPU time | 594.6 seconds |
| Started | Jun 29 08:07:25 PM PDT 24 |
| Finished | Jun 29 08:17:20 PM PDT 24 |
| Peak memory | 643428 kb |
| Host | smart-263dfd53-b832-4710-b2e1-60dba72bb062 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 135378099 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.chip_sw_all_escalation_resets.135378099 |
| Directory | /workspace/16.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/17.chip_sw_alert_handler_lpg_sleep_mode_alerts.103337499 |
| Short name | T767 |
| Test name | |
| Test status | |
| Simulation time | 4225713376 ps |
| CPU time | 469.76 seconds |
| Started | Jun 29 08:07:22 PM PDT 24 |
| Finished | Jun 29 08:15:12 PM PDT 24 |
| Peak memory | 642148 kb |
| Host | smart-b55d7052-0ca2-4e77-b711-98e1c85c455a |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=103337499 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all _escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.chip_s w_alert_handler_lpg_sleep_mode_alerts.103337499 |
| Directory | /workspace/17.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/17.chip_sw_all_escalation_resets.244498320 |
| Short name | T327 |
| Test name | |
| Test status | |
| Simulation time | 5651171196 ps |
| CPU time | 800.07 seconds |
| Started | Jun 29 08:08:15 PM PDT 24 |
| Finished | Jun 29 08:21:36 PM PDT 24 |
| Peak memory | 648128 kb |
| Host | smart-620f7a27-39c4-42ba-aaea-14d017d0763d |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 244498320 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.chip_sw_all_escalation_resets.244498320 |
| Directory | /workspace/17.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/18.chip_sw_alert_handler_lpg_sleep_mode_alerts.455664748 |
| Short name | T678 |
| Test name | |
| Test status | |
| Simulation time | 3756662296 ps |
| CPU time | 391.99 seconds |
| Started | Jun 29 08:07:37 PM PDT 24 |
| Finished | Jun 29 08:14:09 PM PDT 24 |
| Peak memory | 647048 kb |
| Host | smart-01468054-f8c2-4903-b2d7-96efb619e2b2 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=455664748 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all _escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.chip_s w_alert_handler_lpg_sleep_mode_alerts.455664748 |
| Directory | /workspace/18.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/2.chip_sw_alert_handler_lpg_sleep_mode_alerts.279999983 |
| Short name | T1252 |
| Test name | |
| Test status | |
| Simulation time | 3784489000 ps |
| CPU time | 421.19 seconds |
| Started | Jun 29 07:58:55 PM PDT 24 |
| Finished | Jun 29 08:05:56 PM PDT 24 |
| Peak memory | 647388 kb |
| Host | smart-f872b3fe-f8c3-4e0e-9479-28ea141f63f5 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=279999983 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all _escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw _alert_handler_lpg_sleep_mode_alerts.279999983 |
| Directory | /workspace/2.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/2.chip_sw_all_escalation_resets.917139284 |
| Short name | T728 |
| Test name | |
| Test status | |
| Simulation time | 4392159036 ps |
| CPU time | 594.62 seconds |
| Started | Jun 29 07:54:02 PM PDT 24 |
| Finished | Jun 29 08:03:56 PM PDT 24 |
| Peak memory | 643460 kb |
| Host | smart-a9dcbd14-bf07-4cc0-98ff-5986d5525d79 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 917139284 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_all_escalation_resets.917139284 |
| Directory | /workspace/2.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/20.chip_sw_alert_handler_lpg_sleep_mode_alerts.4075590089 |
| Short name | T697 |
| Test name | |
| Test status | |
| Simulation time | 4215379796 ps |
| CPU time | 388.07 seconds |
| Started | Jun 29 08:08:15 PM PDT 24 |
| Finished | Jun 29 08:14:44 PM PDT 24 |
| Peak memory | 647056 kb |
| Host | smart-d833d377-cc96-4d53-a388-27e189da7158 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4075590089 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.chip_ sw_alert_handler_lpg_sleep_mode_alerts.4075590089 |
| Directory | /workspace/20.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/20.chip_sw_all_escalation_resets.2962262756 |
| Short name | T682 |
| Test name | |
| Test status | |
| Simulation time | 6050407850 ps |
| CPU time | 643.65 seconds |
| Started | Jun 29 08:06:57 PM PDT 24 |
| Finished | Jun 29 08:17:41 PM PDT 24 |
| Peak memory | 648100 kb |
| Host | smart-f9e4ee19-f864-4b67-b501-82681d0c1ee6 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 2962262756 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.chip_sw_all_escalation_resets.2962262756 |
| Directory | /workspace/20.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/21.chip_sw_alert_handler_lpg_sleep_mode_alerts.2241956121 |
| Short name | T423 |
| Test name | |
| Test status | |
| Simulation time | 3837373998 ps |
| CPU time | 381.63 seconds |
| Started | Jun 29 08:09:17 PM PDT 24 |
| Finished | Jun 29 08:15:39 PM PDT 24 |
| Peak memory | 646908 kb |
| Host | smart-b9093098-a079-45d9-b42f-e3834169fe6d |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2241956121 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.chip_ sw_alert_handler_lpg_sleep_mode_alerts.2241956121 |
| Directory | /workspace/21.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/22.chip_sw_all_escalation_resets.1044490885 |
| Short name | T237 |
| Test name | |
| Test status | |
| Simulation time | 5782646000 ps |
| CPU time | 710.1 seconds |
| Started | Jun 29 08:09:17 PM PDT 24 |
| Finished | Jun 29 08:21:08 PM PDT 24 |
| Peak memory | 643688 kb |
| Host | smart-88d44c25-bfa9-46f3-8ca9-766123528572 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 1044490885 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.chip_sw_all_escalation_resets.1044490885 |
| Directory | /workspace/22.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/23.chip_sw_alert_handler_lpg_sleep_mode_alerts.1196819450 |
| Short name | T694 |
| Test name | |
| Test status | |
| Simulation time | 3367881720 ps |
| CPU time | 344.41 seconds |
| Started | Jun 29 08:07:11 PM PDT 24 |
| Finished | Jun 29 08:12:56 PM PDT 24 |
| Peak memory | 646976 kb |
| Host | smart-c904e08d-2c7d-44c4-ad10-f336aaa5cf31 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1196819450 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.chip_ sw_alert_handler_lpg_sleep_mode_alerts.1196819450 |
| Directory | /workspace/23.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/26.chip_sw_alert_handler_lpg_sleep_mode_alerts.3968408663 |
| Short name | T962 |
| Test name | |
| Test status | |
| Simulation time | 3340046792 ps |
| CPU time | 405.62 seconds |
| Started | Jun 29 08:08:07 PM PDT 24 |
| Finished | Jun 29 08:14:53 PM PDT 24 |
| Peak memory | 647108 kb |
| Host | smart-ba55b274-af4b-4d55-9ebc-d76a36770738 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3968408663 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.chip_ sw_alert_handler_lpg_sleep_mode_alerts.3968408663 |
| Directory | /workspace/26.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/26.chip_sw_all_escalation_resets.1216336774 |
| Short name | T409 |
| Test name | |
| Test status | |
| Simulation time | 5809791200 ps |
| CPU time | 497.15 seconds |
| Started | Jun 29 08:07:33 PM PDT 24 |
| Finished | Jun 29 08:15:51 PM PDT 24 |
| Peak memory | 643412 kb |
| Host | smart-53a0e6d7-7a30-4b62-9bd1-e8b42e92a75a |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 1216336774 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.chip_sw_all_escalation_resets.1216336774 |
| Directory | /workspace/26.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/27.chip_sw_alert_handler_lpg_sleep_mode_alerts.3120859526 |
| Short name | T732 |
| Test name | |
| Test status | |
| Simulation time | 3200439680 ps |
| CPU time | 357.48 seconds |
| Started | Jun 29 08:09:11 PM PDT 24 |
| Finished | Jun 29 08:15:09 PM PDT 24 |
| Peak memory | 647336 kb |
| Host | smart-eb34d2d7-46f4-4c38-9237-a31ec6a2ec83 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3120859526 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.chip_ sw_alert_handler_lpg_sleep_mode_alerts.3120859526 |
| Directory | /workspace/27.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/27.chip_sw_all_escalation_resets.3365790283 |
| Short name | T278 |
| Test name | |
| Test status | |
| Simulation time | 5045506266 ps |
| CPU time | 658.15 seconds |
| Started | Jun 29 08:08:09 PM PDT 24 |
| Finished | Jun 29 08:19:07 PM PDT 24 |
| Peak memory | 643592 kb |
| Host | smart-a2883904-b15a-4fc4-a041-70eb7fed70a1 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 3365790283 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.chip_sw_all_escalation_resets.3365790283 |
| Directory | /workspace/27.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/28.chip_sw_alert_handler_lpg_sleep_mode_alerts.1623531316 |
| Short name | T711 |
| Test name | |
| Test status | |
| Simulation time | 4039401848 ps |
| CPU time | 399.34 seconds |
| Started | Jun 29 08:08:30 PM PDT 24 |
| Finished | Jun 29 08:15:10 PM PDT 24 |
| Peak memory | 646952 kb |
| Host | smart-3a2b6417-a514-4169-a1ca-3bd93588c057 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1623531316 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.chip_ sw_alert_handler_lpg_sleep_mode_alerts.1623531316 |
| Directory | /workspace/28.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/28.chip_sw_all_escalation_resets.673994146 |
| Short name | T686 |
| Test name | |
| Test status | |
| Simulation time | 6171546664 ps |
| CPU time | 670.22 seconds |
| Started | Jun 29 08:08:57 PM PDT 24 |
| Finished | Jun 29 08:20:07 PM PDT 24 |
| Peak memory | 643384 kb |
| Host | smart-5b080d6c-84e0-4b8b-8990-b3c8d72ffe8b |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 673994146 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.chip_sw_all_escalation_resets.673994146 |
| Directory | /workspace/28.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/3.chip_sw_alert_handler_lpg_sleep_mode_alerts.1626327980 |
| Short name | T746 |
| Test name | |
| Test status | |
| Simulation time | 3635843084 ps |
| CPU time | 393.75 seconds |
| Started | Jun 29 08:03:33 PM PDT 24 |
| Finished | Jun 29 08:10:07 PM PDT 24 |
| Peak memory | 642256 kb |
| Host | smart-0a3f67c5-918a-41a8-b345-19565e245f08 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1626327980 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.chip_s w_alert_handler_lpg_sleep_mode_alerts.1626327980 |
| Directory | /workspace/3.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/3.chip_sw_all_escalation_resets.1834468410 |
| Short name | T762 |
| Test name | |
| Test status | |
| Simulation time | 6506772196 ps |
| CPU time | 669.17 seconds |
| Started | Jun 29 08:03:49 PM PDT 24 |
| Finished | Jun 29 08:14:59 PM PDT 24 |
| Peak memory | 643608 kb |
| Host | smart-216f7f95-aabd-4a21-b2bc-36a0fdb216e2 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 1834468410 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.chip_sw_all_escalation_resets.1834468410 |
| Directory | /workspace/3.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/30.chip_sw_alert_handler_lpg_sleep_mode_alerts.2531947386 |
| Short name | T756 |
| Test name | |
| Test status | |
| Simulation time | 3777860700 ps |
| CPU time | 344.7 seconds |
| Started | Jun 29 08:09:41 PM PDT 24 |
| Finished | Jun 29 08:15:26 PM PDT 24 |
| Peak memory | 646992 kb |
| Host | smart-9fc55a83-b89d-48a9-bb9a-7a3aa13a2b3b |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2531947386 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.chip_ sw_alert_handler_lpg_sleep_mode_alerts.2531947386 |
| Directory | /workspace/30.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/30.chip_sw_all_escalation_resets.254768906 |
| Short name | T241 |
| Test name | |
| Test status | |
| Simulation time | 5157174344 ps |
| CPU time | 801.63 seconds |
| Started | Jun 29 08:08:40 PM PDT 24 |
| Finished | Jun 29 08:22:02 PM PDT 24 |
| Peak memory | 643696 kb |
| Host | smart-b9d943b9-bce8-4ae9-82ba-c1992b1077c6 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 254768906 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.chip_sw_all_escalation_resets.254768906 |
| Directory | /workspace/30.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/31.chip_sw_alert_handler_lpg_sleep_mode_alerts.3558074507 |
| Short name | T721 |
| Test name | |
| Test status | |
| Simulation time | 3753326472 ps |
| CPU time | 351.83 seconds |
| Started | Jun 29 08:08:14 PM PDT 24 |
| Finished | Jun 29 08:14:08 PM PDT 24 |
| Peak memory | 647060 kb |
| Host | smart-9a07f566-3696-41f9-b07e-a6bab765f288 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3558074507 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.chip_ sw_alert_handler_lpg_sleep_mode_alerts.3558074507 |
| Directory | /workspace/31.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/32.chip_sw_all_escalation_resets.4244111542 |
| Short name | T734 |
| Test name | |
| Test status | |
| Simulation time | 5168711726 ps |
| CPU time | 875.57 seconds |
| Started | Jun 29 08:09:13 PM PDT 24 |
| Finished | Jun 29 08:23:50 PM PDT 24 |
| Peak memory | 643484 kb |
| Host | smart-53e62c1b-3962-4260-b24b-678a7a03deaa |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 4244111542 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.chip_sw_all_escalation_resets.4244111542 |
| Directory | /workspace/32.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/33.chip_sw_alert_handler_lpg_sleep_mode_alerts.2908410064 |
| Short name | T738 |
| Test name | |
| Test status | |
| Simulation time | 3734851896 ps |
| CPU time | 354.92 seconds |
| Started | Jun 29 08:09:04 PM PDT 24 |
| Finished | Jun 29 08:15:00 PM PDT 24 |
| Peak memory | 646968 kb |
| Host | smart-518fe2f0-9c79-42fc-88b6-1f2a885c3c57 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2908410064 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.chip_ sw_alert_handler_lpg_sleep_mode_alerts.2908410064 |
| Directory | /workspace/33.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/35.chip_sw_all_escalation_resets.2312863094 |
| Short name | T281 |
| Test name | |
| Test status | |
| Simulation time | 4773993770 ps |
| CPU time | 706.13 seconds |
| Started | Jun 29 08:09:35 PM PDT 24 |
| Finished | Jun 29 08:21:22 PM PDT 24 |
| Peak memory | 648096 kb |
| Host | smart-14be92f3-9a39-4ab0-8f37-3c328cd9d641 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 2312863094 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.chip_sw_all_escalation_resets.2312863094 |
| Directory | /workspace/35.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/36.chip_sw_alert_handler_lpg_sleep_mode_alerts.371902152 |
| Short name | T715 |
| Test name | |
| Test status | |
| Simulation time | 4381259768 ps |
| CPU time | 513.63 seconds |
| Started | Jun 29 08:09:28 PM PDT 24 |
| Finished | Jun 29 08:18:03 PM PDT 24 |
| Peak memory | 647576 kb |
| Host | smart-847ae7a5-d7fb-441c-b176-f5adb7331069 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=371902152 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all _escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.chip_s w_alert_handler_lpg_sleep_mode_alerts.371902152 |
| Directory | /workspace/36.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/37.chip_sw_all_escalation_resets.3741872749 |
| Short name | T335 |
| Test name | |
| Test status | |
| Simulation time | 4502848634 ps |
| CPU time | 579.96 seconds |
| Started | Jun 29 08:09:24 PM PDT 24 |
| Finished | Jun 29 08:19:04 PM PDT 24 |
| Peak memory | 648016 kb |
| Host | smart-dab23de1-3a4c-4fcc-a2ad-80c90d421bd0 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 3741872749 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.chip_sw_all_escalation_resets.3741872749 |
| Directory | /workspace/37.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/40.chip_sw_all_escalation_resets.3345491929 |
| Short name | T770 |
| Test name | |
| Test status | |
| Simulation time | 4325338368 ps |
| CPU time | 689.12 seconds |
| Started | Jun 29 08:09:28 PM PDT 24 |
| Finished | Jun 29 08:20:59 PM PDT 24 |
| Peak memory | 643600 kb |
| Host | smart-9c04b111-720a-4b55-8f8d-be960d994961 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 3345491929 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.chip_sw_all_escalation_resets.3345491929 |
| Directory | /workspace/40.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/41.chip_sw_alert_handler_lpg_sleep_mode_alerts.1577233936 |
| Short name | T747 |
| Test name | |
| Test status | |
| Simulation time | 3848669180 ps |
| CPU time | 351.63 seconds |
| Started | Jun 29 08:10:19 PM PDT 24 |
| Finished | Jun 29 08:16:11 PM PDT 24 |
| Peak memory | 647088 kb |
| Host | smart-7f6583b6-fb38-43c7-8d33-bbe0bbd31551 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1577233936 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.chip_ sw_alert_handler_lpg_sleep_mode_alerts.1577233936 |
| Directory | /workspace/41.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/41.chip_sw_all_escalation_resets.1436842668 |
| Short name | T1248 |
| Test name | |
| Test status | |
| Simulation time | 5797070232 ps |
| CPU time | 809.16 seconds |
| Started | Jun 29 08:09:32 PM PDT 24 |
| Finished | Jun 29 08:23:02 PM PDT 24 |
| Peak memory | 647796 kb |
| Host | smart-7bc4a8aa-ed60-432f-b284-b3803c973bd3 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 1436842668 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.chip_sw_all_escalation_resets.1436842668 |
| Directory | /workspace/41.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/42.chip_sw_alert_handler_lpg_sleep_mode_alerts.3368992563 |
| Short name | T758 |
| Test name | |
| Test status | |
| Simulation time | 3717301504 ps |
| CPU time | 430.19 seconds |
| Started | Jun 29 08:09:40 PM PDT 24 |
| Finished | Jun 29 08:16:51 PM PDT 24 |
| Peak memory | 647036 kb |
| Host | smart-dc1673ef-ced6-434e-86d5-e75ed16c1517 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3368992563 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.chip_ sw_alert_handler_lpg_sleep_mode_alerts.3368992563 |
| Directory | /workspace/42.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/42.chip_sw_all_escalation_resets.328938363 |
| Short name | T414 |
| Test name | |
| Test status | |
| Simulation time | 5029095960 ps |
| CPU time | 847.72 seconds |
| Started | Jun 29 08:09:48 PM PDT 24 |
| Finished | Jun 29 08:23:56 PM PDT 24 |
| Peak memory | 643292 kb |
| Host | smart-0389e600-8fb3-4dbe-9019-2abdd81b84f9 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 328938363 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.chip_sw_all_escalation_resets.328938363 |
| Directory | /workspace/42.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/43.chip_sw_all_escalation_resets.3318870413 |
| Short name | T325 |
| Test name | |
| Test status | |
| Simulation time | 5096458844 ps |
| CPU time | 545.55 seconds |
| Started | Jun 29 08:10:45 PM PDT 24 |
| Finished | Jun 29 08:19:51 PM PDT 24 |
| Peak memory | 647896 kb |
| Host | smart-6f4dde8a-8e2d-494b-99ef-164a06c83f96 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 3318870413 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.chip_sw_all_escalation_resets.3318870413 |
| Directory | /workspace/43.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/46.chip_sw_alert_handler_lpg_sleep_mode_alerts.176648945 |
| Short name | T348 |
| Test name | |
| Test status | |
| Simulation time | 3296770070 ps |
| CPU time | 473.76 seconds |
| Started | Jun 29 08:10:13 PM PDT 24 |
| Finished | Jun 29 08:18:07 PM PDT 24 |
| Peak memory | 647012 kb |
| Host | smart-9ee98617-2b84-4d30-ab7e-10d934238d99 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=176648945 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all _escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.chip_s w_alert_handler_lpg_sleep_mode_alerts.176648945 |
| Directory | /workspace/46.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/46.chip_sw_all_escalation_resets.3864001870 |
| Short name | T1031 |
| Test name | |
| Test status | |
| Simulation time | 4397043176 ps |
| CPU time | 558.78 seconds |
| Started | Jun 29 08:09:50 PM PDT 24 |
| Finished | Jun 29 08:19:09 PM PDT 24 |
| Peak memory | 647936 kb |
| Host | smart-70efde91-18e6-4f77-95da-b93ca19d9aea |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 3864001870 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.chip_sw_all_escalation_resets.3864001870 |
| Directory | /workspace/46.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/48.chip_sw_all_escalation_resets.2555127153 |
| Short name | T689 |
| Test name | |
| Test status | |
| Simulation time | 4242018026 ps |
| CPU time | 469.07 seconds |
| Started | Jun 29 08:11:58 PM PDT 24 |
| Finished | Jun 29 08:19:47 PM PDT 24 |
| Peak memory | 647736 kb |
| Host | smart-06efedfc-f9a1-4262-9d6a-4396c962f752 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 2555127153 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.chip_sw_all_escalation_resets.2555127153 |
| Directory | /workspace/48.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/52.chip_sw_all_escalation_resets.3861187716 |
| Short name | T724 |
| Test name | |
| Test status | |
| Simulation time | 4952441710 ps |
| CPU time | 847.69 seconds |
| Started | Jun 29 08:10:26 PM PDT 24 |
| Finished | Jun 29 08:24:34 PM PDT 24 |
| Peak memory | 643460 kb |
| Host | smart-d3e97703-44bb-4895-8bbb-a20539e36d01 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 3861187716 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.chip_sw_all_escalation_resets.3861187716 |
| Directory | /workspace/52.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/55.chip_sw_alert_handler_lpg_sleep_mode_alerts.4145134653 |
| Short name | T719 |
| Test name | |
| Test status | |
| Simulation time | 3702491056 ps |
| CPU time | 363.18 seconds |
| Started | Jun 29 08:10:43 PM PDT 24 |
| Finished | Jun 29 08:16:47 PM PDT 24 |
| Peak memory | 646972 kb |
| Host | smart-2fd374a9-9784-4c02-ae13-5b6e65afbaed |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4145134653 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.chip_ sw_alert_handler_lpg_sleep_mode_alerts.4145134653 |
| Directory | /workspace/55.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/57.chip_sw_alert_handler_lpg_sleep_mode_alerts.3985877964 |
| Short name | T713 |
| Test name | |
| Test status | |
| Simulation time | 2923383704 ps |
| CPU time | 339.09 seconds |
| Started | Jun 29 08:14:44 PM PDT 24 |
| Finished | Jun 29 08:20:24 PM PDT 24 |
| Peak memory | 642432 kb |
| Host | smart-23fdca29-d682-4765-943c-b59a77fe9902 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3985877964 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.chip_ sw_alert_handler_lpg_sleep_mode_alerts.3985877964 |
| Directory | /workspace/57.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/58.chip_sw_all_escalation_resets.3364492986 |
| Short name | T223 |
| Test name | |
| Test status | |
| Simulation time | 5506862138 ps |
| CPU time | 613.38 seconds |
| Started | Jun 29 08:11:25 PM PDT 24 |
| Finished | Jun 29 08:21:38 PM PDT 24 |
| Peak memory | 643356 kb |
| Host | smart-d05a5348-3a65-40b1-859f-179d2b8ab12c |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 3364492986 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.chip_sw_all_escalation_resets.3364492986 |
| Directory | /workspace/58.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/59.chip_sw_alert_handler_lpg_sleep_mode_alerts.2209362609 |
| Short name | T517 |
| Test name | |
| Test status | |
| Simulation time | 3255922336 ps |
| CPU time | 381.34 seconds |
| Started | Jun 29 08:13:03 PM PDT 24 |
| Finished | Jun 29 08:19:25 PM PDT 24 |
| Peak memory | 646892 kb |
| Host | smart-5fd5140c-4e49-4aa3-9264-c4133e48fc04 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2209362609 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.chip_ sw_alert_handler_lpg_sleep_mode_alerts.2209362609 |
| Directory | /workspace/59.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/60.chip_sw_alert_handler_lpg_sleep_mode_alerts.1656579222 |
| Short name | T766 |
| Test name | |
| Test status | |
| Simulation time | 4437255558 ps |
| CPU time | 425.31 seconds |
| Started | Jun 29 08:11:37 PM PDT 24 |
| Finished | Jun 29 08:18:43 PM PDT 24 |
| Peak memory | 647188 kb |
| Host | smart-8d479032-05f7-479b-8aea-cc5074b2f6bb |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1656579222 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.chip_ sw_alert_handler_lpg_sleep_mode_alerts.1656579222 |
| Directory | /workspace/60.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/64.chip_sw_alert_handler_lpg_sleep_mode_alerts.3635061307 |
| Short name | T235 |
| Test name | |
| Test status | |
| Simulation time | 4486564580 ps |
| CPU time | 454.99 seconds |
| Started | Jun 29 08:14:11 PM PDT 24 |
| Finished | Jun 29 08:21:47 PM PDT 24 |
| Peak memory | 647708 kb |
| Host | smart-33f6e9de-654e-48bd-a7b8-962b8ccac594 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3635061307 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.chip_ sw_alert_handler_lpg_sleep_mode_alerts.3635061307 |
| Directory | /workspace/64.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/64.chip_sw_all_escalation_resets.704410321 |
| Short name | T326 |
| Test name | |
| Test status | |
| Simulation time | 5061788850 ps |
| CPU time | 679.96 seconds |
| Started | Jun 29 08:12:27 PM PDT 24 |
| Finished | Jun 29 08:23:48 PM PDT 24 |
| Peak memory | 643740 kb |
| Host | smart-b8ec031d-e77c-46f6-8e58-eca36efeed46 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 704410321 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.chip_sw_all_escalation_resets.704410321 |
| Directory | /workspace/64.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/65.chip_sw_all_escalation_resets.3782814176 |
| Short name | T749 |
| Test name | |
| Test status | |
| Simulation time | 4561691284 ps |
| CPU time | 541.56 seconds |
| Started | Jun 29 08:12:26 PM PDT 24 |
| Finished | Jun 29 08:21:28 PM PDT 24 |
| Peak memory | 643392 kb |
| Host | smart-b67e6cfe-230a-47a3-82f7-c8ce0b66bdea |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 3782814176 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.chip_sw_all_escalation_resets.3782814176 |
| Directory | /workspace/65.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/72.chip_sw_alert_handler_lpg_sleep_mode_alerts.1541584298 |
| Short name | T701 |
| Test name | |
| Test status | |
| Simulation time | 4011638910 ps |
| CPU time | 451.38 seconds |
| Started | Jun 29 08:22:11 PM PDT 24 |
| Finished | Jun 29 08:29:43 PM PDT 24 |
| Peak memory | 642152 kb |
| Host | smart-0a598229-5ae6-4f21-a469-271ff7cbbfeb |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1541584298 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.chip_ sw_alert_handler_lpg_sleep_mode_alerts.1541584298 |
| Directory | /workspace/72.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/8.chip_sw_alert_handler_lpg_sleep_mode_alerts.3227394658 |
| Short name | T769 |
| Test name | |
| Test status | |
| Simulation time | 3896195392 ps |
| CPU time | 412.34 seconds |
| Started | Jun 29 08:06:06 PM PDT 24 |
| Finished | Jun 29 08:12:59 PM PDT 24 |
| Peak memory | 646912 kb |
| Host | smart-253d95cb-0633-4d50-94a0-1bc496a8bb50 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3227394658 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.chip_s w_alert_handler_lpg_sleep_mode_alerts.3227394658 |
| Directory | /workspace/8.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/81.chip_sw_all_escalation_resets.1835973107 |
| Short name | T714 |
| Test name | |
| Test status | |
| Simulation time | 5497229540 ps |
| CPU time | 686.71 seconds |
| Started | Jun 29 08:13:14 PM PDT 24 |
| Finished | Jun 29 08:24:41 PM PDT 24 |
| Peak memory | 643764 kb |
| Host | smart-952ce508-ede7-47b4-91b7-6b9940ec2e39 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 1835973107 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 81.chip_sw_all_escalation_resets.1835973107 |
| Directory | /workspace/81.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/84.chip_sw_all_escalation_resets.3183667411 |
| Short name | T676 |
| Test name | |
| Test status | |
| Simulation time | 5805290860 ps |
| CPU time | 666.76 seconds |
| Started | Jun 29 08:14:05 PM PDT 24 |
| Finished | Jun 29 08:25:12 PM PDT 24 |
| Peak memory | 643816 kb |
| Host | smart-47736866-ab10-4074-86ac-dbeb24abbdd7 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 3183667411 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 84.chip_sw_all_escalation_resets.3183667411 |
| Directory | /workspace/84.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/87.chip_sw_alert_handler_lpg_sleep_mode_alerts.283620786 |
| Short name | T744 |
| Test name | |
| Test status | |
| Simulation time | 3660254130 ps |
| CPU time | 421.29 seconds |
| Started | Jun 29 08:13:38 PM PDT 24 |
| Finished | Jun 29 08:20:40 PM PDT 24 |
| Peak memory | 647044 kb |
| Host | smart-65adcbc4-a8e2-477d-96c5-f4d04de9a060 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=283620786 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all _escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 87.chip_s w_alert_handler_lpg_sleep_mode_alerts.283620786 |
| Directory | /workspace/87.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/9.chip_sw_alert_handler_lpg_sleep_mode_alerts.3289020559 |
| Short name | T764 |
| Test name | |
| Test status | |
| Simulation time | 3299392158 ps |
| CPU time | 412.68 seconds |
| Started | Jun 29 08:06:41 PM PDT 24 |
| Finished | Jun 29 08:13:33 PM PDT 24 |
| Peak memory | 646920 kb |
| Host | smart-d920faa0-dc22-4b91-ad71-46d8bafc826f |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3289020559 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.chip_s w_alert_handler_lpg_sleep_mode_alerts.3289020559 |
| Directory | /workspace/9.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/94.chip_sw_all_escalation_resets.494596607 |
| Short name | T236 |
| Test name | |
| Test status | |
| Simulation time | 4821682352 ps |
| CPU time | 588.57 seconds |
| Started | Jun 29 08:14:32 PM PDT 24 |
| Finished | Jun 29 08:24:21 PM PDT 24 |
| Peak memory | 643712 kb |
| Host | smart-154f3a04-5e19-4045-9f58-474cec99f166 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 494596607 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 94.chip_sw_all_escalation_resets.494596607 |
| Directory | /workspace/94.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/95.chip_sw_all_escalation_resets.1496318146 |
| Short name | T760 |
| Test name | |
| Test status | |
| Simulation time | 4611908216 ps |
| CPU time | 512.39 seconds |
| Started | Jun 29 08:13:51 PM PDT 24 |
| Finished | Jun 29 08:22:23 PM PDT 24 |
| Peak memory | 643540 kb |
| Host | smart-f5fe29be-3951-45a5-addb-c5a0fa8577fb |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 1496318146 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 95.chip_sw_all_escalation_resets.1496318146 |
| Directory | /workspace/95.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/0.chip_sw_hmac_enc.1692186772 |
| Short name | T329 |
| Test name | |
| Test status | |
| Simulation time | 2745987160 ps |
| CPU time | 270.34 seconds |
| Started | Jun 29 07:37:05 PM PDT 24 |
| Finished | Jun 29 07:41:36 PM PDT 24 |
| Peak memory | 607100 kb |
| Host | smart-f4fad6ee-49d4-432f-b635-f4f2f8b71f8c |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=hmac_enc_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1692186772 -assert nopostproc +UVM_TESTNAME=chip _base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_hmac_enc.1692186772 |
| Directory | /workspace/0.chip_sw_hmac_enc/latest |
| Test location | /workspace/coverage/default/0.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.822980154 |
| Short name | T330 |
| Test name | |
| Test status | |
| Simulation time | 13249184143 ps |
| CPU time | 1924.65 seconds |
| Started | Jun 29 07:39:21 PM PDT 24 |
| Finished | Jun 29 08:11:27 PM PDT 24 |
| Peak memory | 617636 kb |
| Host | smart-c87e0950-4707-4d41-a8e4-7125bb2d1b19 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +chip_clock_source=ChipClockSourceExternal48Mhz +sw_build_device=sim_dv +s w_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=822980154 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_ba udrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_uart_tx_rx_ alt_clk_freq_low_speed.822980154 |
| Directory | /workspace/0.chip_sw_uart_tx_rx_alt_clk_freq_low_speed/latest |
| Test location | /workspace/coverage/default/1.chip_sw_rstmgr_alert_info.195407374 |
| Short name | T295 |
| Test name | |
| Test status | |
| Simulation time | 10588317710 ps |
| CPU time | 2394.39 seconds |
| Started | Jun 29 07:46:10 PM PDT 24 |
| Finished | Jun 29 08:26:05 PM PDT 24 |
| Peak memory | 609192 kb |
| Host | smart-05ca4a0d-967f-42fa-a651-cad69c41346a |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=30_000_000 +en_scb_tl_err_chk=0 +sw_build_device=sim_dv +sw_images=rstmgr_alert_info_test:1:new_rules,test _rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb _random_seed=195407374 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_rstmgr_alert_info.195407374 |
| Directory | /workspace/1.chip_sw_rstmgr_alert_info/latest |
| Test location | /workspace/coverage/default/34.chip_sw_all_escalation_resets.3754343770 |
| Short name | T337 |
| Test name | |
| Test status | |
| Simulation time | 5614382156 ps |
| CPU time | 802.32 seconds |
| Started | Jun 29 08:08:32 PM PDT 24 |
| Finished | Jun 29 08:21:55 PM PDT 24 |
| Peak memory | 608656 kb |
| Host | smart-10a31b6d-3c0f-4863-a02b-8e737bbfef8d |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 3754343770 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.chip_sw_all_escalation_resets.3754343770 |
| Directory | /workspace/34.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/0.chip_sw_plic_sw_irq.1806173997 |
| Short name | T228 |
| Test name | |
| Test status | |
| Simulation time | 3723801708 ps |
| CPU time | 391.89 seconds |
| Started | Jun 29 07:39:59 PM PDT 24 |
| Finished | Jun 29 07:46:31 PM PDT 24 |
| Peak memory | 607124 kb |
| Host | smart-cd8c0523-0bd4-4ebe-a5bd-3a3645d0d01c |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=plic_sw_irq_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1806173997 -assert nopostproc +UVM_TESTNAME=c hip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n ull -cm_name 0.chip_sw_plic_sw_irq.1806173997 |
| Directory | /workspace/0.chip_sw_plic_sw_irq/latest |
| Test location | /workspace/coverage/default/0.chip_sw_pwrmgr_full_aon_reset.4107748357 |
| Short name | T1227 |
| Test name | |
| Test status | |
| Simulation time | 7088587256 ps |
| CPU time | 481.42 seconds |
| Started | Jun 29 07:39:40 PM PDT 24 |
| Finished | Jun 29 07:47:42 PM PDT 24 |
| Peak memory | 609172 kb |
| Host | smart-64af5359-2b84-402c-bb8a-958080e4508c |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=rstmgr_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4107748357 -assert nopostproc +UVM_TESTNAME=c hip_base_test +UVM_TEST_SEQ=chip_sw_full_aon_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_ log /dev/null -cm_name 0.chip_sw_pwrmgr_full_aon_reset.4107748357 |
| Directory | /workspace/0.chip_sw_pwrmgr_full_aon_reset/latest |
| Test location | /workspace/coverage/default/0.chip_sw_pwrmgr_random_sleep_power_glitch_reset.2988192615 |
| Short name | T946 |
| Test name | |
| Test status | |
| Simulation time | 40931817436 ps |
| CPU time | 4114.1 seconds |
| Started | Jun 29 07:38:33 PM PDT 24 |
| Finished | Jun 29 08:47:09 PM PDT 24 |
| Peak memory | 609408 kb |
| Host | smart-ddbb538f-6640-47f2-a987-a9fcc9ececb0 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_test_timeout_ns=24_000_000 +sw_build_device=sim_dv +sw_images=pwrmgr_random_sleep_power _glitch_reset_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2988192615 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_random_power_glit ch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_random_s leep_power_glitch_reset.2988192615 |
| Directory | /workspace/0.chip_sw_pwrmgr_random_sleep_power_glitch_reset/latest |
| Test location | /workspace/coverage/default/0.chip_sw_pwrmgr_random_sleep_all_wake_ups.2751802091 |
| Short name | T14 |
| Test name | |
| Test status | |
| Simulation time | 23765782152 ps |
| CPU time | 2134.92 seconds |
| Started | Jun 29 07:40:27 PM PDT 24 |
| Finished | Jun 29 08:16:03 PM PDT 24 |
| Peak memory | 608716 kb |
| Host | smart-f652bbbd-19e8-46f7-808a-5ad97e90ccf6 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +do_random=1 +sw_build_device=sim_dv +sw_images=pwrmgr_random_sleep_all_wake_ups:1:new_rules,te st_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n tb_random_seed=2751802091 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_pwrmgr_deep_sleep_all_wake_ups_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_random_sleep_all_wake_ups.2751802091 |
| Directory | /workspace/0.chip_sw_pwrmgr_random_sleep_all_wake_ups/latest |
| Test location | /workspace/coverage/default/0.chip_tap_straps_dev.3054010846 |
| Short name | T642 |
| Test name | |
| Test status | |
| Simulation time | 6687557271 ps |
| CPU time | 685.95 seconds |
| Started | Jun 29 07:38:54 PM PDT 24 |
| Finished | Jun 29 07:50:20 PM PDT 24 |
| Peak memory | 618168 kb |
| Host | smart-a2f4ac3e-2747-4b76-bc12-0d52ea857571 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStDev +create_jtag_riscv_map=1 +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:test_in_rom: new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=3054010846 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_tap_straps_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_tap_straps_dev.3054010846 |
| Directory | /workspace/0.chip_tap_straps_dev/latest |
| Test location | /workspace/coverage/cover_reg_top/13.xbar_random_zero_delays.1693740690 |
| Short name | T489 |
| Test name | |
| Test status | |
| Simulation time | 557112597 ps |
| CPU time | 40.41 seconds |
| Started | Jun 29 08:15:27 PM PDT 24 |
| Finished | Jun 29 08:16:07 PM PDT 24 |
| Peak memory | 575120 kb |
| Host | smart-ab07733e-357f-438d-99f5-8c974b706b8b |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1693740690 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.xbar_random_zero_del ays.1693740690 |
| Directory | /workspace/13.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/default/0.chip_sw_pwrmgr_lowpower_cancel.848446537 |
| Short name | T312 |
| Test name | |
| Test status | |
| Simulation time | 3843405788 ps |
| CPU time | 365.84 seconds |
| Started | Jun 29 07:41:02 PM PDT 24 |
| Finished | Jun 29 07:47:08 PM PDT 24 |
| Peak memory | 607180 kb |
| Host | smart-a773b813-2103-4b48-98e0-c96b56902dbe |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_lowpower_cancel_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=848446537 -assert nopostproc +UVM_ TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_ log /dev/null -cm_name 0.chip_sw_pwrmgr_lowpower_cancel.848446537 |
| Directory | /workspace/0.chip_sw_pwrmgr_lowpower_cancel/latest |
| Test location | /workspace/coverage/default/1.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.1872301211 |
| Short name | T289 |
| Test name | |
| Test status | |
| Simulation time | 5175278519 ps |
| CPU time | 668.01 seconds |
| Started | Jun 29 07:42:34 PM PDT 24 |
| Finished | Jun 29 07:53:43 PM PDT 24 |
| Peak memory | 618952 kb |
| Host | smart-9a71f67d-ec9a-49c7-950e-658b53b1eaa8 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +chip_clock_source=ChipClockSourceExternal48Mhz +sw_build_device=sim_dv +s w_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1872301211 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_b audrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_uart_tx_rx _alt_clk_freq_low_speed.1872301211 |
| Directory | /workspace/1.chip_sw_uart_tx_rx_alt_clk_freq_low_speed/latest |
| Test location | /workspace/coverage/default/2.chip_plic_all_irqs_10.2154324060 |
| Short name | T168 |
| Test name | |
| Test status | |
| Simulation time | 4162074340 ps |
| CPU time | 656.73 seconds |
| Started | Jun 29 07:58:55 PM PDT 24 |
| Finished | Jun 29 08:09:52 PM PDT 24 |
| Peak memory | 609172 kb |
| Host | smart-0070f177-d81a-4bf6-9a9f-fd9d9d783b86 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=plic_all_irqs_test_10:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2154324060 -assert nopostproc +UVM_TESTN AME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log / dev/null -cm_name 2.chip_plic_all_irqs_10.2154324060 |
| Directory | /workspace/2.chip_plic_all_irqs_10/latest |
| Test location | /workspace/coverage/default/0.chip_sw_adc_ctrl_sleep_debug_cable_wakeup.4235081401 |
| Short name | T1098 |
| Test name | |
| Test status | |
| Simulation time | 18706828078 ps |
| CPU time | 561.38 seconds |
| Started | Jun 29 07:39:47 PM PDT 24 |
| Finished | Jun 29 07:49:10 PM PDT 24 |
| Peak memory | 617452 kb |
| Host | smart-906f6b02-16b2-499b-b466-ba48ed483f02 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=adc_ctrl_sleep_debug_cable_wakeup_test:1:new_rules,test_rom: 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand om_seed=4235081401 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_adc_ctrl_sleep_debug_cable_wakeup_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_adc_ctrl_sleep_debug_cable_wakeup.4235081401 |
| Directory | /workspace/0.chip_sw_adc_ctrl_sleep_debug_cable_wakeup/latest |
| Test location | /workspace/coverage/default/0.chip_sw_edn_entropy_reqs_jitter.8408208 |
| Short name | T1108 |
| Test name | |
| Test status | |
| Simulation time | 8223988052 ps |
| CPU time | 1495.46 seconds |
| Started | Jun 29 07:41:37 PM PDT 24 |
| Finished | Jun 29 08:06:34 PM PDT 24 |
| Peak memory | 609472 kb |
| Host | smart-fbf10f20-b1df-40cb-9cce-35f9b4eaa2d5 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=15000000 +rng_srate_value_min=15 +rng_srate_value_max=30 +en_jitter=1 +sw_build_device=sim_dv +sw_images=e ntropy_src_edn_reqs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=8408208 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_edn_entropy_reqs_jitter.8408208 |
| Directory | /workspace/0.chip_sw_edn_entropy_reqs_jitter/latest |
| Test location | /workspace/coverage/default/0.chip_sw_flash_init.4293808922 |
| Short name | T209 |
| Test name | |
| Test status | |
| Simulation time | 18738447784 ps |
| CPU time | 1727.71 seconds |
| Started | Jun 29 07:38:25 PM PDT 24 |
| Finished | Jun 29 08:07:14 PM PDT 24 |
| Peak memory | 611744 kb |
| Host | smart-ba648841-e177-4ac5-a1b6-53b6dc4b3fa0 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=25_000_000 +sw_build_device=sim_dv +sw_images=flash_init_test:0:test_in_rom:new_rules +cdc_instrumentation _enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4293808922 -as sert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_flash_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac e/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_flash_init.4293808922 |
| Directory | /workspace/0.chip_sw_flash_init/latest |
| Test location | /workspace/coverage/default/0.chip_sw_i2c_host_tx_rx.2505750378 |
| Short name | T308 |
| Test name | |
| Test status | |
| Simulation time | 5547866140 ps |
| CPU time | 831.01 seconds |
| Started | Jun 29 07:38:20 PM PDT 24 |
| Finished | Jun 29 07:52:12 PM PDT 24 |
| Peak memory | 608280 kb |
| Host | smart-9fde1dc1-51cf-4178-86b5-aa9fcdebd819 |
| User | root |
| Command | /workspace/default/simv +i2c_idx=0 +sw_build_device=sim_dv +sw_images=i2c_host_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2505750378 -assert nopostproc + UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_i2c_host_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de fault.vdb -cm_log /dev/null -cm_name 0.chip_sw_i2c_host_tx_rx.2505750378 |
| Directory | /workspace/0.chip_sw_i2c_host_tx_rx/latest |
| Test location | /workspace/coverage/default/0.chip_sw_i2c_host_tx_rx_idx1.101379556 |
| Short name | T369 |
| Test name | |
| Test status | |
| Simulation time | 5309197880 ps |
| CPU time | 777.13 seconds |
| Started | Jun 29 07:38:40 PM PDT 24 |
| Finished | Jun 29 07:51:37 PM PDT 24 |
| Peak memory | 608256 kb |
| Host | smart-24f7a146-e78e-428e-8548-d01d12af9944 |
| User | root |
| Command | /workspace/default/simv +i2c_idx=1 +sw_build_device=sim_dv +sw_images=i2c_host_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=101379556 -assert nopostproc +U VM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_i2c_host_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def ault.vdb -cm_log /dev/null -cm_name 0.chip_sw_i2c_host_tx_rx_idx1.101379556 |
| Directory | /workspace/0.chip_sw_i2c_host_tx_rx_idx1/latest |
| Test location | /workspace/coverage/default/0.chip_sw_lc_ctrl_program_error.1544423089 |
| Short name | T177 |
| Test name | |
| Test status | |
| Simulation time | 4824303624 ps |
| CPU time | 522.22 seconds |
| Started | Jun 29 07:38:31 PM PDT 24 |
| Finished | Jun 29 07:47:14 PM PDT 24 |
| Peak memory | 608444 kb |
| Host | smart-d5a7976c-65b2-4368-9b90-2a4ff580aa7a |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=lc_ctrl_program_error:1:new_rules,test_rom:0 + cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_ seed=1544423089 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_program_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_lc_ctrl_program_error.1544423089 |
| Directory | /workspace/0.chip_sw_lc_ctrl_program_error/latest |
| Test location | /workspace/coverage/default/0.chip_sw_otp_ctrl_vendor_test_csr_access.95311963 |
| Short name | T172 |
| Test name | |
| Test status | |
| Simulation time | 2464878219 ps |
| CPU time | 116.88 seconds |
| Started | Jun 29 07:41:44 PM PDT 24 |
| Finished | Jun 29 07:43:42 PM PDT 24 |
| Peak memory | 615624 kb |
| Host | smart-5943c9e9-f37c-4a0f-827e-c02735997141 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=otp_ctrl_vendor_test_csr_access_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95311963 -assert nopostpr oc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_otp_ctrl_vendor_test_csr_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_otp_ctrl_vendor_test_csr_access.95311963 |
| Directory | /workspace/0.chip_sw_otp_ctrl_vendor_test_csr_access/latest |
| Test location | /workspace/coverage/cover_reg_top/0.chip_csr_rw.3657761400 |
| Short name | T2333 |
| Test name | |
| Test status | |
| Simulation time | 4511518230 ps |
| CPU time | 307.03 seconds |
| Started | Jun 29 08:08:31 PM PDT 24 |
| Finished | Jun 29 08:13:39 PM PDT 24 |
| Peak memory | 597756 kb |
| Host | smart-5aff6785-f56c-4b43-9c75-7b1ac5e08479 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3657761400 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.chip_csr_rw.3657761400 |
| Directory | /workspace/0.chip_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/11.chip_tl_errors.2371004694 |
| Short name | T1829 |
| Test name | |
| Test status | |
| Simulation time | 3436069185 ps |
| CPU time | 147.03 seconds |
| Started | Jun 29 08:14:38 PM PDT 24 |
| Finished | Jun 29 08:17:05 PM PDT 24 |
| Peak memory | 597528 kb |
| Host | smart-94d8e97f-a289-433d-8ab5-bd518a6be0e4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2371004694 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.chip_tl_errors.2371004694 |
| Directory | /workspace/11.chip_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/18.xbar_error_and_unmapped_addr.956998522 |
| Short name | T653 |
| Test name | |
| Test status | |
| Simulation time | 95438204 ps |
| CPU time | 16.51 seconds |
| Started | Jun 29 08:17:01 PM PDT 24 |
| Finished | Jun 29 08:17:18 PM PDT 24 |
| Peak memory | 574272 kb |
| Host | smart-2458fc0b-c0c3-4c66-b70f-f82e5f451e26 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=956998522 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.xbar_error_and_unmapped_addr .956998522 |
| Directory | /workspace/18.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/24.xbar_stress_all_with_error.3776646479 |
| Short name | T600 |
| Test name | |
| Test status | |
| Simulation time | 12319577808 ps |
| CPU time | 492.36 seconds |
| Started | Jun 29 08:18:27 PM PDT 24 |
| Finished | Jun 29 08:26:40 PM PDT 24 |
| Peak memory | 574728 kb |
| Host | smart-8e776826-0051-4e24-8117-70e4cc602468 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3776646479 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.xbar_stress_all_with_error.3776646479 |
| Directory | /workspace/24.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/28.xbar_stress_all_with_error.2402311239 |
| Short name | T601 |
| Test name | |
| Test status | |
| Simulation time | 8810225747 ps |
| CPU time | 382.96 seconds |
| Started | Jun 29 08:19:29 PM PDT 24 |
| Finished | Jun 29 08:25:52 PM PDT 24 |
| Peak memory | 574452 kb |
| Host | smart-087a52e3-7b79-4d85-8923-bcc45a30f844 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2402311239 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.xbar_stress_all_with_error.2402311239 |
| Directory | /workspace/28.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/30.xbar_stress_all_with_reset_error.3690340626 |
| Short name | T603 |
| Test name | |
| Test status | |
| Simulation time | 1201051616 ps |
| CPU time | 215.62 seconds |
| Started | Jun 29 08:19:52 PM PDT 24 |
| Finished | Jun 29 08:23:28 PM PDT 24 |
| Peak memory | 574680 kb |
| Host | smart-147c1088-2775-491e-a31e-cbf857ea807b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3690340626 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.xbar_stress_al l_with_reset_error.3690340626 |
| Directory | /workspace/30.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/77.xbar_stress_all_with_error.4258886213 |
| Short name | T613 |
| Test name | |
| Test status | |
| Simulation time | 15151898901 ps |
| CPU time | 558.72 seconds |
| Started | Jun 29 08:27:56 PM PDT 24 |
| Finished | Jun 29 08:37:15 PM PDT 24 |
| Peak memory | 574736 kb |
| Host | smart-3651276b-7fce-40fd-b1d3-d1775ae23d76 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4258886213 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 77.xbar_stress_all_with_error.4258886213 |
| Directory | /workspace/77.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/97.xbar_stress_all_with_error.3906274906 |
| Short name | T610 |
| Test name | |
| Test status | |
| Simulation time | 9881726085 ps |
| CPU time | 364.78 seconds |
| Started | Jun 29 08:31:18 PM PDT 24 |
| Finished | Jun 29 08:37:23 PM PDT 24 |
| Peak memory | 574680 kb |
| Host | smart-f47b9a1d-f19a-4764-a5ff-3b7e1c5a3ab4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3906274906 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 97.xbar_stress_all_with_error.3906274906 |
| Directory | /workspace/97.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/default/0.chip_sw_rstmgr_alert_info.2031491725 |
| Short name | T222 |
| Test name | |
| Test status | |
| Simulation time | 11295311356 ps |
| CPU time | 1726.3 seconds |
| Started | Jun 29 07:39:35 PM PDT 24 |
| Finished | Jun 29 08:08:22 PM PDT 24 |
| Peak memory | 609196 kb |
| Host | smart-38aaafb5-9e9b-47fa-bd05-61b69ca8076c |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=30_000_000 +en_scb_tl_err_chk=0 +sw_build_device=sim_dv +sw_images=rstmgr_alert_info_test:1:new_rules,test _rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb _random_seed=2031491725 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_rstmgr_alert_info.2031491725 |
| Directory | /workspace/0.chip_sw_rstmgr_alert_info/latest |
| Test location | /workspace/coverage/default/0.chip_sw_rv_core_ibex_nmi_irq.2564415855 |
| Short name | T672 |
| Test name | |
| Test status | |
| Simulation time | 5253881464 ps |
| CPU time | 1026.38 seconds |
| Started | Jun 29 07:47:01 PM PDT 24 |
| Finished | Jun 29 08:04:08 PM PDT 24 |
| Peak memory | 607572 kb |
| Host | smart-1fe7bc44-9116-4128-8fbb-d676fd561925 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=10_000_000 +sw_build_device=sim_dv +sw_images=rv_core_ibex_nmi_irq_test:1:new_rules,test_rom:0 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25644 15855 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_rv_core_ibex_nmi_irq.2564415855 |
| Directory | /workspace/0.chip_sw_rv_core_ibex_nmi_irq/latest |
| Test location | /workspace/coverage/default/2.chip_sw_gpio.2786171915 |
| Short name | T35 |
| Test name | |
| Test status | |
| Simulation time | 3583010464 ps |
| CPU time | 464.97 seconds |
| Started | Jun 29 07:54:14 PM PDT 24 |
| Finished | Jun 29 08:01:59 PM PDT 24 |
| Peak memory | 607952 kb |
| Host | smart-06729a55-becd-479d-b922-7a1d16b0ec5b |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=gpio_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2786171915 -assert nopostproc +UVM_TESTNAME=chip_bas e_test +UVM_TEST_SEQ=chip_sw_gpio_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm _name 2.chip_sw_gpio.2786171915 |
| Directory | /workspace/2.chip_sw_gpio/latest |
| Test location | /workspace/coverage/default/0.chip_tap_straps_testunlock0.1486566793 |
| Short name | T911 |
| Test name | |
| Test status | |
| Simulation time | 2686775037 ps |
| CPU time | 146.41 seconds |
| Started | Jun 29 07:40:32 PM PDT 24 |
| Finished | Jun 29 07:42:58 PM PDT 24 |
| Peak memory | 620292 kb |
| Host | smart-ac2309c5-1063-48d9-9c0d-0fdaba497d2e |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStTestUnlocked0 +create_jtag_riscv_map=1 +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:te st_in_rom:new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1486566793 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_tap_straps_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_tap_straps_testunlock0.1486566793 |
| Directory | /workspace/0.chip_tap_straps_testunlock0/latest |
| Test location | /workspace/coverage/default/0.chip_sw_pattgen_ios.2320193182 |
| Short name | T322 |
| Test name | |
| Test status | |
| Simulation time | 2648127000 ps |
| CPU time | 260.01 seconds |
| Started | Jun 29 07:39:36 PM PDT 24 |
| Finished | Jun 29 07:43:57 PM PDT 24 |
| Peak memory | 607644 kb |
| Host | smart-100d1cd8-03c9-484f-8863-d72792c32c23 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=5_000_000 +sw_build_device=sim_dv +sw_images=pattgen_ios_test:1:new_rules,test_rom:0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2320193182 -ass ert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_patt_ios_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/c overage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pattgen_ios.2320193182 |
| Directory | /workspace/0.chip_sw_pattgen_ios/latest |
| Test location | /workspace/coverage/default/1.chip_sw_pattgen_ios.196620208 |
| Short name | T191 |
| Test name | |
| Test status | |
| Simulation time | 2554834520 ps |
| CPU time | 255.21 seconds |
| Started | Jun 29 07:41:43 PM PDT 24 |
| Finished | Jun 29 07:45:59 PM PDT 24 |
| Peak memory | 608996 kb |
| Host | smart-6b417ad5-1c0f-4dc9-afb8-9becff18c248 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=5_000_000 +sw_build_device=sim_dv +sw_images=pattgen_ios_test:1:new_rules,test_rom:0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=196620208 -asse rt nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_patt_ios_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co verage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pattgen_ios.196620208 |
| Directory | /workspace/1.chip_sw_pattgen_ios/latest |
| Test location | /workspace/coverage/cover_reg_top/0.chip_rv_dm_lc_disabled.1809506379 |
| Short name | T2878 |
| Test name | |
| Test status | |
| Simulation time | 8284244786 ps |
| CPU time | 413.08 seconds |
| Started | Jun 29 08:07:35 PM PDT 24 |
| Finished | Jun 29 08:14:28 PM PDT 24 |
| Peak memory | 589676 kb |
| Host | smart-2a558748-ecc1-4cbc-b66f-0639d2682875 |
| User | root |
| Command | /workspace/cover_reg_top/simv +en_scb=0 +en_scb_tl_err_chk=0 +use_jtag_dmi=1 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1809506379 -assert nopostproc +UVM_TESTNAME=chip_base_t est +UVM_TEST_SEQ=chip_rv_dm_lc_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.chip_rv_dm_lc_disabled.1809506379 |
| Directory | /workspace/0.chip_rv_dm_lc_disabled/latest |
| Test location | /workspace/coverage/default/0.chip_sw_csrng_edn_concurrency.3191771472 |
| Short name | T234 |
| Test name | |
| Test status | |
| Simulation time | 26954303240 ps |
| CPU time | 7033.64 seconds |
| Started | Jun 29 07:38:03 PM PDT 24 |
| Finished | Jun 29 09:35:18 PM PDT 24 |
| Peak memory | 608168 kb |
| Host | smart-934b5ba0-4780-435b-8cc4-debd96ff64a4 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=140_000_000 +rng_srate_value_min=15 +rng_srate_value_max=20 +sw_build_device=sim_dv +sw_images=csrng_edn_c oncurrency_test:1:new_rules,test_rom:0 +accelerate_cold_power_up_time=3 +accelerate_regulators_power_up_time=2 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3191771472 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd b -cm_log /dev/null -cm_name 0.chip_sw_csrng_edn_concurrency.3191771472 |
| Directory | /workspace/0.chip_sw_csrng_edn_concurrency/latest |
| Test location | /workspace/coverage/default/0.chip_sw_edn_boot_mode.1408454291 |
| Short name | T451 |
| Test name | |
| Test status | |
| Simulation time | 3314391700 ps |
| CPU time | 688.61 seconds |
| Started | Jun 29 07:37:46 PM PDT 24 |
| Finished | Jun 29 07:49:15 PM PDT 24 |
| Peak memory | 609268 kb |
| Host | smart-7157f830-4570-4409-a848-56dc108b082c |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +rng_srate_value=5 +sw_build_device=sim_dv +sw_images=edn_boot_mode:1:new_rules,test_rom:0 +acc elerate_cold_power_up_time=3 +accelerate_regulators_power_up_time=2 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1408454291 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ =chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_edn_ boot_mode.1408454291 |
| Directory | /workspace/0.chip_sw_edn_boot_mode/latest |
| Test location | /workspace/coverage/default/0.chip_sw_keymgr_sideload_otbn.2820157061 |
| Short name | T205 |
| Test name | |
| Test status | |
| Simulation time | 15029058200 ps |
| CPU time | 4472.7 seconds |
| Started | Jun 29 07:39:47 PM PDT 24 |
| Finished | Jun 29 08:54:21 PM PDT 24 |
| Peak memory | 609324 kb |
| Host | smart-298adcaf-02ea-4ece-a9b8-93b1021a38bb |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=20_000_000 +sw_build_device=sim_dv +sw_images=keymgr_sideload_otbn_test:1:new_rules,test_rom:0 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28201 57061 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_keymgr_sideload_otbn.2820157061 |
| Directory | /workspace/0.chip_sw_keymgr_sideload_otbn/latest |
| Test location | /workspace/coverage/default/1.chip_sw_rv_core_ibex_lockstep_glitch.3774098627 |
| Short name | T374 |
| Test name | |
| Test status | |
| Simulation time | 2365656830 ps |
| CPU time | 270.46 seconds |
| Started | Jun 29 07:50:50 PM PDT 24 |
| Finished | Jun 29 07:55:21 PM PDT 24 |
| Peak memory | 608392 kb |
| Host | smart-17989730-7774-482d-a95e-c93910a43c04 |
| User | root |
| Command | /workspace/default/simv +disable_assert_final_checks +sw_build_device=sim_dv +sw_images=aes_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3774098627 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rv_core_ibex_lockstep_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_rv_core_ibex_lockstep_glitch.3774098627 |
| Directory | /workspace/1.chip_sw_rv_core_ibex_lockstep_glitch/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_bad_b_good_dev.3190520422 |
| Short name | T1199 |
| Test name | |
| Test status | |
| Simulation time | 24802559304 ps |
| CPU time | 6641.72 seconds |
| Started | Jun 29 07:45:34 PM PDT 24 |
| Finished | Jun 29 09:36:18 PM PDT 24 |
| Peak memory | 608148 kb |
| Host | smart-f93ba0ec-8dff-45d8-a244-7647a537451d |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_corrupted:1: ot_flash_binary:signed:fake_ecdsa_prod_key_0,empty_test_slot_b_fake_ecdsa_prod_key_0:2:ot_flash_binary,otp_img_boot_policy_valid_dev:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=3190520422 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_boot_policy_valid_a_bad_b_good_dev.3190520422 |
| Directory | /workspace/0.rom_e2e_boot_policy_valid_a_bad_b_good_dev/latest |
| Test location | /workspace/coverage/cover_reg_top/0.chip_csr_aliasing.3669122121 |
| Short name | T2665 |
| Test name | |
| Test status | |
| Simulation time | 52614987744 ps |
| CPU time | 9047.7 seconds |
| Started | Jun 29 08:07:33 PM PDT 24 |
| Finished | Jun 29 10:38:22 PM PDT 24 |
| Peak memory | 633952 kb |
| Host | smart-419914e5-c59a-4e70-ab15-2bd5f1456284 |
| User | root |
| Command | /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +csr_aliasing +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3669122121 -assert nopostproc +UVM_TESTNAME=chip_ base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/ null -cm_name 0.chip_csr_aliasing.3669122121 |
| Directory | /workspace/0.chip_csr_aliasing/latest |
| Test location | /workspace/coverage/cover_reg_top/0.chip_csr_bit_bash.3774078448 |
| Short name | T2079 |
| Test name | |
| Test status | |
| Simulation time | 7356086892 ps |
| CPU time | 1075.63 seconds |
| Started | Jun 29 08:07:16 PM PDT 24 |
| Finished | Jun 29 08:25:12 PM PDT 24 |
| Peak memory | 589236 kb |
| Host | smart-8f5c5b78-d293-449b-9c18-0f6dab54fff7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +num_test_csrs=200 +csr_bit_bash +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3774078448 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to p.vdb -cm_log /dev/null -cm_name 0.chip_csr_bit_bash.3774078448 |
| Directory | /workspace/0.chip_csr_bit_bash/latest |
| Test location | /workspace/coverage/cover_reg_top/0.chip_csr_hw_reset.3814966914 |
| Short name | T125 |
| Test name | |
| Test status | |
| Simulation time | 5284779288 ps |
| CPU time | 240.38 seconds |
| Started | Jun 29 08:08:31 PM PDT 24 |
| Finished | Jun 29 08:12:32 PM PDT 24 |
| Peak memory | 662448 kb |
| Host | smart-bad3b555-f39d-4f7a-8a4d-7888367ba72c |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3814966914 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.chip_csr_hw_r eset.3814966914 |
| Directory | /workspace/0.chip_csr_hw_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/0.chip_prim_tl_access.768174261 |
| Short name | T2448 |
| Test name | |
| Test status | |
| Simulation time | 3311039654 ps |
| CPU time | 134.11 seconds |
| Started | Jun 29 08:07:24 PM PDT 24 |
| Finished | Jun 29 08:09:39 PM PDT 24 |
| Peak memory | 589232 kb |
| Host | smart-c856eaad-8af6-4910-9b8b-a665c8dfab78 |
| User | root |
| Command | /workspace/cover_reg_top/simv +en_scb=0 +en_scb_tl_err_chk=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=768174261 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ =chip_prim_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0 .chip_prim_tl_access.768174261 |
| Directory | /workspace/0.chip_prim_tl_access/latest |
| Test location | /workspace/coverage/cover_reg_top/0.chip_same_csr_outstanding.2517635532 |
| Short name | T2130 |
| Test name | |
| Test status | |
| Simulation time | 16228213827 ps |
| CPU time | 2063.93 seconds |
| Started | Jun 29 08:07:19 PM PDT 24 |
| Finished | Jun 29 08:41:43 PM PDT 24 |
| Peak memory | 591904 kb |
| Host | smart-fbec1348-7787-4fc8-8e3a-b741338af041 |
| User | root |
| Command | /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +run_same_csr_outstanding +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2517635532 -assert nopostproc +UVM_TE STNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb - cm_log /dev/null -cm_name 0.chip_same_csr_outstanding.2517635532 |
| Directory | /workspace/0.chip_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/0.xbar_access_same_device.3920716006 |
| Short name | T2822 |
| Test name | |
| Test status | |
| Simulation time | 191275872 ps |
| CPU time | 15.74 seconds |
| Started | Jun 29 08:07:48 PM PDT 24 |
| Finished | Jun 29 08:08:04 PM PDT 24 |
| Peak memory | 575300 kb |
| Host | smart-a950a997-bd8d-4905-b0a2-e8117d072d29 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3920716006 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.xbar_access_same_device. 3920716006 |
| Directory | /workspace/0.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/0.xbar_access_same_device_slow_rsp.2644755338 |
| Short name | T500 |
| Test name | |
| Test status | |
| Simulation time | 43225901458 ps |
| CPU time | 767.24 seconds |
| Started | Jun 29 08:07:51 PM PDT 24 |
| Finished | Jun 29 08:20:39 PM PDT 24 |
| Peak memory | 574384 kb |
| Host | smart-19d357cd-db38-46a6-bfb1-561a61b8e611 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2644755338 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.xbar_access_same_d evice_slow_rsp.2644755338 |
| Directory | /workspace/0.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/0.xbar_error_and_unmapped_addr.4108235017 |
| Short name | T1524 |
| Test name | |
| Test status | |
| Simulation time | 213548925 ps |
| CPU time | 28.6 seconds |
| Started | Jun 29 08:08:05 PM PDT 24 |
| Finished | Jun 29 08:08:34 PM PDT 24 |
| Peak memory | 574516 kb |
| Host | smart-b4b654ec-a513-45fe-b875-ad41eb2f152d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4108235017 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.xbar_error_and_unmapped_addr .4108235017 |
| Directory | /workspace/0.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/0.xbar_error_random.3584833831 |
| Short name | T2290 |
| Test name | |
| Test status | |
| Simulation time | 753841122 ps |
| CPU time | 32.17 seconds |
| Started | Jun 29 08:07:57 PM PDT 24 |
| Finished | Jun 29 08:08:29 PM PDT 24 |
| Peak memory | 574268 kb |
| Host | smart-434d6f2d-09de-4ae8-9bfd-7dd92685f923 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3584833831 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.xbar_error_random.3584833831 |
| Directory | /workspace/0.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/0.xbar_random.30746046 |
| Short name | T2840 |
| Test name | |
| Test status | |
| Simulation time | 1705300477 ps |
| CPU time | 82.46 seconds |
| Started | Jun 29 08:07:41 PM PDT 24 |
| Finished | Jun 29 08:09:04 PM PDT 24 |
| Peak memory | 574244 kb |
| Host | smart-18e8e984-09e6-4489-a26c-171fe97d505d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30746046 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.xbar_random.30746046 |
| Directory | /workspace/0.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/0.xbar_random_large_delays.4116729886 |
| Short name | T1378 |
| Test name | |
| Test status | |
| Simulation time | 7773035044 ps |
| CPU time | 80.72 seconds |
| Started | Jun 29 08:07:39 PM PDT 24 |
| Finished | Jun 29 08:09:00 PM PDT 24 |
| Peak memory | 574380 kb |
| Host | smart-9c88a514-0ba7-45bd-9a53-d91a34f96dad |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4116729886 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.xbar_random_large_delays.4116729886 |
| Directory | /workspace/0.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/0.xbar_random_slow_rsp.3170792586 |
| Short name | T2657 |
| Test name | |
| Test status | |
| Simulation time | 18490400791 ps |
| CPU time | 349.53 seconds |
| Started | Jun 29 08:07:41 PM PDT 24 |
| Finished | Jun 29 08:13:31 PM PDT 24 |
| Peak memory | 575356 kb |
| Host | smart-77038bf5-969d-443f-9a0e-6b8609139cd9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3170792586 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.xbar_random_slow_rsp.3170792586 |
| Directory | /workspace/0.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/0.xbar_random_zero_delays.3970768977 |
| Short name | T1680 |
| Test name | |
| Test status | |
| Simulation time | 79554849 ps |
| CPU time | 11.75 seconds |
| Started | Jun 29 08:07:47 PM PDT 24 |
| Finished | Jun 29 08:07:59 PM PDT 24 |
| Peak memory | 575292 kb |
| Host | smart-3bcb49e2-d1f3-4fd8-a869-694cbb8799db |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3970768977 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.xbar_random_zero_dela ys.3970768977 |
| Directory | /workspace/0.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/0.xbar_same_source.515037951 |
| Short name | T2699 |
| Test name | |
| Test status | |
| Simulation time | 1296979744 ps |
| CPU time | 45.88 seconds |
| Started | Jun 29 08:07:59 PM PDT 24 |
| Finished | Jun 29 08:08:45 PM PDT 24 |
| Peak memory | 575288 kb |
| Host | smart-485ea204-5e62-4758-8113-c74b6be608de |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=515037951 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.xbar_same_source.515037951 |
| Directory | /workspace/0.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/0.xbar_smoke.2013314603 |
| Short name | T2766 |
| Test name | |
| Test status | |
| Simulation time | 51000072 ps |
| CPU time | 7.49 seconds |
| Started | Jun 29 08:07:36 PM PDT 24 |
| Finished | Jun 29 08:07:44 PM PDT 24 |
| Peak memory | 574256 kb |
| Host | smart-59f5fec2-f8c4-4021-9a62-366d9573f0f6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2013314603 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.xbar_smoke.2013314603 |
| Directory | /workspace/0.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/0.xbar_smoke_large_delays.1141865681 |
| Short name | T2063 |
| Test name | |
| Test status | |
| Simulation time | 6523078654 ps |
| CPU time | 75.99 seconds |
| Started | Jun 29 08:07:34 PM PDT 24 |
| Finished | Jun 29 08:08:50 PM PDT 24 |
| Peak memory | 574196 kb |
| Host | smart-dd52db68-94dd-4e6d-a4d9-20f76ea85bf7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1141865681 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.xbar_smoke_large_delays.1141865681 |
| Directory | /workspace/0.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/0.xbar_smoke_slow_rsp.823332400 |
| Short name | T2003 |
| Test name | |
| Test status | |
| Simulation time | 4256820767 ps |
| CPU time | 82.63 seconds |
| Started | Jun 29 08:07:37 PM PDT 24 |
| Finished | Jun 29 08:09:00 PM PDT 24 |
| Peak memory | 574316 kb |
| Host | smart-86c0c747-f2e6-4c92-8634-4f3ea601cf20 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=823332400 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.xbar_smoke_slow_rsp.823332400 |
| Directory | /workspace/0.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/0.xbar_smoke_zero_delays.3475761954 |
| Short name | T2213 |
| Test name | |
| Test status | |
| Simulation time | 45391457 ps |
| CPU time | 7.12 seconds |
| Started | Jun 29 08:07:36 PM PDT 24 |
| Finished | Jun 29 08:07:44 PM PDT 24 |
| Peak memory | 574248 kb |
| Host | smart-8f09264c-4450-4ff4-b2b9-fc16b24b1fff |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3475761954 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.xbar_smoke_zero_delays .3475761954 |
| Directory | /workspace/0.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/0.xbar_stress_all.3942967089 |
| Short name | T2656 |
| Test name | |
| Test status | |
| Simulation time | 17089572649 ps |
| CPU time | 712.82 seconds |
| Started | Jun 29 08:08:10 PM PDT 24 |
| Finished | Jun 29 08:20:03 PM PDT 24 |
| Peak memory | 574392 kb |
| Host | smart-e6ae1a2a-f1d7-4ab0-97e7-9cdd4f3e1521 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3942967089 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.xbar_stress_all.3942967089 |
| Directory | /workspace/0.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/0.xbar_stress_all_with_error.1252473071 |
| Short name | T1429 |
| Test name | |
| Test status | |
| Simulation time | 442655556 ps |
| CPU time | 44.68 seconds |
| Started | Jun 29 08:08:22 PM PDT 24 |
| Finished | Jun 29 08:09:08 PM PDT 24 |
| Peak memory | 574308 kb |
| Host | smart-c9a52a20-6afb-4be1-857b-160b800de8f3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1252473071 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.xbar_stress_all_with_error.1252473071 |
| Directory | /workspace/0.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/0.xbar_stress_all_with_rand_reset.4037813335 |
| Short name | T2666 |
| Test name | |
| Test status | |
| Simulation time | 429467536 ps |
| CPU time | 100.64 seconds |
| Started | Jun 29 08:08:08 PM PDT 24 |
| Finished | Jun 29 08:09:49 PM PDT 24 |
| Peak memory | 575420 kb |
| Host | smart-ebdfb4fe-c0bb-432d-b8ef-82ee17f4acc7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4037813335 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.xbar_stress_all_ with_rand_reset.4037813335 |
| Directory | /workspace/0.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/0.xbar_stress_all_with_reset_error.2919232330 |
| Short name | T2673 |
| Test name | |
| Test status | |
| Simulation time | 389568507 ps |
| CPU time | 150.99 seconds |
| Started | Jun 29 08:08:27 PM PDT 24 |
| Finished | Jun 29 08:10:58 PM PDT 24 |
| Peak memory | 574648 kb |
| Host | smart-5f0b9e76-8064-4986-8311-e84136cfb04e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2919232330 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.xbar_stress_all _with_reset_error.2919232330 |
| Directory | /workspace/0.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/0.xbar_unmapped_addr.2833609809 |
| Short name | T2748 |
| Test name | |
| Test status | |
| Simulation time | 528529221 ps |
| CPU time | 19.58 seconds |
| Started | Jun 29 08:07:56 PM PDT 24 |
| Finished | Jun 29 08:08:16 PM PDT 24 |
| Peak memory | 575128 kb |
| Host | smart-fb64eaf2-9d26-42a5-91d6-b543513f91dd |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2833609809 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.xbar_unmapped_addr.2833609809 |
| Directory | /workspace/0.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/1.chip_csr_aliasing.3790672116 |
| Short name | T2234 |
| Test name | |
| Test status | |
| Simulation time | 38415211554 ps |
| CPU time | 5349.47 seconds |
| Started | Jun 29 08:08:19 PM PDT 24 |
| Finished | Jun 29 09:37:29 PM PDT 24 |
| Peak memory | 592704 kb |
| Host | smart-f9a3ef5d-50ce-495f-98c2-230463d2324a |
| User | root |
| Command | /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +csr_aliasing +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3790672116 -assert nopostproc +UVM_TESTNAME=chip_ base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/ null -cm_name 1.chip_csr_aliasing.3790672116 |
| Directory | /workspace/1.chip_csr_aliasing/latest |
| Test location | /workspace/coverage/cover_reg_top/1.chip_csr_bit_bash.440763517 |
| Short name | T1516 |
| Test name | |
| Test status | |
| Simulation time | 4210494331 ps |
| CPU time | 244.25 seconds |
| Started | Jun 29 08:08:20 PM PDT 24 |
| Finished | Jun 29 08:12:25 PM PDT 24 |
| Peak memory | 588164 kb |
| Host | smart-98670d56-cab1-486c-a95f-dc51f202ec09 |
| User | root |
| Command | /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +num_test_csrs=200 +csr_bit_bash +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=440763517 -assert nopostproc + UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top .vdb -cm_log /dev/null -cm_name 1.chip_csr_bit_bash.440763517 |
| Directory | /workspace/1.chip_csr_bit_bash/latest |
| Test location | /workspace/coverage/cover_reg_top/1.chip_csr_hw_reset.3610084045 |
| Short name | T131 |
| Test name | |
| Test status | |
| Simulation time | 6450296272 ps |
| CPU time | 470.62 seconds |
| Started | Jun 29 08:09:10 PM PDT 24 |
| Finished | Jun 29 08:17:01 PM PDT 24 |
| Peak memory | 657876 kb |
| Host | smart-8dc8a53e-d532-4f40-a757-dbf7600f8ee4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3610084045 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.chip_csr_hw_r eset.3610084045 |
| Directory | /workspace/1.chip_csr_hw_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/1.chip_csr_rw.3208466950 |
| Short name | T1924 |
| Test name | |
| Test status | |
| Simulation time | 5011411060 ps |
| CPU time | 602.79 seconds |
| Started | Jun 29 08:09:06 PM PDT 24 |
| Finished | Jun 29 08:19:09 PM PDT 24 |
| Peak memory | 597376 kb |
| Host | smart-29c9a1fa-f98d-4619-b617-aa251bdbfa46 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3208466950 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.chip_csr_rw.3208466950 |
| Directory | /workspace/1.chip_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/1.chip_prim_tl_access.2337128693 |
| Short name | T1537 |
| Test name | |
| Test status | |
| Simulation time | 5697148669 ps |
| CPU time | 175.32 seconds |
| Started | Jun 29 08:08:33 PM PDT 24 |
| Finished | Jun 29 08:11:29 PM PDT 24 |
| Peak memory | 589136 kb |
| Host | smart-13d6e0e7-e2d7-41de-a858-37e22346972b |
| User | root |
| Command | /workspace/cover_reg_top/simv +en_scb=0 +en_scb_tl_err_chk=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2337128693 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SE Q=chip_prim_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.chip_prim_tl_access.2337128693 |
| Directory | /workspace/1.chip_prim_tl_access/latest |
| Test location | /workspace/coverage/cover_reg_top/1.chip_rv_dm_lc_disabled.2334529947 |
| Short name | T1389 |
| Test name | |
| Test status | |
| Simulation time | 13377499902 ps |
| CPU time | 408.19 seconds |
| Started | Jun 29 08:08:33 PM PDT 24 |
| Finished | Jun 29 08:15:21 PM PDT 24 |
| Peak memory | 588896 kb |
| Host | smart-b57a35e4-12f6-4215-9ffa-8dbb0683d7eb |
| User | root |
| Command | /workspace/cover_reg_top/simv +en_scb=0 +en_scb_tl_err_chk=0 +use_jtag_dmi=1 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2334529947 -assert nopostproc +UVM_TESTNAME=chip_base_t est +UVM_TEST_SEQ=chip_rv_dm_lc_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.chip_rv_dm_lc_disabled.2334529947 |
| Directory | /workspace/1.chip_rv_dm_lc_disabled/latest |
| Test location | /workspace/coverage/cover_reg_top/1.chip_tl_errors.2304821436 |
| Short name | T2468 |
| Test name | |
| Test status | |
| Simulation time | 3602355552 ps |
| CPU time | 274.75 seconds |
| Started | Jun 29 08:08:29 PM PDT 24 |
| Finished | Jun 29 08:13:04 PM PDT 24 |
| Peak memory | 603568 kb |
| Host | smart-e1301e3e-2442-4ea5-a0ab-fbce7121d8b7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2304821436 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.chip_tl_errors.2304821436 |
| Directory | /workspace/1.chip_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/1.xbar_access_same_device.2710238653 |
| Short name | T1625 |
| Test name | |
| Test status | |
| Simulation time | 1097527213 ps |
| CPU time | 51.32 seconds |
| Started | Jun 29 08:08:51 PM PDT 24 |
| Finished | Jun 29 08:09:43 PM PDT 24 |
| Peak memory | 574224 kb |
| Host | smart-d5203554-c6ce-43be-881e-983ef158d767 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2710238653 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.xbar_access_same_device. 2710238653 |
| Directory | /workspace/1.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/1.xbar_access_same_device_slow_rsp.2954529366 |
| Short name | T1415 |
| Test name | |
| Test status | |
| Simulation time | 49562922179 ps |
| CPU time | 834.15 seconds |
| Started | Jun 29 08:08:51 PM PDT 24 |
| Finished | Jun 29 08:22:46 PM PDT 24 |
| Peak memory | 575448 kb |
| Host | smart-900b9504-6c6e-4638-9c30-192130bb4e43 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2954529366 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.xbar_access_same_d evice_slow_rsp.2954529366 |
| Directory | /workspace/1.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/1.xbar_error_and_unmapped_addr.1269466505 |
| Short name | T1892 |
| Test name | |
| Test status | |
| Simulation time | 288685311 ps |
| CPU time | 35.5 seconds |
| Started | Jun 29 08:08:59 PM PDT 24 |
| Finished | Jun 29 08:09:34 PM PDT 24 |
| Peak memory | 574276 kb |
| Host | smart-86adfbdb-94bb-4a83-b6e5-bfdeda20ad54 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1269466505 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.xbar_error_and_unmapped_addr .1269466505 |
| Directory | /workspace/1.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/1.xbar_error_random.1051831613 |
| Short name | T1841 |
| Test name | |
| Test status | |
| Simulation time | 481874176 ps |
| CPU time | 49.21 seconds |
| Started | Jun 29 08:09:00 PM PDT 24 |
| Finished | Jun 29 08:09:49 PM PDT 24 |
| Peak memory | 574500 kb |
| Host | smart-caeb6b7a-d21b-453e-b302-e5b018dd73d8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1051831613 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.xbar_error_random.1051831613 |
| Directory | /workspace/1.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/1.xbar_random.1258996467 |
| Short name | T1866 |
| Test name | |
| Test status | |
| Simulation time | 1709128183 ps |
| CPU time | 70.36 seconds |
| Started | Jun 29 08:08:37 PM PDT 24 |
| Finished | Jun 29 08:09:47 PM PDT 24 |
| Peak memory | 574232 kb |
| Host | smart-2aace38a-9b45-4a19-8307-0123dc384ff0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1258996467 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.xbar_random.1258996467 |
| Directory | /workspace/1.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/1.xbar_random_large_delays.4141211428 |
| Short name | T2564 |
| Test name | |
| Test status | |
| Simulation time | 105868338308 ps |
| CPU time | 1149.76 seconds |
| Started | Jun 29 08:08:41 PM PDT 24 |
| Finished | Jun 29 08:27:51 PM PDT 24 |
| Peak memory | 574312 kb |
| Host | smart-4db6407f-60e9-48e1-9f93-7e8c0116a6bd |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4141211428 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.xbar_random_large_delays.4141211428 |
| Directory | /workspace/1.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/1.xbar_random_slow_rsp.2489345456 |
| Short name | T2187 |
| Test name | |
| Test status | |
| Simulation time | 62692505645 ps |
| CPU time | 1088.28 seconds |
| Started | Jun 29 08:08:42 PM PDT 24 |
| Finished | Jun 29 08:26:51 PM PDT 24 |
| Peak memory | 574364 kb |
| Host | smart-5ab636c5-8c60-435e-8e40-e72414528617 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2489345456 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.xbar_random_slow_rsp.2489345456 |
| Directory | /workspace/1.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/1.xbar_random_zero_delays.3113990409 |
| Short name | T1720 |
| Test name | |
| Test status | |
| Simulation time | 218987600 ps |
| CPU time | 22.84 seconds |
| Started | Jun 29 08:08:54 PM PDT 24 |
| Finished | Jun 29 08:09:17 PM PDT 24 |
| Peak memory | 574276 kb |
| Host | smart-e0440bae-2b83-4280-8c2d-8914c5b7dcee |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3113990409 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.xbar_random_zero_dela ys.3113990409 |
| Directory | /workspace/1.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/1.xbar_same_source.3684314758 |
| Short name | T454 |
| Test name | |
| Test status | |
| Simulation time | 379548212 ps |
| CPU time | 33.84 seconds |
| Started | Jun 29 08:08:48 PM PDT 24 |
| Finished | Jun 29 08:09:22 PM PDT 24 |
| Peak memory | 575284 kb |
| Host | smart-c22cca56-5448-4d0c-9dab-7beb0197bb36 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3684314758 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.xbar_same_source.3684314758 |
| Directory | /workspace/1.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/1.xbar_smoke.1088529539 |
| Short name | T2839 |
| Test name | |
| Test status | |
| Simulation time | 41465481 ps |
| CPU time | 7.1 seconds |
| Started | Jun 29 08:08:36 PM PDT 24 |
| Finished | Jun 29 08:08:43 PM PDT 24 |
| Peak memory | 574268 kb |
| Host | smart-d61eb49e-a8be-4be7-9642-0808383864d5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1088529539 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.xbar_smoke.1088529539 |
| Directory | /workspace/1.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/1.xbar_smoke_large_delays.523612885 |
| Short name | T2636 |
| Test name | |
| Test status | |
| Simulation time | 8385956365 ps |
| CPU time | 89.87 seconds |
| Started | Jun 29 08:08:35 PM PDT 24 |
| Finished | Jun 29 08:10:05 PM PDT 24 |
| Peak memory | 566080 kb |
| Host | smart-48118cac-cf77-4294-a620-fb8a5a136bb8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=523612885 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.xbar_smoke_large_delays.523612885 |
| Directory | /workspace/1.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/1.xbar_smoke_slow_rsp.2838878841 |
| Short name | T1790 |
| Test name | |
| Test status | |
| Simulation time | 3429347033 ps |
| CPU time | 66.69 seconds |
| Started | Jun 29 08:08:41 PM PDT 24 |
| Finished | Jun 29 08:09:48 PM PDT 24 |
| Peak memory | 566076 kb |
| Host | smart-a890bddb-e95d-4ac9-ae50-f88a22f197e8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2838878841 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.xbar_smoke_slow_rsp.2838878841 |
| Directory | /workspace/1.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/1.xbar_smoke_zero_delays.905156742 |
| Short name | T2284 |
| Test name | |
| Test status | |
| Simulation time | 51768354 ps |
| CPU time | 6.91 seconds |
| Started | Jun 29 08:08:37 PM PDT 24 |
| Finished | Jun 29 08:08:44 PM PDT 24 |
| Peak memory | 574244 kb |
| Host | smart-80cf10c8-9501-45e4-a42e-a23b904a83d7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=905156742 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.xbar_smoke_zero_delays. 905156742 |
| Directory | /workspace/1.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/1.xbar_stress_all.2273038600 |
| Short name | T496 |
| Test name | |
| Test status | |
| Simulation time | 6251093822 ps |
| CPU time | 285.49 seconds |
| Started | Jun 29 08:09:05 PM PDT 24 |
| Finished | Jun 29 08:13:51 PM PDT 24 |
| Peak memory | 575484 kb |
| Host | smart-89ceff38-0d89-40a0-9558-60e64635f61b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2273038600 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.xbar_stress_all.2273038600 |
| Directory | /workspace/1.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/1.xbar_stress_all_with_error.2211081157 |
| Short name | T1964 |
| Test name | |
| Test status | |
| Simulation time | 3861741842 ps |
| CPU time | 313.02 seconds |
| Started | Jun 29 08:09:06 PM PDT 24 |
| Finished | Jun 29 08:14:19 PM PDT 24 |
| Peak memory | 574468 kb |
| Host | smart-d80c5004-751b-4f41-a760-d8e025768ee8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2211081157 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.xbar_stress_all_with_error.2211081157 |
| Directory | /workspace/1.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/1.xbar_stress_all_with_rand_reset.259923763 |
| Short name | T1937 |
| Test name | |
| Test status | |
| Simulation time | 57570426 ps |
| CPU time | 23.21 seconds |
| Started | Jun 29 08:09:05 PM PDT 24 |
| Finished | Jun 29 08:09:28 PM PDT 24 |
| Peak memory | 575464 kb |
| Host | smart-2590587b-b619-41da-8cfd-f9001db4fbaa |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=259923763 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_res et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.xbar_stress_all_w ith_rand_reset.259923763 |
| Directory | /workspace/1.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/1.xbar_stress_all_with_reset_error.400070637 |
| Short name | T2877 |
| Test name | |
| Test status | |
| Simulation time | 421450905 ps |
| CPU time | 155.1 seconds |
| Started | Jun 29 08:09:08 PM PDT 24 |
| Finished | Jun 29 08:11:44 PM PDT 24 |
| Peak memory | 574652 kb |
| Host | smart-0703f15e-2964-4a5a-a84a-681c694b22b9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=400070637 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.xbar_stress_all_ with_reset_error.400070637 |
| Directory | /workspace/1.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/1.xbar_unmapped_addr.2582852432 |
| Short name | T2613 |
| Test name | |
| Test status | |
| Simulation time | 300019300 ps |
| CPU time | 18.04 seconds |
| Started | Jun 29 08:09:01 PM PDT 24 |
| Finished | Jun 29 08:09:20 PM PDT 24 |
| Peak memory | 575332 kb |
| Host | smart-c1f0244f-05a0-4fbf-8074-d998883d4ee3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2582852432 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.xbar_unmapped_addr.2582852432 |
| Directory | /workspace/1.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/10.chip_csr_rw.2422688999 |
| Short name | T1971 |
| Test name | |
| Test status | |
| Simulation time | 3996900420 ps |
| CPU time | 317.93 seconds |
| Started | Jun 29 08:14:38 PM PDT 24 |
| Finished | Jun 29 08:19:56 PM PDT 24 |
| Peak memory | 596220 kb |
| Host | smart-68b9f041-5a34-4557-934c-5057b7aacf35 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2422688999 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.chip_csr_rw.2422688999 |
| Directory | /workspace/10.chip_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/10.chip_same_csr_outstanding.675306057 |
| Short name | T1492 |
| Test name | |
| Test status | |
| Simulation time | 15426795557 ps |
| CPU time | 1783.47 seconds |
| Started | Jun 29 08:14:12 PM PDT 24 |
| Finished | Jun 29 08:43:56 PM PDT 24 |
| Peak memory | 591952 kb |
| Host | smart-be7f3280-24be-4941-a20d-1027f210481a |
| User | root |
| Command | /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +run_same_csr_outstanding +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=675306057 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c m_log /dev/null -cm_name 10.chip_same_csr_outstanding.675306057 |
| Directory | /workspace/10.chip_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/10.chip_tl_errors.1895386165 |
| Short name | T2690 |
| Test name | |
| Test status | |
| Simulation time | 5404196410 ps |
| CPU time | 530.51 seconds |
| Started | Jun 29 08:14:13 PM PDT 24 |
| Finished | Jun 29 08:23:04 PM PDT 24 |
| Peak memory | 597428 kb |
| Host | smart-8e55d4b2-2c4d-471d-9f9b-1a9c3a379e70 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1895386165 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.chip_tl_errors.1895386165 |
| Directory | /workspace/10.chip_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/10.xbar_access_same_device.2530175853 |
| Short name | T2719 |
| Test name | |
| Test status | |
| Simulation time | 682804974 ps |
| CPU time | 58.98 seconds |
| Started | Jun 29 08:14:29 PM PDT 24 |
| Finished | Jun 29 08:15:28 PM PDT 24 |
| Peak memory | 575296 kb |
| Host | smart-22331439-5982-420b-8e70-5d44f059ab0c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2530175853 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.xbar_access_same_device .2530175853 |
| Directory | /workspace/10.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/10.xbar_access_same_device_slow_rsp.3356405376 |
| Short name | T1714 |
| Test name | |
| Test status | |
| Simulation time | 96325177439 ps |
| CPU time | 1675.95 seconds |
| Started | Jun 29 08:14:31 PM PDT 24 |
| Finished | Jun 29 08:42:27 PM PDT 24 |
| Peak memory | 575504 kb |
| Host | smart-7c6ed507-798e-4556-84a9-c50ffa7fd85e |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3356405376 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.xbar_access_same_ device_slow_rsp.3356405376 |
| Directory | /workspace/10.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/10.xbar_error_and_unmapped_addr.1275949295 |
| Short name | T1727 |
| Test name | |
| Test status | |
| Simulation time | 180435656 ps |
| CPU time | 23.79 seconds |
| Started | Jun 29 08:14:31 PM PDT 24 |
| Finished | Jun 29 08:14:55 PM PDT 24 |
| Peak memory | 574264 kb |
| Host | smart-037164c7-6ce2-4f19-97e0-a74727daea09 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1275949295 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.xbar_error_and_unmapped_add r.1275949295 |
| Directory | /workspace/10.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/10.xbar_error_random.2549369632 |
| Short name | T634 |
| Test name | |
| Test status | |
| Simulation time | 610988224 ps |
| CPU time | 43.63 seconds |
| Started | Jun 29 08:14:30 PM PDT 24 |
| Finished | Jun 29 08:15:14 PM PDT 24 |
| Peak memory | 573924 kb |
| Host | smart-d3e9b25d-7400-4913-a08c-8d5a793cdcfa |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2549369632 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.xbar_error_random.2549369632 |
| Directory | /workspace/10.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/10.xbar_random.3862421609 |
| Short name | T2745 |
| Test name | |
| Test status | |
| Simulation time | 1903211448 ps |
| CPU time | 74.95 seconds |
| Started | Jun 29 08:14:21 PM PDT 24 |
| Finished | Jun 29 08:15:37 PM PDT 24 |
| Peak memory | 575312 kb |
| Host | smart-cd3bcf3f-d329-4a04-956e-47de6e545f2b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3862421609 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.xbar_random.3862421609 |
| Directory | /workspace/10.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/10.xbar_random_large_delays.2691565500 |
| Short name | T2349 |
| Test name | |
| Test status | |
| Simulation time | 27681364110 ps |
| CPU time | 318.07 seconds |
| Started | Jun 29 08:14:20 PM PDT 24 |
| Finished | Jun 29 08:19:39 PM PDT 24 |
| Peak memory | 574320 kb |
| Host | smart-bbe1038b-0868-4f44-81ee-2b77bf35d100 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2691565500 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.xbar_random_large_delays.2691565500 |
| Directory | /workspace/10.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/10.xbar_random_slow_rsp.949468601 |
| Short name | T1810 |
| Test name | |
| Test status | |
| Simulation time | 38149393281 ps |
| CPU time | 678.92 seconds |
| Started | Jun 29 08:14:32 PM PDT 24 |
| Finished | Jun 29 08:25:51 PM PDT 24 |
| Peak memory | 575396 kb |
| Host | smart-f77e1c1d-e5ca-415b-8757-2430c6874e03 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=949468601 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.xbar_random_slow_rsp.949468601 |
| Directory | /workspace/10.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/10.xbar_random_zero_delays.3227147151 |
| Short name | T1957 |
| Test name | |
| Test status | |
| Simulation time | 286677270 ps |
| CPU time | 29.47 seconds |
| Started | Jun 29 08:14:26 PM PDT 24 |
| Finished | Jun 29 08:14:56 PM PDT 24 |
| Peak memory | 575320 kb |
| Host | smart-4c6e3ddc-9b82-4fde-8a2e-a7b32f30b4dd |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3227147151 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.xbar_random_zero_del ays.3227147151 |
| Directory | /workspace/10.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/10.xbar_same_source.201738605 |
| Short name | T670 |
| Test name | |
| Test status | |
| Simulation time | 314439468 ps |
| CPU time | 13.46 seconds |
| Started | Jun 29 08:14:29 PM PDT 24 |
| Finished | Jun 29 08:14:43 PM PDT 24 |
| Peak memory | 574252 kb |
| Host | smart-f4f2b894-885c-48ff-9112-901be5459a61 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=201738605 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.xbar_same_source.201738605 |
| Directory | /workspace/10.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/10.xbar_smoke.1278750027 |
| Short name | T1370 |
| Test name | |
| Test status | |
| Simulation time | 51773931 ps |
| CPU time | 6.75 seconds |
| Started | Jun 29 08:14:23 PM PDT 24 |
| Finished | Jun 29 08:14:30 PM PDT 24 |
| Peak memory | 574264 kb |
| Host | smart-f5e9af57-9aca-4aae-ad1b-ce047f487b9a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1278750027 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.xbar_smoke.1278750027 |
| Directory | /workspace/10.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/10.xbar_smoke_large_delays.844648887 |
| Short name | T1864 |
| Test name | |
| Test status | |
| Simulation time | 7602248185 ps |
| CPU time | 79.86 seconds |
| Started | Jun 29 08:14:22 PM PDT 24 |
| Finished | Jun 29 08:15:42 PM PDT 24 |
| Peak memory | 574324 kb |
| Host | smart-7e4f7bfe-3b65-4b77-a906-3c4edcace724 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=844648887 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.xbar_smoke_large_delays.844648887 |
| Directory | /workspace/10.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/10.xbar_smoke_slow_rsp.941714945 |
| Short name | T2094 |
| Test name | |
| Test status | |
| Simulation time | 4173274832 ps |
| CPU time | 76.2 seconds |
| Started | Jun 29 08:14:21 PM PDT 24 |
| Finished | Jun 29 08:15:38 PM PDT 24 |
| Peak memory | 574316 kb |
| Host | smart-3487ce3b-2195-4039-9960-6ed992aa5136 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=941714945 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.xbar_smoke_slow_rsp.941714945 |
| Directory | /workspace/10.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/10.xbar_smoke_zero_delays.1416832364 |
| Short name | T1654 |
| Test name | |
| Test status | |
| Simulation time | 54685956 ps |
| CPU time | 7.77 seconds |
| Started | Jun 29 08:14:21 PM PDT 24 |
| Finished | Jun 29 08:14:29 PM PDT 24 |
| Peak memory | 574264 kb |
| Host | smart-d3a39193-0d68-4ff7-9f73-7a2f518f09e4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1416832364 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.xbar_smoke_zero_delay s.1416832364 |
| Directory | /workspace/10.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/10.xbar_stress_all.4257881827 |
| Short name | T2490 |
| Test name | |
| Test status | |
| Simulation time | 4328344226 ps |
| CPU time | 213.77 seconds |
| Started | Jun 29 08:14:31 PM PDT 24 |
| Finished | Jun 29 08:18:05 PM PDT 24 |
| Peak memory | 574472 kb |
| Host | smart-278f81de-463b-4f08-aa4c-3f3ef075aa1b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4257881827 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.xbar_stress_all.4257881827 |
| Directory | /workspace/10.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/10.xbar_stress_all_with_error.3023391416 |
| Short name | T1771 |
| Test name | |
| Test status | |
| Simulation time | 967320787 ps |
| CPU time | 36.08 seconds |
| Started | Jun 29 08:14:33 PM PDT 24 |
| Finished | Jun 29 08:15:10 PM PDT 24 |
| Peak memory | 574256 kb |
| Host | smart-6ae014af-eb0a-4c5f-92d6-2fa60d3d63d0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3023391416 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.xbar_stress_all_with_error.3023391416 |
| Directory | /workspace/10.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/10.xbar_stress_all_with_rand_reset.244976793 |
| Short name | T2697 |
| Test name | |
| Test status | |
| Simulation time | 169884250 ps |
| CPU time | 44.58 seconds |
| Started | Jun 29 08:14:30 PM PDT 24 |
| Finished | Jun 29 08:15:15 PM PDT 24 |
| Peak memory | 577472 kb |
| Host | smart-26716468-f50c-4cdf-8935-2ab5b9b18966 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=244976793 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_res et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.xbar_stress_all_ with_rand_reset.244976793 |
| Directory | /workspace/10.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/10.xbar_stress_all_with_reset_error.2004549395 |
| Short name | T1368 |
| Test name | |
| Test status | |
| Simulation time | 74897696 ps |
| CPU time | 23.31 seconds |
| Started | Jun 29 08:14:32 PM PDT 24 |
| Finished | Jun 29 08:14:56 PM PDT 24 |
| Peak memory | 574388 kb |
| Host | smart-5c1b5e7d-15bd-4e52-bbb2-044027a7a652 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2004549395 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.xbar_stress_al l_with_reset_error.2004549395 |
| Directory | /workspace/10.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/10.xbar_unmapped_addr.2075075382 |
| Short name | T1921 |
| Test name | |
| Test status | |
| Simulation time | 737525923 ps |
| CPU time | 36.16 seconds |
| Started | Jun 29 08:14:29 PM PDT 24 |
| Finished | Jun 29 08:15:06 PM PDT 24 |
| Peak memory | 575348 kb |
| Host | smart-ff0351ed-02ab-4242-bf56-29c98e2c7bc5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2075075382 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.xbar_unmapped_addr.2075075382 |
| Directory | /workspace/10.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/11.chip_csr_rw.2942830556 |
| Short name | T1987 |
| Test name | |
| Test status | |
| Simulation time | 4225320394 ps |
| CPU time | 334.32 seconds |
| Started | Jun 29 08:14:58 PM PDT 24 |
| Finished | Jun 29 08:20:32 PM PDT 24 |
| Peak memory | 595896 kb |
| Host | smart-23d6cdcc-bd67-4436-b8a5-7d56c856fd59 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2942830556 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.chip_csr_rw.2942830556 |
| Directory | /workspace/11.chip_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/11.xbar_access_same_device.1369061629 |
| Short name | T1535 |
| Test name | |
| Test status | |
| Simulation time | 244706647 ps |
| CPU time | 32.79 seconds |
| Started | Jun 29 08:14:49 PM PDT 24 |
| Finished | Jun 29 08:15:22 PM PDT 24 |
| Peak memory | 575292 kb |
| Host | smart-a0d7a955-d77c-454e-8651-d9cec43ccfc1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1369061629 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.xbar_access_same_device .1369061629 |
| Directory | /workspace/11.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/11.xbar_access_same_device_slow_rsp.476490705 |
| Short name | T1794 |
| Test name | |
| Test status | |
| Simulation time | 115307893467 ps |
| CPU time | 2120.87 seconds |
| Started | Jun 29 08:14:55 PM PDT 24 |
| Finished | Jun 29 08:50:17 PM PDT 24 |
| Peak memory | 575488 kb |
| Host | smart-c005b536-c03d-4df1-9f15-ad706b4c62d1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=476490705 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.xbar_access_same_d evice_slow_rsp.476490705 |
| Directory | /workspace/11.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/11.xbar_error_and_unmapped_addr.2640677813 |
| Short name | T1828 |
| Test name | |
| Test status | |
| Simulation time | 243581174 ps |
| CPU time | 14.95 seconds |
| Started | Jun 29 08:14:54 PM PDT 24 |
| Finished | Jun 29 08:15:10 PM PDT 24 |
| Peak memory | 574524 kb |
| Host | smart-bdd22892-a377-4018-bad7-acede9bdc9e8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2640677813 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.xbar_error_and_unmapped_add r.2640677813 |
| Directory | /workspace/11.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/11.xbar_error_random.1582844803 |
| Short name | T1589 |
| Test name | |
| Test status | |
| Simulation time | 563342823 ps |
| CPU time | 54.2 seconds |
| Started | Jun 29 08:14:57 PM PDT 24 |
| Finished | Jun 29 08:15:51 PM PDT 24 |
| Peak memory | 574400 kb |
| Host | smart-31afbbfe-357e-4008-8bdf-6964adc02700 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1582844803 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.xbar_error_random.1582844803 |
| Directory | /workspace/11.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/11.xbar_random.1587504156 |
| Short name | T1942 |
| Test name | |
| Test status | |
| Simulation time | 687067199 ps |
| CPU time | 28.8 seconds |
| Started | Jun 29 08:14:37 PM PDT 24 |
| Finished | Jun 29 08:15:06 PM PDT 24 |
| Peak memory | 574236 kb |
| Host | smart-489a525f-70e2-4623-940d-5c96909944f7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1587504156 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.xbar_random.1587504156 |
| Directory | /workspace/11.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/11.xbar_random_large_delays.2801981656 |
| Short name | T1705 |
| Test name | |
| Test status | |
| Simulation time | 42913916981 ps |
| CPU time | 479.87 seconds |
| Started | Jun 29 08:14:47 PM PDT 24 |
| Finished | Jun 29 08:22:47 PM PDT 24 |
| Peak memory | 575380 kb |
| Host | smart-ffb68a87-2d5f-4098-8c0a-b2af8a4eea25 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2801981656 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.xbar_random_large_delays.2801981656 |
| Directory | /workspace/11.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/11.xbar_random_slow_rsp.2974643672 |
| Short name | T2238 |
| Test name | |
| Test status | |
| Simulation time | 46479822359 ps |
| CPU time | 776.66 seconds |
| Started | Jun 29 08:14:49 PM PDT 24 |
| Finished | Jun 29 08:27:46 PM PDT 24 |
| Peak memory | 574332 kb |
| Host | smart-c402fcfa-704e-4551-bbc8-dab33894e706 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2974643672 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.xbar_random_slow_rsp.2974643672 |
| Directory | /workspace/11.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/11.xbar_random_zero_delays.3434116335 |
| Short name | T1313 |
| Test name | |
| Test status | |
| Simulation time | 110801824 ps |
| CPU time | 13.27 seconds |
| Started | Jun 29 08:14:46 PM PDT 24 |
| Finished | Jun 29 08:15:00 PM PDT 24 |
| Peak memory | 574240 kb |
| Host | smart-ea991a0d-56b1-43f8-a0e7-952db1363e08 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3434116335 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.xbar_random_zero_del ays.3434116335 |
| Directory | /workspace/11.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/11.xbar_same_source.2619583640 |
| Short name | T1455 |
| Test name | |
| Test status | |
| Simulation time | 1330191791 ps |
| CPU time | 45.09 seconds |
| Started | Jun 29 08:14:57 PM PDT 24 |
| Finished | Jun 29 08:15:42 PM PDT 24 |
| Peak memory | 575268 kb |
| Host | smart-ddd05d59-cc7d-4dc4-94b4-86f942a73766 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2619583640 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.xbar_same_source.2619583640 |
| Directory | /workspace/11.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/11.xbar_smoke.4235451667 |
| Short name | T2207 |
| Test name | |
| Test status | |
| Simulation time | 250328588 ps |
| CPU time | 10.69 seconds |
| Started | Jun 29 08:14:39 PM PDT 24 |
| Finished | Jun 29 08:14:50 PM PDT 24 |
| Peak memory | 565992 kb |
| Host | smart-91727c28-d973-480e-a7c3-f550be6abdb2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4235451667 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.xbar_smoke.4235451667 |
| Directory | /workspace/11.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/11.xbar_smoke_large_delays.2428904002 |
| Short name | T1848 |
| Test name | |
| Test status | |
| Simulation time | 8193556222 ps |
| CPU time | 86.6 seconds |
| Started | Jun 29 08:14:37 PM PDT 24 |
| Finished | Jun 29 08:16:04 PM PDT 24 |
| Peak memory | 566088 kb |
| Host | smart-7b83ec63-11dd-4135-9dc1-4a2b6f69a7e6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2428904002 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.xbar_smoke_large_delays.2428904002 |
| Directory | /workspace/11.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/11.xbar_smoke_slow_rsp.33171208 |
| Short name | T1858 |
| Test name | |
| Test status | |
| Simulation time | 4491399263 ps |
| CPU time | 78.7 seconds |
| Started | Jun 29 08:14:38 PM PDT 24 |
| Finished | Jun 29 08:15:57 PM PDT 24 |
| Peak memory | 574320 kb |
| Host | smart-d9a4b2c0-e331-497d-a40c-043016685861 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33171208 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.xbar_smoke_slow_rsp.33171208 |
| Directory | /workspace/11.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/11.xbar_smoke_zero_delays.2276405419 |
| Short name | T1695 |
| Test name | |
| Test status | |
| Simulation time | 48818914 ps |
| CPU time | 7.16 seconds |
| Started | Jun 29 08:14:42 PM PDT 24 |
| Finished | Jun 29 08:14:49 PM PDT 24 |
| Peak memory | 566008 kb |
| Host | smart-b6d4a39e-4175-49cb-9108-b735b0a5b765 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2276405419 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.xbar_smoke_zero_delay s.2276405419 |
| Directory | /workspace/11.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/11.xbar_stress_all.1458064778 |
| Short name | T498 |
| Test name | |
| Test status | |
| Simulation time | 11013794431 ps |
| CPU time | 433.42 seconds |
| Started | Jun 29 08:14:55 PM PDT 24 |
| Finished | Jun 29 08:22:09 PM PDT 24 |
| Peak memory | 574456 kb |
| Host | smart-fe4b7c6b-fc29-45ab-8675-562652421d8f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1458064778 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.xbar_stress_all.1458064778 |
| Directory | /workspace/11.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/11.xbar_stress_all_with_error.2316773718 |
| Short name | T1767 |
| Test name | |
| Test status | |
| Simulation time | 2672988203 ps |
| CPU time | 255.61 seconds |
| Started | Jun 29 08:14:56 PM PDT 24 |
| Finished | Jun 29 08:19:12 PM PDT 24 |
| Peak memory | 574732 kb |
| Host | smart-3489d844-9fcb-4ff0-8749-867bea2eafa1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2316773718 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.xbar_stress_all_with_error.2316773718 |
| Directory | /workspace/11.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/11.xbar_stress_all_with_rand_reset.3585858261 |
| Short name | T2265 |
| Test name | |
| Test status | |
| Simulation time | 390836530 ps |
| CPU time | 119.59 seconds |
| Started | Jun 29 08:14:56 PM PDT 24 |
| Finished | Jun 29 08:16:55 PM PDT 24 |
| Peak memory | 575448 kb |
| Host | smart-38eaf051-9d21-4ad5-a19d-a6c2dd68e4e2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3585858261 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.xbar_stress_all _with_rand_reset.3585858261 |
| Directory | /workspace/11.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/11.xbar_stress_all_with_reset_error.575253283 |
| Short name | T1511 |
| Test name | |
| Test status | |
| Simulation time | 136821473 ps |
| CPU time | 46.42 seconds |
| Started | Jun 29 08:14:55 PM PDT 24 |
| Finished | Jun 29 08:15:42 PM PDT 24 |
| Peak memory | 575452 kb |
| Host | smart-fc9fdba2-8b36-4cdb-b98b-c28617c7ab95 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=575253283 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.xbar_stress_all _with_reset_error.575253283 |
| Directory | /workspace/11.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/11.xbar_unmapped_addr.879595949 |
| Short name | T2355 |
| Test name | |
| Test status | |
| Simulation time | 113566365 ps |
| CPU time | 17.21 seconds |
| Started | Jun 29 08:14:57 PM PDT 24 |
| Finished | Jun 29 08:15:14 PM PDT 24 |
| Peak memory | 574276 kb |
| Host | smart-30b73c13-1352-4247-b55b-48b2a9e854c3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=879595949 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.xbar_unmapped_addr.879595949 |
| Directory | /workspace/11.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/12.chip_csr_rw.3101132687 |
| Short name | T1777 |
| Test name | |
| Test status | |
| Simulation time | 6057982152 ps |
| CPU time | 686.82 seconds |
| Started | Jun 29 08:15:14 PM PDT 24 |
| Finished | Jun 29 08:26:41 PM PDT 24 |
| Peak memory | 597340 kb |
| Host | smart-28990729-911e-4f9d-9877-68d555a02aa9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3101132687 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.chip_csr_rw.3101132687 |
| Directory | /workspace/12.chip_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/12.chip_same_csr_outstanding.2191162895 |
| Short name | T2651 |
| Test name | |
| Test status | |
| Simulation time | 29667449159 ps |
| CPU time | 3577.02 seconds |
| Started | Jun 29 08:14:55 PM PDT 24 |
| Finished | Jun 29 09:14:33 PM PDT 24 |
| Peak memory | 591976 kb |
| Host | smart-997f252f-b671-43a9-8743-9c284ad852ca |
| User | root |
| Command | /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +run_same_csr_outstanding +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2191162895 -assert nopostproc +UVM_TE STNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb - cm_log /dev/null -cm_name 12.chip_same_csr_outstanding.2191162895 |
| Directory | /workspace/12.chip_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/12.chip_tl_errors.4212867099 |
| Short name | T662 |
| Test name | |
| Test status | |
| Simulation time | 3228804444 ps |
| CPU time | 160.91 seconds |
| Started | Jun 29 08:14:54 PM PDT 24 |
| Finished | Jun 29 08:17:36 PM PDT 24 |
| Peak memory | 597496 kb |
| Host | smart-7fb51b19-106c-4257-ae1d-f757eeb40d2f |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4212867099 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.chip_tl_errors.4212867099 |
| Directory | /workspace/12.chip_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/12.xbar_access_same_device.1365439631 |
| Short name | T1444 |
| Test name | |
| Test status | |
| Simulation time | 438366731 ps |
| CPU time | 40.38 seconds |
| Started | Jun 29 08:15:03 PM PDT 24 |
| Finished | Jun 29 08:15:44 PM PDT 24 |
| Peak memory | 575312 kb |
| Host | smart-cc9446fb-8cf5-4e03-975f-68afa72a8e8b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1365439631 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.xbar_access_same_device .1365439631 |
| Directory | /workspace/12.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/12.xbar_access_same_device_slow_rsp.2316160492 |
| Short name | T2510 |
| Test name | |
| Test status | |
| Simulation time | 37066564769 ps |
| CPU time | 668.74 seconds |
| Started | Jun 29 08:15:14 PM PDT 24 |
| Finished | Jun 29 08:26:24 PM PDT 24 |
| Peak memory | 575432 kb |
| Host | smart-0e09bec8-936c-4ef7-a789-3625bfc7952f |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2316160492 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.xbar_access_same_ device_slow_rsp.2316160492 |
| Directory | /workspace/12.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/12.xbar_error_and_unmapped_addr.2071862784 |
| Short name | T2569 |
| Test name | |
| Test status | |
| Simulation time | 319839708 ps |
| CPU time | 18.77 seconds |
| Started | Jun 29 08:15:13 PM PDT 24 |
| Finished | Jun 29 08:15:33 PM PDT 24 |
| Peak memory | 574264 kb |
| Host | smart-54dbc1b7-c83d-4965-9cb7-f7c519d9bbc7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2071862784 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.xbar_error_and_unmapped_add r.2071862784 |
| Directory | /workspace/12.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/12.xbar_error_random.773193867 |
| Short name | T1424 |
| Test name | |
| Test status | |
| Simulation time | 572298386 ps |
| CPU time | 48.75 seconds |
| Started | Jun 29 08:15:15 PM PDT 24 |
| Finished | Jun 29 08:16:04 PM PDT 24 |
| Peak memory | 574264 kb |
| Host | smart-ad17458c-eb31-4000-bab0-f55bf84bb78b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=773193867 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.xbar_error_random.773193867 |
| Directory | /workspace/12.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/12.xbar_random.3657110988 |
| Short name | T2597 |
| Test name | |
| Test status | |
| Simulation time | 609868779 ps |
| CPU time | 56.19 seconds |
| Started | Jun 29 08:15:11 PM PDT 24 |
| Finished | Jun 29 08:16:08 PM PDT 24 |
| Peak memory | 574280 kb |
| Host | smart-a9cc3135-e351-4762-abba-ee6c21d932be |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3657110988 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.xbar_random.3657110988 |
| Directory | /workspace/12.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/12.xbar_random_large_delays.3879809151 |
| Short name | T1635 |
| Test name | |
| Test status | |
| Simulation time | 104725013179 ps |
| CPU time | 1095.29 seconds |
| Started | Jun 29 08:15:08 PM PDT 24 |
| Finished | Jun 29 08:33:24 PM PDT 24 |
| Peak memory | 575400 kb |
| Host | smart-54255133-9826-46d8-a9da-a4b2fa028cb7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3879809151 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.xbar_random_large_delays.3879809151 |
| Directory | /workspace/12.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/12.xbar_random_slow_rsp.630076470 |
| Short name | T2030 |
| Test name | |
| Test status | |
| Simulation time | 27628342147 ps |
| CPU time | 504.03 seconds |
| Started | Jun 29 08:15:02 PM PDT 24 |
| Finished | Jun 29 08:23:26 PM PDT 24 |
| Peak memory | 575376 kb |
| Host | smart-ccc94218-32b5-4a55-aa76-4243ac449241 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=630076470 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.xbar_random_slow_rsp.630076470 |
| Directory | /workspace/12.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/12.xbar_random_zero_delays.4215339807 |
| Short name | T1707 |
| Test name | |
| Test status | |
| Simulation time | 55353799 ps |
| CPU time | 9 seconds |
| Started | Jun 29 08:15:02 PM PDT 24 |
| Finished | Jun 29 08:15:11 PM PDT 24 |
| Peak memory | 574176 kb |
| Host | smart-079c1194-b9c5-499f-9071-52855bb22a9a |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4215339807 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.xbar_random_zero_del ays.4215339807 |
| Directory | /workspace/12.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/12.xbar_same_source.3157831100 |
| Short name | T583 |
| Test name | |
| Test status | |
| Simulation time | 164880993 ps |
| CPU time | 15.74 seconds |
| Started | Jun 29 08:15:14 PM PDT 24 |
| Finished | Jun 29 08:15:30 PM PDT 24 |
| Peak memory | 574236 kb |
| Host | smart-8411d841-70c2-48f4-ab85-772612d1ef0e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3157831100 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.xbar_same_source.3157831100 |
| Directory | /workspace/12.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/12.xbar_smoke.3547258230 |
| Short name | T2446 |
| Test name | |
| Test status | |
| Simulation time | 181721453 ps |
| CPU time | 9.59 seconds |
| Started | Jun 29 08:15:04 PM PDT 24 |
| Finished | Jun 29 08:15:13 PM PDT 24 |
| Peak memory | 566024 kb |
| Host | smart-26e19ba7-239d-4eb8-8e85-0a89f66c7d42 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3547258230 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.xbar_smoke.3547258230 |
| Directory | /workspace/12.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/12.xbar_smoke_large_delays.722971333 |
| Short name | T1362 |
| Test name | |
| Test status | |
| Simulation time | 9706594228 ps |
| CPU time | 110.64 seconds |
| Started | Jun 29 08:15:04 PM PDT 24 |
| Finished | Jun 29 08:16:55 PM PDT 24 |
| Peak memory | 566080 kb |
| Host | smart-7fc338a1-e810-4b1c-b8a4-f57f1f979f6b |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=722971333 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.xbar_smoke_large_delays.722971333 |
| Directory | /workspace/12.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/12.xbar_smoke_slow_rsp.1509214728 |
| Short name | T1300 |
| Test name | |
| Test status | |
| Simulation time | 5677264780 ps |
| CPU time | 106.58 seconds |
| Started | Jun 29 08:15:03 PM PDT 24 |
| Finished | Jun 29 08:16:50 PM PDT 24 |
| Peak memory | 574336 kb |
| Host | smart-cdee8135-1e23-447d-b0c1-9331a99cd049 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1509214728 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.xbar_smoke_slow_rsp.1509214728 |
| Directory | /workspace/12.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/12.xbar_smoke_zero_delays.35209423 |
| Short name | T2629 |
| Test name | |
| Test status | |
| Simulation time | 51110967 ps |
| CPU time | 6.9 seconds |
| Started | Jun 29 08:15:02 PM PDT 24 |
| Finished | Jun 29 08:15:10 PM PDT 24 |
| Peak memory | 574252 kb |
| Host | smart-9b47283f-40f2-4193-80c2-79dbc2bc0836 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35209423 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.xbar_smoke_zero_delays.35209423 |
| Directory | /workspace/12.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/12.xbar_stress_all.1616194233 |
| Short name | T1716 |
| Test name | |
| Test status | |
| Simulation time | 1914190393 ps |
| CPU time | 177.02 seconds |
| Started | Jun 29 08:15:15 PM PDT 24 |
| Finished | Jun 29 08:18:13 PM PDT 24 |
| Peak memory | 575464 kb |
| Host | smart-7cfae673-f0f5-4254-ab6f-2ac6e7408430 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1616194233 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.xbar_stress_all.1616194233 |
| Directory | /workspace/12.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/12.xbar_stress_all_with_error.3346317382 |
| Short name | T2288 |
| Test name | |
| Test status | |
| Simulation time | 2481429879 ps |
| CPU time | 88.25 seconds |
| Started | Jun 29 08:15:13 PM PDT 24 |
| Finished | Jun 29 08:16:42 PM PDT 24 |
| Peak memory | 574532 kb |
| Host | smart-649b1cda-a561-4831-841b-660e2d5d1220 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3346317382 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.xbar_stress_all_with_error.3346317382 |
| Directory | /workspace/12.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/12.xbar_stress_all_with_rand_reset.1372385587 |
| Short name | T1656 |
| Test name | |
| Test status | |
| Simulation time | 15499922461 ps |
| CPU time | 887.85 seconds |
| Started | Jun 29 08:15:15 PM PDT 24 |
| Finished | Jun 29 08:30:03 PM PDT 24 |
| Peak memory | 575508 kb |
| Host | smart-28ae943c-ae46-4ee5-ac7a-72e84cafa0c4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1372385587 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.xbar_stress_all _with_rand_reset.1372385587 |
| Directory | /workspace/12.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/12.xbar_stress_all_with_reset_error.1501379467 |
| Short name | T1476 |
| Test name | |
| Test status | |
| Simulation time | 44174356 ps |
| CPU time | 18.78 seconds |
| Started | Jun 29 08:15:14 PM PDT 24 |
| Finished | Jun 29 08:15:33 PM PDT 24 |
| Peak memory | 575432 kb |
| Host | smart-01d0ac15-a847-4736-ac69-34dc7598a9eb |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1501379467 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.xbar_stress_al l_with_reset_error.1501379467 |
| Directory | /workspace/12.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/12.xbar_unmapped_addr.1241838828 |
| Short name | T2222 |
| Test name | |
| Test status | |
| Simulation time | 1086412436 ps |
| CPU time | 47.35 seconds |
| Started | Jun 29 08:15:14 PM PDT 24 |
| Finished | Jun 29 08:16:02 PM PDT 24 |
| Peak memory | 574284 kb |
| Host | smart-edf52399-c96a-499c-8765-665bbe4b232f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1241838828 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.xbar_unmapped_addr.1241838828 |
| Directory | /workspace/12.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/13.chip_csr_rw.370620982 |
| Short name | T2364 |
| Test name | |
| Test status | |
| Simulation time | 4836968944 ps |
| CPU time | 397.9 seconds |
| Started | Jun 29 08:15:31 PM PDT 24 |
| Finished | Jun 29 08:22:09 PM PDT 24 |
| Peak memory | 595732 kb |
| Host | smart-99eac873-3be9-4954-8d61-a22fdb49f96b |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=370620982 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.chip_csr_rw.370620982 |
| Directory | /workspace/13.chip_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/13.chip_same_csr_outstanding.2572274061 |
| Short name | T380 |
| Test name | |
| Test status | |
| Simulation time | 16626678257 ps |
| CPU time | 1961 seconds |
| Started | Jun 29 08:15:15 PM PDT 24 |
| Finished | Jun 29 08:47:57 PM PDT 24 |
| Peak memory | 591852 kb |
| Host | smart-61850f2e-a606-4d98-9ec1-1b6d75bb1e29 |
| User | root |
| Command | /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +run_same_csr_outstanding +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2572274061 -assert nopostproc +UVM_TE STNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb - cm_log /dev/null -cm_name 13.chip_same_csr_outstanding.2572274061 |
| Directory | /workspace/13.chip_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/13.chip_tl_errors.3201433729 |
| Short name | T544 |
| Test name | |
| Test status | |
| Simulation time | 3253074560 ps |
| CPU time | 186.69 seconds |
| Started | Jun 29 08:15:18 PM PDT 24 |
| Finished | Jun 29 08:18:25 PM PDT 24 |
| Peak memory | 597512 kb |
| Host | smart-cf2006b7-aae7-4325-8c33-575ed9bf0487 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3201433729 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.chip_tl_errors.3201433729 |
| Directory | /workspace/13.chip_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/13.xbar_access_same_device.418335258 |
| Short name | T2140 |
| Test name | |
| Test status | |
| Simulation time | 2901891520 ps |
| CPU time | 148.48 seconds |
| Started | Jun 29 08:15:22 PM PDT 24 |
| Finished | Jun 29 08:17:51 PM PDT 24 |
| Peak memory | 574404 kb |
| Host | smart-448c76a4-ed27-4b10-ae9e-177fba06211b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=418335258 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.xbar_access_same_device. 418335258 |
| Directory | /workspace/13.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/13.xbar_access_same_device_slow_rsp.3494610008 |
| Short name | T2092 |
| Test name | |
| Test status | |
| Simulation time | 10988673431 ps |
| CPU time | 204.05 seconds |
| Started | Jun 29 08:15:30 PM PDT 24 |
| Finished | Jun 29 08:18:54 PM PDT 24 |
| Peak memory | 574252 kb |
| Host | smart-6fda2038-4a49-4744-8f38-d37c1273a063 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3494610008 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.xbar_access_same_ device_slow_rsp.3494610008 |
| Directory | /workspace/13.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/13.xbar_error_and_unmapped_addr.2049376073 |
| Short name | T2135 |
| Test name | |
| Test status | |
| Simulation time | 1221445748 ps |
| CPU time | 52.05 seconds |
| Started | Jun 29 08:15:30 PM PDT 24 |
| Finished | Jun 29 08:16:22 PM PDT 24 |
| Peak memory | 574508 kb |
| Host | smart-4c7378ae-9165-45d3-8259-70b28eed6200 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2049376073 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.xbar_error_and_unmapped_add r.2049376073 |
| Directory | /workspace/13.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/13.xbar_error_random.2914359518 |
| Short name | T1915 |
| Test name | |
| Test status | |
| Simulation time | 1470801502 ps |
| CPU time | 53.83 seconds |
| Started | Jun 29 08:15:32 PM PDT 24 |
| Finished | Jun 29 08:16:26 PM PDT 24 |
| Peak memory | 574236 kb |
| Host | smart-b0a13b65-318b-48ba-8955-f5db6711f089 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2914359518 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.xbar_error_random.2914359518 |
| Directory | /workspace/13.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/13.xbar_random.2511864229 |
| Short name | T2263 |
| Test name | |
| Test status | |
| Simulation time | 238581063 ps |
| CPU time | 11.8 seconds |
| Started | Jun 29 08:15:29 PM PDT 24 |
| Finished | Jun 29 08:15:41 PM PDT 24 |
| Peak memory | 574324 kb |
| Host | smart-88156031-7b55-4913-823e-8fe6baf68795 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2511864229 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.xbar_random.2511864229 |
| Directory | /workspace/13.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/13.xbar_random_large_delays.592224607 |
| Short name | T1536 |
| Test name | |
| Test status | |
| Simulation time | 43834248086 ps |
| CPU time | 411.54 seconds |
| Started | Jun 29 08:15:27 PM PDT 24 |
| Finished | Jun 29 08:22:18 PM PDT 24 |
| Peak memory | 574120 kb |
| Host | smart-8d46fd75-6a8d-47eb-b238-ff489a8849ec |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=592224607 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.xbar_random_large_delays.592224607 |
| Directory | /workspace/13.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/13.xbar_random_slow_rsp.2716381983 |
| Short name | T2347 |
| Test name | |
| Test status | |
| Simulation time | 3695049899 ps |
| CPU time | 63.49 seconds |
| Started | Jun 29 08:15:21 PM PDT 24 |
| Finished | Jun 29 08:16:25 PM PDT 24 |
| Peak memory | 574312 kb |
| Host | smart-7f1299b1-14bb-42df-a4ac-c07c978b0f69 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2716381983 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.xbar_random_slow_rsp.2716381983 |
| Directory | /workspace/13.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/13.xbar_same_source.2363004073 |
| Short name | T2054 |
| Test name | |
| Test status | |
| Simulation time | 2343027584 ps |
| CPU time | 78.55 seconds |
| Started | Jun 29 08:15:29 PM PDT 24 |
| Finished | Jun 29 08:16:48 PM PDT 24 |
| Peak memory | 575344 kb |
| Host | smart-0f36f522-c56f-4c6d-a5eb-b3ed82422277 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2363004073 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.xbar_same_source.2363004073 |
| Directory | /workspace/13.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/13.xbar_smoke.1190012148 |
| Short name | T2509 |
| Test name | |
| Test status | |
| Simulation time | 259799152 ps |
| CPU time | 12.04 seconds |
| Started | Jun 29 08:15:23 PM PDT 24 |
| Finished | Jun 29 08:15:35 PM PDT 24 |
| Peak memory | 574256 kb |
| Host | smart-3827d487-d619-4f5a-833e-12949ddb45a1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1190012148 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.xbar_smoke.1190012148 |
| Directory | /workspace/13.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/13.xbar_smoke_large_delays.2526549540 |
| Short name | T652 |
| Test name | |
| Test status | |
| Simulation time | 7404411031 ps |
| CPU time | 78.43 seconds |
| Started | Jun 29 08:15:28 PM PDT 24 |
| Finished | Jun 29 08:16:47 PM PDT 24 |
| Peak memory | 566104 kb |
| Host | smart-4bb32dcc-f89f-4a95-85f4-99076fbede3a |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2526549540 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.xbar_smoke_large_delays.2526549540 |
| Directory | /workspace/13.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/13.xbar_smoke_slow_rsp.3800621536 |
| Short name | T2773 |
| Test name | |
| Test status | |
| Simulation time | 4279516654 ps |
| CPU time | 64.59 seconds |
| Started | Jun 29 08:15:26 PM PDT 24 |
| Finished | Jun 29 08:16:31 PM PDT 24 |
| Peak memory | 573928 kb |
| Host | smart-a1b1d344-8461-4250-aa17-eeee8b0723db |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3800621536 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.xbar_smoke_slow_rsp.3800621536 |
| Directory | /workspace/13.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/13.xbar_smoke_zero_delays.3558922646 |
| Short name | T2534 |
| Test name | |
| Test status | |
| Simulation time | 40359211 ps |
| CPU time | 6.27 seconds |
| Started | Jun 29 08:15:28 PM PDT 24 |
| Finished | Jun 29 08:15:35 PM PDT 24 |
| Peak memory | 574272 kb |
| Host | smart-86853c1e-2d01-42b4-99b7-535c285edf27 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3558922646 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.xbar_smoke_zero_delay s.3558922646 |
| Directory | /workspace/13.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/13.xbar_stress_all.958855165 |
| Short name | T507 |
| Test name | |
| Test status | |
| Simulation time | 2030672897 ps |
| CPU time | 192.81 seconds |
| Started | Jun 29 08:15:30 PM PDT 24 |
| Finished | Jun 29 08:18:43 PM PDT 24 |
| Peak memory | 575452 kb |
| Host | smart-238e6b3c-f9ef-4175-bee5-56b22f27fa95 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=958855165 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.xbar_stress_all.958855165 |
| Directory | /workspace/13.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/13.xbar_stress_all_with_error.2634001166 |
| Short name | T1732 |
| Test name | |
| Test status | |
| Simulation time | 2173145664 ps |
| CPU time | 162.99 seconds |
| Started | Jun 29 08:15:30 PM PDT 24 |
| Finished | Jun 29 08:18:14 PM PDT 24 |
| Peak memory | 574456 kb |
| Host | smart-521d172f-3cbe-40f5-bfaf-dec16dc163e2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2634001166 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.xbar_stress_all_with_error.2634001166 |
| Directory | /workspace/13.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/13.xbar_stress_all_with_rand_reset.1622806903 |
| Short name | T1613 |
| Test name | |
| Test status | |
| Simulation time | 580970147 ps |
| CPU time | 155.34 seconds |
| Started | Jun 29 08:15:29 PM PDT 24 |
| Finished | Jun 29 08:18:05 PM PDT 24 |
| Peak memory | 576436 kb |
| Host | smart-5a22cf09-62dc-408f-87e0-b95437a2a348 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1622806903 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.xbar_stress_all _with_rand_reset.1622806903 |
| Directory | /workspace/13.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/13.xbar_stress_all_with_reset_error.1650677406 |
| Short name | T807 |
| Test name | |
| Test status | |
| Simulation time | 3334610262 ps |
| CPU time | 403.41 seconds |
| Started | Jun 29 08:15:29 PM PDT 24 |
| Finished | Jun 29 08:22:13 PM PDT 24 |
| Peak memory | 574508 kb |
| Host | smart-5bda2d5b-f406-42cd-9f16-15de0d13960b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1650677406 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.xbar_stress_al l_with_reset_error.1650677406 |
| Directory | /workspace/13.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/13.xbar_unmapped_addr.109946430 |
| Short name | T430 |
| Test name | |
| Test status | |
| Simulation time | 236683005 ps |
| CPU time | 31.38 seconds |
| Started | Jun 29 08:15:29 PM PDT 24 |
| Finished | Jun 29 08:16:01 PM PDT 24 |
| Peak memory | 574312 kb |
| Host | smart-e50fba25-03c5-42c2-83a5-3fc791218c68 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=109946430 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.xbar_unmapped_addr.109946430 |
| Directory | /workspace/13.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/14.chip_csr_rw.3907775576 |
| Short name | T1751 |
| Test name | |
| Test status | |
| Simulation time | 3955107852 ps |
| CPU time | 335.2 seconds |
| Started | Jun 29 08:15:53 PM PDT 24 |
| Finished | Jun 29 08:21:29 PM PDT 24 |
| Peak memory | 595268 kb |
| Host | smart-67fe7039-e1b9-42ee-b8b0-715f467d95b3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3907775576 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.chip_csr_rw.3907775576 |
| Directory | /workspace/14.chip_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/14.chip_same_csr_outstanding.4290595894 |
| Short name | T1874 |
| Test name | |
| Test status | |
| Simulation time | 33057209633 ps |
| CPU time | 3695.87 seconds |
| Started | Jun 29 08:15:29 PM PDT 24 |
| Finished | Jun 29 09:17:06 PM PDT 24 |
| Peak memory | 591872 kb |
| Host | smart-156136d9-8bd8-44e5-8a14-1f929087ca7c |
| User | root |
| Command | /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +run_same_csr_outstanding +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4290595894 -assert nopostproc +UVM_TE STNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb - cm_log /dev/null -cm_name 14.chip_same_csr_outstanding.4290595894 |
| Directory | /workspace/14.chip_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/14.xbar_access_same_device.11198164 |
| Short name | T2086 |
| Test name | |
| Test status | |
| Simulation time | 575860343 ps |
| CPU time | 51.92 seconds |
| Started | Jun 29 08:15:50 PM PDT 24 |
| Finished | Jun 29 08:16:42 PM PDT 24 |
| Peak memory | 575284 kb |
| Host | smart-4b967ab6-379b-4bd0-84d5-d21b868fce49 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11198164 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.xbar_access_same_device.11198164 |
| Directory | /workspace/14.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/14.xbar_access_same_device_slow_rsp.3457273147 |
| Short name | T2742 |
| Test name | |
| Test status | |
| Simulation time | 64926975499 ps |
| CPU time | 1127.2 seconds |
| Started | Jun 29 08:15:50 PM PDT 24 |
| Finished | Jun 29 08:34:37 PM PDT 24 |
| Peak memory | 575476 kb |
| Host | smart-b8a38cc4-8fd1-4344-89f8-fe601555e891 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3457273147 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.xbar_access_same_ device_slow_rsp.3457273147 |
| Directory | /workspace/14.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/14.xbar_error_and_unmapped_addr.372981012 |
| Short name | T2368 |
| Test name | |
| Test status | |
| Simulation time | 544179986 ps |
| CPU time | 24.53 seconds |
| Started | Jun 29 08:15:56 PM PDT 24 |
| Finished | Jun 29 08:16:21 PM PDT 24 |
| Peak memory | 573896 kb |
| Host | smart-23782455-e0b5-4f12-b418-7ea944c0f7a5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=372981012 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.xbar_error_and_unmapped_addr .372981012 |
| Directory | /workspace/14.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/14.xbar_error_random.2305138172 |
| Short name | T2782 |
| Test name | |
| Test status | |
| Simulation time | 64887239 ps |
| CPU time | 8.71 seconds |
| Started | Jun 29 08:15:54 PM PDT 24 |
| Finished | Jun 29 08:16:03 PM PDT 24 |
| Peak memory | 573872 kb |
| Host | smart-1b6d835f-1cd0-4e1b-b282-1ac3040178a1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2305138172 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.xbar_error_random.2305138172 |
| Directory | /workspace/14.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/14.xbar_random.2050992456 |
| Short name | T1406 |
| Test name | |
| Test status | |
| Simulation time | 1917579853 ps |
| CPU time | 73.68 seconds |
| Started | Jun 29 08:15:39 PM PDT 24 |
| Finished | Jun 29 08:16:53 PM PDT 24 |
| Peak memory | 575348 kb |
| Host | smart-c43f9e94-1507-45bb-8b11-0c01df4d8063 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2050992456 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.xbar_random.2050992456 |
| Directory | /workspace/14.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/14.xbar_random_large_delays.533788818 |
| Short name | T2246 |
| Test name | |
| Test status | |
| Simulation time | 12900225673 ps |
| CPU time | 144.59 seconds |
| Started | Jun 29 08:15:46 PM PDT 24 |
| Finished | Jun 29 08:18:11 PM PDT 24 |
| Peak memory | 574376 kb |
| Host | smart-9aa86245-1637-4e7d-a8d2-8bb7918d63cf |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=533788818 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.xbar_random_large_delays.533788818 |
| Directory | /workspace/14.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/14.xbar_random_slow_rsp.2105777277 |
| Short name | T2078 |
| Test name | |
| Test status | |
| Simulation time | 26744492829 ps |
| CPU time | 463.56 seconds |
| Started | Jun 29 08:15:48 PM PDT 24 |
| Finished | Jun 29 08:23:31 PM PDT 24 |
| Peak memory | 575376 kb |
| Host | smart-2bcfd56c-192e-49e1-81cf-89e51ddad592 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2105777277 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.xbar_random_slow_rsp.2105777277 |
| Directory | /workspace/14.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/14.xbar_random_zero_delays.3386956757 |
| Short name | T541 |
| Test name | |
| Test status | |
| Simulation time | 228793669 ps |
| CPU time | 23.33 seconds |
| Started | Jun 29 08:15:39 PM PDT 24 |
| Finished | Jun 29 08:16:03 PM PDT 24 |
| Peak memory | 574240 kb |
| Host | smart-33dd5e30-1d28-47e9-9808-568e4708cfe1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3386956757 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.xbar_random_zero_del ays.3386956757 |
| Directory | /workspace/14.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/14.xbar_same_source.3543679901 |
| Short name | T2394 |
| Test name | |
| Test status | |
| Simulation time | 63451334 ps |
| CPU time | 8.53 seconds |
| Started | Jun 29 08:15:55 PM PDT 24 |
| Finished | Jun 29 08:16:04 PM PDT 24 |
| Peak memory | 574252 kb |
| Host | smart-2ec90c65-5976-489c-9261-bff5373ad50b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3543679901 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.xbar_same_source.3543679901 |
| Directory | /workspace/14.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/14.xbar_smoke.2870743847 |
| Short name | T2614 |
| Test name | |
| Test status | |
| Simulation time | 43712955 ps |
| CPU time | 6.57 seconds |
| Started | Jun 29 08:15:39 PM PDT 24 |
| Finished | Jun 29 08:15:46 PM PDT 24 |
| Peak memory | 574264 kb |
| Host | smart-27e840de-6b56-4684-b9f9-12a69973449d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2870743847 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.xbar_smoke.2870743847 |
| Directory | /workspace/14.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/14.xbar_smoke_large_delays.4277126821 |
| Short name | T559 |
| Test name | |
| Test status | |
| Simulation time | 6751810706 ps |
| CPU time | 71.02 seconds |
| Started | Jun 29 08:15:38 PM PDT 24 |
| Finished | Jun 29 08:16:49 PM PDT 24 |
| Peak memory | 574324 kb |
| Host | smart-f6330ada-4a1e-45ee-abc3-29a618597475 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4277126821 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.xbar_smoke_large_delays.4277126821 |
| Directory | /workspace/14.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/14.xbar_smoke_slow_rsp.2018301993 |
| Short name | T1447 |
| Test name | |
| Test status | |
| Simulation time | 5989101014 ps |
| CPU time | 103.84 seconds |
| Started | Jun 29 08:15:38 PM PDT 24 |
| Finished | Jun 29 08:17:23 PM PDT 24 |
| Peak memory | 574144 kb |
| Host | smart-fefac7c4-643e-4c74-bbf5-f51642c8001b |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2018301993 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.xbar_smoke_slow_rsp.2018301993 |
| Directory | /workspace/14.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/14.xbar_smoke_zero_delays.305210158 |
| Short name | T1579 |
| Test name | |
| Test status | |
| Simulation time | 41137949 ps |
| CPU time | 6.29 seconds |
| Started | Jun 29 08:15:37 PM PDT 24 |
| Finished | Jun 29 08:15:44 PM PDT 24 |
| Peak memory | 574252 kb |
| Host | smart-44b5b7ea-38f2-4e57-9a97-b5a5b1cb6c1f |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=305210158 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.xbar_smoke_zero_delays .305210158 |
| Directory | /workspace/14.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/14.xbar_stress_all.4193111217 |
| Short name | T616 |
| Test name | |
| Test status | |
| Simulation time | 2563926527 ps |
| CPU time | 91.72 seconds |
| Started | Jun 29 08:15:53 PM PDT 24 |
| Finished | Jun 29 08:17:25 PM PDT 24 |
| Peak memory | 575444 kb |
| Host | smart-9beefa7e-8e05-46db-801e-001dbe4c7d88 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4193111217 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.xbar_stress_all.4193111217 |
| Directory | /workspace/14.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/14.xbar_stress_all_with_error.4182976211 |
| Short name | T1999 |
| Test name | |
| Test status | |
| Simulation time | 11121212206 ps |
| CPU time | 464.27 seconds |
| Started | Jun 29 08:15:55 PM PDT 24 |
| Finished | Jun 29 08:23:40 PM PDT 24 |
| Peak memory | 574496 kb |
| Host | smart-d981796b-dbdc-4756-8850-55cbd62d5359 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4182976211 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.xbar_stress_all_with_error.4182976211 |
| Directory | /workspace/14.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/14.xbar_stress_all_with_reset_error.2361467058 |
| Short name | T2062 |
| Test name | |
| Test status | |
| Simulation time | 2297811687 ps |
| CPU time | 362.7 seconds |
| Started | Jun 29 08:17:38 PM PDT 24 |
| Finished | Jun 29 08:23:42 PM PDT 24 |
| Peak memory | 574656 kb |
| Host | smart-72662fe4-3f74-4deb-aa21-036991554a35 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2361467058 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.xbar_stress_al l_with_reset_error.2361467058 |
| Directory | /workspace/14.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/14.xbar_unmapped_addr.4033233029 |
| Short name | T477 |
| Test name | |
| Test status | |
| Simulation time | 264718726 ps |
| CPU time | 35.19 seconds |
| Started | Jun 29 08:15:55 PM PDT 24 |
| Finished | Jun 29 08:16:30 PM PDT 24 |
| Peak memory | 575340 kb |
| Host | smart-51346e5a-0c77-4085-a4ce-1e72f9351141 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4033233029 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.xbar_unmapped_addr.4033233029 |
| Directory | /workspace/14.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/15.chip_csr_rw.3831421124 |
| Short name | T363 |
| Test name | |
| Test status | |
| Simulation time | 6525358404 ps |
| CPU time | 739.51 seconds |
| Started | Jun 29 08:16:11 PM PDT 24 |
| Finished | Jun 29 08:28:30 PM PDT 24 |
| Peak memory | 595628 kb |
| Host | smart-48b55877-af02-40bc-b240-fc60ad68f7af |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3831421124 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.chip_csr_rw.3831421124 |
| Directory | /workspace/15.chip_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/15.chip_same_csr_outstanding.1290562377 |
| Short name | T362 |
| Test name | |
| Test status | |
| Simulation time | 29488940960 ps |
| CPU time | 3674.15 seconds |
| Started | Jun 29 08:15:55 PM PDT 24 |
| Finished | Jun 29 09:17:09 PM PDT 24 |
| Peak memory | 591996 kb |
| Host | smart-8f046ae4-35ce-4783-ac01-a5e9628e4eec |
| User | root |
| Command | /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +run_same_csr_outstanding +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1290562377 -assert nopostproc +UVM_TE STNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb - cm_log /dev/null -cm_name 15.chip_same_csr_outstanding.1290562377 |
| Directory | /workspace/15.chip_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/15.chip_tl_errors.3793872228 |
| Short name | T661 |
| Test name | |
| Test status | |
| Simulation time | 4225960175 ps |
| CPU time | 307.14 seconds |
| Started | Jun 29 08:15:53 PM PDT 24 |
| Finished | Jun 29 08:21:01 PM PDT 24 |
| Peak memory | 603612 kb |
| Host | smart-d7b0a53b-b92f-4948-9d96-19b65b1e24fb |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3793872228 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.chip_tl_errors.3793872228 |
| Directory | /workspace/15.chip_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/15.xbar_access_same_device.684729014 |
| Short name | T2536 |
| Test name | |
| Test status | |
| Simulation time | 834722169 ps |
| CPU time | 41.61 seconds |
| Started | Jun 29 08:16:01 PM PDT 24 |
| Finished | Jun 29 08:16:43 PM PDT 24 |
| Peak memory | 575308 kb |
| Host | smart-c0b931ef-fbf3-458f-9c1b-d7dea761f659 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=684729014 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.xbar_access_same_device. 684729014 |
| Directory | /workspace/15.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/15.xbar_access_same_device_slow_rsp.315914917 |
| Short name | T1706 |
| Test name | |
| Test status | |
| Simulation time | 69303933634 ps |
| CPU time | 1297.08 seconds |
| Started | Jun 29 08:16:02 PM PDT 24 |
| Finished | Jun 29 08:37:40 PM PDT 24 |
| Peak memory | 574400 kb |
| Host | smart-0e180421-949d-447a-b0d8-0025f1a97553 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=315914917 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.xbar_access_same_d evice_slow_rsp.315914917 |
| Directory | /workspace/15.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/15.xbar_error_and_unmapped_addr.1350082337 |
| Short name | T2337 |
| Test name | |
| Test status | |
| Simulation time | 695008743 ps |
| CPU time | 30.1 seconds |
| Started | Jun 29 08:16:05 PM PDT 24 |
| Finished | Jun 29 08:16:36 PM PDT 24 |
| Peak memory | 574476 kb |
| Host | smart-4cb1ef58-4d59-4361-bf35-5ead95999dc0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1350082337 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.xbar_error_and_unmapped_add r.1350082337 |
| Directory | /workspace/15.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/15.xbar_error_random.4011891419 |
| Short name | T1581 |
| Test name | |
| Test status | |
| Simulation time | 547605454 ps |
| CPU time | 45.32 seconds |
| Started | Jun 29 08:16:03 PM PDT 24 |
| Finished | Jun 29 08:16:48 PM PDT 24 |
| Peak memory | 573888 kb |
| Host | smart-f29d93ba-7246-4f15-85ff-8cb13f5121bf |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4011891419 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.xbar_error_random.4011891419 |
| Directory | /workspace/15.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/15.xbar_random.3739154759 |
| Short name | T586 |
| Test name | |
| Test status | |
| Simulation time | 1139865559 ps |
| CPU time | 47.31 seconds |
| Started | Jun 29 08:16:05 PM PDT 24 |
| Finished | Jun 29 08:16:52 PM PDT 24 |
| Peak memory | 575292 kb |
| Host | smart-30fd40b6-4c9d-4030-bd47-3c5d67e07555 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3739154759 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.xbar_random.3739154759 |
| Directory | /workspace/15.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/15.xbar_random_large_delays.1756929034 |
| Short name | T1526 |
| Test name | |
| Test status | |
| Simulation time | 5938695210 ps |
| CPU time | 63.01 seconds |
| Started | Jun 29 08:16:01 PM PDT 24 |
| Finished | Jun 29 08:17:04 PM PDT 24 |
| Peak memory | 574324 kb |
| Host | smart-9023c134-2e81-4f19-82ec-4f46bd359ee2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1756929034 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.xbar_random_large_delays.1756929034 |
| Directory | /workspace/15.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/15.xbar_random_slow_rsp.766907167 |
| Short name | T1974 |
| Test name | |
| Test status | |
| Simulation time | 2444570705 ps |
| CPU time | 43.36 seconds |
| Started | Jun 29 08:16:02 PM PDT 24 |
| Finished | Jun 29 08:16:46 PM PDT 24 |
| Peak memory | 574344 kb |
| Host | smart-0e0a8d6d-5150-4028-b218-9aa4a7b3c402 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=766907167 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.xbar_random_slow_rsp.766907167 |
| Directory | /workspace/15.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/15.xbar_random_zero_delays.2626970911 |
| Short name | T1479 |
| Test name | |
| Test status | |
| Simulation time | 598388647 ps |
| CPU time | 57.94 seconds |
| Started | Jun 29 08:16:01 PM PDT 24 |
| Finished | Jun 29 08:16:59 PM PDT 24 |
| Peak memory | 575300 kb |
| Host | smart-e5a60113-9201-413f-8ab3-9bdb4730c5ac |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2626970911 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.xbar_random_zero_del ays.2626970911 |
| Directory | /workspace/15.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/15.xbar_same_source.1277172846 |
| Short name | T2144 |
| Test name | |
| Test status | |
| Simulation time | 1431702646 ps |
| CPU time | 46.91 seconds |
| Started | Jun 29 08:16:02 PM PDT 24 |
| Finished | Jun 29 08:16:49 PM PDT 24 |
| Peak memory | 574248 kb |
| Host | smart-28a75e4c-1de4-4133-8208-418aa08df75f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1277172846 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.xbar_same_source.1277172846 |
| Directory | /workspace/15.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/15.xbar_smoke.993583691 |
| Short name | T531 |
| Test name | |
| Test status | |
| Simulation time | 49108675 ps |
| CPU time | 7.38 seconds |
| Started | Jun 29 08:15:56 PM PDT 24 |
| Finished | Jun 29 08:16:04 PM PDT 24 |
| Peak memory | 574216 kb |
| Host | smart-32cb119c-86b0-43a7-8119-ca9566429357 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=993583691 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.xbar_smoke.993583691 |
| Directory | /workspace/15.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/15.xbar_smoke_large_delays.1266013562 |
| Short name | T1545 |
| Test name | |
| Test status | |
| Simulation time | 9293647305 ps |
| CPU time | 99.97 seconds |
| Started | Jun 29 08:15:54 PM PDT 24 |
| Finished | Jun 29 08:17:34 PM PDT 24 |
| Peak memory | 574332 kb |
| Host | smart-df932427-c812-413e-b096-d7e6ba90e211 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1266013562 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.xbar_smoke_large_delays.1266013562 |
| Directory | /workspace/15.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/15.xbar_smoke_slow_rsp.3638079535 |
| Short name | T2663 |
| Test name | |
| Test status | |
| Simulation time | 4807622599 ps |
| CPU time | 83.16 seconds |
| Started | Jun 29 08:16:01 PM PDT 24 |
| Finished | Jun 29 08:17:24 PM PDT 24 |
| Peak memory | 574200 kb |
| Host | smart-026a5bbc-29e7-4fea-a10e-ae7b7605141e |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3638079535 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.xbar_smoke_slow_rsp.3638079535 |
| Directory | /workspace/15.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/15.xbar_smoke_zero_delays.2397279988 |
| Short name | T1432 |
| Test name | |
| Test status | |
| Simulation time | 41008872 ps |
| CPU time | 6.37 seconds |
| Started | Jun 29 08:15:54 PM PDT 24 |
| Finished | Jun 29 08:16:00 PM PDT 24 |
| Peak memory | 574256 kb |
| Host | smart-00f9767f-f37d-4c14-98b4-3a7749506e41 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2397279988 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.xbar_smoke_zero_delay s.2397279988 |
| Directory | /workspace/15.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/15.xbar_stress_all.923634186 |
| Short name | T2267 |
| Test name | |
| Test status | |
| Simulation time | 2100074802 ps |
| CPU time | 189.79 seconds |
| Started | Jun 29 08:16:10 PM PDT 24 |
| Finished | Jun 29 08:19:20 PM PDT 24 |
| Peak memory | 575400 kb |
| Host | smart-e55c89b1-e142-426f-ac79-8712ce226439 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=923634186 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.xbar_stress_all.923634186 |
| Directory | /workspace/15.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/15.xbar_stress_all_with_error.696099435 |
| Short name | T1953 |
| Test name | |
| Test status | |
| Simulation time | 1469400985 ps |
| CPU time | 58.21 seconds |
| Started | Jun 29 08:16:12 PM PDT 24 |
| Finished | Jun 29 08:17:10 PM PDT 24 |
| Peak memory | 574276 kb |
| Host | smart-4bb277b8-accb-4e67-8a9b-6e9914c4f5e0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=696099435 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.xbar_stress_all_with_error.696099435 |
| Directory | /workspace/15.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/15.xbar_stress_all_with_rand_reset.2155473408 |
| Short name | T2667 |
| Test name | |
| Test status | |
| Simulation time | 4126111265 ps |
| CPU time | 444.49 seconds |
| Started | Jun 29 08:16:08 PM PDT 24 |
| Finished | Jun 29 08:23:33 PM PDT 24 |
| Peak memory | 575504 kb |
| Host | smart-47717c4d-be6d-450d-a927-a32223f82275 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2155473408 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.xbar_stress_all _with_rand_reset.2155473408 |
| Directory | /workspace/15.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/15.xbar_stress_all_with_reset_error.3303764561 |
| Short name | T2856 |
| Test name | |
| Test status | |
| Simulation time | 472151927 ps |
| CPU time | 156.73 seconds |
| Started | Jun 29 08:16:13 PM PDT 24 |
| Finished | Jun 29 08:18:50 PM PDT 24 |
| Peak memory | 577268 kb |
| Host | smart-c2343e27-2124-42f4-809d-ffdbb9f8b2bc |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3303764561 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.xbar_stress_al l_with_reset_error.3303764561 |
| Directory | /workspace/15.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/15.xbar_unmapped_addr.639145976 |
| Short name | T1331 |
| Test name | |
| Test status | |
| Simulation time | 179111159 ps |
| CPU time | 25.8 seconds |
| Started | Jun 29 08:16:03 PM PDT 24 |
| Finished | Jun 29 08:16:29 PM PDT 24 |
| Peak memory | 575356 kb |
| Host | smart-f1d13f82-a785-4a87-8369-87f1ce2b8cb2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=639145976 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.xbar_unmapped_addr.639145976 |
| Directory | /workspace/15.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/16.chip_csr_rw.1184521908 |
| Short name | T365 |
| Test name | |
| Test status | |
| Simulation time | 3602430860 ps |
| CPU time | 364.14 seconds |
| Started | Jun 29 08:16:27 PM PDT 24 |
| Finished | Jun 29 08:22:31 PM PDT 24 |
| Peak memory | 596124 kb |
| Host | smart-fe5cce27-548f-4794-af0f-96cc90fc9a1e |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1184521908 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.chip_csr_rw.1184521908 |
| Directory | /workspace/16.chip_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/16.chip_same_csr_outstanding.4080042330 |
| Short name | T376 |
| Test name | |
| Test status | |
| Simulation time | 15564035208 ps |
| CPU time | 2466.73 seconds |
| Started | Jun 29 08:16:09 PM PDT 24 |
| Finished | Jun 29 08:57:16 PM PDT 24 |
| Peak memory | 591880 kb |
| Host | smart-51e85840-1673-44b5-a805-1abaa5a0299a |
| User | root |
| Command | /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +run_same_csr_outstanding +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4080042330 -assert nopostproc +UVM_TE STNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb - cm_log /dev/null -cm_name 16.chip_same_csr_outstanding.4080042330 |
| Directory | /workspace/16.chip_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/16.xbar_access_same_device.280925594 |
| Short name | T2420 |
| Test name | |
| Test status | |
| Simulation time | 941014114 ps |
| CPU time | 83.21 seconds |
| Started | Jun 29 08:16:21 PM PDT 24 |
| Finished | Jun 29 08:17:44 PM PDT 24 |
| Peak memory | 575304 kb |
| Host | smart-33142caa-5382-4b28-9d3c-73b0dd486c35 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=280925594 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.xbar_access_same_device. 280925594 |
| Directory | /workspace/16.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/16.xbar_access_same_device_slow_rsp.4169238818 |
| Short name | T2256 |
| Test name | |
| Test status | |
| Simulation time | 111971536997 ps |
| CPU time | 1877.69 seconds |
| Started | Jun 29 08:16:19 PM PDT 24 |
| Finished | Jun 29 08:47:37 PM PDT 24 |
| Peak memory | 575504 kb |
| Host | smart-89dafd68-0fc0-4591-bb31-615bb580ca37 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4169238818 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.xbar_access_same_ device_slow_rsp.4169238818 |
| Directory | /workspace/16.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/16.xbar_error_and_unmapped_addr.3109292309 |
| Short name | T1899 |
| Test name | |
| Test status | |
| Simulation time | 61196389 ps |
| CPU time | 9.81 seconds |
| Started | Jun 29 08:16:17 PM PDT 24 |
| Finished | Jun 29 08:16:27 PM PDT 24 |
| Peak memory | 574504 kb |
| Host | smart-e2ba186d-a536-47af-96f0-3db28a7a24ae |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3109292309 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.xbar_error_and_unmapped_add r.3109292309 |
| Directory | /workspace/16.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/16.xbar_error_random.990239960 |
| Short name | T1935 |
| Test name | |
| Test status | |
| Simulation time | 911677826 ps |
| CPU time | 37.95 seconds |
| Started | Jun 29 08:16:19 PM PDT 24 |
| Finished | Jun 29 08:16:57 PM PDT 24 |
| Peak memory | 573912 kb |
| Host | smart-c1946a0c-d032-4620-be43-156437e0bc27 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=990239960 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.xbar_error_random.990239960 |
| Directory | /workspace/16.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/16.xbar_random.2482624469 |
| Short name | T1665 |
| Test name | |
| Test status | |
| Simulation time | 449773785 ps |
| CPU time | 46.73 seconds |
| Started | Jun 29 08:16:20 PM PDT 24 |
| Finished | Jun 29 08:17:07 PM PDT 24 |
| Peak memory | 574260 kb |
| Host | smart-54504d41-3a41-46cb-a6eb-4409c4217f0f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2482624469 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.xbar_random.2482624469 |
| Directory | /workspace/16.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/16.xbar_random_large_delays.1811728068 |
| Short name | T1456 |
| Test name | |
| Test status | |
| Simulation time | 57259077121 ps |
| CPU time | 585.81 seconds |
| Started | Jun 29 08:16:21 PM PDT 24 |
| Finished | Jun 29 08:26:07 PM PDT 24 |
| Peak memory | 575396 kb |
| Host | smart-5d164ec8-9415-490c-98da-4fe809b1bdf1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1811728068 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.xbar_random_large_delays.1811728068 |
| Directory | /workspace/16.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/16.xbar_random_slow_rsp.3311228674 |
| Short name | T1622 |
| Test name | |
| Test status | |
| Simulation time | 36660167431 ps |
| CPU time | 639.71 seconds |
| Started | Jun 29 08:16:18 PM PDT 24 |
| Finished | Jun 29 08:26:58 PM PDT 24 |
| Peak memory | 575376 kb |
| Host | smart-d5b35036-babd-4002-be14-f5546626e1d2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3311228674 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.xbar_random_slow_rsp.3311228674 |
| Directory | /workspace/16.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/16.xbar_random_zero_delays.3814603590 |
| Short name | T2583 |
| Test name | |
| Test status | |
| Simulation time | 477077888 ps |
| CPU time | 48.29 seconds |
| Started | Jun 29 08:16:21 PM PDT 24 |
| Finished | Jun 29 08:17:09 PM PDT 24 |
| Peak memory | 574248 kb |
| Host | smart-2cce4bef-4645-412a-9e2d-96314e3c1f6d |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3814603590 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.xbar_random_zero_del ays.3814603590 |
| Directory | /workspace/16.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/16.xbar_same_source.4269234929 |
| Short name | T1540 |
| Test name | |
| Test status | |
| Simulation time | 375849808 ps |
| CPU time | 30.84 seconds |
| Started | Jun 29 08:16:18 PM PDT 24 |
| Finished | Jun 29 08:16:49 PM PDT 24 |
| Peak memory | 575288 kb |
| Host | smart-444d4156-2ed1-4260-8c7e-70794e22cb60 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4269234929 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.xbar_same_source.4269234929 |
| Directory | /workspace/16.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/16.xbar_smoke.1682653583 |
| Short name | T1506 |
| Test name | |
| Test status | |
| Simulation time | 253882301 ps |
| CPU time | 10.76 seconds |
| Started | Jun 29 08:16:08 PM PDT 24 |
| Finished | Jun 29 08:16:19 PM PDT 24 |
| Peak memory | 574256 kb |
| Host | smart-2a8a526d-79f7-43ed-b504-d65418296300 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1682653583 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.xbar_smoke.1682653583 |
| Directory | /workspace/16.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/16.xbar_smoke_large_delays.1421247134 |
| Short name | T2335 |
| Test name | |
| Test status | |
| Simulation time | 9413400718 ps |
| CPU time | 99.83 seconds |
| Started | Jun 29 08:16:10 PM PDT 24 |
| Finished | Jun 29 08:17:50 PM PDT 24 |
| Peak memory | 574320 kb |
| Host | smart-55f76e9f-572a-4aca-9a9c-d7050de1e765 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1421247134 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.xbar_smoke_large_delays.1421247134 |
| Directory | /workspace/16.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/16.xbar_smoke_slow_rsp.142548513 |
| Short name | T1927 |
| Test name | |
| Test status | |
| Simulation time | 4583116616 ps |
| CPU time | 87.42 seconds |
| Started | Jun 29 08:16:10 PM PDT 24 |
| Finished | Jun 29 08:17:37 PM PDT 24 |
| Peak memory | 574140 kb |
| Host | smart-a5b29a57-d6f4-43b5-8eb3-97f82c23f83b |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=142548513 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.xbar_smoke_slow_rsp.142548513 |
| Directory | /workspace/16.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/16.xbar_smoke_zero_delays.2137500405 |
| Short name | T1609 |
| Test name | |
| Test status | |
| Simulation time | 41492931 ps |
| CPU time | 6.1 seconds |
| Started | Jun 29 08:16:13 PM PDT 24 |
| Finished | Jun 29 08:16:20 PM PDT 24 |
| Peak memory | 574252 kb |
| Host | smart-05b83996-8c28-42ae-a99b-1842e2d043ce |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2137500405 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.xbar_smoke_zero_delay s.2137500405 |
| Directory | /workspace/16.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/16.xbar_stress_all.2375061939 |
| Short name | T2587 |
| Test name | |
| Test status | |
| Simulation time | 4055693528 ps |
| CPU time | 171.87 seconds |
| Started | Jun 29 08:16:20 PM PDT 24 |
| Finished | Jun 29 08:19:12 PM PDT 24 |
| Peak memory | 574460 kb |
| Host | smart-62d14360-6d82-48e5-9048-40c20fb972d9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2375061939 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.xbar_stress_all.2375061939 |
| Directory | /workspace/16.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/16.xbar_stress_all_with_error.621012803 |
| Short name | T1731 |
| Test name | |
| Test status | |
| Simulation time | 7527163754 ps |
| CPU time | 269.12 seconds |
| Started | Jun 29 08:16:19 PM PDT 24 |
| Finished | Jun 29 08:20:49 PM PDT 24 |
| Peak memory | 574672 kb |
| Host | smart-98d15f60-3bd1-4035-94d3-614994d9ba19 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=621012803 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.xbar_stress_all_with_error.621012803 |
| Directory | /workspace/16.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/16.xbar_stress_all_with_rand_reset.1340543700 |
| Short name | T2374 |
| Test name | |
| Test status | |
| Simulation time | 573681382 ps |
| CPU time | 238.85 seconds |
| Started | Jun 29 08:16:18 PM PDT 24 |
| Finished | Jun 29 08:20:18 PM PDT 24 |
| Peak memory | 575468 kb |
| Host | smart-32bbfb01-81eb-4e5c-8593-638927c496d8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1340543700 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.xbar_stress_all _with_rand_reset.1340543700 |
| Directory | /workspace/16.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/16.xbar_stress_all_with_reset_error.735321622 |
| Short name | T1671 |
| Test name | |
| Test status | |
| Simulation time | 3595892449 ps |
| CPU time | 377.22 seconds |
| Started | Jun 29 08:16:30 PM PDT 24 |
| Finished | Jun 29 08:22:48 PM PDT 24 |
| Peak memory | 574456 kb |
| Host | smart-106f3bfc-e18d-499c-8d67-cbc79077e05d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=735321622 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.xbar_stress_all _with_reset_error.735321622 |
| Directory | /workspace/16.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/16.xbar_unmapped_addr.1301749647 |
| Short name | T2304 |
| Test name | |
| Test status | |
| Simulation time | 339964507 ps |
| CPU time | 42.41 seconds |
| Started | Jun 29 08:16:18 PM PDT 24 |
| Finished | Jun 29 08:17:01 PM PDT 24 |
| Peak memory | 574272 kb |
| Host | smart-8a9af240-d7cb-44db-9abc-caca78599af6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1301749647 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.xbar_unmapped_addr.1301749647 |
| Directory | /workspace/16.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/17.chip_csr_rw.2495957160 |
| Short name | T1652 |
| Test name | |
| Test status | |
| Simulation time | 5849705790 ps |
| CPU time | 627.57 seconds |
| Started | Jun 29 08:16:43 PM PDT 24 |
| Finished | Jun 29 08:27:13 PM PDT 24 |
| Peak memory | 597296 kb |
| Host | smart-0fa8574d-46fb-411a-b1ae-7a95349e2b5a |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2495957160 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.chip_csr_rw.2495957160 |
| Directory | /workspace/17.chip_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/17.chip_same_csr_outstanding.1453331463 |
| Short name | T375 |
| Test name | |
| Test status | |
| Simulation time | 13631127570 ps |
| CPU time | 1470.84 seconds |
| Started | Jun 29 08:16:27 PM PDT 24 |
| Finished | Jun 29 08:40:59 PM PDT 24 |
| Peak memory | 591852 kb |
| Host | smart-6a52559e-0904-4065-8cf8-8b012588b727 |
| User | root |
| Command | /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +run_same_csr_outstanding +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1453331463 -assert nopostproc +UVM_TE STNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb - cm_log /dev/null -cm_name 17.chip_same_csr_outstanding.1453331463 |
| Directory | /workspace/17.chip_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/17.chip_tl_errors.3252658731 |
| Short name | T535 |
| Test name | |
| Test status | |
| Simulation time | 4019107855 ps |
| CPU time | 346.26 seconds |
| Started | Jun 29 08:16:30 PM PDT 24 |
| Finished | Jun 29 08:22:17 PM PDT 24 |
| Peak memory | 597796 kb |
| Host | smart-c33055af-b5d3-4a2e-b1e1-256519762dcc |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3252658731 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.chip_tl_errors.3252658731 |
| Directory | /workspace/17.chip_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/17.xbar_access_same_device.2871733186 |
| Short name | T2707 |
| Test name | |
| Test status | |
| Simulation time | 78386568 ps |
| CPU time | 11.91 seconds |
| Started | Jun 29 08:16:37 PM PDT 24 |
| Finished | Jun 29 08:16:50 PM PDT 24 |
| Peak memory | 574220 kb |
| Host | smart-695ccf3e-58bc-411d-b6a2-ac64410409ec |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2871733186 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.xbar_access_same_device .2871733186 |
| Directory | /workspace/17.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/17.xbar_access_same_device_slow_rsp.1084715914 |
| Short name | T2230 |
| Test name | |
| Test status | |
| Simulation time | 139957350388 ps |
| CPU time | 2577.96 seconds |
| Started | Jun 29 08:16:37 PM PDT 24 |
| Finished | Jun 29 08:59:36 PM PDT 24 |
| Peak memory | 574332 kb |
| Host | smart-95ea0349-3ed7-43d5-9320-6e1232347dc2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1084715914 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.xbar_access_same_ device_slow_rsp.1084715914 |
| Directory | /workspace/17.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/17.xbar_error_and_unmapped_addr.2534741935 |
| Short name | T2507 |
| Test name | |
| Test status | |
| Simulation time | 390629284 ps |
| CPU time | 21.31 seconds |
| Started | Jun 29 08:16:43 PM PDT 24 |
| Finished | Jun 29 08:17:05 PM PDT 24 |
| Peak memory | 573932 kb |
| Host | smart-30b0d618-cc29-4a5f-80fb-67e591a9c920 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2534741935 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.xbar_error_and_unmapped_add r.2534741935 |
| Directory | /workspace/17.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/17.xbar_error_random.1446210954 |
| Short name | T2145 |
| Test name | |
| Test status | |
| Simulation time | 186746914 ps |
| CPU time | 18.06 seconds |
| Started | Jun 29 08:16:37 PM PDT 24 |
| Finished | Jun 29 08:16:55 PM PDT 24 |
| Peak memory | 573936 kb |
| Host | smart-50f79527-4efa-483d-9300-6663a4819390 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1446210954 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.xbar_error_random.1446210954 |
| Directory | /workspace/17.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/17.xbar_random.4071574545 |
| Short name | T1657 |
| Test name | |
| Test status | |
| Simulation time | 390040160 ps |
| CPU time | 43.68 seconds |
| Started | Jun 29 08:16:36 PM PDT 24 |
| Finished | Jun 29 08:17:21 PM PDT 24 |
| Peak memory | 575352 kb |
| Host | smart-bae9af67-d6cb-4be0-9719-86256cf48150 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4071574545 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.xbar_random.4071574545 |
| Directory | /workspace/17.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/17.xbar_random_large_delays.711808928 |
| Short name | T1865 |
| Test name | |
| Test status | |
| Simulation time | 51186753648 ps |
| CPU time | 586.67 seconds |
| Started | Jun 29 08:16:36 PM PDT 24 |
| Finished | Jun 29 08:26:24 PM PDT 24 |
| Peak memory | 575316 kb |
| Host | smart-6d0d0752-230b-42be-8e8c-3c09fcb37c6b |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=711808928 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.xbar_random_large_delays.711808928 |
| Directory | /workspace/17.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/17.xbar_random_slow_rsp.1290788137 |
| Short name | T2309 |
| Test name | |
| Test status | |
| Simulation time | 61498551027 ps |
| CPU time | 1027.38 seconds |
| Started | Jun 29 08:16:37 PM PDT 24 |
| Finished | Jun 29 08:33:45 PM PDT 24 |
| Peak memory | 574344 kb |
| Host | smart-3ed93c78-d0d5-4ea0-817f-54a2c0574f60 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1290788137 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.xbar_random_slow_rsp.1290788137 |
| Directory | /workspace/17.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/17.xbar_random_zero_delays.199098933 |
| Short name | T2271 |
| Test name | |
| Test status | |
| Simulation time | 554944433 ps |
| CPU time | 52.69 seconds |
| Started | Jun 29 08:16:37 PM PDT 24 |
| Finished | Jun 29 08:17:30 PM PDT 24 |
| Peak memory | 575300 kb |
| Host | smart-e249aea5-edd6-4f4e-9d78-7f54fc9f32f5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=199098933 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.xbar_random_zero_dela ys.199098933 |
| Directory | /workspace/17.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/17.xbar_same_source.3729509873 |
| Short name | T1708 |
| Test name | |
| Test status | |
| Simulation time | 834698574 ps |
| CPU time | 28.65 seconds |
| Started | Jun 29 08:16:42 PM PDT 24 |
| Finished | Jun 29 08:17:12 PM PDT 24 |
| Peak memory | 574228 kb |
| Host | smart-36e89f8e-9bfc-4d8e-bb49-ea54f6e20568 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3729509873 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.xbar_same_source.3729509873 |
| Directory | /workspace/17.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/17.xbar_smoke.2767256707 |
| Short name | T2797 |
| Test name | |
| Test status | |
| Simulation time | 202242919 ps |
| CPU time | 9.39 seconds |
| Started | Jun 29 08:16:30 PM PDT 24 |
| Finished | Jun 29 08:16:40 PM PDT 24 |
| Peak memory | 574252 kb |
| Host | smart-d2a77a73-ba7f-462b-8b9d-8c6c96e37d52 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2767256707 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.xbar_smoke.2767256707 |
| Directory | /workspace/17.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/17.xbar_smoke_large_delays.21867247 |
| Short name | T1498 |
| Test name | |
| Test status | |
| Simulation time | 6357411555 ps |
| CPU time | 68.17 seconds |
| Started | Jun 29 08:16:42 PM PDT 24 |
| Finished | Jun 29 08:17:52 PM PDT 24 |
| Peak memory | 574320 kb |
| Host | smart-ac922b8a-f958-4a60-b6bd-415d1d0ca584 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21867247 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.xbar_smoke_large_delays.21867247 |
| Directory | /workspace/17.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/17.xbar_smoke_slow_rsp.1634871140 |
| Short name | T75 |
| Test name | |
| Test status | |
| Simulation time | 4600597047 ps |
| CPU time | 75.97 seconds |
| Started | Jun 29 08:16:42 PM PDT 24 |
| Finished | Jun 29 08:17:59 PM PDT 24 |
| Peak memory | 574320 kb |
| Host | smart-b1c24c97-60d7-4560-9008-a508d8fbc34e |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1634871140 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.xbar_smoke_slow_rsp.1634871140 |
| Directory | /workspace/17.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/17.xbar_smoke_zero_delays.4008255876 |
| Short name | T1780 |
| Test name | |
| Test status | |
| Simulation time | 37963517 ps |
| CPU time | 6.03 seconds |
| Started | Jun 29 08:16:30 PM PDT 24 |
| Finished | Jun 29 08:16:37 PM PDT 24 |
| Peak memory | 574252 kb |
| Host | smart-804d96a9-b87f-4919-8783-e649257e8d3f |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4008255876 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.xbar_smoke_zero_delay s.4008255876 |
| Directory | /workspace/17.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/17.xbar_stress_all.886149690 |
| Short name | T1547 |
| Test name | |
| Test status | |
| Simulation time | 2851002140 ps |
| CPU time | 125.68 seconds |
| Started | Jun 29 08:16:43 PM PDT 24 |
| Finished | Jun 29 08:18:50 PM PDT 24 |
| Peak memory | 575460 kb |
| Host | smart-ac791405-0c1e-46b8-a64e-cf31f962b78d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=886149690 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.xbar_stress_all.886149690 |
| Directory | /workspace/17.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/17.xbar_stress_all_with_error.685233757 |
| Short name | T2235 |
| Test name | |
| Test status | |
| Simulation time | 1432679880 ps |
| CPU time | 136.76 seconds |
| Started | Jun 29 08:16:44 PM PDT 24 |
| Finished | Jun 29 08:19:02 PM PDT 24 |
| Peak memory | 574428 kb |
| Host | smart-96fb504c-426d-4375-a49f-4009745f25a9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=685233757 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.xbar_stress_all_with_error.685233757 |
| Directory | /workspace/17.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/17.xbar_stress_all_with_rand_reset.1061099968 |
| Short name | T1694 |
| Test name | |
| Test status | |
| Simulation time | 2031787161 ps |
| CPU time | 258.43 seconds |
| Started | Jun 29 08:16:43 PM PDT 24 |
| Finished | Jun 29 08:21:02 PM PDT 24 |
| Peak memory | 575448 kb |
| Host | smart-43994d5e-7422-4db0-8a7b-1730302fc22a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1061099968 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.xbar_stress_all _with_rand_reset.1061099968 |
| Directory | /workspace/17.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/17.xbar_stress_all_with_reset_error.888801244 |
| Short name | T2571 |
| Test name | |
| Test status | |
| Simulation time | 6333850189 ps |
| CPU time | 746.25 seconds |
| Started | Jun 29 08:16:43 PM PDT 24 |
| Finished | Jun 29 08:29:11 PM PDT 24 |
| Peak memory | 576712 kb |
| Host | smart-6cf1b626-7794-4547-9c01-4d605890b3e0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=888801244 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.xbar_stress_all _with_reset_error.888801244 |
| Directory | /workspace/17.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/17.xbar_unmapped_addr.1377425904 |
| Short name | T2143 |
| Test name | |
| Test status | |
| Simulation time | 302910499 ps |
| CPU time | 40.98 seconds |
| Started | Jun 29 08:16:37 PM PDT 24 |
| Finished | Jun 29 08:17:19 PM PDT 24 |
| Peak memory | 574296 kb |
| Host | smart-2eb78078-1c0d-45e9-8928-23fb0daac512 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1377425904 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.xbar_unmapped_addr.1377425904 |
| Directory | /workspace/17.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/18.chip_csr_rw.2080989583 |
| Short name | T389 |
| Test name | |
| Test status | |
| Simulation time | 3944877084 ps |
| CPU time | 331.58 seconds |
| Started | Jun 29 08:17:01 PM PDT 24 |
| Finished | Jun 29 08:22:33 PM PDT 24 |
| Peak memory | 595728 kb |
| Host | smart-857afd1a-c423-465c-8787-34d4685097df |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2080989583 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.chip_csr_rw.2080989583 |
| Directory | /workspace/18.chip_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/18.chip_same_csr_outstanding.13222079 |
| Short name | T381 |
| Test name | |
| Test status | |
| Simulation time | 16388172116 ps |
| CPU time | 1913.07 seconds |
| Started | Jun 29 08:16:45 PM PDT 24 |
| Finished | Jun 29 08:48:39 PM PDT 24 |
| Peak memory | 591752 kb |
| Host | smart-ef8e3ca0-9156-4eb9-834d-bbbe7b59a998 |
| User | root |
| Command | /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +run_same_csr_outstanding +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13222079 -assert nopostproc +UVM_TEST NAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm _log /dev/null -cm_name 18.chip_same_csr_outstanding.13222079 |
| Directory | /workspace/18.chip_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/18.chip_tl_errors.3000268017 |
| Short name | T546 |
| Test name | |
| Test status | |
| Simulation time | 3732343292 ps |
| CPU time | 295.48 seconds |
| Started | Jun 29 08:16:47 PM PDT 24 |
| Finished | Jun 29 08:21:43 PM PDT 24 |
| Peak memory | 597476 kb |
| Host | smart-f5e346cc-b9cb-43bf-ba10-667ad41da70a |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3000268017 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.chip_tl_errors.3000268017 |
| Directory | /workspace/18.chip_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/18.xbar_access_same_device.1764937655 |
| Short name | T798 |
| Test name | |
| Test status | |
| Simulation time | 1957114749 ps |
| CPU time | 86.45 seconds |
| Started | Jun 29 08:16:53 PM PDT 24 |
| Finished | Jun 29 08:18:20 PM PDT 24 |
| Peak memory | 575332 kb |
| Host | smart-db1146d1-82b9-4a1b-8fa5-b87c07e5c01e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1764937655 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.xbar_access_same_device .1764937655 |
| Directory | /workspace/18.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/18.xbar_access_same_device_slow_rsp.951078724 |
| Short name | T1969 |
| Test name | |
| Test status | |
| Simulation time | 27512234071 ps |
| CPU time | 530.67 seconds |
| Started | Jun 29 08:16:55 PM PDT 24 |
| Finished | Jun 29 08:25:46 PM PDT 24 |
| Peak memory | 575564 kb |
| Host | smart-4a256c9c-ae0b-4d67-8556-e1773404121e |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=951078724 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.xbar_access_same_d evice_slow_rsp.951078724 |
| Directory | /workspace/18.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/18.xbar_error_random.3661190769 |
| Short name | T2862 |
| Test name | |
| Test status | |
| Simulation time | 372434940 ps |
| CPU time | 38.71 seconds |
| Started | Jun 29 08:16:54 PM PDT 24 |
| Finished | Jun 29 08:17:33 PM PDT 24 |
| Peak memory | 574272 kb |
| Host | smart-0598bd1c-68aa-446f-b25b-837c31c9455a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3661190769 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.xbar_error_random.3661190769 |
| Directory | /workspace/18.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/18.xbar_random.336440720 |
| Short name | T1431 |
| Test name | |
| Test status | |
| Simulation time | 390714843 ps |
| CPU time | 40.77 seconds |
| Started | Jun 29 08:16:53 PM PDT 24 |
| Finished | Jun 29 08:17:34 PM PDT 24 |
| Peak memory | 575308 kb |
| Host | smart-e6fb696a-b3b5-424b-a53a-87277e7504c0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=336440720 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.xbar_random.336440720 |
| Directory | /workspace/18.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/18.xbar_random_large_delays.2460161268 |
| Short name | T2109 |
| Test name | |
| Test status | |
| Simulation time | 60039013474 ps |
| CPU time | 634.95 seconds |
| Started | Jun 29 08:16:53 PM PDT 24 |
| Finished | Jun 29 08:27:28 PM PDT 24 |
| Peak memory | 574280 kb |
| Host | smart-b77421e1-20ee-4f85-8224-df07cabf3669 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2460161268 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.xbar_random_large_delays.2460161268 |
| Directory | /workspace/18.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/18.xbar_random_slow_rsp.1276127069 |
| Short name | T2350 |
| Test name | |
| Test status | |
| Simulation time | 32007235476 ps |
| CPU time | 555.85 seconds |
| Started | Jun 29 08:16:54 PM PDT 24 |
| Finished | Jun 29 08:26:10 PM PDT 24 |
| Peak memory | 574316 kb |
| Host | smart-13ef0ecf-e16b-406f-8927-869e8a7fdf8c |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1276127069 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.xbar_random_slow_rsp.1276127069 |
| Directory | /workspace/18.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/18.xbar_random_zero_delays.3504471089 |
| Short name | T2303 |
| Test name | |
| Test status | |
| Simulation time | 405959898 ps |
| CPU time | 39.17 seconds |
| Started | Jun 29 08:16:52 PM PDT 24 |
| Finished | Jun 29 08:17:32 PM PDT 24 |
| Peak memory | 575316 kb |
| Host | smart-5dfe81fa-0341-485e-9804-ed9382ee3b25 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3504471089 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.xbar_random_zero_del ays.3504471089 |
| Directory | /workspace/18.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/18.xbar_same_source.450456401 |
| Short name | T1862 |
| Test name | |
| Test status | |
| Simulation time | 482284292 ps |
| CPU time | 18.73 seconds |
| Started | Jun 29 08:16:54 PM PDT 24 |
| Finished | Jun 29 08:17:13 PM PDT 24 |
| Peak memory | 575268 kb |
| Host | smart-b16eb83b-a4a5-4229-a9e2-45a1ca690206 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=450456401 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.xbar_same_source.450456401 |
| Directory | /workspace/18.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/18.xbar_smoke.1318195731 |
| Short name | T1764 |
| Test name | |
| Test status | |
| Simulation time | 58530250 ps |
| CPU time | 7.28 seconds |
| Started | Jun 29 08:16:44 PM PDT 24 |
| Finished | Jun 29 08:16:53 PM PDT 24 |
| Peak memory | 574268 kb |
| Host | smart-25a6e1ed-205c-4f85-8bf1-2dcaae7436ef |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1318195731 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.xbar_smoke.1318195731 |
| Directory | /workspace/18.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/18.xbar_smoke_large_delays.2173124814 |
| Short name | T2346 |
| Test name | |
| Test status | |
| Simulation time | 11230487811 ps |
| CPU time | 127.68 seconds |
| Started | Jun 29 08:16:44 PM PDT 24 |
| Finished | Jun 29 08:18:53 PM PDT 24 |
| Peak memory | 566052 kb |
| Host | smart-7b449b27-116e-43de-87bd-9e72a1d8db65 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2173124814 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.xbar_smoke_large_delays.2173124814 |
| Directory | /workspace/18.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/18.xbar_smoke_slow_rsp.1769089620 |
| Short name | T1430 |
| Test name | |
| Test status | |
| Simulation time | 5147630042 ps |
| CPU time | 92.42 seconds |
| Started | Jun 29 08:16:52 PM PDT 24 |
| Finished | Jun 29 08:18:25 PM PDT 24 |
| Peak memory | 574308 kb |
| Host | smart-5c6f7a92-6d20-47b5-800c-18b84db270e1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1769089620 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.xbar_smoke_slow_rsp.1769089620 |
| Directory | /workspace/18.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/18.xbar_smoke_zero_delays.1148056311 |
| Short name | T1769 |
| Test name | |
| Test status | |
| Simulation time | 56143303 ps |
| CPU time | 6.98 seconds |
| Started | Jun 29 08:16:44 PM PDT 24 |
| Finished | Jun 29 08:16:53 PM PDT 24 |
| Peak memory | 574272 kb |
| Host | smart-c0c080f0-e0c7-4f7b-89ef-5365a682d6c8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1148056311 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.xbar_smoke_zero_delay s.1148056311 |
| Directory | /workspace/18.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/18.xbar_stress_all.4146699589 |
| Short name | T2610 |
| Test name | |
| Test status | |
| Simulation time | 4203495406 ps |
| CPU time | 200.32 seconds |
| Started | Jun 29 08:17:03 PM PDT 24 |
| Finished | Jun 29 08:20:23 PM PDT 24 |
| Peak memory | 575512 kb |
| Host | smart-7a2fd7a8-6f1c-483b-b296-bb8d92068fed |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4146699589 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.xbar_stress_all.4146699589 |
| Directory | /workspace/18.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/18.xbar_stress_all_with_error.1665730458 |
| Short name | T2779 |
| Test name | |
| Test status | |
| Simulation time | 12555848837 ps |
| CPU time | 467.78 seconds |
| Started | Jun 29 08:17:02 PM PDT 24 |
| Finished | Jun 29 08:24:50 PM PDT 24 |
| Peak memory | 574732 kb |
| Host | smart-98943c21-e1c3-4a15-92dc-021933853c25 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1665730458 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.xbar_stress_all_with_error.1665730458 |
| Directory | /workspace/18.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/18.xbar_stress_all_with_rand_reset.3732301159 |
| Short name | T492 |
| Test name | |
| Test status | |
| Simulation time | 12787525827 ps |
| CPU time | 614.04 seconds |
| Started | Jun 29 08:17:01 PM PDT 24 |
| Finished | Jun 29 08:27:15 PM PDT 24 |
| Peak memory | 575520 kb |
| Host | smart-77851652-aa66-48ee-8e66-a07246f52d53 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3732301159 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.xbar_stress_all _with_rand_reset.3732301159 |
| Directory | /workspace/18.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/18.xbar_stress_all_with_reset_error.1689125310 |
| Short name | T1819 |
| Test name | |
| Test status | |
| Simulation time | 1096052882 ps |
| CPU time | 220.03 seconds |
| Started | Jun 29 08:17:08 PM PDT 24 |
| Finished | Jun 29 08:20:48 PM PDT 24 |
| Peak memory | 576448 kb |
| Host | smart-c16a5d94-1c0f-4b62-a2cf-0d25a64cd68d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1689125310 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.xbar_stress_al l_with_reset_error.1689125310 |
| Directory | /workspace/18.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/18.xbar_unmapped_addr.2351946084 |
| Short name | T1798 |
| Test name | |
| Test status | |
| Simulation time | 203019827 ps |
| CPU time | 28.37 seconds |
| Started | Jun 29 08:16:53 PM PDT 24 |
| Finished | Jun 29 08:17:22 PM PDT 24 |
| Peak memory | 575344 kb |
| Host | smart-7a490c07-c38b-4109-b59a-a1c2ebbf5b76 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2351946084 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.xbar_unmapped_addr.2351946084 |
| Directory | /workspace/18.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/19.chip_csr_rw.2508175439 |
| Short name | T1450 |
| Test name | |
| Test status | |
| Simulation time | 5788355800 ps |
| CPU time | 711.56 seconds |
| Started | Jun 29 08:17:20 PM PDT 24 |
| Finished | Jun 29 08:29:12 PM PDT 24 |
| Peak memory | 597424 kb |
| Host | smart-07329c01-cf5b-42ff-a46c-2977e0215d31 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2508175439 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.chip_csr_rw.2508175439 |
| Directory | /workspace/19.chip_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/19.chip_tl_errors.1163559523 |
| Short name | T2408 |
| Test name | |
| Test status | |
| Simulation time | 3950345180 ps |
| CPU time | 273.83 seconds |
| Started | Jun 29 08:17:10 PM PDT 24 |
| Finished | Jun 29 08:21:45 PM PDT 24 |
| Peak memory | 597516 kb |
| Host | smart-d13b56f8-0388-4cc2-b96e-b2aaf11a0503 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1163559523 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.chip_tl_errors.1163559523 |
| Directory | /workspace/19.chip_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/19.xbar_access_same_device.2522863061 |
| Short name | T2100 |
| Test name | |
| Test status | |
| Simulation time | 121209196 ps |
| CPU time | 16.11 seconds |
| Started | Jun 29 08:17:10 PM PDT 24 |
| Finished | Jun 29 08:17:27 PM PDT 24 |
| Peak memory | 574228 kb |
| Host | smart-d8ac98f5-504d-42cf-9679-c5d5c7e71c5d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2522863061 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.xbar_access_same_device .2522863061 |
| Directory | /workspace/19.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/19.xbar_access_same_device_slow_rsp.114998668 |
| Short name | T1684 |
| Test name | |
| Test status | |
| Simulation time | 122252505350 ps |
| CPU time | 2137.47 seconds |
| Started | Jun 29 08:17:10 PM PDT 24 |
| Finished | Jun 29 08:52:49 PM PDT 24 |
| Peak memory | 575496 kb |
| Host | smart-7a0efa3f-deab-46f4-9ccb-ac03153c2e92 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=114998668 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.xbar_access_same_d evice_slow_rsp.114998668 |
| Directory | /workspace/19.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/19.xbar_error_and_unmapped_addr.2121135098 |
| Short name | T1463 |
| Test name | |
| Test status | |
| Simulation time | 79718725 ps |
| CPU time | 11.58 seconds |
| Started | Jun 29 08:17:11 PM PDT 24 |
| Finished | Jun 29 08:17:23 PM PDT 24 |
| Peak memory | 574504 kb |
| Host | smart-a90cbb0e-e2e8-4918-b90d-26284c0acc42 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2121135098 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.xbar_error_and_unmapped_add r.2121135098 |
| Directory | /workspace/19.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/19.xbar_error_random.877127227 |
| Short name | T2731 |
| Test name | |
| Test status | |
| Simulation time | 1413146851 ps |
| CPU time | 57.89 seconds |
| Started | Jun 29 08:17:12 PM PDT 24 |
| Finished | Jun 29 08:18:11 PM PDT 24 |
| Peak memory | 573888 kb |
| Host | smart-14dc37ef-c587-4f72-a6e0-a34713b0282e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=877127227 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.xbar_error_random.877127227 |
| Directory | /workspace/19.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/19.xbar_random.3502271247 |
| Short name | T1836 |
| Test name | |
| Test status | |
| Simulation time | 141852041 ps |
| CPU time | 14.61 seconds |
| Started | Jun 29 08:17:10 PM PDT 24 |
| Finished | Jun 29 08:17:25 PM PDT 24 |
| Peak memory | 574236 kb |
| Host | smart-3d867949-40e2-4f0e-a73d-d5ccbebf963d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3502271247 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.xbar_random.3502271247 |
| Directory | /workspace/19.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/19.xbar_random_large_delays.3785788387 |
| Short name | T2084 |
| Test name | |
| Test status | |
| Simulation time | 39165925506 ps |
| CPU time | 398.43 seconds |
| Started | Jun 29 08:17:11 PM PDT 24 |
| Finished | Jun 29 08:23:50 PM PDT 24 |
| Peak memory | 575332 kb |
| Host | smart-039d66ba-c430-49a0-9bad-632a595a765c |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3785788387 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.xbar_random_large_delays.3785788387 |
| Directory | /workspace/19.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/19.xbar_random_slow_rsp.2488081508 |
| Short name | T2414 |
| Test name | |
| Test status | |
| Simulation time | 50341999886 ps |
| CPU time | 904.26 seconds |
| Started | Jun 29 08:17:10 PM PDT 24 |
| Finished | Jun 29 08:32:15 PM PDT 24 |
| Peak memory | 574312 kb |
| Host | smart-8d245ae7-4718-483e-9ed3-edc681cf79ba |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2488081508 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.xbar_random_slow_rsp.2488081508 |
| Directory | /workspace/19.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/19.xbar_random_zero_delays.2500563055 |
| Short name | T1893 |
| Test name | |
| Test status | |
| Simulation time | 270995693 ps |
| CPU time | 27.67 seconds |
| Started | Jun 29 08:17:09 PM PDT 24 |
| Finished | Jun 29 08:17:37 PM PDT 24 |
| Peak memory | 575316 kb |
| Host | smart-9d903375-6bdc-4104-bdea-2c09afb26b1a |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2500563055 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.xbar_random_zero_del ays.2500563055 |
| Directory | /workspace/19.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/19.xbar_same_source.4226258625 |
| Short name | T1325 |
| Test name | |
| Test status | |
| Simulation time | 132028287 ps |
| CPU time | 14.27 seconds |
| Started | Jun 29 08:17:12 PM PDT 24 |
| Finished | Jun 29 08:17:27 PM PDT 24 |
| Peak memory | 575428 kb |
| Host | smart-9a3aa2fc-0455-43a5-9b71-8876cb66c0a6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4226258625 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.xbar_same_source.4226258625 |
| Directory | /workspace/19.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/19.xbar_smoke.936640851 |
| Short name | T2604 |
| Test name | |
| Test status | |
| Simulation time | 43235867 ps |
| CPU time | 6.59 seconds |
| Started | Jun 29 08:17:10 PM PDT 24 |
| Finished | Jun 29 08:17:17 PM PDT 24 |
| Peak memory | 574256 kb |
| Host | smart-3b2667b5-e97c-4fd8-b76c-151835704e3a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=936640851 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.xbar_smoke.936640851 |
| Directory | /workspace/19.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/19.xbar_smoke_large_delays.3775993766 |
| Short name | T1474 |
| Test name | |
| Test status | |
| Simulation time | 7207145737 ps |
| CPU time | 81.43 seconds |
| Started | Jun 29 08:17:10 PM PDT 24 |
| Finished | Jun 29 08:18:32 PM PDT 24 |
| Peak memory | 574320 kb |
| Host | smart-6d5217c0-3b33-4376-8927-07cd3b6cf75e |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3775993766 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.xbar_smoke_large_delays.3775993766 |
| Directory | /workspace/19.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/19.xbar_smoke_slow_rsp.2627291114 |
| Short name | T532 |
| Test name | |
| Test status | |
| Simulation time | 2660674909 ps |
| CPU time | 44.56 seconds |
| Started | Jun 29 08:17:09 PM PDT 24 |
| Finished | Jun 29 08:17:54 PM PDT 24 |
| Peak memory | 566080 kb |
| Host | smart-1e4c8670-1796-43ac-adcd-580fe2c325e7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2627291114 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.xbar_smoke_slow_rsp.2627291114 |
| Directory | /workspace/19.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/19.xbar_smoke_zero_delays.1593361757 |
| Short name | T1298 |
| Test name | |
| Test status | |
| Simulation time | 53650832 ps |
| CPU time | 7.25 seconds |
| Started | Jun 29 08:17:10 PM PDT 24 |
| Finished | Jun 29 08:17:18 PM PDT 24 |
| Peak memory | 565940 kb |
| Host | smart-ffbebc0d-50bf-4e4f-b5de-fbf167441f27 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1593361757 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.xbar_smoke_zero_delay s.1593361757 |
| Directory | /workspace/19.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/19.xbar_stress_all.2871978570 |
| Short name | T2214 |
| Test name | |
| Test status | |
| Simulation time | 8065902199 ps |
| CPU time | 338.65 seconds |
| Started | Jun 29 08:17:21 PM PDT 24 |
| Finished | Jun 29 08:22:59 PM PDT 24 |
| Peak memory | 575516 kb |
| Host | smart-93f9881e-8f5b-403d-ba2b-ed930e8b8376 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2871978570 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.xbar_stress_all.2871978570 |
| Directory | /workspace/19.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/19.xbar_stress_all_with_error.3086614585 |
| Short name | T2388 |
| Test name | |
| Test status | |
| Simulation time | 440429898 ps |
| CPU time | 35.71 seconds |
| Started | Jun 29 08:17:20 PM PDT 24 |
| Finished | Jun 29 08:17:56 PM PDT 24 |
| Peak memory | 574212 kb |
| Host | smart-1218179f-6591-47d1-b0b7-14146bed4bfe |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3086614585 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.xbar_stress_all_with_error.3086614585 |
| Directory | /workspace/19.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/19.xbar_stress_all_with_rand_reset.2766668801 |
| Short name | T1643 |
| Test name | |
| Test status | |
| Simulation time | 361962175 ps |
| CPU time | 201.29 seconds |
| Started | Jun 29 08:17:20 PM PDT 24 |
| Finished | Jun 29 08:20:41 PM PDT 24 |
| Peak memory | 576452 kb |
| Host | smart-f547c233-040c-4e79-bb73-8dd2046dc2e4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2766668801 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.xbar_stress_all _with_rand_reset.2766668801 |
| Directory | /workspace/19.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/19.xbar_stress_all_with_reset_error.2171441632 |
| Short name | T2369 |
| Test name | |
| Test status | |
| Simulation time | 3228614723 ps |
| CPU time | 477.4 seconds |
| Started | Jun 29 08:17:21 PM PDT 24 |
| Finished | Jun 29 08:25:19 PM PDT 24 |
| Peak memory | 576508 kb |
| Host | smart-d6150427-7df9-4a88-9c21-c23be0d172d4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2171441632 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.xbar_stress_al l_with_reset_error.2171441632 |
| Directory | /workspace/19.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/19.xbar_unmapped_addr.2228249992 |
| Short name | T1291 |
| Test name | |
| Test status | |
| Simulation time | 24028487 ps |
| CPU time | 6.53 seconds |
| Started | Jun 29 08:17:10 PM PDT 24 |
| Finished | Jun 29 08:17:18 PM PDT 24 |
| Peak memory | 574180 kb |
| Host | smart-6480b2ff-1885-48bf-a6fd-a282e5350db0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2228249992 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.xbar_unmapped_addr.2228249992 |
| Directory | /workspace/19.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/2.chip_csr_aliasing.3203825346 |
| Short name | T1725 |
| Test name | |
| Test status | |
| Simulation time | 28492347414 ps |
| CPU time | 4653.85 seconds |
| Started | Jun 29 08:09:26 PM PDT 24 |
| Finished | Jun 29 09:27:02 PM PDT 24 |
| Peak memory | 592400 kb |
| Host | smart-8b4ebab7-7d0d-4af9-88bd-de1a517ff698 |
| User | root |
| Command | /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +csr_aliasing +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3203825346 -assert nopostproc +UVM_TESTNAME=chip_ base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/ null -cm_name 2.chip_csr_aliasing.3203825346 |
| Directory | /workspace/2.chip_csr_aliasing/latest |
| Test location | /workspace/coverage/cover_reg_top/2.chip_csr_bit_bash.224663736 |
| Short name | T2810 |
| Test name | |
| Test status | |
| Simulation time | 6724635335 ps |
| CPU time | 849.74 seconds |
| Started | Jun 29 08:09:27 PM PDT 24 |
| Finished | Jun 29 08:23:39 PM PDT 24 |
| Peak memory | 588716 kb |
| Host | smart-b6a01b03-7ffd-46b8-9e71-4720b89a0bab |
| User | root |
| Command | /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +num_test_csrs=200 +csr_bit_bash +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=224663736 -assert nopostproc + UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top .vdb -cm_log /dev/null -cm_name 2.chip_csr_bit_bash.224663736 |
| Directory | /workspace/2.chip_csr_bit_bash/latest |
| Test location | /workspace/coverage/cover_reg_top/2.chip_csr_rw.628324404 |
| Short name | T2016 |
| Test name | |
| Test status | |
| Simulation time | 4596169946 ps |
| CPU time | 372.13 seconds |
| Started | Jun 29 08:10:11 PM PDT 24 |
| Finished | Jun 29 08:16:23 PM PDT 24 |
| Peak memory | 597248 kb |
| Host | smart-cecaca08-aaf6-4232-9896-5a70b7e74673 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=628324404 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.chip_csr_rw.628324404 |
| Directory | /workspace/2.chip_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/2.chip_prim_tl_access.2841938096 |
| Short name | T1686 |
| Test name | |
| Test status | |
| Simulation time | 9290294750 ps |
| CPU time | 479.77 seconds |
| Started | Jun 29 08:09:31 PM PDT 24 |
| Finished | Jun 29 08:17:32 PM PDT 24 |
| Peak memory | 589328 kb |
| Host | smart-b324ad1b-4f63-4d54-bcd2-b6838dffdedb |
| User | root |
| Command | /workspace/cover_reg_top/simv +en_scb=0 +en_scb_tl_err_chk=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2841938096 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SE Q=chip_prim_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.chip_prim_tl_access.2841938096 |
| Directory | /workspace/2.chip_prim_tl_access/latest |
| Test location | /workspace/coverage/cover_reg_top/2.chip_rv_dm_lc_disabled.1510763139 |
| Short name | T1664 |
| Test name | |
| Test status | |
| Simulation time | 10223727934 ps |
| CPU time | 410.11 seconds |
| Started | Jun 29 08:09:40 PM PDT 24 |
| Finished | Jun 29 08:16:31 PM PDT 24 |
| Peak memory | 589768 kb |
| Host | smart-57cae5ed-aed0-4f6b-9956-bebbba6d03bb |
| User | root |
| Command | /workspace/cover_reg_top/simv +en_scb=0 +en_scb_tl_err_chk=0 +use_jtag_dmi=1 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1510763139 -assert nopostproc +UVM_TESTNAME=chip_base_t est +UVM_TEST_SEQ=chip_rv_dm_lc_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.chip_rv_dm_lc_disabled.1510763139 |
| Directory | /workspace/2.chip_rv_dm_lc_disabled/latest |
| Test location | /workspace/coverage/cover_reg_top/2.chip_same_csr_outstanding.610650455 |
| Short name | T443 |
| Test name | |
| Test status | |
| Simulation time | 15536025546 ps |
| CPU time | 2165.52 seconds |
| Started | Jun 29 08:09:42 PM PDT 24 |
| Finished | Jun 29 08:45:48 PM PDT 24 |
| Peak memory | 590912 kb |
| Host | smart-529fad40-4c35-4220-9b76-d82e1d92952e |
| User | root |
| Command | /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +run_same_csr_outstanding +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=610650455 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c m_log /dev/null -cm_name 2.chip_same_csr_outstanding.610650455 |
| Directory | /workspace/2.chip_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/2.chip_tl_errors.122303522 |
| Short name | T664 |
| Test name | |
| Test status | |
| Simulation time | 2877720835 ps |
| CPU time | 204.57 seconds |
| Started | Jun 29 08:09:43 PM PDT 24 |
| Finished | Jun 29 08:13:08 PM PDT 24 |
| Peak memory | 597492 kb |
| Host | smart-5313a81f-e8e6-461f-9f13-24cb91bc12ca |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=122303522 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.chip_tl_errors.122303522 |
| Directory | /workspace/2.chip_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/2.xbar_access_same_device.815793548 |
| Short name | T2366 |
| Test name | |
| Test status | |
| Simulation time | 2320535507 ps |
| CPU time | 97.84 seconds |
| Started | Jun 29 08:10:10 PM PDT 24 |
| Finished | Jun 29 08:11:48 PM PDT 24 |
| Peak memory | 575192 kb |
| Host | smart-75a48f20-49b9-4129-8e97-aeb8f44792b4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=815793548 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.xbar_access_same_device.815793548 |
| Directory | /workspace/2.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/2.xbar_access_same_device_slow_rsp.104886187 |
| Short name | T2771 |
| Test name | |
| Test status | |
| Simulation time | 88140621728 ps |
| CPU time | 1681.86 seconds |
| Started | Jun 29 08:09:51 PM PDT 24 |
| Finished | Jun 29 08:37:53 PM PDT 24 |
| Peak memory | 575484 kb |
| Host | smart-d55ebcc7-0e84-4a64-a6de-405cae1df32a |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=104886187 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.xbar_access_same_de vice_slow_rsp.104886187 |
| Directory | /workspace/2.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/2.xbar_error_and_unmapped_addr.1847675351 |
| Short name | T1407 |
| Test name | |
| Test status | |
| Simulation time | 103624054 ps |
| CPU time | 15.73 seconds |
| Started | Jun 29 08:09:58 PM PDT 24 |
| Finished | Jun 29 08:10:14 PM PDT 24 |
| Peak memory | 574528 kb |
| Host | smart-1db2478e-c421-4339-af73-56b713f08900 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1847675351 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.xbar_error_and_unmapped_addr .1847675351 |
| Directory | /workspace/2.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/2.xbar_error_random.1649038922 |
| Short name | T1386 |
| Test name | |
| Test status | |
| Simulation time | 1658297816 ps |
| CPU time | 68.27 seconds |
| Started | Jun 29 08:10:04 PM PDT 24 |
| Finished | Jun 29 08:11:13 PM PDT 24 |
| Peak memory | 574272 kb |
| Host | smart-a8c44f41-3927-4fc1-be24-164a65633cdd |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1649038922 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.xbar_error_random.1649038922 |
| Directory | /workspace/2.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/2.xbar_random.138247997 |
| Short name | T1446 |
| Test name | |
| Test status | |
| Simulation time | 199729104 ps |
| CPU time | 24.7 seconds |
| Started | Jun 29 08:09:50 PM PDT 24 |
| Finished | Jun 29 08:10:15 PM PDT 24 |
| Peak memory | 575320 kb |
| Host | smart-50dce05b-ecbd-44fb-b67d-05ad34ef44a4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=138247997 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.xbar_random.138247997 |
| Directory | /workspace/2.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/2.xbar_random_large_delays.2693035021 |
| Short name | T2103 |
| Test name | |
| Test status | |
| Simulation time | 35438749394 ps |
| CPU time | 386.19 seconds |
| Started | Jun 29 08:09:48 PM PDT 24 |
| Finished | Jun 29 08:16:15 PM PDT 24 |
| Peak memory | 575372 kb |
| Host | smart-c09e53d4-dc3f-4383-826d-188175901eba |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2693035021 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.xbar_random_large_delays.2693035021 |
| Directory | /workspace/2.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/2.xbar_random_slow_rsp.1933019109 |
| Short name | T2091 |
| Test name | |
| Test status | |
| Simulation time | 17694407272 ps |
| CPU time | 303.88 seconds |
| Started | Jun 29 08:09:50 PM PDT 24 |
| Finished | Jun 29 08:14:54 PM PDT 24 |
| Peak memory | 575388 kb |
| Host | smart-88178135-0624-47a7-aca4-b7792f400529 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1933019109 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.xbar_random_slow_rsp.1933019109 |
| Directory | /workspace/2.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/2.xbar_random_zero_delays.1883151574 |
| Short name | T1585 |
| Test name | |
| Test status | |
| Simulation time | 162968573 ps |
| CPU time | 19.09 seconds |
| Started | Jun 29 08:10:13 PM PDT 24 |
| Finished | Jun 29 08:10:32 PM PDT 24 |
| Peak memory | 575260 kb |
| Host | smart-c7f400fc-59b7-4d3e-8817-0812aab121be |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1883151574 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.xbar_random_zero_dela ys.1883151574 |
| Directory | /workspace/2.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/2.xbar_same_source.1431703170 |
| Short name | T1966 |
| Test name | |
| Test status | |
| Simulation time | 147073921 ps |
| CPU time | 14.09 seconds |
| Started | Jun 29 08:09:53 PM PDT 24 |
| Finished | Jun 29 08:10:07 PM PDT 24 |
| Peak memory | 574224 kb |
| Host | smart-24a43da6-6767-427a-95d8-aba12316a5c3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1431703170 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.xbar_same_source.1431703170 |
| Directory | /workspace/2.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/2.xbar_smoke.1284048861 |
| Short name | T2685 |
| Test name | |
| Test status | |
| Simulation time | 44633707 ps |
| CPU time | 6.63 seconds |
| Started | Jun 29 08:09:31 PM PDT 24 |
| Finished | Jun 29 08:09:38 PM PDT 24 |
| Peak memory | 574244 kb |
| Host | smart-87ca741d-7edc-4a0d-8620-ee9fc6ee1c1a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1284048861 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.xbar_smoke.1284048861 |
| Directory | /workspace/2.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/2.xbar_smoke_large_delays.376518387 |
| Short name | T1411 |
| Test name | |
| Test status | |
| Simulation time | 9016389889 ps |
| CPU time | 98.62 seconds |
| Started | Jun 29 08:09:51 PM PDT 24 |
| Finished | Jun 29 08:11:29 PM PDT 24 |
| Peak memory | 574328 kb |
| Host | smart-9eb21b86-1be6-4a7d-b254-c35407747e05 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=376518387 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.xbar_smoke_large_delays.376518387 |
| Directory | /workspace/2.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/2.xbar_smoke_slow_rsp.2297478423 |
| Short name | T2464 |
| Test name | |
| Test status | |
| Simulation time | 4116830464 ps |
| CPU time | 80.18 seconds |
| Started | Jun 29 08:09:52 PM PDT 24 |
| Finished | Jun 29 08:11:12 PM PDT 24 |
| Peak memory | 574144 kb |
| Host | smart-1cd35833-cdee-4889-b793-9280a7274ac8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2297478423 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.xbar_smoke_slow_rsp.2297478423 |
| Directory | /workspace/2.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/2.xbar_smoke_zero_delays.584813636 |
| Short name | T2139 |
| Test name | |
| Test status | |
| Simulation time | 51220058 ps |
| CPU time | 8.09 seconds |
| Started | Jun 29 08:09:42 PM PDT 24 |
| Finished | Jun 29 08:09:50 PM PDT 24 |
| Peak memory | 574216 kb |
| Host | smart-ee0aadfc-aff0-4291-9795-d14184a804df |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=584813636 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.xbar_smoke_zero_delays. 584813636 |
| Directory | /workspace/2.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/2.xbar_stress_all.1727512515 |
| Short name | T2553 |
| Test name | |
| Test status | |
| Simulation time | 558128295 ps |
| CPU time | 43.09 seconds |
| Started | Jun 29 08:10:15 PM PDT 24 |
| Finished | Jun 29 08:10:58 PM PDT 24 |
| Peak memory | 574092 kb |
| Host | smart-494af1d2-6a62-4d04-8572-86f6947b1436 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1727512515 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.xbar_stress_all.1727512515 |
| Directory | /workspace/2.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/2.xbar_stress_all_with_error.4113965017 |
| Short name | T1984 |
| Test name | |
| Test status | |
| Simulation time | 2945450955 ps |
| CPU time | 141.68 seconds |
| Started | Jun 29 08:10:07 PM PDT 24 |
| Finished | Jun 29 08:12:29 PM PDT 24 |
| Peak memory | 574600 kb |
| Host | smart-badd1387-b024-4c83-9eec-53c41eb91fb3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4113965017 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.xbar_stress_all_with_error.4113965017 |
| Directory | /workspace/2.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/2.xbar_stress_all_with_rand_reset.876920295 |
| Short name | T2747 |
| Test name | |
| Test status | |
| Simulation time | 8312050074 ps |
| CPU time | 395.24 seconds |
| Started | Jun 29 08:10:14 PM PDT 24 |
| Finished | Jun 29 08:16:49 PM PDT 24 |
| Peak memory | 575316 kb |
| Host | smart-52186501-2021-46c9-955e-261521055133 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=876920295 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_res et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.xbar_stress_all_w ith_rand_reset.876920295 |
| Directory | /workspace/2.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/2.xbar_stress_all_with_reset_error.749132311 |
| Short name | T2096 |
| Test name | |
| Test status | |
| Simulation time | 159371294 ps |
| CPU time | 44.73 seconds |
| Started | Jun 29 08:10:21 PM PDT 24 |
| Finished | Jun 29 08:11:06 PM PDT 24 |
| Peak memory | 575388 kb |
| Host | smart-4c847bcb-4b08-415b-97fe-b310715faf18 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=749132311 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.xbar_stress_all_ with_reset_error.749132311 |
| Directory | /workspace/2.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/2.xbar_unmapped_addr.1162835958 |
| Short name | T2660 |
| Test name | |
| Test status | |
| Simulation time | 303128405 ps |
| CPU time | 33.74 seconds |
| Started | Jun 29 08:10:11 PM PDT 24 |
| Finished | Jun 29 08:10:45 PM PDT 24 |
| Peak memory | 574076 kb |
| Host | smart-b44d283c-3d1a-4f44-9306-954c8f1c070a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1162835958 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.xbar_unmapped_addr.1162835958 |
| Directory | /workspace/2.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/20.chip_tl_errors.1775325668 |
| Short name | T1894 |
| Test name | |
| Test status | |
| Simulation time | 3063432975 ps |
| CPU time | 137.11 seconds |
| Started | Jun 29 08:17:22 PM PDT 24 |
| Finished | Jun 29 08:19:39 PM PDT 24 |
| Peak memory | 597496 kb |
| Host | smart-31ee9c3c-b81d-4f9b-868e-9192534b3d12 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1775325668 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.chip_tl_errors.1775325668 |
| Directory | /workspace/20.chip_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/20.xbar_access_same_device.1982507282 |
| Short name | T2528 |
| Test name | |
| Test status | |
| Simulation time | 928067444 ps |
| CPU time | 91.78 seconds |
| Started | Jun 29 08:17:30 PM PDT 24 |
| Finished | Jun 29 08:19:02 PM PDT 24 |
| Peak memory | 574232 kb |
| Host | smart-07e82231-8c2d-4979-8280-13658018a8f9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1982507282 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.xbar_access_same_device .1982507282 |
| Directory | /workspace/20.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/20.xbar_access_same_device_slow_rsp.2600438048 |
| Short name | T802 |
| Test name | |
| Test status | |
| Simulation time | 95890397522 ps |
| CPU time | 1719.34 seconds |
| Started | Jun 29 08:17:29 PM PDT 24 |
| Finished | Jun 29 08:46:08 PM PDT 24 |
| Peak memory | 575416 kb |
| Host | smart-d93be704-68a6-47a8-a7c0-a9ef05fb2b66 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2600438048 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.xbar_access_same_ device_slow_rsp.2600438048 |
| Directory | /workspace/20.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/20.xbar_error_and_unmapped_addr.3751498303 |
| Short name | T1315 |
| Test name | |
| Test status | |
| Simulation time | 1328339493 ps |
| CPU time | 58.85 seconds |
| Started | Jun 29 08:17:39 PM PDT 24 |
| Finished | Jun 29 08:18:38 PM PDT 24 |
| Peak memory | 573904 kb |
| Host | smart-36264744-0e49-45ed-91fb-e2b50599caa7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3751498303 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.xbar_error_and_unmapped_add r.3751498303 |
| Directory | /workspace/20.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/20.xbar_error_random.1344936971 |
| Short name | T1333 |
| Test name | |
| Test status | |
| Simulation time | 871127720 ps |
| CPU time | 35.65 seconds |
| Started | Jun 29 08:17:30 PM PDT 24 |
| Finished | Jun 29 08:18:06 PM PDT 24 |
| Peak memory | 574492 kb |
| Host | smart-2124d819-b8a6-4f55-8321-f86cb1328a0e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1344936971 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.xbar_error_random.1344936971 |
| Directory | /workspace/20.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/20.xbar_random.3354887521 |
| Short name | T1582 |
| Test name | |
| Test status | |
| Simulation time | 106321678 ps |
| CPU time | 13.67 seconds |
| Started | Jun 29 08:17:30 PM PDT 24 |
| Finished | Jun 29 08:17:44 PM PDT 24 |
| Peak memory | 575308 kb |
| Host | smart-f7007fe7-fa73-492f-910f-b673f28c8bc1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3354887521 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.xbar_random.3354887521 |
| Directory | /workspace/20.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/20.xbar_random_large_delays.1393422843 |
| Short name | T503 |
| Test name | |
| Test status | |
| Simulation time | 24059915064 ps |
| CPU time | 259.6 seconds |
| Started | Jun 29 08:17:30 PM PDT 24 |
| Finished | Jun 29 08:21:50 PM PDT 24 |
| Peak memory | 575392 kb |
| Host | smart-935a4ad3-0589-4ad3-867e-1703bd1cb030 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1393422843 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.xbar_random_large_delays.1393422843 |
| Directory | /workspace/20.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/20.xbar_random_slow_rsp.3155201244 |
| Short name | T1495 |
| Test name | |
| Test status | |
| Simulation time | 51635789140 ps |
| CPU time | 925.99 seconds |
| Started | Jun 29 08:17:29 PM PDT 24 |
| Finished | Jun 29 08:32:55 PM PDT 24 |
| Peak memory | 574364 kb |
| Host | smart-fa71bc46-e107-4e14-ac48-a4bb459d7ee7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3155201244 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.xbar_random_slow_rsp.3155201244 |
| Directory | /workspace/20.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/20.xbar_random_zero_delays.1809301391 |
| Short name | T2356 |
| Test name | |
| Test status | |
| Simulation time | 244927272 ps |
| CPU time | 24.11 seconds |
| Started | Jun 29 08:17:33 PM PDT 24 |
| Finished | Jun 29 08:17:57 PM PDT 24 |
| Peak memory | 575272 kb |
| Host | smart-d5738075-4e30-4014-a581-4e019f14b54b |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1809301391 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.xbar_random_zero_del ays.1809301391 |
| Directory | /workspace/20.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/20.xbar_same_source.3165064678 |
| Short name | T1799 |
| Test name | |
| Test status | |
| Simulation time | 2459568217 ps |
| CPU time | 87.18 seconds |
| Started | Jun 29 08:17:29 PM PDT 24 |
| Finished | Jun 29 08:18:57 PM PDT 24 |
| Peak memory | 574296 kb |
| Host | smart-d98866e0-7296-4878-9a7d-87a883aabd31 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3165064678 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.xbar_same_source.3165064678 |
| Directory | /workspace/20.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/20.xbar_smoke.241352697 |
| Short name | T1388 |
| Test name | |
| Test status | |
| Simulation time | 48126485 ps |
| CPU time | 6.71 seconds |
| Started | Jun 29 08:17:22 PM PDT 24 |
| Finished | Jun 29 08:17:29 PM PDT 24 |
| Peak memory | 574256 kb |
| Host | smart-bf692081-47d0-45d0-9920-e965facfa36f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=241352697 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.xbar_smoke.241352697 |
| Directory | /workspace/20.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/20.xbar_smoke_large_delays.3113820003 |
| Short name | T2294 |
| Test name | |
| Test status | |
| Simulation time | 7673636366 ps |
| CPU time | 78.62 seconds |
| Started | Jun 29 08:17:32 PM PDT 24 |
| Finished | Jun 29 08:18:51 PM PDT 24 |
| Peak memory | 566080 kb |
| Host | smart-ec4d2678-8f79-4065-a551-0f44b8369460 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3113820003 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.xbar_smoke_large_delays.3113820003 |
| Directory | /workspace/20.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/20.xbar_smoke_slow_rsp.4241463186 |
| Short name | T2831 |
| Test name | |
| Test status | |
| Simulation time | 4478293257 ps |
| CPU time | 77.8 seconds |
| Started | Jun 29 08:17:33 PM PDT 24 |
| Finished | Jun 29 08:18:51 PM PDT 24 |
| Peak memory | 574112 kb |
| Host | smart-e3b27d87-fa00-404e-b102-4a1171f6e934 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4241463186 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.xbar_smoke_slow_rsp.4241463186 |
| Directory | /workspace/20.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/20.xbar_smoke_zero_delays.221835124 |
| Short name | T2146 |
| Test name | |
| Test status | |
| Simulation time | 56239408 ps |
| CPU time | 7.64 seconds |
| Started | Jun 29 08:17:32 PM PDT 24 |
| Finished | Jun 29 08:17:40 PM PDT 24 |
| Peak memory | 566012 kb |
| Host | smart-c4fc3263-296b-460b-b3e2-4a019ed87ea2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=221835124 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.xbar_smoke_zero_delays .221835124 |
| Directory | /workspace/20.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/20.xbar_stress_all.2739307831 |
| Short name | T1508 |
| Test name | |
| Test status | |
| Simulation time | 3910649822 ps |
| CPU time | 177.65 seconds |
| Started | Jun 29 08:17:38 PM PDT 24 |
| Finished | Jun 29 08:20:36 PM PDT 24 |
| Peak memory | 575524 kb |
| Host | smart-526f1804-ceab-4986-be30-b43e2a69f1d3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2739307831 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.xbar_stress_all.2739307831 |
| Directory | /workspace/20.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/20.xbar_stress_all_with_error.612677421 |
| Short name | T2261 |
| Test name | |
| Test status | |
| Simulation time | 11984192525 ps |
| CPU time | 466.94 seconds |
| Started | Jun 29 08:17:37 PM PDT 24 |
| Finished | Jun 29 08:25:25 PM PDT 24 |
| Peak memory | 574464 kb |
| Host | smart-17964879-668e-4d00-b1a2-afdb5bcb4be5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=612677421 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.xbar_stress_all_with_error.612677421 |
| Directory | /workspace/20.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/20.xbar_stress_all_with_rand_reset.1047794426 |
| Short name | T2806 |
| Test name | |
| Test status | |
| Simulation time | 147095339 ps |
| CPU time | 71.28 seconds |
| Started | Jun 29 08:17:36 PM PDT 24 |
| Finished | Jun 29 08:18:48 PM PDT 24 |
| Peak memory | 575452 kb |
| Host | smart-d1a12902-9669-4eaf-a422-65e89865f395 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1047794426 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.xbar_stress_all _with_rand_reset.1047794426 |
| Directory | /workspace/20.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/20.xbar_stress_all_with_reset_error.3600700376 |
| Short name | T809 |
| Test name | |
| Test status | |
| Simulation time | 465999390 ps |
| CPU time | 111.41 seconds |
| Started | Jun 29 08:17:38 PM PDT 24 |
| Finished | Jun 29 08:19:30 PM PDT 24 |
| Peak memory | 576440 kb |
| Host | smart-9f9180df-f087-4bee-97e1-42438cbbda16 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3600700376 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.xbar_stress_al l_with_reset_error.3600700376 |
| Directory | /workspace/20.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/20.xbar_unmapped_addr.778487895 |
| Short name | T2082 |
| Test name | |
| Test status | |
| Simulation time | 502462489 ps |
| CPU time | 27.51 seconds |
| Started | Jun 29 08:17:30 PM PDT 24 |
| Finished | Jun 29 08:17:58 PM PDT 24 |
| Peak memory | 575356 kb |
| Host | smart-a0ff5931-92aa-40fc-a365-796d31827fe0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=778487895 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.xbar_unmapped_addr.778487895 |
| Directory | /workspace/20.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/21.chip_tl_errors.3245031804 |
| Short name | T1945 |
| Test name | |
| Test status | |
| Simulation time | 2974390452 ps |
| CPU time | 188.39 seconds |
| Started | Jun 29 08:17:38 PM PDT 24 |
| Finished | Jun 29 08:20:46 PM PDT 24 |
| Peak memory | 597532 kb |
| Host | smart-19ee2498-d8d5-4166-90f6-8e0fdaf6e079 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3245031804 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.chip_tl_errors.3245031804 |
| Directory | /workspace/21.chip_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/21.xbar_access_same_device.2597255967 |
| Short name | T2137 |
| Test name | |
| Test status | |
| Simulation time | 817118213 ps |
| CPU time | 68.66 seconds |
| Started | Jun 29 08:17:51 PM PDT 24 |
| Finished | Jun 29 08:19:00 PM PDT 24 |
| Peak memory | 574276 kb |
| Host | smart-4e8f0e26-1570-46f6-8f40-0c786e0e48ed |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2597255967 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.xbar_access_same_device .2597255967 |
| Directory | /workspace/21.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/21.xbar_access_same_device_slow_rsp.2846104118 |
| Short name | T2851 |
| Test name | |
| Test status | |
| Simulation time | 88039194937 ps |
| CPU time | 1532.71 seconds |
| Started | Jun 29 08:17:45 PM PDT 24 |
| Finished | Jun 29 08:43:18 PM PDT 24 |
| Peak memory | 574372 kb |
| Host | smart-a1aaf4d9-0b4f-4a4f-8211-4d3530bea5b0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2846104118 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.xbar_access_same_ device_slow_rsp.2846104118 |
| Directory | /workspace/21.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/21.xbar_error_and_unmapped_addr.4102372718 |
| Short name | T1883 |
| Test name | |
| Test status | |
| Simulation time | 661329552 ps |
| CPU time | 32.15 seconds |
| Started | Jun 29 08:17:55 PM PDT 24 |
| Finished | Jun 29 08:18:27 PM PDT 24 |
| Peak memory | 573948 kb |
| Host | smart-f00dd59d-ffe8-470e-899c-d6001e75b148 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4102372718 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.xbar_error_and_unmapped_add r.4102372718 |
| Directory | /workspace/21.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/21.xbar_error_random.847613682 |
| Short name | T2561 |
| Test name | |
| Test status | |
| Simulation time | 2013676654 ps |
| CPU time | 84.79 seconds |
| Started | Jun 29 08:17:48 PM PDT 24 |
| Finished | Jun 29 08:19:13 PM PDT 24 |
| Peak memory | 574252 kb |
| Host | smart-90ef8b2a-da61-4da3-ae76-dd64e69a83ae |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=847613682 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.xbar_error_random.847613682 |
| Directory | /workspace/21.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/21.xbar_random.461308403 |
| Short name | T1728 |
| Test name | |
| Test status | |
| Simulation time | 2486398529 ps |
| CPU time | 100.28 seconds |
| Started | Jun 29 08:17:45 PM PDT 24 |
| Finished | Jun 29 08:19:25 PM PDT 24 |
| Peak memory | 575352 kb |
| Host | smart-eef22075-50f2-4a2b-8f78-7fb0091036e4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=461308403 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.xbar_random.461308403 |
| Directory | /workspace/21.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/21.xbar_random_large_delays.74797896 |
| Short name | T2018 |
| Test name | |
| Test status | |
| Simulation time | 18315507326 ps |
| CPU time | 198.09 seconds |
| Started | Jun 29 08:17:50 PM PDT 24 |
| Finished | Jun 29 08:21:09 PM PDT 24 |
| Peak memory | 575384 kb |
| Host | smart-13e97b7c-6616-49a1-af92-e91a3e74bbf8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74797896 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.xbar_random_large_delays.74797896 |
| Directory | /workspace/21.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/21.xbar_random_slow_rsp.1124792312 |
| Short name | T2519 |
| Test name | |
| Test status | |
| Simulation time | 19193965761 ps |
| CPU time | 320.75 seconds |
| Started | Jun 29 08:17:46 PM PDT 24 |
| Finished | Jun 29 08:23:07 PM PDT 24 |
| Peak memory | 575404 kb |
| Host | smart-1533c740-244e-40a5-93af-88ecf4c79d0b |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1124792312 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.xbar_random_slow_rsp.1124792312 |
| Directory | /workspace/21.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/21.xbar_random_zero_delays.999158908 |
| Short name | T2557 |
| Test name | |
| Test status | |
| Simulation time | 561970090 ps |
| CPU time | 59.36 seconds |
| Started | Jun 29 08:17:45 PM PDT 24 |
| Finished | Jun 29 08:18:45 PM PDT 24 |
| Peak memory | 575296 kb |
| Host | smart-b82963d1-15cd-4828-92bb-d7eab2250ebb |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=999158908 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.xbar_random_zero_dela ys.999158908 |
| Directory | /workspace/21.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/21.xbar_same_source.1076150217 |
| Short name | T2736 |
| Test name | |
| Test status | |
| Simulation time | 2499759040 ps |
| CPU time | 79.99 seconds |
| Started | Jun 29 08:17:47 PM PDT 24 |
| Finished | Jun 29 08:19:07 PM PDT 24 |
| Peak memory | 575316 kb |
| Host | smart-0de55ddc-3022-489b-a611-c436a3c81a02 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1076150217 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.xbar_same_source.1076150217 |
| Directory | /workspace/21.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/21.xbar_smoke.2005430165 |
| Short name | T1917 |
| Test name | |
| Test status | |
| Simulation time | 54847437 ps |
| CPU time | 7.17 seconds |
| Started | Jun 29 08:17:37 PM PDT 24 |
| Finished | Jun 29 08:17:44 PM PDT 24 |
| Peak memory | 566028 kb |
| Host | smart-cfae7692-e136-4036-a6e0-a5f9de82fcc1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2005430165 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.xbar_smoke.2005430165 |
| Directory | /workspace/21.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/21.xbar_smoke_large_delays.1020299736 |
| Short name | T1963 |
| Test name | |
| Test status | |
| Simulation time | 9184519322 ps |
| CPU time | 100.71 seconds |
| Started | Jun 29 08:17:40 PM PDT 24 |
| Finished | Jun 29 08:19:21 PM PDT 24 |
| Peak memory | 574340 kb |
| Host | smart-8d9c79c2-0bee-4579-af3f-43ff8800b229 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1020299736 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.xbar_smoke_large_delays.1020299736 |
| Directory | /workspace/21.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/21.xbar_smoke_slow_rsp.3456989778 |
| Short name | T1933 |
| Test name | |
| Test status | |
| Simulation time | 4776870726 ps |
| CPU time | 82.44 seconds |
| Started | Jun 29 08:17:46 PM PDT 24 |
| Finished | Jun 29 08:19:08 PM PDT 24 |
| Peak memory | 566112 kb |
| Host | smart-6557dc8a-c870-4f39-871e-6dc4904b9e23 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3456989778 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.xbar_smoke_slow_rsp.3456989778 |
| Directory | /workspace/21.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/21.xbar_smoke_zero_delays.1024552920 |
| Short name | T2552 |
| Test name | |
| Test status | |
| Simulation time | 43026565 ps |
| CPU time | 6.07 seconds |
| Started | Jun 29 08:17:39 PM PDT 24 |
| Finished | Jun 29 08:17:45 PM PDT 24 |
| Peak memory | 574264 kb |
| Host | smart-6e8922d1-1311-4124-86ee-e0bb71d20924 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1024552920 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.xbar_smoke_zero_delay s.1024552920 |
| Directory | /workspace/21.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/21.xbar_stress_all.2655478815 |
| Short name | T2155 |
| Test name | |
| Test status | |
| Simulation time | 1181483523 ps |
| CPU time | 110.72 seconds |
| Started | Jun 29 08:17:59 PM PDT 24 |
| Finished | Jun 29 08:19:50 PM PDT 24 |
| Peak memory | 575444 kb |
| Host | smart-292dc4f4-b11d-454f-beb9-f57f2e01725a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2655478815 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.xbar_stress_all.2655478815 |
| Directory | /workspace/21.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/21.xbar_stress_all_with_error.3967991482 |
| Short name | T2212 |
| Test name | |
| Test status | |
| Simulation time | 6677856957 ps |
| CPU time | 253.09 seconds |
| Started | Jun 29 08:17:59 PM PDT 24 |
| Finished | Jun 29 08:22:13 PM PDT 24 |
| Peak memory | 574676 kb |
| Host | smart-fe7a26cf-b44e-4f1e-b497-15846192a1bc |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3967991482 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.xbar_stress_all_with_error.3967991482 |
| Directory | /workspace/21.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/21.xbar_stress_all_with_rand_reset.1031280957 |
| Short name | T2136 |
| Test name | |
| Test status | |
| Simulation time | 330620815 ps |
| CPU time | 119.59 seconds |
| Started | Jun 29 08:17:54 PM PDT 24 |
| Finished | Jun 29 08:19:54 PM PDT 24 |
| Peak memory | 575456 kb |
| Host | smart-0ee7416a-d09e-45e0-b167-c945623ffc6a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1031280957 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.xbar_stress_all _with_rand_reset.1031280957 |
| Directory | /workspace/21.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/21.xbar_stress_all_with_reset_error.2835312967 |
| Short name | T1309 |
| Test name | |
| Test status | |
| Simulation time | 7847390 ps |
| CPU time | 12.51 seconds |
| Started | Jun 29 08:17:53 PM PDT 24 |
| Finished | Jun 29 08:18:06 PM PDT 24 |
| Peak memory | 565672 kb |
| Host | smart-9124939e-ec29-4c92-bce0-2f9c2eda3aa6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2835312967 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.xbar_stress_al l_with_reset_error.2835312967 |
| Directory | /workspace/21.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/21.xbar_unmapped_addr.692729762 |
| Short name | T1497 |
| Test name | |
| Test status | |
| Simulation time | 229787761 ps |
| CPU time | 29.88 seconds |
| Started | Jun 29 08:17:53 PM PDT 24 |
| Finished | Jun 29 08:18:24 PM PDT 24 |
| Peak memory | 575388 kb |
| Host | smart-0dba420a-4a8e-47eb-a48f-fb758a8ca3eb |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=692729762 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.xbar_unmapped_addr.692729762 |
| Directory | /workspace/21.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/22.xbar_access_same_device.1990703852 |
| Short name | T2495 |
| Test name | |
| Test status | |
| Simulation time | 75293149 ps |
| CPU time | 8.82 seconds |
| Started | Jun 29 08:17:57 PM PDT 24 |
| Finished | Jun 29 08:18:06 PM PDT 24 |
| Peak memory | 566020 kb |
| Host | smart-9e657484-ac1e-4a6e-b7e4-72337ed470e4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1990703852 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.xbar_access_same_device .1990703852 |
| Directory | /workspace/22.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/22.xbar_access_same_device_slow_rsp.1767454360 |
| Short name | T1667 |
| Test name | |
| Test status | |
| Simulation time | 103351636845 ps |
| CPU time | 1805.7 seconds |
| Started | Jun 29 08:17:53 PM PDT 24 |
| Finished | Jun 29 08:47:59 PM PDT 24 |
| Peak memory | 575472 kb |
| Host | smart-b95daa3d-bb22-405b-96a0-8aa3efeeba23 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1767454360 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.xbar_access_same_ device_slow_rsp.1767454360 |
| Directory | /workspace/22.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/22.xbar_error_and_unmapped_addr.1354928423 |
| Short name | T2258 |
| Test name | |
| Test status | |
| Simulation time | 896362578 ps |
| CPU time | 41.02 seconds |
| Started | Jun 29 08:17:53 PM PDT 24 |
| Finished | Jun 29 08:18:34 PM PDT 24 |
| Peak memory | 573948 kb |
| Host | smart-55a0b30a-2610-4679-a48a-f7fc385c0c08 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1354928423 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.xbar_error_and_unmapped_add r.1354928423 |
| Directory | /workspace/22.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/22.xbar_error_random.775044480 |
| Short name | T2809 |
| Test name | |
| Test status | |
| Simulation time | 747248816 ps |
| CPU time | 29.39 seconds |
| Started | Jun 29 08:17:57 PM PDT 24 |
| Finished | Jun 29 08:18:26 PM PDT 24 |
| Peak memory | 573920 kb |
| Host | smart-4455d93f-f053-4e0c-8602-e84e9e333c0d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=775044480 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.xbar_error_random.775044480 |
| Directory | /workspace/22.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/22.xbar_random.3799516314 |
| Short name | T1928 |
| Test name | |
| Test status | |
| Simulation time | 2347082372 ps |
| CPU time | 94.76 seconds |
| Started | Jun 29 08:17:57 PM PDT 24 |
| Finished | Jun 29 08:19:32 PM PDT 24 |
| Peak memory | 575372 kb |
| Host | smart-2fdac782-ef05-4e15-9e18-07b273f28192 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3799516314 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.xbar_random.3799516314 |
| Directory | /workspace/22.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/22.xbar_random_large_delays.2588008167 |
| Short name | T2875 |
| Test name | |
| Test status | |
| Simulation time | 12715103052 ps |
| CPU time | 151.37 seconds |
| Started | Jun 29 08:17:54 PM PDT 24 |
| Finished | Jun 29 08:20:26 PM PDT 24 |
| Peak memory | 574380 kb |
| Host | smart-4ea521d0-a479-4824-ba93-5acad158797c |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2588008167 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.xbar_random_large_delays.2588008167 |
| Directory | /workspace/22.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/22.xbar_random_slow_rsp.3200272633 |
| Short name | T1882 |
| Test name | |
| Test status | |
| Simulation time | 58110687890 ps |
| CPU time | 971.6 seconds |
| Started | Jun 29 08:17:53 PM PDT 24 |
| Finished | Jun 29 08:34:05 PM PDT 24 |
| Peak memory | 575424 kb |
| Host | smart-75992e5d-9966-42e6-bf30-e7943f337256 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3200272633 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.xbar_random_slow_rsp.3200272633 |
| Directory | /workspace/22.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/22.xbar_random_zero_delays.323935961 |
| Short name | T1336 |
| Test name | |
| Test status | |
| Simulation time | 30272111 ps |
| CPU time | 6.51 seconds |
| Started | Jun 29 08:17:53 PM PDT 24 |
| Finished | Jun 29 08:18:00 PM PDT 24 |
| Peak memory | 574084 kb |
| Host | smart-86d39b95-e94c-4f67-993e-5b9919a500f1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=323935961 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.xbar_random_zero_dela ys.323935961 |
| Directory | /workspace/22.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/22.xbar_same_source.1432701791 |
| Short name | T2539 |
| Test name | |
| Test status | |
| Simulation time | 2703915435 ps |
| CPU time | 89.92 seconds |
| Started | Jun 29 08:17:56 PM PDT 24 |
| Finished | Jun 29 08:19:27 PM PDT 24 |
| Peak memory | 575360 kb |
| Host | smart-77b5058e-3e29-4d49-97d9-3021c0bea40e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1432701791 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.xbar_same_source.1432701791 |
| Directory | /workspace/22.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/22.xbar_smoke.474517112 |
| Short name | T1876 |
| Test name | |
| Test status | |
| Simulation time | 216146073 ps |
| CPU time | 10.42 seconds |
| Started | Jun 29 08:17:53 PM PDT 24 |
| Finished | Jun 29 08:18:04 PM PDT 24 |
| Peak memory | 574236 kb |
| Host | smart-c9eeb8bb-a380-433a-88ff-ef44614eaec8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=474517112 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.xbar_smoke.474517112 |
| Directory | /workspace/22.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/22.xbar_smoke_large_delays.157332961 |
| Short name | T1286 |
| Test name | |
| Test status | |
| Simulation time | 7935244479 ps |
| CPU time | 82.01 seconds |
| Started | Jun 29 08:17:54 PM PDT 24 |
| Finished | Jun 29 08:19:17 PM PDT 24 |
| Peak memory | 566092 kb |
| Host | smart-6a6fd8f3-4f39-4ced-a1f1-c8cc6ea0faba |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=157332961 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.xbar_smoke_large_delays.157332961 |
| Directory | /workspace/22.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/22.xbar_smoke_slow_rsp.3584077126 |
| Short name | T2022 |
| Test name | |
| Test status | |
| Simulation time | 4825238335 ps |
| CPU time | 80.11 seconds |
| Started | Jun 29 08:17:56 PM PDT 24 |
| Finished | Jun 29 08:19:17 PM PDT 24 |
| Peak memory | 574340 kb |
| Host | smart-9a20ccbf-caf9-4156-91a4-f1ff46f952c9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3584077126 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.xbar_smoke_slow_rsp.3584077126 |
| Directory | /workspace/22.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/22.xbar_smoke_zero_delays.3613415925 |
| Short name | T2245 |
| Test name | |
| Test status | |
| Simulation time | 47570637 ps |
| CPU time | 6.51 seconds |
| Started | Jun 29 08:17:53 PM PDT 24 |
| Finished | Jun 29 08:18:00 PM PDT 24 |
| Peak memory | 574224 kb |
| Host | smart-8aac6e95-39fa-4d2f-9a90-c1611f01e16d |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3613415925 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.xbar_smoke_zero_delay s.3613415925 |
| Directory | /workspace/22.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/22.xbar_stress_all.1962771778 |
| Short name | T1784 |
| Test name | |
| Test status | |
| Simulation time | 4211780062 ps |
| CPU time | 197.54 seconds |
| Started | Jun 29 08:18:01 PM PDT 24 |
| Finished | Jun 29 08:21:19 PM PDT 24 |
| Peak memory | 574464 kb |
| Host | smart-aad113b6-2086-4390-8375-b81713721ce7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1962771778 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.xbar_stress_all.1962771778 |
| Directory | /workspace/22.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/22.xbar_stress_all_with_error.1954315521 |
| Short name | T1931 |
| Test name | |
| Test status | |
| Simulation time | 4375643329 ps |
| CPU time | 162.76 seconds |
| Started | Jun 29 08:18:01 PM PDT 24 |
| Finished | Jun 29 08:20:44 PM PDT 24 |
| Peak memory | 574484 kb |
| Host | smart-3d5827bc-6158-4e03-82ad-2b77e25b7619 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1954315521 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.xbar_stress_all_with_error.1954315521 |
| Directory | /workspace/22.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/22.xbar_stress_all_with_rand_reset.3001073348 |
| Short name | T2750 |
| Test name | |
| Test status | |
| Simulation time | 312866856 ps |
| CPU time | 144.41 seconds |
| Started | Jun 29 08:18:00 PM PDT 24 |
| Finished | Jun 29 08:20:24 PM PDT 24 |
| Peak memory | 576440 kb |
| Host | smart-ae06f201-61ad-4ae8-96b2-eec27bd62cc8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3001073348 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.xbar_stress_all _with_rand_reset.3001073348 |
| Directory | /workspace/22.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/22.xbar_stress_all_with_reset_error.2484128747 |
| Short name | T1741 |
| Test name | |
| Test status | |
| Simulation time | 672334665 ps |
| CPU time | 268.64 seconds |
| Started | Jun 29 08:18:02 PM PDT 24 |
| Finished | Jun 29 08:22:31 PM PDT 24 |
| Peak memory | 574672 kb |
| Host | smart-2d55c598-c60b-40ab-a8db-653b9cc03218 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2484128747 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.xbar_stress_al l_with_reset_error.2484128747 |
| Directory | /workspace/22.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/22.xbar_unmapped_addr.302056652 |
| Short name | T1839 |
| Test name | |
| Test status | |
| Simulation time | 73713368 ps |
| CPU time | 14 seconds |
| Started | Jun 29 08:17:54 PM PDT 24 |
| Finished | Jun 29 08:18:09 PM PDT 24 |
| Peak memory | 575336 kb |
| Host | smart-e3131d8e-1b9c-4176-8bc2-b1753e4625f1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=302056652 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.xbar_unmapped_addr.302056652 |
| Directory | /workspace/22.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/23.chip_tl_errors.1014149868 |
| Short name | T536 |
| Test name | |
| Test status | |
| Simulation time | 3271195100 ps |
| CPU time | 168.48 seconds |
| Started | Jun 29 08:18:03 PM PDT 24 |
| Finished | Jun 29 08:20:52 PM PDT 24 |
| Peak memory | 597512 kb |
| Host | smart-ebb9ec17-63da-4123-87a7-f83b5360653e |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1014149868 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.chip_tl_errors.1014149868 |
| Directory | /workspace/23.chip_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/23.xbar_access_same_device.1181016280 |
| Short name | T1872 |
| Test name | |
| Test status | |
| Simulation time | 1785431857 ps |
| CPU time | 96.19 seconds |
| Started | Jun 29 08:18:09 PM PDT 24 |
| Finished | Jun 29 08:19:45 PM PDT 24 |
| Peak memory | 575404 kb |
| Host | smart-61ed154f-7c93-4c14-98b4-9760c19fa9d2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1181016280 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.xbar_access_same_device .1181016280 |
| Directory | /workspace/23.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/23.xbar_access_same_device_slow_rsp.273360833 |
| Short name | T2120 |
| Test name | |
| Test status | |
| Simulation time | 19595038745 ps |
| CPU time | 359.83 seconds |
| Started | Jun 29 08:18:09 PM PDT 24 |
| Finished | Jun 29 08:24:09 PM PDT 24 |
| Peak memory | 575416 kb |
| Host | smart-279188ea-8b7b-4e32-920c-194e7db69368 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=273360833 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.xbar_access_same_d evice_slow_rsp.273360833 |
| Directory | /workspace/23.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/23.xbar_error_and_unmapped_addr.800175957 |
| Short name | T2813 |
| Test name | |
| Test status | |
| Simulation time | 135766026 ps |
| CPU time | 9.09 seconds |
| Started | Jun 29 08:18:18 PM PDT 24 |
| Finished | Jun 29 08:18:27 PM PDT 24 |
| Peak memory | 574256 kb |
| Host | smart-56fbb6f2-e602-43fa-9f72-c72c45bca2dc |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=800175957 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.xbar_error_and_unmapped_addr .800175957 |
| Directory | /workspace/23.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/23.xbar_error_random.3201302793 |
| Short name | T1791 |
| Test name | |
| Test status | |
| Simulation time | 186217236 ps |
| CPU time | 18.44 seconds |
| Started | Jun 29 08:18:10 PM PDT 24 |
| Finished | Jun 29 08:18:29 PM PDT 24 |
| Peak memory | 573932 kb |
| Host | smart-a1de48ea-7a5d-4b69-b86f-9b0bcd600dca |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3201302793 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.xbar_error_random.3201302793 |
| Directory | /workspace/23.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/23.xbar_random.2710988171 |
| Short name | T1959 |
| Test name | |
| Test status | |
| Simulation time | 770818447 ps |
| CPU time | 32.64 seconds |
| Started | Jun 29 08:18:10 PM PDT 24 |
| Finished | Jun 29 08:18:43 PM PDT 24 |
| Peak memory | 575308 kb |
| Host | smart-bd1f3b2f-9100-4916-81f2-b46a1acedf89 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2710988171 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.xbar_random.2710988171 |
| Directory | /workspace/23.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/23.xbar_random_large_delays.2062583533 |
| Short name | T2444 |
| Test name | |
| Test status | |
| Simulation time | 32707950628 ps |
| CPU time | 363.82 seconds |
| Started | Jun 29 08:18:12 PM PDT 24 |
| Finished | Jun 29 08:24:17 PM PDT 24 |
| Peak memory | 575396 kb |
| Host | smart-02564f6a-3d3d-4170-b664-d8f19c55dbf5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2062583533 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.xbar_random_large_delays.2062583533 |
| Directory | /workspace/23.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/23.xbar_random_slow_rsp.29999377 |
| Short name | T2555 |
| Test name | |
| Test status | |
| Simulation time | 45759797102 ps |
| CPU time | 777.33 seconds |
| Started | Jun 29 08:18:09 PM PDT 24 |
| Finished | Jun 29 08:31:07 PM PDT 24 |
| Peak memory | 575412 kb |
| Host | smart-caa905f2-daa8-4003-9eb8-5c30df1d051d |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29999377 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.xbar_random_slow_rsp.29999377 |
| Directory | /workspace/23.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/23.xbar_random_zero_delays.3881213447 |
| Short name | T1855 |
| Test name | |
| Test status | |
| Simulation time | 461548697 ps |
| CPU time | 41.95 seconds |
| Started | Jun 29 08:18:09 PM PDT 24 |
| Finished | Jun 29 08:18:51 PM PDT 24 |
| Peak memory | 575292 kb |
| Host | smart-e7476106-4abc-4c6a-88a8-33e46920e9b6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3881213447 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.xbar_random_zero_del ays.3881213447 |
| Directory | /workspace/23.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/23.xbar_same_source.2703319217 |
| Short name | T619 |
| Test name | |
| Test status | |
| Simulation time | 561825470 ps |
| CPU time | 46.64 seconds |
| Started | Jun 29 08:18:09 PM PDT 24 |
| Finished | Jun 29 08:18:56 PM PDT 24 |
| Peak memory | 574232 kb |
| Host | smart-dca6382e-4b7e-426d-9a46-0616462e6f25 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2703319217 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.xbar_same_source.2703319217 |
| Directory | /workspace/23.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/23.xbar_smoke.1853279727 |
| Short name | T2121 |
| Test name | |
| Test status | |
| Simulation time | 44762593 ps |
| CPU time | 6.75 seconds |
| Started | Jun 29 08:18:03 PM PDT 24 |
| Finished | Jun 29 08:18:10 PM PDT 24 |
| Peak memory | 574256 kb |
| Host | smart-20256dcc-0acb-4277-9b21-334bfbe773a4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1853279727 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.xbar_smoke.1853279727 |
| Directory | /workspace/23.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/23.xbar_smoke_large_delays.2535044521 |
| Short name | T2669 |
| Test name | |
| Test status | |
| Simulation time | 7197124028 ps |
| CPU time | 79.1 seconds |
| Started | Jun 29 08:17:59 PM PDT 24 |
| Finished | Jun 29 08:19:19 PM PDT 24 |
| Peak memory | 566084 kb |
| Host | smart-008a1782-ee8b-4091-9d1c-fa908de5c643 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2535044521 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.xbar_smoke_large_delays.2535044521 |
| Directory | /workspace/23.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/23.xbar_smoke_slow_rsp.2703847163 |
| Short name | T1521 |
| Test name | |
| Test status | |
| Simulation time | 5000989786 ps |
| CPU time | 86.81 seconds |
| Started | Jun 29 08:18:09 PM PDT 24 |
| Finished | Jun 29 08:19:36 PM PDT 24 |
| Peak memory | 566076 kb |
| Host | smart-4701e4fa-73fc-4ff4-922c-51c7964217f2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2703847163 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.xbar_smoke_slow_rsp.2703847163 |
| Directory | /workspace/23.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/23.xbar_smoke_zero_delays.2200353801 |
| Short name | T1642 |
| Test name | |
| Test status | |
| Simulation time | 49185069 ps |
| CPU time | 7.14 seconds |
| Started | Jun 29 08:18:01 PM PDT 24 |
| Finished | Jun 29 08:18:08 PM PDT 24 |
| Peak memory | 565956 kb |
| Host | smart-a9ab813b-a4a1-427c-b47f-118f41e49f8f |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2200353801 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.xbar_smoke_zero_delay s.2200353801 |
| Directory | /workspace/23.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/23.xbar_stress_all.2528375431 |
| Short name | T1850 |
| Test name | |
| Test status | |
| Simulation time | 12295329414 ps |
| CPU time | 514.07 seconds |
| Started | Jun 29 08:18:17 PM PDT 24 |
| Finished | Jun 29 08:26:51 PM PDT 24 |
| Peak memory | 575524 kb |
| Host | smart-cd0f5282-e1b3-42a6-9268-9d8b1bd7b9a1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2528375431 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.xbar_stress_all.2528375431 |
| Directory | /workspace/23.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/23.xbar_stress_all_with_error.1300639510 |
| Short name | T2559 |
| Test name | |
| Test status | |
| Simulation time | 3528845300 ps |
| CPU time | 252.54 seconds |
| Started | Jun 29 08:18:21 PM PDT 24 |
| Finished | Jun 29 08:22:34 PM PDT 24 |
| Peak memory | 574668 kb |
| Host | smart-93e9a897-4ded-46ca-9169-cef224e6230b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1300639510 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.xbar_stress_all_with_error.1300639510 |
| Directory | /workspace/23.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/23.xbar_stress_all_with_rand_reset.880802564 |
| Short name | T2503 |
| Test name | |
| Test status | |
| Simulation time | 1273877935 ps |
| CPU time | 276.54 seconds |
| Started | Jun 29 08:18:17 PM PDT 24 |
| Finished | Jun 29 08:22:54 PM PDT 24 |
| Peak memory | 574396 kb |
| Host | smart-d5e139f0-ee03-49d3-bdec-01bfca581ec5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=880802564 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_res et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.xbar_stress_all_ with_rand_reset.880802564 |
| Directory | /workspace/23.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/23.xbar_stress_all_with_reset_error.3882450708 |
| Short name | T2184 |
| Test name | |
| Test status | |
| Simulation time | 6773054433 ps |
| CPU time | 353.07 seconds |
| Started | Jun 29 08:18:22 PM PDT 24 |
| Finished | Jun 29 08:24:15 PM PDT 24 |
| Peak memory | 576508 kb |
| Host | smart-de1943c2-ec27-4e94-8f90-517ccfa65239 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3882450708 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.xbar_stress_al l_with_reset_error.3882450708 |
| Directory | /workspace/23.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/23.xbar_unmapped_addr.655235633 |
| Short name | T1833 |
| Test name | |
| Test status | |
| Simulation time | 217629042 ps |
| CPU time | 29.37 seconds |
| Started | Jun 29 08:18:10 PM PDT 24 |
| Finished | Jun 29 08:18:40 PM PDT 24 |
| Peak memory | 575360 kb |
| Host | smart-7345f0c8-12c6-4ce1-b968-1133fc120357 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=655235633 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.xbar_unmapped_addr.655235633 |
| Directory | /workspace/23.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/24.chip_tl_errors.3995824183 |
| Short name | T550 |
| Test name | |
| Test status | |
| Simulation time | 4051605821 ps |
| CPU time | 319.89 seconds |
| Started | Jun 29 08:18:17 PM PDT 24 |
| Finished | Jun 29 08:23:37 PM PDT 24 |
| Peak memory | 597516 kb |
| Host | smart-384f9ed0-2be4-49bf-b5c5-fa71bd48d85f |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3995824183 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.chip_tl_errors.3995824183 |
| Directory | /workspace/24.chip_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/24.xbar_access_same_device.3109685163 |
| Short name | T1879 |
| Test name | |
| Test status | |
| Simulation time | 353027040 ps |
| CPU time | 21.81 seconds |
| Started | Jun 29 08:18:30 PM PDT 24 |
| Finished | Jun 29 08:18:52 PM PDT 24 |
| Peak memory | 574372 kb |
| Host | smart-8ef77629-4a3d-405e-9ab1-c4ab2eddcbab |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3109685163 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.xbar_access_same_device .3109685163 |
| Directory | /workspace/24.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/24.xbar_access_same_device_slow_rsp.3733824975 |
| Short name | T2679 |
| Test name | |
| Test status | |
| Simulation time | 95644634268 ps |
| CPU time | 1712.35 seconds |
| Started | Jun 29 08:18:26 PM PDT 24 |
| Finished | Jun 29 08:46:59 PM PDT 24 |
| Peak memory | 575424 kb |
| Host | smart-e801b97a-766b-4bf9-b88f-ed2a708cee5a |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3733824975 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.xbar_access_same_ device_slow_rsp.3733824975 |
| Directory | /workspace/24.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/24.xbar_error_and_unmapped_addr.3123427798 |
| Short name | T1944 |
| Test name | |
| Test status | |
| Simulation time | 428643338 ps |
| CPU time | 19.56 seconds |
| Started | Jun 29 08:18:30 PM PDT 24 |
| Finished | Jun 29 08:18:50 PM PDT 24 |
| Peak memory | 573940 kb |
| Host | smart-cecec648-e89c-4818-8d0c-ba43dfc788fb |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3123427798 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.xbar_error_and_unmapped_add r.3123427798 |
| Directory | /workspace/24.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/24.xbar_error_random.409479306 |
| Short name | T1533 |
| Test name | |
| Test status | |
| Simulation time | 2374817082 ps |
| CPU time | 96.74 seconds |
| Started | Jun 29 08:18:26 PM PDT 24 |
| Finished | Jun 29 08:20:03 PM PDT 24 |
| Peak memory | 574556 kb |
| Host | smart-ff60d09d-9082-424a-8c5e-dec50b4e200a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=409479306 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.xbar_error_random.409479306 |
| Directory | /workspace/24.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/24.xbar_random.3982754538 |
| Short name | T621 |
| Test name | |
| Test status | |
| Simulation time | 2579390843 ps |
| CPU time | 107.35 seconds |
| Started | Jun 29 08:18:20 PM PDT 24 |
| Finished | Jun 29 08:20:08 PM PDT 24 |
| Peak memory | 575308 kb |
| Host | smart-bae37425-55f5-43a5-acd0-fcd5dc118ea8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3982754538 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.xbar_random.3982754538 |
| Directory | /workspace/24.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/24.xbar_random_large_delays.1256530586 |
| Short name | T2560 |
| Test name | |
| Test status | |
| Simulation time | 25034853744 ps |
| CPU time | 278.72 seconds |
| Started | Jun 29 08:18:27 PM PDT 24 |
| Finished | Jun 29 08:23:07 PM PDT 24 |
| Peak memory | 574312 kb |
| Host | smart-ce8d184b-63aa-4131-a945-0e56fc5c24b7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1256530586 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.xbar_random_large_delays.1256530586 |
| Directory | /workspace/24.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/24.xbar_random_slow_rsp.4024995604 |
| Short name | T2008 |
| Test name | |
| Test status | |
| Simulation time | 12636567813 ps |
| CPU time | 221.63 seconds |
| Started | Jun 29 08:18:29 PM PDT 24 |
| Finished | Jun 29 08:22:11 PM PDT 24 |
| Peak memory | 575396 kb |
| Host | smart-95b304c1-cbaf-4a0b-a8cf-dbc90337cd08 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4024995604 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.xbar_random_slow_rsp.4024995604 |
| Directory | /workspace/24.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/24.xbar_random_zero_delays.3044972982 |
| Short name | T2475 |
| Test name | |
| Test status | |
| Simulation time | 138909014 ps |
| CPU time | 16.27 seconds |
| Started | Jun 29 08:18:27 PM PDT 24 |
| Finished | Jun 29 08:18:43 PM PDT 24 |
| Peak memory | 575312 kb |
| Host | smart-3fe13579-5c15-4309-a782-dd92e51bd5c8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3044972982 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.xbar_random_zero_del ays.3044972982 |
| Directory | /workspace/24.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/24.xbar_same_source.2526562874 |
| Short name | T1326 |
| Test name | |
| Test status | |
| Simulation time | 40707594 ps |
| CPU time | 6.62 seconds |
| Started | Jun 29 08:18:28 PM PDT 24 |
| Finished | Jun 29 08:18:35 PM PDT 24 |
| Peak memory | 574140 kb |
| Host | smart-4d328c27-a65e-4b8d-b15a-63a3672e4862 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2526562874 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.xbar_same_source.2526562874 |
| Directory | /workspace/24.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/24.xbar_smoke.3478206009 |
| Short name | T2554 |
| Test name | |
| Test status | |
| Simulation time | 50272840 ps |
| CPU time | 6.78 seconds |
| Started | Jun 29 08:18:17 PM PDT 24 |
| Finished | Jun 29 08:18:24 PM PDT 24 |
| Peak memory | 566020 kb |
| Host | smart-c6d3783b-8bbd-4b1f-a2a7-ae23dd2b0f28 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3478206009 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.xbar_smoke.3478206009 |
| Directory | /workspace/24.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/24.xbar_smoke_large_delays.3440213486 |
| Short name | T1651 |
| Test name | |
| Test status | |
| Simulation time | 8794396374 ps |
| CPU time | 92.98 seconds |
| Started | Jun 29 08:18:21 PM PDT 24 |
| Finished | Jun 29 08:19:55 PM PDT 24 |
| Peak memory | 574328 kb |
| Host | smart-a95f004b-23aa-412e-a19a-d83954bb2857 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3440213486 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.xbar_smoke_large_delays.3440213486 |
| Directory | /workspace/24.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/24.xbar_smoke_slow_rsp.3124196185 |
| Short name | T1355 |
| Test name | |
| Test status | |
| Simulation time | 3854282574 ps |
| CPU time | 72.14 seconds |
| Started | Jun 29 08:18:17 PM PDT 24 |
| Finished | Jun 29 08:19:30 PM PDT 24 |
| Peak memory | 574204 kb |
| Host | smart-2b2a7606-e59e-4602-a59e-f2e5c1fd6ef5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3124196185 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.xbar_smoke_slow_rsp.3124196185 |
| Directory | /workspace/24.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/24.xbar_smoke_zero_delays.329718868 |
| Short name | T1755 |
| Test name | |
| Test status | |
| Simulation time | 48493990 ps |
| CPU time | 7.1 seconds |
| Started | Jun 29 08:18:20 PM PDT 24 |
| Finished | Jun 29 08:18:27 PM PDT 24 |
| Peak memory | 574248 kb |
| Host | smart-0adea63d-94fc-4c95-a720-40ddcec9e436 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=329718868 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.xbar_smoke_zero_delays .329718868 |
| Directory | /workspace/24.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/24.xbar_stress_all.2223948769 |
| Short name | T1949 |
| Test name | |
| Test status | |
| Simulation time | 1783242780 ps |
| CPU time | 180 seconds |
| Started | Jun 29 08:18:27 PM PDT 24 |
| Finished | Jun 29 08:21:28 PM PDT 24 |
| Peak memory | 575432 kb |
| Host | smart-1baafb82-c672-4212-9a60-e9b4581db598 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2223948769 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.xbar_stress_all.2223948769 |
| Directory | /workspace/24.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/24.xbar_stress_all_with_rand_reset.1541151766 |
| Short name | T1543 |
| Test name | |
| Test status | |
| Simulation time | 194371904 ps |
| CPU time | 147.59 seconds |
| Started | Jun 29 08:18:29 PM PDT 24 |
| Finished | Jun 29 08:20:57 PM PDT 24 |
| Peak memory | 575452 kb |
| Host | smart-8f86e0e2-ef13-4ace-a883-6b8cee82fab9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1541151766 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.xbar_stress_all _with_rand_reset.1541151766 |
| Directory | /workspace/24.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/24.xbar_stress_all_with_reset_error.3474372759 |
| Short name | T1587 |
| Test name | |
| Test status | |
| Simulation time | 8148008231 ps |
| CPU time | 897.92 seconds |
| Started | Jun 29 08:18:27 PM PDT 24 |
| Finished | Jun 29 08:33:26 PM PDT 24 |
| Peak memory | 574476 kb |
| Host | smart-81c8b441-6924-4a15-8a1c-acfe5f04bb65 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3474372759 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.xbar_stress_al l_with_reset_error.3474372759 |
| Directory | /workspace/24.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/24.xbar_unmapped_addr.1062993385 |
| Short name | T1584 |
| Test name | |
| Test status | |
| Simulation time | 91087549 ps |
| CPU time | 14.91 seconds |
| Started | Jun 29 08:18:30 PM PDT 24 |
| Finished | Jun 29 08:18:45 PM PDT 24 |
| Peak memory | 574288 kb |
| Host | smart-bcaf6332-fcd9-4a3f-8550-3ed4f1dea948 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1062993385 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.xbar_unmapped_addr.1062993385 |
| Directory | /workspace/24.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/25.chip_tl_errors.3371073325 |
| Short name | T561 |
| Test name | |
| Test status | |
| Simulation time | 3363296124 ps |
| CPU time | 246.67 seconds |
| Started | Jun 29 08:18:37 PM PDT 24 |
| Finished | Jun 29 08:22:44 PM PDT 24 |
| Peak memory | 597516 kb |
| Host | smart-e1e77247-71c3-4180-9b47-084700481c18 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3371073325 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.chip_tl_errors.3371073325 |
| Directory | /workspace/25.chip_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/25.xbar_access_same_device.3455187439 |
| Short name | T2544 |
| Test name | |
| Test status | |
| Simulation time | 2974225196 ps |
| CPU time | 136.2 seconds |
| Started | Jun 29 08:18:36 PM PDT 24 |
| Finished | Jun 29 08:20:52 PM PDT 24 |
| Peak memory | 575424 kb |
| Host | smart-1c5921b7-d5c7-419a-a205-5eb785e64bb1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3455187439 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.xbar_access_same_device .3455187439 |
| Directory | /workspace/25.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/25.xbar_access_same_device_slow_rsp.1016247885 |
| Short name | T2691 |
| Test name | |
| Test status | |
| Simulation time | 37146469781 ps |
| CPU time | 671.09 seconds |
| Started | Jun 29 08:18:35 PM PDT 24 |
| Finished | Jun 29 08:29:47 PM PDT 24 |
| Peak memory | 575452 kb |
| Host | smart-192740ef-6bf1-47ae-b9bb-30a6e5a95bfe |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1016247885 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.xbar_access_same_ device_slow_rsp.1016247885 |
| Directory | /workspace/25.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/25.xbar_error_and_unmapped_addr.2217623550 |
| Short name | T2127 |
| Test name | |
| Test status | |
| Simulation time | 1122402208 ps |
| CPU time | 49.23 seconds |
| Started | Jun 29 08:18:44 PM PDT 24 |
| Finished | Jun 29 08:19:33 PM PDT 24 |
| Peak memory | 573880 kb |
| Host | smart-5fe0f33a-f9ef-4097-9ad1-ae3b3c1db59a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2217623550 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.xbar_error_and_unmapped_add r.2217623550 |
| Directory | /workspace/25.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/25.xbar_error_random.354450884 |
| Short name | T1503 |
| Test name | |
| Test status | |
| Simulation time | 1774485592 ps |
| CPU time | 63.86 seconds |
| Started | Jun 29 08:18:39 PM PDT 24 |
| Finished | Jun 29 08:19:44 PM PDT 24 |
| Peak memory | 574524 kb |
| Host | smart-818877bd-f778-4058-b082-5c4a831e17e3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=354450884 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.xbar_error_random.354450884 |
| Directory | /workspace/25.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/25.xbar_random.2553400561 |
| Short name | T2313 |
| Test name | |
| Test status | |
| Simulation time | 2603649369 ps |
| CPU time | 97.15 seconds |
| Started | Jun 29 08:18:36 PM PDT 24 |
| Finished | Jun 29 08:20:13 PM PDT 24 |
| Peak memory | 574324 kb |
| Host | smart-e27d5764-bece-49cc-a655-2226eaeb093a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2553400561 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.xbar_random.2553400561 |
| Directory | /workspace/25.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/25.xbar_random_large_delays.2090860673 |
| Short name | T1485 |
| Test name | |
| Test status | |
| Simulation time | 41959029990 ps |
| CPU time | 438.06 seconds |
| Started | Jun 29 08:18:36 PM PDT 24 |
| Finished | Jun 29 08:25:54 PM PDT 24 |
| Peak memory | 574320 kb |
| Host | smart-139f4b0a-1846-449c-b5e5-349e40a11a0c |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2090860673 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.xbar_random_large_delays.2090860673 |
| Directory | /workspace/25.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/25.xbar_random_slow_rsp.3361962229 |
| Short name | T469 |
| Test name | |
| Test status | |
| Simulation time | 71118557832 ps |
| CPU time | 1240.34 seconds |
| Started | Jun 29 08:18:36 PM PDT 24 |
| Finished | Jun 29 08:39:17 PM PDT 24 |
| Peak memory | 575400 kb |
| Host | smart-5557c3e8-8822-4eff-841c-8d0dc2a7c16b |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3361962229 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.xbar_random_slow_rsp.3361962229 |
| Directory | /workspace/25.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/25.xbar_random_zero_delays.2400420419 |
| Short name | T2165 |
| Test name | |
| Test status | |
| Simulation time | 599553332 ps |
| CPU time | 55.72 seconds |
| Started | Jun 29 08:18:38 PM PDT 24 |
| Finished | Jun 29 08:19:34 PM PDT 24 |
| Peak memory | 575276 kb |
| Host | smart-eb86cfa0-7872-4372-801f-9d77f33a0271 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2400420419 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.xbar_random_zero_del ays.2400420419 |
| Directory | /workspace/25.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/25.xbar_same_source.2234884717 |
| Short name | T2842 |
| Test name | |
| Test status | |
| Simulation time | 2258889923 ps |
| CPU time | 74.42 seconds |
| Started | Jun 29 08:18:34 PM PDT 24 |
| Finished | Jun 29 08:19:49 PM PDT 24 |
| Peak memory | 575364 kb |
| Host | smart-3eef6088-bedf-4518-a75d-02cea0a11629 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2234884717 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.xbar_same_source.2234884717 |
| Directory | /workspace/25.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/25.xbar_smoke.1950017283 |
| Short name | T2545 |
| Test name | |
| Test status | |
| Simulation time | 47280923 ps |
| CPU time | 6.77 seconds |
| Started | Jun 29 08:18:35 PM PDT 24 |
| Finished | Jun 29 08:18:42 PM PDT 24 |
| Peak memory | 566020 kb |
| Host | smart-164e1aba-385e-406c-8e25-6063c3233451 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1950017283 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.xbar_smoke.1950017283 |
| Directory | /workspace/25.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/25.xbar_smoke_large_delays.3383150130 |
| Short name | T1513 |
| Test name | |
| Test status | |
| Simulation time | 9643327152 ps |
| CPU time | 103.51 seconds |
| Started | Jun 29 08:18:34 PM PDT 24 |
| Finished | Jun 29 08:20:17 PM PDT 24 |
| Peak memory | 574328 kb |
| Host | smart-1a44bc0f-0332-444c-8de6-a9e5e5dd8e3c |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3383150130 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.xbar_smoke_large_delays.3383150130 |
| Directory | /workspace/25.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/25.xbar_smoke_slow_rsp.3682244467 |
| Short name | T1837 |
| Test name | |
| Test status | |
| Simulation time | 4085600454 ps |
| CPU time | 70.93 seconds |
| Started | Jun 29 08:18:39 PM PDT 24 |
| Finished | Jun 29 08:19:50 PM PDT 24 |
| Peak memory | 574220 kb |
| Host | smart-006606a9-1de1-4d5c-ab93-618f240f7fc7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3682244467 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.xbar_smoke_slow_rsp.3682244467 |
| Directory | /workspace/25.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/25.xbar_smoke_zero_delays.816876846 |
| Short name | T2396 |
| Test name | |
| Test status | |
| Simulation time | 48076174 ps |
| CPU time | 6.34 seconds |
| Started | Jun 29 08:18:37 PM PDT 24 |
| Finished | Jun 29 08:18:44 PM PDT 24 |
| Peak memory | 565980 kb |
| Host | smart-55148dae-1382-40f3-a47c-7e0879673c6c |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=816876846 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.xbar_smoke_zero_delays .816876846 |
| Directory | /workspace/25.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/25.xbar_stress_all_with_error.2561534964 |
| Short name | T1612 |
| Test name | |
| Test status | |
| Simulation time | 2015605000 ps |
| CPU time | 174.92 seconds |
| Started | Jun 29 08:18:43 PM PDT 24 |
| Finished | Jun 29 08:21:39 PM PDT 24 |
| Peak memory | 574404 kb |
| Host | smart-9ac8d549-984e-489b-9bfa-e5007b0f37c1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2561534964 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.xbar_stress_all_with_error.2561534964 |
| Directory | /workspace/25.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/25.xbar_stress_all_with_reset_error.718971910 |
| Short name | T1559 |
| Test name | |
| Test status | |
| Simulation time | 325527185 ps |
| CPU time | 62.88 seconds |
| Started | Jun 29 08:18:44 PM PDT 24 |
| Finished | Jun 29 08:19:47 PM PDT 24 |
| Peak memory | 574656 kb |
| Host | smart-e3a0d4f6-4602-47c1-bb16-f8ce3dcf162f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=718971910 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.xbar_stress_all _with_reset_error.718971910 |
| Directory | /workspace/25.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/25.xbar_unmapped_addr.3088423372 |
| Short name | T1504 |
| Test name | |
| Test status | |
| Simulation time | 1000656120 ps |
| CPU time | 45.67 seconds |
| Started | Jun 29 08:18:36 PM PDT 24 |
| Finished | Jun 29 08:19:22 PM PDT 24 |
| Peak memory | 574292 kb |
| Host | smart-ec1eb951-cb1f-4244-89f8-913f0214628b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3088423372 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.xbar_unmapped_addr.3088423372 |
| Directory | /workspace/25.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/26.chip_tl_errors.3948127559 |
| Short name | T2730 |
| Test name | |
| Test status | |
| Simulation time | 3496323722 ps |
| CPU time | 247.32 seconds |
| Started | Jun 29 08:18:43 PM PDT 24 |
| Finished | Jun 29 08:22:51 PM PDT 24 |
| Peak memory | 603576 kb |
| Host | smart-36927c39-5f9c-4f4a-ac5e-93e1fd4d0f15 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3948127559 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.chip_tl_errors.3948127559 |
| Directory | /workspace/26.chip_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/26.xbar_access_same_device.2356004497 |
| Short name | T782 |
| Test name | |
| Test status | |
| Simulation time | 65392203 ps |
| CPU time | 8.53 seconds |
| Started | Jun 29 08:18:55 PM PDT 24 |
| Finished | Jun 29 08:19:04 PM PDT 24 |
| Peak memory | 574120 kb |
| Host | smart-c728f729-996d-47a1-84be-254c56a941ff |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2356004497 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.xbar_access_same_device .2356004497 |
| Directory | /workspace/26.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/26.xbar_access_same_device_slow_rsp.1067021068 |
| Short name | T2640 |
| Test name | |
| Test status | |
| Simulation time | 53342978836 ps |
| CPU time | 1044.52 seconds |
| Started | Jun 29 08:18:54 PM PDT 24 |
| Finished | Jun 29 08:36:19 PM PDT 24 |
| Peak memory | 575392 kb |
| Host | smart-79b83f06-57f9-4b80-9e71-2422c140f646 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1067021068 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.xbar_access_same_ device_slow_rsp.1067021068 |
| Directory | /workspace/26.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/26.xbar_error_and_unmapped_addr.1895873566 |
| Short name | T1311 |
| Test name | |
| Test status | |
| Simulation time | 67268572 ps |
| CPU time | 9.68 seconds |
| Started | Jun 29 08:18:52 PM PDT 24 |
| Finished | Jun 29 08:19:03 PM PDT 24 |
| Peak memory | 573896 kb |
| Host | smart-f03980a0-f399-45c7-b74d-0f3f4be4fcdf |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1895873566 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.xbar_error_and_unmapped_add r.1895873566 |
| Directory | /workspace/26.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/26.xbar_error_random.2759948726 |
| Short name | T1939 |
| Test name | |
| Test status | |
| Simulation time | 753016628 ps |
| CPU time | 27.05 seconds |
| Started | Jun 29 08:18:54 PM PDT 24 |
| Finished | Jun 29 08:19:21 PM PDT 24 |
| Peak memory | 574264 kb |
| Host | smart-e2817c00-164b-40a4-9af2-dff8a95f2bb6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2759948726 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.xbar_error_random.2759948726 |
| Directory | /workspace/26.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/26.xbar_random.1927793855 |
| Short name | T2124 |
| Test name | |
| Test status | |
| Simulation time | 1866075237 ps |
| CPU time | 72.53 seconds |
| Started | Jun 29 08:18:44 PM PDT 24 |
| Finished | Jun 29 08:19:57 PM PDT 24 |
| Peak memory | 575320 kb |
| Host | smart-b7e55ad0-05fb-4373-8336-4c53ded1db90 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1927793855 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.xbar_random.1927793855 |
| Directory | /workspace/26.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/26.xbar_random_large_delays.2850265051 |
| Short name | T2447 |
| Test name | |
| Test status | |
| Simulation time | 108839957908 ps |
| CPU time | 1052.32 seconds |
| Started | Jun 29 08:18:53 PM PDT 24 |
| Finished | Jun 29 08:36:26 PM PDT 24 |
| Peak memory | 575412 kb |
| Host | smart-0b73ad8d-0cfd-448f-aecf-f4d7da84410e |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2850265051 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.xbar_random_large_delays.2850265051 |
| Directory | /workspace/26.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/26.xbar_random_slow_rsp.3605036572 |
| Short name | T2578 |
| Test name | |
| Test status | |
| Simulation time | 17596526506 ps |
| CPU time | 325.04 seconds |
| Started | Jun 29 08:18:53 PM PDT 24 |
| Finished | Jun 29 08:24:19 PM PDT 24 |
| Peak memory | 575384 kb |
| Host | smart-3d9d1da7-11c0-49a9-9e2c-0d3ad151158b |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3605036572 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.xbar_random_slow_rsp.3605036572 |
| Directory | /workspace/26.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/26.xbar_random_zero_delays.2860931218 |
| Short name | T1908 |
| Test name | |
| Test status | |
| Simulation time | 516039714 ps |
| CPU time | 43.7 seconds |
| Started | Jun 29 08:18:51 PM PDT 24 |
| Finished | Jun 29 08:19:35 PM PDT 24 |
| Peak memory | 574256 kb |
| Host | smart-0425193d-e6e0-44f7-9f14-7963a0d41c30 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2860931218 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.xbar_random_zero_del ays.2860931218 |
| Directory | /workspace/26.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/26.xbar_same_source.3195948902 |
| Short name | T604 |
| Test name | |
| Test status | |
| Simulation time | 175673862 ps |
| CPU time | 15.95 seconds |
| Started | Jun 29 08:18:52 PM PDT 24 |
| Finished | Jun 29 08:19:09 PM PDT 24 |
| Peak memory | 575300 kb |
| Host | smart-eb2af70c-ad2b-4968-b369-7ab363f4ca60 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3195948902 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.xbar_same_source.3195948902 |
| Directory | /workspace/26.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/26.xbar_smoke.3246920502 |
| Short name | T2816 |
| Test name | |
| Test status | |
| Simulation time | 268974137 ps |
| CPU time | 12.15 seconds |
| Started | Jun 29 08:18:45 PM PDT 24 |
| Finished | Jun 29 08:18:58 PM PDT 24 |
| Peak memory | 574196 kb |
| Host | smart-bb296a54-9c48-4bd6-9344-6ff369a4ea6b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3246920502 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.xbar_smoke.3246920502 |
| Directory | /workspace/26.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/26.xbar_smoke_large_delays.3113624519 |
| Short name | T1919 |
| Test name | |
| Test status | |
| Simulation time | 9057943241 ps |
| CPU time | 93.34 seconds |
| Started | Jun 29 08:18:44 PM PDT 24 |
| Finished | Jun 29 08:20:18 PM PDT 24 |
| Peak memory | 574316 kb |
| Host | smart-a536b92c-2f45-418b-9f91-cb47784d2f51 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3113624519 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.xbar_smoke_large_delays.3113624519 |
| Directory | /workspace/26.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/26.xbar_smoke_slow_rsp.668946540 |
| Short name | T2696 |
| Test name | |
| Test status | |
| Simulation time | 4734781890 ps |
| CPU time | 80.97 seconds |
| Started | Jun 29 08:18:44 PM PDT 24 |
| Finished | Jun 29 08:20:05 PM PDT 24 |
| Peak memory | 566084 kb |
| Host | smart-4ab49bc5-e396-42f2-bc32-60d56845db24 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=668946540 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.xbar_smoke_slow_rsp.668946540 |
| Directory | /workspace/26.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/26.xbar_smoke_zero_delays.1650259568 |
| Short name | T1641 |
| Test name | |
| Test status | |
| Simulation time | 49418939 ps |
| CPU time | 7.04 seconds |
| Started | Jun 29 08:18:42 PM PDT 24 |
| Finished | Jun 29 08:18:50 PM PDT 24 |
| Peak memory | 574256 kb |
| Host | smart-94394025-76d2-4383-bb8b-dfd229f24e16 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1650259568 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.xbar_smoke_zero_delay s.1650259568 |
| Directory | /workspace/26.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/26.xbar_stress_all.1411950349 |
| Short name | T2465 |
| Test name | |
| Test status | |
| Simulation time | 2884603782 ps |
| CPU time | 122.35 seconds |
| Started | Jun 29 08:18:55 PM PDT 24 |
| Finished | Jun 29 08:20:57 PM PDT 24 |
| Peak memory | 575476 kb |
| Host | smart-2eb111c0-24ac-4590-846d-83c9adf5702f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1411950349 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.xbar_stress_all.1411950349 |
| Directory | /workspace/26.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/26.xbar_stress_all_with_error.215574994 |
| Short name | T2834 |
| Test name | |
| Test status | |
| Simulation time | 4182863266 ps |
| CPU time | 320.23 seconds |
| Started | Jun 29 08:19:05 PM PDT 24 |
| Finished | Jun 29 08:24:26 PM PDT 24 |
| Peak memory | 574688 kb |
| Host | smart-31972959-16dc-4e6d-80b9-a0d0574056b9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=215574994 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.xbar_stress_all_with_error.215574994 |
| Directory | /workspace/26.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/26.xbar_stress_all_with_rand_reset.2268366408 |
| Short name | T823 |
| Test name | |
| Test status | |
| Simulation time | 2364988965 ps |
| CPU time | 252.88 seconds |
| Started | Jun 29 08:18:54 PM PDT 24 |
| Finished | Jun 29 08:23:08 PM PDT 24 |
| Peak memory | 575516 kb |
| Host | smart-7eba518f-03cb-4f02-bee5-8cd3514ae330 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2268366408 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.xbar_stress_all _with_rand_reset.2268366408 |
| Directory | /workspace/26.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/26.xbar_stress_all_with_reset_error.2753655617 |
| Short name | T806 |
| Test name | |
| Test status | |
| Simulation time | 154955712 ps |
| CPU time | 68.13 seconds |
| Started | Jun 29 08:19:07 PM PDT 24 |
| Finished | Jun 29 08:20:15 PM PDT 24 |
| Peak memory | 574648 kb |
| Host | smart-e8067c8e-2a82-4dbb-a7c5-0800636a949f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2753655617 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.xbar_stress_al l_with_reset_error.2753655617 |
| Directory | /workspace/26.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/26.xbar_unmapped_addr.1048432627 |
| Short name | T2070 |
| Test name | |
| Test status | |
| Simulation time | 70809189 ps |
| CPU time | 11.04 seconds |
| Started | Jun 29 08:18:54 PM PDT 24 |
| Finished | Jun 29 08:19:06 PM PDT 24 |
| Peak memory | 575352 kb |
| Host | smart-05f8e0d9-285b-4425-9acc-a547e698875f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1048432627 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.xbar_unmapped_addr.1048432627 |
| Directory | /workspace/26.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/27.chip_tl_errors.3133813827 |
| Short name | T2556 |
| Test name | |
| Test status | |
| Simulation time | 4059144297 ps |
| CPU time | 302.46 seconds |
| Started | Jun 29 08:19:06 PM PDT 24 |
| Finished | Jun 29 08:24:09 PM PDT 24 |
| Peak memory | 597572 kb |
| Host | smart-b382ff72-7b29-49d1-b34e-1ddfbf9a8b26 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3133813827 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.chip_tl_errors.3133813827 |
| Directory | /workspace/27.chip_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/27.xbar_access_same_device.2255463720 |
| Short name | T587 |
| Test name | |
| Test status | |
| Simulation time | 212870926 ps |
| CPU time | 29.5 seconds |
| Started | Jun 29 08:19:10 PM PDT 24 |
| Finished | Jun 29 08:19:39 PM PDT 24 |
| Peak memory | 575300 kb |
| Host | smart-f1d213cb-7fa1-4a9e-b8a8-4cb1c4ec10b4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2255463720 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.xbar_access_same_device .2255463720 |
| Directory | /workspace/27.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/27.xbar_access_same_device_slow_rsp.2086872267 |
| Short name | T2412 |
| Test name | |
| Test status | |
| Simulation time | 56435788642 ps |
| CPU time | 956.62 seconds |
| Started | Jun 29 08:19:11 PM PDT 24 |
| Finished | Jun 29 08:35:08 PM PDT 24 |
| Peak memory | 575464 kb |
| Host | smart-bbbbbe25-1c0f-4de3-8a88-d14b48b9f4a4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2086872267 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.xbar_access_same_ device_slow_rsp.2086872267 |
| Directory | /workspace/27.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/27.xbar_error_and_unmapped_addr.1722146219 |
| Short name | T2076 |
| Test name | |
| Test status | |
| Simulation time | 108923532 ps |
| CPU time | 15.41 seconds |
| Started | Jun 29 08:19:12 PM PDT 24 |
| Finished | Jun 29 08:19:27 PM PDT 24 |
| Peak memory | 574468 kb |
| Host | smart-199fb0d6-c064-41e6-b6a9-62ba752f2c1e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1722146219 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.xbar_error_and_unmapped_add r.1722146219 |
| Directory | /workspace/27.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/27.xbar_error_random.2207688141 |
| Short name | T1493 |
| Test name | |
| Test status | |
| Simulation time | 1031832373 ps |
| CPU time | 40.63 seconds |
| Started | Jun 29 08:19:14 PM PDT 24 |
| Finished | Jun 29 08:19:55 PM PDT 24 |
| Peak memory | 573888 kb |
| Host | smart-f1d6c156-6d29-4181-95dc-4c79c699a2e3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2207688141 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.xbar_error_random.2207688141 |
| Directory | /workspace/27.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/27.xbar_random.4228842251 |
| Short name | T1775 |
| Test name | |
| Test status | |
| Simulation time | 419033926 ps |
| CPU time | 33.16 seconds |
| Started | Jun 29 08:19:05 PM PDT 24 |
| Finished | Jun 29 08:19:39 PM PDT 24 |
| Peak memory | 575280 kb |
| Host | smart-78866178-1c54-4f0e-81ce-48733946b8f7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4228842251 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.xbar_random.4228842251 |
| Directory | /workspace/27.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/27.xbar_random_large_delays.2426724384 |
| Short name | T493 |
| Test name | |
| Test status | |
| Simulation time | 69325208863 ps |
| CPU time | 743.47 seconds |
| Started | Jun 29 08:19:09 PM PDT 24 |
| Finished | Jun 29 08:31:33 PM PDT 24 |
| Peak memory | 575348 kb |
| Host | smart-109af156-1cf1-45d7-b7fc-461eb40d9245 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2426724384 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.xbar_random_large_delays.2426724384 |
| Directory | /workspace/27.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/27.xbar_random_slow_rsp.1092059399 |
| Short name | T1854 |
| Test name | |
| Test status | |
| Simulation time | 60649062389 ps |
| CPU time | 1030.25 seconds |
| Started | Jun 29 08:19:06 PM PDT 24 |
| Finished | Jun 29 08:36:16 PM PDT 24 |
| Peak memory | 574316 kb |
| Host | smart-23cb4a86-b97f-40c4-aaf3-e109ed58eb61 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1092059399 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.xbar_random_slow_rsp.1092059399 |
| Directory | /workspace/27.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/27.xbar_random_zero_delays.3245427629 |
| Short name | T2170 |
| Test name | |
| Test status | |
| Simulation time | 109685976 ps |
| CPU time | 14 seconds |
| Started | Jun 29 08:19:07 PM PDT 24 |
| Finished | Jun 29 08:19:21 PM PDT 24 |
| Peak memory | 575288 kb |
| Host | smart-9868bfa5-b4c6-444b-bfaf-b94ca01f262e |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3245427629 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.xbar_random_zero_del ays.3245427629 |
| Directory | /workspace/27.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/27.xbar_same_source.2702125913 |
| Short name | T2024 |
| Test name | |
| Test status | |
| Simulation time | 502845598 ps |
| CPU time | 40.51 seconds |
| Started | Jun 29 08:19:11 PM PDT 24 |
| Finished | Jun 29 08:19:52 PM PDT 24 |
| Peak memory | 575232 kb |
| Host | smart-3493a71b-fdf3-429a-aab6-1b1ef2731711 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2702125913 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.xbar_same_source.2702125913 |
| Directory | /workspace/27.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/27.xbar_smoke.409433298 |
| Short name | T1700 |
| Test name | |
| Test status | |
| Simulation time | 222773030 ps |
| CPU time | 9.69 seconds |
| Started | Jun 29 08:19:05 PM PDT 24 |
| Finished | Jun 29 08:19:15 PM PDT 24 |
| Peak memory | 574244 kb |
| Host | smart-478b0565-1ddf-4d02-8589-fdb03e6f5fea |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=409433298 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.xbar_smoke.409433298 |
| Directory | /workspace/27.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/27.xbar_smoke_large_delays.3366567779 |
| Short name | T1807 |
| Test name | |
| Test status | |
| Simulation time | 10068516905 ps |
| CPU time | 105.45 seconds |
| Started | Jun 29 08:19:06 PM PDT 24 |
| Finished | Jun 29 08:20:52 PM PDT 24 |
| Peak memory | 574328 kb |
| Host | smart-81685d93-a1a1-4ebe-8401-fb081028d980 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3366567779 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.xbar_smoke_large_delays.3366567779 |
| Directory | /workspace/27.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/27.xbar_smoke_slow_rsp.3415382426 |
| Short name | T1610 |
| Test name | |
| Test status | |
| Simulation time | 4578871071 ps |
| CPU time | 81.01 seconds |
| Started | Jun 29 08:19:07 PM PDT 24 |
| Finished | Jun 29 08:20:28 PM PDT 24 |
| Peak memory | 574304 kb |
| Host | smart-e339ffde-1903-427a-9fe3-35fb185d1d6b |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3415382426 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.xbar_smoke_slow_rsp.3415382426 |
| Directory | /workspace/27.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/27.xbar_smoke_zero_delays.2995036415 |
| Short name | T2474 |
| Test name | |
| Test status | |
| Simulation time | 35729961 ps |
| CPU time | 6.23 seconds |
| Started | Jun 29 08:19:06 PM PDT 24 |
| Finished | Jun 29 08:19:12 PM PDT 24 |
| Peak memory | 566008 kb |
| Host | smart-a6cbd033-48d1-40c5-9184-a99213f399e3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2995036415 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.xbar_smoke_zero_delay s.2995036415 |
| Directory | /workspace/27.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/27.xbar_stress_all.2833450087 |
| Short name | T1638 |
| Test name | |
| Test status | |
| Simulation time | 1279784508 ps |
| CPU time | 121.7 seconds |
| Started | Jun 29 08:19:10 PM PDT 24 |
| Finished | Jun 29 08:21:12 PM PDT 24 |
| Peak memory | 574400 kb |
| Host | smart-2069c28c-25e9-46d8-a288-65f66cb20563 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2833450087 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.xbar_stress_all.2833450087 |
| Directory | /workspace/27.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/27.xbar_stress_all_with_error.3078923168 |
| Short name | T2001 |
| Test name | |
| Test status | |
| Simulation time | 3300657710 ps |
| CPU time | 116.44 seconds |
| Started | Jun 29 08:19:10 PM PDT 24 |
| Finished | Jun 29 08:21:07 PM PDT 24 |
| Peak memory | 574372 kb |
| Host | smart-99384b86-f390-49d1-9d44-c313d1e222f2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3078923168 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.xbar_stress_all_with_error.3078923168 |
| Directory | /workspace/27.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/27.xbar_stress_all_with_rand_reset.591490756 |
| Short name | T2168 |
| Test name | |
| Test status | |
| Simulation time | 169990885 ps |
| CPU time | 65.75 seconds |
| Started | Jun 29 08:19:15 PM PDT 24 |
| Finished | Jun 29 08:20:21 PM PDT 24 |
| Peak memory | 574392 kb |
| Host | smart-442c9bc4-5968-46ac-9352-67b8ef776db0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=591490756 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_res et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.xbar_stress_all_ with_rand_reset.591490756 |
| Directory | /workspace/27.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/27.xbar_stress_all_with_reset_error.2188066965 |
| Short name | T2268 |
| Test name | |
| Test status | |
| Simulation time | 498324203 ps |
| CPU time | 66.55 seconds |
| Started | Jun 29 08:19:10 PM PDT 24 |
| Finished | Jun 29 08:20:16 PM PDT 24 |
| Peak memory | 574680 kb |
| Host | smart-5c55510d-05c7-4602-85f2-1ea6f414dbaf |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2188066965 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.xbar_stress_al l_with_reset_error.2188066965 |
| Directory | /workspace/27.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/27.xbar_unmapped_addr.2232551351 |
| Short name | T1572 |
| Test name | |
| Test status | |
| Simulation time | 291476714 ps |
| CPU time | 39.2 seconds |
| Started | Jun 29 08:19:09 PM PDT 24 |
| Finished | Jun 29 08:19:49 PM PDT 24 |
| Peak memory | 574276 kb |
| Host | smart-b35cb326-db78-4074-bcb2-c43b70cd717f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2232551351 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.xbar_unmapped_addr.2232551351 |
| Directory | /workspace/27.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/28.chip_tl_errors.1489231634 |
| Short name | T2815 |
| Test name | |
| Test status | |
| Simulation time | 2808941140 ps |
| CPU time | 100.88 seconds |
| Started | Jun 29 08:19:14 PM PDT 24 |
| Finished | Jun 29 08:20:56 PM PDT 24 |
| Peak memory | 597512 kb |
| Host | smart-ecb9c9b6-2dd2-48b4-96d4-6fda2ebb7c2c |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1489231634 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.chip_tl_errors.1489231634 |
| Directory | /workspace/28.chip_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/28.xbar_access_same_device.479459422 |
| Short name | T1746 |
| Test name | |
| Test status | |
| Simulation time | 277985178 ps |
| CPU time | 27.26 seconds |
| Started | Jun 29 08:19:25 PM PDT 24 |
| Finished | Jun 29 08:19:52 PM PDT 24 |
| Peak memory | 575264 kb |
| Host | smart-beb844bc-837d-4e15-8839-a616f705186f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=479459422 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.xbar_access_same_device. 479459422 |
| Directory | /workspace/28.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/28.xbar_access_same_device_slow_rsp.2204567377 |
| Short name | T2868 |
| Test name | |
| Test status | |
| Simulation time | 115399483334 ps |
| CPU time | 2047.14 seconds |
| Started | Jun 29 08:19:26 PM PDT 24 |
| Finished | Jun 29 08:53:33 PM PDT 24 |
| Peak memory | 574292 kb |
| Host | smart-af9ae08f-f5d2-48e0-b372-3eac9d011de2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2204567377 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.xbar_access_same_ device_slow_rsp.2204567377 |
| Directory | /workspace/28.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/28.xbar_error_and_unmapped_addr.1934777519 |
| Short name | T2233 |
| Test name | |
| Test status | |
| Simulation time | 556211503 ps |
| CPU time | 24.71 seconds |
| Started | Jun 29 08:19:28 PM PDT 24 |
| Finished | Jun 29 08:19:53 PM PDT 24 |
| Peak memory | 574512 kb |
| Host | smart-d0cf8eb4-6f82-4ff3-838f-fdeaaa3a9783 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1934777519 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.xbar_error_and_unmapped_add r.1934777519 |
| Directory | /workspace/28.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/28.xbar_error_random.3849415674 |
| Short name | T2575 |
| Test name | |
| Test status | |
| Simulation time | 899151100 ps |
| CPU time | 38.64 seconds |
| Started | Jun 29 08:19:29 PM PDT 24 |
| Finished | Jun 29 08:20:08 PM PDT 24 |
| Peak memory | 574252 kb |
| Host | smart-c56260b2-58ec-4e29-a429-bd87f7dea097 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3849415674 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.xbar_error_random.3849415674 |
| Directory | /workspace/28.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/28.xbar_random.3610646863 |
| Short name | T612 |
| Test name | |
| Test status | |
| Simulation time | 2052096577 ps |
| CPU time | 86.46 seconds |
| Started | Jun 29 08:19:18 PM PDT 24 |
| Finished | Jun 29 08:20:45 PM PDT 24 |
| Peak memory | 574236 kb |
| Host | smart-1d3ef243-3e1d-4833-9191-86bcca85f360 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3610646863 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.xbar_random.3610646863 |
| Directory | /workspace/28.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/28.xbar_random_large_delays.1553122453 |
| Short name | T1947 |
| Test name | |
| Test status | |
| Simulation time | 81223749553 ps |
| CPU time | 841.42 seconds |
| Started | Jun 29 08:19:16 PM PDT 24 |
| Finished | Jun 29 08:33:18 PM PDT 24 |
| Peak memory | 575416 kb |
| Host | smart-0234fafb-407e-44d1-9261-46da64ab8a0d |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1553122453 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.xbar_random_large_delays.1553122453 |
| Directory | /workspace/28.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/28.xbar_random_slow_rsp.4256504643 |
| Short name | T2641 |
| Test name | |
| Test status | |
| Simulation time | 59810351007 ps |
| CPU time | 1101.75 seconds |
| Started | Jun 29 08:19:18 PM PDT 24 |
| Finished | Jun 29 08:37:40 PM PDT 24 |
| Peak memory | 575388 kb |
| Host | smart-aeeb22c1-1651-476b-b017-2a70c60a6dac |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4256504643 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.xbar_random_slow_rsp.4256504643 |
| Directory | /workspace/28.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/28.xbar_random_zero_delays.3753020715 |
| Short name | T2272 |
| Test name | |
| Test status | |
| Simulation time | 127380717 ps |
| CPU time | 14.39 seconds |
| Started | Jun 29 08:19:18 PM PDT 24 |
| Finished | Jun 29 08:19:32 PM PDT 24 |
| Peak memory | 575176 kb |
| Host | smart-ea2d34b4-6111-4f59-908c-0f4a52248ecc |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3753020715 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.xbar_random_zero_del ays.3753020715 |
| Directory | /workspace/28.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/28.xbar_same_source.3586606909 |
| Short name | T2581 |
| Test name | |
| Test status | |
| Simulation time | 1549727210 ps |
| CPU time | 45.33 seconds |
| Started | Jun 29 08:19:26 PM PDT 24 |
| Finished | Jun 29 08:20:12 PM PDT 24 |
| Peak memory | 575240 kb |
| Host | smart-5be60051-e626-47d8-8a2a-0674e5612447 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3586606909 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.xbar_same_source.3586606909 |
| Directory | /workspace/28.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/28.xbar_smoke.2140603936 |
| Short name | T1683 |
| Test name | |
| Test status | |
| Simulation time | 226892213 ps |
| CPU time | 10.55 seconds |
| Started | Jun 29 08:19:13 PM PDT 24 |
| Finished | Jun 29 08:19:24 PM PDT 24 |
| Peak memory | 574216 kb |
| Host | smart-efa90563-25e4-403f-8c3f-533dd4b07510 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2140603936 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.xbar_smoke.2140603936 |
| Directory | /workspace/28.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/28.xbar_smoke_large_delays.1907902130 |
| Short name | T1372 |
| Test name | |
| Test status | |
| Simulation time | 9799912357 ps |
| CPU time | 107.28 seconds |
| Started | Jun 29 08:19:13 PM PDT 24 |
| Finished | Jun 29 08:21:01 PM PDT 24 |
| Peak memory | 574320 kb |
| Host | smart-7009032a-b3ab-4206-98ae-04b9455120ce |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1907902130 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.xbar_smoke_large_delays.1907902130 |
| Directory | /workspace/28.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/28.xbar_smoke_slow_rsp.544603399 |
| Short name | T2754 |
| Test name | |
| Test status | |
| Simulation time | 2962991800 ps |
| CPU time | 52.86 seconds |
| Started | Jun 29 08:19:11 PM PDT 24 |
| Finished | Jun 29 08:20:04 PM PDT 24 |
| Peak memory | 565976 kb |
| Host | smart-a6ac3204-7abe-4160-8d2b-d795423bfea9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=544603399 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.xbar_smoke_slow_rsp.544603399 |
| Directory | /workspace/28.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/28.xbar_smoke_zero_delays.2546523798 |
| Short name | T1314 |
| Test name | |
| Test status | |
| Simulation time | 45460789 ps |
| CPU time | 6.24 seconds |
| Started | Jun 29 08:19:08 PM PDT 24 |
| Finished | Jun 29 08:19:15 PM PDT 24 |
| Peak memory | 565932 kb |
| Host | smart-c78f80e2-4c7b-4989-bb07-cd399ba76d72 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2546523798 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.xbar_smoke_zero_delay s.2546523798 |
| Directory | /workspace/28.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/28.xbar_stress_all.3845598365 |
| Short name | T1636 |
| Test name | |
| Test status | |
| Simulation time | 2202249034 ps |
| CPU time | 194.12 seconds |
| Started | Jun 29 08:19:29 PM PDT 24 |
| Finished | Jun 29 08:22:44 PM PDT 24 |
| Peak memory | 575516 kb |
| Host | smart-988dae01-6c5a-4b1e-a3a6-6c30e93be6e7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3845598365 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.xbar_stress_all.3845598365 |
| Directory | /workspace/28.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/28.xbar_stress_all_with_rand_reset.1039216598 |
| Short name | T2167 |
| Test name | |
| Test status | |
| Simulation time | 1844729145 ps |
| CPU time | 356.29 seconds |
| Started | Jun 29 08:19:29 PM PDT 24 |
| Finished | Jun 29 08:25:26 PM PDT 24 |
| Peak memory | 575468 kb |
| Host | smart-dd004370-8a94-4095-b897-1a2a93ca99c7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1039216598 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.xbar_stress_all _with_rand_reset.1039216598 |
| Directory | /workspace/28.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/28.xbar_stress_all_with_reset_error.55072529 |
| Short name | T1960 |
| Test name | |
| Test status | |
| Simulation time | 579377640 ps |
| CPU time | 183.33 seconds |
| Started | Jun 29 08:19:29 PM PDT 24 |
| Finished | Jun 29 08:22:32 PM PDT 24 |
| Peak memory | 574436 kb |
| Host | smart-f5bc9157-ebbf-4eb3-9373-de87f04bfd74 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55072529 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_res et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.xbar_stress_all_ with_reset_error.55072529 |
| Directory | /workspace/28.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/28.xbar_unmapped_addr.1499706618 |
| Short name | T2824 |
| Test name | |
| Test status | |
| Simulation time | 223477465 ps |
| CPU time | 27.31 seconds |
| Started | Jun 29 08:19:29 PM PDT 24 |
| Finished | Jun 29 08:19:56 PM PDT 24 |
| Peak memory | 575356 kb |
| Host | smart-75f90fc5-2595-4084-8920-eab445140c40 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1499706618 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.xbar_unmapped_addr.1499706618 |
| Directory | /workspace/28.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/29.xbar_access_same_device.2667530641 |
| Short name | T519 |
| Test name | |
| Test status | |
| Simulation time | 581169418 ps |
| CPU time | 36.34 seconds |
| Started | Jun 29 08:19:39 PM PDT 24 |
| Finished | Jun 29 08:20:15 PM PDT 24 |
| Peak memory | 575308 kb |
| Host | smart-7d3293d6-d919-4b98-822e-535f80424652 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2667530641 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.xbar_access_same_device .2667530641 |
| Directory | /workspace/29.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/29.xbar_access_same_device_slow_rsp.1820763298 |
| Short name | T527 |
| Test name | |
| Test status | |
| Simulation time | 49706140153 ps |
| CPU time | 871.73 seconds |
| Started | Jun 29 08:19:55 PM PDT 24 |
| Finished | Jun 29 08:34:27 PM PDT 24 |
| Peak memory | 575352 kb |
| Host | smart-d975d0a1-e7d4-494b-ae4d-980a417231d2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1820763298 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.xbar_access_same_ device_slow_rsp.1820763298 |
| Directory | /workspace/29.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/29.xbar_error_and_unmapped_addr.1156954089 |
| Short name | T2483 |
| Test name | |
| Test status | |
| Simulation time | 498854920 ps |
| CPU time | 25.38 seconds |
| Started | Jun 29 08:19:46 PM PDT 24 |
| Finished | Jun 29 08:20:12 PM PDT 24 |
| Peak memory | 574260 kb |
| Host | smart-320c8109-87cf-4d43-ae47-9ccda3d44abf |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1156954089 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.xbar_error_and_unmapped_add r.1156954089 |
| Directory | /workspace/29.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/29.xbar_error_random.52928002 |
| Short name | T1399 |
| Test name | |
| Test status | |
| Simulation time | 39802002 ps |
| CPU time | 6.36 seconds |
| Started | Jun 29 08:19:46 PM PDT 24 |
| Finished | Jun 29 08:19:53 PM PDT 24 |
| Peak memory | 574196 kb |
| Host | smart-a98bd75b-884b-48af-acc6-cbe499bb7d8f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52928002 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.xbar_error_random.52928002 |
| Directory | /workspace/29.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/29.xbar_random.1124830685 |
| Short name | T2638 |
| Test name | |
| Test status | |
| Simulation time | 830924530 ps |
| CPU time | 31.93 seconds |
| Started | Jun 29 08:19:38 PM PDT 24 |
| Finished | Jun 29 08:20:11 PM PDT 24 |
| Peak memory | 575280 kb |
| Host | smart-4a339135-3ac2-4629-a08a-452a52a13df5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1124830685 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.xbar_random.1124830685 |
| Directory | /workspace/29.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/29.xbar_random_large_delays.2848414698 |
| Short name | T2668 |
| Test name | |
| Test status | |
| Simulation time | 85223482117 ps |
| CPU time | 952.44 seconds |
| Started | Jun 29 08:19:39 PM PDT 24 |
| Finished | Jun 29 08:35:31 PM PDT 24 |
| Peak memory | 574332 kb |
| Host | smart-21a81893-6a4c-4790-8434-8e49974e9147 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2848414698 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.xbar_random_large_delays.2848414698 |
| Directory | /workspace/29.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/29.xbar_random_slow_rsp.477879843 |
| Short name | T2393 |
| Test name | |
| Test status | |
| Simulation time | 39182794334 ps |
| CPU time | 708.2 seconds |
| Started | Jun 29 08:19:37 PM PDT 24 |
| Finished | Jun 29 08:31:25 PM PDT 24 |
| Peak memory | 575368 kb |
| Host | smart-376281bd-6344-4394-9212-47073b28f887 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=477879843 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.xbar_random_slow_rsp.477879843 |
| Directory | /workspace/29.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/29.xbar_random_zero_delays.1460940513 |
| Short name | T2497 |
| Test name | |
| Test status | |
| Simulation time | 377593651 ps |
| CPU time | 37.6 seconds |
| Started | Jun 29 08:19:36 PM PDT 24 |
| Finished | Jun 29 08:20:14 PM PDT 24 |
| Peak memory | 575328 kb |
| Host | smart-0d5dd7eb-af97-471b-9d9e-e71171224090 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1460940513 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.xbar_random_zero_del ays.1460940513 |
| Directory | /workspace/29.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/29.xbar_same_source.2597234536 |
| Short name | T2793 |
| Test name | |
| Test status | |
| Simulation time | 177849183 ps |
| CPU time | 8.21 seconds |
| Started | Jun 29 08:19:44 PM PDT 24 |
| Finished | Jun 29 08:19:53 PM PDT 24 |
| Peak memory | 565980 kb |
| Host | smart-b25522bd-69e2-46a7-9f22-3211a85069de |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2597234536 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.xbar_same_source.2597234536 |
| Directory | /workspace/29.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/29.xbar_smoke.2780596391 |
| Short name | T1293 |
| Test name | |
| Test status | |
| Simulation time | 217336861 ps |
| CPU time | 9.79 seconds |
| Started | Jun 29 08:19:29 PM PDT 24 |
| Finished | Jun 29 08:19:39 PM PDT 24 |
| Peak memory | 574260 kb |
| Host | smart-a176c6e9-d289-4fe1-be9a-db277a37401c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2780596391 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.xbar_smoke.2780596391 |
| Directory | /workspace/29.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/29.xbar_smoke_large_delays.1395869787 |
| Short name | T2566 |
| Test name | |
| Test status | |
| Simulation time | 5071144057 ps |
| CPU time | 54.69 seconds |
| Started | Jun 29 08:19:40 PM PDT 24 |
| Finished | Jun 29 08:20:35 PM PDT 24 |
| Peak memory | 574080 kb |
| Host | smart-7a68bb01-569d-4962-829e-28a8676fd8ec |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1395869787 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.xbar_smoke_large_delays.1395869787 |
| Directory | /workspace/29.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/29.xbar_smoke_slow_rsp.1425598029 |
| Short name | T2283 |
| Test name | |
| Test status | |
| Simulation time | 5695045223 ps |
| CPU time | 101.23 seconds |
| Started | Jun 29 08:19:37 PM PDT 24 |
| Finished | Jun 29 08:21:18 PM PDT 24 |
| Peak memory | 574332 kb |
| Host | smart-eaafe957-473f-4cae-8d6f-5adb16ae372a |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1425598029 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.xbar_smoke_slow_rsp.1425598029 |
| Directory | /workspace/29.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/29.xbar_smoke_zero_delays.4130115356 |
| Short name | T1679 |
| Test name | |
| Test status | |
| Simulation time | 43358963 ps |
| CPU time | 6.58 seconds |
| Started | Jun 29 08:19:38 PM PDT 24 |
| Finished | Jun 29 08:19:45 PM PDT 24 |
| Peak memory | 574180 kb |
| Host | smart-7e801eed-49b2-460b-bbeb-16dc5051edf6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4130115356 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.xbar_smoke_zero_delay s.4130115356 |
| Directory | /workspace/29.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/29.xbar_stress_all.2380594550 |
| Short name | T2327 |
| Test name | |
| Test status | |
| Simulation time | 16374486600 ps |
| CPU time | 659.67 seconds |
| Started | Jun 29 08:19:45 PM PDT 24 |
| Finished | Jun 29 08:30:45 PM PDT 24 |
| Peak memory | 575524 kb |
| Host | smart-a67e25fe-8318-40f5-a6dc-fb3cc8e4a3f9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2380594550 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.xbar_stress_all.2380594550 |
| Directory | /workspace/29.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/29.xbar_stress_all_with_error.1488833529 |
| Short name | T654 |
| Test name | |
| Test status | |
| Simulation time | 2753116734 ps |
| CPU time | 222.58 seconds |
| Started | Jun 29 08:19:56 PM PDT 24 |
| Finished | Jun 29 08:23:39 PM PDT 24 |
| Peak memory | 574616 kb |
| Host | smart-3d9e4d8b-57e5-4aa6-9593-354e72a46ef6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1488833529 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.xbar_stress_all_with_error.1488833529 |
| Directory | /workspace/29.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/29.xbar_stress_all_with_rand_reset.2547341183 |
| Short name | T2573 |
| Test name | |
| Test status | |
| Simulation time | 8037193 ps |
| CPU time | 15.12 seconds |
| Started | Jun 29 08:19:44 PM PDT 24 |
| Finished | Jun 29 08:19:59 PM PDT 24 |
| Peak memory | 574056 kb |
| Host | smart-4bb902ed-31e6-43b5-832e-ebe2a367d307 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2547341183 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.xbar_stress_all _with_rand_reset.2547341183 |
| Directory | /workspace/29.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/29.xbar_stress_all_with_reset_error.2135817702 |
| Short name | T2777 |
| Test name | |
| Test status | |
| Simulation time | 4897432323 ps |
| CPU time | 588.8 seconds |
| Started | Jun 29 08:19:44 PM PDT 24 |
| Finished | Jun 29 08:29:34 PM PDT 24 |
| Peak memory | 581348 kb |
| Host | smart-3ca8e2c3-14a8-46d9-9af8-0b66f9a8bd5b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2135817702 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.xbar_stress_al l_with_reset_error.2135817702 |
| Directory | /workspace/29.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/29.xbar_unmapped_addr.1513982307 |
| Short name | T1673 |
| Test name | |
| Test status | |
| Simulation time | 1083488521 ps |
| CPU time | 50.98 seconds |
| Started | Jun 29 08:19:46 PM PDT 24 |
| Finished | Jun 29 08:20:38 PM PDT 24 |
| Peak memory | 575352 kb |
| Host | smart-6969af78-e2dd-40a2-a906-c8f5e6f35120 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1513982307 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.xbar_unmapped_addr.1513982307 |
| Directory | /workspace/29.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/3.chip_csr_aliasing.363540299 |
| Short name | T364 |
| Test name | |
| Test status | |
| Simulation time | 29370168822 ps |
| CPU time | 4534.36 seconds |
| Started | Jun 29 08:10:16 PM PDT 24 |
| Finished | Jun 29 09:25:51 PM PDT 24 |
| Peak memory | 591864 kb |
| Host | smart-1511f6c7-97c5-4a36-9bf4-11aebde1bea9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +csr_aliasing +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=363540299 -assert nopostproc +UVM_TESTNAME=chip_b ase_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/n ull -cm_name 3.chip_csr_aliasing.363540299 |
| Directory | /workspace/3.chip_csr_aliasing/latest |
| Test location | /workspace/coverage/cover_reg_top/3.chip_csr_bit_bash.4008210572 |
| Short name | T2382 |
| Test name | |
| Test status | |
| Simulation time | 41644437186 ps |
| CPU time | 4302.29 seconds |
| Started | Jun 29 08:10:10 PM PDT 24 |
| Finished | Jun 29 09:21:53 PM PDT 24 |
| Peak memory | 589976 kb |
| Host | smart-07643a46-4fcd-4504-b272-66175bb72ed1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +num_test_csrs=200 +csr_bit_bash +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4008210572 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to p.vdb -cm_log /dev/null -cm_name 3.chip_csr_bit_bash.4008210572 |
| Directory | /workspace/3.chip_csr_bit_bash/latest |
| Test location | /workspace/coverage/cover_reg_top/3.chip_csr_hw_reset.1728818914 |
| Short name | T129 |
| Test name | |
| Test status | |
| Simulation time | 5043671569 ps |
| CPU time | 303.49 seconds |
| Started | Jun 29 08:10:56 PM PDT 24 |
| Finished | Jun 29 08:16:00 PM PDT 24 |
| Peak memory | 661492 kb |
| Host | smart-1a5dae72-8683-4adc-acb9-a01095d98d98 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1728818914 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.chip_csr_hw_r eset.1728818914 |
| Directory | /workspace/3.chip_csr_hw_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/3.chip_csr_rw.2849049815 |
| Short name | T2716 |
| Test name | |
| Test status | |
| Simulation time | 4106221518 ps |
| CPU time | 364.2 seconds |
| Started | Jun 29 08:10:54 PM PDT 24 |
| Finished | Jun 29 08:16:58 PM PDT 24 |
| Peak memory | 596044 kb |
| Host | smart-53b18737-df5f-46de-a0ec-912d54058751 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2849049815 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.chip_csr_rw.2849049815 |
| Directory | /workspace/3.chip_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/3.chip_same_csr_outstanding.4010625610 |
| Short name | T2654 |
| Test name | |
| Test status | |
| Simulation time | 13811667584 ps |
| CPU time | 2064.89 seconds |
| Started | Jun 29 08:10:21 PM PDT 24 |
| Finished | Jun 29 08:44:46 PM PDT 24 |
| Peak memory | 591436 kb |
| Host | smart-8cd46ddb-3b86-4ca6-9047-56b864bcb546 |
| User | root |
| Command | /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +run_same_csr_outstanding +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4010625610 -assert nopostproc +UVM_TE STNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb - cm_log /dev/null -cm_name 3.chip_same_csr_outstanding.4010625610 |
| Directory | /workspace/3.chip_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/3.chip_tl_errors.2801061714 |
| Short name | T545 |
| Test name | |
| Test status | |
| Simulation time | 3599975776 ps |
| CPU time | 308.89 seconds |
| Started | Jun 29 08:10:16 PM PDT 24 |
| Finished | Jun 29 08:15:25 PM PDT 24 |
| Peak memory | 589316 kb |
| Host | smart-f0e3de93-bdb7-4d19-ac5b-1fd0440de14a |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2801061714 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.chip_tl_errors.2801061714 |
| Directory | /workspace/3.chip_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/3.xbar_access_same_device.1579390573 |
| Short name | T2577 |
| Test name | |
| Test status | |
| Simulation time | 1258033365 ps |
| CPU time | 114.35 seconds |
| Started | Jun 29 08:10:30 PM PDT 24 |
| Finished | Jun 29 08:12:25 PM PDT 24 |
| Peak memory | 575364 kb |
| Host | smart-ac6d311c-16b3-4358-9df6-7f6418085146 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1579390573 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.xbar_access_same_device. 1579390573 |
| Directory | /workspace/3.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/3.xbar_access_same_device_slow_rsp.3751641025 |
| Short name | T2308 |
| Test name | |
| Test status | |
| Simulation time | 125092958492 ps |
| CPU time | 2241.47 seconds |
| Started | Jun 29 08:10:45 PM PDT 24 |
| Finished | Jun 29 08:48:07 PM PDT 24 |
| Peak memory | 575496 kb |
| Host | smart-a8ddec61-cd06-4ea5-b2fd-843a563ce784 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3751641025 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.xbar_access_same_d evice_slow_rsp.3751641025 |
| Directory | /workspace/3.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/3.xbar_error_and_unmapped_addr.420020576 |
| Short name | T1290 |
| Test name | |
| Test status | |
| Simulation time | 431941649 ps |
| CPU time | 26.62 seconds |
| Started | Jun 29 08:10:39 PM PDT 24 |
| Finished | Jun 29 08:11:06 PM PDT 24 |
| Peak memory | 573916 kb |
| Host | smart-fcf1cf30-9a40-4530-b6be-a85f91766f51 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=420020576 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.xbar_error_and_unmapped_addr. 420020576 |
| Directory | /workspace/3.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/3.xbar_error_random.1025415515 |
| Short name | T2671 |
| Test name | |
| Test status | |
| Simulation time | 806661491 ps |
| CPU time | 30.64 seconds |
| Started | Jun 29 08:10:38 PM PDT 24 |
| Finished | Jun 29 08:11:09 PM PDT 24 |
| Peak memory | 574268 kb |
| Host | smart-3e1a0546-3f84-4148-9c6f-8d79c8c245e5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1025415515 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.xbar_error_random.1025415515 |
| Directory | /workspace/3.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/3.xbar_random.2478581530 |
| Short name | T565 |
| Test name | |
| Test status | |
| Simulation time | 832768666 ps |
| CPU time | 34.13 seconds |
| Started | Jun 29 08:10:33 PM PDT 24 |
| Finished | Jun 29 08:11:08 PM PDT 24 |
| Peak memory | 575332 kb |
| Host | smart-1a88e4e4-9990-4bf6-813f-35a22fed20d5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2478581530 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.xbar_random.2478581530 |
| Directory | /workspace/3.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/3.xbar_random_large_delays.2761153408 |
| Short name | T2776 |
| Test name | |
| Test status | |
| Simulation time | 89850900453 ps |
| CPU time | 946.02 seconds |
| Started | Jun 29 08:10:33 PM PDT 24 |
| Finished | Jun 29 08:26:20 PM PDT 24 |
| Peak memory | 574352 kb |
| Host | smart-04d2d1b9-82ec-44a4-a816-9e7edf5882a7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2761153408 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.xbar_random_large_delays.2761153408 |
| Directory | /workspace/3.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/3.xbar_random_slow_rsp.1984904588 |
| Short name | T1826 |
| Test name | |
| Test status | |
| Simulation time | 64171293672 ps |
| CPU time | 1127.12 seconds |
| Started | Jun 29 08:10:41 PM PDT 24 |
| Finished | Jun 29 08:29:28 PM PDT 24 |
| Peak memory | 575452 kb |
| Host | smart-d696354a-1b82-4ea3-ac9d-1c034d745a6b |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1984904588 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.xbar_random_slow_rsp.1984904588 |
| Directory | /workspace/3.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/3.xbar_random_zero_delays.4163791944 |
| Short name | T580 |
| Test name | |
| Test status | |
| Simulation time | 402425015 ps |
| CPU time | 37.25 seconds |
| Started | Jun 29 08:10:31 PM PDT 24 |
| Finished | Jun 29 08:11:08 PM PDT 24 |
| Peak memory | 574240 kb |
| Host | smart-7dcb6fea-c455-4b11-9a4f-511c0b8dae4f |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4163791944 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.xbar_random_zero_dela ys.4163791944 |
| Directory | /workspace/3.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/3.xbar_same_source.10579824 |
| Short name | T1358 |
| Test name | |
| Test status | |
| Simulation time | 165887470 ps |
| CPU time | 16.58 seconds |
| Started | Jun 29 08:10:37 PM PDT 24 |
| Finished | Jun 29 08:10:54 PM PDT 24 |
| Peak memory | 575308 kb |
| Host | smart-ec4c3814-93d4-43f7-90f3-40fbc75cedd3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10579824 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.xbar_same_source.10579824 |
| Directory | /workspace/3.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/3.xbar_smoke.1088519892 |
| Short name | T2035 |
| Test name | |
| Test status | |
| Simulation time | 201207140 ps |
| CPU time | 9.32 seconds |
| Started | Jun 29 08:10:18 PM PDT 24 |
| Finished | Jun 29 08:10:28 PM PDT 24 |
| Peak memory | 574260 kb |
| Host | smart-d1a05a29-9d2f-4a6b-b1ad-007d19d47b6a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1088519892 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.xbar_smoke.1088519892 |
| Directory | /workspace/3.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/3.xbar_smoke_large_delays.2099879977 |
| Short name | T1772 |
| Test name | |
| Test status | |
| Simulation time | 5541045733 ps |
| CPU time | 61.49 seconds |
| Started | Jun 29 08:10:22 PM PDT 24 |
| Finished | Jun 29 08:11:24 PM PDT 24 |
| Peak memory | 574140 kb |
| Host | smart-66d79d64-a8ea-42a7-84aa-08f83b5292ab |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2099879977 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.xbar_smoke_large_delays.2099879977 |
| Directory | /workspace/3.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/3.xbar_smoke_slow_rsp.2118897079 |
| Short name | T1515 |
| Test name | |
| Test status | |
| Simulation time | 5198444050 ps |
| CPU time | 94.06 seconds |
| Started | Jun 29 08:10:27 PM PDT 24 |
| Finished | Jun 29 08:12:01 PM PDT 24 |
| Peak memory | 574456 kb |
| Host | smart-86d7463c-9af0-4123-be19-441bd0ab4a78 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2118897079 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.xbar_smoke_slow_rsp.2118897079 |
| Directory | /workspace/3.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/3.xbar_smoke_zero_delays.2418261986 |
| Short name | T1520 |
| Test name | |
| Test status | |
| Simulation time | 52456873 ps |
| CPU time | 7.68 seconds |
| Started | Jun 29 08:10:27 PM PDT 24 |
| Finished | Jun 29 08:10:35 PM PDT 24 |
| Peak memory | 566108 kb |
| Host | smart-3a394603-7389-4d17-a40b-32aa9cda5a62 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2418261986 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.xbar_smoke_zero_delays .2418261986 |
| Directory | /workspace/3.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/3.xbar_stress_all.1672201362 |
| Short name | T2264 |
| Test name | |
| Test status | |
| Simulation time | 7750165406 ps |
| CPU time | 324.98 seconds |
| Started | Jun 29 08:10:49 PM PDT 24 |
| Finished | Jun 29 08:16:15 PM PDT 24 |
| Peak memory | 574456 kb |
| Host | smart-826aebab-6af2-4f12-9032-774179b37e66 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1672201362 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.xbar_stress_all.1672201362 |
| Directory | /workspace/3.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/3.xbar_stress_all_with_error.1482247837 |
| Short name | T1452 |
| Test name | |
| Test status | |
| Simulation time | 120442490 ps |
| CPU time | 15.14 seconds |
| Started | Jun 29 08:10:54 PM PDT 24 |
| Finished | Jun 29 08:11:09 PM PDT 24 |
| Peak memory | 573896 kb |
| Host | smart-f7293334-7687-4033-8bb7-c3f5dddb88f6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1482247837 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.xbar_stress_all_with_error.1482247837 |
| Directory | /workspace/3.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/3.xbar_stress_all_with_rand_reset.2179798751 |
| Short name | T2273 |
| Test name | |
| Test status | |
| Simulation time | 213614033 ps |
| CPU time | 153.05 seconds |
| Started | Jun 29 08:10:45 PM PDT 24 |
| Finished | Jun 29 08:13:19 PM PDT 24 |
| Peak memory | 575456 kb |
| Host | smart-68e7bbfc-9440-409b-8741-2564b12bd1d0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2179798751 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.xbar_stress_all_ with_rand_reset.2179798751 |
| Directory | /workspace/3.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/3.xbar_stress_all_with_reset_error.393200447 |
| Short name | T1797 |
| Test name | |
| Test status | |
| Simulation time | 4742478295 ps |
| CPU time | 723.64 seconds |
| Started | Jun 29 08:11:04 PM PDT 24 |
| Finished | Jun 29 08:23:08 PM PDT 24 |
| Peak memory | 582252 kb |
| Host | smart-c88eba08-d040-485e-9d96-7b9fd5e3cca4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=393200447 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.xbar_stress_all_ with_reset_error.393200447 |
| Directory | /workspace/3.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/3.xbar_unmapped_addr.4114664258 |
| Short name | T2718 |
| Test name | |
| Test status | |
| Simulation time | 189210570 ps |
| CPU time | 28.59 seconds |
| Started | Jun 29 08:10:44 PM PDT 24 |
| Finished | Jun 29 08:11:13 PM PDT 24 |
| Peak memory | 575368 kb |
| Host | smart-aae306d9-e978-4b4e-8eee-23116521c271 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4114664258 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.xbar_unmapped_addr.4114664258 |
| Directory | /workspace/3.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/30.xbar_access_same_device.597924509 |
| Short name | T2715 |
| Test name | |
| Test status | |
| Simulation time | 954195491 ps |
| CPU time | 40.74 seconds |
| Started | Jun 29 08:19:53 PM PDT 24 |
| Finished | Jun 29 08:20:34 PM PDT 24 |
| Peak memory | 574228 kb |
| Host | smart-fd22bca3-1455-442a-930e-b5c20d4def4f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=597924509 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.xbar_access_same_device. 597924509 |
| Directory | /workspace/30.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/30.xbar_access_same_device_slow_rsp.636060335 |
| Short name | T786 |
| Test name | |
| Test status | |
| Simulation time | 29355678709 ps |
| CPU time | 542.99 seconds |
| Started | Jun 29 08:19:55 PM PDT 24 |
| Finished | Jun 29 08:28:58 PM PDT 24 |
| Peak memory | 575548 kb |
| Host | smart-2b5b70d8-88c3-46d1-af22-4c59128ff216 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=636060335 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.xbar_access_same_d evice_slow_rsp.636060335 |
| Directory | /workspace/30.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/30.xbar_error_and_unmapped_addr.3563740528 |
| Short name | T1719 |
| Test name | |
| Test status | |
| Simulation time | 26228691 ps |
| CPU time | 5.99 seconds |
| Started | Jun 29 08:19:52 PM PDT 24 |
| Finished | Jun 29 08:19:58 PM PDT 24 |
| Peak memory | 565648 kb |
| Host | smart-c18edaaa-6ca1-4ea1-8452-f6ef084897ba |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3563740528 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.xbar_error_and_unmapped_add r.3563740528 |
| Directory | /workspace/30.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/30.xbar_error_random.3986545071 |
| Short name | T1759 |
| Test name | |
| Test status | |
| Simulation time | 2424820224 ps |
| CPU time | 97.52 seconds |
| Started | Jun 29 08:19:58 PM PDT 24 |
| Finished | Jun 29 08:21:36 PM PDT 24 |
| Peak memory | 574516 kb |
| Host | smart-4018239a-16a4-4137-bb40-359b1fe3c429 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3986545071 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.xbar_error_random.3986545071 |
| Directory | /workspace/30.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/30.xbar_random.3143358477 |
| Short name | T2174 |
| Test name | |
| Test status | |
| Simulation time | 455431136 ps |
| CPU time | 41.3 seconds |
| Started | Jun 29 08:19:47 PM PDT 24 |
| Finished | Jun 29 08:20:28 PM PDT 24 |
| Peak memory | 575300 kb |
| Host | smart-9f5bc663-3f4a-4a7c-88c6-95a6587e7fec |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3143358477 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.xbar_random.3143358477 |
| Directory | /workspace/30.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/30.xbar_random_large_delays.1451484886 |
| Short name | T2648 |
| Test name | |
| Test status | |
| Simulation time | 37218358171 ps |
| CPU time | 393.97 seconds |
| Started | Jun 29 08:19:53 PM PDT 24 |
| Finished | Jun 29 08:26:27 PM PDT 24 |
| Peak memory | 575348 kb |
| Host | smart-42b7a2f0-d8a0-4adb-b430-e5cf43606a2c |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1451484886 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.xbar_random_large_delays.1451484886 |
| Directory | /workspace/30.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/30.xbar_random_slow_rsp.91777236 |
| Short name | T2352 |
| Test name | |
| Test status | |
| Simulation time | 34464606344 ps |
| CPU time | 584.07 seconds |
| Started | Jun 29 08:19:55 PM PDT 24 |
| Finished | Jun 29 08:29:39 PM PDT 24 |
| Peak memory | 574304 kb |
| Host | smart-4791cef8-cc6f-4ae3-ad09-2ee2d1e7f246 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=91777236 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.xbar_random_slow_rsp.91777236 |
| Directory | /workspace/30.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/30.xbar_random_zero_delays.3606571137 |
| Short name | T1426 |
| Test name | |
| Test status | |
| Simulation time | 110681346 ps |
| CPU time | 13.12 seconds |
| Started | Jun 29 08:19:52 PM PDT 24 |
| Finished | Jun 29 08:20:06 PM PDT 24 |
| Peak memory | 575304 kb |
| Host | smart-23c3fd7e-e0b0-44c3-aa23-c54a4d6b2548 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3606571137 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.xbar_random_zero_del ays.3606571137 |
| Directory | /workspace/30.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/30.xbar_same_source.3239217151 |
| Short name | T1906 |
| Test name | |
| Test status | |
| Simulation time | 2625846225 ps |
| CPU time | 86.56 seconds |
| Started | Jun 29 08:19:53 PM PDT 24 |
| Finished | Jun 29 08:21:19 PM PDT 24 |
| Peak memory | 574304 kb |
| Host | smart-41389b32-be56-4c59-a84c-0c7fc042038d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3239217151 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.xbar_same_source.3239217151 |
| Directory | /workspace/30.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/30.xbar_smoke.1913592080 |
| Short name | T2015 |
| Test name | |
| Test status | |
| Simulation time | 50817953 ps |
| CPU time | 7.05 seconds |
| Started | Jun 29 08:19:44 PM PDT 24 |
| Finished | Jun 29 08:19:51 PM PDT 24 |
| Peak memory | 574260 kb |
| Host | smart-35076c4b-df58-4ee3-9844-5f41c41fbb39 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1913592080 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.xbar_smoke.1913592080 |
| Directory | /workspace/30.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/30.xbar_smoke_large_delays.4134039096 |
| Short name | T2048 |
| Test name | |
| Test status | |
| Simulation time | 10265826140 ps |
| CPU time | 106.27 seconds |
| Started | Jun 29 08:19:55 PM PDT 24 |
| Finished | Jun 29 08:21:42 PM PDT 24 |
| Peak memory | 574288 kb |
| Host | smart-51c97b2c-9d57-43a9-8be6-91bc48832ad0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4134039096 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.xbar_smoke_large_delays.4134039096 |
| Directory | /workspace/30.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/30.xbar_smoke_slow_rsp.2110860881 |
| Short name | T2138 |
| Test name | |
| Test status | |
| Simulation time | 5159047815 ps |
| CPU time | 92.21 seconds |
| Started | Jun 29 08:19:44 PM PDT 24 |
| Finished | Jun 29 08:21:17 PM PDT 24 |
| Peak memory | 574208 kb |
| Host | smart-2cec8278-745e-40ac-b040-45b10550ac01 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2110860881 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.xbar_smoke_slow_rsp.2110860881 |
| Directory | /workspace/30.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/30.xbar_smoke_zero_delays.2275202280 |
| Short name | T2626 |
| Test name | |
| Test status | |
| Simulation time | 56294280 ps |
| CPU time | 7.37 seconds |
| Started | Jun 29 08:19:45 PM PDT 24 |
| Finished | Jun 29 08:19:53 PM PDT 24 |
| Peak memory | 574196 kb |
| Host | smart-880ab527-bd31-42b9-8619-0b3db7252368 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2275202280 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.xbar_smoke_zero_delay s.2275202280 |
| Directory | /workspace/30.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/30.xbar_stress_all.3579236213 |
| Short name | T495 |
| Test name | |
| Test status | |
| Simulation time | 1314662756 ps |
| CPU time | 146.08 seconds |
| Started | Jun 29 08:19:53 PM PDT 24 |
| Finished | Jun 29 08:22:19 PM PDT 24 |
| Peak memory | 574416 kb |
| Host | smart-11626f56-3541-41b2-a44f-f2fb3c023f86 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3579236213 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.xbar_stress_all.3579236213 |
| Directory | /workspace/30.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/30.xbar_stress_all_with_error.393196994 |
| Short name | T2520 |
| Test name | |
| Test status | |
| Simulation time | 871627722 ps |
| CPU time | 87.65 seconds |
| Started | Jun 29 08:19:52 PM PDT 24 |
| Finished | Jun 29 08:21:20 PM PDT 24 |
| Peak memory | 574280 kb |
| Host | smart-d43a16c2-0bce-453b-ab3b-6739445183a9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=393196994 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.xbar_stress_all_with_error.393196994 |
| Directory | /workspace/30.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/30.xbar_stress_all_with_rand_reset.539181361 |
| Short name | T1875 |
| Test name | |
| Test status | |
| Simulation time | 180395922 ps |
| CPU time | 99.24 seconds |
| Started | Jun 29 08:19:54 PM PDT 24 |
| Finished | Jun 29 08:21:33 PM PDT 24 |
| Peak memory | 575448 kb |
| Host | smart-c711471e-4e47-46f6-802c-4a1c55355bd9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=539181361 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_res et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.xbar_stress_all_ with_rand_reset.539181361 |
| Directory | /workspace/30.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/30.xbar_unmapped_addr.50921338 |
| Short name | T1824 |
| Test name | |
| Test status | |
| Simulation time | 210970433 ps |
| CPU time | 28.12 seconds |
| Started | Jun 29 08:19:53 PM PDT 24 |
| Finished | Jun 29 08:20:22 PM PDT 24 |
| Peak memory | 575344 kb |
| Host | smart-e5e091ac-c174-4b29-b00b-80c33a71fad4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50921338 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.xbar_unmapped_addr.50921338 |
| Directory | /workspace/30.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/31.xbar_access_same_device.301384787 |
| Short name | T2441 |
| Test name | |
| Test status | |
| Simulation time | 261235069 ps |
| CPU time | 36 seconds |
| Started | Jun 29 08:20:02 PM PDT 24 |
| Finished | Jun 29 08:20:38 PM PDT 24 |
| Peak memory | 575284 kb |
| Host | smart-80df0056-737c-4158-8631-1041eaace246 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=301384787 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.xbar_access_same_device. 301384787 |
| Directory | /workspace/31.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/31.xbar_access_same_device_slow_rsp.538495994 |
| Short name | T1563 |
| Test name | |
| Test status | |
| Simulation time | 102147389252 ps |
| CPU time | 1771.26 seconds |
| Started | Jun 29 08:20:00 PM PDT 24 |
| Finished | Jun 29 08:49:32 PM PDT 24 |
| Peak memory | 575480 kb |
| Host | smart-abb8c793-8918-43dc-b4bd-0ddfddc03d55 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=538495994 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.xbar_access_same_d evice_slow_rsp.538495994 |
| Directory | /workspace/31.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/31.xbar_error_and_unmapped_addr.494433631 |
| Short name | T1310 |
| Test name | |
| Test status | |
| Simulation time | 60307118 ps |
| CPU time | 8.53 seconds |
| Started | Jun 29 08:20:10 PM PDT 24 |
| Finished | Jun 29 08:20:19 PM PDT 24 |
| Peak memory | 573848 kb |
| Host | smart-8c337268-ce1d-4981-9b96-c28d07911963 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=494433631 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.xbar_error_and_unmapped_addr .494433631 |
| Directory | /workspace/31.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/31.xbar_error_random.3102573333 |
| Short name | T1793 |
| Test name | |
| Test status | |
| Simulation time | 1423486442 ps |
| CPU time | 54.02 seconds |
| Started | Jun 29 08:20:02 PM PDT 24 |
| Finished | Jun 29 08:20:56 PM PDT 24 |
| Peak memory | 574492 kb |
| Host | smart-74e0d7af-36bc-4f77-8858-85b133097c97 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3102573333 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.xbar_error_random.3102573333 |
| Directory | /workspace/31.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/31.xbar_random.3955899832 |
| Short name | T620 |
| Test name | |
| Test status | |
| Simulation time | 629525527 ps |
| CPU time | 62.83 seconds |
| Started | Jun 29 08:20:03 PM PDT 24 |
| Finished | Jun 29 08:21:06 PM PDT 24 |
| Peak memory | 575348 kb |
| Host | smart-1f9cd48a-e4d0-4e8f-bc44-2f5f8bec093a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3955899832 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.xbar_random.3955899832 |
| Directory | /workspace/31.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/31.xbar_random_large_delays.1326350194 |
| Short name | T1840 |
| Test name | |
| Test status | |
| Simulation time | 93797623626 ps |
| CPU time | 1058.87 seconds |
| Started | Jun 29 08:20:09 PM PDT 24 |
| Finished | Jun 29 08:37:49 PM PDT 24 |
| Peak memory | 574312 kb |
| Host | smart-c63eb708-311d-4b88-bb2e-42bbf4971cde |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1326350194 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.xbar_random_large_delays.1326350194 |
| Directory | /workspace/31.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/31.xbar_random_slow_rsp.1779368554 |
| Short name | T2324 |
| Test name | |
| Test status | |
| Simulation time | 62597228861 ps |
| CPU time | 1100.97 seconds |
| Started | Jun 29 08:20:01 PM PDT 24 |
| Finished | Jun 29 08:38:22 PM PDT 24 |
| Peak memory | 574364 kb |
| Host | smart-646abe9f-d94e-4fc2-9650-6dcb91754a91 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1779368554 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.xbar_random_slow_rsp.1779368554 |
| Directory | /workspace/31.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/31.xbar_random_zero_delays.2494833742 |
| Short name | T2524 |
| Test name | |
| Test status | |
| Simulation time | 64633234 ps |
| CPU time | 9.18 seconds |
| Started | Jun 29 08:20:02 PM PDT 24 |
| Finished | Jun 29 08:20:11 PM PDT 24 |
| Peak memory | 574284 kb |
| Host | smart-e7a4f8c5-7833-4e6c-8bd0-dbe7e3f06595 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2494833742 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.xbar_random_zero_del ays.2494833742 |
| Directory | /workspace/31.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/31.xbar_same_source.1222137406 |
| Short name | T2684 |
| Test name | |
| Test status | |
| Simulation time | 1533777844 ps |
| CPU time | 48.92 seconds |
| Started | Jun 29 08:20:03 PM PDT 24 |
| Finished | Jun 29 08:20:52 PM PDT 24 |
| Peak memory | 575296 kb |
| Host | smart-bc733749-3df1-4a3f-b599-6ad846951aea |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1222137406 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.xbar_same_source.1222137406 |
| Directory | /workspace/31.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/31.xbar_smoke.241601654 |
| Short name | T2122 |
| Test name | |
| Test status | |
| Simulation time | 164942165 ps |
| CPU time | 8.67 seconds |
| Started | Jun 29 08:20:01 PM PDT 24 |
| Finished | Jun 29 08:20:10 PM PDT 24 |
| Peak memory | 574248 kb |
| Host | smart-102ea699-c274-429d-b2e0-7ecb3bf4f100 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=241601654 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.xbar_smoke.241601654 |
| Directory | /workspace/31.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/31.xbar_smoke_large_delays.3650117563 |
| Short name | T2442 |
| Test name | |
| Test status | |
| Simulation time | 7866086271 ps |
| CPU time | 83.17 seconds |
| Started | Jun 29 08:20:01 PM PDT 24 |
| Finished | Jun 29 08:21:24 PM PDT 24 |
| Peak memory | 574320 kb |
| Host | smart-71ad6980-0149-4f75-8b34-4d2070d80522 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3650117563 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.xbar_smoke_large_delays.3650117563 |
| Directory | /workspace/31.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/31.xbar_smoke_slow_rsp.3971718663 |
| Short name | T1982 |
| Test name | |
| Test status | |
| Simulation time | 5432191197 ps |
| CPU time | 93.64 seconds |
| Started | Jun 29 08:20:04 PM PDT 24 |
| Finished | Jun 29 08:21:38 PM PDT 24 |
| Peak memory | 566088 kb |
| Host | smart-dd4e7617-aff1-4604-80d4-8437d229d04d |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3971718663 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.xbar_smoke_slow_rsp.3971718663 |
| Directory | /workspace/31.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/31.xbar_smoke_zero_delays.4187306204 |
| Short name | T1703 |
| Test name | |
| Test status | |
| Simulation time | 47872999 ps |
| CPU time | 6.42 seconds |
| Started | Jun 29 08:20:02 PM PDT 24 |
| Finished | Jun 29 08:20:09 PM PDT 24 |
| Peak memory | 574256 kb |
| Host | smart-7f818dab-bba2-4e97-bcf1-0950858dd0bd |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4187306204 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.xbar_smoke_zero_delay s.4187306204 |
| Directory | /workspace/31.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/31.xbar_stress_all.486317029 |
| Short name | T2513 |
| Test name | |
| Test status | |
| Simulation time | 3496497146 ps |
| CPU time | 133.03 seconds |
| Started | Jun 29 08:20:09 PM PDT 24 |
| Finished | Jun 29 08:22:23 PM PDT 24 |
| Peak memory | 574400 kb |
| Host | smart-8010281a-1027-44ec-939c-2cb5677d5f9f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=486317029 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.xbar_stress_all.486317029 |
| Directory | /workspace/31.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/31.xbar_stress_all_with_error.2763903804 |
| Short name | T1761 |
| Test name | |
| Test status | |
| Simulation time | 6405258907 ps |
| CPU time | 267.83 seconds |
| Started | Jun 29 08:20:09 PM PDT 24 |
| Finished | Jun 29 08:24:37 PM PDT 24 |
| Peak memory | 574392 kb |
| Host | smart-31b46b6d-47e0-43f0-877c-a35d919cbb74 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2763903804 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.xbar_stress_all_with_error.2763903804 |
| Directory | /workspace/31.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/31.xbar_stress_all_with_rand_reset.2451509444 |
| Short name | T2183 |
| Test name | |
| Test status | |
| Simulation time | 16901397 ps |
| CPU time | 14.01 seconds |
| Started | Jun 29 08:20:09 PM PDT 24 |
| Finished | Jun 29 08:20:23 PM PDT 24 |
| Peak memory | 574296 kb |
| Host | smart-8ffa852c-f6b6-456c-96c9-5d61043ae2a2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2451509444 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.xbar_stress_all _with_rand_reset.2451509444 |
| Directory | /workspace/31.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/31.xbar_stress_all_with_reset_error.2227939372 |
| Short name | T452 |
| Test name | |
| Test status | |
| Simulation time | 81639699 ps |
| CPU time | 18.49 seconds |
| Started | Jun 29 08:20:10 PM PDT 24 |
| Finished | Jun 29 08:20:29 PM PDT 24 |
| Peak memory | 575360 kb |
| Host | smart-45008df8-5711-4373-a71d-3f220961f395 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2227939372 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.xbar_stress_al l_with_reset_error.2227939372 |
| Directory | /workspace/31.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/31.xbar_unmapped_addr.3396408895 |
| Short name | T2090 |
| Test name | |
| Test status | |
| Simulation time | 96699461 ps |
| CPU time | 16.41 seconds |
| Started | Jun 29 08:20:01 PM PDT 24 |
| Finished | Jun 29 08:20:18 PM PDT 24 |
| Peak memory | 574264 kb |
| Host | smart-0d83633a-d72c-4bff-8668-62f5a64709d5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3396408895 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.xbar_unmapped_addr.3396408895 |
| Directory | /workspace/31.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/32.xbar_access_same_device.2356407022 |
| Short name | T2540 |
| Test name | |
| Test status | |
| Simulation time | 1074591801 ps |
| CPU time | 84.8 seconds |
| Started | Jun 29 08:20:13 PM PDT 24 |
| Finished | Jun 29 08:21:38 PM PDT 24 |
| Peak memory | 575336 kb |
| Host | smart-027a57e6-c5af-4f75-aa65-cdea7c8115ca |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2356407022 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.xbar_access_same_device .2356407022 |
| Directory | /workspace/32.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/32.xbar_access_same_device_slow_rsp.627735615 |
| Short name | T1672 |
| Test name | |
| Test status | |
| Simulation time | 56870309831 ps |
| CPU time | 978.49 seconds |
| Started | Jun 29 08:20:17 PM PDT 24 |
| Finished | Jun 29 08:36:36 PM PDT 24 |
| Peak memory | 575404 kb |
| Host | smart-e4fd2e3c-215e-496a-80f5-b21c02e888fa |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=627735615 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.xbar_access_same_d evice_slow_rsp.627735615 |
| Directory | /workspace/32.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/32.xbar_error_and_unmapped_addr.1667718793 |
| Short name | T2784 |
| Test name | |
| Test status | |
| Simulation time | 204277079 ps |
| CPU time | 22.71 seconds |
| Started | Jun 29 08:20:19 PM PDT 24 |
| Finished | Jun 29 08:20:42 PM PDT 24 |
| Peak memory | 574508 kb |
| Host | smart-0a6b25e5-9ffa-4684-accc-31c0ece5a985 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1667718793 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.xbar_error_and_unmapped_add r.1667718793 |
| Directory | /workspace/32.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/32.xbar_error_random.2746237221 |
| Short name | T2864 |
| Test name | |
| Test status | |
| Simulation time | 1436835676 ps |
| CPU time | 52.62 seconds |
| Started | Jun 29 08:20:16 PM PDT 24 |
| Finished | Jun 29 08:21:09 PM PDT 24 |
| Peak memory | 574504 kb |
| Host | smart-090d52f2-491d-4550-9d3c-7b543f4d4d5c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2746237221 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.xbar_error_random.2746237221 |
| Directory | /workspace/32.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/32.xbar_random.871628093 |
| Short name | T2882 |
| Test name | |
| Test status | |
| Simulation time | 422028761 ps |
| CPU time | 36.31 seconds |
| Started | Jun 29 08:20:21 PM PDT 24 |
| Finished | Jun 29 08:20:58 PM PDT 24 |
| Peak memory | 574240 kb |
| Host | smart-c49eaf14-ec7c-42b3-b3da-bb79a1d6229e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=871628093 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.xbar_random.871628093 |
| Directory | /workspace/32.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/32.xbar_random_large_delays.316366572 |
| Short name | T1768 |
| Test name | |
| Test status | |
| Simulation time | 101575879567 ps |
| CPU time | 1110.35 seconds |
| Started | Jun 29 08:20:09 PM PDT 24 |
| Finished | Jun 29 08:38:40 PM PDT 24 |
| Peak memory | 575380 kb |
| Host | smart-b8e3889f-aa95-4ecb-8cdf-81dc97d9085f |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=316366572 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.xbar_random_large_delays.316366572 |
| Directory | /workspace/32.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/32.xbar_random_slow_rsp.396458568 |
| Short name | T1623 |
| Test name | |
| Test status | |
| Simulation time | 49336990476 ps |
| CPU time | 860.73 seconds |
| Started | Jun 29 08:20:10 PM PDT 24 |
| Finished | Jun 29 08:34:31 PM PDT 24 |
| Peak memory | 574360 kb |
| Host | smart-d443c89d-7beb-4a99-9fa6-0ecacd7e5151 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=396458568 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.xbar_random_slow_rsp.396458568 |
| Directory | /workspace/32.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/32.xbar_random_zero_delays.849948010 |
| Short name | T540 |
| Test name | |
| Test status | |
| Simulation time | 315461836 ps |
| CPU time | 34.01 seconds |
| Started | Jun 29 08:20:13 PM PDT 24 |
| Finished | Jun 29 08:20:48 PM PDT 24 |
| Peak memory | 575272 kb |
| Host | smart-93e796e4-fb3a-4886-8abb-beb3dcc8bcc2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=849948010 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.xbar_random_zero_dela ys.849948010 |
| Directory | /workspace/32.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/32.xbar_same_source.384797975 |
| Short name | T2517 |
| Test name | |
| Test status | |
| Simulation time | 91567620 ps |
| CPU time | 11.15 seconds |
| Started | Jun 29 08:20:20 PM PDT 24 |
| Finished | Jun 29 08:20:31 PM PDT 24 |
| Peak memory | 574208 kb |
| Host | smart-52021806-be5b-445d-861a-4ad77092349a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=384797975 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.xbar_same_source.384797975 |
| Directory | /workspace/32.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/32.xbar_smoke.507321930 |
| Short name | T1454 |
| Test name | |
| Test status | |
| Simulation time | 200029140 ps |
| CPU time | 9.32 seconds |
| Started | Jun 29 08:20:13 PM PDT 24 |
| Finished | Jun 29 08:20:22 PM PDT 24 |
| Peak memory | 574252 kb |
| Host | smart-337d3665-27c5-4170-a355-e623a86f1121 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=507321930 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.xbar_smoke.507321930 |
| Directory | /workspace/32.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/32.xbar_smoke_large_delays.690350141 |
| Short name | T1911 |
| Test name | |
| Test status | |
| Simulation time | 6862890232 ps |
| CPU time | 71.68 seconds |
| Started | Jun 29 08:20:09 PM PDT 24 |
| Finished | Jun 29 08:21:21 PM PDT 24 |
| Peak memory | 574312 kb |
| Host | smart-da529ecc-6d49-4789-85e9-154ee81ad8a2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=690350141 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.xbar_smoke_large_delays.690350141 |
| Directory | /workspace/32.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/32.xbar_smoke_slow_rsp.3276234216 |
| Short name | T1660 |
| Test name | |
| Test status | |
| Simulation time | 4525184449 ps |
| CPU time | 79.19 seconds |
| Started | Jun 29 08:20:14 PM PDT 24 |
| Finished | Jun 29 08:21:33 PM PDT 24 |
| Peak memory | 574280 kb |
| Host | smart-e5e634f0-d21c-44ad-9965-d8f379a57c0d |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3276234216 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.xbar_smoke_slow_rsp.3276234216 |
| Directory | /workspace/32.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/32.xbar_smoke_zero_delays.3164508743 |
| Short name | T2757 |
| Test name | |
| Test status | |
| Simulation time | 47088908 ps |
| CPU time | 7.01 seconds |
| Started | Jun 29 08:20:09 PM PDT 24 |
| Finished | Jun 29 08:20:17 PM PDT 24 |
| Peak memory | 574268 kb |
| Host | smart-ad01db3b-4be5-470b-b658-57a6765f6f21 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3164508743 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.xbar_smoke_zero_delay s.3164508743 |
| Directory | /workspace/32.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/32.xbar_stress_all.437397627 |
| Short name | T476 |
| Test name | |
| Test status | |
| Simulation time | 10521185079 ps |
| CPU time | 411.52 seconds |
| Started | Jun 29 08:20:17 PM PDT 24 |
| Finished | Jun 29 08:27:09 PM PDT 24 |
| Peak memory | 574468 kb |
| Host | smart-75d02baf-220e-4823-8406-33658aff53c6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=437397627 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.xbar_stress_all.437397627 |
| Directory | /workspace/32.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/32.xbar_stress_all_with_error.1592470826 |
| Short name | T2354 |
| Test name | |
| Test status | |
| Simulation time | 2114846523 ps |
| CPU time | 64.01 seconds |
| Started | Jun 29 08:20:28 PM PDT 24 |
| Finished | Jun 29 08:21:32 PM PDT 24 |
| Peak memory | 574216 kb |
| Host | smart-4a4196ee-954c-46ec-bec9-47715eeaec53 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1592470826 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.xbar_stress_all_with_error.1592470826 |
| Directory | /workspace/32.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/32.xbar_stress_all_with_reset_error.261644692 |
| Short name | T2381 |
| Test name | |
| Test status | |
| Simulation time | 6344790054 ps |
| CPU time | 363 seconds |
| Started | Jun 29 08:20:15 PM PDT 24 |
| Finished | Jun 29 08:26:19 PM PDT 24 |
| Peak memory | 576496 kb |
| Host | smart-77b69a55-5b56-4cf5-931d-5ad6312a06a0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=261644692 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.xbar_stress_all _with_reset_error.261644692 |
| Directory | /workspace/32.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/32.xbar_unmapped_addr.4226949373 |
| Short name | T577 |
| Test name | |
| Test status | |
| Simulation time | 26031937 ps |
| CPU time | 6.35 seconds |
| Started | Jun 29 08:20:18 PM PDT 24 |
| Finished | Jun 29 08:20:25 PM PDT 24 |
| Peak memory | 566040 kb |
| Host | smart-29eee94d-519a-428e-9f0d-ec112f4bafbb |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4226949373 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.xbar_unmapped_addr.4226949373 |
| Directory | /workspace/32.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/33.xbar_access_same_device.1599505914 |
| Short name | T2372 |
| Test name | |
| Test status | |
| Simulation time | 575953689 ps |
| CPU time | 52.83 seconds |
| Started | Jun 29 08:20:43 PM PDT 24 |
| Finished | Jun 29 08:21:36 PM PDT 24 |
| Peak memory | 575316 kb |
| Host | smart-f45814fe-fe9d-4473-a2f5-cff9d0c03ce4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1599505914 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.xbar_access_same_device .1599505914 |
| Directory | /workspace/33.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/33.xbar_access_same_device_slow_rsp.1617498961 |
| Short name | T2353 |
| Test name | |
| Test status | |
| Simulation time | 16008433578 ps |
| CPU time | 302.27 seconds |
| Started | Jun 29 08:20:25 PM PDT 24 |
| Finished | Jun 29 08:25:28 PM PDT 24 |
| Peak memory | 574324 kb |
| Host | smart-137f56ec-7f96-416e-a067-fc1c06664692 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1617498961 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.xbar_access_same_ device_slow_rsp.1617498961 |
| Directory | /workspace/33.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/33.xbar_error_and_unmapped_addr.3416448597 |
| Short name | T1885 |
| Test name | |
| Test status | |
| Simulation time | 151827735 ps |
| CPU time | 17.14 seconds |
| Started | Jun 29 08:20:40 PM PDT 24 |
| Finished | Jun 29 08:20:57 PM PDT 24 |
| Peak memory | 574008 kb |
| Host | smart-31f43985-4dec-4bcd-ae7a-085b9f25eff2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3416448597 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.xbar_error_and_unmapped_add r.3416448597 |
| Directory | /workspace/33.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/33.xbar_error_random.2194682044 |
| Short name | T1305 |
| Test name | |
| Test status | |
| Simulation time | 1584280472 ps |
| CPU time | 56.23 seconds |
| Started | Jun 29 08:20:29 PM PDT 24 |
| Finished | Jun 29 08:21:25 PM PDT 24 |
| Peak memory | 573900 kb |
| Host | smart-10623ecc-89aa-4b72-8708-edfa80ff67c9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2194682044 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.xbar_error_random.2194682044 |
| Directory | /workspace/33.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/33.xbar_random.1856053480 |
| Short name | T608 |
| Test name | |
| Test status | |
| Simulation time | 1679848735 ps |
| CPU time | 57.86 seconds |
| Started | Jun 29 08:20:40 PM PDT 24 |
| Finished | Jun 29 08:21:38 PM PDT 24 |
| Peak memory | 575300 kb |
| Host | smart-7de56a9e-bd5c-467d-84c2-8afc48ef1c27 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1856053480 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.xbar_random.1856053480 |
| Directory | /workspace/33.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/33.xbar_random_large_delays.3316065719 |
| Short name | T2855 |
| Test name | |
| Test status | |
| Simulation time | 33170351267 ps |
| CPU time | 336.48 seconds |
| Started | Jun 29 08:20:41 PM PDT 24 |
| Finished | Jun 29 08:26:17 PM PDT 24 |
| Peak memory | 574328 kb |
| Host | smart-879ebb81-3c44-45fd-9658-41d365b6ad31 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3316065719 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.xbar_random_large_delays.3316065719 |
| Directory | /workspace/33.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/33.xbar_random_slow_rsp.3930416594 |
| Short name | T2032 |
| Test name | |
| Test status | |
| Simulation time | 54167893290 ps |
| CPU time | 1011.36 seconds |
| Started | Jun 29 08:20:25 PM PDT 24 |
| Finished | Jun 29 08:37:16 PM PDT 24 |
| Peak memory | 575388 kb |
| Host | smart-394ed3a9-9db9-46b8-b6ee-bda3da071031 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3930416594 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.xbar_random_slow_rsp.3930416594 |
| Directory | /workspace/33.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/33.xbar_random_zero_delays.1611242780 |
| Short name | T2501 |
| Test name | |
| Test status | |
| Simulation time | 496058953 ps |
| CPU time | 42.9 seconds |
| Started | Jun 29 08:20:27 PM PDT 24 |
| Finished | Jun 29 08:21:10 PM PDT 24 |
| Peak memory | 575296 kb |
| Host | smart-ab9e1fbd-ca9a-464c-8319-b789d8e3b53e |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1611242780 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.xbar_random_zero_del ays.1611242780 |
| Directory | /workspace/33.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/33.xbar_same_source.3973061304 |
| Short name | T497 |
| Test name | |
| Test status | |
| Simulation time | 2321849883 ps |
| CPU time | 68.32 seconds |
| Started | Jun 29 08:20:41 PM PDT 24 |
| Finished | Jun 29 08:21:49 PM PDT 24 |
| Peak memory | 575348 kb |
| Host | smart-2227f0ff-b0ec-490b-9f72-3205bac303c4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3973061304 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.xbar_same_source.3973061304 |
| Directory | /workspace/33.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/33.xbar_smoke.934610349 |
| Short name | T2737 |
| Test name | |
| Test status | |
| Simulation time | 128605311 ps |
| CPU time | 7.61 seconds |
| Started | Jun 29 08:20:19 PM PDT 24 |
| Finished | Jun 29 08:20:27 PM PDT 24 |
| Peak memory | 566004 kb |
| Host | smart-5fd42063-88ca-49f6-849f-92a2d76f478a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=934610349 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.xbar_smoke.934610349 |
| Directory | /workspace/33.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/33.xbar_smoke_large_delays.3398746529 |
| Short name | T2159 |
| Test name | |
| Test status | |
| Simulation time | 9072437864 ps |
| CPU time | 91.03 seconds |
| Started | Jun 29 08:20:27 PM PDT 24 |
| Finished | Jun 29 08:21:58 PM PDT 24 |
| Peak memory | 566076 kb |
| Host | smart-a45e4d66-2cf8-413c-b4dd-f154f4cfd6d7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3398746529 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.xbar_smoke_large_delays.3398746529 |
| Directory | /workspace/33.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/33.xbar_smoke_slow_rsp.3022910349 |
| Short name | T2775 |
| Test name | |
| Test status | |
| Simulation time | 5100824419 ps |
| CPU time | 87.55 seconds |
| Started | Jun 29 08:20:25 PM PDT 24 |
| Finished | Jun 29 08:21:53 PM PDT 24 |
| Peak memory | 574196 kb |
| Host | smart-3eec212a-932e-4ec3-aeea-4b68a9627233 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3022910349 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.xbar_smoke_slow_rsp.3022910349 |
| Directory | /workspace/33.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/33.xbar_smoke_zero_delays.3188531930 |
| Short name | T1709 |
| Test name | |
| Test status | |
| Simulation time | 45111960 ps |
| CPU time | 6.92 seconds |
| Started | Jun 29 08:20:17 PM PDT 24 |
| Finished | Jun 29 08:20:24 PM PDT 24 |
| Peak memory | 565976 kb |
| Host | smart-24cb16a2-c391-4a79-bb5f-ac6d11fe79d2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3188531930 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.xbar_smoke_zero_delay s.3188531930 |
| Directory | /workspace/33.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/33.xbar_stress_all.2687189137 |
| Short name | T2661 |
| Test name | |
| Test status | |
| Simulation time | 17408186319 ps |
| CPU time | 668.75 seconds |
| Started | Jun 29 08:20:36 PM PDT 24 |
| Finished | Jun 29 08:31:45 PM PDT 24 |
| Peak memory | 574456 kb |
| Host | smart-f2a78a06-c75b-4b7c-ba56-2295495cd502 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2687189137 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.xbar_stress_all.2687189137 |
| Directory | /workspace/33.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/33.xbar_stress_all_with_error.755054304 |
| Short name | T2205 |
| Test name | |
| Test status | |
| Simulation time | 537028546 ps |
| CPU time | 39.42 seconds |
| Started | Jun 29 08:20:35 PM PDT 24 |
| Finished | Jun 29 08:21:14 PM PDT 24 |
| Peak memory | 573964 kb |
| Host | smart-a6410416-22da-419b-ace1-47aee75e9965 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=755054304 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.xbar_stress_all_with_error.755054304 |
| Directory | /workspace/33.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/33.xbar_stress_all_with_reset_error.2898394155 |
| Short name | T813 |
| Test name | |
| Test status | |
| Simulation time | 610108044 ps |
| CPU time | 225.44 seconds |
| Started | Jun 29 08:20:36 PM PDT 24 |
| Finished | Jun 29 08:24:21 PM PDT 24 |
| Peak memory | 574692 kb |
| Host | smart-14a1bd66-bc6e-4ee7-9734-5c14fb362df2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2898394155 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.xbar_stress_al l_with_reset_error.2898394155 |
| Directory | /workspace/33.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/33.xbar_unmapped_addr.2471955249 |
| Short name | T1512 |
| Test name | |
| Test status | |
| Simulation time | 186847507 ps |
| CPU time | 11.69 seconds |
| Started | Jun 29 08:20:25 PM PDT 24 |
| Finished | Jun 29 08:20:37 PM PDT 24 |
| Peak memory | 575332 kb |
| Host | smart-1e77a150-6326-4994-8894-5883d7889441 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2471955249 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.xbar_unmapped_addr.2471955249 |
| Directory | /workspace/33.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/34.xbar_access_same_device.301991010 |
| Short name | T2828 |
| Test name | |
| Test status | |
| Simulation time | 1673035526 ps |
| CPU time | 79.37 seconds |
| Started | Jun 29 08:20:34 PM PDT 24 |
| Finished | Jun 29 08:21:54 PM PDT 24 |
| Peak memory | 575316 kb |
| Host | smart-e67e53fa-9854-4f05-89e3-2f60dd381f37 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=301991010 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.xbar_access_same_device. 301991010 |
| Directory | /workspace/34.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/34.xbar_error_and_unmapped_addr.1233037746 |
| Short name | T1631 |
| Test name | |
| Test status | |
| Simulation time | 531718662 ps |
| CPU time | 26.1 seconds |
| Started | Jun 29 08:20:42 PM PDT 24 |
| Finished | Jun 29 08:21:09 PM PDT 24 |
| Peak memory | 573920 kb |
| Host | smart-f59e70e1-3203-42e4-b777-9cc0aadb0eae |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1233037746 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.xbar_error_and_unmapped_add r.1233037746 |
| Directory | /workspace/34.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/34.xbar_error_random.2503515421 |
| Short name | T2250 |
| Test name | |
| Test status | |
| Simulation time | 266040603 ps |
| CPU time | 23.62 seconds |
| Started | Jun 29 08:20:45 PM PDT 24 |
| Finished | Jun 29 08:21:09 PM PDT 24 |
| Peak memory | 573936 kb |
| Host | smart-b7073077-203a-4a86-8490-041fb7ea97ac |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2503515421 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.xbar_error_random.2503515421 |
| Directory | /workspace/34.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/34.xbar_random.3453586530 |
| Short name | T623 |
| Test name | |
| Test status | |
| Simulation time | 321145096 ps |
| CPU time | 16.95 seconds |
| Started | Jun 29 08:20:38 PM PDT 24 |
| Finished | Jun 29 08:20:55 PM PDT 24 |
| Peak memory | 575296 kb |
| Host | smart-cefe8fc2-97d0-4083-8784-aae7e63ccb63 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3453586530 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.xbar_random.3453586530 |
| Directory | /workspace/34.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/34.xbar_random_large_delays.4195578053 |
| Short name | T1950 |
| Test name | |
| Test status | |
| Simulation time | 91209528651 ps |
| CPU time | 945.8 seconds |
| Started | Jun 29 08:20:33 PM PDT 24 |
| Finished | Jun 29 08:36:19 PM PDT 24 |
| Peak memory | 575456 kb |
| Host | smart-c246329f-e07a-4d09-9edd-4db86d364c87 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4195578053 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.xbar_random_large_delays.4195578053 |
| Directory | /workspace/34.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/34.xbar_random_slow_rsp.2527137227 |
| Short name | T2646 |
| Test name | |
| Test status | |
| Simulation time | 7042378490 ps |
| CPU time | 125.46 seconds |
| Started | Jun 29 08:20:35 PM PDT 24 |
| Finished | Jun 29 08:22:40 PM PDT 24 |
| Peak memory | 574388 kb |
| Host | smart-9441cb12-4e0b-4e98-9bc1-24c26544d69e |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2527137227 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.xbar_random_slow_rsp.2527137227 |
| Directory | /workspace/34.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/34.xbar_random_zero_delays.297144443 |
| Short name | T1607 |
| Test name | |
| Test status | |
| Simulation time | 301625635 ps |
| CPU time | 27.31 seconds |
| Started | Jun 29 08:20:34 PM PDT 24 |
| Finished | Jun 29 08:21:01 PM PDT 24 |
| Peak memory | 574228 kb |
| Host | smart-f104eb91-c0fe-4205-9a9e-d694bf8ed803 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=297144443 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.xbar_random_zero_dela ys.297144443 |
| Directory | /workspace/34.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/34.xbar_same_source.3253888230 |
| Short name | T2389 |
| Test name | |
| Test status | |
| Simulation time | 86162168 ps |
| CPU time | 9.85 seconds |
| Started | Jun 29 08:20:45 PM PDT 24 |
| Finished | Jun 29 08:20:56 PM PDT 24 |
| Peak memory | 575296 kb |
| Host | smart-2fdf250b-79ba-4abd-a870-4501d7dd75dd |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3253888230 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.xbar_same_source.3253888230 |
| Directory | /workspace/34.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/34.xbar_smoke.2103103696 |
| Short name | T2725 |
| Test name | |
| Test status | |
| Simulation time | 250110310 ps |
| CPU time | 10.6 seconds |
| Started | Jun 29 08:20:36 PM PDT 24 |
| Finished | Jun 29 08:20:47 PM PDT 24 |
| Peak memory | 574264 kb |
| Host | smart-3c32ca7f-7025-440c-bdb5-0c435c15fad3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2103103696 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.xbar_smoke.2103103696 |
| Directory | /workspace/34.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/34.xbar_smoke_large_delays.1362197256 |
| Short name | T542 |
| Test name | |
| Test status | |
| Simulation time | 8245856725 ps |
| CPU time | 84.72 seconds |
| Started | Jun 29 08:20:35 PM PDT 24 |
| Finished | Jun 29 08:22:00 PM PDT 24 |
| Peak memory | 566080 kb |
| Host | smart-0bba6577-064e-4654-b712-88d8ae778f27 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1362197256 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.xbar_smoke_large_delays.1362197256 |
| Directory | /workspace/34.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/34.xbar_smoke_slow_rsp.2132690096 |
| Short name | T2508 |
| Test name | |
| Test status | |
| Simulation time | 3983091110 ps |
| CPU time | 72.83 seconds |
| Started | Jun 29 08:20:36 PM PDT 24 |
| Finished | Jun 29 08:21:49 PM PDT 24 |
| Peak memory | 574168 kb |
| Host | smart-badc135b-d3b3-4756-b49f-504179dd83ad |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2132690096 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.xbar_smoke_slow_rsp.2132690096 |
| Directory | /workspace/34.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/34.xbar_smoke_zero_delays.906218652 |
| Short name | T2713 |
| Test name | |
| Test status | |
| Simulation time | 50595916 ps |
| CPU time | 7.18 seconds |
| Started | Jun 29 08:20:34 PM PDT 24 |
| Finished | Jun 29 08:20:41 PM PDT 24 |
| Peak memory | 574236 kb |
| Host | smart-db32f2fc-c5a1-4774-925d-e1e7d9cdc7a8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=906218652 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.xbar_smoke_zero_delays .906218652 |
| Directory | /workspace/34.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/34.xbar_stress_all.2475429003 |
| Short name | T1958 |
| Test name | |
| Test status | |
| Simulation time | 4376214109 ps |
| CPU time | 408.75 seconds |
| Started | Jun 29 08:20:42 PM PDT 24 |
| Finished | Jun 29 08:27:31 PM PDT 24 |
| Peak memory | 575516 kb |
| Host | smart-21352e41-6e2c-44f8-a9b4-01369dcf27e9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2475429003 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.xbar_stress_all.2475429003 |
| Directory | /workspace/34.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/34.xbar_stress_all_with_error.1684550985 |
| Short name | T674 |
| Test name | |
| Test status | |
| Simulation time | 6361473936 ps |
| CPU time | 246.75 seconds |
| Started | Jun 29 08:20:43 PM PDT 24 |
| Finished | Jun 29 08:24:50 PM PDT 24 |
| Peak memory | 574568 kb |
| Host | smart-ac05239b-6bf0-431c-99e7-db5462c3e274 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1684550985 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.xbar_stress_all_with_error.1684550985 |
| Directory | /workspace/34.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/34.xbar_stress_all_with_rand_reset.2598348203 |
| Short name | T481 |
| Test name | |
| Test status | |
| Simulation time | 13865569589 ps |
| CPU time | 830.12 seconds |
| Started | Jun 29 08:20:44 PM PDT 24 |
| Finished | Jun 29 08:34:34 PM PDT 24 |
| Peak memory | 575516 kb |
| Host | smart-48ac40f8-02e1-4cd2-87bc-f60f6027c35d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2598348203 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.xbar_stress_all _with_rand_reset.2598348203 |
| Directory | /workspace/34.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/34.xbar_stress_all_with_reset_error.1360999235 |
| Short name | T1722 |
| Test name | |
| Test status | |
| Simulation time | 85621720 ps |
| CPU time | 48.17 seconds |
| Started | Jun 29 08:20:55 PM PDT 24 |
| Finished | Jun 29 08:21:43 PM PDT 24 |
| Peak memory | 575468 kb |
| Host | smart-4281f185-85c9-4a5e-b36e-307df70bd0f0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1360999235 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.xbar_stress_al l_with_reset_error.1360999235 |
| Directory | /workspace/34.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/34.xbar_unmapped_addr.220530821 |
| Short name | T2047 |
| Test name | |
| Test status | |
| Simulation time | 279143007 ps |
| CPU time | 32.75 seconds |
| Started | Jun 29 08:20:43 PM PDT 24 |
| Finished | Jun 29 08:21:16 PM PDT 24 |
| Peak memory | 575376 kb |
| Host | smart-36e9ba55-07d0-4d05-8796-4d1bc69cf230 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=220530821 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.xbar_unmapped_addr.220530821 |
| Directory | /workspace/34.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/35.xbar_access_same_device.3857754958 |
| Short name | T2289 |
| Test name | |
| Test status | |
| Simulation time | 301425610 ps |
| CPU time | 29.86 seconds |
| Started | Jun 29 08:20:52 PM PDT 24 |
| Finished | Jun 29 08:21:22 PM PDT 24 |
| Peak memory | 575268 kb |
| Host | smart-cc500f34-2f1d-4366-8c00-8577a5900a1b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3857754958 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.xbar_access_same_device .3857754958 |
| Directory | /workspace/35.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/35.xbar_access_same_device_slow_rsp.2164675968 |
| Short name | T1889 |
| Test name | |
| Test status | |
| Simulation time | 38580581445 ps |
| CPU time | 660.51 seconds |
| Started | Jun 29 08:20:51 PM PDT 24 |
| Finished | Jun 29 08:31:52 PM PDT 24 |
| Peak memory | 575444 kb |
| Host | smart-d2501ad6-0df4-48c0-a8c4-175dcd13c2b3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2164675968 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.xbar_access_same_ device_slow_rsp.2164675968 |
| Directory | /workspace/35.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/35.xbar_error_and_unmapped_addr.1513293378 |
| Short name | T1868 |
| Test name | |
| Test status | |
| Simulation time | 1055562952 ps |
| CPU time | 47.05 seconds |
| Started | Jun 29 08:20:57 PM PDT 24 |
| Finished | Jun 29 08:21:45 PM PDT 24 |
| Peak memory | 574276 kb |
| Host | smart-8b008ba8-32fa-423f-a62b-fbd5066035a6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1513293378 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.xbar_error_and_unmapped_add r.1513293378 |
| Directory | /workspace/35.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/35.xbar_error_random.3092053077 |
| Short name | T2318 |
| Test name | |
| Test status | |
| Simulation time | 1678246679 ps |
| CPU time | 66.65 seconds |
| Started | Jun 29 08:20:52 PM PDT 24 |
| Finished | Jun 29 08:21:59 PM PDT 24 |
| Peak memory | 574272 kb |
| Host | smart-07476499-9510-4b60-b9dd-d79214757175 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3092053077 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.xbar_error_random.3092053077 |
| Directory | /workspace/35.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/35.xbar_random.2503213505 |
| Short name | T2853 |
| Test name | |
| Test status | |
| Simulation time | 32413503 ps |
| CPU time | 6.77 seconds |
| Started | Jun 29 08:20:49 PM PDT 24 |
| Finished | Jun 29 08:20:56 PM PDT 24 |
| Peak memory | 566036 kb |
| Host | smart-30a36582-fcea-4394-bddd-ca1af9ccf859 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2503213505 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.xbar_random.2503213505 |
| Directory | /workspace/35.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/35.xbar_random_large_delays.3253418423 |
| Short name | T2277 |
| Test name | |
| Test status | |
| Simulation time | 94791758999 ps |
| CPU time | 1030.11 seconds |
| Started | Jun 29 08:20:51 PM PDT 24 |
| Finished | Jun 29 08:38:01 PM PDT 24 |
| Peak memory | 575392 kb |
| Host | smart-23173364-a910-4c78-b584-2abe688d7f13 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3253418423 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.xbar_random_large_delays.3253418423 |
| Directory | /workspace/35.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/35.xbar_random_slow_rsp.1356448800 |
| Short name | T1860 |
| Test name | |
| Test status | |
| Simulation time | 53164100503 ps |
| CPU time | 901.16 seconds |
| Started | Jun 29 08:20:55 PM PDT 24 |
| Finished | Jun 29 08:35:56 PM PDT 24 |
| Peak memory | 575448 kb |
| Host | smart-0be62b30-7b5b-4b3b-b1d4-5018a31c51af |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1356448800 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.xbar_random_slow_rsp.1356448800 |
| Directory | /workspace/35.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/35.xbar_random_zero_delays.661803295 |
| Short name | T2726 |
| Test name | |
| Test status | |
| Simulation time | 217386191 ps |
| CPU time | 23.28 seconds |
| Started | Jun 29 08:20:49 PM PDT 24 |
| Finished | Jun 29 08:21:13 PM PDT 24 |
| Peak memory | 575308 kb |
| Host | smart-6267c1fc-7efd-4533-8b0f-2b64e1c71056 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=661803295 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.xbar_random_zero_dela ys.661803295 |
| Directory | /workspace/35.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/35.xbar_same_source.3951277879 |
| Short name | T2789 |
| Test name | |
| Test status | |
| Simulation time | 1453596162 ps |
| CPU time | 43.96 seconds |
| Started | Jun 29 08:20:49 PM PDT 24 |
| Finished | Jun 29 08:21:33 PM PDT 24 |
| Peak memory | 575268 kb |
| Host | smart-37f0ac28-a63b-4cd5-9ce9-93180abdd600 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3951277879 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.xbar_same_source.3951277879 |
| Directory | /workspace/35.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/35.xbar_smoke.3555671154 |
| Short name | T1786 |
| Test name | |
| Test status | |
| Simulation time | 235246429 ps |
| CPU time | 10.24 seconds |
| Started | Jun 29 08:20:50 PM PDT 24 |
| Finished | Jun 29 08:21:00 PM PDT 24 |
| Peak memory | 574284 kb |
| Host | smart-e0cb6644-184e-41b2-b868-1b7fe52be628 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3555671154 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.xbar_smoke.3555671154 |
| Directory | /workspace/35.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/35.xbar_smoke_large_delays.1394591038 |
| Short name | T2596 |
| Test name | |
| Test status | |
| Simulation time | 7282184491 ps |
| CPU time | 82.63 seconds |
| Started | Jun 29 08:20:50 PM PDT 24 |
| Finished | Jun 29 08:22:13 PM PDT 24 |
| Peak memory | 574328 kb |
| Host | smart-342e437c-47b2-4083-a922-afc404cf808a |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1394591038 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.xbar_smoke_large_delays.1394591038 |
| Directory | /workspace/35.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/35.xbar_smoke_slow_rsp.1915922793 |
| Short name | T2647 |
| Test name | |
| Test status | |
| Simulation time | 5791044769 ps |
| CPU time | 103.55 seconds |
| Started | Jun 29 08:20:50 PM PDT 24 |
| Finished | Jun 29 08:22:33 PM PDT 24 |
| Peak memory | 574336 kb |
| Host | smart-88717f99-2a1b-4318-8c57-a6392926c526 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1915922793 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.xbar_smoke_slow_rsp.1915922793 |
| Directory | /workspace/35.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/35.xbar_smoke_zero_delays.634133128 |
| Short name | T1961 |
| Test name | |
| Test status | |
| Simulation time | 45565097 ps |
| CPU time | 6.49 seconds |
| Started | Jun 29 08:20:55 PM PDT 24 |
| Finished | Jun 29 08:21:01 PM PDT 24 |
| Peak memory | 566028 kb |
| Host | smart-6ffccef2-7870-464f-a6e8-c33fd1485f32 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=634133128 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.xbar_smoke_zero_delays .634133128 |
| Directory | /workspace/35.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/35.xbar_stress_all.2005103911 |
| Short name | T499 |
| Test name | |
| Test status | |
| Simulation time | 12582638971 ps |
| CPU time | 509.76 seconds |
| Started | Jun 29 08:20:57 PM PDT 24 |
| Finished | Jun 29 08:29:27 PM PDT 24 |
| Peak memory | 574472 kb |
| Host | smart-08e3db01-2552-4e4b-9365-bbe5466b93fd |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2005103911 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.xbar_stress_all.2005103911 |
| Directory | /workspace/35.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/35.xbar_stress_all_with_error.3432280926 |
| Short name | T1367 |
| Test name | |
| Test status | |
| Simulation time | 837888376 ps |
| CPU time | 66.4 seconds |
| Started | Jun 29 08:20:57 PM PDT 24 |
| Finished | Jun 29 08:22:03 PM PDT 24 |
| Peak memory | 574612 kb |
| Host | smart-ebe8a4ef-2f5f-4ef6-b323-b213f55bc7d3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3432280926 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.xbar_stress_all_with_error.3432280926 |
| Directory | /workspace/35.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/35.xbar_stress_all_with_rand_reset.2011784267 |
| Short name | T2225 |
| Test name | |
| Test status | |
| Simulation time | 8151990 ps |
| CPU time | 5.05 seconds |
| Started | Jun 29 08:20:59 PM PDT 24 |
| Finished | Jun 29 08:21:04 PM PDT 24 |
| Peak memory | 565828 kb |
| Host | smart-63a4cbb9-e7f4-4037-a514-8260c5edab84 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2011784267 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.xbar_stress_all _with_rand_reset.2011784267 |
| Directory | /workspace/35.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/35.xbar_stress_all_with_reset_error.4057488684 |
| Short name | T2798 |
| Test name | |
| Test status | |
| Simulation time | 1509683289 ps |
| CPU time | 318.69 seconds |
| Started | Jun 29 08:21:00 PM PDT 24 |
| Finished | Jun 29 08:26:19 PM PDT 24 |
| Peak memory | 576448 kb |
| Host | smart-ededcc40-2d3c-4b3d-8b18-459e124ebe6d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4057488684 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.xbar_stress_al l_with_reset_error.4057488684 |
| Directory | /workspace/35.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/35.xbar_unmapped_addr.341661647 |
| Short name | T1736 |
| Test name | |
| Test status | |
| Simulation time | 894349863 ps |
| CPU time | 42.83 seconds |
| Started | Jun 29 08:21:04 PM PDT 24 |
| Finished | Jun 29 08:21:47 PM PDT 24 |
| Peak memory | 575276 kb |
| Host | smart-90e301e0-ceb3-49f5-8557-95e828fe6d8e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=341661647 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.xbar_unmapped_addr.341661647 |
| Directory | /workspace/35.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/36.xbar_access_same_device.657713728 |
| Short name | T2454 |
| Test name | |
| Test status | |
| Simulation time | 2381636744 ps |
| CPU time | 119.47 seconds |
| Started | Jun 29 08:20:56 PM PDT 24 |
| Finished | Jun 29 08:22:56 PM PDT 24 |
| Peak memory | 575408 kb |
| Host | smart-502f270a-46e6-4997-a6b6-5e805591ceb7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=657713728 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.xbar_access_same_device. 657713728 |
| Directory | /workspace/36.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/36.xbar_access_same_device_slow_rsp.178153581 |
| Short name | T1901 |
| Test name | |
| Test status | |
| Simulation time | 88651146115 ps |
| CPU time | 1493.57 seconds |
| Started | Jun 29 08:20:57 PM PDT 24 |
| Finished | Jun 29 08:45:52 PM PDT 24 |
| Peak memory | 575408 kb |
| Host | smart-c2805f82-9a6b-4cb8-a69f-42236234fc54 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=178153581 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.xbar_access_same_d evice_slow_rsp.178153581 |
| Directory | /workspace/36.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/36.xbar_error_and_unmapped_addr.1873872401 |
| Short name | T2439 |
| Test name | |
| Test status | |
| Simulation time | 182503639 ps |
| CPU time | 23.08 seconds |
| Started | Jun 29 08:21:05 PM PDT 24 |
| Finished | Jun 29 08:21:29 PM PDT 24 |
| Peak memory | 573944 kb |
| Host | smart-977913ea-b019-4724-8775-eb72a7db2090 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1873872401 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.xbar_error_and_unmapped_add r.1873872401 |
| Directory | /workspace/36.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/36.xbar_error_random.3976048586 |
| Short name | T1902 |
| Test name | |
| Test status | |
| Simulation time | 445341551 ps |
| CPU time | 20.77 seconds |
| Started | Jun 29 08:21:07 PM PDT 24 |
| Finished | Jun 29 08:21:28 PM PDT 24 |
| Peak memory | 574464 kb |
| Host | smart-ed71fd85-9e19-4181-a35a-f1ba5e614170 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3976048586 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.xbar_error_random.3976048586 |
| Directory | /workspace/36.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/36.xbar_random.95141796 |
| Short name | T2021 |
| Test name | |
| Test status | |
| Simulation time | 1031716397 ps |
| CPU time | 38.76 seconds |
| Started | Jun 29 08:20:59 PM PDT 24 |
| Finished | Jun 29 08:21:38 PM PDT 24 |
| Peak memory | 575304 kb |
| Host | smart-a86fbfed-1221-46b0-9d86-5062fa8b695a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95141796 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.xbar_random.95141796 |
| Directory | /workspace/36.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/36.xbar_random_large_delays.388683963 |
| Short name | T2104 |
| Test name | |
| Test status | |
| Simulation time | 20842106766 ps |
| CPU time | 219.29 seconds |
| Started | Jun 29 08:20:57 PM PDT 24 |
| Finished | Jun 29 08:24:36 PM PDT 24 |
| Peak memory | 575392 kb |
| Host | smart-cadbcefa-6759-483c-9424-55003b4f41e5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=388683963 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.xbar_random_large_delays.388683963 |
| Directory | /workspace/36.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/36.xbar_random_slow_rsp.3516610028 |
| Short name | T1698 |
| Test name | |
| Test status | |
| Simulation time | 3944906001 ps |
| CPU time | 66.84 seconds |
| Started | Jun 29 08:21:03 PM PDT 24 |
| Finished | Jun 29 08:22:10 PM PDT 24 |
| Peak memory | 574212 kb |
| Host | smart-62bbc8a9-5347-4af5-b16e-d681e323a2e2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3516610028 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.xbar_random_slow_rsp.3516610028 |
| Directory | /workspace/36.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/36.xbar_random_zero_delays.632721270 |
| Short name | T2479 |
| Test name | |
| Test status | |
| Simulation time | 120793056 ps |
| CPU time | 15.82 seconds |
| Started | Jun 29 08:20:57 PM PDT 24 |
| Finished | Jun 29 08:21:14 PM PDT 24 |
| Peak memory | 575320 kb |
| Host | smart-296fdf3d-1bae-44fc-96e6-eae9f804de1d |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=632721270 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.xbar_random_zero_dela ys.632721270 |
| Directory | /workspace/36.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/36.xbar_same_source.4241752863 |
| Short name | T1570 |
| Test name | |
| Test status | |
| Simulation time | 494992291 ps |
| CPU time | 18.01 seconds |
| Started | Jun 29 08:20:59 PM PDT 24 |
| Finished | Jun 29 08:21:17 PM PDT 24 |
| Peak memory | 575268 kb |
| Host | smart-5bb53561-4a8e-4068-8e66-a1a06fba7011 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4241752863 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.xbar_same_source.4241752863 |
| Directory | /workspace/36.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/36.xbar_smoke.3907888025 |
| Short name | T1413 |
| Test name | |
| Test status | |
| Simulation time | 43669935 ps |
| CPU time | 6.75 seconds |
| Started | Jun 29 08:20:57 PM PDT 24 |
| Finished | Jun 29 08:21:05 PM PDT 24 |
| Peak memory | 574260 kb |
| Host | smart-3890c415-8d7b-4b38-9aa7-bb3f6acb1ee6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3907888025 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.xbar_smoke.3907888025 |
| Directory | /workspace/36.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/36.xbar_smoke_large_delays.52041392 |
| Short name | T2123 |
| Test name | |
| Test status | |
| Simulation time | 8189328273 ps |
| CPU time | 90.36 seconds |
| Started | Jun 29 08:20:57 PM PDT 24 |
| Finished | Jun 29 08:22:27 PM PDT 24 |
| Peak memory | 574332 kb |
| Host | smart-c189e5b9-13e1-453d-bbd7-5614c26539de |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52041392 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.xbar_smoke_large_delays.52041392 |
| Directory | /workspace/36.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/36.xbar_smoke_slow_rsp.186199277 |
| Short name | T2462 |
| Test name | |
| Test status | |
| Simulation time | 4811231602 ps |
| CPU time | 79.07 seconds |
| Started | Jun 29 08:21:02 PM PDT 24 |
| Finished | Jun 29 08:22:21 PM PDT 24 |
| Peak memory | 566020 kb |
| Host | smart-57659639-f7c8-41e2-914b-2961f69a9a1e |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=186199277 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.xbar_smoke_slow_rsp.186199277 |
| Directory | /workspace/36.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/36.xbar_smoke_zero_delays.1011963364 |
| Short name | T1312 |
| Test name | |
| Test status | |
| Simulation time | 54866495 ps |
| CPU time | 8.06 seconds |
| Started | Jun 29 08:21:00 PM PDT 24 |
| Finished | Jun 29 08:21:09 PM PDT 24 |
| Peak memory | 566000 kb |
| Host | smart-502b2c1f-a4c2-434e-a356-c3f31f61be4d |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1011963364 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.xbar_smoke_zero_delay s.1011963364 |
| Directory | /workspace/36.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/36.xbar_stress_all.3677951274 |
| Short name | T2199 |
| Test name | |
| Test status | |
| Simulation time | 6873226667 ps |
| CPU time | 282.32 seconds |
| Started | Jun 29 08:21:05 PM PDT 24 |
| Finished | Jun 29 08:25:47 PM PDT 24 |
| Peak memory | 574464 kb |
| Host | smart-7d899f4e-782e-48e6-8a39-2264f3e375dc |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3677951274 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.xbar_stress_all.3677951274 |
| Directory | /workspace/36.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/36.xbar_stress_all_with_error.40661110 |
| Short name | T1670 |
| Test name | |
| Test status | |
| Simulation time | 4393968355 ps |
| CPU time | 190.92 seconds |
| Started | Jun 29 08:21:06 PM PDT 24 |
| Finished | Jun 29 08:24:17 PM PDT 24 |
| Peak memory | 574584 kb |
| Host | smart-0badffc3-b656-461e-89b9-93a2520dc7f8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40661110 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.xbar_stress_all_with_error.40661110 |
| Directory | /workspace/36.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/36.xbar_stress_all_with_rand_reset.3368332861 |
| Short name | T2783 |
| Test name | |
| Test status | |
| Simulation time | 6387796038 ps |
| CPU time | 399.05 seconds |
| Started | Jun 29 08:21:07 PM PDT 24 |
| Finished | Jun 29 08:27:46 PM PDT 24 |
| Peak memory | 575512 kb |
| Host | smart-5f9ebd34-a798-4639-8208-c5f1be339702 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3368332861 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.xbar_stress_all _with_rand_reset.3368332861 |
| Directory | /workspace/36.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/36.xbar_stress_all_with_reset_error.3005044278 |
| Short name | T1390 |
| Test name | |
| Test status | |
| Simulation time | 7897849413 ps |
| CPU time | 437.89 seconds |
| Started | Jun 29 08:21:06 PM PDT 24 |
| Finished | Jun 29 08:28:24 PM PDT 24 |
| Peak memory | 574412 kb |
| Host | smart-a69be954-7267-43d4-864e-932c600c5fe5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3005044278 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.xbar_stress_al l_with_reset_error.3005044278 |
| Directory | /workspace/36.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/36.xbar_unmapped_addr.322651233 |
| Short name | T2119 |
| Test name | |
| Test status | |
| Simulation time | 1309743936 ps |
| CPU time | 65.52 seconds |
| Started | Jun 29 08:21:07 PM PDT 24 |
| Finished | Jun 29 08:22:13 PM PDT 24 |
| Peak memory | 575384 kb |
| Host | smart-1eaca4a7-f6df-4fe1-ada9-9ddac2e80e53 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=322651233 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.xbar_unmapped_addr.322651233 |
| Directory | /workspace/36.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/37.xbar_access_same_device.2993098134 |
| Short name | T1729 |
| Test name | |
| Test status | |
| Simulation time | 2343488293 ps |
| CPU time | 96.9 seconds |
| Started | Jun 29 08:21:19 PM PDT 24 |
| Finished | Jun 29 08:22:57 PM PDT 24 |
| Peak memory | 575384 kb |
| Host | smart-86e7310d-a6b1-4a97-a3e1-3edc98c09d0e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2993098134 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.xbar_access_same_device .2993098134 |
| Directory | /workspace/37.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/37.xbar_access_same_device_slow_rsp.395295514 |
| Short name | T1528 |
| Test name | |
| Test status | |
| Simulation time | 31633966226 ps |
| CPU time | 564.7 seconds |
| Started | Jun 29 08:21:20 PM PDT 24 |
| Finished | Jun 29 08:30:45 PM PDT 24 |
| Peak memory | 574348 kb |
| Host | smart-f1a6260c-7537-4dc2-9ffe-bcf16161ed98 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=395295514 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.xbar_access_same_d evice_slow_rsp.395295514 |
| Directory | /workspace/37.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/37.xbar_error_and_unmapped_addr.2320304283 |
| Short name | T1753 |
| Test name | |
| Test status | |
| Simulation time | 1194333383 ps |
| CPU time | 55.45 seconds |
| Started | Jun 29 08:21:18 PM PDT 24 |
| Finished | Jun 29 08:22:14 PM PDT 24 |
| Peak memory | 574264 kb |
| Host | smart-bf0df946-831c-4202-bb8d-ca053b00b72d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2320304283 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.xbar_error_and_unmapped_add r.2320304283 |
| Directory | /workspace/37.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/37.xbar_error_random.116857454 |
| Short name | T1294 |
| Test name | |
| Test status | |
| Simulation time | 232610617 ps |
| CPU time | 22.85 seconds |
| Started | Jun 29 08:21:18 PM PDT 24 |
| Finished | Jun 29 08:21:41 PM PDT 24 |
| Peak memory | 574448 kb |
| Host | smart-7a7f9723-92ca-4e4a-9d9a-3df1d52a2763 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=116857454 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.xbar_error_random.116857454 |
| Directory | /workspace/37.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/37.xbar_random.2379301520 |
| Short name | T1744 |
| Test name | |
| Test status | |
| Simulation time | 1444051429 ps |
| CPU time | 50.52 seconds |
| Started | Jun 29 08:21:18 PM PDT 24 |
| Finished | Jun 29 08:22:08 PM PDT 24 |
| Peak memory | 574244 kb |
| Host | smart-7cb6e061-c6f1-4821-9b51-96e2c03579cf |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2379301520 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.xbar_random.2379301520 |
| Directory | /workspace/37.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/37.xbar_random_large_delays.3755086329 |
| Short name | T1717 |
| Test name | |
| Test status | |
| Simulation time | 86591719155 ps |
| CPU time | 918.06 seconds |
| Started | Jun 29 08:21:19 PM PDT 24 |
| Finished | Jun 29 08:36:37 PM PDT 24 |
| Peak memory | 574352 kb |
| Host | smart-fdaad1d5-d481-4545-8697-92ff7dd139a0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3755086329 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.xbar_random_large_delays.3755086329 |
| Directory | /workspace/37.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/37.xbar_random_slow_rsp.1653863766 |
| Short name | T1943 |
| Test name | |
| Test status | |
| Simulation time | 56641579333 ps |
| CPU time | 1014.44 seconds |
| Started | Jun 29 08:21:19 PM PDT 24 |
| Finished | Jun 29 08:38:14 PM PDT 24 |
| Peak memory | 574284 kb |
| Host | smart-401f0fe5-8a13-448e-a204-e3ebbb36ae7c |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1653863766 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.xbar_random_slow_rsp.1653863766 |
| Directory | /workspace/37.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/37.xbar_random_zero_delays.4063357391 |
| Short name | T2053 |
| Test name | |
| Test status | |
| Simulation time | 120783765 ps |
| CPU time | 12.82 seconds |
| Started | Jun 29 08:21:22 PM PDT 24 |
| Finished | Jun 29 08:21:35 PM PDT 24 |
| Peak memory | 575300 kb |
| Host | smart-46bba510-2beb-4feb-b8ef-8b1bd3353d49 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4063357391 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.xbar_random_zero_del ays.4063357391 |
| Directory | /workspace/37.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/37.xbar_same_source.2811337723 |
| Short name | T2253 |
| Test name | |
| Test status | |
| Simulation time | 1583262667 ps |
| CPU time | 50.38 seconds |
| Started | Jun 29 08:21:19 PM PDT 24 |
| Finished | Jun 29 08:22:10 PM PDT 24 |
| Peak memory | 575292 kb |
| Host | smart-f4b0945c-503c-4867-8baf-d638086ea9b1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2811337723 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.xbar_same_source.2811337723 |
| Directory | /workspace/37.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/37.xbar_smoke.2570344322 |
| Short name | T1818 |
| Test name | |
| Test status | |
| Simulation time | 38406461 ps |
| CPU time | 6.19 seconds |
| Started | Jun 29 08:21:20 PM PDT 24 |
| Finished | Jun 29 08:21:26 PM PDT 24 |
| Peak memory | 574236 kb |
| Host | smart-8c912e99-1e8a-405b-a3b0-1c618d14d5db |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2570344322 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.xbar_smoke.2570344322 |
| Directory | /workspace/37.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/37.xbar_smoke_large_delays.1215901997 |
| Short name | T1302 |
| Test name | |
| Test status | |
| Simulation time | 8814679066 ps |
| CPU time | 95.71 seconds |
| Started | Jun 29 08:21:20 PM PDT 24 |
| Finished | Jun 29 08:22:56 PM PDT 24 |
| Peak memory | 566068 kb |
| Host | smart-b334ae84-c2e7-412d-b65f-2369b4dd0547 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1215901997 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.xbar_smoke_large_delays.1215901997 |
| Directory | /workspace/37.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/37.xbar_smoke_slow_rsp.1636669938 |
| Short name | T2674 |
| Test name | |
| Test status | |
| Simulation time | 5961359826 ps |
| CPU time | 99.5 seconds |
| Started | Jun 29 08:21:19 PM PDT 24 |
| Finished | Jun 29 08:22:59 PM PDT 24 |
| Peak memory | 574148 kb |
| Host | smart-ddbea33c-e9dc-4031-83eb-f112cb2a88e9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1636669938 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.xbar_smoke_slow_rsp.1636669938 |
| Directory | /workspace/37.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/37.xbar_smoke_zero_delays.2559186422 |
| Short name | T1441 |
| Test name | |
| Test status | |
| Simulation time | 49403309 ps |
| CPU time | 7.25 seconds |
| Started | Jun 29 08:21:20 PM PDT 24 |
| Finished | Jun 29 08:21:28 PM PDT 24 |
| Peak memory | 574396 kb |
| Host | smart-2a41a581-be83-41ae-9265-594a496ba292 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2559186422 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.xbar_smoke_zero_delay s.2559186422 |
| Directory | /workspace/37.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/37.xbar_stress_all.4262678225 |
| Short name | T456 |
| Test name | |
| Test status | |
| Simulation time | 18407870112 ps |
| CPU time | 729.36 seconds |
| Started | Jun 29 08:21:21 PM PDT 24 |
| Finished | Jun 29 08:33:31 PM PDT 24 |
| Peak memory | 574480 kb |
| Host | smart-cd6a63e2-e6e8-488b-97ce-15942c97e7d5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4262678225 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.xbar_stress_all.4262678225 |
| Directory | /workspace/37.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/37.xbar_stress_all_with_error.906589392 |
| Short name | T2601 |
| Test name | |
| Test status | |
| Simulation time | 3245637305 ps |
| CPU time | 284.2 seconds |
| Started | Jun 29 08:21:21 PM PDT 24 |
| Finished | Jun 29 08:26:06 PM PDT 24 |
| Peak memory | 574424 kb |
| Host | smart-34eddc3e-4b63-467b-99c4-d93c58363f27 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=906589392 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.xbar_stress_all_with_error.906589392 |
| Directory | /workspace/37.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/37.xbar_stress_all_with_rand_reset.2909443585 |
| Short name | T2542 |
| Test name | |
| Test status | |
| Simulation time | 629246385 ps |
| CPU time | 209 seconds |
| Started | Jun 29 08:21:38 PM PDT 24 |
| Finished | Jun 29 08:25:07 PM PDT 24 |
| Peak memory | 574364 kb |
| Host | smart-6291f25a-a085-48c0-b59c-df22a3a76b0e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2909443585 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.xbar_stress_all _with_rand_reset.2909443585 |
| Directory | /workspace/37.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/37.xbar_stress_all_with_reset_error.3390085025 |
| Short name | T2639 |
| Test name | |
| Test status | |
| Simulation time | 145158524 ps |
| CPU time | 21.75 seconds |
| Started | Jun 29 08:21:25 PM PDT 24 |
| Finished | Jun 29 08:21:47 PM PDT 24 |
| Peak memory | 574416 kb |
| Host | smart-d5bd6989-0390-494b-9d1e-3e1d776898bb |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3390085025 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.xbar_stress_al l_with_reset_error.3390085025 |
| Directory | /workspace/37.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/37.xbar_unmapped_addr.1369367450 |
| Short name | T2069 |
| Test name | |
| Test status | |
| Simulation time | 427337801 ps |
| CPU time | 21.28 seconds |
| Started | Jun 29 08:21:20 PM PDT 24 |
| Finished | Jun 29 08:21:42 PM PDT 24 |
| Peak memory | 575352 kb |
| Host | smart-031ef7e3-e711-49c3-b8a1-e6e3851f25dd |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1369367450 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.xbar_unmapped_addr.1369367450 |
| Directory | /workspace/37.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/38.xbar_access_same_device.2485837263 |
| Short name | T1620 |
| Test name | |
| Test status | |
| Simulation time | 2925313905 ps |
| CPU time | 131.02 seconds |
| Started | Jun 29 08:21:38 PM PDT 24 |
| Finished | Jun 29 08:23:50 PM PDT 24 |
| Peak memory | 575316 kb |
| Host | smart-15a00e1e-96c0-46ef-a34d-5e43728ec95f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2485837263 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.xbar_access_same_device .2485837263 |
| Directory | /workspace/38.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/38.xbar_access_same_device_slow_rsp.4192016066 |
| Short name | T2164 |
| Test name | |
| Test status | |
| Simulation time | 68858701711 ps |
| CPU time | 1276.4 seconds |
| Started | Jun 29 08:21:22 PM PDT 24 |
| Finished | Jun 29 08:42:39 PM PDT 24 |
| Peak memory | 575484 kb |
| Host | smart-422886d9-03d8-407f-869b-0099af2c5fe2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4192016066 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.xbar_access_same_ device_slow_rsp.4192016066 |
| Directory | /workspace/38.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/38.xbar_error_and_unmapped_addr.1521976607 |
| Short name | T1568 |
| Test name | |
| Test status | |
| Simulation time | 1371649943 ps |
| CPU time | 54.91 seconds |
| Started | Jun 29 08:21:31 PM PDT 24 |
| Finished | Jun 29 08:22:26 PM PDT 24 |
| Peak memory | 573904 kb |
| Host | smart-04343a86-bb2b-4ee3-a353-6feabb6a9b2a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1521976607 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.xbar_error_and_unmapped_add r.1521976607 |
| Directory | /workspace/38.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/38.xbar_error_random.4057810287 |
| Short name | T1909 |
| Test name | |
| Test status | |
| Simulation time | 267908530 ps |
| CPU time | 25.88 seconds |
| Started | Jun 29 08:21:30 PM PDT 24 |
| Finished | Jun 29 08:21:56 PM PDT 24 |
| Peak memory | 574484 kb |
| Host | smart-ae8aa85c-46d9-422a-a103-e318c411ec0f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4057810287 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.xbar_error_random.4057810287 |
| Directory | /workspace/38.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/38.xbar_random.3415486969 |
| Short name | T2767 |
| Test name | |
| Test status | |
| Simulation time | 2314022233 ps |
| CPU time | 96.76 seconds |
| Started | Jun 29 08:21:21 PM PDT 24 |
| Finished | Jun 29 08:22:59 PM PDT 24 |
| Peak memory | 574292 kb |
| Host | smart-53cfbece-e619-4bb5-810d-80aac392488a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3415486969 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.xbar_random.3415486969 |
| Directory | /workspace/38.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/38.xbar_random_large_delays.73143781 |
| Short name | T2607 |
| Test name | |
| Test status | |
| Simulation time | 46529676598 ps |
| CPU time | 526.3 seconds |
| Started | Jun 29 08:21:22 PM PDT 24 |
| Finished | Jun 29 08:30:09 PM PDT 24 |
| Peak memory | 574328 kb |
| Host | smart-d49d33be-62e7-477c-a84f-c761228ab083 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73143781 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.xbar_random_large_delays.73143781 |
| Directory | /workspace/38.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/38.xbar_random_slow_rsp.3651387049 |
| Short name | T1951 |
| Test name | |
| Test status | |
| Simulation time | 58198642663 ps |
| CPU time | 967.24 seconds |
| Started | Jun 29 08:21:38 PM PDT 24 |
| Finished | Jun 29 08:37:46 PM PDT 24 |
| Peak memory | 575360 kb |
| Host | smart-b0566d2a-914a-4faf-9c86-2c0538c44853 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3651387049 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.xbar_random_slow_rsp.3651387049 |
| Directory | /workspace/38.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/38.xbar_random_zero_delays.1842523992 |
| Short name | T2472 |
| Test name | |
| Test status | |
| Simulation time | 463165857 ps |
| CPU time | 49.07 seconds |
| Started | Jun 29 08:21:22 PM PDT 24 |
| Finished | Jun 29 08:22:11 PM PDT 24 |
| Peak memory | 575352 kb |
| Host | smart-cb01878a-b000-4716-a35a-270fb45a9dd2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1842523992 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.xbar_random_zero_del ays.1842523992 |
| Directory | /workspace/38.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/38.xbar_same_source.690082550 |
| Short name | T538 |
| Test name | |
| Test status | |
| Simulation time | 2030923940 ps |
| CPU time | 69.85 seconds |
| Started | Jun 29 08:21:31 PM PDT 24 |
| Finished | Jun 29 08:22:41 PM PDT 24 |
| Peak memory | 575272 kb |
| Host | smart-997bdb81-31b4-4754-a728-d3fce24d5261 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=690082550 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.xbar_same_source.690082550 |
| Directory | /workspace/38.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/38.xbar_smoke.2872602169 |
| Short name | T2404 |
| Test name | |
| Test status | |
| Simulation time | 39635940 ps |
| CPU time | 6.1 seconds |
| Started | Jun 29 08:21:21 PM PDT 24 |
| Finished | Jun 29 08:21:27 PM PDT 24 |
| Peak memory | 574252 kb |
| Host | smart-75dcf0f2-14bd-4df8-ab01-9897313da1ff |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2872602169 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.xbar_smoke.2872602169 |
| Directory | /workspace/38.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/38.xbar_smoke_large_delays.2105528286 |
| Short name | T1701 |
| Test name | |
| Test status | |
| Simulation time | 7238695303 ps |
| CPU time | 79 seconds |
| Started | Jun 29 08:21:22 PM PDT 24 |
| Finished | Jun 29 08:22:41 PM PDT 24 |
| Peak memory | 574216 kb |
| Host | smart-45f78cf0-83b0-45f0-8682-663a967b4886 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2105528286 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.xbar_smoke_large_delays.2105528286 |
| Directory | /workspace/38.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/38.xbar_smoke_slow_rsp.2169116146 |
| Short name | T1295 |
| Test name | |
| Test status | |
| Simulation time | 6042096345 ps |
| CPU time | 107.76 seconds |
| Started | Jun 29 08:21:38 PM PDT 24 |
| Finished | Jun 29 08:23:26 PM PDT 24 |
| Peak memory | 574296 kb |
| Host | smart-73004fb7-f7e2-499f-b547-46d2619af3ec |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2169116146 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.xbar_smoke_slow_rsp.2169116146 |
| Directory | /workspace/38.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/38.xbar_smoke_zero_delays.2420465725 |
| Short name | T1788 |
| Test name | |
| Test status | |
| Simulation time | 55542134 ps |
| CPU time | 7.19 seconds |
| Started | Jun 29 08:21:22 PM PDT 24 |
| Finished | Jun 29 08:21:29 PM PDT 24 |
| Peak memory | 574256 kb |
| Host | smart-9cebe147-2b18-4f65-969e-bbfd484ff718 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2420465725 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.xbar_smoke_zero_delay s.2420465725 |
| Directory | /workspace/38.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/38.xbar_stress_all.1113696734 |
| Short name | T2338 |
| Test name | |
| Test status | |
| Simulation time | 2167246196 ps |
| CPU time | 206.95 seconds |
| Started | Jun 29 08:21:29 PM PDT 24 |
| Finished | Jun 29 08:24:56 PM PDT 24 |
| Peak memory | 574460 kb |
| Host | smart-4681146a-f5e3-4326-8dea-d495c8c79bf5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1113696734 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.xbar_stress_all.1113696734 |
| Directory | /workspace/38.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/38.xbar_stress_all_with_error.3377804384 |
| Short name | T2759 |
| Test name | |
| Test status | |
| Simulation time | 5520686054 ps |
| CPU time | 195.22 seconds |
| Started | Jun 29 08:21:34 PM PDT 24 |
| Finished | Jun 29 08:24:50 PM PDT 24 |
| Peak memory | 574636 kb |
| Host | smart-8db223cb-674b-49ed-a34e-0acf6f0dcc13 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3377804384 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.xbar_stress_all_with_error.3377804384 |
| Directory | /workspace/38.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/38.xbar_stress_all_with_rand_reset.1907167454 |
| Short name | T1888 |
| Test name | |
| Test status | |
| Simulation time | 20986181598 ps |
| CPU time | 1182.56 seconds |
| Started | Jun 29 08:21:29 PM PDT 24 |
| Finished | Jun 29 08:41:12 PM PDT 24 |
| Peak memory | 575532 kb |
| Host | smart-56f19b25-4aec-4ed8-8fd4-96925add74be |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1907167454 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.xbar_stress_all _with_rand_reset.1907167454 |
| Directory | /workspace/38.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/38.xbar_stress_all_with_reset_error.3072966605 |
| Short name | T2039 |
| Test name | |
| Test status | |
| Simulation time | 2193736841 ps |
| CPU time | 329.96 seconds |
| Started | Jun 29 08:21:29 PM PDT 24 |
| Finished | Jun 29 08:27:00 PM PDT 24 |
| Peak memory | 574728 kb |
| Host | smart-1e86dc7e-ffde-46ee-bd5a-b543825099a2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3072966605 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.xbar_stress_al l_with_reset_error.3072966605 |
| Directory | /workspace/38.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/38.xbar_unmapped_addr.1084423695 |
| Short name | T539 |
| Test name | |
| Test status | |
| Simulation time | 172964393 ps |
| CPU time | 24.28 seconds |
| Started | Jun 29 08:21:28 PM PDT 24 |
| Finished | Jun 29 08:21:53 PM PDT 24 |
| Peak memory | 575332 kb |
| Host | smart-cead4d3f-9250-44aa-a944-9644e4d7016d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1084423695 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.xbar_unmapped_addr.1084423695 |
| Directory | /workspace/38.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/39.xbar_access_same_device.913271855 |
| Short name | T2000 |
| Test name | |
| Test status | |
| Simulation time | 1204930008 ps |
| CPU time | 103.22 seconds |
| Started | Jun 29 08:21:46 PM PDT 24 |
| Finished | Jun 29 08:23:29 PM PDT 24 |
| Peak memory | 575296 kb |
| Host | smart-434da655-7edd-4f6a-a9fa-f3933a94ba9d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=913271855 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.xbar_access_same_device. 913271855 |
| Directory | /workspace/39.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/39.xbar_access_same_device_slow_rsp.821442633 |
| Short name | T1980 |
| Test name | |
| Test status | |
| Simulation time | 58576028708 ps |
| CPU time | 1055.73 seconds |
| Started | Jun 29 08:21:43 PM PDT 24 |
| Finished | Jun 29 08:39:19 PM PDT 24 |
| Peak memory | 575408 kb |
| Host | smart-7823f1f1-b18a-42a8-b9e1-83b640018632 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=821442633 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.xbar_access_same_d evice_slow_rsp.821442633 |
| Directory | /workspace/39.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/39.xbar_error_and_unmapped_addr.1057739357 |
| Short name | T1414 |
| Test name | |
| Test status | |
| Simulation time | 335382869 ps |
| CPU time | 37.92 seconds |
| Started | Jun 29 08:21:40 PM PDT 24 |
| Finished | Jun 29 08:22:19 PM PDT 24 |
| Peak memory | 574244 kb |
| Host | smart-ce1002ce-461c-410d-99be-329e633ffbe0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1057739357 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.xbar_error_and_unmapped_add r.1057739357 |
| Directory | /workspace/39.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/39.xbar_error_random.280341069 |
| Short name | T2749 |
| Test name | |
| Test status | |
| Simulation time | 478546788 ps |
| CPU time | 41.71 seconds |
| Started | Jun 29 08:21:41 PM PDT 24 |
| Finished | Jun 29 08:22:23 PM PDT 24 |
| Peak memory | 574464 kb |
| Host | smart-51a0fe71-70ae-4801-9133-ef32b1bdddb6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=280341069 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.xbar_error_random.280341069 |
| Directory | /workspace/39.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/39.xbar_random.1188041937 |
| Short name | T2453 |
| Test name | |
| Test status | |
| Simulation time | 2137384687 ps |
| CPU time | 81.73 seconds |
| Started | Jun 29 08:21:38 PM PDT 24 |
| Finished | Jun 29 08:23:01 PM PDT 24 |
| Peak memory | 575316 kb |
| Host | smart-153231d3-47fa-4b1b-a47d-9cf43871a651 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1188041937 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.xbar_random.1188041937 |
| Directory | /workspace/39.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/39.xbar_random_large_delays.1851204749 |
| Short name | T1742 |
| Test name | |
| Test status | |
| Simulation time | 87016706661 ps |
| CPU time | 902.14 seconds |
| Started | Jun 29 08:21:34 PM PDT 24 |
| Finished | Jun 29 08:36:37 PM PDT 24 |
| Peak memory | 574284 kb |
| Host | smart-da34c9cb-fe43-42ef-80ac-2ecdb621f629 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1851204749 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.xbar_random_large_delays.1851204749 |
| Directory | /workspace/39.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/39.xbar_random_slow_rsp.4044825431 |
| Short name | T1880 |
| Test name | |
| Test status | |
| Simulation time | 45872056158 ps |
| CPU time | 791.69 seconds |
| Started | Jun 29 08:21:43 PM PDT 24 |
| Finished | Jun 29 08:34:55 PM PDT 24 |
| Peak memory | 575420 kb |
| Host | smart-de1712c0-da09-45b9-bb1e-35cfd430620f |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4044825431 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.xbar_random_slow_rsp.4044825431 |
| Directory | /workspace/39.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/39.xbar_random_zero_delays.987763449 |
| Short name | T1435 |
| Test name | |
| Test status | |
| Simulation time | 313748592 ps |
| CPU time | 35.5 seconds |
| Started | Jun 29 08:21:28 PM PDT 24 |
| Finished | Jun 29 08:22:04 PM PDT 24 |
| Peak memory | 575332 kb |
| Host | smart-fef3378d-9aa0-4db3-bc48-1f5291677522 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=987763449 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.xbar_random_zero_dela ys.987763449 |
| Directory | /workspace/39.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/39.xbar_same_source.3518408774 |
| Short name | T1598 |
| Test name | |
| Test status | |
| Simulation time | 829469779 ps |
| CPU time | 30.11 seconds |
| Started | Jun 29 08:21:40 PM PDT 24 |
| Finished | Jun 29 08:22:11 PM PDT 24 |
| Peak memory | 575300 kb |
| Host | smart-bb1e469b-4d13-4287-9018-0fdbf5e286ff |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3518408774 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.xbar_same_source.3518408774 |
| Directory | /workspace/39.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/39.xbar_smoke.1398875564 |
| Short name | T2169 |
| Test name | |
| Test status | |
| Simulation time | 218444996 ps |
| CPU time | 9.46 seconds |
| Started | Jun 29 08:21:30 PM PDT 24 |
| Finished | Jun 29 08:21:40 PM PDT 24 |
| Peak memory | 574096 kb |
| Host | smart-5686da88-7699-4d45-b078-867f9c2c173d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1398875564 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.xbar_smoke.1398875564 |
| Directory | /workspace/39.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/39.xbar_smoke_large_delays.2596830518 |
| Short name | T2631 |
| Test name | |
| Test status | |
| Simulation time | 6796860253 ps |
| CPU time | 70.9 seconds |
| Started | Jun 29 08:21:31 PM PDT 24 |
| Finished | Jun 29 08:22:42 PM PDT 24 |
| Peak memory | 574312 kb |
| Host | smart-99acefbc-cb68-4fa1-862f-797c03d270ee |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2596830518 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.xbar_smoke_large_delays.2596830518 |
| Directory | /workspace/39.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/39.xbar_smoke_slow_rsp.2849970220 |
| Short name | T1465 |
| Test name | |
| Test status | |
| Simulation time | 5789644570 ps |
| CPU time | 105.26 seconds |
| Started | Jun 29 08:21:29 PM PDT 24 |
| Finished | Jun 29 08:23:15 PM PDT 24 |
| Peak memory | 574336 kb |
| Host | smart-ddf48e00-86c6-437f-95e9-9e6205c5c1e1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2849970220 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.xbar_smoke_slow_rsp.2849970220 |
| Directory | /workspace/39.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/39.xbar_smoke_zero_delays.3858375022 |
| Short name | T2841 |
| Test name | |
| Test status | |
| Simulation time | 55850000 ps |
| CPU time | 7.64 seconds |
| Started | Jun 29 08:21:29 PM PDT 24 |
| Finished | Jun 29 08:21:37 PM PDT 24 |
| Peak memory | 574276 kb |
| Host | smart-d308306d-2759-4f00-99f2-ce725a4bfb35 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3858375022 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.xbar_smoke_zero_delay s.3858375022 |
| Directory | /workspace/39.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/39.xbar_stress_all.3955493913 |
| Short name | T2416 |
| Test name | |
| Test status | |
| Simulation time | 11372461399 ps |
| CPU time | 465.25 seconds |
| Started | Jun 29 08:21:41 PM PDT 24 |
| Finished | Jun 29 08:29:26 PM PDT 24 |
| Peak memory | 574460 kb |
| Host | smart-de80b280-5c5a-43cb-bf36-606bc34d3020 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3955493913 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.xbar_stress_all.3955493913 |
| Directory | /workspace/39.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/39.xbar_stress_all_with_error.3287693858 |
| Short name | T1900 |
| Test name | |
| Test status | |
| Simulation time | 14966077979 ps |
| CPU time | 540.01 seconds |
| Started | Jun 29 08:21:43 PM PDT 24 |
| Finished | Jun 29 08:30:44 PM PDT 24 |
| Peak memory | 574716 kb |
| Host | smart-436b214b-e0e8-412a-bb52-4653111f07ff |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3287693858 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.xbar_stress_all_with_error.3287693858 |
| Directory | /workspace/39.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/39.xbar_stress_all_with_rand_reset.986884235 |
| Short name | T2010 |
| Test name | |
| Test status | |
| Simulation time | 9990613813 ps |
| CPU time | 514.38 seconds |
| Started | Jun 29 08:21:45 PM PDT 24 |
| Finished | Jun 29 08:30:20 PM PDT 24 |
| Peak memory | 577532 kb |
| Host | smart-e3422ca5-2541-4d53-ac55-29e39400c47c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=986884235 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_res et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.xbar_stress_all_ with_rand_reset.986884235 |
| Directory | /workspace/39.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/39.xbar_stress_all_with_reset_error.4212872233 |
| Short name | T827 |
| Test name | |
| Test status | |
| Simulation time | 5874284021 ps |
| CPU time | 336.82 seconds |
| Started | Jun 29 08:21:46 PM PDT 24 |
| Finished | Jun 29 08:27:23 PM PDT 24 |
| Peak memory | 576516 kb |
| Host | smart-29109263-a902-4a7b-9c02-f495fe3e9ba7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4212872233 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.xbar_stress_al l_with_reset_error.4212872233 |
| Directory | /workspace/39.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/39.xbar_unmapped_addr.2657370041 |
| Short name | T2026 |
| Test name | |
| Test status | |
| Simulation time | 1397769151 ps |
| CPU time | 63.41 seconds |
| Started | Jun 29 08:21:40 PM PDT 24 |
| Finished | Jun 29 08:22:44 PM PDT 24 |
| Peak memory | 575392 kb |
| Host | smart-0495d2e2-fb19-4069-a22d-447a886324fd |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2657370041 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.xbar_unmapped_addr.2657370041 |
| Directory | /workspace/39.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/4.chip_csr_aliasing.1111156500 |
| Short name | T2873 |
| Test name | |
| Test status | |
| Simulation time | 32107232395 ps |
| CPU time | 4703.84 seconds |
| Started | Jun 29 08:10:52 PM PDT 24 |
| Finished | Jun 29 09:29:16 PM PDT 24 |
| Peak memory | 592784 kb |
| Host | smart-ff795cc5-c141-4798-961e-31bca995c0b8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +csr_aliasing +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1111156500 -assert nopostproc +UVM_TESTNAME=chip_ base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/ null -cm_name 4.chip_csr_aliasing.1111156500 |
| Directory | /workspace/4.chip_csr_aliasing/latest |
| Test location | /workspace/coverage/cover_reg_top/4.chip_csr_bit_bash.3087757868 |
| Short name | T2537 |
| Test name | |
| Test status | |
| Simulation time | 8022160141 ps |
| CPU time | 999.87 seconds |
| Started | Jun 29 08:10:55 PM PDT 24 |
| Finished | Jun 29 08:27:35 PM PDT 24 |
| Peak memory | 588204 kb |
| Host | smart-393b925f-934c-4bb1-bb1c-578684af6362 |
| User | root |
| Command | /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +num_test_csrs=200 +csr_bit_bash +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3087757868 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to p.vdb -cm_log /dev/null -cm_name 4.chip_csr_bit_bash.3087757868 |
| Directory | /workspace/4.chip_csr_bit_bash/latest |
| Test location | /workspace/coverage/cover_reg_top/4.chip_csr_rw.3395483686 |
| Short name | T2790 |
| Test name | |
| Test status | |
| Simulation time | 3825596348 ps |
| CPU time | 297.87 seconds |
| Started | Jun 29 08:11:47 PM PDT 24 |
| Finished | Jun 29 08:16:45 PM PDT 24 |
| Peak memory | 597440 kb |
| Host | smart-0679e5cb-f8c0-4819-91d4-e8d5ed360b8f |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3395483686 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.chip_csr_rw.3395483686 |
| Directory | /workspace/4.chip_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/4.chip_same_csr_outstanding.2733436190 |
| Short name | T2633 |
| Test name | |
| Test status | |
| Simulation time | 16166453386 ps |
| CPU time | 2192.9 seconds |
| Started | Jun 29 08:11:08 PM PDT 24 |
| Finished | Jun 29 08:47:42 PM PDT 24 |
| Peak memory | 590536 kb |
| Host | smart-0ce6255f-c9f6-4f38-b68f-801f5fb42b52 |
| User | root |
| Command | /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +run_same_csr_outstanding +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2733436190 -assert nopostproc +UVM_TE STNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb - cm_log /dev/null -cm_name 4.chip_same_csr_outstanding.2733436190 |
| Directory | /workspace/4.chip_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/4.chip_tl_errors.2799990497 |
| Short name | T543 |
| Test name | |
| Test status | |
| Simulation time | 3473624604 ps |
| CPU time | 201.15 seconds |
| Started | Jun 29 08:11:07 PM PDT 24 |
| Finished | Jun 29 08:14:29 PM PDT 24 |
| Peak memory | 603636 kb |
| Host | smart-ad783990-c40e-4a10-90fe-5280a0e9a97c |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2799990497 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.chip_tl_errors.2799990497 |
| Directory | /workspace/4.chip_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/4.xbar_access_same_device.2721116658 |
| Short name | T2429 |
| Test name | |
| Test status | |
| Simulation time | 2033735791 ps |
| CPU time | 101.29 seconds |
| Started | Jun 29 08:11:18 PM PDT 24 |
| Finished | Jun 29 08:13:00 PM PDT 24 |
| Peak memory | 574244 kb |
| Host | smart-07825a4b-71f4-4f7d-a5f0-7adfa4907b39 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2721116658 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.xbar_access_same_device. 2721116658 |
| Directory | /workspace/4.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/4.xbar_access_same_device_slow_rsp.9428322 |
| Short name | T2605 |
| Test name | |
| Test status | |
| Simulation time | 31230864421 ps |
| CPU time | 558.05 seconds |
| Started | Jun 29 08:11:17 PM PDT 24 |
| Finished | Jun 29 08:20:35 PM PDT 24 |
| Peak memory | 575428 kb |
| Host | smart-43cd3674-b394-4fad-909f-96f3fb134370 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=9428322 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.xbar_access_same_devi ce_slow_rsp.9428322 |
| Directory | /workspace/4.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/4.xbar_error_and_unmapped_addr.4167425246 |
| Short name | T1785 |
| Test name | |
| Test status | |
| Simulation time | 1299877228 ps |
| CPU time | 53.03 seconds |
| Started | Jun 29 08:11:33 PM PDT 24 |
| Finished | Jun 29 08:12:26 PM PDT 24 |
| Peak memory | 574252 kb |
| Host | smart-9807b21e-f740-4aee-9875-8e441fdb0e67 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4167425246 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.xbar_error_and_unmapped_addr .4167425246 |
| Directory | /workspace/4.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/4.xbar_error_random.681604448 |
| Short name | T2111 |
| Test name | |
| Test status | |
| Simulation time | 2110580842 ps |
| CPU time | 82.43 seconds |
| Started | Jun 29 08:11:17 PM PDT 24 |
| Finished | Jun 29 08:12:40 PM PDT 24 |
| Peak memory | 574476 kb |
| Host | smart-882d01f4-f5e9-4936-9259-eb00bb268e17 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=681604448 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.xbar_error_random.681604448 |
| Directory | /workspace/4.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/4.xbar_random.3164177575 |
| Short name | T2527 |
| Test name | |
| Test status | |
| Simulation time | 1654695013 ps |
| CPU time | 58.58 seconds |
| Started | Jun 29 08:11:13 PM PDT 24 |
| Finished | Jun 29 08:12:12 PM PDT 24 |
| Peak memory | 575300 kb |
| Host | smart-13c26615-edbe-44e7-a693-cb2c0550a74c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3164177575 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.xbar_random.3164177575 |
| Directory | /workspace/4.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/4.xbar_random_large_delays.3326262092 |
| Short name | T2582 |
| Test name | |
| Test status | |
| Simulation time | 94111706945 ps |
| CPU time | 986.77 seconds |
| Started | Jun 29 08:11:21 PM PDT 24 |
| Finished | Jun 29 08:27:49 PM PDT 24 |
| Peak memory | 575456 kb |
| Host | smart-b390f41c-b191-4ce5-939b-87c4cc5cfc46 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3326262092 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.xbar_random_large_delays.3326262092 |
| Directory | /workspace/4.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/4.xbar_random_slow_rsp.3392786042 |
| Short name | T2296 |
| Test name | |
| Test status | |
| Simulation time | 30257534424 ps |
| CPU time | 558.09 seconds |
| Started | Jun 29 08:11:16 PM PDT 24 |
| Finished | Jun 29 08:20:35 PM PDT 24 |
| Peak memory | 575380 kb |
| Host | smart-f33b596b-08cc-4600-ac98-99a83fd5936b |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3392786042 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.xbar_random_slow_rsp.3392786042 |
| Directory | /workspace/4.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/4.xbar_random_zero_delays.4136481417 |
| Short name | T1748 |
| Test name | |
| Test status | |
| Simulation time | 328285595 ps |
| CPU time | 34.87 seconds |
| Started | Jun 29 08:11:10 PM PDT 24 |
| Finished | Jun 29 08:11:45 PM PDT 24 |
| Peak memory | 574248 kb |
| Host | smart-78a5855d-db19-4951-8d09-669c6a0b2f8f |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4136481417 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.xbar_random_zero_dela ys.4136481417 |
| Directory | /workspace/4.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/4.xbar_same_source.4204025766 |
| Short name | T501 |
| Test name | |
| Test status | |
| Simulation time | 2673938242 ps |
| CPU time | 94.19 seconds |
| Started | Jun 29 08:11:17 PM PDT 24 |
| Finished | Jun 29 08:12:52 PM PDT 24 |
| Peak memory | 575344 kb |
| Host | smart-f08a62cd-1a9f-4ee3-a456-add7c9bc540f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4204025766 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.xbar_same_source.4204025766 |
| Directory | /workspace/4.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/4.xbar_smoke.4263251118 |
| Short name | T2694 |
| Test name | |
| Test status | |
| Simulation time | 205992381 ps |
| CPU time | 9.03 seconds |
| Started | Jun 29 08:11:13 PM PDT 24 |
| Finished | Jun 29 08:11:23 PM PDT 24 |
| Peak memory | 574264 kb |
| Host | smart-e2250077-dc54-4b3a-807a-7c78e40e621a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4263251118 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.xbar_smoke.4263251118 |
| Directory | /workspace/4.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/4.xbar_smoke_large_delays.1079807030 |
| Short name | T2299 |
| Test name | |
| Test status | |
| Simulation time | 9355142263 ps |
| CPU time | 103.53 seconds |
| Started | Jun 29 08:11:09 PM PDT 24 |
| Finished | Jun 29 08:12:53 PM PDT 24 |
| Peak memory | 566052 kb |
| Host | smart-1d28661c-da61-4628-bdb9-42fcb4bba7a6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1079807030 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.xbar_smoke_large_delays.1079807030 |
| Directory | /workspace/4.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/4.xbar_smoke_slow_rsp.197548320 |
| Short name | T1343 |
| Test name | |
| Test status | |
| Simulation time | 6521267380 ps |
| CPU time | 114.12 seconds |
| Started | Jun 29 08:11:08 PM PDT 24 |
| Finished | Jun 29 08:13:02 PM PDT 24 |
| Peak memory | 566084 kb |
| Host | smart-034fb6e9-a69f-484b-a6ed-2878c279ffde |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=197548320 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.xbar_smoke_slow_rsp.197548320 |
| Directory | /workspace/4.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/4.xbar_smoke_zero_delays.1337179178 |
| Short name | T1307 |
| Test name | |
| Test status | |
| Simulation time | 40985995 ps |
| CPU time | 6.2 seconds |
| Started | Jun 29 08:11:13 PM PDT 24 |
| Finished | Jun 29 08:11:20 PM PDT 24 |
| Peak memory | 566016 kb |
| Host | smart-3390e43b-b673-4336-9150-30fcb15f27d6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1337179178 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.xbar_smoke_zero_delays .1337179178 |
| Directory | /workspace/4.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/4.xbar_stress_all.834511853 |
| Short name | T2019 |
| Test name | |
| Test status | |
| Simulation time | 12542057137 ps |
| CPU time | 565.19 seconds |
| Started | Jun 29 08:11:31 PM PDT 24 |
| Finished | Jun 29 08:20:57 PM PDT 24 |
| Peak memory | 574468 kb |
| Host | smart-dbe3d53e-815e-4bcb-bd9f-bb49c15c41fb |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=834511853 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.xbar_stress_all.834511853 |
| Directory | /workspace/4.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/4.xbar_stress_all_with_error.662685072 |
| Short name | T2129 |
| Test name | |
| Test status | |
| Simulation time | 950755445 ps |
| CPU time | 43.64 seconds |
| Started | Jun 29 08:11:43 PM PDT 24 |
| Finished | Jun 29 08:12:27 PM PDT 24 |
| Peak memory | 574512 kb |
| Host | smart-c43eed0c-af9c-446b-82e2-ad90e62cdf35 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=662685072 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.xbar_stress_all_with_error.662685072 |
| Directory | /workspace/4.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/4.xbar_stress_all_with_rand_reset.2681275691 |
| Short name | T1659 |
| Test name | |
| Test status | |
| Simulation time | 482870530 ps |
| CPU time | 158.51 seconds |
| Started | Jun 29 08:11:33 PM PDT 24 |
| Finished | Jun 29 08:14:11 PM PDT 24 |
| Peak memory | 575456 kb |
| Host | smart-421ce19b-4da7-4d05-9a00-5bdccadb7a91 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2681275691 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.xbar_stress_all_ with_rand_reset.2681275691 |
| Directory | /workspace/4.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/4.xbar_stress_all_with_reset_error.3796352717 |
| Short name | T2055 |
| Test name | |
| Test status | |
| Simulation time | 3266596650 ps |
| CPU time | 260.79 seconds |
| Started | Jun 29 08:11:44 PM PDT 24 |
| Finished | Jun 29 08:16:06 PM PDT 24 |
| Peak memory | 574636 kb |
| Host | smart-d4b755e0-1f3d-474b-9595-1eb1a62938e6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3796352717 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.xbar_stress_all _with_reset_error.3796352717 |
| Directory | /workspace/4.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/4.xbar_unmapped_addr.3707398708 |
| Short name | T2803 |
| Test name | |
| Test status | |
| Simulation time | 999769052 ps |
| CPU time | 51.66 seconds |
| Started | Jun 29 08:11:16 PM PDT 24 |
| Finished | Jun 29 08:12:08 PM PDT 24 |
| Peak memory | 575336 kb |
| Host | smart-f0e5cd01-b2b5-44ad-b455-a41992ccc293 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3707398708 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.xbar_unmapped_addr.3707398708 |
| Directory | /workspace/4.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/40.xbar_access_same_device.3253353939 |
| Short name | T1507 |
| Test name | |
| Test status | |
| Simulation time | 3634244575 ps |
| CPU time | 147.33 seconds |
| Started | Jun 29 08:21:49 PM PDT 24 |
| Finished | Jun 29 08:24:16 PM PDT 24 |
| Peak memory | 575388 kb |
| Host | smart-f2edb3d4-5110-4681-b874-aa8d635296c8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3253353939 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.xbar_access_same_device .3253353939 |
| Directory | /workspace/40.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/40.xbar_error_and_unmapped_addr.1647652575 |
| Short name | T2279 |
| Test name | |
| Test status | |
| Simulation time | 505108690 ps |
| CPU time | 24.37 seconds |
| Started | Jun 29 08:21:51 PM PDT 24 |
| Finished | Jun 29 08:22:16 PM PDT 24 |
| Peak memory | 574512 kb |
| Host | smart-fab57351-6309-4adf-b2c1-8668613daef9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1647652575 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.xbar_error_and_unmapped_add r.1647652575 |
| Directory | /workspace/40.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/40.xbar_error_random.1202262662 |
| Short name | T2074 |
| Test name | |
| Test status | |
| Simulation time | 2230046256 ps |
| CPU time | 75.57 seconds |
| Started | Jun 29 08:21:49 PM PDT 24 |
| Finished | Jun 29 08:23:04 PM PDT 24 |
| Peak memory | 573980 kb |
| Host | smart-d4858c66-7f97-4fde-b6e8-7fa25864bf89 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1202262662 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.xbar_error_random.1202262662 |
| Directory | /workspace/40.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/40.xbar_random.2327748911 |
| Short name | T2467 |
| Test name | |
| Test status | |
| Simulation time | 1586202858 ps |
| CPU time | 71.16 seconds |
| Started | Jun 29 08:21:53 PM PDT 24 |
| Finished | Jun 29 08:23:04 PM PDT 24 |
| Peak memory | 574240 kb |
| Host | smart-20529b90-942b-44eb-8ee2-32ae6e795b30 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2327748911 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.xbar_random.2327748911 |
| Directory | /workspace/40.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/40.xbar_random_large_delays.1742989036 |
| Short name | T1532 |
| Test name | |
| Test status | |
| Simulation time | 60486270203 ps |
| CPU time | 650.71 seconds |
| Started | Jun 29 08:21:48 PM PDT 24 |
| Finished | Jun 29 08:32:40 PM PDT 24 |
| Peak memory | 575420 kb |
| Host | smart-f918cec1-2845-4354-a628-178186ad7c0d |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1742989036 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.xbar_random_large_delays.1742989036 |
| Directory | /workspace/40.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/40.xbar_random_slow_rsp.3316067089 |
| Short name | T1629 |
| Test name | |
| Test status | |
| Simulation time | 28177443869 ps |
| CPU time | 470.76 seconds |
| Started | Jun 29 08:21:49 PM PDT 24 |
| Finished | Jun 29 08:29:40 PM PDT 24 |
| Peak memory | 575392 kb |
| Host | smart-742d9f10-5f87-42c8-8f4d-66d230368427 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3316067089 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.xbar_random_slow_rsp.3316067089 |
| Directory | /workspace/40.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/40.xbar_random_zero_delays.4042078834 |
| Short name | T1973 |
| Test name | |
| Test status | |
| Simulation time | 361248636 ps |
| CPU time | 35.25 seconds |
| Started | Jun 29 08:21:49 PM PDT 24 |
| Finished | Jun 29 08:22:25 PM PDT 24 |
| Peak memory | 575320 kb |
| Host | smart-d9c09536-360d-4f68-9654-870222d98c9e |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4042078834 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.xbar_random_zero_del ays.4042078834 |
| Directory | /workspace/40.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/40.xbar_same_source.1249456745 |
| Short name | T1457 |
| Test name | |
| Test status | |
| Simulation time | 256590258 ps |
| CPU time | 22.21 seconds |
| Started | Jun 29 08:21:48 PM PDT 24 |
| Finished | Jun 29 08:22:10 PM PDT 24 |
| Peak memory | 574244 kb |
| Host | smart-8fc36cf0-c783-464f-8344-632473806c14 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1249456745 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.xbar_same_source.1249456745 |
| Directory | /workspace/40.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/40.xbar_smoke.2341004780 |
| Short name | T1637 |
| Test name | |
| Test status | |
| Simulation time | 42550062 ps |
| CPU time | 6.3 seconds |
| Started | Jun 29 08:21:46 PM PDT 24 |
| Finished | Jun 29 08:21:52 PM PDT 24 |
| Peak memory | 574216 kb |
| Host | smart-47636cfc-1926-4503-8a6b-9418253f8af7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2341004780 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.xbar_smoke.2341004780 |
| Directory | /workspace/40.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/40.xbar_smoke_large_delays.2383513384 |
| Short name | T2698 |
| Test name | |
| Test status | |
| Simulation time | 6944722371 ps |
| CPU time | 74.88 seconds |
| Started | Jun 29 08:21:47 PM PDT 24 |
| Finished | Jun 29 08:23:02 PM PDT 24 |
| Peak memory | 574284 kb |
| Host | smart-7f536b31-5bca-4d9e-8992-80a3d63c3eb1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2383513384 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.xbar_smoke_large_delays.2383513384 |
| Directory | /workspace/40.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/40.xbar_smoke_slow_rsp.1122949473 |
| Short name | T1626 |
| Test name | |
| Test status | |
| Simulation time | 4669847051 ps |
| CPU time | 80.75 seconds |
| Started | Jun 29 08:21:48 PM PDT 24 |
| Finished | Jun 29 08:23:09 PM PDT 24 |
| Peak memory | 566088 kb |
| Host | smart-48c244fe-8fc6-4db0-a2d7-80f319b44cef |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1122949473 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.xbar_smoke_slow_rsp.1122949473 |
| Directory | /workspace/40.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/40.xbar_smoke_zero_delays.4261255419 |
| Short name | T1418 |
| Test name | |
| Test status | |
| Simulation time | 42244902 ps |
| CPU time | 6.38 seconds |
| Started | Jun 29 08:21:53 PM PDT 24 |
| Finished | Jun 29 08:22:00 PM PDT 24 |
| Peak memory | 574160 kb |
| Host | smart-fdd4a985-cc8f-4202-8193-e94c03a52a8a |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4261255419 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.xbar_smoke_zero_delay s.4261255419 |
| Directory | /workspace/40.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/40.xbar_stress_all.3049711266 |
| Short name | T597 |
| Test name | |
| Test status | |
| Simulation time | 1571113268 ps |
| CPU time | 70.71 seconds |
| Started | Jun 29 08:21:53 PM PDT 24 |
| Finished | Jun 29 08:23:04 PM PDT 24 |
| Peak memory | 574228 kb |
| Host | smart-4729c2fb-5bef-49de-9c5b-1a52c0f62189 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3049711266 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.xbar_stress_all.3049711266 |
| Directory | /workspace/40.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/40.xbar_stress_all_with_error.1490313336 |
| Short name | T638 |
| Test name | |
| Test status | |
| Simulation time | 11077588142 ps |
| CPU time | 437.61 seconds |
| Started | Jun 29 08:21:52 PM PDT 24 |
| Finished | Jun 29 08:29:10 PM PDT 24 |
| Peak memory | 574436 kb |
| Host | smart-d90b22a0-f67a-4493-a297-099c724e7722 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1490313336 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.xbar_stress_all_with_error.1490313336 |
| Directory | /workspace/40.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/40.xbar_stress_all_with_rand_reset.236039398 |
| Short name | T465 |
| Test name | |
| Test status | |
| Simulation time | 8003880104 ps |
| CPU time | 573.74 seconds |
| Started | Jun 29 08:21:53 PM PDT 24 |
| Finished | Jun 29 08:31:27 PM PDT 24 |
| Peak memory | 575488 kb |
| Host | smart-5683b12b-58a5-4211-b5fb-12a708803fbc |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=236039398 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_res et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.xbar_stress_all_ with_rand_reset.236039398 |
| Directory | /workspace/40.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/40.xbar_stress_all_with_reset_error.2165203472 |
| Short name | T2476 |
| Test name | |
| Test status | |
| Simulation time | 6273487838 ps |
| CPU time | 328.41 seconds |
| Started | Jun 29 08:22:00 PM PDT 24 |
| Finished | Jun 29 08:27:28 PM PDT 24 |
| Peak memory | 576516 kb |
| Host | smart-91881295-c9bd-49ba-afee-95a5f7c1ad38 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2165203472 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.xbar_stress_al l_with_reset_error.2165203472 |
| Directory | /workspace/40.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/40.xbar_unmapped_addr.3978092562 |
| Short name | T2744 |
| Test name | |
| Test status | |
| Simulation time | 182583789 ps |
| CPU time | 25.44 seconds |
| Started | Jun 29 08:21:48 PM PDT 24 |
| Finished | Jun 29 08:22:14 PM PDT 24 |
| Peak memory | 575368 kb |
| Host | smart-97132c6a-ccd0-427f-9667-47c5668bdb68 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3978092562 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.xbar_unmapped_addr.3978092562 |
| Directory | /workspace/40.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/41.xbar_access_same_device.3500801671 |
| Short name | T779 |
| Test name | |
| Test status | |
| Simulation time | 2190976294 ps |
| CPU time | 103.63 seconds |
| Started | Jun 29 08:22:00 PM PDT 24 |
| Finished | Jun 29 08:23:44 PM PDT 24 |
| Peak memory | 575416 kb |
| Host | smart-f3aa0683-8989-4d08-892a-2e5243dc56df |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3500801671 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.xbar_access_same_device .3500801671 |
| Directory | /workspace/41.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/41.xbar_access_same_device_slow_rsp.2291531750 |
| Short name | T1661 |
| Test name | |
| Test status | |
| Simulation time | 55836241827 ps |
| CPU time | 966.21 seconds |
| Started | Jun 29 08:22:01 PM PDT 24 |
| Finished | Jun 29 08:38:08 PM PDT 24 |
| Peak memory | 574328 kb |
| Host | smart-513dbfa9-15c0-4eb9-9b0e-6260c0637f7a |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2291531750 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.xbar_access_same_ device_slow_rsp.2291531750 |
| Directory | /workspace/41.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/41.xbar_error_and_unmapped_addr.7733538 |
| Short name | T1292 |
| Test name | |
| Test status | |
| Simulation time | 108241667 ps |
| CPU time | 15.23 seconds |
| Started | Jun 29 08:21:57 PM PDT 24 |
| Finished | Jun 29 08:22:12 PM PDT 24 |
| Peak memory | 574508 kb |
| Host | smart-fde88c58-7271-4e19-a6d4-54c3cebb3a39 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=7733538 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.xbar_error_and_unmapped_addr.7733538 |
| Directory | /workspace/41.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/41.xbar_error_random.908734730 |
| Short name | T1496 |
| Test name | |
| Test status | |
| Simulation time | 95455183 ps |
| CPU time | 11.72 seconds |
| Started | Jun 29 08:21:59 PM PDT 24 |
| Finished | Jun 29 08:22:11 PM PDT 24 |
| Peak memory | 574248 kb |
| Host | smart-49b8cf8d-eb98-4991-9377-9bcfcd09b03e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=908734730 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.xbar_error_random.908734730 |
| Directory | /workspace/41.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/41.xbar_random.1967578655 |
| Short name | T1913 |
| Test name | |
| Test status | |
| Simulation time | 2423860111 ps |
| CPU time | 104.56 seconds |
| Started | Jun 29 08:21:59 PM PDT 24 |
| Finished | Jun 29 08:23:44 PM PDT 24 |
| Peak memory | 575368 kb |
| Host | smart-c7db2580-0f16-4b02-b570-48d284485cf9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1967578655 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.xbar_random.1967578655 |
| Directory | /workspace/41.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/41.xbar_random_large_delays.3957319113 |
| Short name | T2098 |
| Test name | |
| Test status | |
| Simulation time | 71187036902 ps |
| CPU time | 779.69 seconds |
| Started | Jun 29 08:21:57 PM PDT 24 |
| Finished | Jun 29 08:34:57 PM PDT 24 |
| Peak memory | 575412 kb |
| Host | smart-24d7cf07-42d7-4152-8993-600b07d1ef3b |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3957319113 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.xbar_random_large_delays.3957319113 |
| Directory | /workspace/41.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/41.xbar_random_slow_rsp.3170116013 |
| Short name | T1369 |
| Test name | |
| Test status | |
| Simulation time | 38312532680 ps |
| CPU time | 691.07 seconds |
| Started | Jun 29 08:22:00 PM PDT 24 |
| Finished | Jun 29 08:33:31 PM PDT 24 |
| Peak memory | 575404 kb |
| Host | smart-badd380f-ae4c-48f6-a03e-9f309ee76c66 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3170116013 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.xbar_random_slow_rsp.3170116013 |
| Directory | /workspace/41.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/41.xbar_random_zero_delays.2048818487 |
| Short name | T1442 |
| Test name | |
| Test status | |
| Simulation time | 34536370 ps |
| CPU time | 6.83 seconds |
| Started | Jun 29 08:21:57 PM PDT 24 |
| Finished | Jun 29 08:22:04 PM PDT 24 |
| Peak memory | 574272 kb |
| Host | smart-f90d5dfe-010d-4001-8700-2402d67134a6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2048818487 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.xbar_random_zero_del ays.2048818487 |
| Directory | /workspace/41.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/41.xbar_same_source.2463605505 |
| Short name | T1838 |
| Test name | |
| Test status | |
| Simulation time | 1293423245 ps |
| CPU time | 44.71 seconds |
| Started | Jun 29 08:21:57 PM PDT 24 |
| Finished | Jun 29 08:22:42 PM PDT 24 |
| Peak memory | 575296 kb |
| Host | smart-ea830237-aba0-4281-8773-bc8d6b40e359 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2463605505 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.xbar_same_source.2463605505 |
| Directory | /workspace/41.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/41.xbar_smoke.1546677172 |
| Short name | T2009 |
| Test name | |
| Test status | |
| Simulation time | 38751586 ps |
| CPU time | 6.48 seconds |
| Started | Jun 29 08:21:59 PM PDT 24 |
| Finished | Jun 29 08:22:06 PM PDT 24 |
| Peak memory | 565932 kb |
| Host | smart-ec1566d1-2e06-4b05-ac20-a3a1d4a2a45a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1546677172 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.xbar_smoke.1546677172 |
| Directory | /workspace/41.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/41.xbar_smoke_large_delays.847182382 |
| Short name | T2704 |
| Test name | |
| Test status | |
| Simulation time | 10560383967 ps |
| CPU time | 108.89 seconds |
| Started | Jun 29 08:22:01 PM PDT 24 |
| Finished | Jun 29 08:23:50 PM PDT 24 |
| Peak memory | 574236 kb |
| Host | smart-e070f67c-fa6c-4121-8db3-253ded47ed7e |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=847182382 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.xbar_smoke_large_delays.847182382 |
| Directory | /workspace/41.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/41.xbar_smoke_slow_rsp.2560656988 |
| Short name | T1601 |
| Test name | |
| Test status | |
| Simulation time | 5709526393 ps |
| CPU time | 102.77 seconds |
| Started | Jun 29 08:22:01 PM PDT 24 |
| Finished | Jun 29 08:23:44 PM PDT 24 |
| Peak memory | 574324 kb |
| Host | smart-cbb13de8-560d-4fe2-81d4-390831f3a027 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2560656988 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.xbar_smoke_slow_rsp.2560656988 |
| Directory | /workspace/41.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/41.xbar_smoke_zero_delays.4028059602 |
| Short name | T2282 |
| Test name | |
| Test status | |
| Simulation time | 40768935 ps |
| CPU time | 6.63 seconds |
| Started | Jun 29 08:21:58 PM PDT 24 |
| Finished | Jun 29 08:22:06 PM PDT 24 |
| Peak memory | 574256 kb |
| Host | smart-c0b7f995-dd63-48f6-902c-0e07f9c8ee3a |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4028059602 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.xbar_smoke_zero_delay s.4028059602 |
| Directory | /workspace/41.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/41.xbar_stress_all.3531625105 |
| Short name | T2179 |
| Test name | |
| Test status | |
| Simulation time | 1060843710 ps |
| CPU time | 101.84 seconds |
| Started | Jun 29 08:22:04 PM PDT 24 |
| Finished | Jun 29 08:23:46 PM PDT 24 |
| Peak memory | 575384 kb |
| Host | smart-617b73ca-ee54-4c70-9fe6-84725ac09070 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3531625105 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.xbar_stress_all.3531625105 |
| Directory | /workspace/41.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/41.xbar_stress_all_with_error.2539710481 |
| Short name | T2046 |
| Test name | |
| Test status | |
| Simulation time | 8433232983 ps |
| CPU time | 295.32 seconds |
| Started | Jun 29 08:22:04 PM PDT 24 |
| Finished | Jun 29 08:27:00 PM PDT 24 |
| Peak memory | 574724 kb |
| Host | smart-3b7abf35-b4b1-4921-97cb-58b8004c2889 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2539710481 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.xbar_stress_all_with_error.2539710481 |
| Directory | /workspace/41.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/41.xbar_stress_all_with_rand_reset.3460947913 |
| Short name | T2682 |
| Test name | |
| Test status | |
| Simulation time | 533819752 ps |
| CPU time | 134.7 seconds |
| Started | Jun 29 08:22:09 PM PDT 24 |
| Finished | Jun 29 08:24:24 PM PDT 24 |
| Peak memory | 575424 kb |
| Host | smart-cedc3ca1-a7c0-4222-b871-a0a1f97897a6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3460947913 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.xbar_stress_all _with_rand_reset.3460947913 |
| Directory | /workspace/41.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/41.xbar_stress_all_with_reset_error.3816779854 |
| Short name | T2365 |
| Test name | |
| Test status | |
| Simulation time | 1306567286 ps |
| CPU time | 258.04 seconds |
| Started | Jun 29 08:22:05 PM PDT 24 |
| Finished | Jun 29 08:26:24 PM PDT 24 |
| Peak memory | 574688 kb |
| Host | smart-557463df-c902-460f-81a7-923c573d84cc |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3816779854 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.xbar_stress_al l_with_reset_error.3816779854 |
| Directory | /workspace/41.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/41.xbar_unmapped_addr.3396665372 |
| Short name | T2826 |
| Test name | |
| Test status | |
| Simulation time | 249847966 ps |
| CPU time | 33.24 seconds |
| Started | Jun 29 08:21:59 PM PDT 24 |
| Finished | Jun 29 08:22:32 PM PDT 24 |
| Peak memory | 575376 kb |
| Host | smart-569b7eb7-57a0-4910-a57e-b0d030b17e8d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3396665372 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.xbar_unmapped_addr.3396665372 |
| Directory | /workspace/41.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/42.xbar_access_same_device.1821969328 |
| Short name | T2764 |
| Test name | |
| Test status | |
| Simulation time | 948175027 ps |
| CPU time | 78.85 seconds |
| Started | Jun 29 08:22:13 PM PDT 24 |
| Finished | Jun 29 08:23:32 PM PDT 24 |
| Peak memory | 575340 kb |
| Host | smart-014295db-ef46-428b-9a64-6730079b3435 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1821969328 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.xbar_access_same_device .1821969328 |
| Directory | /workspace/42.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/42.xbar_access_same_device_slow_rsp.587794259 |
| Short name | T2326 |
| Test name | |
| Test status | |
| Simulation time | 116663223669 ps |
| CPU time | 2034.96 seconds |
| Started | Jun 29 08:22:12 PM PDT 24 |
| Finished | Jun 29 08:56:07 PM PDT 24 |
| Peak memory | 575508 kb |
| Host | smart-ef6f6dd6-1d42-4beb-90c2-abb9c446ef52 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=587794259 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.xbar_access_same_d evice_slow_rsp.587794259 |
| Directory | /workspace/42.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/42.xbar_error_and_unmapped_addr.1705202168 |
| Short name | T1555 |
| Test name | |
| Test status | |
| Simulation time | 339647239 ps |
| CPU time | 18.97 seconds |
| Started | Jun 29 08:22:10 PM PDT 24 |
| Finished | Jun 29 08:22:30 PM PDT 24 |
| Peak memory | 573848 kb |
| Host | smart-7c12f5f5-7edf-4aa1-9f1f-859710d3fae9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1705202168 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.xbar_error_and_unmapped_add r.1705202168 |
| Directory | /workspace/42.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/42.xbar_error_random.1509345252 |
| Short name | T2005 |
| Test name | |
| Test status | |
| Simulation time | 1627850504 ps |
| CPU time | 57.84 seconds |
| Started | Jun 29 08:22:16 PM PDT 24 |
| Finished | Jun 29 08:23:14 PM PDT 24 |
| Peak memory | 574500 kb |
| Host | smart-a6e42e0a-5cf8-4dbe-8bf4-66c9aad9aadf |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1509345252 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.xbar_error_random.1509345252 |
| Directory | /workspace/42.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/42.xbar_random.3718879083 |
| Short name | T1600 |
| Test name | |
| Test status | |
| Simulation time | 1235253257 ps |
| CPU time | 51.14 seconds |
| Started | Jun 29 08:22:11 PM PDT 24 |
| Finished | Jun 29 08:23:03 PM PDT 24 |
| Peak memory | 575312 kb |
| Host | smart-e3942e0e-abb5-42fa-b6ea-d02d2d9241c0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3718879083 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.xbar_random.3718879083 |
| Directory | /workspace/42.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/42.xbar_random_large_delays.205734511 |
| Short name | T1318 |
| Test name | |
| Test status | |
| Simulation time | 5952797151 ps |
| CPU time | 66.49 seconds |
| Started | Jun 29 08:22:13 PM PDT 24 |
| Finished | Jun 29 08:23:20 PM PDT 24 |
| Peak memory | 574224 kb |
| Host | smart-b9a3bb87-4444-4af0-8fe9-add5982dbf8c |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=205734511 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.xbar_random_large_delays.205734511 |
| Directory | /workspace/42.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/42.xbar_random_slow_rsp.1431526460 |
| Short name | T1682 |
| Test name | |
| Test status | |
| Simulation time | 17584050860 ps |
| CPU time | 303.28 seconds |
| Started | Jun 29 08:22:12 PM PDT 24 |
| Finished | Jun 29 08:27:16 PM PDT 24 |
| Peak memory | 574328 kb |
| Host | smart-d35db270-37a8-42d3-af22-c220cf0d2633 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1431526460 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.xbar_random_slow_rsp.1431526460 |
| Directory | /workspace/42.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/42.xbar_random_zero_delays.3879688633 |
| Short name | T1561 |
| Test name | |
| Test status | |
| Simulation time | 217585975 ps |
| CPU time | 23.56 seconds |
| Started | Jun 29 08:22:03 PM PDT 24 |
| Finished | Jun 29 08:22:27 PM PDT 24 |
| Peak memory | 574284 kb |
| Host | smart-d634be5d-148a-4909-bd45-1eccfad485fc |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3879688633 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.xbar_random_zero_del ays.3879688633 |
| Directory | /workspace/42.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/42.xbar_same_source.2608787398 |
| Short name | T1852 |
| Test name | |
| Test status | |
| Simulation time | 1704651985 ps |
| CPU time | 52.92 seconds |
| Started | Jun 29 08:22:10 PM PDT 24 |
| Finished | Jun 29 08:23:03 PM PDT 24 |
| Peak memory | 575284 kb |
| Host | smart-ecce49f4-43df-4e7a-9479-2514538ff857 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2608787398 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.xbar_same_source.2608787398 |
| Directory | /workspace/42.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/42.xbar_smoke.3428410839 |
| Short name | T1677 |
| Test name | |
| Test status | |
| Simulation time | 46330498 ps |
| CPU time | 6.86 seconds |
| Started | Jun 29 08:22:12 PM PDT 24 |
| Finished | Jun 29 08:22:19 PM PDT 24 |
| Peak memory | 566008 kb |
| Host | smart-554e1fe2-0124-403d-8391-a1a0f165d2a1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3428410839 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.xbar_smoke.3428410839 |
| Directory | /workspace/42.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/42.xbar_smoke_large_delays.3505890669 |
| Short name | T1801 |
| Test name | |
| Test status | |
| Simulation time | 5591262910 ps |
| CPU time | 62.25 seconds |
| Started | Jun 29 08:22:04 PM PDT 24 |
| Finished | Jun 29 08:23:06 PM PDT 24 |
| Peak memory | 574328 kb |
| Host | smart-8e8afe75-383a-4ac6-a449-80134be65606 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3505890669 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.xbar_smoke_large_delays.3505890669 |
| Directory | /workspace/42.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/42.xbar_smoke_slow_rsp.4059214131 |
| Short name | T1443 |
| Test name | |
| Test status | |
| Simulation time | 4686546501 ps |
| CPU time | 76.47 seconds |
| Started | Jun 29 08:22:03 PM PDT 24 |
| Finished | Jun 29 08:23:19 PM PDT 24 |
| Peak memory | 574144 kb |
| Host | smart-159aaab6-37b8-47a9-b2e3-9916901d31ab |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4059214131 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.xbar_smoke_slow_rsp.4059214131 |
| Directory | /workspace/42.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/42.xbar_smoke_zero_delays.2195679926 |
| Short name | T1588 |
| Test name | |
| Test status | |
| Simulation time | 38266138 ps |
| CPU time | 6.51 seconds |
| Started | Jun 29 08:22:08 PM PDT 24 |
| Finished | Jun 29 08:22:15 PM PDT 24 |
| Peak memory | 574256 kb |
| Host | smart-7420c832-b0cc-4146-9bda-47446a8e5557 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2195679926 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.xbar_smoke_zero_delay s.2195679926 |
| Directory | /workspace/42.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/42.xbar_stress_all.2158446257 |
| Short name | T485 |
| Test name | |
| Test status | |
| Simulation time | 741288901 ps |
| CPU time | 40.71 seconds |
| Started | Jun 29 08:22:11 PM PDT 24 |
| Finished | Jun 29 08:22:52 PM PDT 24 |
| Peak memory | 574312 kb |
| Host | smart-09f07931-3756-4bc3-89ab-8c75a0f42e0c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2158446257 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.xbar_stress_all.2158446257 |
| Directory | /workspace/42.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/42.xbar_stress_all_with_rand_reset.1375341500 |
| Short name | T617 |
| Test name | |
| Test status | |
| Simulation time | 13372914418 ps |
| CPU time | 686.71 seconds |
| Started | Jun 29 08:22:16 PM PDT 24 |
| Finished | Jun 29 08:33:43 PM PDT 24 |
| Peak memory | 575516 kb |
| Host | smart-af3a3913-42ec-48ff-8835-80eb731317ac |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1375341500 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.xbar_stress_all _with_rand_reset.1375341500 |
| Directory | /workspace/42.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/42.xbar_stress_all_with_reset_error.333224928 |
| Short name | T599 |
| Test name | |
| Test status | |
| Simulation time | 2563718088 ps |
| CPU time | 226.76 seconds |
| Started | Jun 29 08:22:10 PM PDT 24 |
| Finished | Jun 29 08:25:57 PM PDT 24 |
| Peak memory | 574716 kb |
| Host | smart-1a351220-ef72-47ef-ab78-553bba98a82b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=333224928 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.xbar_stress_all _with_reset_error.333224928 |
| Directory | /workspace/42.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/42.xbar_unmapped_addr.138433978 |
| Short name | T1477 |
| Test name | |
| Test status | |
| Simulation time | 273167672 ps |
| CPU time | 32.12 seconds |
| Started | Jun 29 08:22:13 PM PDT 24 |
| Finished | Jun 29 08:22:45 PM PDT 24 |
| Peak memory | 575376 kb |
| Host | smart-98aea756-5ed3-4dff-bf51-4f1af5717ead |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=138433978 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.xbar_unmapped_addr.138433978 |
| Directory | /workspace/42.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/43.xbar_access_same_device.3426568271 |
| Short name | T2340 |
| Test name | |
| Test status | |
| Simulation time | 1512960042 ps |
| CPU time | 71.79 seconds |
| Started | Jun 29 08:22:19 PM PDT 24 |
| Finished | Jun 29 08:23:31 PM PDT 24 |
| Peak memory | 575312 kb |
| Host | smart-50442c4f-20ea-40b0-b77a-fb11cecef127 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3426568271 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.xbar_access_same_device .3426568271 |
| Directory | /workspace/43.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/43.xbar_access_same_device_slow_rsp.515403607 |
| Short name | T482 |
| Test name | |
| Test status | |
| Simulation time | 128857429063 ps |
| CPU time | 2196.14 seconds |
| Started | Jun 29 08:22:19 PM PDT 24 |
| Finished | Jun 29 08:58:56 PM PDT 24 |
| Peak memory | 575508 kb |
| Host | smart-a6a0f9de-16b5-4573-aa03-c1b555e59f54 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=515403607 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.xbar_access_same_d evice_slow_rsp.515403607 |
| Directory | /workspace/43.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/43.xbar_error_and_unmapped_addr.1344973531 |
| Short name | T1566 |
| Test name | |
| Test status | |
| Simulation time | 303653814 ps |
| CPU time | 38.34 seconds |
| Started | Jun 29 08:22:18 PM PDT 24 |
| Finished | Jun 29 08:22:57 PM PDT 24 |
| Peak memory | 573928 kb |
| Host | smart-b6c91dd8-02d8-48c9-aa28-6f100b297610 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1344973531 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.xbar_error_and_unmapped_add r.1344973531 |
| Directory | /workspace/43.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/43.xbar_error_random.281866805 |
| Short name | T2077 |
| Test name | |
| Test status | |
| Simulation time | 373922730 ps |
| CPU time | 37.09 seconds |
| Started | Jun 29 08:22:21 PM PDT 24 |
| Finished | Jun 29 08:22:59 PM PDT 24 |
| Peak memory | 574256 kb |
| Host | smart-cd2bd90a-988e-46c3-9819-ea9ed1c57643 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=281866805 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.xbar_error_random.281866805 |
| Directory | /workspace/43.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/43.xbar_random.3445497933 |
| Short name | T2240 |
| Test name | |
| Test status | |
| Simulation time | 211831066 ps |
| CPU time | 24.94 seconds |
| Started | Jun 29 08:22:21 PM PDT 24 |
| Finished | Jun 29 08:22:47 PM PDT 24 |
| Peak memory | 575300 kb |
| Host | smart-0fc35e78-900d-4ddf-90b7-dee7f2b394e2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3445497933 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.xbar_random.3445497933 |
| Directory | /workspace/43.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/43.xbar_random_large_delays.2627039386 |
| Short name | T1599 |
| Test name | |
| Test status | |
| Simulation time | 107956433781 ps |
| CPU time | 1144.54 seconds |
| Started | Jun 29 08:22:19 PM PDT 24 |
| Finished | Jun 29 08:41:24 PM PDT 24 |
| Peak memory | 575396 kb |
| Host | smart-6d42d7dc-f212-4864-a5a2-144bfd56d3fa |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2627039386 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.xbar_random_large_delays.2627039386 |
| Directory | /workspace/43.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/43.xbar_random_slow_rsp.1000823418 |
| Short name | T226 |
| Test name | |
| Test status | |
| Simulation time | 59187811009 ps |
| CPU time | 1029.8 seconds |
| Started | Jun 29 08:22:22 PM PDT 24 |
| Finished | Jun 29 08:39:33 PM PDT 24 |
| Peak memory | 574340 kb |
| Host | smart-adbdeec0-3e3e-4128-8cc0-d1f7a34063f3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1000823418 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.xbar_random_slow_rsp.1000823418 |
| Directory | /workspace/43.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/43.xbar_random_zero_delays.1097981796 |
| Short name | T1576 |
| Test name | |
| Test status | |
| Simulation time | 472258320 ps |
| CPU time | 45.3 seconds |
| Started | Jun 29 08:22:21 PM PDT 24 |
| Finished | Jun 29 08:23:06 PM PDT 24 |
| Peak memory | 575304 kb |
| Host | smart-2a4efac0-4412-41fd-9d1e-1470b3f13dec |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1097981796 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.xbar_random_zero_del ays.1097981796 |
| Directory | /workspace/43.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/43.xbar_same_source.385323959 |
| Short name | T2681 |
| Test name | |
| Test status | |
| Simulation time | 1187812169 ps |
| CPU time | 36.85 seconds |
| Started | Jun 29 08:22:19 PM PDT 24 |
| Finished | Jun 29 08:22:57 PM PDT 24 |
| Peak memory | 574232 kb |
| Host | smart-86cfceb0-c772-4075-a57a-e5a4b6b749bc |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=385323959 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.xbar_same_source.385323959 |
| Directory | /workspace/43.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/43.xbar_smoke.746184784 |
| Short name | T2521 |
| Test name | |
| Test status | |
| Simulation time | 41872853 ps |
| CPU time | 6.61 seconds |
| Started | Jun 29 08:22:10 PM PDT 24 |
| Finished | Jun 29 08:22:17 PM PDT 24 |
| Peak memory | 574252 kb |
| Host | smart-0fb9c39e-6801-4874-8020-87a0e97fdaed |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=746184784 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.xbar_smoke.746184784 |
| Directory | /workspace/43.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/43.xbar_smoke_large_delays.4231221598 |
| Short name | T1605 |
| Test name | |
| Test status | |
| Simulation time | 9273043752 ps |
| CPU time | 102.9 seconds |
| Started | Jun 29 08:22:10 PM PDT 24 |
| Finished | Jun 29 08:23:53 PM PDT 24 |
| Peak memory | 574328 kb |
| Host | smart-f63588cd-8431-43e2-95e5-363c9c11f535 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4231221598 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.xbar_smoke_large_delays.4231221598 |
| Directory | /workspace/43.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/43.xbar_smoke_slow_rsp.1356264063 |
| Short name | T1402 |
| Test name | |
| Test status | |
| Simulation time | 3475107067 ps |
| CPU time | 61.52 seconds |
| Started | Jun 29 08:22:12 PM PDT 24 |
| Finished | Jun 29 08:23:14 PM PDT 24 |
| Peak memory | 574136 kb |
| Host | smart-14b30ab9-06d8-4d83-ac1a-7d0c12964ac6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1356264063 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.xbar_smoke_slow_rsp.1356264063 |
| Directory | /workspace/43.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/43.xbar_smoke_zero_delays.2541576142 |
| Short name | T1334 |
| Test name | |
| Test status | |
| Simulation time | 37589672 ps |
| CPU time | 5.96 seconds |
| Started | Jun 29 08:22:16 PM PDT 24 |
| Finished | Jun 29 08:22:22 PM PDT 24 |
| Peak memory | 565956 kb |
| Host | smart-c3a0bded-24de-41ec-8f2f-805228c9254c |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2541576142 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.xbar_smoke_zero_delay s.2541576142 |
| Directory | /workspace/43.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/43.xbar_stress_all.4183777241 |
| Short name | T2017 |
| Test name | |
| Test status | |
| Simulation time | 4257775488 ps |
| CPU time | 148.78 seconds |
| Started | Jun 29 08:22:18 PM PDT 24 |
| Finished | Jun 29 08:24:47 PM PDT 24 |
| Peak memory | 575448 kb |
| Host | smart-e52a21ab-2f07-4ccc-bcc7-788a64a6bf6c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4183777241 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.xbar_stress_all.4183777241 |
| Directory | /workspace/43.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/43.xbar_stress_all_with_error.4280080940 |
| Short name | T2703 |
| Test name | |
| Test status | |
| Simulation time | 11055365652 ps |
| CPU time | 412.29 seconds |
| Started | Jun 29 08:22:27 PM PDT 24 |
| Finished | Jun 29 08:29:20 PM PDT 24 |
| Peak memory | 574676 kb |
| Host | smart-c370d5dc-be96-4908-b060-68af677396f6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4280080940 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.xbar_stress_all_with_error.4280080940 |
| Directory | /workspace/43.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/43.xbar_stress_all_with_rand_reset.2264517439 |
| Short name | T2740 |
| Test name | |
| Test status | |
| Simulation time | 3687092430 ps |
| CPU time | 278.22 seconds |
| Started | Jun 29 08:22:21 PM PDT 24 |
| Finished | Jun 29 08:27:00 PM PDT 24 |
| Peak memory | 574456 kb |
| Host | smart-d60e9ba8-32d4-4b4c-9984-d54362b04d7c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2264517439 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.xbar_stress_all _with_rand_reset.2264517439 |
| Directory | /workspace/43.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/43.xbar_stress_all_with_reset_error.4225321380 |
| Short name | T805 |
| Test name | |
| Test status | |
| Simulation time | 124861379 ps |
| CPU time | 40.53 seconds |
| Started | Jun 29 08:22:27 PM PDT 24 |
| Finished | Jun 29 08:23:08 PM PDT 24 |
| Peak memory | 574428 kb |
| Host | smart-30442886-7d57-49f6-a0f3-9634ffbde3cc |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4225321380 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.xbar_stress_al l_with_reset_error.4225321380 |
| Directory | /workspace/43.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/43.xbar_unmapped_addr.4190162724 |
| Short name | T2244 |
| Test name | |
| Test status | |
| Simulation time | 364199505 ps |
| CPU time | 19.96 seconds |
| Started | Jun 29 08:22:19 PM PDT 24 |
| Finished | Jun 29 08:22:40 PM PDT 24 |
| Peak memory | 574276 kb |
| Host | smart-fa064b45-5ae6-48c5-b148-c09c348123d8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4190162724 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.xbar_unmapped_addr.4190162724 |
| Directory | /workspace/43.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/44.xbar_access_same_device.3183122854 |
| Short name | T1981 |
| Test name | |
| Test status | |
| Simulation time | 101284692 ps |
| CPU time | 9.89 seconds |
| Started | Jun 29 08:22:27 PM PDT 24 |
| Finished | Jun 29 08:22:37 PM PDT 24 |
| Peak memory | 574264 kb |
| Host | smart-68c48629-fcba-4444-9f2b-e542b618cf83 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3183122854 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.xbar_access_same_device .3183122854 |
| Directory | /workspace/44.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/44.xbar_access_same_device_slow_rsp.3293521153 |
| Short name | T1480 |
| Test name | |
| Test status | |
| Simulation time | 2834914748 ps |
| CPU time | 52.26 seconds |
| Started | Jun 29 08:22:32 PM PDT 24 |
| Finished | Jun 29 08:23:24 PM PDT 24 |
| Peak memory | 574164 kb |
| Host | smart-e95865ea-b82e-4698-b766-f08a14a5e1ca |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3293521153 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.xbar_access_same_ device_slow_rsp.3293521153 |
| Directory | /workspace/44.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/44.xbar_error_and_unmapped_addr.1932746543 |
| Short name | T2859 |
| Test name | |
| Test status | |
| Simulation time | 145702924 ps |
| CPU time | 19.18 seconds |
| Started | Jun 29 08:22:27 PM PDT 24 |
| Finished | Jun 29 08:22:47 PM PDT 24 |
| Peak memory | 574276 kb |
| Host | smart-73391d63-5e04-4d53-905d-5b4173bb1a56 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1932746543 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.xbar_error_and_unmapped_add r.1932746543 |
| Directory | /workspace/44.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/44.xbar_error_random.2930012664 |
| Short name | T2178 |
| Test name | |
| Test status | |
| Simulation time | 625731552 ps |
| CPU time | 55.23 seconds |
| Started | Jun 29 08:22:29 PM PDT 24 |
| Finished | Jun 29 08:23:25 PM PDT 24 |
| Peak memory | 574488 kb |
| Host | smart-eb18fd02-bdb5-4e90-958b-c935020d8262 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2930012664 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.xbar_error_random.2930012664 |
| Directory | /workspace/44.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/44.xbar_random.3070626270 |
| Short name | T2171 |
| Test name | |
| Test status | |
| Simulation time | 312512200 ps |
| CPU time | 31.31 seconds |
| Started | Jun 29 08:22:29 PM PDT 24 |
| Finished | Jun 29 08:23:01 PM PDT 24 |
| Peak memory | 575304 kb |
| Host | smart-720cf2b7-b6cf-4706-a8b5-953ecf4a4e32 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3070626270 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.xbar_random.3070626270 |
| Directory | /workspace/44.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/44.xbar_random_large_delays.2079162873 |
| Short name | T2071 |
| Test name | |
| Test status | |
| Simulation time | 109842692928 ps |
| CPU time | 1173.43 seconds |
| Started | Jun 29 08:22:26 PM PDT 24 |
| Finished | Jun 29 08:41:59 PM PDT 24 |
| Peak memory | 575404 kb |
| Host | smart-14524bf5-ad10-4014-8f0f-0dc1e70a9cc7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2079162873 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.xbar_random_large_delays.2079162873 |
| Directory | /workspace/44.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/44.xbar_random_slow_rsp.1638042431 |
| Short name | T1979 |
| Test name | |
| Test status | |
| Simulation time | 27052619793 ps |
| CPU time | 504.95 seconds |
| Started | Jun 29 08:22:26 PM PDT 24 |
| Finished | Jun 29 08:30:52 PM PDT 24 |
| Peak memory | 575400 kb |
| Host | smart-41e2d95f-9b96-4cae-b036-ba1f6d870500 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1638042431 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.xbar_random_slow_rsp.1638042431 |
| Directory | /workspace/44.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/44.xbar_random_zero_delays.2112484531 |
| Short name | T1323 |
| Test name | |
| Test status | |
| Simulation time | 35209489 ps |
| CPU time | 6.04 seconds |
| Started | Jun 29 08:22:27 PM PDT 24 |
| Finished | Jun 29 08:22:33 PM PDT 24 |
| Peak memory | 566036 kb |
| Host | smart-1c153a93-8f5e-4b54-876f-e670b99deca2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2112484531 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.xbar_random_zero_del ays.2112484531 |
| Directory | /workspace/44.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/44.xbar_same_source.87346275 |
| Short name | T1592 |
| Test name | |
| Test status | |
| Simulation time | 2132142089 ps |
| CPU time | 69.21 seconds |
| Started | Jun 29 08:22:28 PM PDT 24 |
| Finished | Jun 29 08:23:37 PM PDT 24 |
| Peak memory | 575300 kb |
| Host | smart-c741b330-6cea-44af-992d-eabd97d38e81 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87346275 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.xbar_same_source.87346275 |
| Directory | /workspace/44.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/44.xbar_smoke.1848303894 |
| Short name | T1783 |
| Test name | |
| Test status | |
| Simulation time | 55570590 ps |
| CPU time | 7.19 seconds |
| Started | Jun 29 08:22:30 PM PDT 24 |
| Finished | Jun 29 08:22:37 PM PDT 24 |
| Peak memory | 574268 kb |
| Host | smart-c5f19175-9670-4c54-961b-230075d2f44f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1848303894 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.xbar_smoke.1848303894 |
| Directory | /workspace/44.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/44.xbar_smoke_large_delays.2284436988 |
| Short name | T2434 |
| Test name | |
| Test status | |
| Simulation time | 8924664120 ps |
| CPU time | 94.8 seconds |
| Started | Jun 29 08:22:30 PM PDT 24 |
| Finished | Jun 29 08:24:05 PM PDT 24 |
| Peak memory | 566088 kb |
| Host | smart-aa66abf3-94a6-4ba4-aae2-5442995cef02 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2284436988 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.xbar_smoke_large_delays.2284436988 |
| Directory | /workspace/44.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/44.xbar_smoke_slow_rsp.2016910900 |
| Short name | T1699 |
| Test name | |
| Test status | |
| Simulation time | 4882585623 ps |
| CPU time | 89.22 seconds |
| Started | Jun 29 08:22:30 PM PDT 24 |
| Finished | Jun 29 08:23:59 PM PDT 24 |
| Peak memory | 574324 kb |
| Host | smart-3828a1e3-c795-483c-8dc9-572e9c6e5250 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2016910900 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.xbar_smoke_slow_rsp.2016910900 |
| Directory | /workspace/44.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/44.xbar_smoke_zero_delays.371226219 |
| Short name | T2884 |
| Test name | |
| Test status | |
| Simulation time | 52260015 ps |
| CPU time | 7.23 seconds |
| Started | Jun 29 08:22:26 PM PDT 24 |
| Finished | Jun 29 08:22:34 PM PDT 24 |
| Peak memory | 574256 kb |
| Host | smart-564848d4-2e01-436b-ac4d-c39b7c7bd9b4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=371226219 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.xbar_smoke_zero_delays .371226219 |
| Directory | /workspace/44.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/44.xbar_stress_all.863183535 |
| Short name | T511 |
| Test name | |
| Test status | |
| Simulation time | 9989525031 ps |
| CPU time | 360.59 seconds |
| Started | Jun 29 08:22:26 PM PDT 24 |
| Finished | Jun 29 08:28:27 PM PDT 24 |
| Peak memory | 575496 kb |
| Host | smart-27423b9b-a0db-453d-b416-016ab3def851 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=863183535 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.xbar_stress_all.863183535 |
| Directory | /workspace/44.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/44.xbar_stress_all_with_error.3098287790 |
| Short name | T2589 |
| Test name | |
| Test status | |
| Simulation time | 6469699129 ps |
| CPU time | 254.23 seconds |
| Started | Jun 29 08:22:35 PM PDT 24 |
| Finished | Jun 29 08:26:50 PM PDT 24 |
| Peak memory | 574720 kb |
| Host | smart-1159ed68-cb4d-4bf1-abea-d92fc21dc0fc |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3098287790 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.xbar_stress_all_with_error.3098287790 |
| Directory | /workspace/44.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/44.xbar_stress_all_with_rand_reset.1698083281 |
| Short name | T596 |
| Test name | |
| Test status | |
| Simulation time | 3467715403 ps |
| CPU time | 455.63 seconds |
| Started | Jun 29 08:22:28 PM PDT 24 |
| Finished | Jun 29 08:30:04 PM PDT 24 |
| Peak memory | 575480 kb |
| Host | smart-90c2e631-d14e-4c07-b0ec-57f7a268a521 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1698083281 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.xbar_stress_all _with_rand_reset.1698083281 |
| Directory | /workspace/44.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/44.xbar_stress_all_with_reset_error.1744083536 |
| Short name | T2006 |
| Test name | |
| Test status | |
| Simulation time | 617369171 ps |
| CPU time | 204.45 seconds |
| Started | Jun 29 08:22:33 PM PDT 24 |
| Finished | Jun 29 08:25:57 PM PDT 24 |
| Peak memory | 574364 kb |
| Host | smart-d68bd84c-f2f5-45e7-9a26-afcb268e358c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1744083536 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.xbar_stress_al l_with_reset_error.1744083536 |
| Directory | /workspace/44.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/44.xbar_unmapped_addr.1996127 |
| Short name | T1594 |
| Test name | |
| Test status | |
| Simulation time | 317970789 ps |
| CPU time | 42.34 seconds |
| Started | Jun 29 08:22:30 PM PDT 24 |
| Finished | Jun 29 08:23:13 PM PDT 24 |
| Peak memory | 574296 kb |
| Host | smart-b3e3f239-5619-4836-8817-bc7deb46fc65 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1996127 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.xbar_unmapped_addr.1996127 |
| Directory | /workspace/44.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/45.xbar_access_same_device.2837515607 |
| Short name | T2232 |
| Test name | |
| Test status | |
| Simulation time | 422253041 ps |
| CPU time | 17.75 seconds |
| Started | Jun 29 08:22:33 PM PDT 24 |
| Finished | Jun 29 08:22:51 PM PDT 24 |
| Peak memory | 574228 kb |
| Host | smart-2112a0c4-552d-446c-9ea3-134a00a7245b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2837515607 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.xbar_access_same_device .2837515607 |
| Directory | /workspace/45.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/45.xbar_access_same_device_slow_rsp.4227108603 |
| Short name | T1774 |
| Test name | |
| Test status | |
| Simulation time | 82685666779 ps |
| CPU time | 1495.48 seconds |
| Started | Jun 29 08:22:35 PM PDT 24 |
| Finished | Jun 29 08:47:31 PM PDT 24 |
| Peak memory | 575404 kb |
| Host | smart-b2c6037e-7d5f-4be8-beab-bcf569e679f9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4227108603 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.xbar_access_same_ device_slow_rsp.4227108603 |
| Directory | /workspace/45.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/45.xbar_error_and_unmapped_addr.3634186115 |
| Short name | T1890 |
| Test name | |
| Test status | |
| Simulation time | 802271413 ps |
| CPU time | 36.69 seconds |
| Started | Jun 29 08:22:42 PM PDT 24 |
| Finished | Jun 29 08:23:19 PM PDT 24 |
| Peak memory | 573940 kb |
| Host | smart-e95498f2-217e-4ede-8b21-dddef1a6c3d5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3634186115 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.xbar_error_and_unmapped_add r.3634186115 |
| Directory | /workspace/45.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/45.xbar_error_random.3215795025 |
| Short name | T1371 |
| Test name | |
| Test status | |
| Simulation time | 1799056186 ps |
| CPU time | 68.94 seconds |
| Started | Jun 29 08:22:43 PM PDT 24 |
| Finished | Jun 29 08:23:53 PM PDT 24 |
| Peak memory | 574484 kb |
| Host | smart-c6508f9c-31fa-4f49-8981-8cdfb5a48d9f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3215795025 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.xbar_error_random.3215795025 |
| Directory | /workspace/45.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/45.xbar_random.552065049 |
| Short name | T2590 |
| Test name | |
| Test status | |
| Simulation time | 467446023 ps |
| CPU time | 38.81 seconds |
| Started | Jun 29 08:22:34 PM PDT 24 |
| Finished | Jun 29 08:23:13 PM PDT 24 |
| Peak memory | 574248 kb |
| Host | smart-b0a10c95-2e38-467f-afc0-e9dda34b5181 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=552065049 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.xbar_random.552065049 |
| Directory | /workspace/45.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/45.xbar_random_large_delays.2442506885 |
| Short name | T582 |
| Test name | |
| Test status | |
| Simulation time | 75077889065 ps |
| CPU time | 867.7 seconds |
| Started | Jun 29 08:22:37 PM PDT 24 |
| Finished | Jun 29 08:37:05 PM PDT 24 |
| Peak memory | 575312 kb |
| Host | smart-cb45e96f-51d9-4ac7-9cae-b086a05ca205 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2442506885 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.xbar_random_large_delays.2442506885 |
| Directory | /workspace/45.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/45.xbar_random_slow_rsp.3397565510 |
| Short name | T506 |
| Test name | |
| Test status | |
| Simulation time | 23400782083 ps |
| CPU time | 403.12 seconds |
| Started | Jun 29 08:22:32 PM PDT 24 |
| Finished | Jun 29 08:29:16 PM PDT 24 |
| Peak memory | 575328 kb |
| Host | smart-2de17f18-ef18-4da8-8b54-d3df324fb2cd |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3397565510 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.xbar_random_slow_rsp.3397565510 |
| Directory | /workspace/45.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/45.xbar_random_zero_delays.1461228463 |
| Short name | T1523 |
| Test name | |
| Test status | |
| Simulation time | 389161089 ps |
| CPU time | 39.36 seconds |
| Started | Jun 29 08:22:37 PM PDT 24 |
| Finished | Jun 29 08:23:17 PM PDT 24 |
| Peak memory | 575176 kb |
| Host | smart-0dc12749-5408-4862-9ebb-e0118f99b5f3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1461228463 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.xbar_random_zero_del ays.1461228463 |
| Directory | /workspace/45.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/45.xbar_same_source.1206767719 |
| Short name | T2546 |
| Test name | |
| Test status | |
| Simulation time | 1516413164 ps |
| CPU time | 51.89 seconds |
| Started | Jun 29 08:22:48 PM PDT 24 |
| Finished | Jun 29 08:23:40 PM PDT 24 |
| Peak memory | 575296 kb |
| Host | smart-130548cf-13e4-4137-bd96-c872563bde09 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1206767719 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.xbar_same_source.1206767719 |
| Directory | /workspace/45.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/45.xbar_smoke.2985693286 |
| Short name | T2227 |
| Test name | |
| Test status | |
| Simulation time | 191670280 ps |
| CPU time | 8.97 seconds |
| Started | Jun 29 08:22:34 PM PDT 24 |
| Finished | Jun 29 08:22:44 PM PDT 24 |
| Peak memory | 566012 kb |
| Host | smart-f858e1e5-092c-4c88-bad3-fff395d50d83 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2985693286 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.xbar_smoke.2985693286 |
| Directory | /workspace/45.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/45.xbar_smoke_large_delays.3884628494 |
| Short name | T2620 |
| Test name | |
| Test status | |
| Simulation time | 8732887478 ps |
| CPU time | 97.04 seconds |
| Started | Jun 29 08:22:35 PM PDT 24 |
| Finished | Jun 29 08:24:13 PM PDT 24 |
| Peak memory | 566220 kb |
| Host | smart-50e58232-c877-4352-bae5-f22d6d605659 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3884628494 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.xbar_smoke_large_delays.3884628494 |
| Directory | /workspace/45.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/45.xbar_smoke_slow_rsp.638018871 |
| Short name | T2852 |
| Test name | |
| Test status | |
| Simulation time | 5094085563 ps |
| CPU time | 95.26 seconds |
| Started | Jun 29 08:22:33 PM PDT 24 |
| Finished | Jun 29 08:24:08 PM PDT 24 |
| Peak memory | 566112 kb |
| Host | smart-fe3bd5eb-436b-4fe6-9bc5-a9308dc86c0a |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=638018871 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.xbar_smoke_slow_rsp.638018871 |
| Directory | /workspace/45.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/45.xbar_smoke_zero_delays.343311074 |
| Short name | T2427 |
| Test name | |
| Test status | |
| Simulation time | 56500575 ps |
| CPU time | 6.92 seconds |
| Started | Jun 29 08:22:33 PM PDT 24 |
| Finished | Jun 29 08:22:40 PM PDT 24 |
| Peak memory | 574260 kb |
| Host | smart-3f37bd7d-2fc0-4314-b143-2022539e16b7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=343311074 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.xbar_smoke_zero_delays .343311074 |
| Directory | /workspace/45.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/45.xbar_stress_all.1005815198 |
| Short name | T513 |
| Test name | |
| Test status | |
| Simulation time | 2243353794 ps |
| CPU time | 232.18 seconds |
| Started | Jun 29 08:22:41 PM PDT 24 |
| Finished | Jun 29 08:26:34 PM PDT 24 |
| Peak memory | 575424 kb |
| Host | smart-62e6e742-842d-4163-868b-60654b1013af |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1005815198 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.xbar_stress_all.1005815198 |
| Directory | /workspace/45.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/45.xbar_stress_all_with_error.1818808651 |
| Short name | T1952 |
| Test name | |
| Test status | |
| Simulation time | 12070212008 ps |
| CPU time | 462.95 seconds |
| Started | Jun 29 08:22:42 PM PDT 24 |
| Finished | Jun 29 08:30:26 PM PDT 24 |
| Peak memory | 574740 kb |
| Host | smart-07228d46-5bf1-4ffa-a08b-5a4857f5cd34 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1818808651 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.xbar_stress_all_with_error.1818808651 |
| Directory | /workspace/45.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/45.xbar_stress_all_with_rand_reset.1574731579 |
| Short name | T2687 |
| Test name | |
| Test status | |
| Simulation time | 560914684 ps |
| CPU time | 234.13 seconds |
| Started | Jun 29 08:22:43 PM PDT 24 |
| Finished | Jun 29 08:26:38 PM PDT 24 |
| Peak memory | 576428 kb |
| Host | smart-72e3af41-688e-4721-b3f8-60d4fdd23c81 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1574731579 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.xbar_stress_all _with_rand_reset.1574731579 |
| Directory | /workspace/45.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/45.xbar_stress_all_with_reset_error.3253416124 |
| Short name | T2558 |
| Test name | |
| Test status | |
| Simulation time | 602436071 ps |
| CPU time | 127.36 seconds |
| Started | Jun 29 08:22:49 PM PDT 24 |
| Finished | Jun 29 08:24:57 PM PDT 24 |
| Peak memory | 574396 kb |
| Host | smart-247dfaf3-6dc1-4777-8c34-42bc49f0f9cf |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3253416124 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.xbar_stress_al l_with_reset_error.3253416124 |
| Directory | /workspace/45.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/45.xbar_unmapped_addr.1715499333 |
| Short name | T2538 |
| Test name | |
| Test status | |
| Simulation time | 712787290 ps |
| CPU time | 35.65 seconds |
| Started | Jun 29 08:22:42 PM PDT 24 |
| Finished | Jun 29 08:23:18 PM PDT 24 |
| Peak memory | 575360 kb |
| Host | smart-4dedaeaf-e473-43c6-a13e-e4b25eaa76e0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1715499333 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.xbar_unmapped_addr.1715499333 |
| Directory | /workspace/45.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/46.xbar_access_same_device.3209186786 |
| Short name | T509 |
| Test name | |
| Test status | |
| Simulation time | 1118202614 ps |
| CPU time | 100.34 seconds |
| Started | Jun 29 08:22:51 PM PDT 24 |
| Finished | Jun 29 08:24:31 PM PDT 24 |
| Peak memory | 575300 kb |
| Host | smart-b69151a1-e835-477a-8869-5bc32e5e8191 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3209186786 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.xbar_access_same_device .3209186786 |
| Directory | /workspace/46.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/46.xbar_access_same_device_slow_rsp.542217214 |
| Short name | T2644 |
| Test name | |
| Test status | |
| Simulation time | 26944481426 ps |
| CPU time | 489.27 seconds |
| Started | Jun 29 08:22:53 PM PDT 24 |
| Finished | Jun 29 08:31:03 PM PDT 24 |
| Peak memory | 574376 kb |
| Host | smart-269cca87-c814-41b4-9be1-d43057fc72f5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=542217214 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.xbar_access_same_d evice_slow_rsp.542217214 |
| Directory | /workspace/46.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/46.xbar_error_and_unmapped_addr.3342885663 |
| Short name | T1380 |
| Test name | |
| Test status | |
| Simulation time | 926055741 ps |
| CPU time | 37.4 seconds |
| Started | Jun 29 08:22:51 PM PDT 24 |
| Finished | Jun 29 08:23:28 PM PDT 24 |
| Peak memory | 574268 kb |
| Host | smart-e1c30f2d-5ff6-4e0b-9b01-f093a798e83d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3342885663 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.xbar_error_and_unmapped_add r.3342885663 |
| Directory | /workspace/46.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/46.xbar_error_random.3539096573 |
| Short name | T2217 |
| Test name | |
| Test status | |
| Simulation time | 894978901 ps |
| CPU time | 35.65 seconds |
| Started | Jun 29 08:22:48 PM PDT 24 |
| Finished | Jun 29 08:23:24 PM PDT 24 |
| Peak memory | 574268 kb |
| Host | smart-77a1ccae-c2f9-458c-a817-3db0ae10dfb1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3539096573 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.xbar_error_random.3539096573 |
| Directory | /workspace/46.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/46.xbar_random.1444226508 |
| Short name | T2700 |
| Test name | |
| Test status | |
| Simulation time | 1416845480 ps |
| CPU time | 57.75 seconds |
| Started | Jun 29 08:22:49 PM PDT 24 |
| Finished | Jun 29 08:23:47 PM PDT 24 |
| Peak memory | 575284 kb |
| Host | smart-421e461d-aacb-4419-ab2c-a7d23fd2136b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1444226508 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.xbar_random.1444226508 |
| Directory | /workspace/46.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/46.xbar_random_large_delays.1757539694 |
| Short name | T1693 |
| Test name | |
| Test status | |
| Simulation time | 57126049083 ps |
| CPU time | 599.87 seconds |
| Started | Jun 29 08:22:42 PM PDT 24 |
| Finished | Jun 29 08:32:43 PM PDT 24 |
| Peak memory | 575416 kb |
| Host | smart-dbfaa1ce-6773-41bc-9ec6-0e3da6eba6a0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1757539694 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.xbar_random_large_delays.1757539694 |
| Directory | /workspace/46.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/46.xbar_random_slow_rsp.1255676150 |
| Short name | T1357 |
| Test name | |
| Test status | |
| Simulation time | 14256840751 ps |
| CPU time | 248.16 seconds |
| Started | Jun 29 08:22:48 PM PDT 24 |
| Finished | Jun 29 08:26:56 PM PDT 24 |
| Peak memory | 575432 kb |
| Host | smart-065570f9-97c4-4682-b1dc-5ab736d798ab |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1255676150 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.xbar_random_slow_rsp.1255676150 |
| Directory | /workspace/46.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/46.xbar_random_zero_delays.1118517183 |
| Short name | T2854 |
| Test name | |
| Test status | |
| Simulation time | 311681765 ps |
| CPU time | 31.42 seconds |
| Started | Jun 29 08:22:43 PM PDT 24 |
| Finished | Jun 29 08:23:14 PM PDT 24 |
| Peak memory | 574244 kb |
| Host | smart-1262facc-891d-4be6-8898-9a16603f9175 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1118517183 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.xbar_random_zero_del ays.1118517183 |
| Directory | /workspace/46.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/46.xbar_same_source.2456167405 |
| Short name | T1546 |
| Test name | |
| Test status | |
| Simulation time | 206332457 ps |
| CPU time | 9.45 seconds |
| Started | Jun 29 08:22:47 PM PDT 24 |
| Finished | Jun 29 08:22:57 PM PDT 24 |
| Peak memory | 566024 kb |
| Host | smart-e14c2613-4952-4b4d-8058-3812187838ef |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2456167405 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.xbar_same_source.2456167405 |
| Directory | /workspace/46.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/46.xbar_smoke.4032606159 |
| Short name | T1342 |
| Test name | |
| Test status | |
| Simulation time | 229102574 ps |
| CPU time | 10.42 seconds |
| Started | Jun 29 08:22:49 PM PDT 24 |
| Finished | Jun 29 08:23:00 PM PDT 24 |
| Peak memory | 574216 kb |
| Host | smart-d4c10870-2e50-4b3f-86cb-13b4fb20e38d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4032606159 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.xbar_smoke.4032606159 |
| Directory | /workspace/46.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/46.xbar_smoke_large_delays.3054953255 |
| Short name | T2618 |
| Test name | |
| Test status | |
| Simulation time | 6324901135 ps |
| CPU time | 66.28 seconds |
| Started | Jun 29 08:22:43 PM PDT 24 |
| Finished | Jun 29 08:23:50 PM PDT 24 |
| Peak memory | 566080 kb |
| Host | smart-96d14cda-9e7f-4528-89e3-8bdcbe2b0778 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3054953255 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.xbar_smoke_large_delays.3054953255 |
| Directory | /workspace/46.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/46.xbar_smoke_slow_rsp.2861894854 |
| Short name | T2431 |
| Test name | |
| Test status | |
| Simulation time | 4405677695 ps |
| CPU time | 76.58 seconds |
| Started | Jun 29 08:22:41 PM PDT 24 |
| Finished | Jun 29 08:23:58 PM PDT 24 |
| Peak memory | 574328 kb |
| Host | smart-ada60f90-b2f2-45fb-909e-0e441f0a827a |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2861894854 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.xbar_smoke_slow_rsp.2861894854 |
| Directory | /workspace/46.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/46.xbar_smoke_zero_delays.3150616992 |
| Short name | T2794 |
| Test name | |
| Test status | |
| Simulation time | 41450049 ps |
| CPU time | 6.01 seconds |
| Started | Jun 29 08:22:43 PM PDT 24 |
| Finished | Jun 29 08:22:50 PM PDT 24 |
| Peak memory | 574252 kb |
| Host | smart-ef600ecb-1101-45d9-86f6-6c31e0dc910d |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3150616992 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.xbar_smoke_zero_delay s.3150616992 |
| Directory | /workspace/46.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/46.xbar_stress_all.1798666083 |
| Short name | T2741 |
| Test name | |
| Test status | |
| Simulation time | 1324587703 ps |
| CPU time | 117.73 seconds |
| Started | Jun 29 08:22:50 PM PDT 24 |
| Finished | Jun 29 08:24:48 PM PDT 24 |
| Peak memory | 574364 kb |
| Host | smart-c8bebaa7-524f-4991-9bf9-7ccea2170544 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1798666083 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.xbar_stress_all.1798666083 |
| Directory | /workspace/46.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/46.xbar_stress_all_with_error.4182584314 |
| Short name | T1808 |
| Test name | |
| Test status | |
| Simulation time | 2085821044 ps |
| CPU time | 171.3 seconds |
| Started | Jun 29 08:22:50 PM PDT 24 |
| Finished | Jun 29 08:25:41 PM PDT 24 |
| Peak memory | 574580 kb |
| Host | smart-d6e1f371-47fa-42e4-8850-dbbd04081f4f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4182584314 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.xbar_stress_all_with_error.4182584314 |
| Directory | /workspace/46.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/46.xbar_stress_all_with_rand_reset.820887248 |
| Short name | T2711 |
| Test name | |
| Test status | |
| Simulation time | 534396431 ps |
| CPU time | 208.43 seconds |
| Started | Jun 29 08:22:49 PM PDT 24 |
| Finished | Jun 29 08:26:18 PM PDT 24 |
| Peak memory | 575452 kb |
| Host | smart-c2e4194f-d4fa-4636-b3a8-f5a5e8e64211 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=820887248 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_res et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.xbar_stress_all_ with_rand_reset.820887248 |
| Directory | /workspace/46.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/46.xbar_stress_all_with_reset_error.1303519765 |
| Short name | T812 |
| Test name | |
| Test status | |
| Simulation time | 284252106 ps |
| CPU time | 74.95 seconds |
| Started | Jun 29 08:22:49 PM PDT 24 |
| Finished | Jun 29 08:24:04 PM PDT 24 |
| Peak memory | 574672 kb |
| Host | smart-7f694e50-300f-4030-af31-dcbe2a828785 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1303519765 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.xbar_stress_al l_with_reset_error.1303519765 |
| Directory | /workspace/46.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/46.xbar_unmapped_addr.2940133744 |
| Short name | T2275 |
| Test name | |
| Test status | |
| Simulation time | 120295756 ps |
| CPU time | 16.73 seconds |
| Started | Jun 29 08:22:49 PM PDT 24 |
| Finished | Jun 29 08:23:06 PM PDT 24 |
| Peak memory | 574260 kb |
| Host | smart-804c8816-e84a-4f20-89e1-3a905751722d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2940133744 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.xbar_unmapped_addr.2940133744 |
| Directory | /workspace/46.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/47.xbar_access_same_device.161661371 |
| Short name | T788 |
| Test name | |
| Test status | |
| Simulation time | 913355345 ps |
| CPU time | 46.22 seconds |
| Started | Jun 29 08:23:01 PM PDT 24 |
| Finished | Jun 29 08:23:47 PM PDT 24 |
| Peak memory | 575336 kb |
| Host | smart-8d463f63-17e5-4083-aea3-5f516d97d20c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=161661371 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.xbar_access_same_device. 161661371 |
| Directory | /workspace/47.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/47.xbar_access_same_device_slow_rsp.4052274584 |
| Short name | T2774 |
| Test name | |
| Test status | |
| Simulation time | 26256951649 ps |
| CPU time | 497.9 seconds |
| Started | Jun 29 08:22:57 PM PDT 24 |
| Finished | Jun 29 08:31:15 PM PDT 24 |
| Peak memory | 575444 kb |
| Host | smart-311580a4-67e6-4ce7-ae9f-98c3f7c3bf0d |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4052274584 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.xbar_access_same_ device_slow_rsp.4052274584 |
| Directory | /workspace/47.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/47.xbar_error_and_unmapped_addr.3975562442 |
| Short name | T1445 |
| Test name | |
| Test status | |
| Simulation time | 1355064153 ps |
| CPU time | 53.96 seconds |
| Started | Jun 29 08:23:08 PM PDT 24 |
| Finished | Jun 29 08:24:02 PM PDT 24 |
| Peak memory | 574476 kb |
| Host | smart-7b5e0558-3f72-41e3-9326-39a784a1f7fd |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3975562442 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.xbar_error_and_unmapped_add r.3975562442 |
| Directory | /workspace/47.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/47.xbar_error_random.3613687264 |
| Short name | T2013 |
| Test name | |
| Test status | |
| Simulation time | 1801068488 ps |
| CPU time | 60.97 seconds |
| Started | Jun 29 08:23:01 PM PDT 24 |
| Finished | Jun 29 08:24:02 PM PDT 24 |
| Peak memory | 574272 kb |
| Host | smart-7b1ece58-c399-4064-bb3a-9879a77e153a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3613687264 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.xbar_error_random.3613687264 |
| Directory | /workspace/47.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/47.xbar_random.808227524 |
| Short name | T2739 |
| Test name | |
| Test status | |
| Simulation time | 1936703175 ps |
| CPU time | 74.87 seconds |
| Started | Jun 29 08:22:57 PM PDT 24 |
| Finished | Jun 29 08:24:13 PM PDT 24 |
| Peak memory | 575308 kb |
| Host | smart-bb1c9831-c36f-428d-a0aa-0c992c71fba5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=808227524 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.xbar_random.808227524 |
| Directory | /workspace/47.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/47.xbar_random_large_delays.269932532 |
| Short name | T614 |
| Test name | |
| Test status | |
| Simulation time | 68802559274 ps |
| CPU time | 809.53 seconds |
| Started | Jun 29 08:23:00 PM PDT 24 |
| Finished | Jun 29 08:36:30 PM PDT 24 |
| Peak memory | 575368 kb |
| Host | smart-bb87056b-2cee-48f7-8582-98a9ede30278 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=269932532 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.xbar_random_large_delays.269932532 |
| Directory | /workspace/47.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/47.xbar_random_slow_rsp.2496215577 |
| Short name | T2516 |
| Test name | |
| Test status | |
| Simulation time | 40136865138 ps |
| CPU time | 667.98 seconds |
| Started | Jun 29 08:22:56 PM PDT 24 |
| Finished | Jun 29 08:34:05 PM PDT 24 |
| Peak memory | 575424 kb |
| Host | smart-a735c0d9-1db3-4bac-8076-366f6ec01d89 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2496215577 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.xbar_random_slow_rsp.2496215577 |
| Directory | /workspace/47.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/47.xbar_random_zero_delays.452872426 |
| Short name | T2371 |
| Test name | |
| Test status | |
| Simulation time | 97218567 ps |
| CPU time | 12.32 seconds |
| Started | Jun 29 08:22:57 PM PDT 24 |
| Finished | Jun 29 08:23:09 PM PDT 24 |
| Peak memory | 574228 kb |
| Host | smart-c6259c5b-2349-49db-831c-c8c11599e229 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=452872426 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.xbar_random_zero_dela ys.452872426 |
| Directory | /workspace/47.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/47.xbar_smoke.3732396029 |
| Short name | T1986 |
| Test name | |
| Test status | |
| Simulation time | 47309392 ps |
| CPU time | 7.14 seconds |
| Started | Jun 29 08:22:49 PM PDT 24 |
| Finished | Jun 29 08:22:57 PM PDT 24 |
| Peak memory | 566012 kb |
| Host | smart-2a4d490a-71d7-4a1b-8f05-52217bb35d70 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3732396029 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.xbar_smoke.3732396029 |
| Directory | /workspace/47.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/47.xbar_smoke_large_delays.2914315493 |
| Short name | T510 |
| Test name | |
| Test status | |
| Simulation time | 10204458643 ps |
| CPU time | 102.57 seconds |
| Started | Jun 29 08:23:01 PM PDT 24 |
| Finished | Jun 29 08:24:44 PM PDT 24 |
| Peak memory | 574284 kb |
| Host | smart-d6c8d4bf-d454-4e99-8961-d6fd3596bdd9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2914315493 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.xbar_smoke_large_delays.2914315493 |
| Directory | /workspace/47.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/47.xbar_smoke_slow_rsp.2998343895 |
| Short name | T2192 |
| Test name | |
| Test status | |
| Simulation time | 4410880046 ps |
| CPU time | 77.51 seconds |
| Started | Jun 29 08:22:57 PM PDT 24 |
| Finished | Jun 29 08:24:14 PM PDT 24 |
| Peak memory | 574212 kb |
| Host | smart-7c32e847-6354-4540-96e4-915e6070f597 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2998343895 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.xbar_smoke_slow_rsp.2998343895 |
| Directory | /workspace/47.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/47.xbar_smoke_zero_delays.2909414725 |
| Short name | T1817 |
| Test name | |
| Test status | |
| Simulation time | 41843927 ps |
| CPU time | 6.13 seconds |
| Started | Jun 29 08:22:54 PM PDT 24 |
| Finished | Jun 29 08:23:00 PM PDT 24 |
| Peak memory | 574272 kb |
| Host | smart-d465f9fd-47da-4c6c-8276-f3d3f6c12bff |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2909414725 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.xbar_smoke_zero_delay s.2909414725 |
| Directory | /workspace/47.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/47.xbar_stress_all.3957471329 |
| Short name | T1842 |
| Test name | |
| Test status | |
| Simulation time | 10327531210 ps |
| CPU time | 427.15 seconds |
| Started | Jun 29 08:23:08 PM PDT 24 |
| Finished | Jun 29 08:30:15 PM PDT 24 |
| Peak memory | 575516 kb |
| Host | smart-393fab84-ee4d-4be5-82f3-2ad7f0877457 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3957471329 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.xbar_stress_all.3957471329 |
| Directory | /workspace/47.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/47.xbar_stress_all_with_error.4073412814 |
| Short name | T632 |
| Test name | |
| Test status | |
| Simulation time | 1021963771 ps |
| CPU time | 59.59 seconds |
| Started | Jun 29 08:23:05 PM PDT 24 |
| Finished | Jun 29 08:24:04 PM PDT 24 |
| Peak memory | 574532 kb |
| Host | smart-dadd1496-cc7b-40f4-a800-c3df5e583023 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4073412814 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.xbar_stress_all_with_error.4073412814 |
| Directory | /workspace/47.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/47.xbar_stress_all_with_rand_reset.37062436 |
| Short name | T2498 |
| Test name | |
| Test status | |
| Simulation time | 197208692 ps |
| CPU time | 91.65 seconds |
| Started | Jun 29 08:23:05 PM PDT 24 |
| Finished | Jun 29 08:24:37 PM PDT 24 |
| Peak memory | 575468 kb |
| Host | smart-22a10baf-0b81-4502-9b87-b1a3e7bd41b6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37062436 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_rese t_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.xbar_stress_all_w ith_rand_reset.37062436 |
| Directory | /workspace/47.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/47.xbar_unmapped_addr.1457067915 |
| Short name | T1763 |
| Test name | |
| Test status | |
| Simulation time | 1202400591 ps |
| CPU time | 56.27 seconds |
| Started | Jun 29 08:23:10 PM PDT 24 |
| Finished | Jun 29 08:24:06 PM PDT 24 |
| Peak memory | 575324 kb |
| Host | smart-8b05e6d1-7c20-42a9-9381-127ec4a6ab41 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1457067915 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.xbar_unmapped_addr.1457067915 |
| Directory | /workspace/47.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/48.xbar_access_same_device.4201503754 |
| Short name | T1501 |
| Test name | |
| Test status | |
| Simulation time | 3620801853 ps |
| CPU time | 145.66 seconds |
| Started | Jun 29 08:23:17 PM PDT 24 |
| Finished | Jun 29 08:25:43 PM PDT 24 |
| Peak memory | 574364 kb |
| Host | smart-aa199969-7663-41e0-86fb-e02e8c670279 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4201503754 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.xbar_access_same_device .4201503754 |
| Directory | /workspace/48.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/48.xbar_access_same_device_slow_rsp.2065593036 |
| Short name | T2752 |
| Test name | |
| Test status | |
| Simulation time | 38417917631 ps |
| CPU time | 710.98 seconds |
| Started | Jun 29 08:23:14 PM PDT 24 |
| Finished | Jun 29 08:35:05 PM PDT 24 |
| Peak memory | 575436 kb |
| Host | smart-62c6cf38-a987-42ff-82d0-8f371c7d7af8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2065593036 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.xbar_access_same_ device_slow_rsp.2065593036 |
| Directory | /workspace/48.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/48.xbar_error_and_unmapped_addr.1782509810 |
| Short name | T2595 |
| Test name | |
| Test status | |
| Simulation time | 287780736 ps |
| CPU time | 16.66 seconds |
| Started | Jun 29 08:23:13 PM PDT 24 |
| Finished | Jun 29 08:23:30 PM PDT 24 |
| Peak memory | 574268 kb |
| Host | smart-dd35bd46-7786-41d7-8cd2-5c133a11ef7a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1782509810 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.xbar_error_and_unmapped_add r.1782509810 |
| Directory | /workspace/48.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/48.xbar_error_random.3852909236 |
| Short name | T1375 |
| Test name | |
| Test status | |
| Simulation time | 510461901 ps |
| CPU time | 46.14 seconds |
| Started | Jun 29 08:23:14 PM PDT 24 |
| Finished | Jun 29 08:24:00 PM PDT 24 |
| Peak memory | 573884 kb |
| Host | smart-71410710-43d3-4529-a573-ac1171969211 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3852909236 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.xbar_error_random.3852909236 |
| Directory | /workspace/48.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/48.xbar_random.978137529 |
| Short name | T2041 |
| Test name | |
| Test status | |
| Simulation time | 388638381 ps |
| CPU time | 41.05 seconds |
| Started | Jun 29 08:23:08 PM PDT 24 |
| Finished | Jun 29 08:23:49 PM PDT 24 |
| Peak memory | 575280 kb |
| Host | smart-c2485941-4592-40f9-8432-b47e1c47e239 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=978137529 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.xbar_random.978137529 |
| Directory | /workspace/48.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/48.xbar_random_large_delays.528092923 |
| Short name | T1502 |
| Test name | |
| Test status | |
| Simulation time | 27173659001 ps |
| CPU time | 293.85 seconds |
| Started | Jun 29 08:23:15 PM PDT 24 |
| Finished | Jun 29 08:28:09 PM PDT 24 |
| Peak memory | 574336 kb |
| Host | smart-684ef280-98c3-4cdc-9d67-7bce5953b0d1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=528092923 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.xbar_random_large_delays.528092923 |
| Directory | /workspace/48.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/48.xbar_random_slow_rsp.1927552051 |
| Short name | T1805 |
| Test name | |
| Test status | |
| Simulation time | 41782166819 ps |
| CPU time | 719.62 seconds |
| Started | Jun 29 08:23:15 PM PDT 24 |
| Finished | Jun 29 08:35:15 PM PDT 24 |
| Peak memory | 575440 kb |
| Host | smart-7211b35d-cedb-46ae-b53f-73d4317ea666 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1927552051 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.xbar_random_slow_rsp.1927552051 |
| Directory | /workspace/48.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/48.xbar_random_zero_delays.1209715688 |
| Short name | T1531 |
| Test name | |
| Test status | |
| Simulation time | 232168617 ps |
| CPU time | 22.42 seconds |
| Started | Jun 29 08:23:07 PM PDT 24 |
| Finished | Jun 29 08:23:30 PM PDT 24 |
| Peak memory | 575308 kb |
| Host | smart-b97e8664-6447-4803-82d9-a3f2640a77e9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1209715688 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.xbar_random_zero_del ays.1209715688 |
| Directory | /workspace/48.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/48.xbar_same_source.3937911449 |
| Short name | T1929 |
| Test name | |
| Test status | |
| Simulation time | 368948363 ps |
| CPU time | 14.72 seconds |
| Started | Jun 29 08:23:14 PM PDT 24 |
| Finished | Jun 29 08:23:29 PM PDT 24 |
| Peak memory | 575276 kb |
| Host | smart-215cb680-00bc-4c0b-88ff-fd3fdf0b9a78 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3937911449 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.xbar_same_source.3937911449 |
| Directory | /workspace/48.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/48.xbar_smoke.2556599928 |
| Short name | T2180 |
| Test name | |
| Test status | |
| Simulation time | 239187107 ps |
| CPU time | 10.51 seconds |
| Started | Jun 29 08:23:08 PM PDT 24 |
| Finished | Jun 29 08:23:19 PM PDT 24 |
| Peak memory | 574264 kb |
| Host | smart-d58de2dc-1980-49af-987f-cc274e507cf8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2556599928 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.xbar_smoke.2556599928 |
| Directory | /workspace/48.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/48.xbar_smoke_large_delays.2481928493 |
| Short name | T2278 |
| Test name | |
| Test status | |
| Simulation time | 8594662653 ps |
| CPU time | 94.98 seconds |
| Started | Jun 29 08:23:06 PM PDT 24 |
| Finished | Jun 29 08:24:41 PM PDT 24 |
| Peak memory | 566076 kb |
| Host | smart-7b7a23d6-c19a-4d86-9fde-80992a549b23 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2481928493 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.xbar_smoke_large_delays.2481928493 |
| Directory | /workspace/48.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/48.xbar_smoke_slow_rsp.747226863 |
| Short name | T1384 |
| Test name | |
| Test status | |
| Simulation time | 3031393693 ps |
| CPU time | 53.84 seconds |
| Started | Jun 29 08:23:09 PM PDT 24 |
| Finished | Jun 29 08:24:03 PM PDT 24 |
| Peak memory | 574164 kb |
| Host | smart-baf64163-cb92-405f-85c0-186603ef33bd |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=747226863 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.xbar_smoke_slow_rsp.747226863 |
| Directory | /workspace/48.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/48.xbar_smoke_zero_delays.838585511 |
| Short name | T1565 |
| Test name | |
| Test status | |
| Simulation time | 46563182 ps |
| CPU time | 6.3 seconds |
| Started | Jun 29 08:23:05 PM PDT 24 |
| Finished | Jun 29 08:23:12 PM PDT 24 |
| Peak memory | 566008 kb |
| Host | smart-a21aea41-18d8-4944-a968-cfb0e37546f8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=838585511 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.xbar_smoke_zero_delays .838585511 |
| Directory | /workspace/48.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/48.xbar_stress_all.3847332445 |
| Short name | T2632 |
| Test name | |
| Test status | |
| Simulation time | 2312357139 ps |
| CPU time | 204.71 seconds |
| Started | Jun 29 08:23:17 PM PDT 24 |
| Finished | Jun 29 08:26:42 PM PDT 24 |
| Peak memory | 575504 kb |
| Host | smart-cddda5ba-c4bd-44f9-8a57-e935a420b7c3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3847332445 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.xbar_stress_all.3847332445 |
| Directory | /workspace/48.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/48.xbar_stress_all_with_error.2178406481 |
| Short name | T1930 |
| Test name | |
| Test status | |
| Simulation time | 18227837316 ps |
| CPU time | 639.25 seconds |
| Started | Jun 29 08:23:15 PM PDT 24 |
| Finished | Jun 29 08:33:55 PM PDT 24 |
| Peak memory | 574752 kb |
| Host | smart-a98113d3-a335-4215-b30e-96ae617cffdd |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2178406481 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.xbar_stress_all_with_error.2178406481 |
| Directory | /workspace/48.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/48.xbar_stress_all_with_rand_reset.3075005243 |
| Short name | T2678 |
| Test name | |
| Test status | |
| Simulation time | 877531360 ps |
| CPU time | 291.07 seconds |
| Started | Jun 29 08:23:13 PM PDT 24 |
| Finished | Jun 29 08:28:05 PM PDT 24 |
| Peak memory | 576448 kb |
| Host | smart-0e1a9d3a-f92b-400d-a63a-b971185b4eea |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3075005243 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.xbar_stress_all _with_rand_reset.3075005243 |
| Directory | /workspace/48.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/48.xbar_stress_all_with_reset_error.692533593 |
| Short name | T811 |
| Test name | |
| Test status | |
| Simulation time | 3026275537 ps |
| CPU time | 289.86 seconds |
| Started | Jun 29 08:23:15 PM PDT 24 |
| Finished | Jun 29 08:28:05 PM PDT 24 |
| Peak memory | 576512 kb |
| Host | smart-c298d20a-dcf7-4dec-8fcb-be283b350c4d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=692533593 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.xbar_stress_all _with_reset_error.692533593 |
| Directory | /workspace/48.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/48.xbar_unmapped_addr.2082028416 |
| Short name | T2753 |
| Test name | |
| Test status | |
| Simulation time | 217858022 ps |
| CPU time | 28.03 seconds |
| Started | Jun 29 08:23:15 PM PDT 24 |
| Finished | Jun 29 08:23:43 PM PDT 24 |
| Peak memory | 575344 kb |
| Host | smart-30d57988-f3e6-4eb2-aa0e-9185ac2f447a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2082028416 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.xbar_unmapped_addr.2082028416 |
| Directory | /workspace/48.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/49.xbar_access_same_device.1065192014 |
| Short name | T2514 |
| Test name | |
| Test status | |
| Simulation time | 1376103008 ps |
| CPU time | 105.24 seconds |
| Started | Jun 29 08:23:18 PM PDT 24 |
| Finished | Jun 29 08:25:03 PM PDT 24 |
| Peak memory | 574280 kb |
| Host | smart-c12fb7f8-447a-407b-a623-9648099f0cc4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1065192014 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.xbar_access_same_device .1065192014 |
| Directory | /workspace/49.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/49.xbar_access_same_device_slow_rsp.2138876410 |
| Short name | T801 |
| Test name | |
| Test status | |
| Simulation time | 156623834827 ps |
| CPU time | 2605.57 seconds |
| Started | Jun 29 08:23:13 PM PDT 24 |
| Finished | Jun 29 09:06:40 PM PDT 24 |
| Peak memory | 575496 kb |
| Host | smart-226f59cd-a89a-4a14-8743-03920c6c7838 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2138876410 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.xbar_access_same_ device_slow_rsp.2138876410 |
| Directory | /workspace/49.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/49.xbar_error_and_unmapped_addr.3281540221 |
| Short name | T2702 |
| Test name | |
| Test status | |
| Simulation time | 159452870 ps |
| CPU time | 20.66 seconds |
| Started | Jun 29 08:23:21 PM PDT 24 |
| Finished | Jun 29 08:23:42 PM PDT 24 |
| Peak memory | 573848 kb |
| Host | smart-d9eadebc-dfb5-4123-a8d2-1a1bcdaaf4d7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3281540221 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.xbar_error_and_unmapped_add r.3281540221 |
| Directory | /workspace/49.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/49.xbar_error_random.2849230559 |
| Short name | T2844 |
| Test name | |
| Test status | |
| Simulation time | 1490986212 ps |
| CPU time | 49.83 seconds |
| Started | Jun 29 08:23:13 PM PDT 24 |
| Finished | Jun 29 08:24:03 PM PDT 24 |
| Peak memory | 574232 kb |
| Host | smart-febf3090-0d0c-4b7a-9da5-37b5bcc0d7f8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2849230559 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.xbar_error_random.2849230559 |
| Directory | /workspace/49.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/49.xbar_random.3347388522 |
| Short name | T1948 |
| Test name | |
| Test status | |
| Simulation time | 652284430 ps |
| CPU time | 25.89 seconds |
| Started | Jun 29 08:23:14 PM PDT 24 |
| Finished | Jun 29 08:23:40 PM PDT 24 |
| Peak memory | 575312 kb |
| Host | smart-2c115f1e-5d5e-438f-b9d8-defc0f29af94 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3347388522 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.xbar_random.3347388522 |
| Directory | /workspace/49.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/49.xbar_random_large_delays.4098493989 |
| Short name | T1689 |
| Test name | |
| Test status | |
| Simulation time | 19528529700 ps |
| CPU time | 205.49 seconds |
| Started | Jun 29 08:23:14 PM PDT 24 |
| Finished | Jun 29 08:26:40 PM PDT 24 |
| Peak memory | 575396 kb |
| Host | smart-441f09b0-d447-45e4-ab6d-4b21751c30e4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4098493989 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.xbar_random_large_delays.4098493989 |
| Directory | /workspace/49.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/49.xbar_random_slow_rsp.2140358426 |
| Short name | T2805 |
| Test name | |
| Test status | |
| Simulation time | 31117841662 ps |
| CPU time | 563.24 seconds |
| Started | Jun 29 08:23:16 PM PDT 24 |
| Finished | Jun 29 08:32:40 PM PDT 24 |
| Peak memory | 575364 kb |
| Host | smart-43b1fd22-d189-44d6-b7ea-a170a599d78d |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2140358426 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.xbar_random_slow_rsp.2140358426 |
| Directory | /workspace/49.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/49.xbar_random_zero_delays.46271997 |
| Short name | T2020 |
| Test name | |
| Test status | |
| Simulation time | 301492435 ps |
| CPU time | 30.72 seconds |
| Started | Jun 29 08:23:21 PM PDT 24 |
| Finished | Jun 29 08:23:52 PM PDT 24 |
| Peak memory | 575264 kb |
| Host | smart-7e670810-58df-4ce4-bbc6-d870beb235d5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46271997 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.xbar_random_zero_delay s.46271997 |
| Directory | /workspace/49.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/49.xbar_same_source.916974280 |
| Short name | T2471 |
| Test name | |
| Test status | |
| Simulation time | 1622650827 ps |
| CPU time | 53.3 seconds |
| Started | Jun 29 08:23:18 PM PDT 24 |
| Finished | Jun 29 08:24:12 PM PDT 24 |
| Peak memory | 575188 kb |
| Host | smart-acee5494-e0d1-4878-b39e-26705eee5c30 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=916974280 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.xbar_same_source.916974280 |
| Directory | /workspace/49.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/49.xbar_smoke.3195318257 |
| Short name | T1530 |
| Test name | |
| Test status | |
| Simulation time | 195300875 ps |
| CPU time | 9.28 seconds |
| Started | Jun 29 08:23:18 PM PDT 24 |
| Finished | Jun 29 08:23:28 PM PDT 24 |
| Peak memory | 565828 kb |
| Host | smart-f077f10a-d19b-4be5-8280-51df66bcbf2f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3195318257 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.xbar_smoke.3195318257 |
| Directory | /workspace/49.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/49.xbar_smoke_large_delays.3158830095 |
| Short name | T2229 |
| Test name | |
| Test status | |
| Simulation time | 10210241618 ps |
| CPU time | 111.16 seconds |
| Started | Jun 29 08:23:13 PM PDT 24 |
| Finished | Jun 29 08:25:05 PM PDT 24 |
| Peak memory | 566088 kb |
| Host | smart-f4016bf3-4bd5-4885-9fa4-f50c4ea870ed |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3158830095 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.xbar_smoke_large_delays.3158830095 |
| Directory | /workspace/49.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/49.xbar_smoke_slow_rsp.3239559743 |
| Short name | T2321 |
| Test name | |
| Test status | |
| Simulation time | 4485559130 ps |
| CPU time | 75.87 seconds |
| Started | Jun 29 08:23:16 PM PDT 24 |
| Finished | Jun 29 08:24:32 PM PDT 24 |
| Peak memory | 574320 kb |
| Host | smart-bd89e6f4-3f97-4ceb-a0e1-2b4a82b57ac8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3239559743 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.xbar_smoke_slow_rsp.3239559743 |
| Directory | /workspace/49.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/49.xbar_smoke_zero_delays.1951328906 |
| Short name | T2376 |
| Test name | |
| Test status | |
| Simulation time | 49613111 ps |
| CPU time | 6.73 seconds |
| Started | Jun 29 08:23:15 PM PDT 24 |
| Finished | Jun 29 08:23:22 PM PDT 24 |
| Peak memory | 574256 kb |
| Host | smart-8852ce27-ed37-43e5-8907-36eccdab2ec0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1951328906 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.xbar_smoke_zero_delay s.1951328906 |
| Directory | /workspace/49.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/49.xbar_stress_all.3332120638 |
| Short name | T571 |
| Test name | |
| Test status | |
| Simulation time | 5135887259 ps |
| CPU time | 189.71 seconds |
| Started | Jun 29 08:23:21 PM PDT 24 |
| Finished | Jun 29 08:26:31 PM PDT 24 |
| Peak memory | 575436 kb |
| Host | smart-f52e44ab-aa86-4ef5-9700-ba4a4b2296cb |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3332120638 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.xbar_stress_all.3332120638 |
| Directory | /workspace/49.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/49.xbar_stress_all_with_error.3773643308 |
| Short name | T2101 |
| Test name | |
| Test status | |
| Simulation time | 2742644553 ps |
| CPU time | 210.68 seconds |
| Started | Jun 29 08:23:21 PM PDT 24 |
| Finished | Jun 29 08:26:52 PM PDT 24 |
| Peak memory | 574604 kb |
| Host | smart-5a20f5f1-6ba8-4ae7-9f9c-266d3cec17ab |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3773643308 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.xbar_stress_all_with_error.3773643308 |
| Directory | /workspace/49.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/49.xbar_stress_all_with_rand_reset.2929009451 |
| Short name | T2328 |
| Test name | |
| Test status | |
| Simulation time | 785129106 ps |
| CPU time | 322.44 seconds |
| Started | Jun 29 08:23:14 PM PDT 24 |
| Finished | Jun 29 08:28:37 PM PDT 24 |
| Peak memory | 575452 kb |
| Host | smart-00b282ab-4435-461d-a297-cb8097ec3a37 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2929009451 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.xbar_stress_all _with_rand_reset.2929009451 |
| Directory | /workspace/49.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/49.xbar_stress_all_with_reset_error.1395341067 |
| Short name | T2732 |
| Test name | |
| Test status | |
| Simulation time | 7163918971 ps |
| CPU time | 755.14 seconds |
| Started | Jun 29 08:23:21 PM PDT 24 |
| Finished | Jun 29 08:35:57 PM PDT 24 |
| Peak memory | 582648 kb |
| Host | smart-93958b4e-3713-47df-b0f4-d50f2db47078 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1395341067 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.xbar_stress_al l_with_reset_error.1395341067 |
| Directory | /workspace/49.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/49.xbar_unmapped_addr.3655906918 |
| Short name | T2197 |
| Test name | |
| Test status | |
| Simulation time | 16564648 ps |
| CPU time | 5.53 seconds |
| Started | Jun 29 08:23:15 PM PDT 24 |
| Finished | Jun 29 08:23:21 PM PDT 24 |
| Peak memory | 574080 kb |
| Host | smart-7758d381-0e00-4d58-b608-fce709340b85 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3655906918 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.xbar_unmapped_addr.3655906918 |
| Directory | /workspace/49.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/5.chip_csr_rw.237170387 |
| Short name | T1439 |
| Test name | |
| Test status | |
| Simulation time | 4390486441 ps |
| CPU time | 408.84 seconds |
| Started | Jun 29 08:12:11 PM PDT 24 |
| Finished | Jun 29 08:19:00 PM PDT 24 |
| Peak memory | 596416 kb |
| Host | smart-4bf15af3-5c6c-4425-8080-df03e9dd0f3b |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=237170387 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.chip_csr_rw.237170387 |
| Directory | /workspace/5.chip_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/5.chip_same_csr_outstanding.2046523151 |
| Short name | T1704 |
| Test name | |
| Test status | |
| Simulation time | 15301618664 ps |
| CPU time | 2563.42 seconds |
| Started | Jun 29 08:11:55 PM PDT 24 |
| Finished | Jun 29 08:54:39 PM PDT 24 |
| Peak memory | 591940 kb |
| Host | smart-ef812c9d-fc91-44a4-a880-43a0b1760645 |
| User | root |
| Command | /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +run_same_csr_outstanding +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2046523151 -assert nopostproc +UVM_TE STNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb - cm_log /dev/null -cm_name 5.chip_same_csr_outstanding.2046523151 |
| Directory | /workspace/5.chip_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/5.chip_tl_errors.2863119167 |
| Short name | T2760 |
| Test name | |
| Test status | |
| Simulation time | 4097842936 ps |
| CPU time | 352.66 seconds |
| Started | Jun 29 08:11:56 PM PDT 24 |
| Finished | Jun 29 08:17:49 PM PDT 24 |
| Peak memory | 597576 kb |
| Host | smart-369bb372-915b-4668-b6fd-4cc04ed8d888 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2863119167 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.chip_tl_errors.2863119167 |
| Directory | /workspace/5.chip_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/5.xbar_access_same_device.2182357046 |
| Short name | T1633 |
| Test name | |
| Test status | |
| Simulation time | 2065745361 ps |
| CPU time | 92.02 seconds |
| Started | Jun 29 08:12:08 PM PDT 24 |
| Finished | Jun 29 08:13:41 PM PDT 24 |
| Peak memory | 574268 kb |
| Host | smart-396164fe-d16b-49fc-a361-ae66e67d6f48 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2182357046 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.xbar_access_same_device. 2182357046 |
| Directory | /workspace/5.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/5.xbar_access_same_device_slow_rsp.971217878 |
| Short name | T1869 |
| Test name | |
| Test status | |
| Simulation time | 63860163481 ps |
| CPU time | 1148.86 seconds |
| Started | Jun 29 08:12:09 PM PDT 24 |
| Finished | Jun 29 08:31:18 PM PDT 24 |
| Peak memory | 575456 kb |
| Host | smart-e8c50b1c-ee5a-47e7-9460-f5d30b7316fc |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=971217878 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.xbar_access_same_de vice_slow_rsp.971217878 |
| Directory | /workspace/5.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/5.xbar_error_and_unmapped_addr.2014003719 |
| Short name | T2505 |
| Test name | |
| Test status | |
| Simulation time | 740651545 ps |
| CPU time | 34.53 seconds |
| Started | Jun 29 08:12:16 PM PDT 24 |
| Finished | Jun 29 08:12:51 PM PDT 24 |
| Peak memory | 574504 kb |
| Host | smart-3d4fbef5-c518-4cb9-8db2-4a47d68919d4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2014003719 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.xbar_error_and_unmapped_addr .2014003719 |
| Directory | /workspace/5.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/5.xbar_error_random.1283629225 |
| Short name | T2743 |
| Test name | |
| Test status | |
| Simulation time | 2197286584 ps |
| CPU time | 76.44 seconds |
| Started | Jun 29 08:12:11 PM PDT 24 |
| Finished | Jun 29 08:13:28 PM PDT 24 |
| Peak memory | 573944 kb |
| Host | smart-c1976ca5-6c27-4a8b-92c4-ee46c2317f02 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1283629225 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.xbar_error_random.1283629225 |
| Directory | /workspace/5.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/5.xbar_random.3363010562 |
| Short name | T2162 |
| Test name | |
| Test status | |
| Simulation time | 2285449647 ps |
| CPU time | 96.67 seconds |
| Started | Jun 29 08:11:58 PM PDT 24 |
| Finished | Jun 29 08:13:35 PM PDT 24 |
| Peak memory | 575364 kb |
| Host | smart-1d2e8921-2e4c-45bd-83b2-bc0851ba8dcc |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3363010562 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.xbar_random.3363010562 |
| Directory | /workspace/5.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/5.xbar_random_large_delays.826261895 |
| Short name | T1359 |
| Test name | |
| Test status | |
| Simulation time | 7243931035 ps |
| CPU time | 74.22 seconds |
| Started | Jun 29 08:12:05 PM PDT 24 |
| Finished | Jun 29 08:13:19 PM PDT 24 |
| Peak memory | 574264 kb |
| Host | smart-07e116d9-229f-4e0d-aca1-242953aaef4a |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=826261895 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.xbar_random_large_delays.826261895 |
| Directory | /workspace/5.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/5.xbar_random_slow_rsp.7950369 |
| Short name | T1553 |
| Test name | |
| Test status | |
| Simulation time | 34665155986 ps |
| CPU time | 592.16 seconds |
| Started | Jun 29 08:12:10 PM PDT 24 |
| Finished | Jun 29 08:22:02 PM PDT 24 |
| Peak memory | 575420 kb |
| Host | smart-95960b6b-d481-4d31-878b-a44485b3dc59 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=7950369 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.xbar_random_slow_rsp.7950369 |
| Directory | /workspace/5.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/5.xbar_random_zero_delays.2998155417 |
| Short name | T2845 |
| Test name | |
| Test status | |
| Simulation time | 226718501 ps |
| CPU time | 23.13 seconds |
| Started | Jun 29 08:12:00 PM PDT 24 |
| Finished | Jun 29 08:12:24 PM PDT 24 |
| Peak memory | 574232 kb |
| Host | smart-b13ff738-97ce-4d3b-88ae-fac2a4acf01d |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2998155417 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.xbar_random_zero_dela ys.2998155417 |
| Directory | /workspace/5.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/5.xbar_same_source.3480018507 |
| Short name | T553 |
| Test name | |
| Test status | |
| Simulation time | 2241163203 ps |
| CPU time | 73.64 seconds |
| Started | Jun 29 08:12:08 PM PDT 24 |
| Finished | Jun 29 08:13:22 PM PDT 24 |
| Peak memory | 575364 kb |
| Host | smart-d985b5c1-be27-4180-88fe-1f8aca2ae4d2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3480018507 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.xbar_same_source.3480018507 |
| Directory | /workspace/5.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/5.xbar_smoke.2048022883 |
| Short name | T2565 |
| Test name | |
| Test status | |
| Simulation time | 219668374 ps |
| CPU time | 10.37 seconds |
| Started | Jun 29 08:11:55 PM PDT 24 |
| Finished | Jun 29 08:12:06 PM PDT 24 |
| Peak memory | 574268 kb |
| Host | smart-bbee0364-d878-46ea-88c6-6a2fdd742086 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2048022883 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.xbar_smoke.2048022883 |
| Directory | /workspace/5.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/5.xbar_smoke_large_delays.3557707080 |
| Short name | T2126 |
| Test name | |
| Test status | |
| Simulation time | 7862885223 ps |
| CPU time | 84.45 seconds |
| Started | Jun 29 08:11:57 PM PDT 24 |
| Finished | Jun 29 08:13:21 PM PDT 24 |
| Peak memory | 566092 kb |
| Host | smart-e00ce635-b1c4-4e25-975f-d4c3d1e34dd7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3557707080 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.xbar_smoke_large_delays.3557707080 |
| Directory | /workspace/5.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/5.xbar_smoke_slow_rsp.1224712699 |
| Short name | T2161 |
| Test name | |
| Test status | |
| Simulation time | 5347368080 ps |
| CPU time | 93.8 seconds |
| Started | Jun 29 08:12:00 PM PDT 24 |
| Finished | Jun 29 08:13:35 PM PDT 24 |
| Peak memory | 574196 kb |
| Host | smart-06637523-4725-4211-a175-c07d84274320 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1224712699 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.xbar_smoke_slow_rsp.1224712699 |
| Directory | /workspace/5.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/5.xbar_smoke_zero_delays.3302636748 |
| Short name | T1857 |
| Test name | |
| Test status | |
| Simulation time | 38777628 ps |
| CPU time | 6.26 seconds |
| Started | Jun 29 08:12:04 PM PDT 24 |
| Finished | Jun 29 08:12:10 PM PDT 24 |
| Peak memory | 574216 kb |
| Host | smart-c7770233-a581-4bfc-8d43-998b615a2f89 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3302636748 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.xbar_smoke_zero_delays .3302636748 |
| Directory | /workspace/5.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/5.xbar_stress_all.4148143954 |
| Short name | T2865 |
| Test name | |
| Test status | |
| Simulation time | 10956280246 ps |
| CPU time | 437.06 seconds |
| Started | Jun 29 08:12:11 PM PDT 24 |
| Finished | Jun 29 08:19:28 PM PDT 24 |
| Peak memory | 575500 kb |
| Host | smart-1c090f7a-5779-45d7-9be4-1169777c8159 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4148143954 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.xbar_stress_all.4148143954 |
| Directory | /workspace/5.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/5.xbar_stress_all_with_error.4053619365 |
| Short name | T2028 |
| Test name | |
| Test status | |
| Simulation time | 5534469780 ps |
| CPU time | 198.72 seconds |
| Started | Jun 29 08:12:15 PM PDT 24 |
| Finished | Jun 29 08:15:34 PM PDT 24 |
| Peak memory | 574372 kb |
| Host | smart-f8de7fd7-fee1-4e56-8694-6f4e63ea5dde |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4053619365 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.xbar_stress_all_with_error.4053619365 |
| Directory | /workspace/5.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/5.xbar_stress_all_with_rand_reset.3400767289 |
| Short name | T609 |
| Test name | |
| Test status | |
| Simulation time | 163839627 ps |
| CPU time | 95.75 seconds |
| Started | Jun 29 08:12:16 PM PDT 24 |
| Finished | Jun 29 08:13:52 PM PDT 24 |
| Peak memory | 575460 kb |
| Host | smart-0a0e7308-4c4e-4e86-861f-82a7ab77ca3e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3400767289 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.xbar_stress_all_ with_rand_reset.3400767289 |
| Directory | /workspace/5.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/5.xbar_stress_all_with_reset_error.3093614238 |
| Short name | T2088 |
| Test name | |
| Test status | |
| Simulation time | 403615620 ps |
| CPU time | 142.16 seconds |
| Started | Jun 29 08:12:16 PM PDT 24 |
| Finished | Jun 29 08:14:38 PM PDT 24 |
| Peak memory | 576424 kb |
| Host | smart-97a7af3d-110c-431a-a2aa-1e9d7ba33ed8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3093614238 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.xbar_stress_all _with_reset_error.3093614238 |
| Directory | /workspace/5.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/5.xbar_unmapped_addr.3875237632 |
| Short name | T2031 |
| Test name | |
| Test status | |
| Simulation time | 737164163 ps |
| CPU time | 37.42 seconds |
| Started | Jun 29 08:12:12 PM PDT 24 |
| Finished | Jun 29 08:12:49 PM PDT 24 |
| Peak memory | 575332 kb |
| Host | smart-d1cbfcc1-f0ee-4f88-a833-64e971288bb7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3875237632 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.xbar_unmapped_addr.3875237632 |
| Directory | /workspace/5.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/50.xbar_access_same_device.200189545 |
| Short name | T784 |
| Test name | |
| Test status | |
| Simulation time | 1939986046 ps |
| CPU time | 86.11 seconds |
| Started | Jun 29 08:23:27 PM PDT 24 |
| Finished | Jun 29 08:24:53 PM PDT 24 |
| Peak memory | 575332 kb |
| Host | smart-fbf90c34-6b70-4dd1-baa6-37b023364c1b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=200189545 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 50.xbar_access_same_device. 200189545 |
| Directory | /workspace/50.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/50.xbar_access_same_device_slow_rsp.2921882735 |
| Short name | T581 |
| Test name | |
| Test status | |
| Simulation time | 70914086851 ps |
| CPU time | 1277.91 seconds |
| Started | Jun 29 08:23:27 PM PDT 24 |
| Finished | Jun 29 08:44:45 PM PDT 24 |
| Peak memory | 575424 kb |
| Host | smart-60705c3a-f366-4647-9abd-c5450ae87d59 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2921882735 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 50.xbar_access_same_ device_slow_rsp.2921882735 |
| Directory | /workspace/50.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/50.xbar_error_and_unmapped_addr.1943221639 |
| Short name | T1422 |
| Test name | |
| Test status | |
| Simulation time | 457808424 ps |
| CPU time | 19.98 seconds |
| Started | Jun 29 08:23:32 PM PDT 24 |
| Finished | Jun 29 08:23:53 PM PDT 24 |
| Peak memory | 574476 kb |
| Host | smart-e8a23d37-6430-49e5-9616-2c9ee0fb1fd5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1943221639 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 50.xbar_error_and_unmapped_add r.1943221639 |
| Directory | /workspace/50.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/50.xbar_error_random.634039248 |
| Short name | T1658 |
| Test name | |
| Test status | |
| Simulation time | 1574978893 ps |
| CPU time | 58.91 seconds |
| Started | Jun 29 08:23:23 PM PDT 24 |
| Finished | Jun 29 08:24:22 PM PDT 24 |
| Peak memory | 574516 kb |
| Host | smart-108d2b0a-7c60-4cf9-9113-d4c0307d99ae |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=634039248 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 50.xbar_error_random.634039248 |
| Directory | /workspace/50.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/50.xbar_random.755763188 |
| Short name | T1420 |
| Test name | |
| Test status | |
| Simulation time | 2201434771 ps |
| CPU time | 83.73 seconds |
| Started | Jun 29 08:23:21 PM PDT 24 |
| Finished | Jun 29 08:24:45 PM PDT 24 |
| Peak memory | 575376 kb |
| Host | smart-9aea7bab-df0f-4eb9-96ae-bf1b7c94d65c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=755763188 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 50.xbar_random.755763188 |
| Directory | /workspace/50.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/50.xbar_random_large_delays.4031306273 |
| Short name | T2323 |
| Test name | |
| Test status | |
| Simulation time | 98323673468 ps |
| CPU time | 1068.3 seconds |
| Started | Jun 29 08:23:22 PM PDT 24 |
| Finished | Jun 29 08:41:10 PM PDT 24 |
| Peak memory | 575400 kb |
| Host | smart-9d966bb7-48b5-4ec2-b3dc-310c1e7494e1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4031306273 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 50.xbar_random_large_delays.4031306273 |
| Directory | /workspace/50.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/50.xbar_random_slow_rsp.2463851693 |
| Short name | T2488 |
| Test name | |
| Test status | |
| Simulation time | 51914142793 ps |
| CPU time | 940.82 seconds |
| Started | Jun 29 08:23:23 PM PDT 24 |
| Finished | Jun 29 08:39:04 PM PDT 24 |
| Peak memory | 575384 kb |
| Host | smart-7e6303a1-e2d9-4c84-8bb4-7541069b7ce0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2463851693 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 50.xbar_random_slow_rsp.2463851693 |
| Directory | /workspace/50.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/50.xbar_random_zero_delays.1792265847 |
| Short name | T2617 |
| Test name | |
| Test status | |
| Simulation time | 390408099 ps |
| CPU time | 35.53 seconds |
| Started | Jun 29 08:23:23 PM PDT 24 |
| Finished | Jun 29 08:23:59 PM PDT 24 |
| Peak memory | 574224 kb |
| Host | smart-b2818657-877c-4a8d-86bf-02fedc0bec65 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1792265847 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 50.xbar_random_zero_del ays.1792265847 |
| Directory | /workspace/50.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/50.xbar_same_source.725140641 |
| Short name | T2494 |
| Test name | |
| Test status | |
| Simulation time | 2284262648 ps |
| CPU time | 73.5 seconds |
| Started | Jun 29 08:23:20 PM PDT 24 |
| Finished | Jun 29 08:24:34 PM PDT 24 |
| Peak memory | 575356 kb |
| Host | smart-e8e116ef-db96-4863-a7c8-b1765b93da46 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=725140641 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 50.xbar_same_source.725140641 |
| Directory | /workspace/50.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/50.xbar_smoke.3469662728 |
| Short name | T1735 |
| Test name | |
| Test status | |
| Simulation time | 207914997 ps |
| CPU time | 10.33 seconds |
| Started | Jun 29 08:23:21 PM PDT 24 |
| Finished | Jun 29 08:23:31 PM PDT 24 |
| Peak memory | 574256 kb |
| Host | smart-29dc63ea-7d8c-4590-abc1-a9f6dd783e26 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3469662728 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 50.xbar_smoke.3469662728 |
| Directory | /workspace/50.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/50.xbar_smoke_large_delays.1900696306 |
| Short name | T1460 |
| Test name | |
| Test status | |
| Simulation time | 8409795844 ps |
| CPU time | 89.61 seconds |
| Started | Jun 29 08:23:23 PM PDT 24 |
| Finished | Jun 29 08:24:53 PM PDT 24 |
| Peak memory | 574324 kb |
| Host | smart-3e8c152a-8c87-4890-a0a0-e58f3b43aef3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1900696306 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 50.xbar_smoke_large_delays.1900696306 |
| Directory | /workspace/50.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/50.xbar_smoke_slow_rsp.2271574913 |
| Short name | T1998 |
| Test name | |
| Test status | |
| Simulation time | 3120012751 ps |
| CPU time | 51.91 seconds |
| Started | Jun 29 08:23:27 PM PDT 24 |
| Finished | Jun 29 08:24:19 PM PDT 24 |
| Peak memory | 574144 kb |
| Host | smart-1ec95290-a0fd-4d46-a29e-e451ef38c717 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2271574913 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 50.xbar_smoke_slow_rsp.2271574913 |
| Directory | /workspace/50.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/50.xbar_smoke_zero_delays.1356364869 |
| Short name | T1648 |
| Test name | |
| Test status | |
| Simulation time | 39484988 ps |
| CPU time | 6.17 seconds |
| Started | Jun 29 08:23:23 PM PDT 24 |
| Finished | Jun 29 08:23:29 PM PDT 24 |
| Peak memory | 574248 kb |
| Host | smart-423b11e8-030c-4631-8a22-3f8597163cdf |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1356364869 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 50.xbar_smoke_zero_delay s.1356364869 |
| Directory | /workspace/50.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/50.xbar_stress_all.1938614549 |
| Short name | T2407 |
| Test name | |
| Test status | |
| Simulation time | 8159781852 ps |
| CPU time | 304.44 seconds |
| Started | Jun 29 08:23:30 PM PDT 24 |
| Finished | Jun 29 08:28:35 PM PDT 24 |
| Peak memory | 575532 kb |
| Host | smart-7c236e1c-9c27-4659-aa8c-1c70737fc756 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1938614549 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 50.xbar_stress_all.1938614549 |
| Directory | /workspace/50.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/50.xbar_stress_all_with_error.3075562301 |
| Short name | T796 |
| Test name | |
| Test status | |
| Simulation time | 13115316795 ps |
| CPU time | 508.17 seconds |
| Started | Jun 29 08:23:31 PM PDT 24 |
| Finished | Jun 29 08:31:59 PM PDT 24 |
| Peak memory | 574736 kb |
| Host | smart-a1181eeb-54a3-40bc-8795-2f2e292c1ba7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3075562301 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 50.xbar_stress_all_with_error.3075562301 |
| Directory | /workspace/50.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/50.xbar_stress_all_with_rand_reset.3683842530 |
| Short name | T2499 |
| Test name | |
| Test status | |
| Simulation time | 3718029613 ps |
| CPU time | 459.77 seconds |
| Started | Jun 29 08:23:29 PM PDT 24 |
| Finished | Jun 29 08:31:10 PM PDT 24 |
| Peak memory | 575464 kb |
| Host | smart-fce60e77-003b-4461-929a-1f7f37f1ca60 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3683842530 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 50.xbar_stress_all _with_rand_reset.3683842530 |
| Directory | /workspace/50.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/50.xbar_stress_all_with_reset_error.1118374312 |
| Short name | T2141 |
| Test name | |
| Test status | |
| Simulation time | 207055948 ps |
| CPU time | 55.68 seconds |
| Started | Jun 29 08:23:29 PM PDT 24 |
| Finished | Jun 29 08:24:25 PM PDT 24 |
| Peak memory | 574396 kb |
| Host | smart-21c38717-ed00-4b26-8cfa-53b770583b12 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1118374312 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 50.xbar_stress_al l_with_reset_error.1118374312 |
| Directory | /workspace/50.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/50.xbar_unmapped_addr.3314309457 |
| Short name | T2843 |
| Test name | |
| Test status | |
| Simulation time | 40639558 ps |
| CPU time | 8.23 seconds |
| Started | Jun 29 08:23:21 PM PDT 24 |
| Finished | Jun 29 08:23:30 PM PDT 24 |
| Peak memory | 574200 kb |
| Host | smart-7f3bb5cb-06bb-413e-a37f-63608188e82b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3314309457 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 50.xbar_unmapped_addr.3314309457 |
| Directory | /workspace/50.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/51.xbar_access_same_device.2832130784 |
| Short name | T2485 |
| Test name | |
| Test status | |
| Simulation time | 517468526 ps |
| CPU time | 42.85 seconds |
| Started | Jun 29 08:23:41 PM PDT 24 |
| Finished | Jun 29 08:24:24 PM PDT 24 |
| Peak memory | 575336 kb |
| Host | smart-6d9bd2aa-f702-4cce-888a-0225bb997bb8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2832130784 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 51.xbar_access_same_device .2832130784 |
| Directory | /workspace/51.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/51.xbar_access_same_device_slow_rsp.2456681454 |
| Short name | T2812 |
| Test name | |
| Test status | |
| Simulation time | 104779352236 ps |
| CPU time | 1925.71 seconds |
| Started | Jun 29 08:23:39 PM PDT 24 |
| Finished | Jun 29 08:55:45 PM PDT 24 |
| Peak memory | 574448 kb |
| Host | smart-feb66820-d06c-4bad-b0b9-02a5738dedf2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2456681454 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 51.xbar_access_same_ device_slow_rsp.2456681454 |
| Directory | /workspace/51.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/51.xbar_error_and_unmapped_addr.987562737 |
| Short name | T1918 |
| Test name | |
| Test status | |
| Simulation time | 156466997 ps |
| CPU time | 9.43 seconds |
| Started | Jun 29 08:23:40 PM PDT 24 |
| Finished | Jun 29 08:23:50 PM PDT 24 |
| Peak memory | 566072 kb |
| Host | smart-d14bfabf-0969-4826-a7a1-f32a6ed21f85 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=987562737 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 51.xbar_error_and_unmapped_addr .987562737 |
| Directory | /workspace/51.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/51.xbar_error_random.2866265910 |
| Short name | T1473 |
| Test name | |
| Test status | |
| Simulation time | 389381887 ps |
| CPU time | 35.82 seconds |
| Started | Jun 29 08:23:38 PM PDT 24 |
| Finished | Jun 29 08:24:14 PM PDT 24 |
| Peak memory | 574500 kb |
| Host | smart-0d00853b-3ae9-4ff8-a112-9b614f730423 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2866265910 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 51.xbar_error_random.2866265910 |
| Directory | /workspace/51.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/51.xbar_random.1810220512 |
| Short name | T487 |
| Test name | |
| Test status | |
| Simulation time | 2467939909 ps |
| CPU time | 102.33 seconds |
| Started | Jun 29 08:23:39 PM PDT 24 |
| Finished | Jun 29 08:25:21 PM PDT 24 |
| Peak memory | 575412 kb |
| Host | smart-3253b695-5d54-4291-8307-08eec32c1ecd |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1810220512 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 51.xbar_random.1810220512 |
| Directory | /workspace/51.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/51.xbar_random_large_delays.3247556843 |
| Short name | T526 |
| Test name | |
| Test status | |
| Simulation time | 8330058249 ps |
| CPU time | 95.19 seconds |
| Started | Jun 29 08:23:39 PM PDT 24 |
| Finished | Jun 29 08:25:15 PM PDT 24 |
| Peak memory | 574280 kb |
| Host | smart-745f6e17-66dd-476d-ae91-9c9cf0dc0e5c |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3247556843 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 51.xbar_random_large_delays.3247556843 |
| Directory | /workspace/51.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/51.xbar_random_slow_rsp.892237401 |
| Short name | T2522 |
| Test name | |
| Test status | |
| Simulation time | 59721805417 ps |
| CPU time | 1032.36 seconds |
| Started | Jun 29 08:23:43 PM PDT 24 |
| Finished | Jun 29 08:40:55 PM PDT 24 |
| Peak memory | 575372 kb |
| Host | smart-5bb55614-ce53-47fa-b691-e804bc765830 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=892237401 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 51.xbar_random_slow_rsp.892237401 |
| Directory | /workspace/51.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/51.xbar_random_zero_delays.3346161312 |
| Short name | T2701 |
| Test name | |
| Test status | |
| Simulation time | 426058285 ps |
| CPU time | 41.09 seconds |
| Started | Jun 29 08:23:40 PM PDT 24 |
| Finished | Jun 29 08:24:22 PM PDT 24 |
| Peak memory | 575328 kb |
| Host | smart-30274d7f-7976-4025-97b7-ff31d7c520ad |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3346161312 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 51.xbar_random_zero_del ays.3346161312 |
| Directory | /workspace/51.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/51.xbar_same_source.1631973672 |
| Short name | T1726 |
| Test name | |
| Test status | |
| Simulation time | 2391186821 ps |
| CPU time | 93.83 seconds |
| Started | Jun 29 08:23:39 PM PDT 24 |
| Finished | Jun 29 08:25:13 PM PDT 24 |
| Peak memory | 574300 kb |
| Host | smart-7e2b5fe0-e9b4-4124-b3d5-6e5d7ad106a5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1631973672 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 51.xbar_same_source.1631973672 |
| Directory | /workspace/51.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/51.xbar_smoke.1212069007 |
| Short name | T2425 |
| Test name | |
| Test status | |
| Simulation time | 199860506 ps |
| CPU time | 9.92 seconds |
| Started | Jun 29 08:23:31 PM PDT 24 |
| Finished | Jun 29 08:23:41 PM PDT 24 |
| Peak memory | 566000 kb |
| Host | smart-66a82601-d12c-40ff-8734-120e43b18af9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1212069007 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 51.xbar_smoke.1212069007 |
| Directory | /workspace/51.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/51.xbar_smoke_large_delays.4269005665 |
| Short name | T2504 |
| Test name | |
| Test status | |
| Simulation time | 8354085556 ps |
| CPU time | 90.16 seconds |
| Started | Jun 29 08:23:30 PM PDT 24 |
| Finished | Jun 29 08:25:00 PM PDT 24 |
| Peak memory | 566092 kb |
| Host | smart-df7938dd-8934-4bcb-953e-e2e9eb9f7829 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4269005665 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 51.xbar_smoke_large_delays.4269005665 |
| Directory | /workspace/51.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/51.xbar_smoke_slow_rsp.3749303272 |
| Short name | T2823 |
| Test name | |
| Test status | |
| Simulation time | 4531164815 ps |
| CPU time | 75.95 seconds |
| Started | Jun 29 08:23:30 PM PDT 24 |
| Finished | Jun 29 08:24:46 PM PDT 24 |
| Peak memory | 574300 kb |
| Host | smart-c4de8f0a-d34d-4da8-8e90-8a8d72bab5de |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3749303272 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 51.xbar_smoke_slow_rsp.3749303272 |
| Directory | /workspace/51.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/51.xbar_smoke_zero_delays.1866827255 |
| Short name | T1602 |
| Test name | |
| Test status | |
| Simulation time | 41827666 ps |
| CPU time | 6.23 seconds |
| Started | Jun 29 08:23:30 PM PDT 24 |
| Finished | Jun 29 08:23:36 PM PDT 24 |
| Peak memory | 574236 kb |
| Host | smart-37b09a67-ee74-4c63-a1dc-41df0d0def49 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1866827255 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 51.xbar_smoke_zero_delay s.1866827255 |
| Directory | /workspace/51.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/51.xbar_stress_all.1466041828 |
| Short name | T2037 |
| Test name | |
| Test status | |
| Simulation time | 748345758 ps |
| CPU time | 68.79 seconds |
| Started | Jun 29 08:23:43 PM PDT 24 |
| Finished | Jun 29 08:24:52 PM PDT 24 |
| Peak memory | 575452 kb |
| Host | smart-4bb80a57-4096-41dd-b59d-d99fd76fe3c0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1466041828 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 51.xbar_stress_all.1466041828 |
| Directory | /workspace/51.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/51.xbar_stress_all_with_error.2350285271 |
| Short name | T1560 |
| Test name | |
| Test status | |
| Simulation time | 2102315240 ps |
| CPU time | 185.27 seconds |
| Started | Jun 29 08:23:39 PM PDT 24 |
| Finished | Jun 29 08:26:45 PM PDT 24 |
| Peak memory | 574408 kb |
| Host | smart-ab22dfa7-52b2-45ce-bc90-9fbc88a11ad3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2350285271 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 51.xbar_stress_all_with_error.2350285271 |
| Directory | /workspace/51.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/51.xbar_stress_all_with_rand_reset.2602284299 |
| Short name | T2765 |
| Test name | |
| Test status | |
| Simulation time | 357705694 ps |
| CPU time | 100.67 seconds |
| Started | Jun 29 08:23:40 PM PDT 24 |
| Finished | Jun 29 08:25:21 PM PDT 24 |
| Peak memory | 575440 kb |
| Host | smart-42bfabe3-730d-4b6e-aa1e-14f7d8d06894 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2602284299 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 51.xbar_stress_all _with_rand_reset.2602284299 |
| Directory | /workspace/51.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/51.xbar_stress_all_with_reset_error.1586223809 |
| Short name | T675 |
| Test name | |
| Test status | |
| Simulation time | 5930034238 ps |
| CPU time | 337.33 seconds |
| Started | Jun 29 08:23:49 PM PDT 24 |
| Finished | Jun 29 08:29:27 PM PDT 24 |
| Peak memory | 574744 kb |
| Host | smart-ac748b02-7098-4027-8d9e-6ad18169c036 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1586223809 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 51.xbar_stress_al l_with_reset_error.1586223809 |
| Directory | /workspace/51.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/51.xbar_unmapped_addr.3206562717 |
| Short name | T2572 |
| Test name | |
| Test status | |
| Simulation time | 191089729 ps |
| CPU time | 13.26 seconds |
| Started | Jun 29 08:23:40 PM PDT 24 |
| Finished | Jun 29 08:23:53 PM PDT 24 |
| Peak memory | 574328 kb |
| Host | smart-2a9282dc-717e-40a2-824a-9639534481ab |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3206562717 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 51.xbar_unmapped_addr.3206562717 |
| Directory | /workspace/51.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/52.xbar_access_same_device.231447632 |
| Short name | T1916 |
| Test name | |
| Test status | |
| Simulation time | 362681374 ps |
| CPU time | 29.01 seconds |
| Started | Jun 29 08:23:52 PM PDT 24 |
| Finished | Jun 29 08:24:21 PM PDT 24 |
| Peak memory | 575324 kb |
| Host | smart-b1926392-f4e9-491f-a687-54f5f225ae1f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=231447632 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 52.xbar_access_same_device. 231447632 |
| Directory | /workspace/52.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/52.xbar_access_same_device_slow_rsp.1210381052 |
| Short name | T2710 |
| Test name | |
| Test status | |
| Simulation time | 45052507887 ps |
| CPU time | 783.02 seconds |
| Started | Jun 29 08:23:52 PM PDT 24 |
| Finished | Jun 29 08:36:55 PM PDT 24 |
| Peak memory | 575404 kb |
| Host | smart-877678fe-3233-4542-be30-eda955fb1f4d |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1210381052 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 52.xbar_access_same_ device_slow_rsp.1210381052 |
| Directory | /workspace/52.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/52.xbar_error_and_unmapped_addr.713723851 |
| Short name | T2188 |
| Test name | |
| Test status | |
| Simulation time | 1401477187 ps |
| CPU time | 65.16 seconds |
| Started | Jun 29 08:23:49 PM PDT 24 |
| Finished | Jun 29 08:24:55 PM PDT 24 |
| Peak memory | 574272 kb |
| Host | smart-9b883508-570b-4f73-a1a4-b0e3e33a6202 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=713723851 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 52.xbar_error_and_unmapped_addr .713723851 |
| Directory | /workspace/52.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/52.xbar_error_random.543561720 |
| Short name | T225 |
| Test name | |
| Test status | |
| Simulation time | 578041370 ps |
| CPU time | 52.99 seconds |
| Started | Jun 29 08:23:51 PM PDT 24 |
| Finished | Jun 29 08:24:44 PM PDT 24 |
| Peak memory | 574276 kb |
| Host | smart-d958c044-c980-44b3-8307-496d96ac4569 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=543561720 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 52.xbar_error_random.543561720 |
| Directory | /workspace/52.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/52.xbar_random.2110102462 |
| Short name | T1541 |
| Test name | |
| Test status | |
| Simulation time | 2039524766 ps |
| CPU time | 67.91 seconds |
| Started | Jun 29 08:23:52 PM PDT 24 |
| Finished | Jun 29 08:25:00 PM PDT 24 |
| Peak memory | 575300 kb |
| Host | smart-311260fa-3248-4227-81ae-27e1002b4cf8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2110102462 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 52.xbar_random.2110102462 |
| Directory | /workspace/52.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/52.xbar_random_large_delays.817139397 |
| Short name | T2734 |
| Test name | |
| Test status | |
| Simulation time | 82602218109 ps |
| CPU time | 829.96 seconds |
| Started | Jun 29 08:23:50 PM PDT 24 |
| Finished | Jun 29 08:37:40 PM PDT 24 |
| Peak memory | 575400 kb |
| Host | smart-3f83f683-1e69-4e6a-aedd-60c394b523a9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=817139397 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 52.xbar_random_large_delays.817139397 |
| Directory | /workspace/52.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/52.xbar_random_slow_rsp.871760287 |
| Short name | T2208 |
| Test name | |
| Test status | |
| Simulation time | 16722785908 ps |
| CPU time | 315.9 seconds |
| Started | Jun 29 08:23:56 PM PDT 24 |
| Finished | Jun 29 08:29:12 PM PDT 24 |
| Peak memory | 575352 kb |
| Host | smart-7aefda48-2241-4572-8865-8fdbcbb9e2f5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=871760287 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 52.xbar_random_slow_rsp.871760287 |
| Directory | /workspace/52.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/52.xbar_random_zero_delays.2614939880 |
| Short name | T2377 |
| Test name | |
| Test status | |
| Simulation time | 107751829 ps |
| CPU time | 12.17 seconds |
| Started | Jun 29 08:23:50 PM PDT 24 |
| Finished | Jun 29 08:24:03 PM PDT 24 |
| Peak memory | 575320 kb |
| Host | smart-5c345a76-5467-483d-9866-19980b5754e2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2614939880 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 52.xbar_random_zero_del ays.2614939880 |
| Directory | /workspace/52.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/52.xbar_same_source.993950248 |
| Short name | T2761 |
| Test name | |
| Test status | |
| Simulation time | 427586293 ps |
| CPU time | 32.29 seconds |
| Started | Jun 29 08:23:49 PM PDT 24 |
| Finished | Jun 29 08:24:22 PM PDT 24 |
| Peak memory | 574232 kb |
| Host | smart-4548bed1-2b6a-4e71-b522-bd65a68c58fc |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=993950248 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 52.xbar_same_source.993950248 |
| Directory | /workspace/52.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/52.xbar_smoke.3349334982 |
| Short name | T1396 |
| Test name | |
| Test status | |
| Simulation time | 203416250 ps |
| CPU time | 9.52 seconds |
| Started | Jun 29 08:23:55 PM PDT 24 |
| Finished | Jun 29 08:24:04 PM PDT 24 |
| Peak memory | 574232 kb |
| Host | smart-a790ccee-8c91-4d93-8571-6f7742c6fb2a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3349334982 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 52.xbar_smoke.3349334982 |
| Directory | /workspace/52.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/52.xbar_smoke_large_delays.499642266 |
| Short name | T2093 |
| Test name | |
| Test status | |
| Simulation time | 8949999765 ps |
| CPU time | 101.31 seconds |
| Started | Jun 29 08:23:51 PM PDT 24 |
| Finished | Jun 29 08:25:32 PM PDT 24 |
| Peak memory | 574272 kb |
| Host | smart-d020ebed-47ac-44ae-a2c4-44fe8e2eac28 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=499642266 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 52.xbar_smoke_large_delays.499642266 |
| Directory | /workspace/52.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/52.xbar_smoke_slow_rsp.1463639675 |
| Short name | T1468 |
| Test name | |
| Test status | |
| Simulation time | 3817600684 ps |
| CPU time | 69.44 seconds |
| Started | Jun 29 08:23:49 PM PDT 24 |
| Finished | Jun 29 08:24:59 PM PDT 24 |
| Peak memory | 574320 kb |
| Host | smart-ef90d6d0-9957-4f87-883e-13a935f4e88c |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1463639675 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 52.xbar_smoke_slow_rsp.1463639675 |
| Directory | /workspace/52.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/52.xbar_smoke_zero_delays.3175022072 |
| Short name | T1692 |
| Test name | |
| Test status | |
| Simulation time | 43060630 ps |
| CPU time | 6.47 seconds |
| Started | Jun 29 08:23:54 PM PDT 24 |
| Finished | Jun 29 08:24:00 PM PDT 24 |
| Peak memory | 565864 kb |
| Host | smart-0ab8593b-951e-4678-8695-5c9f0d8f0268 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3175022072 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 52.xbar_smoke_zero_delay s.3175022072 |
| Directory | /workspace/52.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/52.xbar_stress_all.4202377488 |
| Short name | T2733 |
| Test name | |
| Test status | |
| Simulation time | 23334158813 ps |
| CPU time | 858.75 seconds |
| Started | Jun 29 08:23:49 PM PDT 24 |
| Finished | Jun 29 08:38:09 PM PDT 24 |
| Peak memory | 575528 kb |
| Host | smart-ddf40219-c237-429f-84fd-aa853b370cf9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4202377488 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 52.xbar_stress_all.4202377488 |
| Directory | /workspace/52.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/52.xbar_stress_all_with_error.440345407 |
| Short name | T1459 |
| Test name | |
| Test status | |
| Simulation time | 7582734555 ps |
| CPU time | 300.18 seconds |
| Started | Jun 29 08:23:55 PM PDT 24 |
| Finished | Jun 29 08:28:55 PM PDT 24 |
| Peak memory | 574372 kb |
| Host | smart-98108433-3cc2-44cb-9fde-4cf4957e8016 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=440345407 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 52.xbar_stress_all_with_error.440345407 |
| Directory | /workspace/52.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/52.xbar_stress_all_with_rand_reset.607657111 |
| Short name | T808 |
| Test name | |
| Test status | |
| Simulation time | 3553436957 ps |
| CPU time | 360.89 seconds |
| Started | Jun 29 08:23:49 PM PDT 24 |
| Finished | Jun 29 08:29:50 PM PDT 24 |
| Peak memory | 575512 kb |
| Host | smart-36b25b18-1098-47b1-8d23-89c729d6f4b0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=607657111 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_res et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 52.xbar_stress_all_ with_rand_reset.607657111 |
| Directory | /workspace/52.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/52.xbar_stress_all_with_reset_error.3587795352 |
| Short name | T2611 |
| Test name | |
| Test status | |
| Simulation time | 1563747424 ps |
| CPU time | 395.82 seconds |
| Started | Jun 29 08:23:55 PM PDT 24 |
| Finished | Jun 29 08:30:32 PM PDT 24 |
| Peak memory | 574684 kb |
| Host | smart-e740fa67-a077-40ee-82d5-0656ab2be389 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3587795352 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 52.xbar_stress_al l_with_reset_error.3587795352 |
| Directory | /workspace/52.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/52.xbar_unmapped_addr.2255081931 |
| Short name | T1955 |
| Test name | |
| Test status | |
| Simulation time | 1276040810 ps |
| CPU time | 56.03 seconds |
| Started | Jun 29 08:23:49 PM PDT 24 |
| Finished | Jun 29 08:24:45 PM PDT 24 |
| Peak memory | 575384 kb |
| Host | smart-62cd5fd0-8996-47a0-a072-03948e6d9ead |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2255081931 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 52.xbar_unmapped_addr.2255081931 |
| Directory | /workspace/52.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/53.xbar_access_same_device.2629229427 |
| Short name | T2780 |
| Test name | |
| Test status | |
| Simulation time | 808230562 ps |
| CPU time | 83.9 seconds |
| Started | Jun 29 08:24:05 PM PDT 24 |
| Finished | Jun 29 08:25:29 PM PDT 24 |
| Peak memory | 575396 kb |
| Host | smart-9801cf8e-a288-4ef1-98a6-5627a3017d6b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2629229427 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 53.xbar_access_same_device .2629229427 |
| Directory | /workspace/53.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/53.xbar_access_same_device_slow_rsp.1078366723 |
| Short name | T1877 |
| Test name | |
| Test status | |
| Simulation time | 81853633152 ps |
| CPU time | 1407.91 seconds |
| Started | Jun 29 08:23:56 PM PDT 24 |
| Finished | Jun 29 08:47:25 PM PDT 24 |
| Peak memory | 575416 kb |
| Host | smart-99af6da9-0535-400e-9a70-41eb7501f07f |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1078366723 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 53.xbar_access_same_ device_slow_rsp.1078366723 |
| Directory | /workspace/53.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/53.xbar_error_and_unmapped_addr.986614621 |
| Short name | T2049 |
| Test name | |
| Test status | |
| Simulation time | 217944626 ps |
| CPU time | 13.5 seconds |
| Started | Jun 29 08:24:05 PM PDT 24 |
| Finished | Jun 29 08:24:19 PM PDT 24 |
| Peak memory | 573932 kb |
| Host | smart-4f1b072f-216b-4948-a0aa-d438501f8284 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=986614621 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 53.xbar_error_and_unmapped_addr .986614621 |
| Directory | /workspace/53.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/53.xbar_error_random.963172804 |
| Short name | T1813 |
| Test name | |
| Test status | |
| Simulation time | 246405612 ps |
| CPU time | 22.36 seconds |
| Started | Jun 29 08:24:01 PM PDT 24 |
| Finished | Jun 29 08:24:24 PM PDT 24 |
| Peak memory | 573912 kb |
| Host | smart-bca5a471-badd-4cec-bdc4-94178ca47ee7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=963172804 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 53.xbar_error_random.963172804 |
| Directory | /workspace/53.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/53.xbar_random.1088747674 |
| Short name | T2331 |
| Test name | |
| Test status | |
| Simulation time | 211729713 ps |
| CPU time | 22.07 seconds |
| Started | Jun 29 08:24:05 PM PDT 24 |
| Finished | Jun 29 08:24:28 PM PDT 24 |
| Peak memory | 574236 kb |
| Host | smart-96652ad4-a8f3-400f-8696-7e909b46bf79 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1088747674 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 53.xbar_random.1088747674 |
| Directory | /workspace/53.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/53.xbar_random_large_delays.3320166398 |
| Short name | T625 |
| Test name | |
| Test status | |
| Simulation time | 42571017933 ps |
| CPU time | 448.07 seconds |
| Started | Jun 29 08:23:56 PM PDT 24 |
| Finished | Jun 29 08:31:25 PM PDT 24 |
| Peak memory | 575380 kb |
| Host | smart-1502dcb5-fdb6-4391-bd51-19411fd38a28 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3320166398 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 53.xbar_random_large_delays.3320166398 |
| Directory | /workspace/53.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/53.xbar_random_slow_rsp.500678909 |
| Short name | T1544 |
| Test name | |
| Test status | |
| Simulation time | 50872271018 ps |
| CPU time | 919.2 seconds |
| Started | Jun 29 08:24:05 PM PDT 24 |
| Finished | Jun 29 08:39:25 PM PDT 24 |
| Peak memory | 575384 kb |
| Host | smart-c4e6ae0c-345c-434b-9f9c-034ff84df770 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=500678909 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 53.xbar_random_slow_rsp.500678909 |
| Directory | /workspace/53.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/53.xbar_random_zero_delays.1289664049 |
| Short name | T458 |
| Test name | |
| Test status | |
| Simulation time | 384726538 ps |
| CPU time | 40.07 seconds |
| Started | Jun 29 08:23:57 PM PDT 24 |
| Finished | Jun 29 08:24:37 PM PDT 24 |
| Peak memory | 575300 kb |
| Host | smart-4c39e6ee-88dc-4c51-a1a3-0bf52abbc56c |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1289664049 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 53.xbar_random_zero_del ays.1289664049 |
| Directory | /workspace/53.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/53.xbar_same_source.1438733249 |
| Short name | T1920 |
| Test name | |
| Test status | |
| Simulation time | 379844614 ps |
| CPU time | 30.65 seconds |
| Started | Jun 29 08:23:55 PM PDT 24 |
| Finished | Jun 29 08:24:26 PM PDT 24 |
| Peak memory | 575296 kb |
| Host | smart-7178e461-ae43-41fd-9ac4-cb730d8e126c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1438733249 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 53.xbar_same_source.1438733249 |
| Directory | /workspace/53.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/53.xbar_smoke.1700137454 |
| Short name | T1348 |
| Test name | |
| Test status | |
| Simulation time | 53419488 ps |
| CPU time | 7.59 seconds |
| Started | Jun 29 08:23:56 PM PDT 24 |
| Finished | Jun 29 08:24:04 PM PDT 24 |
| Peak memory | 574260 kb |
| Host | smart-ff23f171-0266-48cd-817e-22861174bac2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1700137454 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 53.xbar_smoke.1700137454 |
| Directory | /workspace/53.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/53.xbar_smoke_large_delays.3443449116 |
| Short name | T2788 |
| Test name | |
| Test status | |
| Simulation time | 7871213862 ps |
| CPU time | 88.49 seconds |
| Started | Jun 29 08:24:04 PM PDT 24 |
| Finished | Jun 29 08:25:33 PM PDT 24 |
| Peak memory | 574328 kb |
| Host | smart-baa0a84a-98ba-45d8-9429-525941980673 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3443449116 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 53.xbar_smoke_large_delays.3443449116 |
| Directory | /workspace/53.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/53.xbar_smoke_slow_rsp.2448386503 |
| Short name | T2772 |
| Test name | |
| Test status | |
| Simulation time | 6129690844 ps |
| CPU time | 108.48 seconds |
| Started | Jun 29 08:24:02 PM PDT 24 |
| Finished | Jun 29 08:25:51 PM PDT 24 |
| Peak memory | 566076 kb |
| Host | smart-2e5a9890-693d-4c42-b77a-a145369bad1f |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2448386503 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 53.xbar_smoke_slow_rsp.2448386503 |
| Directory | /workspace/53.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/53.xbar_smoke_zero_delays.1665646289 |
| Short name | T1863 |
| Test name | |
| Test status | |
| Simulation time | 38133619 ps |
| CPU time | 6.4 seconds |
| Started | Jun 29 08:23:58 PM PDT 24 |
| Finished | Jun 29 08:24:05 PM PDT 24 |
| Peak memory | 574260 kb |
| Host | smart-832c76f4-8299-4683-ad27-29d9eba95d0d |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1665646289 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 53.xbar_smoke_zero_delay s.1665646289 |
| Directory | /workspace/53.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/53.xbar_stress_all.1723620906 |
| Short name | T2418 |
| Test name | |
| Test status | |
| Simulation time | 6734712438 ps |
| CPU time | 277.69 seconds |
| Started | Jun 29 08:24:07 PM PDT 24 |
| Finished | Jun 29 08:28:45 PM PDT 24 |
| Peak memory | 575488 kb |
| Host | smart-9624d087-10c3-4ac4-b125-7445f9a37ecf |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1723620906 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 53.xbar_stress_all.1723620906 |
| Directory | /workspace/53.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/53.xbar_stress_all_with_error.1615730757 |
| Short name | T2252 |
| Test name | |
| Test status | |
| Simulation time | 4004494816 ps |
| CPU time | 307 seconds |
| Started | Jun 29 08:24:07 PM PDT 24 |
| Finished | Jun 29 08:29:15 PM PDT 24 |
| Peak memory | 574444 kb |
| Host | smart-1c12ef56-b73f-4a47-a513-414e2905672c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1615730757 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 53.xbar_stress_all_with_error.1615730757 |
| Directory | /workspace/53.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/53.xbar_stress_all_with_rand_reset.3483892558 |
| Short name | T2706 |
| Test name | |
| Test status | |
| Simulation time | 6557836372 ps |
| CPU time | 839.68 seconds |
| Started | Jun 29 08:24:05 PM PDT 24 |
| Finished | Jun 29 08:38:05 PM PDT 24 |
| Peak memory | 575512 kb |
| Host | smart-fe611542-53a1-408e-963c-1e38cec2cc1f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3483892558 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 53.xbar_stress_all _with_rand_reset.3483892558 |
| Directory | /workspace/53.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/53.xbar_stress_all_with_reset_error.2172388466 |
| Short name | T1330 |
| Test name | |
| Test status | |
| Simulation time | 148460925 ps |
| CPU time | 43.19 seconds |
| Started | Jun 29 08:24:05 PM PDT 24 |
| Finished | Jun 29 08:24:49 PM PDT 24 |
| Peak memory | 576480 kb |
| Host | smart-17ec796c-644e-4295-a76d-5516bacf2b0a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2172388466 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 53.xbar_stress_al l_with_reset_error.2172388466 |
| Directory | /workspace/53.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/53.xbar_unmapped_addr.4039097756 |
| Short name | T2105 |
| Test name | |
| Test status | |
| Simulation time | 283567753 ps |
| CPU time | 34.56 seconds |
| Started | Jun 29 08:23:59 PM PDT 24 |
| Finished | Jun 29 08:24:33 PM PDT 24 |
| Peak memory | 575344 kb |
| Host | smart-2fc9707e-386f-4c9f-8943-a55da55be955 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4039097756 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 53.xbar_unmapped_addr.4039097756 |
| Directory | /workspace/53.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/54.xbar_access_same_device_slow_rsp.1747013114 |
| Short name | T2276 |
| Test name | |
| Test status | |
| Simulation time | 120299160460 ps |
| CPU time | 1978.54 seconds |
| Started | Jun 29 08:24:05 PM PDT 24 |
| Finished | Jun 29 08:57:04 PM PDT 24 |
| Peak memory | 575416 kb |
| Host | smart-290956c4-aad9-4bd2-ad45-6bd357b07cf0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1747013114 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 54.xbar_access_same_ device_slow_rsp.1747013114 |
| Directory | /workspace/54.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/54.xbar_error_and_unmapped_addr.2549882313 |
| Short name | T1405 |
| Test name | |
| Test status | |
| Simulation time | 55112606 ps |
| CPU time | 9.09 seconds |
| Started | Jun 29 08:24:07 PM PDT 24 |
| Finished | Jun 29 08:24:17 PM PDT 24 |
| Peak memory | 573924 kb |
| Host | smart-73adff2d-f9ef-42bc-8b6a-2f8d3c781260 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2549882313 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 54.xbar_error_and_unmapped_add r.2549882313 |
| Directory | /workspace/54.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/54.xbar_error_random.156982641 |
| Short name | T2360 |
| Test name | |
| Test status | |
| Simulation time | 61167209 ps |
| CPU time | 8.85 seconds |
| Started | Jun 29 08:24:05 PM PDT 24 |
| Finished | Jun 29 08:24:14 PM PDT 24 |
| Peak memory | 574488 kb |
| Host | smart-15fca4bd-6caf-4b9a-8a75-97a0af80f8b3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=156982641 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 54.xbar_error_random.156982641 |
| Directory | /workspace/54.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/54.xbar_random.625198996 |
| Short name | T2334 |
| Test name | |
| Test status | |
| Simulation time | 184967240 ps |
| CPU time | 19.56 seconds |
| Started | Jun 29 08:24:06 PM PDT 24 |
| Finished | Jun 29 08:24:26 PM PDT 24 |
| Peak memory | 575316 kb |
| Host | smart-4bf2ba83-5757-4522-b350-fd7dbf53d94e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=625198996 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 54.xbar_random.625198996 |
| Directory | /workspace/54.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/54.xbar_random_large_delays.2978285468 |
| Short name | T1926 |
| Test name | |
| Test status | |
| Simulation time | 73064173709 ps |
| CPU time | 723.25 seconds |
| Started | Jun 29 08:24:04 PM PDT 24 |
| Finished | Jun 29 08:36:08 PM PDT 24 |
| Peak memory | 575448 kb |
| Host | smart-7495e610-25c4-4f79-999c-2fa4eca86b50 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2978285468 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 54.xbar_random_large_delays.2978285468 |
| Directory | /workspace/54.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/54.xbar_random_slow_rsp.2196457661 |
| Short name | T1603 |
| Test name | |
| Test status | |
| Simulation time | 49155657261 ps |
| CPU time | 914.44 seconds |
| Started | Jun 29 08:24:04 PM PDT 24 |
| Finished | Jun 29 08:39:20 PM PDT 24 |
| Peak memory | 575404 kb |
| Host | smart-808e6a43-19e3-4209-8cd5-1e485bc10910 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2196457661 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 54.xbar_random_slow_rsp.2196457661 |
| Directory | /workspace/54.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/54.xbar_random_zero_delays.2599433806 |
| Short name | T624 |
| Test name | |
| Test status | |
| Simulation time | 123339145 ps |
| CPU time | 14.46 seconds |
| Started | Jun 29 08:24:08 PM PDT 24 |
| Finished | Jun 29 08:24:23 PM PDT 24 |
| Peak memory | 575312 kb |
| Host | smart-d63ae7c5-a7c5-43fe-8ce0-0b8e49de1627 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2599433806 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 54.xbar_random_zero_del ays.2599433806 |
| Directory | /workspace/54.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/54.xbar_same_source.4222350896 |
| Short name | T2469 |
| Test name | |
| Test status | |
| Simulation time | 1461502256 ps |
| CPU time | 44.85 seconds |
| Started | Jun 29 08:24:07 PM PDT 24 |
| Finished | Jun 29 08:24:52 PM PDT 24 |
| Peak memory | 575296 kb |
| Host | smart-442795b3-5a08-4a75-8977-dd6c548cc230 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4222350896 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 54.xbar_same_source.4222350896 |
| Directory | /workspace/54.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/54.xbar_smoke.3413494274 |
| Short name | T2807 |
| Test name | |
| Test status | |
| Simulation time | 40154600 ps |
| CPU time | 6.5 seconds |
| Started | Jun 29 08:24:07 PM PDT 24 |
| Finished | Jun 29 08:24:14 PM PDT 24 |
| Peak memory | 574236 kb |
| Host | smart-8cc580b9-e00a-4787-9e7d-ab6009f6967f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3413494274 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 54.xbar_smoke.3413494274 |
| Directory | /workspace/54.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/54.xbar_smoke_large_delays.2208515933 |
| Short name | T1730 |
| Test name | |
| Test status | |
| Simulation time | 5865204354 ps |
| CPU time | 61.84 seconds |
| Started | Jun 29 08:24:04 PM PDT 24 |
| Finished | Jun 29 08:25:06 PM PDT 24 |
| Peak memory | 574092 kb |
| Host | smart-69c9fbae-1da1-44f0-be68-cd49cf8611b1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2208515933 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 54.xbar_smoke_large_delays.2208515933 |
| Directory | /workspace/54.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/54.xbar_smoke_slow_rsp.2025232494 |
| Short name | T2087 |
| Test name | |
| Test status | |
| Simulation time | 5392487718 ps |
| CPU time | 95.4 seconds |
| Started | Jun 29 08:24:07 PM PDT 24 |
| Finished | Jun 29 08:25:43 PM PDT 24 |
| Peak memory | 574292 kb |
| Host | smart-becde240-dfbf-4299-887b-1b904b9b8c51 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2025232494 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 54.xbar_smoke_slow_rsp.2025232494 |
| Directory | /workspace/54.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/54.xbar_smoke_zero_delays.1669787881 |
| Short name | T2387 |
| Test name | |
| Test status | |
| Simulation time | 51542064 ps |
| CPU time | 7.31 seconds |
| Started | Jun 29 08:24:04 PM PDT 24 |
| Finished | Jun 29 08:24:11 PM PDT 24 |
| Peak memory | 574220 kb |
| Host | smart-a9fbeeac-a063-4e93-8d2f-d7c1e94c7106 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1669787881 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 54.xbar_smoke_zero_delay s.1669787881 |
| Directory | /workspace/54.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/54.xbar_stress_all.281165937 |
| Short name | T2201 |
| Test name | |
| Test status | |
| Simulation time | 6875515324 ps |
| CPU time | 255.12 seconds |
| Started | Jun 29 08:24:16 PM PDT 24 |
| Finished | Jun 29 08:28:32 PM PDT 24 |
| Peak memory | 574456 kb |
| Host | smart-40554ddc-246b-47b7-9cd9-ed98cff25eb4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=281165937 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 54.xbar_stress_all.281165937 |
| Directory | /workspace/54.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/54.xbar_stress_all_with_error.3130665722 |
| Short name | T2198 |
| Test name | |
| Test status | |
| Simulation time | 9772863657 ps |
| CPU time | 366.35 seconds |
| Started | Jun 29 08:24:13 PM PDT 24 |
| Finished | Jun 29 08:30:20 PM PDT 24 |
| Peak memory | 574488 kb |
| Host | smart-6ba14a6a-3cfa-464b-8296-daae05fcf48a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3130665722 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 54.xbar_stress_all_with_error.3130665722 |
| Directory | /workspace/54.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/54.xbar_stress_all_with_reset_error.1038200574 |
| Short name | T2043 |
| Test name | |
| Test status | |
| Simulation time | 5200218773 ps |
| CPU time | 325.16 seconds |
| Started | Jun 29 08:24:23 PM PDT 24 |
| Finished | Jun 29 08:29:49 PM PDT 24 |
| Peak memory | 576528 kb |
| Host | smart-ee1a1a7d-681b-4020-843d-c7fa91fd348c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1038200574 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 54.xbar_stress_al l_with_reset_error.1038200574 |
| Directory | /workspace/54.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/54.xbar_unmapped_addr.3693979992 |
| Short name | T2391 |
| Test name | |
| Test status | |
| Simulation time | 981767075 ps |
| CPU time | 47.66 seconds |
| Started | Jun 29 08:24:07 PM PDT 24 |
| Finished | Jun 29 08:24:55 PM PDT 24 |
| Peak memory | 575384 kb |
| Host | smart-9aa7f1e1-6fb1-41ef-b9d5-b0b124d34206 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3693979992 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 54.xbar_unmapped_addr.3693979992 |
| Directory | /workspace/54.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/55.xbar_access_same_device.1601240510 |
| Short name | T2380 |
| Test name | |
| Test status | |
| Simulation time | 543336343 ps |
| CPU time | 28.25 seconds |
| Started | Jun 29 08:24:14 PM PDT 24 |
| Finished | Jun 29 08:24:42 PM PDT 24 |
| Peak memory | 575320 kb |
| Host | smart-ae80c9dc-3a22-4ee7-afa9-e3be18207d9d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1601240510 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 55.xbar_access_same_device .1601240510 |
| Directory | /workspace/55.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/55.xbar_access_same_device_slow_rsp.2040935526 |
| Short name | T2224 |
| Test name | |
| Test status | |
| Simulation time | 2752075295 ps |
| CPU time | 50.66 seconds |
| Started | Jun 29 08:24:16 PM PDT 24 |
| Finished | Jun 29 08:25:07 PM PDT 24 |
| Peak memory | 574172 kb |
| Host | smart-4ab10d17-f908-4162-9d22-6994a093d1e8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2040935526 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 55.xbar_access_same_ device_slow_rsp.2040935526 |
| Directory | /workspace/55.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/55.xbar_error_and_unmapped_addr.716723690 |
| Short name | T2274 |
| Test name | |
| Test status | |
| Simulation time | 326196630 ps |
| CPU time | 37.87 seconds |
| Started | Jun 29 08:24:24 PM PDT 24 |
| Finished | Jun 29 08:25:02 PM PDT 24 |
| Peak memory | 574476 kb |
| Host | smart-cb58e957-02b7-441a-b6fd-fd727170c661 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=716723690 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 55.xbar_error_and_unmapped_addr .716723690 |
| Directory | /workspace/55.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/55.xbar_error_random.306074281 |
| Short name | T2108 |
| Test name | |
| Test status | |
| Simulation time | 2307224974 ps |
| CPU time | 93.18 seconds |
| Started | Jun 29 08:24:15 PM PDT 24 |
| Finished | Jun 29 08:25:49 PM PDT 24 |
| Peak memory | 573960 kb |
| Host | smart-50db6eae-7835-42bc-b6b3-73d06bf5d78b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=306074281 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 55.xbar_error_random.306074281 |
| Directory | /workspace/55.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/55.xbar_random.1473962915 |
| Short name | T2655 |
| Test name | |
| Test status | |
| Simulation time | 2021199480 ps |
| CPU time | 76.18 seconds |
| Started | Jun 29 08:24:17 PM PDT 24 |
| Finished | Jun 29 08:25:33 PM PDT 24 |
| Peak memory | 575292 kb |
| Host | smart-80166729-60a2-48da-9674-4e8f2da10a5b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1473962915 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 55.xbar_random.1473962915 |
| Directory | /workspace/55.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/55.xbar_random_large_delays.733518290 |
| Short name | T523 |
| Test name | |
| Test status | |
| Simulation time | 103180169760 ps |
| CPU time | 1082.2 seconds |
| Started | Jun 29 08:24:23 PM PDT 24 |
| Finished | Jun 29 08:42:26 PM PDT 24 |
| Peak memory | 575436 kb |
| Host | smart-ae2aa0f4-94f5-448f-bc12-e3f14ee44509 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=733518290 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 55.xbar_random_large_delays.733518290 |
| Directory | /workspace/55.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/55.xbar_random_slow_rsp.3686892251 |
| Short name | T1895 |
| Test name | |
| Test status | |
| Simulation time | 43863993085 ps |
| CPU time | 817.79 seconds |
| Started | Jun 29 08:24:14 PM PDT 24 |
| Finished | Jun 29 08:37:52 PM PDT 24 |
| Peak memory | 575396 kb |
| Host | smart-ad3eb6a4-ce28-419a-b1b4-00a98de0bae6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3686892251 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 55.xbar_random_slow_rsp.3686892251 |
| Directory | /workspace/55.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/55.xbar_random_zero_delays.4144435091 |
| Short name | T1758 |
| Test name | |
| Test status | |
| Simulation time | 155196298 ps |
| CPU time | 16.63 seconds |
| Started | Jun 29 08:24:17 PM PDT 24 |
| Finished | Jun 29 08:24:34 PM PDT 24 |
| Peak memory | 575276 kb |
| Host | smart-7265ee25-8e4e-41c4-9d65-fab6b28fa07a |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4144435091 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 55.xbar_random_zero_del ays.4144435091 |
| Directory | /workspace/55.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/55.xbar_same_source.614755083 |
| Short name | T504 |
| Test name | |
| Test status | |
| Simulation time | 1314560963 ps |
| CPU time | 37.45 seconds |
| Started | Jun 29 08:24:13 PM PDT 24 |
| Finished | Jun 29 08:24:51 PM PDT 24 |
| Peak memory | 575312 kb |
| Host | smart-c0ae2a68-3c4a-4132-8a39-ea742f2f954e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=614755083 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 55.xbar_same_source.614755083 |
| Directory | /workspace/55.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/55.xbar_smoke.297276126 |
| Short name | T1849 |
| Test name | |
| Test status | |
| Simulation time | 49553367 ps |
| CPU time | 7.2 seconds |
| Started | Jun 29 08:24:14 PM PDT 24 |
| Finished | Jun 29 08:24:21 PM PDT 24 |
| Peak memory | 574248 kb |
| Host | smart-577e019d-c377-4c34-953c-8c2d615c75b2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=297276126 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 55.xbar_smoke.297276126 |
| Directory | /workspace/55.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/55.xbar_smoke_large_delays.1618224794 |
| Short name | T2259 |
| Test name | |
| Test status | |
| Simulation time | 9760186645 ps |
| CPU time | 106.18 seconds |
| Started | Jun 29 08:24:13 PM PDT 24 |
| Finished | Jun 29 08:26:00 PM PDT 24 |
| Peak memory | 566096 kb |
| Host | smart-b0df40b5-ad68-47ca-8dab-f1605338b027 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1618224794 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 55.xbar_smoke_large_delays.1618224794 |
| Directory | /workspace/55.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/55.xbar_smoke_slow_rsp.785426028 |
| Short name | T2067 |
| Test name | |
| Test status | |
| Simulation time | 4789378537 ps |
| CPU time | 78.32 seconds |
| Started | Jun 29 08:24:13 PM PDT 24 |
| Finished | Jun 29 08:25:31 PM PDT 24 |
| Peak memory | 574276 kb |
| Host | smart-5fc8f7e7-0cc2-4996-9810-7a3b8a8f3643 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=785426028 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 55.xbar_smoke_slow_rsp.785426028 |
| Directory | /workspace/55.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/55.xbar_smoke_zero_delays.2452743271 |
| Short name | T1690 |
| Test name | |
| Test status | |
| Simulation time | 38670719 ps |
| CPU time | 6.56 seconds |
| Started | Jun 29 08:24:15 PM PDT 24 |
| Finished | Jun 29 08:24:22 PM PDT 24 |
| Peak memory | 574224 kb |
| Host | smart-b3eaac31-b579-4b64-b9d4-b1c8bbcd6688 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2452743271 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 55.xbar_smoke_zero_delay s.2452743271 |
| Directory | /workspace/55.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/55.xbar_stress_all.81917886 |
| Short name | T1410 |
| Test name | |
| Test status | |
| Simulation time | 1512195959 ps |
| CPU time | 59.03 seconds |
| Started | Jun 29 08:24:21 PM PDT 24 |
| Finished | Jun 29 08:25:21 PM PDT 24 |
| Peak memory | 574316 kb |
| Host | smart-515fcc47-7284-4812-a942-c7200ec3391f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81917886 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 55.xbar_stress_all.81917886 |
| Directory | /workspace/55.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/55.xbar_stress_all_with_error.1177470804 |
| Short name | T1989 |
| Test name | |
| Test status | |
| Simulation time | 2692062394 ps |
| CPU time | 235.15 seconds |
| Started | Jun 29 08:24:23 PM PDT 24 |
| Finished | Jun 29 08:28:19 PM PDT 24 |
| Peak memory | 574464 kb |
| Host | smart-cf3dbb13-2405-4649-8b22-afb226def7b3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1177470804 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 55.xbar_stress_all_with_error.1177470804 |
| Directory | /workspace/55.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/55.xbar_stress_all_with_rand_reset.3555230808 |
| Short name | T1618 |
| Test name | |
| Test status | |
| Simulation time | 8586717267 ps |
| CPU time | 433.02 seconds |
| Started | Jun 29 08:24:29 PM PDT 24 |
| Finished | Jun 29 08:31:42 PM PDT 24 |
| Peak memory | 575528 kb |
| Host | smart-f57e043a-22c7-481d-859d-a8661e0807e7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3555230808 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 55.xbar_stress_all _with_rand_reset.3555230808 |
| Directory | /workspace/55.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/55.xbar_stress_all_with_reset_error.3475648088 |
| Short name | T2547 |
| Test name | |
| Test status | |
| Simulation time | 683858286 ps |
| CPU time | 199.18 seconds |
| Started | Jun 29 08:24:28 PM PDT 24 |
| Finished | Jun 29 08:27:48 PM PDT 24 |
| Peak memory | 576492 kb |
| Host | smart-5fb7dda9-9f00-45a3-9667-927f849177ae |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3475648088 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 55.xbar_stress_al l_with_reset_error.3475648088 |
| Directory | /workspace/55.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/55.xbar_unmapped_addr.924040108 |
| Short name | T2450 |
| Test name | |
| Test status | |
| Simulation time | 403460939 ps |
| CPU time | 21.03 seconds |
| Started | Jun 29 08:24:21 PM PDT 24 |
| Finished | Jun 29 08:24:43 PM PDT 24 |
| Peak memory | 575376 kb |
| Host | smart-2401728a-1465-4ccc-8688-3f41cd77d26e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=924040108 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 55.xbar_unmapped_addr.924040108 |
| Directory | /workspace/55.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/56.xbar_access_same_device.854499015 |
| Short name | T2097 |
| Test name | |
| Test status | |
| Simulation time | 344865419 ps |
| CPU time | 18.75 seconds |
| Started | Jun 29 08:24:49 PM PDT 24 |
| Finished | Jun 29 08:25:08 PM PDT 24 |
| Peak memory | 575292 kb |
| Host | smart-a7ba200e-98ce-4734-88e4-4361309367dd |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=854499015 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 56.xbar_access_same_device. 854499015 |
| Directory | /workspace/56.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/56.xbar_access_same_device_slow_rsp.2043705037 |
| Short name | T1304 |
| Test name | |
| Test status | |
| Simulation time | 11144982388 ps |
| CPU time | 190.65 seconds |
| Started | Jun 29 08:24:31 PM PDT 24 |
| Finished | Jun 29 08:27:41 PM PDT 24 |
| Peak memory | 574192 kb |
| Host | smart-78baa33d-7828-416b-b054-43b12abe09f3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2043705037 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 56.xbar_access_same_ device_slow_rsp.2043705037 |
| Directory | /workspace/56.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/56.xbar_error_and_unmapped_addr.1893019137 |
| Short name | T1822 |
| Test name | |
| Test status | |
| Simulation time | 127478954 ps |
| CPU time | 14.74 seconds |
| Started | Jun 29 08:24:30 PM PDT 24 |
| Finished | Jun 29 08:24:45 PM PDT 24 |
| Peak memory | 574500 kb |
| Host | smart-19d700e7-4a7d-4738-8ae5-1ee8f89fb9c4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1893019137 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 56.xbar_error_and_unmapped_add r.1893019137 |
| Directory | /workspace/56.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/56.xbar_error_random.2826557806 |
| Short name | T2314 |
| Test name | |
| Test status | |
| Simulation time | 154800871 ps |
| CPU time | 16.24 seconds |
| Started | Jun 29 08:24:30 PM PDT 24 |
| Finished | Jun 29 08:24:46 PM PDT 24 |
| Peak memory | 574252 kb |
| Host | smart-a9117742-30cf-467a-9450-d1923b8936f8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2826557806 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 56.xbar_error_random.2826557806 |
| Directory | /workspace/56.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/56.xbar_random.2549992829 |
| Short name | T2525 |
| Test name | |
| Test status | |
| Simulation time | 320235382 ps |
| CPU time | 33.96 seconds |
| Started | Jun 29 08:24:25 PM PDT 24 |
| Finished | Jun 29 08:25:00 PM PDT 24 |
| Peak memory | 575320 kb |
| Host | smart-3e7d3ec1-1c97-4ebb-93dd-ab74f18cd16b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2549992829 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 56.xbar_random.2549992829 |
| Directory | /workspace/56.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/56.xbar_random_large_delays.3641653767 |
| Short name | T2836 |
| Test name | |
| Test status | |
| Simulation time | 75753278054 ps |
| CPU time | 827.03 seconds |
| Started | Jun 29 08:24:23 PM PDT 24 |
| Finished | Jun 29 08:38:11 PM PDT 24 |
| Peak memory | 575384 kb |
| Host | smart-5eb81108-8050-4903-b71b-f5c5301734b8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3641653767 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 56.xbar_random_large_delays.3641653767 |
| Directory | /workspace/56.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/56.xbar_random_slow_rsp.3254844297 |
| Short name | T2838 |
| Test name | |
| Test status | |
| Simulation time | 52449250906 ps |
| CPU time | 899.1 seconds |
| Started | Jun 29 08:24:21 PM PDT 24 |
| Finished | Jun 29 08:39:21 PM PDT 24 |
| Peak memory | 575400 kb |
| Host | smart-e81f0aed-0900-43eb-a426-edd13bfc2b76 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3254844297 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 56.xbar_random_slow_rsp.3254844297 |
| Directory | /workspace/56.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/56.xbar_random_zero_delays.4182138856 |
| Short name | T1782 |
| Test name | |
| Test status | |
| Simulation time | 300787683 ps |
| CPU time | 25.77 seconds |
| Started | Jun 29 08:24:28 PM PDT 24 |
| Finished | Jun 29 08:24:54 PM PDT 24 |
| Peak memory | 574248 kb |
| Host | smart-22cf8046-35c5-4402-afc0-803705a2c67c |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4182138856 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 56.xbar_random_zero_del ays.4182138856 |
| Directory | /workspace/56.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/56.xbar_same_source.45473856 |
| Short name | T512 |
| Test name | |
| Test status | |
| Simulation time | 182574922 ps |
| CPU time | 16.27 seconds |
| Started | Jun 29 08:24:49 PM PDT 24 |
| Finished | Jun 29 08:25:05 PM PDT 24 |
| Peak memory | 575288 kb |
| Host | smart-cb048859-7c4a-4b72-808d-6044ca93224b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45473856 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 56.xbar_same_source.45473856 |
| Directory | /workspace/56.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/56.xbar_smoke.560477718 |
| Short name | T2800 |
| Test name | |
| Test status | |
| Simulation time | 152970096 ps |
| CPU time | 7.99 seconds |
| Started | Jun 29 08:24:22 PM PDT 24 |
| Finished | Jun 29 08:24:30 PM PDT 24 |
| Peak memory | 574128 kb |
| Host | smart-df551625-3bd0-473a-a7dc-ef7ca3d8c6bd |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=560477718 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 56.xbar_smoke.560477718 |
| Directory | /workspace/56.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/56.xbar_smoke_large_delays.2237068022 |
| Short name | T1551 |
| Test name | |
| Test status | |
| Simulation time | 5809552242 ps |
| CPU time | 65.5 seconds |
| Started | Jun 29 08:24:23 PM PDT 24 |
| Finished | Jun 29 08:25:29 PM PDT 24 |
| Peak memory | 574324 kb |
| Host | smart-4baec5b5-edf4-4178-a7d5-a3b46c5840b0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2237068022 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 56.xbar_smoke_large_delays.2237068022 |
| Directory | /workspace/56.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/56.xbar_smoke_slow_rsp.1941663892 |
| Short name | T2320 |
| Test name | |
| Test status | |
| Simulation time | 4429434198 ps |
| CPU time | 74.48 seconds |
| Started | Jun 29 08:24:23 PM PDT 24 |
| Finished | Jun 29 08:25:38 PM PDT 24 |
| Peak memory | 574196 kb |
| Host | smart-8f9c4cd0-7f15-4f80-bd96-856b00f48b85 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1941663892 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 56.xbar_smoke_slow_rsp.1941663892 |
| Directory | /workspace/56.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/56.xbar_smoke_zero_delays.3761429660 |
| Short name | T2791 |
| Test name | |
| Test status | |
| Simulation time | 44253272 ps |
| CPU time | 6.38 seconds |
| Started | Jun 29 08:24:25 PM PDT 24 |
| Finished | Jun 29 08:24:31 PM PDT 24 |
| Peak memory | 566024 kb |
| Host | smart-1f455abf-e92c-46b2-9da0-c8d1a2f5f913 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3761429660 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 56.xbar_smoke_zero_delay s.3761429660 |
| Directory | /workspace/56.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/56.xbar_stress_all.489898010 |
| Short name | T1593 |
| Test name | |
| Test status | |
| Simulation time | 1853683616 ps |
| CPU time | 163.78 seconds |
| Started | Jun 29 08:24:31 PM PDT 24 |
| Finished | Jun 29 08:27:15 PM PDT 24 |
| Peak memory | 575456 kb |
| Host | smart-7334d43a-281e-454f-9221-ce0c8bac344f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=489898010 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 56.xbar_stress_all.489898010 |
| Directory | /workspace/56.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/56.xbar_stress_all_with_error.4208166476 |
| Short name | T1578 |
| Test name | |
| Test status | |
| Simulation time | 2736090486 ps |
| CPU time | 121.31 seconds |
| Started | Jun 29 08:24:29 PM PDT 24 |
| Finished | Jun 29 08:26:31 PM PDT 24 |
| Peak memory | 574436 kb |
| Host | smart-ee53b120-8b43-4109-b1ce-5653024f8129 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4208166476 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 56.xbar_stress_all_with_error.4208166476 |
| Directory | /workspace/56.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/56.xbar_stress_all_with_reset_error.3638267050 |
| Short name | T1738 |
| Test name | |
| Test status | |
| Simulation time | 11031225984 ps |
| CPU time | 575.28 seconds |
| Started | Jun 29 08:24:31 PM PDT 24 |
| Finished | Jun 29 08:34:07 PM PDT 24 |
| Peak memory | 576544 kb |
| Host | smart-6423e666-f958-49f1-ae80-07e1d279c046 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3638267050 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 56.xbar_stress_al l_with_reset_error.3638267050 |
| Directory | /workspace/56.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/56.xbar_unmapped_addr.1379352334 |
| Short name | T618 |
| Test name | |
| Test status | |
| Simulation time | 114141750 ps |
| CPU time | 15.85 seconds |
| Started | Jun 29 08:24:48 PM PDT 24 |
| Finished | Jun 29 08:25:04 PM PDT 24 |
| Peak memory | 575356 kb |
| Host | smart-54d587af-c67a-4c86-8795-096745219403 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1379352334 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 56.xbar_unmapped_addr.1379352334 |
| Directory | /workspace/56.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/57.xbar_access_same_device.192735792 |
| Short name | T2281 |
| Test name | |
| Test status | |
| Simulation time | 100563723 ps |
| CPU time | 14.02 seconds |
| Started | Jun 29 08:24:31 PM PDT 24 |
| Finished | Jun 29 08:24:45 PM PDT 24 |
| Peak memory | 575300 kb |
| Host | smart-cb59fb8c-555b-4d98-a35f-0e3e1bfda604 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=192735792 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 57.xbar_access_same_device. 192735792 |
| Directory | /workspace/57.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/57.xbar_access_same_device_slow_rsp.3594004979 |
| Short name | T2874 |
| Test name | |
| Test status | |
| Simulation time | 30860808528 ps |
| CPU time | 548.96 seconds |
| Started | Jun 29 08:24:48 PM PDT 24 |
| Finished | Jun 29 08:33:57 PM PDT 24 |
| Peak memory | 575432 kb |
| Host | smart-42ed99fc-3b5b-4325-995e-693bc31c33fd |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3594004979 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 57.xbar_access_same_ device_slow_rsp.3594004979 |
| Directory | /workspace/57.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/57.xbar_error_and_unmapped_addr.2032820643 |
| Short name | T2293 |
| Test name | |
| Test status | |
| Simulation time | 140014017 ps |
| CPU time | 20.4 seconds |
| Started | Jun 29 08:24:39 PM PDT 24 |
| Finished | Jun 29 08:24:59 PM PDT 24 |
| Peak memory | 574508 kb |
| Host | smart-655db2f9-1956-4725-bbfd-c7ff92447633 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2032820643 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 57.xbar_error_and_unmapped_add r.2032820643 |
| Directory | /workspace/57.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/57.xbar_error_random.412630025 |
| Short name | T2670 |
| Test name | |
| Test status | |
| Simulation time | 486762032 ps |
| CPU time | 36.78 seconds |
| Started | Jun 29 08:24:49 PM PDT 24 |
| Finished | Jun 29 08:25:26 PM PDT 24 |
| Peak memory | 573932 kb |
| Host | smart-6ad70e30-e31d-4985-884e-bb18ce28526e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=412630025 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 57.xbar_error_random.412630025 |
| Directory | /workspace/57.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/57.xbar_random.1974071955 |
| Short name | T2116 |
| Test name | |
| Test status | |
| Simulation time | 258889909 ps |
| CPU time | 29.33 seconds |
| Started | Jun 29 08:24:32 PM PDT 24 |
| Finished | Jun 29 08:25:01 PM PDT 24 |
| Peak memory | 575344 kb |
| Host | smart-1bcf2174-0cf3-4012-8941-fcc3fd62a49e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1974071955 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 57.xbar_random.1974071955 |
| Directory | /workspace/57.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/57.xbar_random_large_delays.793081117 |
| Short name | T1802 |
| Test name | |
| Test status | |
| Simulation time | 64050616809 ps |
| CPU time | 695.47 seconds |
| Started | Jun 29 08:24:48 PM PDT 24 |
| Finished | Jun 29 08:36:24 PM PDT 24 |
| Peak memory | 575392 kb |
| Host | smart-3e7da1aa-aa62-4b08-84d1-a2cb99656be2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=793081117 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 57.xbar_random_large_delays.793081117 |
| Directory | /workspace/57.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/57.xbar_random_slow_rsp.206794572 |
| Short name | T2106 |
| Test name | |
| Test status | |
| Simulation time | 46963013454 ps |
| CPU time | 782.78 seconds |
| Started | Jun 29 08:24:35 PM PDT 24 |
| Finished | Jun 29 08:37:38 PM PDT 24 |
| Peak memory | 575388 kb |
| Host | smart-3a592666-1032-4854-a696-d51607ae0af3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=206794572 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 57.xbar_random_slow_rsp.206794572 |
| Directory | /workspace/57.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/57.xbar_random_zero_delays.3902173700 |
| Short name | T490 |
| Test name | |
| Test status | |
| Simulation time | 274268386 ps |
| CPU time | 31.02 seconds |
| Started | Jun 29 08:24:30 PM PDT 24 |
| Finished | Jun 29 08:25:01 PM PDT 24 |
| Peak memory | 574228 kb |
| Host | smart-9aaa565b-4eda-45e8-bfa5-3e2f6b64dc84 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3902173700 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 57.xbar_random_zero_del ays.3902173700 |
| Directory | /workspace/57.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/57.xbar_same_source.521666909 |
| Short name | T2401 |
| Test name | |
| Test status | |
| Simulation time | 126311206 ps |
| CPU time | 12.26 seconds |
| Started | Jun 29 08:24:30 PM PDT 24 |
| Finished | Jun 29 08:24:43 PM PDT 24 |
| Peak memory | 575272 kb |
| Host | smart-39974cbb-a99e-444b-a1d8-7443f10d4916 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=521666909 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 57.xbar_same_source.521666909 |
| Directory | /workspace/57.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/57.xbar_smoke.3724396731 |
| Short name | T2600 |
| Test name | |
| Test status | |
| Simulation time | 37211148 ps |
| CPU time | 6.21 seconds |
| Started | Jun 29 08:24:32 PM PDT 24 |
| Finished | Jun 29 08:24:38 PM PDT 24 |
| Peak memory | 574256 kb |
| Host | smart-918c1839-a3fd-48e2-98f6-563c5505a96a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3724396731 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 57.xbar_smoke.3724396731 |
| Directory | /workspace/57.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/57.xbar_smoke_large_delays.2789853572 |
| Short name | T1697 |
| Test name | |
| Test status | |
| Simulation time | 8254030159 ps |
| CPU time | 86.28 seconds |
| Started | Jun 29 08:24:48 PM PDT 24 |
| Finished | Jun 29 08:26:15 PM PDT 24 |
| Peak memory | 574320 kb |
| Host | smart-14b458b7-ae4c-4d6a-b381-912fefefb2c8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2789853572 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 57.xbar_smoke_large_delays.2789853572 |
| Directory | /workspace/57.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/57.xbar_smoke_slow_rsp.385865873 |
| Short name | T1319 |
| Test name | |
| Test status | |
| Simulation time | 5564456646 ps |
| CPU time | 93.61 seconds |
| Started | Jun 29 08:24:32 PM PDT 24 |
| Finished | Jun 29 08:26:06 PM PDT 24 |
| Peak memory | 574172 kb |
| Host | smart-b062a51b-d364-4e80-9ed7-81da3c80b0b5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=385865873 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 57.xbar_smoke_slow_rsp.385865873 |
| Directory | /workspace/57.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/57.xbar_smoke_zero_delays.3742009317 |
| Short name | T1401 |
| Test name | |
| Test status | |
| Simulation time | 39876339 ps |
| CPU time | 6.54 seconds |
| Started | Jun 29 08:24:29 PM PDT 24 |
| Finished | Jun 29 08:24:36 PM PDT 24 |
| Peak memory | 574204 kb |
| Host | smart-fc23d114-3092-4cdb-8c3b-9d430bdde4d2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3742009317 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 57.xbar_smoke_zero_delay s.3742009317 |
| Directory | /workspace/57.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/57.xbar_stress_all.2673108740 |
| Short name | T470 |
| Test name | |
| Test status | |
| Simulation time | 12845104041 ps |
| CPU time | 511.74 seconds |
| Started | Jun 29 08:24:40 PM PDT 24 |
| Finished | Jun 29 08:33:12 PM PDT 24 |
| Peak memory | 574460 kb |
| Host | smart-460c7d1b-99be-4823-b8d1-0dac435e3592 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2673108740 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 57.xbar_stress_all.2673108740 |
| Directory | /workspace/57.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/57.xbar_stress_all_with_error.2533963707 |
| Short name | T774 |
| Test name | |
| Test status | |
| Simulation time | 4758154157 ps |
| CPU time | 181.44 seconds |
| Started | Jun 29 08:24:39 PM PDT 24 |
| Finished | Jun 29 08:27:41 PM PDT 24 |
| Peak memory | 574368 kb |
| Host | smart-58573dae-2e0a-4729-8e67-6ca9fa09ea91 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2533963707 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 57.xbar_stress_all_with_error.2533963707 |
| Directory | /workspace/57.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/57.xbar_stress_all_with_rand_reset.1156242164 |
| Short name | T2221 |
| Test name | |
| Test status | |
| Simulation time | 83789377 ps |
| CPU time | 27.01 seconds |
| Started | Jun 29 08:24:40 PM PDT 24 |
| Finished | Jun 29 08:25:08 PM PDT 24 |
| Peak memory | 574408 kb |
| Host | smart-e9f926ac-bdfc-475a-80d6-27927793adf6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1156242164 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 57.xbar_stress_all _with_rand_reset.1156242164 |
| Directory | /workspace/57.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/57.xbar_stress_all_with_reset_error.1825454935 |
| Short name | T2792 |
| Test name | |
| Test status | |
| Simulation time | 397926174 ps |
| CPU time | 135.4 seconds |
| Started | Jun 29 08:24:38 PM PDT 24 |
| Finished | Jun 29 08:26:54 PM PDT 24 |
| Peak memory | 574408 kb |
| Host | smart-3cf494b4-b297-47a7-bcd1-f356ffc20110 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1825454935 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 57.xbar_stress_al l_with_reset_error.1825454935 |
| Directory | /workspace/57.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/57.xbar_unmapped_addr.4212919170 |
| Short name | T2413 |
| Test name | |
| Test status | |
| Simulation time | 188854233 ps |
| CPU time | 23.77 seconds |
| Started | Jun 29 08:24:37 PM PDT 24 |
| Finished | Jun 29 08:25:01 PM PDT 24 |
| Peak memory | 574300 kb |
| Host | smart-9f8cadcd-adcb-4a76-92ad-4cfa60597c35 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4212919170 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 57.xbar_unmapped_addr.4212919170 |
| Directory | /workspace/57.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/58.xbar_access_same_device.1803452940 |
| Short name | T2588 |
| Test name | |
| Test status | |
| Simulation time | 1214895604 ps |
| CPU time | 84.03 seconds |
| Started | Jun 29 08:24:46 PM PDT 24 |
| Finished | Jun 29 08:26:10 PM PDT 24 |
| Peak memory | 574276 kb |
| Host | smart-4f1dde1b-06eb-414c-8ccb-d8e3894a1eb0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1803452940 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 58.xbar_access_same_device .1803452940 |
| Directory | /workspace/58.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/58.xbar_access_same_device_slow_rsp.1224670536 |
| Short name | T2585 |
| Test name | |
| Test status | |
| Simulation time | 107699011179 ps |
| CPU time | 1880.04 seconds |
| Started | Jun 29 08:24:45 PM PDT 24 |
| Finished | Jun 29 08:56:06 PM PDT 24 |
| Peak memory | 575428 kb |
| Host | smart-f1a7f470-d35e-41e2-8b92-9cd358fda5cc |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1224670536 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 58.xbar_access_same_ device_slow_rsp.1224670536 |
| Directory | /workspace/58.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/58.xbar_error_and_unmapped_addr.3996809765 |
| Short name | T2849 |
| Test name | |
| Test status | |
| Simulation time | 347443763 ps |
| CPU time | 16.61 seconds |
| Started | Jun 29 08:24:45 PM PDT 24 |
| Finished | Jun 29 08:25:01 PM PDT 24 |
| Peak memory | 574520 kb |
| Host | smart-60263f2e-3e46-4d2e-b268-0cb82d53fd04 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3996809765 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 58.xbar_error_and_unmapped_add r.3996809765 |
| Directory | /workspace/58.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/58.xbar_error_random.1896673893 |
| Short name | T1416 |
| Test name | |
| Test status | |
| Simulation time | 630059782 ps |
| CPU time | 24.74 seconds |
| Started | Jun 29 08:24:45 PM PDT 24 |
| Finished | Jun 29 08:25:10 PM PDT 24 |
| Peak memory | 574448 kb |
| Host | smart-59883942-b601-4ea9-ad9e-5b844ebe4246 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1896673893 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 58.xbar_error_random.1896673893 |
| Directory | /workspace/58.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/58.xbar_random.1987574103 |
| Short name | T2226 |
| Test name | |
| Test status | |
| Simulation time | 1027693235 ps |
| CPU time | 44.94 seconds |
| Started | Jun 29 08:24:38 PM PDT 24 |
| Finished | Jun 29 08:25:23 PM PDT 24 |
| Peak memory | 575328 kb |
| Host | smart-1e9bdf56-caa7-45c2-af54-0ad59e8a6222 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1987574103 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 58.xbar_random.1987574103 |
| Directory | /workspace/58.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/58.xbar_random_large_delays.1968301152 |
| Short name | T2172 |
| Test name | |
| Test status | |
| Simulation time | 37621124503 ps |
| CPU time | 432.97 seconds |
| Started | Jun 29 08:24:38 PM PDT 24 |
| Finished | Jun 29 08:31:51 PM PDT 24 |
| Peak memory | 575388 kb |
| Host | smart-100f30c0-6dea-45d5-beed-7163f764a91f |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1968301152 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 58.xbar_random_large_delays.1968301152 |
| Directory | /workspace/58.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/58.xbar_random_slow_rsp.1516641911 |
| Short name | T1608 |
| Test name | |
| Test status | |
| Simulation time | 11066211582 ps |
| CPU time | 193.81 seconds |
| Started | Jun 29 08:24:40 PM PDT 24 |
| Finished | Jun 29 08:27:54 PM PDT 24 |
| Peak memory | 574336 kb |
| Host | smart-a1669d2f-1935-4eb3-9a83-0ec5dfaef04f |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1516641911 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 58.xbar_random_slow_rsp.1516641911 |
| Directory | /workspace/58.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/58.xbar_random_zero_delays.3420237346 |
| Short name | T1789 |
| Test name | |
| Test status | |
| Simulation time | 328080772 ps |
| CPU time | 31.05 seconds |
| Started | Jun 29 08:24:39 PM PDT 24 |
| Finished | Jun 29 08:25:10 PM PDT 24 |
| Peak memory | 575320 kb |
| Host | smart-6df1f02c-063c-4fe2-bcec-bd72d0e5454a |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3420237346 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 58.xbar_random_zero_del ays.3420237346 |
| Directory | /workspace/58.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/58.xbar_same_source.3878959792 |
| Short name | T1773 |
| Test name | |
| Test status | |
| Simulation time | 1479031731 ps |
| CPU time | 52.31 seconds |
| Started | Jun 29 08:24:45 PM PDT 24 |
| Finished | Jun 29 08:25:38 PM PDT 24 |
| Peak memory | 575292 kb |
| Host | smart-797e0be9-0f08-471e-966f-c6cf17349c0a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3878959792 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 58.xbar_same_source.3878959792 |
| Directory | /workspace/58.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/58.xbar_smoke.1493656315 |
| Short name | T1616 |
| Test name | |
| Test status | |
| Simulation time | 220373554 ps |
| CPU time | 10.17 seconds |
| Started | Jun 29 08:24:40 PM PDT 24 |
| Finished | Jun 29 08:24:50 PM PDT 24 |
| Peak memory | 574252 kb |
| Host | smart-6aa69e4b-6755-4105-af06-46f8d8dc58aa |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1493656315 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 58.xbar_smoke.1493656315 |
| Directory | /workspace/58.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/58.xbar_smoke_large_delays.2324501169 |
| Short name | T1472 |
| Test name | |
| Test status | |
| Simulation time | 9233759439 ps |
| CPU time | 94.49 seconds |
| Started | Jun 29 08:24:40 PM PDT 24 |
| Finished | Jun 29 08:26:15 PM PDT 24 |
| Peak memory | 574220 kb |
| Host | smart-73759df3-dcfc-4ec2-ba71-ae2dda8fb32c |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2324501169 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 58.xbar_smoke_large_delays.2324501169 |
| Directory | /workspace/58.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/58.xbar_smoke_slow_rsp.253752824 |
| Short name | T2437 |
| Test name | |
| Test status | |
| Simulation time | 5961944195 ps |
| CPU time | 109.26 seconds |
| Started | Jun 29 08:24:38 PM PDT 24 |
| Finished | Jun 29 08:26:28 PM PDT 24 |
| Peak memory | 574304 kb |
| Host | smart-4ab25d6e-75bb-4427-be69-5e84231732c3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=253752824 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 58.xbar_smoke_slow_rsp.253752824 |
| Directory | /workspace/58.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/58.xbar_smoke_zero_delays.1760300112 |
| Short name | T2802 |
| Test name | |
| Test status | |
| Simulation time | 51456593 ps |
| CPU time | 7.07 seconds |
| Started | Jun 29 08:24:39 PM PDT 24 |
| Finished | Jun 29 08:24:46 PM PDT 24 |
| Peak memory | 574220 kb |
| Host | smart-58568fbc-a25d-4cb3-a292-91bf97f700db |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1760300112 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 58.xbar_smoke_zero_delay s.1760300112 |
| Directory | /workspace/58.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/58.xbar_stress_all.435725670 |
| Short name | T2621 |
| Test name | |
| Test status | |
| Simulation time | 1147700035 ps |
| CPU time | 112.54 seconds |
| Started | Jun 29 08:24:44 PM PDT 24 |
| Finished | Jun 29 08:26:37 PM PDT 24 |
| Peak memory | 575444 kb |
| Host | smart-7e228ae1-d2fa-43cd-9642-415e74eabc89 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=435725670 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 58.xbar_stress_all.435725670 |
| Directory | /workspace/58.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/58.xbar_stress_all_with_error.3827423547 |
| Short name | T2455 |
| Test name | |
| Test status | |
| Simulation time | 3416362642 ps |
| CPU time | 253.67 seconds |
| Started | Jun 29 08:24:45 PM PDT 24 |
| Finished | Jun 29 08:28:59 PM PDT 24 |
| Peak memory | 574456 kb |
| Host | smart-6c052683-5f4b-410c-83a1-e0b24a5d4660 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3827423547 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 58.xbar_stress_all_with_error.3827423547 |
| Directory | /workspace/58.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/58.xbar_stress_all_with_rand_reset.4139885862 |
| Short name | T2384 |
| Test name | |
| Test status | |
| Simulation time | 6827985978 ps |
| CPU time | 408.35 seconds |
| Started | Jun 29 08:24:45 PM PDT 24 |
| Finished | Jun 29 08:31:34 PM PDT 24 |
| Peak memory | 575516 kb |
| Host | smart-2f7aaf27-b46a-4ee8-ab2a-998b01a67c56 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4139885862 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 58.xbar_stress_all _with_rand_reset.4139885862 |
| Directory | /workspace/58.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/58.xbar_stress_all_with_reset_error.1576816601 |
| Short name | T791 |
| Test name | |
| Test status | |
| Simulation time | 2893794853 ps |
| CPU time | 314.7 seconds |
| Started | Jun 29 08:24:46 PM PDT 24 |
| Finished | Jun 29 08:30:01 PM PDT 24 |
| Peak memory | 574744 kb |
| Host | smart-affc772d-082f-4ed8-8fb0-5e17c5d85063 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1576816601 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 58.xbar_stress_al l_with_reset_error.1576816601 |
| Directory | /workspace/58.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/58.xbar_unmapped_addr.1387345944 |
| Short name | T2131 |
| Test name | |
| Test status | |
| Simulation time | 283495349 ps |
| CPU time | 31.91 seconds |
| Started | Jun 29 08:24:50 PM PDT 24 |
| Finished | Jun 29 08:25:22 PM PDT 24 |
| Peak memory | 575364 kb |
| Host | smart-a9a36ef2-4213-47df-8aef-027f40479f1c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1387345944 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 58.xbar_unmapped_addr.1387345944 |
| Directory | /workspace/58.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/59.xbar_access_same_device.279036895 |
| Short name | T2186 |
| Test name | |
| Test status | |
| Simulation time | 3432973773 ps |
| CPU time | 146.25 seconds |
| Started | Jun 29 08:24:55 PM PDT 24 |
| Finished | Jun 29 08:27:22 PM PDT 24 |
| Peak memory | 575368 kb |
| Host | smart-8ee3f925-a1a9-485a-91d2-5c4e0da01326 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=279036895 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 59.xbar_access_same_device. 279036895 |
| Directory | /workspace/59.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/59.xbar_access_same_device_slow_rsp.434843933 |
| Short name | T2818 |
| Test name | |
| Test status | |
| Simulation time | 43254030134 ps |
| CPU time | 776.82 seconds |
| Started | Jun 29 08:24:54 PM PDT 24 |
| Finished | Jun 29 08:37:52 PM PDT 24 |
| Peak memory | 574384 kb |
| Host | smart-0ea76c8c-b8c5-447e-9d25-6cf5e795a572 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=434843933 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 59.xbar_access_same_d evice_slow_rsp.434843933 |
| Directory | /workspace/59.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/59.xbar_error_and_unmapped_addr.4249765049 |
| Short name | T2686 |
| Test name | |
| Test status | |
| Simulation time | 41798589 ps |
| CPU time | 7.33 seconds |
| Started | Jun 29 08:24:54 PM PDT 24 |
| Finished | Jun 29 08:25:01 PM PDT 24 |
| Peak memory | 574264 kb |
| Host | smart-22bcdd8c-e63b-46db-90c7-e394f819037d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4249765049 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 59.xbar_error_and_unmapped_add r.4249765049 |
| Directory | /workspace/59.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/59.xbar_error_random.2940953138 |
| Short name | T2392 |
| Test name | |
| Test status | |
| Simulation time | 588616503 ps |
| CPU time | 51.43 seconds |
| Started | Jun 29 08:24:57 PM PDT 24 |
| Finished | Jun 29 08:25:49 PM PDT 24 |
| Peak memory | 574464 kb |
| Host | smart-a055b4f8-6827-4025-9784-58cc10d7abc5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2940953138 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 59.xbar_error_random.2940953138 |
| Directory | /workspace/59.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/59.xbar_random.3181285018 |
| Short name | T1993 |
| Test name | |
| Test status | |
| Simulation time | 550828109 ps |
| CPU time | 52.75 seconds |
| Started | Jun 29 08:24:55 PM PDT 24 |
| Finished | Jun 29 08:25:48 PM PDT 24 |
| Peak memory | 575336 kb |
| Host | smart-01a124f1-f6a5-4b50-b574-ea32abcddf94 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3181285018 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 59.xbar_random.3181285018 |
| Directory | /workspace/59.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/59.xbar_random_large_delays.1688661071 |
| Short name | T1968 |
| Test name | |
| Test status | |
| Simulation time | 40188669246 ps |
| CPU time | 422.65 seconds |
| Started | Jun 29 08:24:54 PM PDT 24 |
| Finished | Jun 29 08:31:57 PM PDT 24 |
| Peak memory | 575388 kb |
| Host | smart-3c47283a-039a-44f7-9838-8dda375d78a1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1688661071 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 59.xbar_random_large_delays.1688661071 |
| Directory | /workspace/59.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/59.xbar_random_slow_rsp.2461445160 |
| Short name | T463 |
| Test name | |
| Test status | |
| Simulation time | 61421982710 ps |
| CPU time | 1050.55 seconds |
| Started | Jun 29 08:24:55 PM PDT 24 |
| Finished | Jun 29 08:42:26 PM PDT 24 |
| Peak memory | 575384 kb |
| Host | smart-05cd1362-3825-43d8-9dd2-2552b66a10ab |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2461445160 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 59.xbar_random_slow_rsp.2461445160 |
| Directory | /workspace/59.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/59.xbar_random_zero_delays.2948141035 |
| Short name | T626 |
| Test name | |
| Test status | |
| Simulation time | 294812615 ps |
| CPU time | 26.51 seconds |
| Started | Jun 29 08:24:57 PM PDT 24 |
| Finished | Jun 29 08:25:24 PM PDT 24 |
| Peak memory | 574232 kb |
| Host | smart-54a18c7c-3c09-4dd7-a0ee-4c59b7a97ea1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2948141035 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 59.xbar_random_zero_del ays.2948141035 |
| Directory | /workspace/59.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/59.xbar_same_source.2228768694 |
| Short name | T1934 |
| Test name | |
| Test status | |
| Simulation time | 352066096 ps |
| CPU time | 13.72 seconds |
| Started | Jun 29 08:24:54 PM PDT 24 |
| Finished | Jun 29 08:25:09 PM PDT 24 |
| Peak memory | 575272 kb |
| Host | smart-04341211-3e79-4d59-a882-7122a1eb61d2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2228768694 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 59.xbar_same_source.2228768694 |
| Directory | /workspace/59.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/59.xbar_smoke.618168289 |
| Short name | T2343 |
| Test name | |
| Test status | |
| Simulation time | 212435690 ps |
| CPU time | 9.38 seconds |
| Started | Jun 29 08:24:44 PM PDT 24 |
| Finished | Jun 29 08:24:54 PM PDT 24 |
| Peak memory | 574268 kb |
| Host | smart-6fa14350-599b-43ba-a3f7-ec33af720884 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=618168289 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 59.xbar_smoke.618168289 |
| Directory | /workspace/59.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/59.xbar_smoke_large_delays.1762916666 |
| Short name | T1335 |
| Test name | |
| Test status | |
| Simulation time | 9085655698 ps |
| CPU time | 93.61 seconds |
| Started | Jun 29 08:24:47 PM PDT 24 |
| Finished | Jun 29 08:26:20 PM PDT 24 |
| Peak memory | 566004 kb |
| Host | smart-9c63b091-ef99-4223-a6c1-6467b58c00c9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1762916666 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 59.xbar_smoke_large_delays.1762916666 |
| Directory | /workspace/59.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/59.xbar_smoke_slow_rsp.3580237313 |
| Short name | T2550 |
| Test name | |
| Test status | |
| Simulation time | 3744012534 ps |
| CPU time | 62.08 seconds |
| Started | Jun 29 08:24:56 PM PDT 24 |
| Finished | Jun 29 08:25:58 PM PDT 24 |
| Peak memory | 565928 kb |
| Host | smart-733a3b4f-8cf2-48de-9f5f-afb05def040f |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3580237313 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 59.xbar_smoke_slow_rsp.3580237313 |
| Directory | /workspace/59.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/59.xbar_smoke_zero_delays.3941359175 |
| Short name | T2676 |
| Test name | |
| Test status | |
| Simulation time | 56886074 ps |
| CPU time | 7.43 seconds |
| Started | Jun 29 08:24:49 PM PDT 24 |
| Finished | Jun 29 08:24:57 PM PDT 24 |
| Peak memory | 574248 kb |
| Host | smart-72af1bfb-fbd6-46f7-bdee-e3e1eaab6a88 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3941359175 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 59.xbar_smoke_zero_delay s.3941359175 |
| Directory | /workspace/59.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/59.xbar_stress_all.2665063359 |
| Short name | T2535 |
| Test name | |
| Test status | |
| Simulation time | 4119915546 ps |
| CPU time | 364.98 seconds |
| Started | Jun 29 08:24:54 PM PDT 24 |
| Finished | Jun 29 08:30:59 PM PDT 24 |
| Peak memory | 575456 kb |
| Host | smart-e594314c-482b-46d2-b511-ba453eeb5768 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2665063359 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 59.xbar_stress_all.2665063359 |
| Directory | /workspace/59.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/59.xbar_stress_all_with_error.4220267019 |
| Short name | T1438 |
| Test name | |
| Test status | |
| Simulation time | 3010848171 ps |
| CPU time | 237.25 seconds |
| Started | Jun 29 08:24:57 PM PDT 24 |
| Finished | Jun 29 08:28:54 PM PDT 24 |
| Peak memory | 574612 kb |
| Host | smart-c292f3cd-934a-4f4a-b5b3-711f85cb4f55 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4220267019 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 59.xbar_stress_all_with_error.4220267019 |
| Directory | /workspace/59.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/59.xbar_stress_all_with_rand_reset.3192607031 |
| Short name | T2526 |
| Test name | |
| Test status | |
| Simulation time | 166926970 ps |
| CPU time | 65.17 seconds |
| Started | Jun 29 08:24:54 PM PDT 24 |
| Finished | Jun 29 08:26:00 PM PDT 24 |
| Peak memory | 575444 kb |
| Host | smart-db694118-490b-4ad0-be1d-25962bd03768 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3192607031 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 59.xbar_stress_all _with_rand_reset.3192607031 |
| Directory | /workspace/59.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/59.xbar_stress_all_with_reset_error.3758347209 |
| Short name | T2052 |
| Test name | |
| Test status | |
| Simulation time | 9304062927 ps |
| CPU time | 415.1 seconds |
| Started | Jun 29 08:24:57 PM PDT 24 |
| Finished | Jun 29 08:31:52 PM PDT 24 |
| Peak memory | 576508 kb |
| Host | smart-5699207f-f58d-40de-ac61-60c13f6d07da |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3758347209 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 59.xbar_stress_al l_with_reset_error.3758347209 |
| Directory | /workspace/59.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/59.xbar_unmapped_addr.497570633 |
| Short name | T566 |
| Test name | |
| Test status | |
| Simulation time | 312679412 ps |
| CPU time | 39.89 seconds |
| Started | Jun 29 08:24:55 PM PDT 24 |
| Finished | Jun 29 08:25:35 PM PDT 24 |
| Peak memory | 574320 kb |
| Host | smart-56662d46-81fa-436a-83c0-6d52a64a7bd6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=497570633 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 59.xbar_unmapped_addr.497570633 |
| Directory | /workspace/59.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/6.chip_csr_rw.498872006 |
| Short name | T391 |
| Test name | |
| Test status | |
| Simulation time | 5894270733 ps |
| CPU time | 630.08 seconds |
| Started | Jun 29 08:12:41 PM PDT 24 |
| Finished | Jun 29 08:23:12 PM PDT 24 |
| Peak memory | 597812 kb |
| Host | smart-0487540f-1057-4e77-9170-dfcd0e03238e |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=498872006 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.chip_csr_rw.498872006 |
| Directory | /workspace/6.chip_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/6.chip_same_csr_outstanding.1620964986 |
| Short name | T2480 |
| Test name | |
| Test status | |
| Simulation time | 15607005118 ps |
| CPU time | 1927.91 seconds |
| Started | Jun 29 08:12:12 PM PDT 24 |
| Finished | Jun 29 08:44:20 PM PDT 24 |
| Peak memory | 591824 kb |
| Host | smart-de98a2b8-d48c-427a-9edb-fc152d18fe27 |
| User | root |
| Command | /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +run_same_csr_outstanding +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1620964986 -assert nopostproc +UVM_TE STNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb - cm_log /dev/null -cm_name 6.chip_same_csr_outstanding.1620964986 |
| Directory | /workspace/6.chip_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/6.chip_tl_errors.2157724873 |
| Short name | T2619 |
| Test name | |
| Test status | |
| Simulation time | 3371172161 ps |
| CPU time | 200.21 seconds |
| Started | Jun 29 08:12:18 PM PDT 24 |
| Finished | Jun 29 08:15:39 PM PDT 24 |
| Peak memory | 603640 kb |
| Host | smart-29115e8e-b936-47de-bf3a-5fa2e002784b |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2157724873 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.chip_tl_errors.2157724873 |
| Directory | /workspace/6.chip_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/6.xbar_access_same_device.3012006099 |
| Short name | T2769 |
| Test name | |
| Test status | |
| Simulation time | 27209432 ps |
| CPU time | 7.99 seconds |
| Started | Jun 29 08:12:28 PM PDT 24 |
| Finished | Jun 29 08:12:37 PM PDT 24 |
| Peak memory | 575072 kb |
| Host | smart-3684ee04-9e7b-446d-b71f-0ee77b9dfab0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3012006099 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.xbar_access_same_device. 3012006099 |
| Directory | /workspace/6.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/6.xbar_access_same_device_slow_rsp.4168441212 |
| Short name | T797 |
| Test name | |
| Test status | |
| Simulation time | 102646058239 ps |
| CPU time | 1883.84 seconds |
| Started | Jun 29 08:12:36 PM PDT 24 |
| Finished | Jun 29 08:44:01 PM PDT 24 |
| Peak memory | 575488 kb |
| Host | smart-45f92bf9-cf44-42e3-ad90-b32a3d28e4d5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4168441212 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.xbar_access_same_d evice_slow_rsp.4168441212 |
| Directory | /workspace/6.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/6.xbar_error_and_unmapped_addr.3268220106 |
| Short name | T2033 |
| Test name | |
| Test status | |
| Simulation time | 961515085 ps |
| CPU time | 46.17 seconds |
| Started | Jun 29 08:12:36 PM PDT 24 |
| Finished | Jun 29 08:13:23 PM PDT 24 |
| Peak memory | 574444 kb |
| Host | smart-833a554f-39ab-4d18-b714-2a50be9c88a5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3268220106 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.xbar_error_and_unmapped_addr .3268220106 |
| Directory | /workspace/6.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/6.xbar_error_random.1825782053 |
| Short name | T1491 |
| Test name | |
| Test status | |
| Simulation time | 1314041926 ps |
| CPU time | 47.42 seconds |
| Started | Jun 29 08:12:28 PM PDT 24 |
| Finished | Jun 29 08:13:16 PM PDT 24 |
| Peak memory | 574272 kb |
| Host | smart-bbc55972-1610-41e3-b238-47d752833524 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1825782053 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.xbar_error_random.1825782053 |
| Directory | /workspace/6.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/6.xbar_random.2681917122 |
| Short name | T1747 |
| Test name | |
| Test status | |
| Simulation time | 516744273 ps |
| CPU time | 46.57 seconds |
| Started | Jun 29 08:12:20 PM PDT 24 |
| Finished | Jun 29 08:13:07 PM PDT 24 |
| Peak memory | 574232 kb |
| Host | smart-cd200fdb-4502-4f25-87e8-0a8c4b3981ed |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2681917122 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.xbar_random.2681917122 |
| Directory | /workspace/6.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/6.xbar_random_large_delays.2530434733 |
| Short name | T2672 |
| Test name | |
| Test status | |
| Simulation time | 26220323608 ps |
| CPU time | 311.15 seconds |
| Started | Jun 29 08:12:27 PM PDT 24 |
| Finished | Jun 29 08:17:38 PM PDT 24 |
| Peak memory | 575376 kb |
| Host | smart-84db9350-94f7-4944-847d-d8cc49d7e223 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2530434733 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.xbar_random_large_delays.2530434733 |
| Directory | /workspace/6.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/6.xbar_random_slow_rsp.1553139452 |
| Short name | T595 |
| Test name | |
| Test status | |
| Simulation time | 60332622383 ps |
| CPU time | 1109.64 seconds |
| Started | Jun 29 08:12:28 PM PDT 24 |
| Finished | Jun 29 08:30:58 PM PDT 24 |
| Peak memory | 575460 kb |
| Host | smart-cffa6db5-9c46-45a2-95ea-86a0776ebe02 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1553139452 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.xbar_random_slow_rsp.1553139452 |
| Directory | /workspace/6.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/6.xbar_random_zero_delays.915775558 |
| Short name | T1621 |
| Test name | |
| Test status | |
| Simulation time | 63732124 ps |
| CPU time | 8.99 seconds |
| Started | Jun 29 08:12:37 PM PDT 24 |
| Finished | Jun 29 08:12:46 PM PDT 24 |
| Peak memory | 574256 kb |
| Host | smart-7ec9b67f-76d0-4d78-a771-2972af6b3720 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=915775558 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.xbar_random_zero_delay s.915775558 |
| Directory | /workspace/6.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/6.xbar_same_source.966381233 |
| Short name | T2266 |
| Test name | |
| Test status | |
| Simulation time | 167252616 ps |
| CPU time | 15.58 seconds |
| Started | Jun 29 08:12:29 PM PDT 24 |
| Finished | Jun 29 08:12:45 PM PDT 24 |
| Peak memory | 574240 kb |
| Host | smart-f19e58f5-9608-4ce1-b5e2-057faf637946 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=966381233 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.xbar_same_source.966381233 |
| Directory | /workspace/6.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/6.xbar_smoke.865397529 |
| Short name | T1469 |
| Test name | |
| Test status | |
| Simulation time | 226361406 ps |
| CPU time | 9.53 seconds |
| Started | Jun 29 08:12:16 PM PDT 24 |
| Finished | Jun 29 08:12:26 PM PDT 24 |
| Peak memory | 574280 kb |
| Host | smart-964332e4-5597-44fe-8a8b-629422a5650a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=865397529 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.xbar_smoke.865397529 |
| Directory | /workspace/6.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/6.xbar_smoke_large_delays.1888232317 |
| Short name | T1434 |
| Test name | |
| Test status | |
| Simulation time | 7534678018 ps |
| CPU time | 79.22 seconds |
| Started | Jun 29 08:12:21 PM PDT 24 |
| Finished | Jun 29 08:13:40 PM PDT 24 |
| Peak memory | 574336 kb |
| Host | smart-c32d7a33-0c9e-4acb-b478-f20363ae7a53 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1888232317 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.xbar_smoke_large_delays.1888232317 |
| Directory | /workspace/6.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/6.xbar_smoke_slow_rsp.1053123852 |
| Short name | T1345 |
| Test name | |
| Test status | |
| Simulation time | 3267950379 ps |
| CPU time | 62.8 seconds |
| Started | Jun 29 08:12:23 PM PDT 24 |
| Finished | Jun 29 08:13:27 PM PDT 24 |
| Peak memory | 574120 kb |
| Host | smart-ad4f8fdd-8492-4c2a-9ea5-2da22678ebb2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1053123852 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.xbar_smoke_slow_rsp.1053123852 |
| Directory | /workspace/6.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/6.xbar_smoke_zero_delays.2450807125 |
| Short name | T574 |
| Test name | |
| Test status | |
| Simulation time | 47890621 ps |
| CPU time | 6.86 seconds |
| Started | Jun 29 08:12:21 PM PDT 24 |
| Finished | Jun 29 08:12:28 PM PDT 24 |
| Peak memory | 574208 kb |
| Host | smart-115272e2-9974-4c10-ad35-110edf610251 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2450807125 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.xbar_smoke_zero_delays .2450807125 |
| Directory | /workspace/6.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/6.xbar_stress_all.2151466936 |
| Short name | T563 |
| Test name | |
| Test status | |
| Simulation time | 1724591776 ps |
| CPU time | 172.56 seconds |
| Started | Jun 29 08:12:36 PM PDT 24 |
| Finished | Jun 29 08:15:29 PM PDT 24 |
| Peak memory | 574336 kb |
| Host | smart-157990f6-eadf-41bf-9b2a-8c29dcbcff85 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2151466936 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.xbar_stress_all.2151466936 |
| Directory | /workspace/6.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/6.xbar_stress_all_with_error.1358621954 |
| Short name | T1611 |
| Test name | |
| Test status | |
| Simulation time | 4979013794 ps |
| CPU time | 212.04 seconds |
| Started | Jun 29 08:12:44 PM PDT 24 |
| Finished | Jun 29 08:16:16 PM PDT 24 |
| Peak memory | 574396 kb |
| Host | smart-360b376c-80cf-4c0c-b2a1-104a047273f9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1358621954 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.xbar_stress_all_with_error.1358621954 |
| Directory | /workspace/6.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/6.xbar_stress_all_with_reset_error.1363250866 |
| Short name | T2562 |
| Test name | |
| Test status | |
| Simulation time | 15153190243 ps |
| CPU time | 826.96 seconds |
| Started | Jun 29 08:12:41 PM PDT 24 |
| Finished | Jun 29 08:26:29 PM PDT 24 |
| Peak memory | 575484 kb |
| Host | smart-0a3e6c48-429c-4f17-9b08-4c8f62457f7e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1363250866 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.xbar_stress_all _with_reset_error.1363250866 |
| Directory | /workspace/6.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/6.xbar_unmapped_addr.1760213075 |
| Short name | T2147 |
| Test name | |
| Test status | |
| Simulation time | 1223961234 ps |
| CPU time | 60.52 seconds |
| Started | Jun 29 08:12:30 PM PDT 24 |
| Finished | Jun 29 08:13:31 PM PDT 24 |
| Peak memory | 575368 kb |
| Host | smart-d4a1763e-0e2c-4bb3-8c05-d989492ff3a6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1760213075 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.xbar_unmapped_addr.1760213075 |
| Directory | /workspace/6.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/60.xbar_access_same_device.695210582 |
| Short name | T778 |
| Test name | |
| Test status | |
| Simulation time | 2347581930 ps |
| CPU time | 100.8 seconds |
| Started | Jun 29 08:25:05 PM PDT 24 |
| Finished | Jun 29 08:26:46 PM PDT 24 |
| Peak memory | 574300 kb |
| Host | smart-32722d1c-a013-4d65-8972-6c31e1cd482e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=695210582 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 60.xbar_access_same_device. 695210582 |
| Directory | /workspace/60.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/60.xbar_error_and_unmapped_addr.1274955100 |
| Short name | T227 |
| Test name | |
| Test status | |
| Simulation time | 139677911 ps |
| CPU time | 15.19 seconds |
| Started | Jun 29 08:25:02 PM PDT 24 |
| Finished | Jun 29 08:25:18 PM PDT 24 |
| Peak memory | 573944 kb |
| Host | smart-280b468c-522b-4c00-a8e3-54695ff19a5c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1274955100 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 60.xbar_error_and_unmapped_add r.1274955100 |
| Directory | /workspace/60.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/60.xbar_error_random.1822543236 |
| Short name | T2332 |
| Test name | |
| Test status | |
| Simulation time | 1242283134 ps |
| CPU time | 43.06 seconds |
| Started | Jun 29 08:25:02 PM PDT 24 |
| Finished | Jun 29 08:25:45 PM PDT 24 |
| Peak memory | 573952 kb |
| Host | smart-e3f55bdc-5c53-4c5f-bb02-5df3ac82a36b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1822543236 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 60.xbar_error_random.1822543236 |
| Directory | /workspace/60.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/60.xbar_random.3494684493 |
| Short name | T2511 |
| Test name | |
| Test status | |
| Simulation time | 142796798 ps |
| CPU time | 16.9 seconds |
| Started | Jun 29 08:25:03 PM PDT 24 |
| Finished | Jun 29 08:25:21 PM PDT 24 |
| Peak memory | 574240 kb |
| Host | smart-db48b200-5c72-48ee-8f29-c480b6606043 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3494684493 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 60.xbar_random.3494684493 |
| Directory | /workspace/60.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/60.xbar_random_large_delays.277258799 |
| Short name | T630 |
| Test name | |
| Test status | |
| Simulation time | 95793396226 ps |
| CPU time | 1012.24 seconds |
| Started | Jun 29 08:25:10 PM PDT 24 |
| Finished | Jun 29 08:42:02 PM PDT 24 |
| Peak memory | 575352 kb |
| Host | smart-e4e234d9-9f7c-4339-9fa9-113f42fd0cb7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=277258799 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 60.xbar_random_large_delays.277258799 |
| Directory | /workspace/60.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/60.xbar_random_slow_rsp.1246372325 |
| Short name | T2248 |
| Test name | |
| Test status | |
| Simulation time | 25384748773 ps |
| CPU time | 478.79 seconds |
| Started | Jun 29 08:25:05 PM PDT 24 |
| Finished | Jun 29 08:33:04 PM PDT 24 |
| Peak memory | 574328 kb |
| Host | smart-efccfbb4-61ab-4a5f-bd67-36faad71fe97 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1246372325 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 60.xbar_random_slow_rsp.1246372325 |
| Directory | /workspace/60.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/60.xbar_random_zero_delays.2943233293 |
| Short name | T534 |
| Test name | |
| Test status | |
| Simulation time | 568305462 ps |
| CPU time | 53.59 seconds |
| Started | Jun 29 08:25:03 PM PDT 24 |
| Finished | Jun 29 08:25:57 PM PDT 24 |
| Peak memory | 575248 kb |
| Host | smart-b5652bc6-3220-46eb-b59e-3f1476e1fb5e |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2943233293 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 60.xbar_random_zero_del ays.2943233293 |
| Directory | /workspace/60.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/60.xbar_same_source.61373046 |
| Short name | T1580 |
| Test name | |
| Test status | |
| Simulation time | 459965839 ps |
| CPU time | 34.82 seconds |
| Started | Jun 29 08:25:02 PM PDT 24 |
| Finished | Jun 29 08:25:37 PM PDT 24 |
| Peak memory | 575292 kb |
| Host | smart-899ae806-1cf1-40b2-88a2-b5d04e64f1fa |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61373046 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 60.xbar_same_source.61373046 |
| Directory | /workspace/60.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/60.xbar_smoke.233197511 |
| Short name | T2871 |
| Test name | |
| Test status | |
| Simulation time | 52037349 ps |
| CPU time | 7.6 seconds |
| Started | Jun 29 08:24:54 PM PDT 24 |
| Finished | Jun 29 08:25:03 PM PDT 24 |
| Peak memory | 565996 kb |
| Host | smart-1725b5c3-4b61-438d-a50a-f7adec9a241b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=233197511 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 60.xbar_smoke.233197511 |
| Directory | /workspace/60.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/60.xbar_smoke_large_delays.2845526045 |
| Short name | T2829 |
| Test name | |
| Test status | |
| Simulation time | 8464076462 ps |
| CPU time | 92.3 seconds |
| Started | Jun 29 08:24:57 PM PDT 24 |
| Finished | Jun 29 08:26:30 PM PDT 24 |
| Peak memory | 566088 kb |
| Host | smart-3a16a5dc-6950-4d9e-b224-925f9dba81de |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2845526045 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 60.xbar_smoke_large_delays.2845526045 |
| Directory | /workspace/60.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/60.xbar_smoke_slow_rsp.3752745066 |
| Short name | T2236 |
| Test name | |
| Test status | |
| Simulation time | 5344279796 ps |
| CPU time | 93.78 seconds |
| Started | Jun 29 08:25:01 PM PDT 24 |
| Finished | Jun 29 08:26:36 PM PDT 24 |
| Peak memory | 574324 kb |
| Host | smart-21b83432-c93d-4bbe-8769-b651733881d5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3752745066 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 60.xbar_smoke_slow_rsp.3752745066 |
| Directory | /workspace/60.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/60.xbar_smoke_zero_delays.1822252356 |
| Short name | T2424 |
| Test name | |
| Test status | |
| Simulation time | 44259997 ps |
| CPU time | 6.91 seconds |
| Started | Jun 29 08:24:54 PM PDT 24 |
| Finished | Jun 29 08:25:02 PM PDT 24 |
| Peak memory | 574232 kb |
| Host | smart-1fb7fd94-8708-472d-a0f7-ee8209ad994a |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1822252356 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 60.xbar_smoke_zero_delay s.1822252356 |
| Directory | /workspace/60.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/60.xbar_stress_all.2787749143 |
| Short name | T1423 |
| Test name | |
| Test status | |
| Simulation time | 3022041183 ps |
| CPU time | 265.95 seconds |
| Started | Jun 29 08:25:10 PM PDT 24 |
| Finished | Jun 29 08:29:36 PM PDT 24 |
| Peak memory | 574428 kb |
| Host | smart-527f791d-b797-4a74-b005-b59a21c73cac |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2787749143 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 60.xbar_stress_all.2787749143 |
| Directory | /workspace/60.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/60.xbar_stress_all_with_error.174875292 |
| Short name | T2223 |
| Test name | |
| Test status | |
| Simulation time | 1795627926 ps |
| CPU time | 185.08 seconds |
| Started | Jun 29 08:25:13 PM PDT 24 |
| Finished | Jun 29 08:28:19 PM PDT 24 |
| Peak memory | 574544 kb |
| Host | smart-c3d71a6a-b95b-4161-a965-5aaf1e6e399f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=174875292 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 60.xbar_stress_all_with_error.174875292 |
| Directory | /workspace/60.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/60.xbar_stress_all_with_rand_reset.1210878080 |
| Short name | T822 |
| Test name | |
| Test status | |
| Simulation time | 3484117836 ps |
| CPU time | 306.14 seconds |
| Started | Jun 29 08:25:04 PM PDT 24 |
| Finished | Jun 29 08:30:10 PM PDT 24 |
| Peak memory | 575504 kb |
| Host | smart-478255a6-cbc6-44d2-a2ec-d228519d3198 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1210878080 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 60.xbar_stress_all _with_rand_reset.1210878080 |
| Directory | /workspace/60.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/60.xbar_stress_all_with_reset_error.2807864365 |
| Short name | T1739 |
| Test name | |
| Test status | |
| Simulation time | 2211884721 ps |
| CPU time | 347.6 seconds |
| Started | Jun 29 08:25:14 PM PDT 24 |
| Finished | Jun 29 08:31:02 PM PDT 24 |
| Peak memory | 574708 kb |
| Host | smart-54f26f47-f0a4-4e76-b799-aff2147c7654 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2807864365 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 60.xbar_stress_al l_with_reset_error.2807864365 |
| Directory | /workspace/60.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/60.xbar_unmapped_addr.4230040367 |
| Short name | T2351 |
| Test name | |
| Test status | |
| Simulation time | 307180291 ps |
| CPU time | 41.15 seconds |
| Started | Jun 29 08:25:04 PM PDT 24 |
| Finished | Jun 29 08:25:45 PM PDT 24 |
| Peak memory | 575368 kb |
| Host | smart-1fd2c4eb-1519-487c-85b8-9f6545cbc6f5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4230040367 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 60.xbar_unmapped_addr.4230040367 |
| Directory | /workspace/60.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/61.xbar_access_same_device.480731348 |
| Short name | T2390 |
| Test name | |
| Test status | |
| Simulation time | 2493006021 ps |
| CPU time | 109.15 seconds |
| Started | Jun 29 08:25:10 PM PDT 24 |
| Finished | Jun 29 08:26:59 PM PDT 24 |
| Peak memory | 575384 kb |
| Host | smart-3e1b9ae8-619e-4a81-aee5-39c556e39d75 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=480731348 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 61.xbar_access_same_device. 480731348 |
| Directory | /workspace/61.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/61.xbar_access_same_device_slow_rsp.499902180 |
| Short name | T800 |
| Test name | |
| Test status | |
| Simulation time | 112583680408 ps |
| CPU time | 1980.48 seconds |
| Started | Jun 29 08:25:14 PM PDT 24 |
| Finished | Jun 29 08:58:15 PM PDT 24 |
| Peak memory | 574468 kb |
| Host | smart-ac9fc988-c535-4d5c-9660-cc2955a086cc |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=499902180 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 61.xbar_access_same_d evice_slow_rsp.499902180 |
| Directory | /workspace/61.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/61.xbar_error_and_unmapped_addr.325687496 |
| Short name | T2616 |
| Test name | |
| Test status | |
| Simulation time | 1392266639 ps |
| CPU time | 65.68 seconds |
| Started | Jun 29 08:25:11 PM PDT 24 |
| Finished | Jun 29 08:26:17 PM PDT 24 |
| Peak memory | 574508 kb |
| Host | smart-19d92b80-cb29-4f76-85d8-a72f0192a061 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=325687496 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 61.xbar_error_and_unmapped_addr .325687496 |
| Directory | /workspace/61.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/61.xbar_error_random.762548166 |
| Short name | T2580 |
| Test name | |
| Test status | |
| Simulation time | 1866853801 ps |
| CPU time | 55.84 seconds |
| Started | Jun 29 08:25:09 PM PDT 24 |
| Finished | Jun 29 08:26:05 PM PDT 24 |
| Peak memory | 574132 kb |
| Host | smart-eea493b2-9251-4f85-a219-55310d85688a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=762548166 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 61.xbar_error_random.762548166 |
| Directory | /workspace/61.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/61.xbar_random.294064491 |
| Short name | T2361 |
| Test name | |
| Test status | |
| Simulation time | 124929785 ps |
| CPU time | 15.4 seconds |
| Started | Jun 29 08:25:11 PM PDT 24 |
| Finished | Jun 29 08:25:26 PM PDT 24 |
| Peak memory | 574232 kb |
| Host | smart-d6ef43fa-bb34-479a-81d9-2290524df177 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=294064491 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 61.xbar_random.294064491 |
| Directory | /workspace/61.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/61.xbar_random_large_delays.2803304173 |
| Short name | T1509 |
| Test name | |
| Test status | |
| Simulation time | 93760543779 ps |
| CPU time | 1049.28 seconds |
| Started | Jun 29 08:25:10 PM PDT 24 |
| Finished | Jun 29 08:42:39 PM PDT 24 |
| Peak memory | 575432 kb |
| Host | smart-465c62a4-aff5-4c05-a659-b00bc8fcac96 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2803304173 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 61.xbar_random_large_delays.2803304173 |
| Directory | /workspace/61.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/61.xbar_random_slow_rsp.3809100940 |
| Short name | T2443 |
| Test name | |
| Test status | |
| Simulation time | 46843976599 ps |
| CPU time | 790.52 seconds |
| Started | Jun 29 08:25:10 PM PDT 24 |
| Finished | Jun 29 08:38:21 PM PDT 24 |
| Peak memory | 575372 kb |
| Host | smart-c18af188-762f-4c10-ab20-fd93edd45712 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3809100940 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 61.xbar_random_slow_rsp.3809100940 |
| Directory | /workspace/61.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/61.xbar_random_zero_delays.4163621154 |
| Short name | T2512 |
| Test name | |
| Test status | |
| Simulation time | 128519812 ps |
| CPU time | 14.39 seconds |
| Started | Jun 29 08:25:13 PM PDT 24 |
| Finished | Jun 29 08:25:27 PM PDT 24 |
| Peak memory | 575312 kb |
| Host | smart-6d4a2468-938e-4689-bfd3-0b22d993b4e8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4163621154 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 61.xbar_random_zero_del ays.4163621154 |
| Directory | /workspace/61.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/61.xbar_same_source.1012032021 |
| Short name | T589 |
| Test name | |
| Test status | |
| Simulation time | 340239062 ps |
| CPU time | 29.58 seconds |
| Started | Jun 29 08:25:13 PM PDT 24 |
| Finished | Jun 29 08:25:43 PM PDT 24 |
| Peak memory | 574228 kb |
| Host | smart-71dc2e7e-8c91-464b-a921-a2d23b5645d0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1012032021 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 61.xbar_same_source.1012032021 |
| Directory | /workspace/61.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/61.xbar_smoke.3569552569 |
| Short name | T2659 |
| Test name | |
| Test status | |
| Simulation time | 216657930 ps |
| CPU time | 9.86 seconds |
| Started | Jun 29 08:25:11 PM PDT 24 |
| Finished | Jun 29 08:25:21 PM PDT 24 |
| Peak memory | 574248 kb |
| Host | smart-aad72341-6ae3-479d-abef-0371ec9ae711 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3569552569 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 61.xbar_smoke.3569552569 |
| Directory | /workspace/61.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/61.xbar_smoke_large_delays.992596249 |
| Short name | T1417 |
| Test name | |
| Test status | |
| Simulation time | 9300218982 ps |
| CPU time | 98.26 seconds |
| Started | Jun 29 08:25:13 PM PDT 24 |
| Finished | Jun 29 08:26:52 PM PDT 24 |
| Peak memory | 574332 kb |
| Host | smart-c93dc7c1-d983-4409-ab3a-6208430d9afc |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=992596249 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 61.xbar_smoke_large_delays.992596249 |
| Directory | /workspace/61.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/61.xbar_smoke_slow_rsp.2901976199 |
| Short name | T2785 |
| Test name | |
| Test status | |
| Simulation time | 5433543630 ps |
| CPU time | 92.71 seconds |
| Started | Jun 29 08:25:14 PM PDT 24 |
| Finished | Jun 29 08:26:48 PM PDT 24 |
| Peak memory | 566088 kb |
| Host | smart-c149b12e-8bd8-460e-8526-901909965b55 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2901976199 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 61.xbar_smoke_slow_rsp.2901976199 |
| Directory | /workspace/61.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/61.xbar_smoke_zero_delays.582690657 |
| Short name | T2645 |
| Test name | |
| Test status | |
| Simulation time | 52096899 ps |
| CPU time | 7.31 seconds |
| Started | Jun 29 08:25:14 PM PDT 24 |
| Finished | Jun 29 08:25:22 PM PDT 24 |
| Peak memory | 574216 kb |
| Host | smart-b800a019-5c89-4573-9b96-9113cf671f76 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=582690657 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 61.xbar_smoke_zero_delays .582690657 |
| Directory | /workspace/61.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/61.xbar_stress_all.676005468 |
| Short name | T1825 |
| Test name | |
| Test status | |
| Simulation time | 8222966995 ps |
| CPU time | 358.08 seconds |
| Started | Jun 29 08:25:10 PM PDT 24 |
| Finished | Jun 29 08:31:08 PM PDT 24 |
| Peak memory | 575524 kb |
| Host | smart-1f01a7e5-4774-4809-8027-fae4819f9281 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=676005468 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 61.xbar_stress_all.676005468 |
| Directory | /workspace/61.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/61.xbar_stress_all_with_error.886585445 |
| Short name | T2410 |
| Test name | |
| Test status | |
| Simulation time | 2461615233 ps |
| CPU time | 99.87 seconds |
| Started | Jun 29 08:25:29 PM PDT 24 |
| Finished | Jun 29 08:27:09 PM PDT 24 |
| Peak memory | 574596 kb |
| Host | smart-5e44dbe8-280a-40c2-bd4e-b9fb920ed334 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=886585445 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 61.xbar_stress_all_with_error.886585445 |
| Directory | /workspace/61.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/61.xbar_stress_all_with_rand_reset.1704575224 |
| Short name | T1967 |
| Test name | |
| Test status | |
| Simulation time | 4389375936 ps |
| CPU time | 321.51 seconds |
| Started | Jun 29 08:25:18 PM PDT 24 |
| Finished | Jun 29 08:30:39 PM PDT 24 |
| Peak memory | 575504 kb |
| Host | smart-41001456-b48e-44bb-9f85-82c4b377fd30 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1704575224 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 61.xbar_stress_all _with_rand_reset.1704575224 |
| Directory | /workspace/61.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/61.xbar_stress_all_with_reset_error.3755167690 |
| Short name | T1591 |
| Test name | |
| Test status | |
| Simulation time | 5345358418 ps |
| CPU time | 331.89 seconds |
| Started | Jun 29 08:25:19 PM PDT 24 |
| Finished | Jun 29 08:30:51 PM PDT 24 |
| Peak memory | 574488 kb |
| Host | smart-be216bb3-20e1-411b-ba8a-fae7209616d0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3755167690 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 61.xbar_stress_al l_with_reset_error.3755167690 |
| Directory | /workspace/61.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/61.xbar_unmapped_addr.141604767 |
| Short name | T2295 |
| Test name | |
| Test status | |
| Simulation time | 1450076767 ps |
| CPU time | 66.8 seconds |
| Started | Jun 29 08:25:10 PM PDT 24 |
| Finished | Jun 29 08:26:18 PM PDT 24 |
| Peak memory | 575336 kb |
| Host | smart-e1801a7f-fe40-424e-9db0-8fa962433c2a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=141604767 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 61.xbar_unmapped_addr.141604767 |
| Directory | /workspace/61.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/62.xbar_access_same_device.576965369 |
| Short name | T2627 |
| Test name | |
| Test status | |
| Simulation time | 2400452793 ps |
| CPU time | 99.57 seconds |
| Started | Jun 29 08:25:19 PM PDT 24 |
| Finished | Jun 29 08:26:59 PM PDT 24 |
| Peak memory | 575388 kb |
| Host | smart-3c167ff7-0a0e-4b89-bc00-914fbd39fa65 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=576965369 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 62.xbar_access_same_device. 576965369 |
| Directory | /workspace/62.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/62.xbar_access_same_device_slow_rsp.2936517831 |
| Short name | T1992 |
| Test name | |
| Test status | |
| Simulation time | 28264622170 ps |
| CPU time | 490.85 seconds |
| Started | Jun 29 08:25:18 PM PDT 24 |
| Finished | Jun 29 08:33:30 PM PDT 24 |
| Peak memory | 575436 kb |
| Host | smart-9eb71a61-9994-4b06-bae3-339ccd123685 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2936517831 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 62.xbar_access_same_ device_slow_rsp.2936517831 |
| Directory | /workspace/62.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/62.xbar_error_and_unmapped_addr.831505433 |
| Short name | T2724 |
| Test name | |
| Test status | |
| Simulation time | 376763901 ps |
| CPU time | 20.8 seconds |
| Started | Jun 29 08:25:18 PM PDT 24 |
| Finished | Jun 29 08:25:39 PM PDT 24 |
| Peak memory | 573892 kb |
| Host | smart-c86b4278-8bbd-4e67-8a53-6f86172bcd35 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=831505433 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 62.xbar_error_and_unmapped_addr .831505433 |
| Directory | /workspace/62.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/62.xbar_error_random.4125507464 |
| Short name | T1339 |
| Test name | |
| Test status | |
| Simulation time | 84891297 ps |
| CPU time | 7.06 seconds |
| Started | Jun 29 08:25:20 PM PDT 24 |
| Finished | Jun 29 08:25:27 PM PDT 24 |
| Peak memory | 565996 kb |
| Host | smart-44e7eca4-9cc6-4ae9-bc50-76d7101a9764 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4125507464 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 62.xbar_error_random.4125507464 |
| Directory | /workspace/62.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/62.xbar_random.3124866755 |
| Short name | T2568 |
| Test name | |
| Test status | |
| Simulation time | 573040441 ps |
| CPU time | 22.98 seconds |
| Started | Jun 29 08:25:17 PM PDT 24 |
| Finished | Jun 29 08:25:40 PM PDT 24 |
| Peak memory | 575308 kb |
| Host | smart-2c7c55f3-a6b1-4527-a814-dad1bf02a163 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3124866755 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 62.xbar_random.3124866755 |
| Directory | /workspace/62.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/62.xbar_random_large_delays.122204549 |
| Short name | T1630 |
| Test name | |
| Test status | |
| Simulation time | 17075438256 ps |
| CPU time | 183.48 seconds |
| Started | Jun 29 08:25:28 PM PDT 24 |
| Finished | Jun 29 08:28:32 PM PDT 24 |
| Peak memory | 575352 kb |
| Host | smart-eceb3543-aa08-4615-bc9d-cb1119809ca4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=122204549 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 62.xbar_random_large_delays.122204549 |
| Directory | /workspace/62.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/62.xbar_random_slow_rsp.3718770553 |
| Short name | T1946 |
| Test name | |
| Test status | |
| Simulation time | 17808547248 ps |
| CPU time | 309.07 seconds |
| Started | Jun 29 08:25:20 PM PDT 24 |
| Finished | Jun 29 08:30:30 PM PDT 24 |
| Peak memory | 575372 kb |
| Host | smart-3ac6e096-9a01-4b53-ab32-3541db0a33b3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3718770553 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 62.xbar_random_slow_rsp.3718770553 |
| Directory | /workspace/62.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/62.xbar_random_zero_delays.1930780387 |
| Short name | T584 |
| Test name | |
| Test status | |
| Simulation time | 348343978 ps |
| CPU time | 33.73 seconds |
| Started | Jun 29 08:25:28 PM PDT 24 |
| Finished | Jun 29 08:26:02 PM PDT 24 |
| Peak memory | 575276 kb |
| Host | smart-49f0d263-81c3-4899-bcd0-0f267a4c3fd2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1930780387 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 62.xbar_random_zero_del ays.1930780387 |
| Directory | /workspace/62.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/62.xbar_same_source.1332111741 |
| Short name | T2004 |
| Test name | |
| Test status | |
| Simulation time | 78800596 ps |
| CPU time | 9.07 seconds |
| Started | Jun 29 08:25:28 PM PDT 24 |
| Finished | Jun 29 08:25:37 PM PDT 24 |
| Peak memory | 575272 kb |
| Host | smart-56b90793-f883-42e2-9be9-dc09d1e987c4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1332111741 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 62.xbar_same_source.1332111741 |
| Directory | /workspace/62.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/62.xbar_smoke.3866253321 |
| Short name | T1379 |
| Test name | |
| Test status | |
| Simulation time | 39077701 ps |
| CPU time | 6.23 seconds |
| Started | Jun 29 08:25:19 PM PDT 24 |
| Finished | Jun 29 08:25:26 PM PDT 24 |
| Peak memory | 566012 kb |
| Host | smart-559dcb28-2f58-489c-b0e2-71c48cd751c3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3866253321 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 62.xbar_smoke.3866253321 |
| Directory | /workspace/62.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/62.xbar_smoke_large_delays.4141051933 |
| Short name | T2712 |
| Test name | |
| Test status | |
| Simulation time | 9369285299 ps |
| CPU time | 107.71 seconds |
| Started | Jun 29 08:25:20 PM PDT 24 |
| Finished | Jun 29 08:27:08 PM PDT 24 |
| Peak memory | 566220 kb |
| Host | smart-845f30cd-14e8-4632-8104-078cab64a520 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4141051933 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 62.xbar_smoke_large_delays.4141051933 |
| Directory | /workspace/62.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/62.xbar_smoke_slow_rsp.4106694391 |
| Short name | T2011 |
| Test name | |
| Test status | |
| Simulation time | 4022360645 ps |
| CPU time | 70.51 seconds |
| Started | Jun 29 08:25:19 PM PDT 24 |
| Finished | Jun 29 08:26:30 PM PDT 24 |
| Peak memory | 574324 kb |
| Host | smart-79c9d287-c115-4acc-9057-50dd473a448c |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4106694391 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 62.xbar_smoke_slow_rsp.4106694391 |
| Directory | /workspace/62.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/62.xbar_smoke_zero_delays.1055430806 |
| Short name | T2182 |
| Test name | |
| Test status | |
| Simulation time | 37866350 ps |
| CPU time | 5.89 seconds |
| Started | Jun 29 08:25:19 PM PDT 24 |
| Finished | Jun 29 08:25:25 PM PDT 24 |
| Peak memory | 574244 kb |
| Host | smart-15ddd7f0-575a-41d7-9358-16e6ee8ace12 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1055430806 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 62.xbar_smoke_zero_delay s.1055430806 |
| Directory | /workspace/62.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/62.xbar_stress_all.1852360020 |
| Short name | T2599 |
| Test name | |
| Test status | |
| Simulation time | 4295391532 ps |
| CPU time | 407 seconds |
| Started | Jun 29 08:25:25 PM PDT 24 |
| Finished | Jun 29 08:32:13 PM PDT 24 |
| Peak memory | 574460 kb |
| Host | smart-c0b5f9b1-500f-42b3-9ab1-054f05fe950a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1852360020 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 62.xbar_stress_all.1852360020 |
| Directory | /workspace/62.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/62.xbar_stress_all_with_error.4102565918 |
| Short name | T1871 |
| Test name | |
| Test status | |
| Simulation time | 1213878782 ps |
| CPU time | 41.91 seconds |
| Started | Jun 29 08:25:29 PM PDT 24 |
| Finished | Jun 29 08:26:11 PM PDT 24 |
| Peak memory | 574512 kb |
| Host | smart-b32c9fa7-5473-4116-93b7-af202a7aaf13 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4102565918 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 62.xbar_stress_all_with_error.4102565918 |
| Directory | /workspace/62.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/62.xbar_stress_all_with_rand_reset.1404779219 |
| Short name | T2399 |
| Test name | |
| Test status | |
| Simulation time | 457167321 ps |
| CPU time | 119.64 seconds |
| Started | Jun 29 08:25:27 PM PDT 24 |
| Finished | Jun 29 08:27:27 PM PDT 24 |
| Peak memory | 575452 kb |
| Host | smart-081451ed-73a0-4f9b-9cd3-969f7f264d46 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1404779219 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 62.xbar_stress_all _with_rand_reset.1404779219 |
| Directory | /workspace/62.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/62.xbar_stress_all_with_reset_error.1884643791 |
| Short name | T1743 |
| Test name | |
| Test status | |
| Simulation time | 210189588 ps |
| CPU time | 21.93 seconds |
| Started | Jun 29 08:25:26 PM PDT 24 |
| Finished | Jun 29 08:25:49 PM PDT 24 |
| Peak memory | 574320 kb |
| Host | smart-349e67bd-06a4-410d-b186-d3a6a20dd60f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1884643791 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 62.xbar_stress_al l_with_reset_error.1884643791 |
| Directory | /workspace/62.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/62.xbar_unmapped_addr.3650483091 |
| Short name | T1994 |
| Test name | |
| Test status | |
| Simulation time | 470970396 ps |
| CPU time | 22.4 seconds |
| Started | Jun 29 08:25:20 PM PDT 24 |
| Finished | Jun 29 08:25:42 PM PDT 24 |
| Peak memory | 575376 kb |
| Host | smart-3da9b082-e105-4196-adc8-37e7bf36d8d2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3650483091 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 62.xbar_unmapped_addr.3650483091 |
| Directory | /workspace/62.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/63.xbar_access_same_device.262223026 |
| Short name | T1779 |
| Test name | |
| Test status | |
| Simulation time | 1731016624 ps |
| CPU time | 76.91 seconds |
| Started | Jun 29 08:25:36 PM PDT 24 |
| Finished | Jun 29 08:26:53 PM PDT 24 |
| Peak memory | 575300 kb |
| Host | smart-16222f43-a6ae-4856-9092-e47c169509c1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=262223026 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 63.xbar_access_same_device. 262223026 |
| Directory | /workspace/63.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/63.xbar_error_and_unmapped_addr.740906751 |
| Short name | T2808 |
| Test name | |
| Test status | |
| Simulation time | 1455331487 ps |
| CPU time | 63.48 seconds |
| Started | Jun 29 08:25:27 PM PDT 24 |
| Finished | Jun 29 08:26:31 PM PDT 24 |
| Peak memory | 574512 kb |
| Host | smart-22e52432-434f-46bd-a924-32341bc1f22b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=740906751 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 63.xbar_error_and_unmapped_addr .740906751 |
| Directory | /workspace/63.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/63.xbar_error_random.3734763332 |
| Short name | T2484 |
| Test name | |
| Test status | |
| Simulation time | 1419056636 ps |
| CPU time | 56.94 seconds |
| Started | Jun 29 08:25:27 PM PDT 24 |
| Finished | Jun 29 08:26:25 PM PDT 24 |
| Peak memory | 574472 kb |
| Host | smart-2fee0f66-559b-4c7b-9925-6499a131378c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3734763332 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 63.xbar_error_random.3734763332 |
| Directory | /workspace/63.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/63.xbar_random.121372827 |
| Short name | T2695 |
| Test name | |
| Test status | |
| Simulation time | 2280966595 ps |
| CPU time | 86.05 seconds |
| Started | Jun 29 08:25:30 PM PDT 24 |
| Finished | Jun 29 08:26:56 PM PDT 24 |
| Peak memory | 575364 kb |
| Host | smart-5d07bf4b-fb16-4a73-8629-704ce258a6ac |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=121372827 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 63.xbar_random.121372827 |
| Directory | /workspace/63.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/63.xbar_random_large_delays.2395106985 |
| Short name | T1938 |
| Test name | |
| Test status | |
| Simulation time | 10374649604 ps |
| CPU time | 111.23 seconds |
| Started | Jun 29 08:25:35 PM PDT 24 |
| Finished | Jun 29 08:27:27 PM PDT 24 |
| Peak memory | 574404 kb |
| Host | smart-a0650773-1c94-4160-b9ea-bbf3e0982c30 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2395106985 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 63.xbar_random_large_delays.2395106985 |
| Directory | /workspace/63.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/63.xbar_random_slow_rsp.1535336728 |
| Short name | T1832 |
| Test name | |
| Test status | |
| Simulation time | 19227511957 ps |
| CPU time | 331.48 seconds |
| Started | Jun 29 08:25:37 PM PDT 24 |
| Finished | Jun 29 08:31:09 PM PDT 24 |
| Peak memory | 575396 kb |
| Host | smart-35871eea-931e-4ac8-a22d-ba3c8490d356 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1535336728 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 63.xbar_random_slow_rsp.1535336728 |
| Directory | /workspace/63.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/63.xbar_random_zero_delays.184323023 |
| Short name | T2329 |
| Test name | |
| Test status | |
| Simulation time | 402623743 ps |
| CPU time | 41 seconds |
| Started | Jun 29 08:25:27 PM PDT 24 |
| Finished | Jun 29 08:26:08 PM PDT 24 |
| Peak memory | 574236 kb |
| Host | smart-12c9dd25-8b8b-45d1-a634-39e33acbdc1b |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=184323023 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 63.xbar_random_zero_dela ys.184323023 |
| Directory | /workspace/63.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/63.xbar_same_source.2906511533 |
| Short name | T1548 |
| Test name | |
| Test status | |
| Simulation time | 1403673585 ps |
| CPU time | 49.61 seconds |
| Started | Jun 29 08:25:28 PM PDT 24 |
| Finished | Jun 29 08:26:18 PM PDT 24 |
| Peak memory | 575300 kb |
| Host | smart-2062e298-3265-4d98-9d72-243336967478 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2906511533 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 63.xbar_same_source.2906511533 |
| Directory | /workspace/63.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/63.xbar_smoke.708872184 |
| Short name | T1711 |
| Test name | |
| Test status | |
| Simulation time | 47413570 ps |
| CPU time | 6.53 seconds |
| Started | Jun 29 08:25:37 PM PDT 24 |
| Finished | Jun 29 08:25:44 PM PDT 24 |
| Peak memory | 574252 kb |
| Host | smart-f80e7060-7c7c-41cc-8669-7250880f8bf9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=708872184 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 63.xbar_smoke.708872184 |
| Directory | /workspace/63.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/63.xbar_smoke_large_delays.2217640895 |
| Short name | T2500 |
| Test name | |
| Test status | |
| Simulation time | 8492046271 ps |
| CPU time | 95.56 seconds |
| Started | Jun 29 08:25:27 PM PDT 24 |
| Finished | Jun 29 08:27:02 PM PDT 24 |
| Peak memory | 574312 kb |
| Host | smart-1764d491-6252-4a79-9ce3-e57202a2af08 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2217640895 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 63.xbar_smoke_large_delays.2217640895 |
| Directory | /workspace/63.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/63.xbar_smoke_slow_rsp.2862108981 |
| Short name | T2307 |
| Test name | |
| Test status | |
| Simulation time | 5352294480 ps |
| CPU time | 99.27 seconds |
| Started | Jun 29 08:25:27 PM PDT 24 |
| Finished | Jun 29 08:27:07 PM PDT 24 |
| Peak memory | 574312 kb |
| Host | smart-b7340a11-71c8-46e7-bf19-2fa1ee44a36e |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2862108981 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 63.xbar_smoke_slow_rsp.2862108981 |
| Directory | /workspace/63.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/63.xbar_smoke_zero_delays.2312720278 |
| Short name | T1834 |
| Test name | |
| Test status | |
| Simulation time | 46594716 ps |
| CPU time | 6.34 seconds |
| Started | Jun 29 08:25:27 PM PDT 24 |
| Finished | Jun 29 08:25:34 PM PDT 24 |
| Peak memory | 574244 kb |
| Host | smart-c039bf3d-a8ff-43c1-80d4-4618b2da736e |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2312720278 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 63.xbar_smoke_zero_delay s.2312720278 |
| Directory | /workspace/63.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/63.xbar_stress_all.3619601540 |
| Short name | T558 |
| Test name | |
| Test status | |
| Simulation time | 4435143763 ps |
| CPU time | 192.05 seconds |
| Started | Jun 29 08:25:36 PM PDT 24 |
| Finished | Jun 29 08:28:48 PM PDT 24 |
| Peak memory | 574420 kb |
| Host | smart-0f16151d-60d6-4b99-879d-629d28d022fc |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3619601540 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 63.xbar_stress_all.3619601540 |
| Directory | /workspace/63.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/63.xbar_stress_all_with_error.2596529847 |
| Short name | T2336 |
| Test name | |
| Test status | |
| Simulation time | 663161326 ps |
| CPU time | 57.03 seconds |
| Started | Jun 29 08:25:32 PM PDT 24 |
| Finished | Jun 29 08:26:30 PM PDT 24 |
| Peak memory | 574544 kb |
| Host | smart-3e0cc39b-4fb5-4075-9efc-505b9f3033df |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2596529847 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 63.xbar_stress_all_with_error.2596529847 |
| Directory | /workspace/63.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/63.xbar_stress_all_with_rand_reset.1106539123 |
| Short name | T2456 |
| Test name | |
| Test status | |
| Simulation time | 150799456 ps |
| CPU time | 49.43 seconds |
| Started | Jun 29 08:25:37 PM PDT 24 |
| Finished | Jun 29 08:26:27 PM PDT 24 |
| Peak memory | 575436 kb |
| Host | smart-392da785-5965-4888-849f-f79da6c8ba57 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1106539123 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 63.xbar_stress_all _with_rand_reset.1106539123 |
| Directory | /workspace/63.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/63.xbar_stress_all_with_reset_error.1124389495 |
| Short name | T2680 |
| Test name | |
| Test status | |
| Simulation time | 17514481 ps |
| CPU time | 15.17 seconds |
| Started | Jun 29 08:25:27 PM PDT 24 |
| Finished | Jun 29 08:25:42 PM PDT 24 |
| Peak memory | 574348 kb |
| Host | smart-97327141-f3e4-4f23-a3f9-a7cbaffb6504 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1124389495 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 63.xbar_stress_al l_with_reset_error.1124389495 |
| Directory | /workspace/63.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/63.xbar_unmapped_addr.2777670419 |
| Short name | T1462 |
| Test name | |
| Test status | |
| Simulation time | 284110318 ps |
| CPU time | 14.74 seconds |
| Started | Jun 29 08:25:32 PM PDT 24 |
| Finished | Jun 29 08:25:47 PM PDT 24 |
| Peak memory | 575328 kb |
| Host | smart-7b1a11b2-f742-41a8-8988-695352d4f0bf |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2777670419 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 63.xbar_unmapped_addr.2777670419 |
| Directory | /workspace/63.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/64.xbar_access_same_device.1730721666 |
| Short name | T2310 |
| Test name | |
| Test status | |
| Simulation time | 157027171 ps |
| CPU time | 12.37 seconds |
| Started | Jun 29 08:25:48 PM PDT 24 |
| Finished | Jun 29 08:26:01 PM PDT 24 |
| Peak memory | 574212 kb |
| Host | smart-97a582e4-56f9-4ed5-8951-b436a0f14f35 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1730721666 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 64.xbar_access_same_device .1730721666 |
| Directory | /workspace/64.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/64.xbar_access_same_device_slow_rsp.983850672 |
| Short name | T787 |
| Test name | |
| Test status | |
| Simulation time | 129288591558 ps |
| CPU time | 2233.68 seconds |
| Started | Jun 29 08:25:35 PM PDT 24 |
| Finished | Jun 29 09:02:49 PM PDT 24 |
| Peak memory | 575504 kb |
| Host | smart-e7613986-0207-49d0-a5c0-3ca07bbbcede |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=983850672 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 64.xbar_access_same_d evice_slow_rsp.983850672 |
| Directory | /workspace/64.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/64.xbar_error_and_unmapped_addr.1991035458 |
| Short name | T1615 |
| Test name | |
| Test status | |
| Simulation time | 54412220 ps |
| CPU time | 6.25 seconds |
| Started | Jun 29 08:25:46 PM PDT 24 |
| Finished | Jun 29 08:25:53 PM PDT 24 |
| Peak memory | 565696 kb |
| Host | smart-bd89b2f0-2bc3-4713-ba3e-a5504d6278f7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1991035458 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 64.xbar_error_and_unmapped_add r.1991035458 |
| Directory | /workspace/64.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/64.xbar_error_random.2397932059 |
| Short name | T1488 |
| Test name | |
| Test status | |
| Simulation time | 938145345 ps |
| CPU time | 32.82 seconds |
| Started | Jun 29 08:25:45 PM PDT 24 |
| Finished | Jun 29 08:26:19 PM PDT 24 |
| Peak memory | 573880 kb |
| Host | smart-9b55a320-cabe-4cec-982b-9b421e67ff16 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2397932059 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 64.xbar_error_random.2397932059 |
| Directory | /workspace/64.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/64.xbar_random.2344409907 |
| Short name | T2847 |
| Test name | |
| Test status | |
| Simulation time | 909338642 ps |
| CPU time | 30.29 seconds |
| Started | Jun 29 08:25:49 PM PDT 24 |
| Finished | Jun 29 08:26:20 PM PDT 24 |
| Peak memory | 575304 kb |
| Host | smart-441a2582-bd3b-422d-93c4-c80feffd769e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2344409907 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 64.xbar_random.2344409907 |
| Directory | /workspace/64.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/64.xbar_random_large_delays.3314332662 |
| Short name | T2688 |
| Test name | |
| Test status | |
| Simulation time | 104876213108 ps |
| CPU time | 1139.66 seconds |
| Started | Jun 29 08:25:35 PM PDT 24 |
| Finished | Jun 29 08:44:35 PM PDT 24 |
| Peak memory | 575368 kb |
| Host | smart-3c054521-2368-4907-8fb1-8557b36e3a2b |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3314332662 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 64.xbar_random_large_delays.3314332662 |
| Directory | /workspace/64.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/64.xbar_random_slow_rsp.2611025183 |
| Short name | T1737 |
| Test name | |
| Test status | |
| Simulation time | 51813664379 ps |
| CPU time | 833.78 seconds |
| Started | Jun 29 08:25:49 PM PDT 24 |
| Finished | Jun 29 08:39:43 PM PDT 24 |
| Peak memory | 575400 kb |
| Host | smart-27b95657-c142-42ad-b91c-b9df2c9d931b |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2611025183 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 64.xbar_random_slow_rsp.2611025183 |
| Directory | /workspace/64.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/64.xbar_random_zero_delays.1083251577 |
| Short name | T2315 |
| Test name | |
| Test status | |
| Simulation time | 330050186 ps |
| CPU time | 26.88 seconds |
| Started | Jun 29 08:25:49 PM PDT 24 |
| Finished | Jun 29 08:26:16 PM PDT 24 |
| Peak memory | 574240 kb |
| Host | smart-cd484620-e762-4910-a295-47be5f492f89 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1083251577 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 64.xbar_random_zero_del ays.1083251577 |
| Directory | /workspace/64.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/64.xbar_same_source.2612854298 |
| Short name | T2218 |
| Test name | |
| Test status | |
| Simulation time | 312644811 ps |
| CPU time | 26.3 seconds |
| Started | Jun 29 08:25:44 PM PDT 24 |
| Finished | Jun 29 08:26:11 PM PDT 24 |
| Peak memory | 575252 kb |
| Host | smart-a6cde48e-0640-4339-a845-1f889d1644ac |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2612854298 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 64.xbar_same_source.2612854298 |
| Directory | /workspace/64.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/64.xbar_smoke.3124765978 |
| Short name | T1448 |
| Test name | |
| Test status | |
| Simulation time | 228312916 ps |
| CPU time | 10.97 seconds |
| Started | Jun 29 08:25:34 PM PDT 24 |
| Finished | Jun 29 08:25:45 PM PDT 24 |
| Peak memory | 574196 kb |
| Host | smart-95480196-a043-43e7-9bb4-c9429759504a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3124765978 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 64.xbar_smoke.3124765978 |
| Directory | /workspace/64.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/64.xbar_smoke_large_delays.2716199678 |
| Short name | T1449 |
| Test name | |
| Test status | |
| Simulation time | 7756975142 ps |
| CPU time | 78.79 seconds |
| Started | Jun 29 08:25:34 PM PDT 24 |
| Finished | Jun 29 08:26:53 PM PDT 24 |
| Peak memory | 574296 kb |
| Host | smart-0c372277-ebac-4444-a2c2-c3ecc02e1399 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2716199678 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 64.xbar_smoke_large_delays.2716199678 |
| Directory | /workspace/64.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/64.xbar_smoke_slow_rsp.134532497 |
| Short name | T2756 |
| Test name | |
| Test status | |
| Simulation time | 6826293059 ps |
| CPU time | 114.5 seconds |
| Started | Jun 29 08:25:35 PM PDT 24 |
| Finished | Jun 29 08:27:30 PM PDT 24 |
| Peak memory | 574332 kb |
| Host | smart-5bf3559c-53c2-4bbf-9f11-1ff117472e59 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=134532497 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 64.xbar_smoke_slow_rsp.134532497 |
| Directory | /workspace/64.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/64.xbar_smoke_zero_delays.2455754755 |
| Short name | T2210 |
| Test name | |
| Test status | |
| Simulation time | 49527007 ps |
| CPU time | 6.32 seconds |
| Started | Jun 29 08:25:49 PM PDT 24 |
| Finished | Jun 29 08:25:56 PM PDT 24 |
| Peak memory | 566004 kb |
| Host | smart-ffdccbbf-c728-42d6-879c-b6cf095abd1a |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2455754755 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 64.xbar_smoke_zero_delay s.2455754755 |
| Directory | /workspace/64.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/64.xbar_stress_all.3976091717 |
| Short name | T1549 |
| Test name | |
| Test status | |
| Simulation time | 10564690316 ps |
| CPU time | 400.06 seconds |
| Started | Jun 29 08:25:45 PM PDT 24 |
| Finished | Jun 29 08:32:26 PM PDT 24 |
| Peak memory | 575476 kb |
| Host | smart-5bd142b8-2558-4f66-b53e-0be6fd52d28e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3976091717 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 64.xbar_stress_all.3976091717 |
| Directory | /workspace/64.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/64.xbar_stress_all_with_error.1865704245 |
| Short name | T2362 |
| Test name | |
| Test status | |
| Simulation time | 3140493518 ps |
| CPU time | 218.79 seconds |
| Started | Jun 29 08:25:44 PM PDT 24 |
| Finished | Jun 29 08:29:23 PM PDT 24 |
| Peak memory | 574732 kb |
| Host | smart-1ba01f01-8dc1-45d2-97b4-6e662535ee54 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1865704245 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 64.xbar_stress_all_with_error.1865704245 |
| Directory | /workspace/64.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/64.xbar_stress_all_with_reset_error.2552945239 |
| Short name | T1812 |
| Test name | |
| Test status | |
| Simulation time | 16722633 ps |
| CPU time | 12.74 seconds |
| Started | Jun 29 08:25:44 PM PDT 24 |
| Finished | Jun 29 08:25:58 PM PDT 24 |
| Peak memory | 566168 kb |
| Host | smart-0cf2230a-915e-4f76-9355-685065465176 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2552945239 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 64.xbar_stress_al l_with_reset_error.2552945239 |
| Directory | /workspace/64.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/64.xbar_unmapped_addr.3334785031 |
| Short name | T2832 |
| Test name | |
| Test status | |
| Simulation time | 854564000 ps |
| CPU time | 39.63 seconds |
| Started | Jun 29 08:25:45 PM PDT 24 |
| Finished | Jun 29 08:26:25 PM PDT 24 |
| Peak memory | 575344 kb |
| Host | smart-8fd5e8a2-b19d-4207-bc16-af4208590713 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3334785031 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 64.xbar_unmapped_addr.3334785031 |
| Directory | /workspace/64.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/65.xbar_access_same_device.1425154265 |
| Short name | T2781 |
| Test name | |
| Test status | |
| Simulation time | 545449751 ps |
| CPU time | 25.73 seconds |
| Started | Jun 29 08:25:43 PM PDT 24 |
| Finished | Jun 29 08:26:09 PM PDT 24 |
| Peak memory | 575304 kb |
| Host | smart-cbbb74c5-1b35-4976-a1bb-374846c0fc75 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1425154265 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 65.xbar_access_same_device .1425154265 |
| Directory | /workspace/65.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/65.xbar_access_same_device_slow_rsp.854500738 |
| Short name | T2367 |
| Test name | |
| Test status | |
| Simulation time | 11085035232 ps |
| CPU time | 198.33 seconds |
| Started | Jun 29 08:25:51 PM PDT 24 |
| Finished | Jun 29 08:29:10 PM PDT 24 |
| Peak memory | 566104 kb |
| Host | smart-5124de1c-8e5d-49f0-b527-e81a7f5302ee |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=854500738 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 65.xbar_access_same_d evice_slow_rsp.854500738 |
| Directory | /workspace/65.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/65.xbar_error_and_unmapped_addr.927592451 |
| Short name | T1303 |
| Test name | |
| Test status | |
| Simulation time | 186118324 ps |
| CPU time | 23.46 seconds |
| Started | Jun 29 08:25:51 PM PDT 24 |
| Finished | Jun 29 08:26:15 PM PDT 24 |
| Peak memory | 573940 kb |
| Host | smart-7e505d55-0636-4b32-a6ec-81048cc63184 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=927592451 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 65.xbar_error_and_unmapped_addr .927592451 |
| Directory | /workspace/65.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/65.xbar_error_random.2303352437 |
| Short name | T2432 |
| Test name | |
| Test status | |
| Simulation time | 2924361056 ps |
| CPU time | 117.77 seconds |
| Started | Jun 29 08:25:56 PM PDT 24 |
| Finished | Jun 29 08:27:54 PM PDT 24 |
| Peak memory | 573952 kb |
| Host | smart-39b451b0-6c6c-4da3-aefb-d4773af44563 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2303352437 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 65.xbar_error_random.2303352437 |
| Directory | /workspace/65.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/65.xbar_random.1419446601 |
| Short name | T1519 |
| Test name | |
| Test status | |
| Simulation time | 745982573 ps |
| CPU time | 33.12 seconds |
| Started | Jun 29 08:25:45 PM PDT 24 |
| Finished | Jun 29 08:26:19 PM PDT 24 |
| Peak memory | 574244 kb |
| Host | smart-92735c45-1364-4e3c-8d49-d70976eec758 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1419446601 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 65.xbar_random.1419446601 |
| Directory | /workspace/65.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/65.xbar_random_large_delays.3647530624 |
| Short name | T2433 |
| Test name | |
| Test status | |
| Simulation time | 97604447290 ps |
| CPU time | 1057.64 seconds |
| Started | Jun 29 08:25:44 PM PDT 24 |
| Finished | Jun 29 08:43:23 PM PDT 24 |
| Peak memory | 574392 kb |
| Host | smart-46f7e8ee-2080-48c8-828d-d69d1ac39a32 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3647530624 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 65.xbar_random_large_delays.3647530624 |
| Directory | /workspace/65.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/65.xbar_random_slow_rsp.217963665 |
| Short name | T2190 |
| Test name | |
| Test status | |
| Simulation time | 24612732293 ps |
| CPU time | 444.21 seconds |
| Started | Jun 29 08:25:46 PM PDT 24 |
| Finished | Jun 29 08:33:11 PM PDT 24 |
| Peak memory | 575336 kb |
| Host | smart-2589e23a-0f7e-4e4c-bac2-1316813c9f3f |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=217963665 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 65.xbar_random_slow_rsp.217963665 |
| Directory | /workspace/65.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/65.xbar_random_zero_delays.2253477754 |
| Short name | T1586 |
| Test name | |
| Test status | |
| Simulation time | 107970942 ps |
| CPU time | 12.06 seconds |
| Started | Jun 29 08:25:45 PM PDT 24 |
| Finished | Jun 29 08:25:58 PM PDT 24 |
| Peak memory | 575260 kb |
| Host | smart-432abb20-024d-4d09-aa1d-47d61b0beac8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2253477754 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 65.xbar_random_zero_del ays.2253477754 |
| Directory | /workspace/65.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/65.xbar_same_source.4274625949 |
| Short name | T1859 |
| Test name | |
| Test status | |
| Simulation time | 1456356734 ps |
| CPU time | 41.14 seconds |
| Started | Jun 29 08:25:52 PM PDT 24 |
| Finished | Jun 29 08:26:34 PM PDT 24 |
| Peak memory | 575264 kb |
| Host | smart-170fe763-dc54-4c95-a968-25e6904fde14 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4274625949 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 65.xbar_same_source.4274625949 |
| Directory | /workspace/65.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/65.xbar_smoke.3510573608 |
| Short name | T2723 |
| Test name | |
| Test status | |
| Simulation time | 223640236 ps |
| CPU time | 9.96 seconds |
| Started | Jun 29 08:25:44 PM PDT 24 |
| Finished | Jun 29 08:25:55 PM PDT 24 |
| Peak memory | 574260 kb |
| Host | smart-d45b536e-ed53-4385-808d-852ed3816a45 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3510573608 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 65.xbar_smoke.3510573608 |
| Directory | /workspace/65.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/65.xbar_smoke_large_delays.2311955710 |
| Short name | T1340 |
| Test name | |
| Test status | |
| Simulation time | 8477290807 ps |
| CPU time | 93.79 seconds |
| Started | Jun 29 08:25:47 PM PDT 24 |
| Finished | Jun 29 08:27:21 PM PDT 24 |
| Peak memory | 574296 kb |
| Host | smart-ba40e7b9-6aed-4d5e-8d2c-a3117abd71c8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2311955710 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 65.xbar_smoke_large_delays.2311955710 |
| Directory | /workspace/65.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/65.xbar_smoke_slow_rsp.765470210 |
| Short name | T2363 |
| Test name | |
| Test status | |
| Simulation time | 5246789485 ps |
| CPU time | 96 seconds |
| Started | Jun 29 08:25:47 PM PDT 24 |
| Finished | Jun 29 08:27:23 PM PDT 24 |
| Peak memory | 565588 kb |
| Host | smart-c7835aca-da6c-481d-bbbc-d79e6c2afcb2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=765470210 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 65.xbar_smoke_slow_rsp.765470210 |
| Directory | /workspace/65.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/65.xbar_smoke_zero_delays.4220821865 |
| Short name | T1760 |
| Test name | |
| Test status | |
| Simulation time | 53141526 ps |
| CPU time | 6.92 seconds |
| Started | Jun 29 08:25:45 PM PDT 24 |
| Finished | Jun 29 08:25:53 PM PDT 24 |
| Peak memory | 566012 kb |
| Host | smart-1bc2fcc5-e77b-478c-8872-f9cddf6a8667 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4220821865 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 65.xbar_smoke_zero_delay s.4220821865 |
| Directory | /workspace/65.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/65.xbar_stress_all.3138263187 |
| Short name | T1903 |
| Test name | |
| Test status | |
| Simulation time | 4328449728 ps |
| CPU time | 205.97 seconds |
| Started | Jun 29 08:25:53 PM PDT 24 |
| Finished | Jun 29 08:29:19 PM PDT 24 |
| Peak memory | 575520 kb |
| Host | smart-455df482-f1a6-4506-87cd-1f3b3de5b371 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3138263187 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 65.xbar_stress_all.3138263187 |
| Directory | /workspace/65.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/65.xbar_stress_all_with_error.3958170580 |
| Short name | T1364 |
| Test name | |
| Test status | |
| Simulation time | 1525599144 ps |
| CPU time | 124.65 seconds |
| Started | Jun 29 08:25:54 PM PDT 24 |
| Finished | Jun 29 08:27:59 PM PDT 24 |
| Peak memory | 574660 kb |
| Host | smart-3ad8d54a-44fd-496f-aae5-5b733b493b9b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3958170580 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 65.xbar_stress_all_with_error.3958170580 |
| Directory | /workspace/65.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/65.xbar_stress_all_with_rand_reset.751930836 |
| Short name | T1765 |
| Test name | |
| Test status | |
| Simulation time | 3589872932 ps |
| CPU time | 498.76 seconds |
| Started | Jun 29 08:25:51 PM PDT 24 |
| Finished | Jun 29 08:34:10 PM PDT 24 |
| Peak memory | 575520 kb |
| Host | smart-bfa0548b-adf6-4cf7-807a-4ba5fd41c874 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=751930836 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_res et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 65.xbar_stress_all_ with_rand_reset.751930836 |
| Directory | /workspace/65.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/65.xbar_stress_all_with_reset_error.1093390142 |
| Short name | T2549 |
| Test name | |
| Test status | |
| Simulation time | 17398872089 ps |
| CPU time | 873.19 seconds |
| Started | Jun 29 08:25:50 PM PDT 24 |
| Finished | Jun 29 08:40:24 PM PDT 24 |
| Peak memory | 574740 kb |
| Host | smart-ec29609f-277c-43bb-90a1-a4aebc80ff76 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1093390142 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 65.xbar_stress_al l_with_reset_error.1093390142 |
| Directory | /workspace/65.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/65.xbar_unmapped_addr.2432338585 |
| Short name | T1427 |
| Test name | |
| Test status | |
| Simulation time | 294582747 ps |
| CPU time | 40.08 seconds |
| Started | Jun 29 08:25:57 PM PDT 24 |
| Finished | Jun 29 08:26:37 PM PDT 24 |
| Peak memory | 575184 kb |
| Host | smart-e5f72efa-d983-468d-b26b-13e11b4e1729 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2432338585 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 65.xbar_unmapped_addr.2432338585 |
| Directory | /workspace/65.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/66.xbar_access_same_device.4093600546 |
| Short name | T502 |
| Test name | |
| Test status | |
| Simulation time | 1047314666 ps |
| CPU time | 45.3 seconds |
| Started | Jun 29 08:25:54 PM PDT 24 |
| Finished | Jun 29 08:26:40 PM PDT 24 |
| Peak memory | 575372 kb |
| Host | smart-8dd26522-a6a8-447a-8cfd-09ef3c1223c0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4093600546 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 66.xbar_access_same_device .4093600546 |
| Directory | /workspace/66.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/66.xbar_access_same_device_slow_rsp.806880597 |
| Short name | T2850 |
| Test name | |
| Test status | |
| Simulation time | 54974857420 ps |
| CPU time | 957.89 seconds |
| Started | Jun 29 08:25:53 PM PDT 24 |
| Finished | Jun 29 08:41:51 PM PDT 24 |
| Peak memory | 575412 kb |
| Host | smart-480aee92-813b-450c-b15c-d9ee30bf9d36 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=806880597 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 66.xbar_access_same_d evice_slow_rsp.806880597 |
| Directory | /workspace/66.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/66.xbar_error_and_unmapped_addr.726816922 |
| Short name | T1321 |
| Test name | |
| Test status | |
| Simulation time | 108135977 ps |
| CPU time | 13.75 seconds |
| Started | Jun 29 08:26:01 PM PDT 24 |
| Finished | Jun 29 08:26:15 PM PDT 24 |
| Peak memory | 574508 kb |
| Host | smart-809f9d16-9160-4a40-a769-33d48f751fba |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=726816922 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 66.xbar_error_and_unmapped_addr .726816922 |
| Directory | /workspace/66.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/66.xbar_error_random.1002169787 |
| Short name | T2325 |
| Test name | |
| Test status | |
| Simulation time | 67888764 ps |
| CPU time | 8.86 seconds |
| Started | Jun 29 08:25:52 PM PDT 24 |
| Finished | Jun 29 08:26:01 PM PDT 24 |
| Peak memory | 574500 kb |
| Host | smart-43f827bf-e0a0-432e-b988-a0cfa0c3322e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1002169787 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 66.xbar_error_random.1002169787 |
| Directory | /workspace/66.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/66.xbar_random.1634301815 |
| Short name | T564 |
| Test name | |
| Test status | |
| Simulation time | 434651491 ps |
| CPU time | 44.39 seconds |
| Started | Jun 29 08:25:50 PM PDT 24 |
| Finished | Jun 29 08:26:35 PM PDT 24 |
| Peak memory | 575340 kb |
| Host | smart-c4c1c421-96c9-4258-95a1-9ca3c25691be |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1634301815 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 66.xbar_random.1634301815 |
| Directory | /workspace/66.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/66.xbar_random_large_delays.221464018 |
| Short name | T484 |
| Test name | |
| Test status | |
| Simulation time | 31322042728 ps |
| CPU time | 350.36 seconds |
| Started | Jun 29 08:25:52 PM PDT 24 |
| Finished | Jun 29 08:31:43 PM PDT 24 |
| Peak memory | 575364 kb |
| Host | smart-a2c93aca-4bc8-402e-a2c9-6c2dac2ebefb |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=221464018 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 66.xbar_random_large_delays.221464018 |
| Directory | /workspace/66.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/66.xbar_random_slow_rsp.1686307505 |
| Short name | T2254 |
| Test name | |
| Test status | |
| Simulation time | 53119148412 ps |
| CPU time | 989.42 seconds |
| Started | Jun 29 08:25:52 PM PDT 24 |
| Finished | Jun 29 08:42:21 PM PDT 24 |
| Peak memory | 574324 kb |
| Host | smart-ec54e183-4c79-484e-8771-4b84b021b5fc |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1686307505 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 66.xbar_random_slow_rsp.1686307505 |
| Directory | /workspace/66.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/66.xbar_random_zero_delays.212558807 |
| Short name | T505 |
| Test name | |
| Test status | |
| Simulation time | 595744542 ps |
| CPU time | 55.36 seconds |
| Started | Jun 29 08:25:55 PM PDT 24 |
| Finished | Jun 29 08:26:51 PM PDT 24 |
| Peak memory | 575304 kb |
| Host | smart-f5803287-3b02-4133-b597-5d5b5042f692 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=212558807 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 66.xbar_random_zero_dela ys.212558807 |
| Directory | /workspace/66.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/66.xbar_same_source.2195254809 |
| Short name | T2378 |
| Test name | |
| Test status | |
| Simulation time | 231191137 ps |
| CPU time | 9.92 seconds |
| Started | Jun 29 08:25:51 PM PDT 24 |
| Finished | Jun 29 08:26:01 PM PDT 24 |
| Peak memory | 574092 kb |
| Host | smart-bc6b39af-8de8-4151-a848-b414167ae678 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2195254809 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 66.xbar_same_source.2195254809 |
| Directory | /workspace/66.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/66.xbar_smoke.1930823607 |
| Short name | T2085 |
| Test name | |
| Test status | |
| Simulation time | 177537654 ps |
| CPU time | 9 seconds |
| Started | Jun 29 08:25:51 PM PDT 24 |
| Finished | Jun 29 08:26:01 PM PDT 24 |
| Peak memory | 574140 kb |
| Host | smart-5628a3fc-d281-454f-98a0-a42e0ce608da |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1930823607 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 66.xbar_smoke.1930823607 |
| Directory | /workspace/66.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/66.xbar_smoke_large_delays.1701010187 |
| Short name | T548 |
| Test name | |
| Test status | |
| Simulation time | 8233519190 ps |
| CPU time | 91.52 seconds |
| Started | Jun 29 08:25:52 PM PDT 24 |
| Finished | Jun 29 08:27:24 PM PDT 24 |
| Peak memory | 574328 kb |
| Host | smart-131e8ada-2636-4343-8181-b57a3ce5e557 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1701010187 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 66.xbar_smoke_large_delays.1701010187 |
| Directory | /workspace/66.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/66.xbar_smoke_slow_rsp.2466787783 |
| Short name | T1990 |
| Test name | |
| Test status | |
| Simulation time | 4565592222 ps |
| CPU time | 78.72 seconds |
| Started | Jun 29 08:25:51 PM PDT 24 |
| Finished | Jun 29 08:27:10 PM PDT 24 |
| Peak memory | 574320 kb |
| Host | smart-25348649-411f-4e9d-9b3e-7134ee3415ac |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2466787783 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 66.xbar_smoke_slow_rsp.2466787783 |
| Directory | /workspace/66.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/66.xbar_smoke_zero_delays.412839226 |
| Short name | T2194 |
| Test name | |
| Test status | |
| Simulation time | 43366520 ps |
| CPU time | 6.24 seconds |
| Started | Jun 29 08:25:52 PM PDT 24 |
| Finished | Jun 29 08:25:59 PM PDT 24 |
| Peak memory | 574204 kb |
| Host | smart-df1ae5ea-b664-401f-955c-7c04c41c5eac |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=412839226 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 66.xbar_smoke_zero_delays .412839226 |
| Directory | /workspace/66.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/66.xbar_stress_all.812364544 |
| Short name | T576 |
| Test name | |
| Test status | |
| Simulation time | 823436326 ps |
| CPU time | 83.71 seconds |
| Started | Jun 29 08:26:00 PM PDT 24 |
| Finished | Jun 29 08:27:24 PM PDT 24 |
| Peak memory | 574368 kb |
| Host | smart-a58afab5-663e-46f0-aa57-3fe28a8df4f1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=812364544 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 66.xbar_stress_all.812364544 |
| Directory | /workspace/66.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/66.xbar_stress_all_with_error.1550344885 |
| Short name | T2134 |
| Test name | |
| Test status | |
| Simulation time | 10131396733 ps |
| CPU time | 433.89 seconds |
| Started | Jun 29 08:26:04 PM PDT 24 |
| Finished | Jun 29 08:33:19 PM PDT 24 |
| Peak memory | 574456 kb |
| Host | smart-f4bd5470-8b3a-4b13-a1e9-db2429d48909 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1550344885 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 66.xbar_stress_all_with_error.1550344885 |
| Directory | /workspace/66.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/66.xbar_stress_all_with_rand_reset.349944438 |
| Short name | T552 |
| Test name | |
| Test status | |
| Simulation time | 4447062891 ps |
| CPU time | 339.39 seconds |
| Started | Jun 29 08:26:05 PM PDT 24 |
| Finished | Jun 29 08:31:45 PM PDT 24 |
| Peak memory | 575512 kb |
| Host | smart-5d0e39ef-baa9-411b-a2b6-e907708ff246 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=349944438 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_res et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 66.xbar_stress_all_ with_rand_reset.349944438 |
| Directory | /workspace/66.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/66.xbar_stress_all_with_reset_error.344172187 |
| Short name | T2628 |
| Test name | |
| Test status | |
| Simulation time | 249291253 ps |
| CPU time | 115.16 seconds |
| Started | Jun 29 08:26:00 PM PDT 24 |
| Finished | Jun 29 08:27:56 PM PDT 24 |
| Peak memory | 574404 kb |
| Host | smart-32f4344c-c08e-4559-bc3c-fac0458dc71c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=344172187 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 66.xbar_stress_all _with_reset_error.344172187 |
| Directory | /workspace/66.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/66.xbar_unmapped_addr.1885767862 |
| Short name | T2405 |
| Test name | |
| Test status | |
| Simulation time | 54269889 ps |
| CPU time | 10.17 seconds |
| Started | Jun 29 08:25:52 PM PDT 24 |
| Finished | Jun 29 08:26:03 PM PDT 24 |
| Peak memory | 575368 kb |
| Host | smart-3ad2f466-8858-4b6b-b70b-1df9cd4434fd |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1885767862 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 66.xbar_unmapped_addr.1885767862 |
| Directory | /workspace/66.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/67.xbar_access_same_device.999669038 |
| Short name | T2523 |
| Test name | |
| Test status | |
| Simulation time | 2727825861 ps |
| CPU time | 113.83 seconds |
| Started | Jun 29 08:26:12 PM PDT 24 |
| Finished | Jun 29 08:28:06 PM PDT 24 |
| Peak memory | 575424 kb |
| Host | smart-d897d700-c5e3-431d-a5ff-9939344ee527 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=999669038 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 67.xbar_access_same_device. 999669038 |
| Directory | /workspace/67.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/67.xbar_access_same_device_slow_rsp.4276165069 |
| Short name | T1721 |
| Test name | |
| Test status | |
| Simulation time | 37919337995 ps |
| CPU time | 650.38 seconds |
| Started | Jun 29 08:26:07 PM PDT 24 |
| Finished | Jun 29 08:36:58 PM PDT 24 |
| Peak memory | 575408 kb |
| Host | smart-b33672c1-7eff-4095-bd7f-75328e5f032b |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4276165069 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 67.xbar_access_same_ device_slow_rsp.4276165069 |
| Directory | /workspace/67.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/67.xbar_error_and_unmapped_addr.2468471218 |
| Short name | T1299 |
| Test name | |
| Test status | |
| Simulation time | 264519232 ps |
| CPU time | 28.05 seconds |
| Started | Jun 29 08:26:09 PM PDT 24 |
| Finished | Jun 29 08:26:37 PM PDT 24 |
| Peak memory | 573888 kb |
| Host | smart-a0b23e6e-22e8-4bae-88e2-1c3e72995897 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2468471218 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 67.xbar_error_and_unmapped_add r.2468471218 |
| Directory | /workspace/67.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/67.xbar_error_random.4227277073 |
| Short name | T1627 |
| Test name | |
| Test status | |
| Simulation time | 540779342 ps |
| CPU time | 41.51 seconds |
| Started | Jun 29 08:26:06 PM PDT 24 |
| Finished | Jun 29 08:26:48 PM PDT 24 |
| Peak memory | 574496 kb |
| Host | smart-66ae41e1-ef5d-43df-9840-9f56cd0eb791 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4227277073 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 67.xbar_error_random.4227277073 |
| Directory | /workspace/67.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/67.xbar_random.3724676986 |
| Short name | T2203 |
| Test name | |
| Test status | |
| Simulation time | 969396552 ps |
| CPU time | 37.64 seconds |
| Started | Jun 29 08:25:58 PM PDT 24 |
| Finished | Jun 29 08:26:36 PM PDT 24 |
| Peak memory | 574256 kb |
| Host | smart-9d2959ad-7164-4883-a5a2-fbf0874e7c44 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3724676986 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 67.xbar_random.3724676986 |
| Directory | /workspace/67.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/67.xbar_random_large_delays.973400011 |
| Short name | T2125 |
| Test name | |
| Test status | |
| Simulation time | 28741416431 ps |
| CPU time | 324.39 seconds |
| Started | Jun 29 08:26:03 PM PDT 24 |
| Finished | Jun 29 08:31:28 PM PDT 24 |
| Peak memory | 575388 kb |
| Host | smart-59542341-048c-4044-a461-b3bf03d96da9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=973400011 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 67.xbar_random_large_delays.973400011 |
| Directory | /workspace/67.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/67.xbar_random_slow_rsp.3516982592 |
| Short name | T2285 |
| Test name | |
| Test status | |
| Simulation time | 49516875826 ps |
| CPU time | 876.67 seconds |
| Started | Jun 29 08:26:03 PM PDT 24 |
| Finished | Jun 29 08:40:40 PM PDT 24 |
| Peak memory | 575416 kb |
| Host | smart-56071358-054b-4500-a5db-54f76b00472d |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3516982592 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 67.xbar_random_slow_rsp.3516982592 |
| Directory | /workspace/67.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/67.xbar_random_zero_delays.389781148 |
| Short name | T615 |
| Test name | |
| Test status | |
| Simulation time | 482309435 ps |
| CPU time | 45.62 seconds |
| Started | Jun 29 08:26:01 PM PDT 24 |
| Finished | Jun 29 08:26:47 PM PDT 24 |
| Peak memory | 575328 kb |
| Host | smart-d79198e0-4d4e-4da0-80dc-6b9197bf0403 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=389781148 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 67.xbar_random_zero_dela ys.389781148 |
| Directory | /workspace/67.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/67.xbar_same_source.24676999 |
| Short name | T2814 |
| Test name | |
| Test status | |
| Simulation time | 431314747 ps |
| CPU time | 30.95 seconds |
| Started | Jun 29 08:26:07 PM PDT 24 |
| Finished | Jun 29 08:26:39 PM PDT 24 |
| Peak memory | 575292 kb |
| Host | smart-bffaadb3-e533-4d3b-843d-1e39d4638a57 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24676999 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 67.xbar_same_source.24676999 |
| Directory | /workspace/67.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/67.xbar_smoke.3308051075 |
| Short name | T1538 |
| Test name | |
| Test status | |
| Simulation time | 210831906 ps |
| CPU time | 9.46 seconds |
| Started | Jun 29 08:26:01 PM PDT 24 |
| Finished | Jun 29 08:26:10 PM PDT 24 |
| Peak memory | 574260 kb |
| Host | smart-b1b54853-40c2-4c36-b5d5-04194e670145 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3308051075 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 67.xbar_smoke.3308051075 |
| Directory | /workspace/67.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/67.xbar_smoke_large_delays.3552166010 |
| Short name | T2311 |
| Test name | |
| Test status | |
| Simulation time | 7307569143 ps |
| CPU time | 79.46 seconds |
| Started | Jun 29 08:26:04 PM PDT 24 |
| Finished | Jun 29 08:27:23 PM PDT 24 |
| Peak memory | 574320 kb |
| Host | smart-38061b4b-1d12-4978-84eb-69691d36f3f3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3552166010 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 67.xbar_smoke_large_delays.3552166010 |
| Directory | /workspace/67.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/67.xbar_smoke_slow_rsp.3567672420 |
| Short name | T2579 |
| Test name | |
| Test status | |
| Simulation time | 4377559482 ps |
| CPU time | 75.95 seconds |
| Started | Jun 29 08:26:03 PM PDT 24 |
| Finished | Jun 29 08:27:19 PM PDT 24 |
| Peak memory | 574328 kb |
| Host | smart-4c8f59ba-a4cd-4653-a76b-bbe02c1a6ff9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3567672420 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 67.xbar_smoke_slow_rsp.3567672420 |
| Directory | /workspace/67.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/67.xbar_smoke_zero_delays.1849545777 |
| Short name | T1756 |
| Test name | |
| Test status | |
| Simulation time | 47700715 ps |
| CPU time | 6.44 seconds |
| Started | Jun 29 08:26:04 PM PDT 24 |
| Finished | Jun 29 08:26:10 PM PDT 24 |
| Peak memory | 574260 kb |
| Host | smart-6b813cb4-15b3-40cb-a536-2586a0bc67af |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1849545777 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 67.xbar_smoke_zero_delay s.1849545777 |
| Directory | /workspace/67.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/67.xbar_stress_all.2575554448 |
| Short name | T439 |
| Test name | |
| Test status | |
| Simulation time | 9703976030 ps |
| CPU time | 332.1 seconds |
| Started | Jun 29 08:26:09 PM PDT 24 |
| Finished | Jun 29 08:31:41 PM PDT 24 |
| Peak memory | 575472 kb |
| Host | smart-f9b3618d-242b-4945-aabe-0e642df67cd0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2575554448 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 67.xbar_stress_all.2575554448 |
| Directory | /workspace/67.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/67.xbar_stress_all_with_error.2316497430 |
| Short name | T792 |
| Test name | |
| Test status | |
| Simulation time | 2587522088 ps |
| CPU time | 252.71 seconds |
| Started | Jun 29 08:26:08 PM PDT 24 |
| Finished | Jun 29 08:30:21 PM PDT 24 |
| Peak memory | 574368 kb |
| Host | smart-b55ebdc0-94ae-4a10-bd41-931db53073f9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2316497430 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 67.xbar_stress_all_with_error.2316497430 |
| Directory | /workspace/67.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/67.xbar_stress_all_with_rand_reset.2663895972 |
| Short name | T459 |
| Test name | |
| Test status | |
| Simulation time | 506319789 ps |
| CPU time | 200.44 seconds |
| Started | Jun 29 08:26:06 PM PDT 24 |
| Finished | Jun 29 08:29:27 PM PDT 24 |
| Peak memory | 575420 kb |
| Host | smart-ee36a706-9a93-4b6b-83f4-7b59363af0d3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2663895972 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 67.xbar_stress_all _with_rand_reset.2663895972 |
| Directory | /workspace/67.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/67.xbar_stress_all_with_reset_error.886921009 |
| Short name | T1338 |
| Test name | |
| Test status | |
| Simulation time | 7565157 ps |
| CPU time | 19.58 seconds |
| Started | Jun 29 08:26:07 PM PDT 24 |
| Finished | Jun 29 08:26:27 PM PDT 24 |
| Peak memory | 574340 kb |
| Host | smart-7b94567a-3c4a-4b37-8c51-9e04805089f3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=886921009 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 67.xbar_stress_all _with_reset_error.886921009 |
| Directory | /workspace/67.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/67.xbar_unmapped_addr.432196167 |
| Short name | T2081 |
| Test name | |
| Test status | |
| Simulation time | 855856517 ps |
| CPU time | 38.13 seconds |
| Started | Jun 29 08:26:08 PM PDT 24 |
| Finished | Jun 29 08:26:47 PM PDT 24 |
| Peak memory | 574316 kb |
| Host | smart-d2e00ba0-fb52-4488-acbd-122a013605e8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=432196167 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 67.xbar_unmapped_addr.432196167 |
| Directory | /workspace/67.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/68.xbar_access_same_device.3281575141 |
| Short name | T1962 |
| Test name | |
| Test status | |
| Simulation time | 3050793401 ps |
| CPU time | 134.52 seconds |
| Started | Jun 29 08:26:07 PM PDT 24 |
| Finished | Jun 29 08:28:21 PM PDT 24 |
| Peak memory | 575364 kb |
| Host | smart-f6051f78-f49f-4de0-9b52-c36fd0f82a37 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3281575141 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 68.xbar_access_same_device .3281575141 |
| Directory | /workspace/68.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/68.xbar_access_same_device_slow_rsp.1682718196 |
| Short name | T2623 |
| Test name | |
| Test status | |
| Simulation time | 147426970880 ps |
| CPU time | 2535.32 seconds |
| Started | Jun 29 08:26:18 PM PDT 24 |
| Finished | Jun 29 09:08:34 PM PDT 24 |
| Peak memory | 575476 kb |
| Host | smart-1b2fedec-e99c-4d99-83c9-b084ff8b9369 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1682718196 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 68.xbar_access_same_ device_slow_rsp.1682718196 |
| Directory | /workspace/68.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/68.xbar_error_and_unmapped_addr.2217779006 |
| Short name | T1666 |
| Test name | |
| Test status | |
| Simulation time | 127894123 ps |
| CPU time | 14.9 seconds |
| Started | Jun 29 08:26:15 PM PDT 24 |
| Finished | Jun 29 08:26:30 PM PDT 24 |
| Peak memory | 573944 kb |
| Host | smart-ff2a506f-c467-4308-8cef-1da61f5715d9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2217779006 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 68.xbar_error_and_unmapped_add r.2217779006 |
| Directory | /workspace/68.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/68.xbar_error_random.1395192054 |
| Short name | T1392 |
| Test name | |
| Test status | |
| Simulation time | 2266471973 ps |
| CPU time | 85.61 seconds |
| Started | Jun 29 08:26:15 PM PDT 24 |
| Finished | Jun 29 08:27:40 PM PDT 24 |
| Peak memory | 574552 kb |
| Host | smart-a56c6c12-05c8-4dea-bd03-1b7a852748c0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1395192054 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 68.xbar_error_random.1395192054 |
| Directory | /workspace/68.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/68.xbar_random.1398049074 |
| Short name | T2189 |
| Test name | |
| Test status | |
| Simulation time | 350316211 ps |
| CPU time | 17.57 seconds |
| Started | Jun 29 08:26:07 PM PDT 24 |
| Finished | Jun 29 08:26:25 PM PDT 24 |
| Peak memory | 575296 kb |
| Host | smart-a878b2f1-25d3-49df-a67d-dcbe98b64605 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1398049074 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 68.xbar_random.1398049074 |
| Directory | /workspace/68.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/68.xbar_random_large_delays.3072843210 |
| Short name | T588 |
| Test name | |
| Test status | |
| Simulation time | 41448742351 ps |
| CPU time | 433.81 seconds |
| Started | Jun 29 08:26:12 PM PDT 24 |
| Finished | Jun 29 08:33:26 PM PDT 24 |
| Peak memory | 575396 kb |
| Host | smart-89fa15ac-12ca-41f2-9e04-db1eb7bf1415 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3072843210 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 68.xbar_random_large_delays.3072843210 |
| Directory | /workspace/68.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/68.xbar_random_slow_rsp.688766159 |
| Short name | T2551 |
| Test name | |
| Test status | |
| Simulation time | 15471974852 ps |
| CPU time | 271.27 seconds |
| Started | Jun 29 08:26:08 PM PDT 24 |
| Finished | Jun 29 08:30:40 PM PDT 24 |
| Peak memory | 575376 kb |
| Host | smart-326df260-7b64-4190-a1f9-5ffa0cc98894 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=688766159 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 68.xbar_random_slow_rsp.688766159 |
| Directory | /workspace/68.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/68.xbar_random_zero_delays.1978245269 |
| Short name | T2344 |
| Test name | |
| Test status | |
| Simulation time | 574512037 ps |
| CPU time | 55.91 seconds |
| Started | Jun 29 08:26:09 PM PDT 24 |
| Finished | Jun 29 08:27:05 PM PDT 24 |
| Peak memory | 575304 kb |
| Host | smart-e1446768-7b7b-465e-ace3-63d241529df2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1978245269 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 68.xbar_random_zero_del ays.1978245269 |
| Directory | /workspace/68.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/68.xbar_same_source.1705565193 |
| Short name | T1702 |
| Test name | |
| Test status | |
| Simulation time | 1455772290 ps |
| CPU time | 43.15 seconds |
| Started | Jun 29 08:26:16 PM PDT 24 |
| Finished | Jun 29 08:26:59 PM PDT 24 |
| Peak memory | 575312 kb |
| Host | smart-2f95d0e6-3cab-4b02-9f98-680a6c79ae33 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1705565193 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 68.xbar_same_source.1705565193 |
| Directory | /workspace/68.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/68.xbar_smoke.3235624776 |
| Short name | T560 |
| Test name | |
| Test status | |
| Simulation time | 231964017 ps |
| CPU time | 10.02 seconds |
| Started | Jun 29 08:26:07 PM PDT 24 |
| Finished | Jun 29 08:26:17 PM PDT 24 |
| Peak memory | 574276 kb |
| Host | smart-492a7a09-a625-43b5-ae68-e204b3381b89 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3235624776 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 68.xbar_smoke.3235624776 |
| Directory | /workspace/68.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/68.xbar_smoke_large_delays.2812636420 |
| Short name | T2717 |
| Test name | |
| Test status | |
| Simulation time | 7688594352 ps |
| CPU time | 78.6 seconds |
| Started | Jun 29 08:26:06 PM PDT 24 |
| Finished | Jun 29 08:27:25 PM PDT 24 |
| Peak memory | 574328 kb |
| Host | smart-7c280fa3-8575-4b34-ae6d-5ce4b7060583 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2812636420 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 68.xbar_smoke_large_delays.2812636420 |
| Directory | /workspace/68.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/68.xbar_smoke_slow_rsp.3278442200 |
| Short name | T1878 |
| Test name | |
| Test status | |
| Simulation time | 3285801040 ps |
| CPU time | 56.64 seconds |
| Started | Jun 29 08:26:12 PM PDT 24 |
| Finished | Jun 29 08:27:09 PM PDT 24 |
| Peak memory | 574144 kb |
| Host | smart-b87cf8f1-77e3-4bf3-9561-6c0f5baf09c0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3278442200 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 68.xbar_smoke_slow_rsp.3278442200 |
| Directory | /workspace/68.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/68.xbar_smoke_zero_delays.1020223885 |
| Short name | T2576 |
| Test name | |
| Test status | |
| Simulation time | 39684681 ps |
| CPU time | 6.05 seconds |
| Started | Jun 29 08:26:12 PM PDT 24 |
| Finished | Jun 29 08:26:18 PM PDT 24 |
| Peak memory | 574252 kb |
| Host | smart-a1422ffc-4076-4931-8f65-c4d90ba46def |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1020223885 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 68.xbar_smoke_zero_delay s.1020223885 |
| Directory | /workspace/68.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/68.xbar_stress_all.3959716857 |
| Short name | T2624 |
| Test name | |
| Test status | |
| Simulation time | 1060819496 ps |
| CPU time | 99.58 seconds |
| Started | Jun 29 08:26:20 PM PDT 24 |
| Finished | Jun 29 08:28:00 PM PDT 24 |
| Peak memory | 575408 kb |
| Host | smart-f7833e0b-e97c-4d12-ba51-a50a3edf0ee6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3959716857 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 68.xbar_stress_all.3959716857 |
| Directory | /workspace/68.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/68.xbar_stress_all_with_error.1619549200 |
| Short name | T2114 |
| Test name | |
| Test status | |
| Simulation time | 2551409442 ps |
| CPU time | 221.64 seconds |
| Started | Jun 29 08:26:14 PM PDT 24 |
| Finished | Jun 29 08:29:56 PM PDT 24 |
| Peak memory | 574452 kb |
| Host | smart-f5c5906d-0897-44e2-8dd9-d5c75e6e6717 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1619549200 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 68.xbar_stress_all_with_error.1619549200 |
| Directory | /workspace/68.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/68.xbar_stress_all_with_rand_reset.54076765 |
| Short name | T818 |
| Test name | |
| Test status | |
| Simulation time | 225941352 ps |
| CPU time | 78.4 seconds |
| Started | Jun 29 08:26:20 PM PDT 24 |
| Finished | Jun 29 08:27:39 PM PDT 24 |
| Peak memory | 574376 kb |
| Host | smart-7fb4787f-33a9-4874-aa24-88dc1699a3bc |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54076765 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_rese t_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 68.xbar_stress_all_w ith_rand_reset.54076765 |
| Directory | /workspace/68.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/68.xbar_stress_all_with_reset_error.2258627727 |
| Short name | T2316 |
| Test name | |
| Test status | |
| Simulation time | 6689507729 ps |
| CPU time | 396.66 seconds |
| Started | Jun 29 08:26:27 PM PDT 24 |
| Finished | Jun 29 08:33:04 PM PDT 24 |
| Peak memory | 577524 kb |
| Host | smart-9113fc80-f537-4c20-93bf-fd4ac8a3d44e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2258627727 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 68.xbar_stress_al l_with_reset_error.2258627727 |
| Directory | /workspace/68.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/68.xbar_unmapped_addr.4202959157 |
| Short name | T2301 |
| Test name | |
| Test status | |
| Simulation time | 208037617 ps |
| CPU time | 27.28 seconds |
| Started | Jun 29 08:26:15 PM PDT 24 |
| Finished | Jun 29 08:26:43 PM PDT 24 |
| Peak memory | 575300 kb |
| Host | smart-76460cd5-6e1d-4fd6-8e44-3f107f0e47e0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4202959157 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 68.xbar_unmapped_addr.4202959157 |
| Directory | /workspace/68.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/69.xbar_access_same_device_slow_rsp.3238587131 |
| Short name | T2881 |
| Test name | |
| Test status | |
| Simulation time | 62887156369 ps |
| CPU time | 1031.92 seconds |
| Started | Jun 29 08:26:24 PM PDT 24 |
| Finished | Jun 29 08:43:36 PM PDT 24 |
| Peak memory | 575412 kb |
| Host | smart-1fa06e54-3e6b-4449-b078-65f44c74efc7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3238587131 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 69.xbar_access_same_ device_slow_rsp.3238587131 |
| Directory | /workspace/69.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/69.xbar_error_and_unmapped_addr.3064001000 |
| Short name | T2059 |
| Test name | |
| Test status | |
| Simulation time | 1399208070 ps |
| CPU time | 58.83 seconds |
| Started | Jun 29 08:26:23 PM PDT 24 |
| Finished | Jun 29 08:27:22 PM PDT 24 |
| Peak memory | 574264 kb |
| Host | smart-79ee8eea-aacc-4b7f-9051-667b399840f6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3064001000 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 69.xbar_error_and_unmapped_add r.3064001000 |
| Directory | /workspace/69.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/69.xbar_error_random.1877543398 |
| Short name | T2804 |
| Test name | |
| Test status | |
| Simulation time | 33583345 ps |
| CPU time | 6.18 seconds |
| Started | Jun 29 08:26:23 PM PDT 24 |
| Finished | Jun 29 08:26:30 PM PDT 24 |
| Peak memory | 565572 kb |
| Host | smart-c909d179-3fda-49b1-b417-a16672ff18fb |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1877543398 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 69.xbar_error_random.1877543398 |
| Directory | /workspace/69.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/69.xbar_random.3439874549 |
| Short name | T1356 |
| Test name | |
| Test status | |
| Simulation time | 746904014 ps |
| CPU time | 31.53 seconds |
| Started | Jun 29 08:26:22 PM PDT 24 |
| Finished | Jun 29 08:26:54 PM PDT 24 |
| Peak memory | 575300 kb |
| Host | smart-6d52ddb8-3229-4ed2-9654-9f17437b4ce4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3439874549 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 69.xbar_random.3439874549 |
| Directory | /workspace/69.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/69.xbar_random_large_delays.1205991825 |
| Short name | T2305 |
| Test name | |
| Test status | |
| Simulation time | 8727944523 ps |
| CPU time | 98.23 seconds |
| Started | Jun 29 08:26:23 PM PDT 24 |
| Finished | Jun 29 08:28:01 PM PDT 24 |
| Peak memory | 574312 kb |
| Host | smart-2da6f3a7-1989-49f7-9fd2-42a16401ab77 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1205991825 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 69.xbar_random_large_delays.1205991825 |
| Directory | /workspace/69.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/69.xbar_random_slow_rsp.1933334506 |
| Short name | T2592 |
| Test name | |
| Test status | |
| Simulation time | 57508929025 ps |
| CPU time | 942.57 seconds |
| Started | Jun 29 08:26:23 PM PDT 24 |
| Finished | Jun 29 08:42:06 PM PDT 24 |
| Peak memory | 575372 kb |
| Host | smart-07db637a-02f0-4225-9f60-92a0d5de2e6d |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1933334506 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 69.xbar_random_slow_rsp.1933334506 |
| Directory | /workspace/69.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/69.xbar_random_zero_delays.2791789810 |
| Short name | T2083 |
| Test name | |
| Test status | |
| Simulation time | 226756314 ps |
| CPU time | 20.92 seconds |
| Started | Jun 29 08:26:23 PM PDT 24 |
| Finished | Jun 29 08:26:45 PM PDT 24 |
| Peak memory | 574236 kb |
| Host | smart-25754023-4ae1-4c1b-85eb-add663affcf5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2791789810 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 69.xbar_random_zero_del ays.2791789810 |
| Directory | /workspace/69.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/69.xbar_same_source.4007537296 |
| Short name | T2291 |
| Test name | |
| Test status | |
| Simulation time | 761256496 ps |
| CPU time | 25.87 seconds |
| Started | Jun 29 08:26:22 PM PDT 24 |
| Finished | Jun 29 08:26:48 PM PDT 24 |
| Peak memory | 575292 kb |
| Host | smart-22c1e042-ca9c-4625-80f9-30ee4a9e4976 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4007537296 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 69.xbar_same_source.4007537296 |
| Directory | /workspace/69.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/69.xbar_smoke.547776722 |
| Short name | T592 |
| Test name | |
| Test status | |
| Simulation time | 163397044 ps |
| CPU time | 8.28 seconds |
| Started | Jun 29 08:26:24 PM PDT 24 |
| Finished | Jun 29 08:26:33 PM PDT 24 |
| Peak memory | 574148 kb |
| Host | smart-c3584134-9956-485b-9831-329d6deb6d46 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=547776722 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 69.xbar_smoke.547776722 |
| Directory | /workspace/69.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/69.xbar_smoke_large_delays.2364107374 |
| Short name | T1740 |
| Test name | |
| Test status | |
| Simulation time | 7816295264 ps |
| CPU time | 81.2 seconds |
| Started | Jun 29 08:26:23 PM PDT 24 |
| Finished | Jun 29 08:27:44 PM PDT 24 |
| Peak memory | 574292 kb |
| Host | smart-25268269-20bd-4483-b5e3-4be6cf15ec6a |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2364107374 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 69.xbar_smoke_large_delays.2364107374 |
| Directory | /workspace/69.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/69.xbar_smoke_slow_rsp.2802026951 |
| Short name | T74 |
| Test name | |
| Test status | |
| Simulation time | 5082561493 ps |
| CPU time | 85.51 seconds |
| Started | Jun 29 08:26:25 PM PDT 24 |
| Finished | Jun 29 08:27:51 PM PDT 24 |
| Peak memory | 574332 kb |
| Host | smart-218631c3-085a-4561-9bb5-7c7d23fbcb50 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2802026951 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 69.xbar_smoke_slow_rsp.2802026951 |
| Directory | /workspace/69.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/69.xbar_smoke_zero_delays.724675668 |
| Short name | T1394 |
| Test name | |
| Test status | |
| Simulation time | 51393904 ps |
| CPU time | 6.74 seconds |
| Started | Jun 29 08:26:23 PM PDT 24 |
| Finished | Jun 29 08:26:30 PM PDT 24 |
| Peak memory | 566016 kb |
| Host | smart-e9f83e9a-7bb3-4ceb-9f76-8ad609482f7b |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=724675668 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 69.xbar_smoke_zero_delays .724675668 |
| Directory | /workspace/69.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/69.xbar_stress_all.2153656541 |
| Short name | T537 |
| Test name | |
| Test status | |
| Simulation time | 5901342917 ps |
| CPU time | 247.15 seconds |
| Started | Jun 29 08:26:35 PM PDT 24 |
| Finished | Jun 29 08:30:42 PM PDT 24 |
| Peak memory | 575528 kb |
| Host | smart-8d5dabce-b0c3-436e-9c3e-b58df78754d9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2153656541 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 69.xbar_stress_all.2153656541 |
| Directory | /workspace/69.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/69.xbar_stress_all_with_error.1840518802 |
| Short name | T1354 |
| Test name | |
| Test status | |
| Simulation time | 545873429 ps |
| CPU time | 23.33 seconds |
| Started | Jun 29 08:26:34 PM PDT 24 |
| Finished | Jun 29 08:26:58 PM PDT 24 |
| Peak memory | 573944 kb |
| Host | smart-f62b94f7-15f3-4f1e-80d0-fe0f645880bb |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1840518802 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 69.xbar_stress_all_with_error.1840518802 |
| Directory | /workspace/69.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/69.xbar_stress_all_with_rand_reset.4049512346 |
| Short name | T2762 |
| Test name | |
| Test status | |
| Simulation time | 8377041994 ps |
| CPU time | 1048.53 seconds |
| Started | Jun 29 08:26:35 PM PDT 24 |
| Finished | Jun 29 08:44:04 PM PDT 24 |
| Peak memory | 582656 kb |
| Host | smart-753c0a91-554c-4bf2-9d8d-e3f64350690d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4049512346 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 69.xbar_stress_all _with_rand_reset.4049512346 |
| Directory | /workspace/69.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/69.xbar_stress_all_with_reset_error.927447472 |
| Short name | T1398 |
| Test name | |
| Test status | |
| Simulation time | 79244287 ps |
| CPU time | 9.31 seconds |
| Started | Jun 29 08:26:34 PM PDT 24 |
| Finished | Jun 29 08:26:44 PM PDT 24 |
| Peak memory | 574232 kb |
| Host | smart-50c7b7d6-00df-436a-8dfb-e1318c289571 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=927447472 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 69.xbar_stress_all _with_reset_error.927447472 |
| Directory | /workspace/69.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/69.xbar_unmapped_addr.214633414 |
| Short name | T2243 |
| Test name | |
| Test status | |
| Simulation time | 299491426 ps |
| CPU time | 14.08 seconds |
| Started | Jun 29 08:26:24 PM PDT 24 |
| Finished | Jun 29 08:26:39 PM PDT 24 |
| Peak memory | 575328 kb |
| Host | smart-8b3d451a-37bb-4c4e-81f4-d5cf137e6157 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=214633414 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 69.xbar_unmapped_addr.214633414 |
| Directory | /workspace/69.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/7.chip_csr_rw.739148250 |
| Short name | T2496 |
| Test name | |
| Test status | |
| Simulation time | 3886190470 ps |
| CPU time | 400.63 seconds |
| Started | Jun 29 08:13:12 PM PDT 24 |
| Finished | Jun 29 08:19:53 PM PDT 24 |
| Peak memory | 596192 kb |
| Host | smart-ab00b43b-5389-47a4-a93d-504247c7ac9c |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=739148250 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.chip_csr_rw.739148250 |
| Directory | /workspace/7.chip_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/7.chip_same_csr_outstanding.2577445896 |
| Short name | T379 |
| Test name | |
| Test status | |
| Simulation time | 29144285710 ps |
| CPU time | 2990.05 seconds |
| Started | Jun 29 08:12:41 PM PDT 24 |
| Finished | Jun 29 09:02:31 PM PDT 24 |
| Peak memory | 592312 kb |
| Host | smart-b509afa6-7881-43b1-b5f9-dcec3630f909 |
| User | root |
| Command | /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +run_same_csr_outstanding +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2577445896 -assert nopostproc +UVM_TE STNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb - cm_log /dev/null -cm_name 7.chip_same_csr_outstanding.2577445896 |
| Directory | /workspace/7.chip_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/7.chip_tl_errors.1916520504 |
| Short name | T2029 |
| Test name | |
| Test status | |
| Simulation time | 2345986120 ps |
| CPU time | 92.19 seconds |
| Started | Jun 29 08:12:43 PM PDT 24 |
| Finished | Jun 29 08:14:15 PM PDT 24 |
| Peak memory | 602064 kb |
| Host | smart-d901f962-09c9-4f44-97e4-ac4dd6db0529 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1916520504 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.chip_tl_errors.1916520504 |
| Directory | /workspace/7.chip_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/7.xbar_access_same_device.3144354345 |
| Short name | T2012 |
| Test name | |
| Test status | |
| Simulation time | 3410729219 ps |
| CPU time | 144.93 seconds |
| Started | Jun 29 08:12:56 PM PDT 24 |
| Finished | Jun 29 08:15:22 PM PDT 24 |
| Peak memory | 575412 kb |
| Host | smart-e01fb30e-c9e2-40bc-8e43-534907d899dc |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3144354345 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.xbar_access_same_device. 3144354345 |
| Directory | /workspace/7.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/7.xbar_access_same_device_slow_rsp.3648148085 |
| Short name | T2128 |
| Test name | |
| Test status | |
| Simulation time | 14055178089 ps |
| CPU time | 259.91 seconds |
| Started | Jun 29 08:13:08 PM PDT 24 |
| Finished | Jun 29 08:17:29 PM PDT 24 |
| Peak memory | 575356 kb |
| Host | smart-d343ec6f-8a9c-4b07-8e6d-167021d24147 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3648148085 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.xbar_access_same_d evice_slow_rsp.3648148085 |
| Directory | /workspace/7.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/7.xbar_error_and_unmapped_addr.4218520829 |
| Short name | T2370 |
| Test name | |
| Test status | |
| Simulation time | 73009284 ps |
| CPU time | 11.65 seconds |
| Started | Jun 29 08:13:03 PM PDT 24 |
| Finished | Jun 29 08:13:15 PM PDT 24 |
| Peak memory | 573904 kb |
| Host | smart-a4cb20b5-ab0b-4d47-b7a9-db489aa566f9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4218520829 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.xbar_error_and_unmapped_addr .4218520829 |
| Directory | /workspace/7.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/7.xbar_error_random.1443155105 |
| Short name | T1821 |
| Test name | |
| Test status | |
| Simulation time | 279361956 ps |
| CPU time | 24.84 seconds |
| Started | Jun 29 08:13:06 PM PDT 24 |
| Finished | Jun 29 08:13:31 PM PDT 24 |
| Peak memory | 573920 kb |
| Host | smart-28f8aedd-9b7b-486d-a8db-e82bb33a4aaf |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1443155105 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.xbar_error_random.1443155105 |
| Directory | /workspace/7.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/7.xbar_random.791008141 |
| Short name | T2677 |
| Test name | |
| Test status | |
| Simulation time | 324513437 ps |
| CPU time | 29.56 seconds |
| Started | Jun 29 08:12:58 PM PDT 24 |
| Finished | Jun 29 08:13:28 PM PDT 24 |
| Peak memory | 574236 kb |
| Host | smart-8cb129ac-92f2-4001-9efa-2b29dc51c82e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=791008141 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.xbar_random.791008141 |
| Directory | /workspace/7.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/7.xbar_random_large_delays.289129836 |
| Short name | T1976 |
| Test name | |
| Test status | |
| Simulation time | 65090677613 ps |
| CPU time | 740.58 seconds |
| Started | Jun 29 08:13:00 PM PDT 24 |
| Finished | Jun 29 08:25:21 PM PDT 24 |
| Peak memory | 575344 kb |
| Host | smart-d5f27843-1ac4-42d8-8ede-857b2f8e9796 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=289129836 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.xbar_random_large_delays.289129836 |
| Directory | /workspace/7.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/7.xbar_random_slow_rsp.1891238751 |
| Short name | T1458 |
| Test name | |
| Test status | |
| Simulation time | 3087701978 ps |
| CPU time | 58.95 seconds |
| Started | Jun 29 08:12:59 PM PDT 24 |
| Finished | Jun 29 08:13:58 PM PDT 24 |
| Peak memory | 566096 kb |
| Host | smart-72594e4a-1a74-4578-a061-5a545ca7f3b6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1891238751 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.xbar_random_slow_rsp.1891238751 |
| Directory | /workspace/7.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/7.xbar_random_zero_delays.811221358 |
| Short name | T1539 |
| Test name | |
| Test status | |
| Simulation time | 266290752 ps |
| CPU time | 25.34 seconds |
| Started | Jun 29 08:13:04 PM PDT 24 |
| Finished | Jun 29 08:13:29 PM PDT 24 |
| Peak memory | 574216 kb |
| Host | smart-ec38e26f-3275-4c62-b180-0aa140f20f0d |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=811221358 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.xbar_random_zero_delay s.811221358 |
| Directory | /workspace/7.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/7.xbar_same_source.3037084944 |
| Short name | T1770 |
| Test name | |
| Test status | |
| Simulation time | 1257575985 ps |
| CPU time | 41.71 seconds |
| Started | Jun 29 08:13:05 PM PDT 24 |
| Finished | Jun 29 08:13:47 PM PDT 24 |
| Peak memory | 574376 kb |
| Host | smart-128f041a-ada4-4ace-b915-85d0f39051f1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3037084944 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.xbar_same_source.3037084944 |
| Directory | /workspace/7.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/7.xbar_smoke.1854516718 |
| Short name | T2574 |
| Test name | |
| Test status | |
| Simulation time | 150641741 ps |
| CPU time | 7.67 seconds |
| Started | Jun 29 08:12:49 PM PDT 24 |
| Finished | Jun 29 08:12:57 PM PDT 24 |
| Peak memory | 574252 kb |
| Host | smart-6de52440-c031-4258-904a-0974b743b018 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1854516718 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.xbar_smoke.1854516718 |
| Directory | /workspace/7.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/7.xbar_smoke_large_delays.3926165519 |
| Short name | T2060 |
| Test name | |
| Test status | |
| Simulation time | 9820082744 ps |
| CPU time | 112.59 seconds |
| Started | Jun 29 08:12:50 PM PDT 24 |
| Finished | Jun 29 08:14:43 PM PDT 24 |
| Peak memory | 566096 kb |
| Host | smart-2a7e0790-361c-4a1e-a0cc-22e0e45c3faa |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3926165519 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.xbar_smoke_large_delays.3926165519 |
| Directory | /workspace/7.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/7.xbar_smoke_slow_rsp.1061649474 |
| Short name | T1353 |
| Test name | |
| Test status | |
| Simulation time | 6150483477 ps |
| CPU time | 112.53 seconds |
| Started | Jun 29 08:12:59 PM PDT 24 |
| Finished | Jun 29 08:14:52 PM PDT 24 |
| Peak memory | 566096 kb |
| Host | smart-1df4f81f-7c31-4df2-a394-4e3c7fe9abda |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1061649474 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.xbar_smoke_slow_rsp.1061649474 |
| Directory | /workspace/7.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/7.xbar_smoke_zero_delays.3458006863 |
| Short name | T1691 |
| Test name | |
| Test status | |
| Simulation time | 54090681 ps |
| CPU time | 6.98 seconds |
| Started | Jun 29 08:12:50 PM PDT 24 |
| Finished | Jun 29 08:12:57 PM PDT 24 |
| Peak memory | 574264 kb |
| Host | smart-fd2de135-1369-4c76-9c94-70f02f4dcda5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3458006863 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.xbar_smoke_zero_delays .3458006863 |
| Directory | /workspace/7.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/7.xbar_stress_all.234280640 |
| Short name | T1525 |
| Test name | |
| Test status | |
| Simulation time | 512001101 ps |
| CPU time | 42.7 seconds |
| Started | Jun 29 08:13:13 PM PDT 24 |
| Finished | Jun 29 08:13:56 PM PDT 24 |
| Peak memory | 575420 kb |
| Host | smart-75874905-76c8-46e0-95d6-1e46feeb0bca |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=234280640 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.xbar_stress_all.234280640 |
| Directory | /workspace/7.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/7.xbar_stress_all_with_error.1073033643 |
| Short name | T1350 |
| Test name | |
| Test status | |
| Simulation time | 3610877839 ps |
| CPU time | 290.5 seconds |
| Started | Jun 29 08:13:12 PM PDT 24 |
| Finished | Jun 29 08:18:03 PM PDT 24 |
| Peak memory | 574504 kb |
| Host | smart-50a544fe-36f5-48b0-bec5-e75bb6984ab0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1073033643 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.xbar_stress_all_with_error.1073033643 |
| Directory | /workspace/7.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/7.xbar_stress_all_with_rand_reset.1867589466 |
| Short name | T1887 |
| Test name | |
| Test status | |
| Simulation time | 328492485 ps |
| CPU time | 63.26 seconds |
| Started | Jun 29 08:13:11 PM PDT 24 |
| Finished | Jun 29 08:14:15 PM PDT 24 |
| Peak memory | 575464 kb |
| Host | smart-07ef58c9-c7e5-47f6-8bd4-877b9cb31484 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1867589466 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.xbar_stress_all_ with_rand_reset.1867589466 |
| Directory | /workspace/7.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/7.xbar_stress_all_with_reset_error.2181071808 |
| Short name | T826 |
| Test name | |
| Test status | |
| Simulation time | 13766278911 ps |
| CPU time | 758.33 seconds |
| Started | Jun 29 08:13:13 PM PDT 24 |
| Finished | Jun 29 08:25:52 PM PDT 24 |
| Peak memory | 576540 kb |
| Host | smart-62ffff13-ba2e-4a1b-b85a-81e77a7d4606 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2181071808 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.xbar_stress_all _with_reset_error.2181071808 |
| Directory | /workspace/7.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/7.xbar_unmapped_addr.1322982841 |
| Short name | T1564 |
| Test name | |
| Test status | |
| Simulation time | 676002288 ps |
| CPU time | 30.06 seconds |
| Started | Jun 29 08:13:04 PM PDT 24 |
| Finished | Jun 29 08:13:34 PM PDT 24 |
| Peak memory | 575340 kb |
| Host | smart-c3f9baea-4e5d-4c1b-9f0b-610991f5080f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1322982841 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.xbar_unmapped_addr.1322982841 |
| Directory | /workspace/7.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/70.xbar_access_same_device.3458051935 |
| Short name | T2185 |
| Test name | |
| Test status | |
| Simulation time | 2761843862 ps |
| CPU time | 117.41 seconds |
| Started | Jun 29 08:26:30 PM PDT 24 |
| Finished | Jun 29 08:28:28 PM PDT 24 |
| Peak memory | 575420 kb |
| Host | smart-6a9c85fe-14ee-4c77-b2f6-54c18ef4ca84 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3458051935 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 70.xbar_access_same_device .3458051935 |
| Directory | /workspace/70.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/70.xbar_access_same_device_slow_rsp.1766790087 |
| Short name | T2206 |
| Test name | |
| Test status | |
| Simulation time | 12023804794 ps |
| CPU time | 216.95 seconds |
| Started | Jun 29 08:26:42 PM PDT 24 |
| Finished | Jun 29 08:30:19 PM PDT 24 |
| Peak memory | 574300 kb |
| Host | smart-03b8c694-3071-4751-80cc-6f46f0b0a264 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1766790087 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 70.xbar_access_same_ device_slow_rsp.1766790087 |
| Directory | /workspace/70.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/70.xbar_error_and_unmapped_addr.2974945338 |
| Short name | T1653 |
| Test name | |
| Test status | |
| Simulation time | 1053767498 ps |
| CPU time | 45.94 seconds |
| Started | Jun 29 08:26:41 PM PDT 24 |
| Finished | Jun 29 08:27:27 PM PDT 24 |
| Peak memory | 574508 kb |
| Host | smart-69a0e012-baa8-465d-b995-793e4e8f6946 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2974945338 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 70.xbar_error_and_unmapped_add r.2974945338 |
| Directory | /workspace/70.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/70.xbar_error_random.2395540129 |
| Short name | T1663 |
| Test name | |
| Test status | |
| Simulation time | 1131389352 ps |
| CPU time | 48.2 seconds |
| Started | Jun 29 08:26:42 PM PDT 24 |
| Finished | Jun 29 08:27:31 PM PDT 24 |
| Peak memory | 574492 kb |
| Host | smart-6e3f079f-0e8a-4751-a1e6-9d935bafaf7a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2395540129 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 70.xbar_error_random.2395540129 |
| Directory | /workspace/70.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/70.xbar_random.1132761886 |
| Short name | T2869 |
| Test name | |
| Test status | |
| Simulation time | 2277057723 ps |
| CPU time | 85.22 seconds |
| Started | Jun 29 08:26:31 PM PDT 24 |
| Finished | Jun 29 08:27:56 PM PDT 24 |
| Peak memory | 574328 kb |
| Host | smart-9ccd364b-3980-48b5-ac1e-0b993a0e4972 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1132761886 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 70.xbar_random.1132761886 |
| Directory | /workspace/70.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/70.xbar_random_large_delays.652004027 |
| Short name | T606 |
| Test name | |
| Test status | |
| Simulation time | 90990145330 ps |
| CPU time | 970.7 seconds |
| Started | Jun 29 08:26:31 PM PDT 24 |
| Finished | Jun 29 08:42:42 PM PDT 24 |
| Peak memory | 575440 kb |
| Host | smart-260bbe77-a2d6-4139-b630-ce4ac826aafc |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=652004027 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 70.xbar_random_large_delays.652004027 |
| Directory | /workspace/70.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/70.xbar_random_slow_rsp.129778366 |
| Short name | T2397 |
| Test name | |
| Test status | |
| Simulation time | 7927551667 ps |
| CPU time | 127.49 seconds |
| Started | Jun 29 08:26:34 PM PDT 24 |
| Finished | Jun 29 08:28:42 PM PDT 24 |
| Peak memory | 575336 kb |
| Host | smart-59b909b1-d358-4f01-94c6-b85c4a86c0cc |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=129778366 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 70.xbar_random_slow_rsp.129778366 |
| Directory | /workspace/70.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/70.xbar_random_zero_delays.462055122 |
| Short name | T2341 |
| Test name | |
| Test status | |
| Simulation time | 490463354 ps |
| CPU time | 50.49 seconds |
| Started | Jun 29 08:26:32 PM PDT 24 |
| Finished | Jun 29 08:27:23 PM PDT 24 |
| Peak memory | 575348 kb |
| Host | smart-43b6f728-6c1d-49ef-9d82-72aa623885c8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=462055122 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 70.xbar_random_zero_dela ys.462055122 |
| Directory | /workspace/70.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/70.xbar_same_source.2149540699 |
| Short name | T1831 |
| Test name | |
| Test status | |
| Simulation time | 91799213 ps |
| CPU time | 10.6 seconds |
| Started | Jun 29 08:26:42 PM PDT 24 |
| Finished | Jun 29 08:26:53 PM PDT 24 |
| Peak memory | 575276 kb |
| Host | smart-f9db25cd-b321-4e5e-afaf-139daa7c582b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2149540699 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 70.xbar_same_source.2149540699 |
| Directory | /workspace/70.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/70.xbar_smoke.2575415971 |
| Short name | T1306 |
| Test name | |
| Test status | |
| Simulation time | 206684001 ps |
| CPU time | 9.13 seconds |
| Started | Jun 29 08:26:32 PM PDT 24 |
| Finished | Jun 29 08:26:42 PM PDT 24 |
| Peak memory | 565976 kb |
| Host | smart-747a5116-93d8-4fda-8b6d-9d635026f44d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2575415971 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 70.xbar_smoke.2575415971 |
| Directory | /workspace/70.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/70.xbar_smoke_large_delays.893936921 |
| Short name | T1288 |
| Test name | |
| Test status | |
| Simulation time | 7818571871 ps |
| CPU time | 86.78 seconds |
| Started | Jun 29 08:26:34 PM PDT 24 |
| Finished | Jun 29 08:28:01 PM PDT 24 |
| Peak memory | 574292 kb |
| Host | smart-e8204a89-e839-473c-ae4b-c2a0b7e72159 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=893936921 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 70.xbar_smoke_large_delays.893936921 |
| Directory | /workspace/70.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/70.xbar_smoke_slow_rsp.311534192 |
| Short name | T1867 |
| Test name | |
| Test status | |
| Simulation time | 3036854752 ps |
| CPU time | 52.74 seconds |
| Started | Jun 29 08:26:33 PM PDT 24 |
| Finished | Jun 29 08:27:26 PM PDT 24 |
| Peak memory | 574108 kb |
| Host | smart-479ad50a-7b6d-45f9-acf8-4f80153c6348 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=311534192 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 70.xbar_smoke_slow_rsp.311534192 |
| Directory | /workspace/70.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/70.xbar_smoke_zero_delays.3021783381 |
| Short name | T2567 |
| Test name | |
| Test status | |
| Simulation time | 48407767 ps |
| CPU time | 6.43 seconds |
| Started | Jun 29 08:26:32 PM PDT 24 |
| Finished | Jun 29 08:26:39 PM PDT 24 |
| Peak memory | 574248 kb |
| Host | smart-2153f22c-e9e5-4d1e-951e-64456d49887d |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3021783381 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 70.xbar_smoke_zero_delay s.3021783381 |
| Directory | /workspace/70.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/70.xbar_stress_all.3846872749 |
| Short name | T605 |
| Test name | |
| Test status | |
| Simulation time | 1405687136 ps |
| CPU time | 54.48 seconds |
| Started | Jun 29 08:26:38 PM PDT 24 |
| Finished | Jun 29 08:27:33 PM PDT 24 |
| Peak memory | 575324 kb |
| Host | smart-468c59c8-9ad3-4d92-b7ac-8f7473929b18 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3846872749 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 70.xbar_stress_all.3846872749 |
| Directory | /workspace/70.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/70.xbar_stress_all_with_error.1614998474 |
| Short name | T1494 |
| Test name | |
| Test status | |
| Simulation time | 8040463969 ps |
| CPU time | 338.08 seconds |
| Started | Jun 29 08:26:40 PM PDT 24 |
| Finished | Jun 29 08:32:18 PM PDT 24 |
| Peak memory | 574472 kb |
| Host | smart-94e4fb8a-61af-41f2-a32d-d3f93e304497 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1614998474 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 70.xbar_stress_all_with_error.1614998474 |
| Directory | /workspace/70.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/70.xbar_stress_all_with_rand_reset.415608619 |
| Short name | T825 |
| Test name | |
| Test status | |
| Simulation time | 737482622 ps |
| CPU time | 205.89 seconds |
| Started | Jun 29 08:26:39 PM PDT 24 |
| Finished | Jun 29 08:30:05 PM PDT 24 |
| Peak memory | 575428 kb |
| Host | smart-cbf67b53-ce21-4887-b76c-405c091630c7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=415608619 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_res et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 70.xbar_stress_all_ with_rand_reset.415608619 |
| Directory | /workspace/70.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/70.xbar_stress_all_with_reset_error.3334458879 |
| Short name | T1676 |
| Test name | |
| Test status | |
| Simulation time | 64062591 ps |
| CPU time | 62.35 seconds |
| Started | Jun 29 08:26:39 PM PDT 24 |
| Finished | Jun 29 08:27:42 PM PDT 24 |
| Peak memory | 576500 kb |
| Host | smart-a484adb3-bb96-4a78-b29f-a4d8a444fc9a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3334458879 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 70.xbar_stress_al l_with_reset_error.3334458879 |
| Directory | /workspace/70.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/70.xbar_unmapped_addr.2564194895 |
| Short name | T2280 |
| Test name | |
| Test status | |
| Simulation time | 150714418 ps |
| CPU time | 9.35 seconds |
| Started | Jun 29 08:26:42 PM PDT 24 |
| Finished | Jun 29 08:26:52 PM PDT 24 |
| Peak memory | 566056 kb |
| Host | smart-4ddb5628-6463-4806-bb8c-c2c39f6a838f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2564194895 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 70.xbar_unmapped_addr.2564194895 |
| Directory | /workspace/70.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/71.xbar_access_same_device.3739607560 |
| Short name | T2040 |
| Test name | |
| Test status | |
| Simulation time | 889311530 ps |
| CPU time | 36.83 seconds |
| Started | Jun 29 08:26:47 PM PDT 24 |
| Finished | Jun 29 08:27:24 PM PDT 24 |
| Peak memory | 574236 kb |
| Host | smart-c3262e8e-b13d-4014-b338-b1014e53cf77 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3739607560 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 71.xbar_access_same_device .3739607560 |
| Directory | /workspace/71.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/71.xbar_error_and_unmapped_addr.1047982464 |
| Short name | T1391 |
| Test name | |
| Test status | |
| Simulation time | 320409879 ps |
| CPU time | 36.88 seconds |
| Started | Jun 29 08:26:48 PM PDT 24 |
| Finished | Jun 29 08:27:25 PM PDT 24 |
| Peak memory | 574496 kb |
| Host | smart-7db6fa48-20c5-42cc-aa98-e527b33e0343 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1047982464 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 71.xbar_error_and_unmapped_add r.1047982464 |
| Directory | /workspace/71.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/71.xbar_error_random.2203384729 |
| Short name | T1322 |
| Test name | |
| Test status | |
| Simulation time | 520052589 ps |
| CPU time | 45.5 seconds |
| Started | Jun 29 08:26:47 PM PDT 24 |
| Finished | Jun 29 08:27:33 PM PDT 24 |
| Peak memory | 574256 kb |
| Host | smart-3262ce9c-8a3e-4a99-837e-d6374d15307e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2203384729 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 71.xbar_error_random.2203384729 |
| Directory | /workspace/71.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/71.xbar_random.3756755240 |
| Short name | T2045 |
| Test name | |
| Test status | |
| Simulation time | 103103915 ps |
| CPU time | 12.62 seconds |
| Started | Jun 29 08:26:50 PM PDT 24 |
| Finished | Jun 29 08:27:03 PM PDT 24 |
| Peak memory | 575308 kb |
| Host | smart-3ad36058-8043-4764-9fff-e6b7f8435f26 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3756755240 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 71.xbar_random.3756755240 |
| Directory | /workspace/71.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/71.xbar_random_large_delays.2467449260 |
| Short name | T2543 |
| Test name | |
| Test status | |
| Simulation time | 60226491370 ps |
| CPU time | 646.41 seconds |
| Started | Jun 29 08:26:50 PM PDT 24 |
| Finished | Jun 29 08:37:36 PM PDT 24 |
| Peak memory | 574300 kb |
| Host | smart-8db0a194-aaf6-4cb8-b0c7-d013610be90f |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2467449260 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 71.xbar_random_large_delays.2467449260 |
| Directory | /workspace/71.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/71.xbar_random_slow_rsp.1653851142 |
| Short name | T602 |
| Test name | |
| Test status | |
| Simulation time | 67431296385 ps |
| CPU time | 1148.28 seconds |
| Started | Jun 29 08:26:49 PM PDT 24 |
| Finished | Jun 29 08:45:57 PM PDT 24 |
| Peak memory | 574328 kb |
| Host | smart-5abc3d8f-86f9-48bf-9584-d785f52398b4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1653851142 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 71.xbar_random_slow_rsp.1653851142 |
| Directory | /workspace/71.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/71.xbar_random_zero_delays.66665183 |
| Short name | T1886 |
| Test name | |
| Test status | |
| Simulation time | 586919624 ps |
| CPU time | 52.21 seconds |
| Started | Jun 29 08:26:50 PM PDT 24 |
| Finished | Jun 29 08:27:42 PM PDT 24 |
| Peak memory | 575340 kb |
| Host | smart-7076afbe-74ea-40aa-b5ff-b0f33dfb331f |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66665183 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 71.xbar_random_zero_delay s.66665183 |
| Directory | /workspace/71.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/71.xbar_same_source.2428759387 |
| Short name | T1557 |
| Test name | |
| Test status | |
| Simulation time | 2524340457 ps |
| CPU time | 80.86 seconds |
| Started | Jun 29 08:26:49 PM PDT 24 |
| Finished | Jun 29 08:28:10 PM PDT 24 |
| Peak memory | 574260 kb |
| Host | smart-0a4dcf9d-4560-4e52-9276-3846fc4bc7ec |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2428759387 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 71.xbar_same_source.2428759387 |
| Directory | /workspace/71.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/71.xbar_smoke.393444414 |
| Short name | T1977 |
| Test name | |
| Test status | |
| Simulation time | 225925970 ps |
| CPU time | 10.89 seconds |
| Started | Jun 29 08:26:39 PM PDT 24 |
| Finished | Jun 29 08:26:50 PM PDT 24 |
| Peak memory | 574240 kb |
| Host | smart-4fcd9191-1166-4685-bbc4-7ca4fabce2cf |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=393444414 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 71.xbar_smoke.393444414 |
| Directory | /workspace/71.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/71.xbar_smoke_large_delays.1043676365 |
| Short name | T1365 |
| Test name | |
| Test status | |
| Simulation time | 6238147518 ps |
| CPU time | 70.95 seconds |
| Started | Jun 29 08:26:47 PM PDT 24 |
| Finished | Jun 29 08:27:58 PM PDT 24 |
| Peak memory | 574320 kb |
| Host | smart-181c2c55-2f8a-4ebb-abc8-2a612514e96f |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1043676365 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 71.xbar_smoke_large_delays.1043676365 |
| Directory | /workspace/71.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/71.xbar_smoke_slow_rsp.455287323 |
| Short name | T2835 |
| Test name | |
| Test status | |
| Simulation time | 3100083242 ps |
| CPU time | 56.52 seconds |
| Started | Jun 29 08:26:49 PM PDT 24 |
| Finished | Jun 29 08:27:46 PM PDT 24 |
| Peak memory | 566068 kb |
| Host | smart-530ca519-622c-42c0-85d9-c83be4647db1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=455287323 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 71.xbar_smoke_slow_rsp.455287323 |
| Directory | /workspace/71.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/71.xbar_smoke_zero_delays.1923224349 |
| Short name | T1289 |
| Test name | |
| Test status | |
| Simulation time | 42008323 ps |
| CPU time | 6.38 seconds |
| Started | Jun 29 08:26:39 PM PDT 24 |
| Finished | Jun 29 08:26:46 PM PDT 24 |
| Peak memory | 574264 kb |
| Host | smart-6477b610-dedb-4e5f-9fb3-24cf4e20d678 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1923224349 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 71.xbar_smoke_zero_delay s.1923224349 |
| Directory | /workspace/71.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/71.xbar_stress_all.2241392755 |
| Short name | T628 |
| Test name | |
| Test status | |
| Simulation time | 5166481644 ps |
| CPU time | 214.11 seconds |
| Started | Jun 29 08:26:51 PM PDT 24 |
| Finished | Jun 29 08:30:26 PM PDT 24 |
| Peak memory | 575532 kb |
| Host | smart-285cee35-17b0-4f58-94d1-2272682528ee |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2241392755 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 71.xbar_stress_all.2241392755 |
| Directory | /workspace/71.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/71.xbar_stress_all_with_error.839911872 |
| Short name | T2863 |
| Test name | |
| Test status | |
| Simulation time | 12596417509 ps |
| CPU time | 462.45 seconds |
| Started | Jun 29 08:26:48 PM PDT 24 |
| Finished | Jun 29 08:34:31 PM PDT 24 |
| Peak memory | 574496 kb |
| Host | smart-b82bbd80-fa4f-4f3b-b122-b5a67ae4ba0b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=839911872 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 71.xbar_stress_all_with_error.839911872 |
| Directory | /workspace/71.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/71.xbar_stress_all_with_reset_error.2121604785 |
| Short name | T2820 |
| Test name | |
| Test status | |
| Simulation time | 385934155 ps |
| CPU time | 142.42 seconds |
| Started | Jun 29 08:26:48 PM PDT 24 |
| Finished | Jun 29 08:29:10 PM PDT 24 |
| Peak memory | 574608 kb |
| Host | smart-24d84058-7838-4a74-b49a-eb4b527634c5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2121604785 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 71.xbar_stress_al l_with_reset_error.2121604785 |
| Directory | /workspace/71.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/71.xbar_unmapped_addr.1585973996 |
| Short name | T1985 |
| Test name | |
| Test status | |
| Simulation time | 747512080 ps |
| CPU time | 36.7 seconds |
| Started | Jun 29 08:26:47 PM PDT 24 |
| Finished | Jun 29 08:27:24 PM PDT 24 |
| Peak memory | 575356 kb |
| Host | smart-5e0c117a-ea8b-4406-9f5a-d82cc5e3fa0d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1585973996 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 71.xbar_unmapped_addr.1585973996 |
| Directory | /workspace/71.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/72.xbar_access_same_device.717708383 |
| Short name | T2173 |
| Test name | |
| Test status | |
| Simulation time | 3347457469 ps |
| CPU time | 152.99 seconds |
| Started | Jun 29 08:26:54 PM PDT 24 |
| Finished | Jun 29 08:29:28 PM PDT 24 |
| Peak memory | 575424 kb |
| Host | smart-366b4e72-bb2a-44f4-97de-259974882598 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=717708383 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 72.xbar_access_same_device. 717708383 |
| Directory | /workspace/72.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/72.xbar_access_same_device_slow_rsp.2359510476 |
| Short name | T569 |
| Test name | |
| Test status | |
| Simulation time | 75011396604 ps |
| CPU time | 1314.48 seconds |
| Started | Jun 29 08:26:55 PM PDT 24 |
| Finished | Jun 29 08:48:49 PM PDT 24 |
| Peak memory | 575472 kb |
| Host | smart-19738547-39e8-4214-8299-5ffbf9e5dc0c |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2359510476 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 72.xbar_access_same_ device_slow_rsp.2359510476 |
| Directory | /workspace/72.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/72.xbar_error_and_unmapped_addr.3479847290 |
| Short name | T1344 |
| Test name | |
| Test status | |
| Simulation time | 84434537 ps |
| CPU time | 7.71 seconds |
| Started | Jun 29 08:26:55 PM PDT 24 |
| Finished | Jun 29 08:27:03 PM PDT 24 |
| Peak memory | 565708 kb |
| Host | smart-036dd56b-22d3-4523-9d8b-af9da0254696 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3479847290 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 72.xbar_error_and_unmapped_add r.3479847290 |
| Directory | /workspace/72.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/72.xbar_error_random.1353913201 |
| Short name | T2758 |
| Test name | |
| Test status | |
| Simulation time | 564327071 ps |
| CPU time | 49.37 seconds |
| Started | Jun 29 08:26:57 PM PDT 24 |
| Finished | Jun 29 08:27:46 PM PDT 24 |
| Peak memory | 574232 kb |
| Host | smart-70c2e915-d06c-4f0b-a0c1-286a4e101963 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1353913201 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 72.xbar_error_random.1353913201 |
| Directory | /workspace/72.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/72.xbar_random.1064837834 |
| Short name | T1940 |
| Test name | |
| Test status | |
| Simulation time | 164697187 ps |
| CPU time | 15.07 seconds |
| Started | Jun 29 08:26:55 PM PDT 24 |
| Finished | Jun 29 08:27:11 PM PDT 24 |
| Peak memory | 574228 kb |
| Host | smart-068ad569-aaa7-4830-8fcb-b7dcd0b7f9e6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1064837834 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 72.xbar_random.1064837834 |
| Directory | /workspace/72.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/72.xbar_random_large_delays.108864189 |
| Short name | T1991 |
| Test name | |
| Test status | |
| Simulation time | 8401692151 ps |
| CPU time | 90.74 seconds |
| Started | Jun 29 08:26:55 PM PDT 24 |
| Finished | Jun 29 08:28:26 PM PDT 24 |
| Peak memory | 574364 kb |
| Host | smart-26b13931-d7c7-4baf-ae86-fce7b9f1c23f |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=108864189 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 72.xbar_random_large_delays.108864189 |
| Directory | /workspace/72.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/72.xbar_random_slow_rsp.3314658105 |
| Short name | T2113 |
| Test name | |
| Test status | |
| Simulation time | 38875990890 ps |
| CPU time | 670.2 seconds |
| Started | Jun 29 08:26:55 PM PDT 24 |
| Finished | Jun 29 08:38:06 PM PDT 24 |
| Peak memory | 575388 kb |
| Host | smart-34e33420-e255-4123-8003-453f2b7deeef |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3314658105 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 72.xbar_random_slow_rsp.3314658105 |
| Directory | /workspace/72.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/72.xbar_random_zero_delays.3681792766 |
| Short name | T1573 |
| Test name | |
| Test status | |
| Simulation time | 567320591 ps |
| CPU time | 55.83 seconds |
| Started | Jun 29 08:26:55 PM PDT 24 |
| Finished | Jun 29 08:27:52 PM PDT 24 |
| Peak memory | 575300 kb |
| Host | smart-0c23c4ef-d9c0-4d19-bf0a-c5458b127e9f |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3681792766 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 72.xbar_random_zero_del ays.3681792766 |
| Directory | /workspace/72.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/72.xbar_same_source.2962375113 |
| Short name | T2219 |
| Test name | |
| Test status | |
| Simulation time | 1308716524 ps |
| CPU time | 43.54 seconds |
| Started | Jun 29 08:26:56 PM PDT 24 |
| Finished | Jun 29 08:27:40 PM PDT 24 |
| Peak memory | 575276 kb |
| Host | smart-f98a9624-c2ea-49bc-ab47-0c6432f25d3a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2962375113 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 72.xbar_same_source.2962375113 |
| Directory | /workspace/72.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/72.xbar_smoke.3408364113 |
| Short name | T1373 |
| Test name | |
| Test status | |
| Simulation time | 40616295 ps |
| CPU time | 6.15 seconds |
| Started | Jun 29 08:26:48 PM PDT 24 |
| Finished | Jun 29 08:26:55 PM PDT 24 |
| Peak memory | 566028 kb |
| Host | smart-046b8b23-e8e9-44d8-b413-f21c6fcaa7e9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3408364113 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 72.xbar_smoke.3408364113 |
| Directory | /workspace/72.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/72.xbar_smoke_large_delays.911325659 |
| Short name | T1645 |
| Test name | |
| Test status | |
| Simulation time | 9896857945 ps |
| CPU time | 101.37 seconds |
| Started | Jun 29 08:26:56 PM PDT 24 |
| Finished | Jun 29 08:28:38 PM PDT 24 |
| Peak memory | 574308 kb |
| Host | smart-43927488-540e-44d6-b456-98e9798c31e9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=911325659 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 72.xbar_smoke_large_delays.911325659 |
| Directory | /workspace/72.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/72.xbar_smoke_slow_rsp.1446816222 |
| Short name | T2727 |
| Test name | |
| Test status | |
| Simulation time | 5556455757 ps |
| CPU time | 96.1 seconds |
| Started | Jun 29 08:26:56 PM PDT 24 |
| Finished | Jun 29 08:28:32 PM PDT 24 |
| Peak memory | 574312 kb |
| Host | smart-31ecccec-daed-4ee6-ba10-542ad9cd4dcd |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1446816222 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 72.xbar_smoke_slow_rsp.1446816222 |
| Directory | /workspace/72.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/72.xbar_smoke_zero_delays.1015319806 |
| Short name | T2689 |
| Test name | |
| Test status | |
| Simulation time | 54748855 ps |
| CPU time | 7.1 seconds |
| Started | Jun 29 08:26:46 PM PDT 24 |
| Finished | Jun 29 08:26:54 PM PDT 24 |
| Peak memory | 574244 kb |
| Host | smart-bc824693-0d84-4ae3-a436-cd187ff6266b |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1015319806 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 72.xbar_smoke_zero_delay s.1015319806 |
| Directory | /workspace/72.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/72.xbar_stress_all.1561749777 |
| Short name | T2215 |
| Test name | |
| Test status | |
| Simulation time | 9692008427 ps |
| CPU time | 360.6 seconds |
| Started | Jun 29 08:26:56 PM PDT 24 |
| Finished | Jun 29 08:32:57 PM PDT 24 |
| Peak memory | 575504 kb |
| Host | smart-00c61109-8cbf-4fa2-a7bd-6c37e1e17789 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1561749777 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 72.xbar_stress_all.1561749777 |
| Directory | /workspace/72.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/72.xbar_stress_all_with_error.3884890735 |
| Short name | T2506 |
| Test name | |
| Test status | |
| Simulation time | 4208764291 ps |
| CPU time | 149.72 seconds |
| Started | Jun 29 08:27:08 PM PDT 24 |
| Finished | Jun 29 08:29:38 PM PDT 24 |
| Peak memory | 574392 kb |
| Host | smart-8baa32fc-1a62-45f4-9e83-a8d364f45e33 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3884890735 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 72.xbar_stress_all_with_error.3884890735 |
| Directory | /workspace/72.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/72.xbar_stress_all_with_rand_reset.873483249 |
| Short name | T1650 |
| Test name | |
| Test status | |
| Simulation time | 249318615 ps |
| CPU time | 87 seconds |
| Started | Jun 29 08:26:56 PM PDT 24 |
| Finished | Jun 29 08:28:23 PM PDT 24 |
| Peak memory | 575452 kb |
| Host | smart-20169423-c28e-44a3-aa13-eb79c3088e54 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=873483249 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_res et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 72.xbar_stress_all_ with_rand_reset.873483249 |
| Directory | /workspace/72.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/72.xbar_stress_all_with_reset_error.4044840967 |
| Short name | T2426 |
| Test name | |
| Test status | |
| Simulation time | 523053996 ps |
| CPU time | 164.03 seconds |
| Started | Jun 29 08:27:04 PM PDT 24 |
| Finished | Jun 29 08:29:48 PM PDT 24 |
| Peak memory | 574676 kb |
| Host | smart-aa90a0b4-67c1-41fa-a43e-4292879c4b3d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4044840967 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 72.xbar_stress_al l_with_reset_error.4044840967 |
| Directory | /workspace/72.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/72.xbar_unmapped_addr.2804375112 |
| Short name | T2403 |
| Test name | |
| Test status | |
| Simulation time | 23025640 ps |
| CPU time | 6.09 seconds |
| Started | Jun 29 08:26:54 PM PDT 24 |
| Finished | Jun 29 08:27:00 PM PDT 24 |
| Peak memory | 574164 kb |
| Host | smart-492a2354-89ff-465a-bf6e-ea0b9b68d324 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2804375112 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 72.xbar_unmapped_addr.2804375112 |
| Directory | /workspace/72.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/73.xbar_access_same_device.3546018172 |
| Short name | T1554 |
| Test name | |
| Test status | |
| Simulation time | 174753591 ps |
| CPU time | 13.11 seconds |
| Started | Jun 29 08:27:03 PM PDT 24 |
| Finished | Jun 29 08:27:16 PM PDT 24 |
| Peak memory | 575184 kb |
| Host | smart-847bfc38-1ec8-4c26-9b63-5ab190e0e5b6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3546018172 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 73.xbar_access_same_device .3546018172 |
| Directory | /workspace/73.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/73.xbar_access_same_device_slow_rsp.3664347788 |
| Short name | T2216 |
| Test name | |
| Test status | |
| Simulation time | 19880828482 ps |
| CPU time | 375.89 seconds |
| Started | Jun 29 08:27:04 PM PDT 24 |
| Finished | Jun 29 08:33:20 PM PDT 24 |
| Peak memory | 575376 kb |
| Host | smart-0179dbf5-0d22-4ddf-8504-49133f274e5e |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3664347788 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 73.xbar_access_same_ device_slow_rsp.3664347788 |
| Directory | /workspace/73.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/73.xbar_error_and_unmapped_addr.1004872807 |
| Short name | T1896 |
| Test name | |
| Test status | |
| Simulation time | 195451952 ps |
| CPU time | 22.83 seconds |
| Started | Jun 29 08:27:13 PM PDT 24 |
| Finished | Jun 29 08:27:36 PM PDT 24 |
| Peak memory | 574512 kb |
| Host | smart-ce1996d6-dea6-476c-b8a0-7e9eeddf7eca |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1004872807 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 73.xbar_error_and_unmapped_add r.1004872807 |
| Directory | /workspace/73.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/73.xbar_error_random.756639842 |
| Short name | T2477 |
| Test name | |
| Test status | |
| Simulation time | 2401772358 ps |
| CPU time | 90.75 seconds |
| Started | Jun 29 08:27:03 PM PDT 24 |
| Finished | Jun 29 08:28:34 PM PDT 24 |
| Peak memory | 574344 kb |
| Host | smart-6ebd5002-850a-4d52-acf1-f88bfb73a665 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=756639842 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 73.xbar_error_random.756639842 |
| Directory | /workspace/73.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/73.xbar_random.1668365919 |
| Short name | T1628 |
| Test name | |
| Test status | |
| Simulation time | 2192540830 ps |
| CPU time | 73.08 seconds |
| Started | Jun 29 08:27:11 PM PDT 24 |
| Finished | Jun 29 08:28:24 PM PDT 24 |
| Peak memory | 574280 kb |
| Host | smart-13462420-78b2-4caf-b159-0ca405ec6fb9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1668365919 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 73.xbar_random.1668365919 |
| Directory | /workspace/73.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/73.xbar_random_large_delays.1649787140 |
| Short name | T1360 |
| Test name | |
| Test status | |
| Simulation time | 17198310124 ps |
| CPU time | 187.55 seconds |
| Started | Jun 29 08:27:08 PM PDT 24 |
| Finished | Jun 29 08:30:15 PM PDT 24 |
| Peak memory | 574324 kb |
| Host | smart-cc2a802c-46d2-48a9-8279-beed046fa346 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1649787140 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 73.xbar_random_large_delays.1649787140 |
| Directory | /workspace/73.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/73.xbar_random_slow_rsp.2457334251 |
| Short name | T570 |
| Test name | |
| Test status | |
| Simulation time | 51641836903 ps |
| CPU time | 858.98 seconds |
| Started | Jun 29 08:27:04 PM PDT 24 |
| Finished | Jun 29 08:41:24 PM PDT 24 |
| Peak memory | 574332 kb |
| Host | smart-e46a785d-7e76-4a77-8cb3-235d8e004b83 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2457334251 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 73.xbar_random_slow_rsp.2457334251 |
| Directory | /workspace/73.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/73.xbar_random_zero_delays.496273639 |
| Short name | T2142 |
| Test name | |
| Test status | |
| Simulation time | 529553309 ps |
| CPU time | 47.66 seconds |
| Started | Jun 29 08:27:05 PM PDT 24 |
| Finished | Jun 29 08:27:53 PM PDT 24 |
| Peak memory | 575316 kb |
| Host | smart-f6ffc21e-76f7-4ab8-ab43-99420f9831cf |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=496273639 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 73.xbar_random_zero_dela ys.496273639 |
| Directory | /workspace/73.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/73.xbar_same_source.913968680 |
| Short name | T1604 |
| Test name | |
| Test status | |
| Simulation time | 2519006496 ps |
| CPU time | 79.75 seconds |
| Started | Jun 29 08:27:04 PM PDT 24 |
| Finished | Jun 29 08:28:24 PM PDT 24 |
| Peak memory | 575356 kb |
| Host | smart-b4e1e372-133e-468a-add6-45fe878e0734 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=913968680 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 73.xbar_same_source.913968680 |
| Directory | /workspace/73.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/73.xbar_smoke.239413884 |
| Short name | T1296 |
| Test name | |
| Test status | |
| Simulation time | 165224142 ps |
| CPU time | 8.46 seconds |
| Started | Jun 29 08:27:07 PM PDT 24 |
| Finished | Jun 29 08:27:15 PM PDT 24 |
| Peak memory | 574224 kb |
| Host | smart-f8c7faf8-5b83-4af0-b968-9f83ea42c3c9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=239413884 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 73.xbar_smoke.239413884 |
| Directory | /workspace/73.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/73.xbar_smoke_large_delays.572085318 |
| Short name | T2866 |
| Test name | |
| Test status | |
| Simulation time | 8007778950 ps |
| CPU time | 80.71 seconds |
| Started | Jun 29 08:27:05 PM PDT 24 |
| Finished | Jun 29 08:28:26 PM PDT 24 |
| Peak memory | 574316 kb |
| Host | smart-0fe36598-5847-4770-a2da-2d9893cffd0b |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=572085318 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 73.xbar_smoke_large_delays.572085318 |
| Directory | /workspace/73.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/73.xbar_smoke_slow_rsp.1473048237 |
| Short name | T1596 |
| Test name | |
| Test status | |
| Simulation time | 5585312523 ps |
| CPU time | 99.92 seconds |
| Started | Jun 29 08:27:06 PM PDT 24 |
| Finished | Jun 29 08:28:46 PM PDT 24 |
| Peak memory | 566040 kb |
| Host | smart-ee8bf025-9427-4a5e-9eed-72bc874f7128 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1473048237 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 73.xbar_smoke_slow_rsp.1473048237 |
| Directory | /workspace/73.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/73.xbar_smoke_zero_delays.788758482 |
| Short name | T1297 |
| Test name | |
| Test status | |
| Simulation time | 55679015 ps |
| CPU time | 7.96 seconds |
| Started | Jun 29 08:27:06 PM PDT 24 |
| Finished | Jun 29 08:27:15 PM PDT 24 |
| Peak memory | 574364 kb |
| Host | smart-0df762f7-1cb0-4512-87d5-306852d2eb22 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=788758482 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 73.xbar_smoke_zero_delays .788758482 |
| Directory | /workspace/73.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/73.xbar_stress_all.1688645813 |
| Short name | T1723 |
| Test name | |
| Test status | |
| Simulation time | 1773509843 ps |
| CPU time | 158.84 seconds |
| Started | Jun 29 08:27:13 PM PDT 24 |
| Finished | Jun 29 08:29:52 PM PDT 24 |
| Peak memory | 575412 kb |
| Host | smart-e3ec0446-9994-41e4-8cf7-bb5f1d60f169 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1688645813 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 73.xbar_stress_all.1688645813 |
| Directory | /workspace/73.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/73.xbar_stress_all_with_error.339493870 |
| Short name | T2220 |
| Test name | |
| Test status | |
| Simulation time | 7451904867 ps |
| CPU time | 306.6 seconds |
| Started | Jun 29 08:27:13 PM PDT 24 |
| Finished | Jun 29 08:32:20 PM PDT 24 |
| Peak memory | 574460 kb |
| Host | smart-d9c6bbcc-c7aa-4cf8-9371-506f672a4613 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=339493870 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 73.xbar_stress_all_with_error.339493870 |
| Directory | /workspace/73.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/73.xbar_stress_all_with_rand_reset.1550487030 |
| Short name | T400 |
| Test name | |
| Test status | |
| Simulation time | 5401167027 ps |
| CPU time | 626.27 seconds |
| Started | Jun 29 08:27:16 PM PDT 24 |
| Finished | Jun 29 08:37:43 PM PDT 24 |
| Peak memory | 575516 kb |
| Host | smart-3ef45745-4fb5-413d-92fa-983b471ccb46 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1550487030 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 73.xbar_stress_all _with_rand_reset.1550487030 |
| Directory | /workspace/73.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/73.xbar_stress_all_with_reset_error.2056850060 |
| Short name | T2339 |
| Test name | |
| Test status | |
| Simulation time | 121310920 ps |
| CPU time | 36.32 seconds |
| Started | Jun 29 08:27:12 PM PDT 24 |
| Finished | Jun 29 08:27:48 PM PDT 24 |
| Peak memory | 574656 kb |
| Host | smart-8d881f2f-bb46-4604-bbd7-dba1e455b42c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2056850060 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 73.xbar_stress_al l_with_reset_error.2056850060 |
| Directory | /workspace/73.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/73.xbar_unmapped_addr.2174912637 |
| Short name | T2231 |
| Test name | |
| Test status | |
| Simulation time | 877864506 ps |
| CPU time | 37.09 seconds |
| Started | Jun 29 08:27:11 PM PDT 24 |
| Finished | Jun 29 08:27:49 PM PDT 24 |
| Peak memory | 574280 kb |
| Host | smart-e4f15b32-ce23-4c50-9eac-0db1b989c030 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2174912637 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 73.xbar_unmapped_addr.2174912637 |
| Directory | /workspace/73.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/74.xbar_access_same_device.8133077 |
| Short name | T2149 |
| Test name | |
| Test status | |
| Simulation time | 314505664 ps |
| CPU time | 33.22 seconds |
| Started | Jun 29 08:27:19 PM PDT 24 |
| Finished | Jun 29 08:27:53 PM PDT 24 |
| Peak memory | 575292 kb |
| Host | smart-13daac95-f34b-4f05-a3d1-6aedfb3e206b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=8133077 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 74.xbar_access_same_device.8133077 |
| Directory | /workspace/74.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/74.xbar_access_same_device_slow_rsp.510617313 |
| Short name | T2486 |
| Test name | |
| Test status | |
| Simulation time | 74529302630 ps |
| CPU time | 1244.89 seconds |
| Started | Jun 29 08:27:19 PM PDT 24 |
| Finished | Jun 29 08:48:05 PM PDT 24 |
| Peak memory | 574364 kb |
| Host | smart-e496c41e-8fc9-4fda-88c9-da9350052407 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=510617313 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 74.xbar_access_same_d evice_slow_rsp.510617313 |
| Directory | /workspace/74.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/74.xbar_error_and_unmapped_addr.3756625472 |
| Short name | T1597 |
| Test name | |
| Test status | |
| Simulation time | 129427859 ps |
| CPU time | 17.05 seconds |
| Started | Jun 29 08:27:21 PM PDT 24 |
| Finished | Jun 29 08:27:39 PM PDT 24 |
| Peak memory | 574484 kb |
| Host | smart-8c9faea0-076a-4eed-ad6a-816ae464a825 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3756625472 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 74.xbar_error_and_unmapped_add r.3756625472 |
| Directory | /workspace/74.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/74.xbar_error_random.1774607766 |
| Short name | T2269 |
| Test name | |
| Test status | |
| Simulation time | 344840567 ps |
| CPU time | 16.57 seconds |
| Started | Jun 29 08:27:19 PM PDT 24 |
| Finished | Jun 29 08:27:36 PM PDT 24 |
| Peak memory | 574472 kb |
| Host | smart-4e3ab903-faad-4168-b489-5a33b91e59ab |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1774607766 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 74.xbar_error_random.1774607766 |
| Directory | /workspace/74.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/74.xbar_random.4151427427 |
| Short name | T478 |
| Test name | |
| Test status | |
| Simulation time | 476852055 ps |
| CPU time | 44.08 seconds |
| Started | Jun 29 08:27:13 PM PDT 24 |
| Finished | Jun 29 08:27:57 PM PDT 24 |
| Peak memory | 575308 kb |
| Host | smart-64e98349-d798-4290-ac32-b1d94c7eaa04 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4151427427 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 74.xbar_random.4151427427 |
| Directory | /workspace/74.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/74.xbar_random_large_delays.2604203864 |
| Short name | T2317 |
| Test name | |
| Test status | |
| Simulation time | 16684968254 ps |
| CPU time | 176.4 seconds |
| Started | Jun 29 08:27:16 PM PDT 24 |
| Finished | Jun 29 08:30:13 PM PDT 24 |
| Peak memory | 575376 kb |
| Host | smart-830e3113-e0d9-44d7-a937-d8e948aa43da |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2604203864 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 74.xbar_random_large_delays.2604203864 |
| Directory | /workspace/74.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/74.xbar_random_slow_rsp.3303805389 |
| Short name | T554 |
| Test name | |
| Test status | |
| Simulation time | 62409646223 ps |
| CPU time | 1132.03 seconds |
| Started | Jun 29 08:27:20 PM PDT 24 |
| Finished | Jun 29 08:46:12 PM PDT 24 |
| Peak memory | 574340 kb |
| Host | smart-d1afd050-9d4e-4404-afce-2094cf9d4be7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3303805389 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 74.xbar_random_slow_rsp.3303805389 |
| Directory | /workspace/74.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/74.xbar_random_zero_delays.2813511261 |
| Short name | T2720 |
| Test name | |
| Test status | |
| Simulation time | 109192669 ps |
| CPU time | 13.2 seconds |
| Started | Jun 29 08:27:13 PM PDT 24 |
| Finished | Jun 29 08:27:27 PM PDT 24 |
| Peak memory | 575300 kb |
| Host | smart-d0ceffc7-1f46-4eae-bac3-95aa0edea2b0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2813511261 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 74.xbar_random_zero_del ays.2813511261 |
| Directory | /workspace/74.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/74.xbar_same_source.9752819 |
| Short name | T591 |
| Test name | |
| Test status | |
| Simulation time | 2392607867 ps |
| CPU time | 74.8 seconds |
| Started | Jun 29 08:27:22 PM PDT 24 |
| Finished | Jun 29 08:28:37 PM PDT 24 |
| Peak memory | 574280 kb |
| Host | smart-bb6834d1-f2ca-4d4b-a8c1-b4fb629eb6c9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=9752819 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 74.xbar_same_source.9752819 |
| Directory | /workspace/74.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/74.xbar_smoke.426395092 |
| Short name | T1970 |
| Test name | |
| Test status | |
| Simulation time | 52684478 ps |
| CPU time | 7.15 seconds |
| Started | Jun 29 08:27:14 PM PDT 24 |
| Finished | Jun 29 08:27:22 PM PDT 24 |
| Peak memory | 566008 kb |
| Host | smart-1bd0060a-a9de-4cce-8ec6-a05afd96c8f1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=426395092 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 74.xbar_smoke.426395092 |
| Directory | /workspace/74.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/74.xbar_smoke_large_delays.586376838 |
| Short name | T2112 |
| Test name | |
| Test status | |
| Simulation time | 7718332726 ps |
| CPU time | 81.16 seconds |
| Started | Jun 29 08:27:16 PM PDT 24 |
| Finished | Jun 29 08:28:38 PM PDT 24 |
| Peak memory | 574316 kb |
| Host | smart-ff65c1fd-1115-4be3-8bd0-55e5e1cff018 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=586376838 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 74.xbar_smoke_large_delays.586376838 |
| Directory | /workspace/74.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/74.xbar_smoke_slow_rsp.3781601584 |
| Short name | T1809 |
| Test name | |
| Test status | |
| Simulation time | 6161117892 ps |
| CPU time | 106.61 seconds |
| Started | Jun 29 08:27:13 PM PDT 24 |
| Finished | Jun 29 08:29:00 PM PDT 24 |
| Peak memory | 574316 kb |
| Host | smart-70e0c3f6-3188-4559-aad4-b14b81d9a9ae |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3781601584 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 74.xbar_smoke_slow_rsp.3781601584 |
| Directory | /workspace/74.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/74.xbar_smoke_zero_delays.3877298399 |
| Short name | T1453 |
| Test name | |
| Test status | |
| Simulation time | 49124849 ps |
| CPU time | 6.96 seconds |
| Started | Jun 29 08:27:14 PM PDT 24 |
| Finished | Jun 29 08:27:21 PM PDT 24 |
| Peak memory | 574176 kb |
| Host | smart-dade98f3-e35f-426f-bf3e-e383a0e0cd3b |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3877298399 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 74.xbar_smoke_zero_delay s.3877298399 |
| Directory | /workspace/74.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/74.xbar_stress_all.3379852196 |
| Short name | T468 |
| Test name | |
| Test status | |
| Simulation time | 4435998643 ps |
| CPU time | 188.19 seconds |
| Started | Jun 29 08:27:23 PM PDT 24 |
| Finished | Jun 29 08:30:32 PM PDT 24 |
| Peak memory | 574476 kb |
| Host | smart-7de06302-24f8-4dcd-a409-5d7c3839469f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3379852196 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 74.xbar_stress_all.3379852196 |
| Directory | /workspace/74.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/74.xbar_stress_all_with_error.1003725016 |
| Short name | T793 |
| Test name | |
| Test status | |
| Simulation time | 3301034221 ps |
| CPU time | 291.59 seconds |
| Started | Jun 29 08:27:24 PM PDT 24 |
| Finished | Jun 29 08:32:16 PM PDT 24 |
| Peak memory | 574476 kb |
| Host | smart-bb5164f4-7e58-4fdd-a2c9-85123410f50b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1003725016 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 74.xbar_stress_all_with_error.1003725016 |
| Directory | /workspace/74.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/74.xbar_stress_all_with_rand_reset.1370279701 |
| Short name | T1574 |
| Test name | |
| Test status | |
| Simulation time | 117801327 ps |
| CPU time | 73.05 seconds |
| Started | Jun 29 08:27:21 PM PDT 24 |
| Finished | Jun 29 08:28:35 PM PDT 24 |
| Peak memory | 575444 kb |
| Host | smart-1552abc4-2899-48d6-bba3-36ef54e691dd |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1370279701 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 74.xbar_stress_all _with_rand_reset.1370279701 |
| Directory | /workspace/74.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/74.xbar_stress_all_with_reset_error.1084862761 |
| Short name | T1803 |
| Test name | |
| Test status | |
| Simulation time | 1123558137 ps |
| CPU time | 301.25 seconds |
| Started | Jun 29 08:27:21 PM PDT 24 |
| Finished | Jun 29 08:32:22 PM PDT 24 |
| Peak memory | 574416 kb |
| Host | smart-839a7f28-daac-4e32-bf2c-1fffbfd87eb5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1084862761 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 74.xbar_stress_al l_with_reset_error.1084862761 |
| Directory | /workspace/74.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/74.xbar_unmapped_addr.3417653775 |
| Short name | T1558 |
| Test name | |
| Test status | |
| Simulation time | 142708502 ps |
| CPU time | 20.38 seconds |
| Started | Jun 29 08:27:18 PM PDT 24 |
| Finished | Jun 29 08:27:39 PM PDT 24 |
| Peak memory | 575352 kb |
| Host | smart-ecf05e93-d49e-424a-9290-d23ca6f97324 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3417653775 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 74.xbar_unmapped_addr.3417653775 |
| Directory | /workspace/74.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/75.xbar_access_same_device.544403649 |
| Short name | T1685 |
| Test name | |
| Test status | |
| Simulation time | 653061879 ps |
| CPU time | 58.87 seconds |
| Started | Jun 29 08:27:35 PM PDT 24 |
| Finished | Jun 29 08:28:34 PM PDT 24 |
| Peak memory | 575296 kb |
| Host | smart-9500ee2b-93d5-4c73-bad8-c2114f7db30a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=544403649 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 75.xbar_access_same_device. 544403649 |
| Directory | /workspace/75.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/75.xbar_error_and_unmapped_addr.1978664821 |
| Short name | T1983 |
| Test name | |
| Test status | |
| Simulation time | 232751649 ps |
| CPU time | 12.29 seconds |
| Started | Jun 29 08:27:28 PM PDT 24 |
| Finished | Jun 29 08:27:41 PM PDT 24 |
| Peak memory | 574500 kb |
| Host | smart-00205e57-4a7d-4028-8579-f37e1610d500 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1978664821 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 75.xbar_error_and_unmapped_add r.1978664821 |
| Directory | /workspace/75.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/75.xbar_error_random.3212513476 |
| Short name | T1320 |
| Test name | |
| Test status | |
| Simulation time | 2099705711 ps |
| CPU time | 75.15 seconds |
| Started | Jun 29 08:27:34 PM PDT 24 |
| Finished | Jun 29 08:28:49 PM PDT 24 |
| Peak memory | 573928 kb |
| Host | smart-be84f039-5167-4e0f-a0dc-075d544c3614 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3212513476 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 75.xbar_error_random.3212513476 |
| Directory | /workspace/75.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/75.xbar_random.2792916860 |
| Short name | T1662 |
| Test name | |
| Test status | |
| Simulation time | 1260123253 ps |
| CPU time | 45.87 seconds |
| Started | Jun 29 08:27:18 PM PDT 24 |
| Finished | Jun 29 08:28:05 PM PDT 24 |
| Peak memory | 575316 kb |
| Host | smart-f0917ba2-1d86-4fcf-9a2d-1db1b6992526 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2792916860 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 75.xbar_random.2792916860 |
| Directory | /workspace/75.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/75.xbar_random_large_delays.1417433982 |
| Short name | T2848 |
| Test name | |
| Test status | |
| Simulation time | 106025922417 ps |
| CPU time | 1109.19 seconds |
| Started | Jun 29 08:27:21 PM PDT 24 |
| Finished | Jun 29 08:45:50 PM PDT 24 |
| Peak memory | 575372 kb |
| Host | smart-70ee5262-63fd-4399-974f-26aa98283f72 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1417433982 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 75.xbar_random_large_delays.1417433982 |
| Directory | /workspace/75.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/75.xbar_random_slow_rsp.3365548763 |
| Short name | T2061 |
| Test name | |
| Test status | |
| Simulation time | 45082689412 ps |
| CPU time | 764.04 seconds |
| Started | Jun 29 08:27:19 PM PDT 24 |
| Finished | Jun 29 08:40:04 PM PDT 24 |
| Peak memory | 575448 kb |
| Host | smart-8dcfc49f-fbb9-40d3-8ce1-ad8c72a7cd4f |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3365548763 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 75.xbar_random_slow_rsp.3365548763 |
| Directory | /workspace/75.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/75.xbar_random_zero_delays.107526864 |
| Short name | T2034 |
| Test name | |
| Test status | |
| Simulation time | 253554177 ps |
| CPU time | 26.12 seconds |
| Started | Jun 29 08:27:20 PM PDT 24 |
| Finished | Jun 29 08:27:46 PM PDT 24 |
| Peak memory | 574224 kb |
| Host | smart-40f0bc96-b8d0-46a6-94b5-c288239e5238 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=107526864 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 75.xbar_random_zero_dela ys.107526864 |
| Directory | /workspace/75.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/75.xbar_same_source.2136494131 |
| Short name | T567 |
| Test name | |
| Test status | |
| Simulation time | 1952682373 ps |
| CPU time | 62.94 seconds |
| Started | Jun 29 08:27:40 PM PDT 24 |
| Finished | Jun 29 08:28:43 PM PDT 24 |
| Peak memory | 575304 kb |
| Host | smart-1fb812a1-bdb9-4060-8b9b-ecae4e824880 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2136494131 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 75.xbar_same_source.2136494131 |
| Directory | /workspace/75.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/75.xbar_smoke.2914392348 |
| Short name | T1655 |
| Test name | |
| Test status | |
| Simulation time | 203311917 ps |
| CPU time | 9.09 seconds |
| Started | Jun 29 08:27:22 PM PDT 24 |
| Finished | Jun 29 08:27:32 PM PDT 24 |
| Peak memory | 574136 kb |
| Host | smart-73cc7956-3caa-4af5-b34e-961351a7c2af |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2914392348 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 75.xbar_smoke.2914392348 |
| Directory | /workspace/75.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/75.xbar_smoke_large_delays.3653401876 |
| Short name | T1484 |
| Test name | |
| Test status | |
| Simulation time | 8013575740 ps |
| CPU time | 85.45 seconds |
| Started | Jun 29 08:27:19 PM PDT 24 |
| Finished | Jun 29 08:28:45 PM PDT 24 |
| Peak memory | 574328 kb |
| Host | smart-f20c7b3a-0ab4-4ea9-9888-1c194a312ce9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3653401876 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 75.xbar_smoke_large_delays.3653401876 |
| Directory | /workspace/75.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/75.xbar_smoke_slow_rsp.4072465108 |
| Short name | T1440 |
| Test name | |
| Test status | |
| Simulation time | 4830501803 ps |
| CPU time | 86.74 seconds |
| Started | Jun 29 08:27:21 PM PDT 24 |
| Finished | Jun 29 08:28:48 PM PDT 24 |
| Peak memory | 566004 kb |
| Host | smart-aaa55975-17a0-43b9-a8e1-38c2e4719bf3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4072465108 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 75.xbar_smoke_slow_rsp.4072465108 |
| Directory | /workspace/75.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/75.xbar_smoke_zero_delays.1765011344 |
| Short name | T2518 |
| Test name | |
| Test status | |
| Simulation time | 47133802 ps |
| CPU time | 7.06 seconds |
| Started | Jun 29 08:27:20 PM PDT 24 |
| Finished | Jun 29 08:27:28 PM PDT 24 |
| Peak memory | 574260 kb |
| Host | smart-32f1c68a-42e1-4d48-9409-b9e6e5b5f4d5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1765011344 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 75.xbar_smoke_zero_delay s.1765011344 |
| Directory | /workspace/75.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/75.xbar_stress_all.3782090753 |
| Short name | T2482 |
| Test name | |
| Test status | |
| Simulation time | 1928561727 ps |
| CPU time | 177.1 seconds |
| Started | Jun 29 08:27:27 PM PDT 24 |
| Finished | Jun 29 08:30:25 PM PDT 24 |
| Peak memory | 574340 kb |
| Host | smart-377dc3fd-a136-42e2-a4f2-36b4b1206084 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3782090753 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 75.xbar_stress_all.3782090753 |
| Directory | /workspace/75.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/75.xbar_stress_all_with_error.1496222609 |
| Short name | T2415 |
| Test name | |
| Test status | |
| Simulation time | 80363877 ps |
| CPU time | 6.75 seconds |
| Started | Jun 29 08:27:40 PM PDT 24 |
| Finished | Jun 29 08:27:47 PM PDT 24 |
| Peak memory | 566040 kb |
| Host | smart-eed935c8-1749-4e11-bb2b-5cff3f3f6269 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1496222609 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 75.xbar_stress_all_with_error.1496222609 |
| Directory | /workspace/75.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/75.xbar_stress_all_with_rand_reset.3473607345 |
| Short name | T2635 |
| Test name | |
| Test status | |
| Simulation time | 164510662 ps |
| CPU time | 41.18 seconds |
| Started | Jun 29 08:27:35 PM PDT 24 |
| Finished | Jun 29 08:28:17 PM PDT 24 |
| Peak memory | 574376 kb |
| Host | smart-92daf958-a2bb-49c6-83e4-41234924fcaa |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3473607345 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 75.xbar_stress_all _with_rand_reset.3473607345 |
| Directory | /workspace/75.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/75.xbar_stress_all_with_reset_error.4170915530 |
| Short name | T819 |
| Test name | |
| Test status | |
| Simulation time | 613237297 ps |
| CPU time | 198.57 seconds |
| Started | Jun 29 08:27:28 PM PDT 24 |
| Finished | Jun 29 08:30:47 PM PDT 24 |
| Peak memory | 574460 kb |
| Host | smart-8fe1a431-d853-4a01-a274-08b0b8010c80 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4170915530 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 75.xbar_stress_al l_with_reset_error.4170915530 |
| Directory | /workspace/75.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/75.xbar_unmapped_addr.856369714 |
| Short name | T1617 |
| Test name | |
| Test status | |
| Simulation time | 1466293934 ps |
| CPU time | 65.13 seconds |
| Started | Jun 29 08:27:39 PM PDT 24 |
| Finished | Jun 29 08:28:45 PM PDT 24 |
| Peak memory | 575388 kb |
| Host | smart-ab9baad5-b679-4cd9-8968-ee7a3668e00b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=856369714 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 75.xbar_unmapped_addr.856369714 |
| Directory | /workspace/75.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/76.xbar_access_same_device.3045123386 |
| Short name | T2532 |
| Test name | |
| Test status | |
| Simulation time | 368778412 ps |
| CPU time | 21.69 seconds |
| Started | Jun 29 08:27:37 PM PDT 24 |
| Finished | Jun 29 08:27:59 PM PDT 24 |
| Peak memory | 575280 kb |
| Host | smart-65acf8d7-3d2f-47fe-aa3d-62db7dc4ac98 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3045123386 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 76.xbar_access_same_device .3045123386 |
| Directory | /workspace/76.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/76.xbar_access_same_device_slow_rsp.2808354677 |
| Short name | T2867 |
| Test name | |
| Test status | |
| Simulation time | 18716950591 ps |
| CPU time | 347.5 seconds |
| Started | Jun 29 08:27:34 PM PDT 24 |
| Finished | Jun 29 08:33:21 PM PDT 24 |
| Peak memory | 574368 kb |
| Host | smart-e53d9d5a-3b2d-4998-850e-56bff4a06e78 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2808354677 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 76.xbar_access_same_ device_slow_rsp.2808354677 |
| Directory | /workspace/76.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/76.xbar_error_and_unmapped_addr.2512234947 |
| Short name | T2428 |
| Test name | |
| Test status | |
| Simulation time | 686946656 ps |
| CPU time | 28.37 seconds |
| Started | Jun 29 08:27:35 PM PDT 24 |
| Finished | Jun 29 08:28:04 PM PDT 24 |
| Peak memory | 574488 kb |
| Host | smart-1dda4d7f-bc21-4ce8-87ac-1032e08f85bd |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2512234947 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 76.xbar_error_and_unmapped_add r.2512234947 |
| Directory | /workspace/76.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/76.xbar_error_random.3432662915 |
| Short name | T1844 |
| Test name | |
| Test status | |
| Simulation time | 534162778 ps |
| CPU time | 44.58 seconds |
| Started | Jun 29 08:27:41 PM PDT 24 |
| Finished | Jun 29 08:28:26 PM PDT 24 |
| Peak memory | 574264 kb |
| Host | smart-2877b262-28ec-41ac-bd7d-e306b064e048 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3432662915 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 76.xbar_error_random.3432662915 |
| Directory | /workspace/76.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/76.xbar_random.3934028987 |
| Short name | T1308 |
| Test name | |
| Test status | |
| Simulation time | 63354115 ps |
| CPU time | 8.36 seconds |
| Started | Jun 29 08:27:27 PM PDT 24 |
| Finished | Jun 29 08:27:35 PM PDT 24 |
| Peak memory | 574284 kb |
| Host | smart-3b5d0be3-f78e-4136-afdf-4fe164a27576 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3934028987 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 76.xbar_random.3934028987 |
| Directory | /workspace/76.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/76.xbar_random_large_delays.3925531814 |
| Short name | T1956 |
| Test name | |
| Test status | |
| Simulation time | 36057666735 ps |
| CPU time | 383.46 seconds |
| Started | Jun 29 08:27:36 PM PDT 24 |
| Finished | Jun 29 08:33:59 PM PDT 24 |
| Peak memory | 575372 kb |
| Host | smart-87ea91e8-154a-4b86-98c9-c78831883cbd |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3925531814 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 76.xbar_random_large_delays.3925531814 |
| Directory | /workspace/76.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/76.xbar_random_slow_rsp.675528843 |
| Short name | T2563 |
| Test name | |
| Test status | |
| Simulation time | 44511447654 ps |
| CPU time | 791.92 seconds |
| Started | Jun 29 08:27:36 PM PDT 24 |
| Finished | Jun 29 08:40:49 PM PDT 24 |
| Peak memory | 575428 kb |
| Host | smart-08ab7495-267c-47cd-ad50-db016839e100 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=675528843 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 76.xbar_random_slow_rsp.675528843 |
| Directory | /workspace/76.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/76.xbar_random_zero_delays.519088914 |
| Short name | T2830 |
| Test name | |
| Test status | |
| Simulation time | 383458265 ps |
| CPU time | 41.16 seconds |
| Started | Jun 29 08:27:27 PM PDT 24 |
| Finished | Jun 29 08:28:08 PM PDT 24 |
| Peak memory | 575204 kb |
| Host | smart-76eec904-95fe-4ea5-860d-8b6fd3cca745 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=519088914 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 76.xbar_random_zero_dela ys.519088914 |
| Directory | /workspace/76.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/76.xbar_same_source.2068857246 |
| Short name | T1800 |
| Test name | |
| Test status | |
| Simulation time | 2328962609 ps |
| CPU time | 69.27 seconds |
| Started | Jun 29 08:27:36 PM PDT 24 |
| Finished | Jun 29 08:28:46 PM PDT 24 |
| Peak memory | 575320 kb |
| Host | smart-cbde11e6-8694-4eaa-ba93-d9abfcc6586e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2068857246 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 76.xbar_same_source.2068857246 |
| Directory | /workspace/76.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/76.xbar_smoke.1730452909 |
| Short name | T2876 |
| Test name | |
| Test status | |
| Simulation time | 224437722 ps |
| CPU time | 9.37 seconds |
| Started | Jun 29 08:27:28 PM PDT 24 |
| Finished | Jun 29 08:27:37 PM PDT 24 |
| Peak memory | 566016 kb |
| Host | smart-f93d0b90-2378-4576-83dc-341e0910f89c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1730452909 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 76.xbar_smoke.1730452909 |
| Directory | /workspace/76.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/76.xbar_smoke_large_delays.1715586913 |
| Short name | T2459 |
| Test name | |
| Test status | |
| Simulation time | 8884210281 ps |
| CPU time | 91.9 seconds |
| Started | Jun 29 08:27:39 PM PDT 24 |
| Finished | Jun 29 08:29:11 PM PDT 24 |
| Peak memory | 566092 kb |
| Host | smart-566f8809-c42f-4d45-9b39-e6d03d6df531 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1715586913 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 76.xbar_smoke_large_delays.1715586913 |
| Directory | /workspace/76.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/76.xbar_smoke_slow_rsp.4189245712 |
| Short name | T2470 |
| Test name | |
| Test status | |
| Simulation time | 5606874278 ps |
| CPU time | 98.51 seconds |
| Started | Jun 29 08:27:39 PM PDT 24 |
| Finished | Jun 29 08:29:18 PM PDT 24 |
| Peak memory | 574328 kb |
| Host | smart-9217ef36-61c3-4f94-ada4-1b35221e79c4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4189245712 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 76.xbar_smoke_slow_rsp.4189245712 |
| Directory | /workspace/76.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/76.xbar_smoke_zero_delays.1996888411 |
| Short name | T2461 |
| Test name | |
| Test status | |
| Simulation time | 47196814 ps |
| CPU time | 6.78 seconds |
| Started | Jun 29 08:27:28 PM PDT 24 |
| Finished | Jun 29 08:27:35 PM PDT 24 |
| Peak memory | 574256 kb |
| Host | smart-81c38f07-5e30-46a5-9d44-d4d6cfec2f4c |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1996888411 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 76.xbar_smoke_zero_delay s.1996888411 |
| Directory | /workspace/76.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/76.xbar_stress_all.1862710367 |
| Short name | T467 |
| Test name | |
| Test status | |
| Simulation time | 4622192102 ps |
| CPU time | 413.04 seconds |
| Started | Jun 29 08:27:34 PM PDT 24 |
| Finished | Jun 29 08:34:27 PM PDT 24 |
| Peak memory | 574448 kb |
| Host | smart-1895c357-37aa-4dcc-a24c-a96a9e2fa77a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1862710367 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 76.xbar_stress_all.1862710367 |
| Directory | /workspace/76.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/76.xbar_stress_all_with_error.1725801850 |
| Short name | T622 |
| Test name | |
| Test status | |
| Simulation time | 1915333929 ps |
| CPU time | 181.49 seconds |
| Started | Jun 29 08:27:37 PM PDT 24 |
| Finished | Jun 29 08:30:39 PM PDT 24 |
| Peak memory | 574680 kb |
| Host | smart-04b002e4-f8c0-4675-bcaf-7b101667997e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1725801850 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 76.xbar_stress_all_with_error.1725801850 |
| Directory | /workspace/76.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/76.xbar_stress_all_with_rand_reset.2409552282 |
| Short name | T2409 |
| Test name | |
| Test status | |
| Simulation time | 135862069 ps |
| CPU time | 63.89 seconds |
| Started | Jun 29 08:27:36 PM PDT 24 |
| Finished | Jun 29 08:28:40 PM PDT 24 |
| Peak memory | 575452 kb |
| Host | smart-6a301b01-f9ff-4fd8-84f3-10b96960b656 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2409552282 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 76.xbar_stress_all _with_rand_reset.2409552282 |
| Directory | /workspace/76.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/76.xbar_stress_all_with_reset_error.1419282196 |
| Short name | T816 |
| Test name | |
| Test status | |
| Simulation time | 11896418764 ps |
| CPU time | 674.94 seconds |
| Started | Jun 29 08:27:36 PM PDT 24 |
| Finished | Jun 29 08:38:52 PM PDT 24 |
| Peak memory | 574496 kb |
| Host | smart-38405c34-e4c1-4a7a-b42d-b1202f156348 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1419282196 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 76.xbar_stress_al l_with_reset_error.1419282196 |
| Directory | /workspace/76.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/76.xbar_unmapped_addr.4079853012 |
| Short name | T1486 |
| Test name | |
| Test status | |
| Simulation time | 363341268 ps |
| CPU time | 42.64 seconds |
| Started | Jun 29 08:27:35 PM PDT 24 |
| Finished | Jun 29 08:28:18 PM PDT 24 |
| Peak memory | 574224 kb |
| Host | smart-438a4ed5-eb74-42df-95ca-bbe9e5b0810a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4079853012 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 76.xbar_unmapped_addr.4079853012 |
| Directory | /workspace/76.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/77.xbar_access_same_device.4057398879 |
| Short name | T2861 |
| Test name | |
| Test status | |
| Simulation time | 89048765 ps |
| CPU time | 7.39 seconds |
| Started | Jun 29 08:27:49 PM PDT 24 |
| Finished | Jun 29 08:27:57 PM PDT 24 |
| Peak memory | 574152 kb |
| Host | smart-088f81de-f87d-493c-acb8-040d96f2111f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4057398879 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 77.xbar_access_same_device .4057398879 |
| Directory | /workspace/77.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/77.xbar_access_same_device_slow_rsp.4026189452 |
| Short name | T2473 |
| Test name | |
| Test status | |
| Simulation time | 90892398312 ps |
| CPU time | 1522.88 seconds |
| Started | Jun 29 08:27:49 PM PDT 24 |
| Finished | Jun 29 08:53:13 PM PDT 24 |
| Peak memory | 575452 kb |
| Host | smart-774df046-ba32-4978-ad9b-b4f69a59d25f |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4026189452 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 77.xbar_access_same_ device_slow_rsp.4026189452 |
| Directory | /workspace/77.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/77.xbar_error_and_unmapped_addr.217191651 |
| Short name | T1387 |
| Test name | |
| Test status | |
| Simulation time | 186399640 ps |
| CPU time | 24.84 seconds |
| Started | Jun 29 08:27:49 PM PDT 24 |
| Finished | Jun 29 08:28:14 PM PDT 24 |
| Peak memory | 574268 kb |
| Host | smart-5ae632fc-ca2c-409a-a14a-3ce9f01880c2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=217191651 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 77.xbar_error_and_unmapped_addr .217191651 |
| Directory | /workspace/77.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/77.xbar_error_random.3063989647 |
| Short name | T1827 |
| Test name | |
| Test status | |
| Simulation time | 194576471 ps |
| CPU time | 18.39 seconds |
| Started | Jun 29 08:27:49 PM PDT 24 |
| Finished | Jun 29 08:28:08 PM PDT 24 |
| Peak memory | 574500 kb |
| Host | smart-ecc49149-fbc3-407a-bb98-cc0a80574f2f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3063989647 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 77.xbar_error_random.3063989647 |
| Directory | /workspace/77.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/77.xbar_random.2325627655 |
| Short name | T2693 |
| Test name | |
| Test status | |
| Simulation time | 63151312 ps |
| CPU time | 9.37 seconds |
| Started | Jun 29 08:27:49 PM PDT 24 |
| Finished | Jun 29 08:27:59 PM PDT 24 |
| Peak memory | 574236 kb |
| Host | smart-3d455224-a712-4312-86d0-651a67690556 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2325627655 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 77.xbar_random.2325627655 |
| Directory | /workspace/77.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/77.xbar_random_large_delays.3535571011 |
| Short name | T494 |
| Test name | |
| Test status | |
| Simulation time | 85516778206 ps |
| CPU time | 869.04 seconds |
| Started | Jun 29 08:27:49 PM PDT 24 |
| Finished | Jun 29 08:42:18 PM PDT 24 |
| Peak memory | 575440 kb |
| Host | smart-7efb0545-bd74-4f81-9601-1790aed4a796 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3535571011 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 77.xbar_random_large_delays.3535571011 |
| Directory | /workspace/77.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/77.xbar_random_slow_rsp.2774419078 |
| Short name | T2821 |
| Test name | |
| Test status | |
| Simulation time | 28249957839 ps |
| CPU time | 476.21 seconds |
| Started | Jun 29 08:27:49 PM PDT 24 |
| Finished | Jun 29 08:35:46 PM PDT 24 |
| Peak memory | 574320 kb |
| Host | smart-b64addac-5aa9-4ca7-8bc4-3f92cc0854e1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2774419078 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 77.xbar_random_slow_rsp.2774419078 |
| Directory | /workspace/77.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/77.xbar_random_zero_delays.1227699575 |
| Short name | T2837 |
| Test name | |
| Test status | |
| Simulation time | 478854590 ps |
| CPU time | 49.18 seconds |
| Started | Jun 29 08:27:49 PM PDT 24 |
| Finished | Jun 29 08:28:39 PM PDT 24 |
| Peak memory | 574284 kb |
| Host | smart-f0e67bb7-2d23-42be-80ab-29415d36fc70 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1227699575 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 77.xbar_random_zero_del ays.1227699575 |
| Directory | /workspace/77.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/77.xbar_same_source.2874065802 |
| Short name | T2014 |
| Test name | |
| Test status | |
| Simulation time | 712744052 ps |
| CPU time | 26.03 seconds |
| Started | Jun 29 08:27:49 PM PDT 24 |
| Finished | Jun 29 08:28:15 PM PDT 24 |
| Peak memory | 575296 kb |
| Host | smart-473da842-2432-4d1d-a2d6-c7e4ba515fed |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2874065802 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 77.xbar_same_source.2874065802 |
| Directory | /workspace/77.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/77.xbar_smoke.292274459 |
| Short name | T1483 |
| Test name | |
| Test status | |
| Simulation time | 189632086 ps |
| CPU time | 9.79 seconds |
| Started | Jun 29 08:27:38 PM PDT 24 |
| Finished | Jun 29 08:27:48 PM PDT 24 |
| Peak memory | 574252 kb |
| Host | smart-89c42db3-8303-4442-9aae-9b301b7a94b5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=292274459 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 77.xbar_smoke.292274459 |
| Directory | /workspace/77.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/77.xbar_smoke_large_delays.808278256 |
| Short name | T1404 |
| Test name | |
| Test status | |
| Simulation time | 9053909624 ps |
| CPU time | 95.29 seconds |
| Started | Jun 29 08:27:51 PM PDT 24 |
| Finished | Jun 29 08:29:26 PM PDT 24 |
| Peak memory | 574320 kb |
| Host | smart-8eca7396-c5bd-499f-a4a9-1d64839270d4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=808278256 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 77.xbar_smoke_large_delays.808278256 |
| Directory | /workspace/77.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/77.xbar_smoke_slow_rsp.286776356 |
| Short name | T2058 |
| Test name | |
| Test status | |
| Simulation time | 5123540224 ps |
| CPU time | 87.23 seconds |
| Started | Jun 29 08:27:48 PM PDT 24 |
| Finished | Jun 29 08:29:16 PM PDT 24 |
| Peak memory | 574308 kb |
| Host | smart-fa1010af-b0f9-4644-9f94-11d2570a5007 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=286776356 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 77.xbar_smoke_slow_rsp.286776356 |
| Directory | /workspace/77.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/77.xbar_smoke_zero_delays.3278343334 |
| Short name | T1757 |
| Test name | |
| Test status | |
| Simulation time | 36649488 ps |
| CPU time | 6.12 seconds |
| Started | Jun 29 08:27:35 PM PDT 24 |
| Finished | Jun 29 08:27:42 PM PDT 24 |
| Peak memory | 574192 kb |
| Host | smart-0a86de48-ad2f-4183-b4f9-880a6a0175b2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3278343334 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 77.xbar_smoke_zero_delay s.3278343334 |
| Directory | /workspace/77.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/77.xbar_stress_all.1932973291 |
| Short name | T483 |
| Test name | |
| Test status | |
| Simulation time | 5845350293 ps |
| CPU time | 197.52 seconds |
| Started | Jun 29 08:27:51 PM PDT 24 |
| Finished | Jun 29 08:31:09 PM PDT 24 |
| Peak memory | 574468 kb |
| Host | smart-65eda608-800b-47ad-9082-052a7370612b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1932973291 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 77.xbar_stress_all.1932973291 |
| Directory | /workspace/77.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/77.xbar_stress_all_with_rand_reset.1141363136 |
| Short name | T2209 |
| Test name | |
| Test status | |
| Simulation time | 189578938 ps |
| CPU time | 67.86 seconds |
| Started | Jun 29 08:27:48 PM PDT 24 |
| Finished | Jun 29 08:28:57 PM PDT 24 |
| Peak memory | 575448 kb |
| Host | smart-5f4a904b-f552-4247-9bed-8b9039b9a748 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1141363136 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 77.xbar_stress_all _with_rand_reset.1141363136 |
| Directory | /workspace/77.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/77.xbar_stress_all_with_reset_error.1016528326 |
| Short name | T1712 |
| Test name | |
| Test status | |
| Simulation time | 13440676057 ps |
| CPU time | 507.16 seconds |
| Started | Jun 29 08:27:48 PM PDT 24 |
| Finished | Jun 29 08:36:16 PM PDT 24 |
| Peak memory | 574496 kb |
| Host | smart-7e609aee-9c95-47d5-863d-021b9eebc071 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1016528326 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 77.xbar_stress_al l_with_reset_error.1016528326 |
| Directory | /workspace/77.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/77.xbar_unmapped_addr.1246930583 |
| Short name | T1317 |
| Test name | |
| Test status | |
| Simulation time | 303847975 ps |
| CPU time | 15.05 seconds |
| Started | Jun 29 08:27:50 PM PDT 24 |
| Finished | Jun 29 08:28:05 PM PDT 24 |
| Peak memory | 575344 kb |
| Host | smart-d27cc4ad-12d9-4a13-8244-6d62c9107118 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1246930583 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 77.xbar_unmapped_addr.1246930583 |
| Directory | /workspace/77.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/78.xbar_access_same_device.1453874677 |
| Short name | T1381 |
| Test name | |
| Test status | |
| Simulation time | 197667304 ps |
| CPU time | 20.35 seconds |
| Started | Jun 29 08:28:07 PM PDT 24 |
| Finished | Jun 29 08:28:28 PM PDT 24 |
| Peak memory | 575268 kb |
| Host | smart-b542df4c-f8b6-415d-bcd4-e2aec3dbcd6f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1453874677 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 78.xbar_access_same_device .1453874677 |
| Directory | /workspace/78.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/78.xbar_access_same_device_slow_rsp.1668367285 |
| Short name | T790 |
| Test name | |
| Test status | |
| Simulation time | 148018515281 ps |
| CPU time | 2466.88 seconds |
| Started | Jun 29 08:28:03 PM PDT 24 |
| Finished | Jun 29 09:09:10 PM PDT 24 |
| Peak memory | 574424 kb |
| Host | smart-5c219dd0-9326-4f71-8812-8e95b4932b84 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1668367285 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 78.xbar_access_same_ device_slow_rsp.1668367285 |
| Directory | /workspace/78.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/78.xbar_error_and_unmapped_addr.3929430053 |
| Short name | T1795 |
| Test name | |
| Test status | |
| Simulation time | 206362148 ps |
| CPU time | 27.57 seconds |
| Started | Jun 29 08:28:04 PM PDT 24 |
| Finished | Jun 29 08:28:32 PM PDT 24 |
| Peak memory | 574488 kb |
| Host | smart-69db2866-6d2c-47a5-9a06-b0a7fadab7b2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3929430053 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 78.xbar_error_and_unmapped_add r.3929430053 |
| Directory | /workspace/78.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/78.xbar_error_random.3082754411 |
| Short name | T1575 |
| Test name | |
| Test status | |
| Simulation time | 2543674294 ps |
| CPU time | 104.25 seconds |
| Started | Jun 29 08:28:07 PM PDT 24 |
| Finished | Jun 29 08:29:52 PM PDT 24 |
| Peak memory | 573920 kb |
| Host | smart-19e6d327-7160-4b32-bc7f-86f3a68587f6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3082754411 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 78.xbar_error_random.3082754411 |
| Directory | /workspace/78.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/78.xbar_random.3531452974 |
| Short name | T594 |
| Test name | |
| Test status | |
| Simulation time | 535509116 ps |
| CPU time | 52.52 seconds |
| Started | Jun 29 08:28:02 PM PDT 24 |
| Finished | Jun 29 08:28:55 PM PDT 24 |
| Peak memory | 575292 kb |
| Host | smart-b43dbf7d-0dc3-44e2-a3d5-58ef43666626 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3531452974 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 78.xbar_random.3531452974 |
| Directory | /workspace/78.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/78.xbar_random_large_delays.3457286185 |
| Short name | T2300 |
| Test name | |
| Test status | |
| Simulation time | 48245729869 ps |
| CPU time | 521.44 seconds |
| Started | Jun 29 08:28:05 PM PDT 24 |
| Finished | Jun 29 08:36:47 PM PDT 24 |
| Peak memory | 575352 kb |
| Host | smart-7236390f-5739-409e-9be1-667ad270e2e0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3457286185 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 78.xbar_random_large_delays.3457286185 |
| Directory | /workspace/78.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/78.xbar_random_slow_rsp.1620848572 |
| Short name | T1845 |
| Test name | |
| Test status | |
| Simulation time | 41935736602 ps |
| CPU time | 750.31 seconds |
| Started | Jun 29 08:28:04 PM PDT 24 |
| Finished | Jun 29 08:40:34 PM PDT 24 |
| Peak memory | 575372 kb |
| Host | smart-8d3359c7-d144-471d-bad9-280dc424db8c |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1620848572 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 78.xbar_random_slow_rsp.1620848572 |
| Directory | /workspace/78.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/78.xbar_random_zero_delays.1076250906 |
| Short name | T1936 |
| Test name | |
| Test status | |
| Simulation time | 213321648 ps |
| CPU time | 26.1 seconds |
| Started | Jun 29 08:28:05 PM PDT 24 |
| Finished | Jun 29 08:28:31 PM PDT 24 |
| Peak memory | 575292 kb |
| Host | smart-ae023b91-1a1f-44d0-807e-ea61704b1fbb |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1076250906 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 78.xbar_random_zero_del ays.1076250906 |
| Directory | /workspace/78.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/78.xbar_same_source.1050261258 |
| Short name | T1696 |
| Test name | |
| Test status | |
| Simulation time | 570060697 ps |
| CPU time | 46.11 seconds |
| Started | Jun 29 08:28:04 PM PDT 24 |
| Finished | Jun 29 08:28:51 PM PDT 24 |
| Peak memory | 575176 kb |
| Host | smart-4e129303-6936-4cc5-8838-4b2f9c3625e6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1050261258 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 78.xbar_same_source.1050261258 |
| Directory | /workspace/78.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/78.xbar_smoke.1944570237 |
| Short name | T1482 |
| Test name | |
| Test status | |
| Simulation time | 233080441 ps |
| CPU time | 10.1 seconds |
| Started | Jun 29 08:27:50 PM PDT 24 |
| Finished | Jun 29 08:28:00 PM PDT 24 |
| Peak memory | 565980 kb |
| Host | smart-e25e7843-896b-44c2-a905-8c87ed18e9ba |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1944570237 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 78.xbar_smoke.1944570237 |
| Directory | /workspace/78.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/78.xbar_smoke_large_delays.2149485406 |
| Short name | T1341 |
| Test name | |
| Test status | |
| Simulation time | 7839810851 ps |
| CPU time | 79.96 seconds |
| Started | Jun 29 08:27:48 PM PDT 24 |
| Finished | Jun 29 08:29:09 PM PDT 24 |
| Peak memory | 574276 kb |
| Host | smart-903af6b9-3687-4dcc-b714-2fc5f0a3d0f5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2149485406 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 78.xbar_smoke_large_delays.2149485406 |
| Directory | /workspace/78.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/78.xbar_smoke_slow_rsp.853978796 |
| Short name | T2027 |
| Test name | |
| Test status | |
| Simulation time | 6056424345 ps |
| CPU time | 105.85 seconds |
| Started | Jun 29 08:27:49 PM PDT 24 |
| Finished | Jun 29 08:29:36 PM PDT 24 |
| Peak memory | 574200 kb |
| Host | smart-ddac0295-d506-4cae-bf48-06e082fc0cb4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=853978796 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 78.xbar_smoke_slow_rsp.853978796 |
| Directory | /workspace/78.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/78.xbar_smoke_zero_delays.1401205239 |
| Short name | T2458 |
| Test name | |
| Test status | |
| Simulation time | 35627656 ps |
| CPU time | 5.91 seconds |
| Started | Jun 29 08:27:48 PM PDT 24 |
| Finished | Jun 29 08:27:55 PM PDT 24 |
| Peak memory | 565868 kb |
| Host | smart-ab59abb5-0b1a-46f7-9605-5916bf1cd1e1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1401205239 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 78.xbar_smoke_zero_delay s.1401205239 |
| Directory | /workspace/78.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/78.xbar_stress_all.2764715673 |
| Short name | T1752 |
| Test name | |
| Test status | |
| Simulation time | 2657877147 ps |
| CPU time | 212.43 seconds |
| Started | Jun 29 08:28:04 PM PDT 24 |
| Finished | Jun 29 08:31:37 PM PDT 24 |
| Peak memory | 575520 kb |
| Host | smart-e920af6b-6d54-45ab-ac17-97e0a194b6ed |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2764715673 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 78.xbar_stress_all.2764715673 |
| Directory | /workspace/78.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/78.xbar_stress_all_with_error.3837137945 |
| Short name | T1550 |
| Test name | |
| Test status | |
| Simulation time | 3796811394 ps |
| CPU time | 317.5 seconds |
| Started | Jun 29 08:28:03 PM PDT 24 |
| Finished | Jun 29 08:33:21 PM PDT 24 |
| Peak memory | 574468 kb |
| Host | smart-35eb55b4-1cf9-4b4a-92f5-f540f6387bed |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3837137945 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 78.xbar_stress_all_with_error.3837137945 |
| Directory | /workspace/78.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/78.xbar_stress_all_with_rand_reset.943916675 |
| Short name | T1529 |
| Test name | |
| Test status | |
| Simulation time | 3873650208 ps |
| CPU time | 176.07 seconds |
| Started | Jun 29 08:28:03 PM PDT 24 |
| Finished | Jun 29 08:30:59 PM PDT 24 |
| Peak memory | 576512 kb |
| Host | smart-0b1a2127-c2ad-414a-bc22-46a88bcd0336 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=943916675 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_res et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 78.xbar_stress_all_ with_rand_reset.943916675 |
| Directory | /workspace/78.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/78.xbar_stress_all_with_reset_error.1841082291 |
| Short name | T785 |
| Test name | |
| Test status | |
| Simulation time | 6540063028 ps |
| CPU time | 489.18 seconds |
| Started | Jun 29 08:28:04 PM PDT 24 |
| Finished | Jun 29 08:36:13 PM PDT 24 |
| Peak memory | 574500 kb |
| Host | smart-5887a0ae-73dd-4080-8226-9434b468b8fd |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1841082291 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 78.xbar_stress_al l_with_reset_error.1841082291 |
| Directory | /workspace/78.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/78.xbar_unmapped_addr.3390702897 |
| Short name | T2593 |
| Test name | |
| Test status | |
| Simulation time | 1245114177 ps |
| CPU time | 58.44 seconds |
| Started | Jun 29 08:28:04 PM PDT 24 |
| Finished | Jun 29 08:29:03 PM PDT 24 |
| Peak memory | 575388 kb |
| Host | smart-f9099b5f-d8dc-410d-b7a0-60b9915e5c1d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3390702897 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 78.xbar_unmapped_addr.3390702897 |
| Directory | /workspace/78.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/79.xbar_access_same_device.296817638 |
| Short name | T2799 |
| Test name | |
| Test status | |
| Simulation time | 1044293611 ps |
| CPU time | 50.81 seconds |
| Started | Jun 29 08:28:02 PM PDT 24 |
| Finished | Jun 29 08:28:53 PM PDT 24 |
| Peak memory | 574236 kb |
| Host | smart-564c7616-2b3f-4f5b-896e-a922d506be30 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=296817638 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 79.xbar_access_same_device. 296817638 |
| Directory | /workspace/79.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/79.xbar_access_same_device_slow_rsp.3270126729 |
| Short name | T1814 |
| Test name | |
| Test status | |
| Simulation time | 114615809014 ps |
| CPU time | 1820.17 seconds |
| Started | Jun 29 08:28:05 PM PDT 24 |
| Finished | Jun 29 08:58:26 PM PDT 24 |
| Peak memory | 575460 kb |
| Host | smart-54378859-b9fd-4b83-b8e1-1e24d88e8e0d |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3270126729 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 79.xbar_access_same_ device_slow_rsp.3270126729 |
| Directory | /workspace/79.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/79.xbar_error_and_unmapped_addr.3016577935 |
| Short name | T1382 |
| Test name | |
| Test status | |
| Simulation time | 90290179 ps |
| CPU time | 12.39 seconds |
| Started | Jun 29 08:28:06 PM PDT 24 |
| Finished | Jun 29 08:28:19 PM PDT 24 |
| Peak memory | 574508 kb |
| Host | smart-6ce2cd77-27e0-4c76-8ea0-c9862c55db28 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3016577935 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 79.xbar_error_and_unmapped_add r.3016577935 |
| Directory | /workspace/79.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/79.xbar_error_random.402249281 |
| Short name | T1377 |
| Test name | |
| Test status | |
| Simulation time | 1575081239 ps |
| CPU time | 60.18 seconds |
| Started | Jun 29 08:28:11 PM PDT 24 |
| Finished | Jun 29 08:29:12 PM PDT 24 |
| Peak memory | 574480 kb |
| Host | smart-0828c609-4630-4f73-bdd1-5eaf86ebd8e3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=402249281 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 79.xbar_error_random.402249281 |
| Directory | /workspace/79.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/79.xbar_random.403387207 |
| Short name | T568 |
| Test name | |
| Test status | |
| Simulation time | 962741384 ps |
| CPU time | 34.56 seconds |
| Started | Jun 29 08:28:05 PM PDT 24 |
| Finished | Jun 29 08:28:40 PM PDT 24 |
| Peak memory | 575308 kb |
| Host | smart-09cbbb14-e217-4456-9948-930c70adba08 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=403387207 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 79.xbar_random.403387207 |
| Directory | /workspace/79.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/79.xbar_random_large_delays.177934458 |
| Short name | T2817 |
| Test name | |
| Test status | |
| Simulation time | 50302678065 ps |
| CPU time | 555.72 seconds |
| Started | Jun 29 08:28:05 PM PDT 24 |
| Finished | Jun 29 08:37:21 PM PDT 24 |
| Peak memory | 575392 kb |
| Host | smart-09c5c217-b6b3-4ca9-ad8a-3ed4f477169f |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=177934458 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 79.xbar_random_large_delays.177934458 |
| Directory | /workspace/79.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/79.xbar_random_slow_rsp.324211093 |
| Short name | T1870 |
| Test name | |
| Test status | |
| Simulation time | 39760539232 ps |
| CPU time | 717.1 seconds |
| Started | Jun 29 08:28:02 PM PDT 24 |
| Finished | Jun 29 08:40:00 PM PDT 24 |
| Peak memory | 574320 kb |
| Host | smart-0a30804f-a101-4dc1-a54f-256c9eb8c5cf |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=324211093 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 79.xbar_random_slow_rsp.324211093 |
| Directory | /workspace/79.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/79.xbar_random_zero_delays.595665529 |
| Short name | T1489 |
| Test name | |
| Test status | |
| Simulation time | 431078529 ps |
| CPU time | 39.23 seconds |
| Started | Jun 29 08:28:02 PM PDT 24 |
| Finished | Jun 29 08:28:42 PM PDT 24 |
| Peak memory | 575320 kb |
| Host | smart-3d6cf7f8-ee19-4b78-8c56-9f2006eedec9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=595665529 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 79.xbar_random_zero_dela ys.595665529 |
| Directory | /workspace/79.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/79.xbar_same_source.2007689029 |
| Short name | T1649 |
| Test name | |
| Test status | |
| Simulation time | 1713140974 ps |
| CPU time | 52.14 seconds |
| Started | Jun 29 08:28:00 PM PDT 24 |
| Finished | Jun 29 08:28:52 PM PDT 24 |
| Peak memory | 575320 kb |
| Host | smart-79c135fc-bf3b-45c6-8f92-bd15093c2a8e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2007689029 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 79.xbar_same_source.2007689029 |
| Directory | /workspace/79.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/79.xbar_smoke.3868647151 |
| Short name | T2107 |
| Test name | |
| Test status | |
| Simulation time | 190938941 ps |
| CPU time | 9.37 seconds |
| Started | Jun 29 08:28:04 PM PDT 24 |
| Finished | Jun 29 08:28:14 PM PDT 24 |
| Peak memory | 565972 kb |
| Host | smart-f3ce029e-7653-42f3-9912-f0553132e3e4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3868647151 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 79.xbar_smoke.3868647151 |
| Directory | /workspace/79.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/79.xbar_smoke_large_delays.1175712675 |
| Short name | T2228 |
| Test name | |
| Test status | |
| Simulation time | 8104217344 ps |
| CPU time | 85.33 seconds |
| Started | Jun 29 08:28:04 PM PDT 24 |
| Finished | Jun 29 08:29:30 PM PDT 24 |
| Peak memory | 574332 kb |
| Host | smart-34a333c2-8a67-4117-86cb-17c1b57b7cb6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1175712675 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 79.xbar_smoke_large_delays.1175712675 |
| Directory | /workspace/79.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/79.xbar_smoke_slow_rsp.2072290441 |
| Short name | T1518 |
| Test name | |
| Test status | |
| Simulation time | 6225556364 ps |
| CPU time | 106.02 seconds |
| Started | Jun 29 08:28:01 PM PDT 24 |
| Finished | Jun 29 08:29:48 PM PDT 24 |
| Peak memory | 574300 kb |
| Host | smart-82b1fd3e-1fb1-453c-93d1-50e01cb96f61 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2072290441 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 79.xbar_smoke_slow_rsp.2072290441 |
| Directory | /workspace/79.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/79.xbar_smoke_zero_delays.676863510 |
| Short name | T2237 |
| Test name | |
| Test status | |
| Simulation time | 53701661 ps |
| CPU time | 6.94 seconds |
| Started | Jun 29 08:28:01 PM PDT 24 |
| Finished | Jun 29 08:28:09 PM PDT 24 |
| Peak memory | 574268 kb |
| Host | smart-cbd89e79-d011-4185-b430-8728026544b4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=676863510 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 79.xbar_smoke_zero_delays .676863510 |
| Directory | /workspace/79.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/79.xbar_stress_all.2467177657 |
| Short name | T629 |
| Test name | |
| Test status | |
| Simulation time | 3705970885 ps |
| CPU time | 152.49 seconds |
| Started | Jun 29 08:28:09 PM PDT 24 |
| Finished | Jun 29 08:30:42 PM PDT 24 |
| Peak memory | 575504 kb |
| Host | smart-c7bdb9ee-b7d3-4f6c-bbf2-869c16b73bb8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2467177657 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 79.xbar_stress_all.2467177657 |
| Directory | /workspace/79.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/79.xbar_stress_all_with_error.4169519025 |
| Short name | T2612 |
| Test name | |
| Test status | |
| Simulation time | 9389335411 ps |
| CPU time | 356.74 seconds |
| Started | Jun 29 08:28:08 PM PDT 24 |
| Finished | Jun 29 08:34:05 PM PDT 24 |
| Peak memory | 574380 kb |
| Host | smart-de3b6017-6e70-41f1-9dd4-0e805270ea80 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4169519025 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 79.xbar_stress_all_with_error.4169519025 |
| Directory | /workspace/79.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/79.xbar_stress_all_with_rand_reset.1625354096 |
| Short name | T2819 |
| Test name | |
| Test status | |
| Simulation time | 5048294052 ps |
| CPU time | 520.27 seconds |
| Started | Jun 29 08:28:08 PM PDT 24 |
| Finished | Jun 29 08:36:48 PM PDT 24 |
| Peak memory | 575516 kb |
| Host | smart-ae9eb890-9696-4c6e-a562-e4f3e8b0b1a8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1625354096 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 79.xbar_stress_all _with_rand_reset.1625354096 |
| Directory | /workspace/79.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/79.xbar_stress_all_with_reset_error.3766168625 |
| Short name | T815 |
| Test name | |
| Test status | |
| Simulation time | 6060437281 ps |
| CPU time | 652.04 seconds |
| Started | Jun 29 08:28:10 PM PDT 24 |
| Finished | Jun 29 08:39:02 PM PDT 24 |
| Peak memory | 577932 kb |
| Host | smart-c01ca0d9-f207-4cc1-b84a-0ea4dfaa7ee9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3766168625 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 79.xbar_stress_al l_with_reset_error.3766168625 |
| Directory | /workspace/79.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/79.xbar_unmapped_addr.3299832551 |
| Short name | T2287 |
| Test name | |
| Test status | |
| Simulation time | 291409943 ps |
| CPU time | 39.09 seconds |
| Started | Jun 29 08:28:12 PM PDT 24 |
| Finished | Jun 29 08:28:51 PM PDT 24 |
| Peak memory | 575336 kb |
| Host | smart-3e24f662-04e4-4985-931a-511a48a84b7f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3299832551 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 79.xbar_unmapped_addr.3299832551 |
| Directory | /workspace/79.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/8.chip_csr_rw.1792389154 |
| Short name | T1583 |
| Test name | |
| Test status | |
| Simulation time | 3200978648 ps |
| CPU time | 271.93 seconds |
| Started | Jun 29 08:13:40 PM PDT 24 |
| Finished | Jun 29 08:18:13 PM PDT 24 |
| Peak memory | 597128 kb |
| Host | smart-a5be0332-4bd8-43d9-8343-4d3537ec9882 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1792389154 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.chip_csr_rw.1792389154 |
| Directory | /workspace/8.chip_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/8.chip_same_csr_outstanding.3455560098 |
| Short name | T1853 |
| Test name | |
| Test status | |
| Simulation time | 16844310664 ps |
| CPU time | 1703.29 seconds |
| Started | Jun 29 08:13:11 PM PDT 24 |
| Finished | Jun 29 08:41:35 PM PDT 24 |
| Peak memory | 592016 kb |
| Host | smart-bfa67c62-5fe3-4dc5-a609-5c740150c080 |
| User | root |
| Command | /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +run_same_csr_outstanding +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3455560098 -assert nopostproc +UVM_TE STNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb - cm_log /dev/null -cm_name 8.chip_same_csr_outstanding.3455560098 |
| Directory | /workspace/8.chip_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/8.xbar_access_same_device.2019061269 |
| Short name | T2080 |
| Test name | |
| Test status | |
| Simulation time | 856483847 ps |
| CPU time | 68.45 seconds |
| Started | Jun 29 08:13:28 PM PDT 24 |
| Finished | Jun 29 08:14:37 PM PDT 24 |
| Peak memory | 575404 kb |
| Host | smart-04c51c8d-19ab-46b0-8864-c37273134042 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2019061269 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.xbar_access_same_device. 2019061269 |
| Directory | /workspace/8.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/8.xbar_access_same_device_slow_rsp.796492509 |
| Short name | T2196 |
| Test name | |
| Test status | |
| Simulation time | 24135798865 ps |
| CPU time | 417.24 seconds |
| Started | Jun 29 08:13:30 PM PDT 24 |
| Finished | Jun 29 08:20:28 PM PDT 24 |
| Peak memory | 575404 kb |
| Host | smart-55d9a5d5-05dd-4d1c-9901-21cd6eb14bff |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=796492509 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.xbar_access_same_de vice_slow_rsp.796492509 |
| Directory | /workspace/8.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/8.xbar_error_and_unmapped_addr.3992862861 |
| Short name | T1562 |
| Test name | |
| Test status | |
| Simulation time | 263474454 ps |
| CPU time | 13.95 seconds |
| Started | Jun 29 08:13:40 PM PDT 24 |
| Finished | Jun 29 08:13:54 PM PDT 24 |
| Peak memory | 573944 kb |
| Host | smart-a118e5e8-2b14-4e50-8725-d9fe0779c9b5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3992862861 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.xbar_error_and_unmapped_addr .3992862861 |
| Directory | /workspace/8.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/8.xbar_error_random.3477413679 |
| Short name | T1910 |
| Test name | |
| Test status | |
| Simulation time | 1067487892 ps |
| CPU time | 40.06 seconds |
| Started | Jun 29 08:13:30 PM PDT 24 |
| Finished | Jun 29 08:14:11 PM PDT 24 |
| Peak memory | 573872 kb |
| Host | smart-0e083eca-110b-41b8-8e97-6a0d30657d8d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3477413679 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.xbar_error_random.3477413679 |
| Directory | /workspace/8.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/8.xbar_random.300761797 |
| Short name | T1487 |
| Test name | |
| Test status | |
| Simulation time | 1580481994 ps |
| CPU time | 59.41 seconds |
| Started | Jun 29 08:13:20 PM PDT 24 |
| Finished | Jun 29 08:14:20 PM PDT 24 |
| Peak memory | 575300 kb |
| Host | smart-f5c6f3f4-313f-4802-be1d-ab7fbcb0673d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=300761797 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.xbar_random.300761797 |
| Directory | /workspace/8.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/8.xbar_random_large_delays.1984460743 |
| Short name | T2151 |
| Test name | |
| Test status | |
| Simulation time | 4805098497 ps |
| CPU time | 55.08 seconds |
| Started | Jun 29 08:13:33 PM PDT 24 |
| Finished | Jun 29 08:14:29 PM PDT 24 |
| Peak memory | 574340 kb |
| Host | smart-5dfe41c7-d2ad-4890-a645-b9e7b6118809 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1984460743 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.xbar_random_large_delays.1984460743 |
| Directory | /workspace/8.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/8.xbar_random_slow_rsp.4070982042 |
| Short name | T2359 |
| Test name | |
| Test status | |
| Simulation time | 33796621937 ps |
| CPU time | 639.54 seconds |
| Started | Jun 29 08:13:30 PM PDT 24 |
| Finished | Jun 29 08:24:10 PM PDT 24 |
| Peak memory | 575404 kb |
| Host | smart-88cd740c-0d00-4ac1-8ade-6d9f009bf170 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4070982042 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.xbar_random_slow_rsp.4070982042 |
| Directory | /workspace/8.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/8.xbar_random_zero_delays.3970276756 |
| Short name | T2615 |
| Test name | |
| Test status | |
| Simulation time | 275578198 ps |
| CPU time | 26.97 seconds |
| Started | Jun 29 08:13:30 PM PDT 24 |
| Finished | Jun 29 08:13:58 PM PDT 24 |
| Peak memory | 575304 kb |
| Host | smart-9eaf2b6e-1dc1-4478-84fc-66f858d7839f |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3970276756 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.xbar_random_zero_dela ys.3970276756 |
| Directory | /workspace/8.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/8.xbar_same_source.3266896212 |
| Short name | T2531 |
| Test name | |
| Test status | |
| Simulation time | 1354715466 ps |
| CPU time | 43.12 seconds |
| Started | Jun 29 08:13:34 PM PDT 24 |
| Finished | Jun 29 08:14:17 PM PDT 24 |
| Peak memory | 574196 kb |
| Host | smart-4377cf85-6117-41a2-85be-773cd3852569 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3266896212 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.xbar_same_source.3266896212 |
| Directory | /workspace/8.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/8.xbar_smoke.3445796709 |
| Short name | T1873 |
| Test name | |
| Test status | |
| Simulation time | 49502851 ps |
| CPU time | 6.22 seconds |
| Started | Jun 29 08:13:21 PM PDT 24 |
| Finished | Jun 29 08:13:27 PM PDT 24 |
| Peak memory | 574252 kb |
| Host | smart-1b2c0e66-b055-4d74-a28e-0bf22b4d194f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3445796709 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.xbar_smoke.3445796709 |
| Directory | /workspace/8.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/8.xbar_smoke_large_delays.681077471 |
| Short name | T2200 |
| Test name | |
| Test status | |
| Simulation time | 7388496408 ps |
| CPU time | 75.05 seconds |
| Started | Jun 29 08:13:21 PM PDT 24 |
| Finished | Jun 29 08:14:36 PM PDT 24 |
| Peak memory | 566088 kb |
| Host | smart-3af40f2a-1088-4b72-9db0-5b99145ce110 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=681077471 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.xbar_smoke_large_delays.681077471 |
| Directory | /workspace/8.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/8.xbar_smoke_slow_rsp.3451217546 |
| Short name | T1996 |
| Test name | |
| Test status | |
| Simulation time | 6026601745 ps |
| CPU time | 106.04 seconds |
| Started | Jun 29 08:13:21 PM PDT 24 |
| Finished | Jun 29 08:15:08 PM PDT 24 |
| Peak memory | 574324 kb |
| Host | smart-f5fa81ee-2ba1-4724-a980-2bce71d4a9a2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3451217546 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.xbar_smoke_slow_rsp.3451217546 |
| Directory | /workspace/8.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/8.xbar_smoke_zero_delays.3113544843 |
| Short name | T1287 |
| Test name | |
| Test status | |
| Simulation time | 38511955 ps |
| CPU time | 6.75 seconds |
| Started | Jun 29 08:13:56 PM PDT 24 |
| Finished | Jun 29 08:14:03 PM PDT 24 |
| Peak memory | 574268 kb |
| Host | smart-06869bb6-6984-4ee5-ad23-c3864cc474ac |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3113544843 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.xbar_smoke_zero_delays .3113544843 |
| Directory | /workspace/8.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/8.xbar_stress_all.3003388463 |
| Short name | T514 |
| Test name | |
| Test status | |
| Simulation time | 1917167989 ps |
| CPU time | 188.79 seconds |
| Started | Jun 29 08:13:39 PM PDT 24 |
| Finished | Jun 29 08:16:48 PM PDT 24 |
| Peak memory | 575436 kb |
| Host | smart-6bf759bf-8e98-4768-9208-af6c994af2f3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3003388463 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.xbar_stress_all.3003388463 |
| Directory | /workspace/8.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/8.xbar_stress_all_with_error.3432757144 |
| Short name | T2653 |
| Test name | |
| Test status | |
| Simulation time | 431837616 ps |
| CPU time | 46.34 seconds |
| Started | Jun 29 08:13:38 PM PDT 24 |
| Finished | Jun 29 08:14:25 PM PDT 24 |
| Peak memory | 574520 kb |
| Host | smart-32420088-e9a7-4d52-bf0b-642b1bebf004 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3432757144 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.xbar_stress_all_with_error.3432757144 |
| Directory | /workspace/8.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/8.xbar_stress_all_with_rand_reset.3350168508 |
| Short name | T1884 |
| Test name | |
| Test status | |
| Simulation time | 92085615 ps |
| CPU time | 17.39 seconds |
| Started | Jun 29 08:13:38 PM PDT 24 |
| Finished | Jun 29 08:13:55 PM PDT 24 |
| Peak memory | 574376 kb |
| Host | smart-b0f138f2-6a99-481f-a9e8-5b6a2d4342d4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3350168508 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.xbar_stress_all_ with_rand_reset.3350168508 |
| Directory | /workspace/8.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/8.xbar_stress_all_with_reset_error.473240056 |
| Short name | T2166 |
| Test name | |
| Test status | |
| Simulation time | 1754641100 ps |
| CPU time | 242.2 seconds |
| Started | Jun 29 08:13:39 PM PDT 24 |
| Finished | Jun 29 08:17:41 PM PDT 24 |
| Peak memory | 574400 kb |
| Host | smart-00a890a8-0984-4dc9-98d8-1b1784769b1b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=473240056 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.xbar_stress_all_ with_reset_error.473240056 |
| Directory | /workspace/8.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/8.xbar_unmapped_addr.4220071225 |
| Short name | T2089 |
| Test name | |
| Test status | |
| Simulation time | 667723545 ps |
| CPU time | 32.48 seconds |
| Started | Jun 29 08:13:34 PM PDT 24 |
| Finished | Jun 29 08:14:07 PM PDT 24 |
| Peak memory | 575324 kb |
| Host | smart-f543e555-7795-4b15-97a1-ff11d2283421 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4220071225 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.xbar_unmapped_addr.4220071225 |
| Directory | /workspace/8.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/80.xbar_access_same_device.1617947898 |
| Short name | T1904 |
| Test name | |
| Test status | |
| Simulation time | 1589272414 ps |
| CPU time | 70.76 seconds |
| Started | Jun 29 08:28:14 PM PDT 24 |
| Finished | Jun 29 08:29:25 PM PDT 24 |
| Peak memory | 574232 kb |
| Host | smart-efa80c13-5499-478f-b883-a879c77bd718 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1617947898 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 80.xbar_access_same_device .1617947898 |
| Directory | /workspace/80.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/80.xbar_access_same_device_slow_rsp.1207342593 |
| Short name | T1614 |
| Test name | |
| Test status | |
| Simulation time | 118057470138 ps |
| CPU time | 1949.47 seconds |
| Started | Jun 29 08:28:15 PM PDT 24 |
| Finished | Jun 29 09:00:45 PM PDT 24 |
| Peak memory | 575440 kb |
| Host | smart-5f006628-9dd7-4eee-8e33-962846a7fd28 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1207342593 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 80.xbar_access_same_ device_slow_rsp.1207342593 |
| Directory | /workspace/80.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/80.xbar_error_and_unmapped_addr.3746285624 |
| Short name | T2652 |
| Test name | |
| Test status | |
| Simulation time | 214028227 ps |
| CPU time | 11.42 seconds |
| Started | Jun 29 08:28:16 PM PDT 24 |
| Finished | Jun 29 08:28:27 PM PDT 24 |
| Peak memory | 573884 kb |
| Host | smart-9a3a5816-3d38-461e-9aa0-9e93bf8dc115 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3746285624 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 80.xbar_error_and_unmapped_add r.3746285624 |
| Directory | /workspace/80.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/80.xbar_error_random.206634750 |
| Short name | T1891 |
| Test name | |
| Test status | |
| Simulation time | 656167223 ps |
| CPU time | 62.59 seconds |
| Started | Jun 29 08:28:13 PM PDT 24 |
| Finished | Jun 29 08:29:16 PM PDT 24 |
| Peak memory | 574504 kb |
| Host | smart-2ea5f2eb-fd01-4dee-ba72-eb5d08ef729f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=206634750 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 80.xbar_error_random.206634750 |
| Directory | /workspace/80.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/80.xbar_random.1129309366 |
| Short name | T1669 |
| Test name | |
| Test status | |
| Simulation time | 679292862 ps |
| CPU time | 26.09 seconds |
| Started | Jun 29 08:28:10 PM PDT 24 |
| Finished | Jun 29 08:28:36 PM PDT 24 |
| Peak memory | 574240 kb |
| Host | smart-dc8b511d-cb9d-4cf1-96ee-a21d0b697a4b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1129309366 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 80.xbar_random.1129309366 |
| Directory | /workspace/80.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/80.xbar_random_large_delays.353137825 |
| Short name | T1965 |
| Test name | |
| Test status | |
| Simulation time | 66690994993 ps |
| CPU time | 701.06 seconds |
| Started | Jun 29 08:28:15 PM PDT 24 |
| Finished | Jun 29 08:39:56 PM PDT 24 |
| Peak memory | 575380 kb |
| Host | smart-3216ee4b-0f4c-4096-b3d5-36f7d17be5cd |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=353137825 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 80.xbar_random_large_delays.353137825 |
| Directory | /workspace/80.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/80.xbar_random_slow_rsp.1890717646 |
| Short name | T2073 |
| Test name | |
| Test status | |
| Simulation time | 35801331669 ps |
| CPU time | 609.08 seconds |
| Started | Jun 29 08:28:12 PM PDT 24 |
| Finished | Jun 29 08:38:22 PM PDT 24 |
| Peak memory | 575400 kb |
| Host | smart-8c672d71-dfed-47ab-a650-c43207ad2927 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1890717646 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 80.xbar_random_slow_rsp.1890717646 |
| Directory | /workspace/80.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/80.xbar_random_zero_delays.3078238342 |
| Short name | T549 |
| Test name | |
| Test status | |
| Simulation time | 188788699 ps |
| CPU time | 20.18 seconds |
| Started | Jun 29 08:28:12 PM PDT 24 |
| Finished | Jun 29 08:28:32 PM PDT 24 |
| Peak memory | 574228 kb |
| Host | smart-21ce2664-c8b3-4287-a824-78bb5716b387 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3078238342 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 80.xbar_random_zero_del ays.3078238342 |
| Directory | /workspace/80.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/80.xbar_same_source.1575747817 |
| Short name | T472 |
| Test name | |
| Test status | |
| Simulation time | 299328458 ps |
| CPU time | 29.08 seconds |
| Started | Jun 29 08:28:14 PM PDT 24 |
| Finished | Jun 29 08:28:44 PM PDT 24 |
| Peak memory | 575436 kb |
| Host | smart-0de8d0c4-de02-4478-bab2-23f6bc1530d8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1575747817 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 80.xbar_same_source.1575747817 |
| Directory | /workspace/80.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/80.xbar_smoke.2984085175 |
| Short name | T2379 |
| Test name | |
| Test status | |
| Simulation time | 170027926 ps |
| CPU time | 8.97 seconds |
| Started | Jun 29 08:28:05 PM PDT 24 |
| Finished | Jun 29 08:28:14 PM PDT 24 |
| Peak memory | 566016 kb |
| Host | smart-ca8b661e-b10a-4fa5-ba23-05d475fdcc03 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2984085175 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 80.xbar_smoke.2984085175 |
| Directory | /workspace/80.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/80.xbar_smoke_large_delays.3250090864 |
| Short name | T533 |
| Test name | |
| Test status | |
| Simulation time | 9114986933 ps |
| CPU time | 95.02 seconds |
| Started | Jun 29 08:28:10 PM PDT 24 |
| Finished | Jun 29 08:29:45 PM PDT 24 |
| Peak memory | 566100 kb |
| Host | smart-1b3947ba-d0c9-457c-ba1b-616ceef31582 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3250090864 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 80.xbar_smoke_large_delays.3250090864 |
| Directory | /workspace/80.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/80.xbar_smoke_slow_rsp.534354643 |
| Short name | T2451 |
| Test name | |
| Test status | |
| Simulation time | 4073373968 ps |
| CPU time | 74.12 seconds |
| Started | Jun 29 08:28:10 PM PDT 24 |
| Finished | Jun 29 08:29:24 PM PDT 24 |
| Peak memory | 574140 kb |
| Host | smart-de22e78f-304a-4146-bd26-6875d0db5187 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=534354643 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 80.xbar_smoke_slow_rsp.534354643 |
| Directory | /workspace/80.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/80.xbar_smoke_zero_delays.1663159551 |
| Short name | T1397 |
| Test name | |
| Test status | |
| Simulation time | 44956107 ps |
| CPU time | 6.63 seconds |
| Started | Jun 29 08:28:09 PM PDT 24 |
| Finished | Jun 29 08:28:16 PM PDT 24 |
| Peak memory | 574232 kb |
| Host | smart-1ee58ee8-bb6f-42e2-8ed1-08d07111cf07 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1663159551 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 80.xbar_smoke_zero_delay s.1663159551 |
| Directory | /workspace/80.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/80.xbar_stress_all.322990766 |
| Short name | T480 |
| Test name | |
| Test status | |
| Simulation time | 2789419744 ps |
| CPU time | 281.41 seconds |
| Started | Jun 29 08:28:15 PM PDT 24 |
| Finished | Jun 29 08:32:57 PM PDT 24 |
| Peak memory | 575500 kb |
| Host | smart-601cbb36-b258-4636-9486-0d061098316d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=322990766 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 80.xbar_stress_all.322990766 |
| Directory | /workspace/80.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/80.xbar_stress_all_with_error.1376238988 |
| Short name | T2598 |
| Test name | |
| Test status | |
| Simulation time | 489734587 ps |
| CPU time | 45.56 seconds |
| Started | Jun 29 08:28:23 PM PDT 24 |
| Finished | Jun 29 08:29:09 PM PDT 24 |
| Peak memory | 574024 kb |
| Host | smart-14cafdc7-3ae5-48d7-a9b8-daef76cd752c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1376238988 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 80.xbar_stress_all_with_error.1376238988 |
| Directory | /workspace/80.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/80.xbar_stress_all_with_rand_reset.771646633 |
| Short name | T2858 |
| Test name | |
| Test status | |
| Simulation time | 306375259 ps |
| CPU time | 151.83 seconds |
| Started | Jun 29 08:28:21 PM PDT 24 |
| Finished | Jun 29 08:30:53 PM PDT 24 |
| Peak memory | 574316 kb |
| Host | smart-deaf6030-a667-4c99-9a61-75c16e0a4998 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=771646633 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_res et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 80.xbar_stress_all_ with_rand_reset.771646633 |
| Directory | /workspace/80.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/80.xbar_stress_all_with_reset_error.3890624470 |
| Short name | T1466 |
| Test name | |
| Test status | |
| Simulation time | 176382593 ps |
| CPU time | 43.87 seconds |
| Started | Jun 29 08:28:23 PM PDT 24 |
| Finished | Jun 29 08:29:07 PM PDT 24 |
| Peak memory | 574296 kb |
| Host | smart-48a800aa-ef41-47b0-88a8-00afa7c19b83 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3890624470 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 80.xbar_stress_al l_with_reset_error.3890624470 |
| Directory | /workspace/80.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/80.xbar_unmapped_addr.2913121291 |
| Short name | T1830 |
| Test name | |
| Test status | |
| Simulation time | 324217937 ps |
| CPU time | 40.73 seconds |
| Started | Jun 29 08:28:14 PM PDT 24 |
| Finished | Jun 29 08:28:55 PM PDT 24 |
| Peak memory | 575376 kb |
| Host | smart-7d5356dd-f993-4c97-b97e-38ebb20dca01 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2913121291 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 80.xbar_unmapped_addr.2913121291 |
| Directory | /workspace/80.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/81.xbar_access_same_device.2781847965 |
| Short name | T2421 |
| Test name | |
| Test status | |
| Simulation time | 593079655 ps |
| CPU time | 30.4 seconds |
| Started | Jun 29 08:28:24 PM PDT 24 |
| Finished | Jun 29 08:28:54 PM PDT 24 |
| Peak memory | 575288 kb |
| Host | smart-f72fbd8a-d17d-4b33-bca3-70e21d9e05fc |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2781847965 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 81.xbar_access_same_device .2781847965 |
| Directory | /workspace/81.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/81.xbar_access_same_device_slow_rsp.3569271099 |
| Short name | T2705 |
| Test name | |
| Test status | |
| Simulation time | 100071748657 ps |
| CPU time | 1673.57 seconds |
| Started | Jun 29 08:28:20 PM PDT 24 |
| Finished | Jun 29 08:56:14 PM PDT 24 |
| Peak memory | 575496 kb |
| Host | smart-1efdfc91-1a15-4856-a489-bd74c70073fb |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3569271099 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 81.xbar_access_same_ device_slow_rsp.3569271099 |
| Directory | /workspace/81.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/81.xbar_error_and_unmapped_addr.1333656337 |
| Short name | T1675 |
| Test name | |
| Test status | |
| Simulation time | 1457711926 ps |
| CPU time | 60.94 seconds |
| Started | Jun 29 08:28:26 PM PDT 24 |
| Finished | Jun 29 08:29:27 PM PDT 24 |
| Peak memory | 574464 kb |
| Host | smart-4beeb6cd-5984-4f67-928e-3697d10e7330 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1333656337 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 81.xbar_error_and_unmapped_add r.1333656337 |
| Directory | /workspace/81.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/81.xbar_error_random.3755838804 |
| Short name | T2658 |
| Test name | |
| Test status | |
| Simulation time | 1452912107 ps |
| CPU time | 56.05 seconds |
| Started | Jun 29 08:28:21 PM PDT 24 |
| Finished | Jun 29 08:29:17 PM PDT 24 |
| Peak memory | 574256 kb |
| Host | smart-508afbcf-b39e-4ab3-b436-cf65ad9df6a9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3755838804 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 81.xbar_error_random.3755838804 |
| Directory | /workspace/81.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/81.xbar_random.955792869 |
| Short name | T579 |
| Test name | |
| Test status | |
| Simulation time | 152010692 ps |
| CPU time | 16.02 seconds |
| Started | Jun 29 08:28:21 PM PDT 24 |
| Finished | Jun 29 08:28:37 PM PDT 24 |
| Peak memory | 575300 kb |
| Host | smart-2e878227-610a-4089-9ef9-9ef1992ddce6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=955792869 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 81.xbar_random.955792869 |
| Directory | /workspace/81.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/81.xbar_random_large_delays.2080716604 |
| Short name | T2492 |
| Test name | |
| Test status | |
| Simulation time | 20810612424 ps |
| CPU time | 209.39 seconds |
| Started | Jun 29 08:28:26 PM PDT 24 |
| Finished | Jun 29 08:31:55 PM PDT 24 |
| Peak memory | 574280 kb |
| Host | smart-cf607b24-36f5-4a41-a2ba-c92c7a9c7fd7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2080716604 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 81.xbar_random_large_delays.2080716604 |
| Directory | /workspace/81.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/81.xbar_random_slow_rsp.160236820 |
| Short name | T2051 |
| Test name | |
| Test status | |
| Simulation time | 64011652375 ps |
| CPU time | 1082.02 seconds |
| Started | Jun 29 08:28:23 PM PDT 24 |
| Finished | Jun 29 08:46:26 PM PDT 24 |
| Peak memory | 575388 kb |
| Host | smart-fea90425-c3cd-4165-b885-3c41fa810d04 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=160236820 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 81.xbar_random_slow_rsp.160236820 |
| Directory | /workspace/81.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/81.xbar_random_zero_delays.3604734399 |
| Short name | T1972 |
| Test name | |
| Test status | |
| Simulation time | 218096265 ps |
| CPU time | 23.5 seconds |
| Started | Jun 29 08:28:20 PM PDT 24 |
| Finished | Jun 29 08:28:43 PM PDT 24 |
| Peak memory | 575304 kb |
| Host | smart-2aaa8f75-f7b3-4ba1-a7cd-9865a76e7d0e |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3604734399 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 81.xbar_random_zero_del ays.3604734399 |
| Directory | /workspace/81.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/81.xbar_same_source.1619268418 |
| Short name | T1361 |
| Test name | |
| Test status | |
| Simulation time | 64126667 ps |
| CPU time | 8.64 seconds |
| Started | Jun 29 08:28:21 PM PDT 24 |
| Finished | Jun 29 08:28:30 PM PDT 24 |
| Peak memory | 575296 kb |
| Host | smart-5d7e9945-76a4-427d-8a7e-951c1bbd3c55 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1619268418 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 81.xbar_same_source.1619268418 |
| Directory | /workspace/81.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/81.xbar_smoke.771212075 |
| Short name | T1678 |
| Test name | |
| Test status | |
| Simulation time | 173156589 ps |
| CPU time | 8.34 seconds |
| Started | Jun 29 08:28:23 PM PDT 24 |
| Finished | Jun 29 08:28:31 PM PDT 24 |
| Peak memory | 574228 kb |
| Host | smart-d3ae04d7-a873-43e7-b53e-a7564658d59f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=771212075 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 81.xbar_smoke.771212075 |
| Directory | /workspace/81.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/81.xbar_smoke_large_delays.1626173869 |
| Short name | T2825 |
| Test name | |
| Test status | |
| Simulation time | 9485133955 ps |
| CPU time | 102.84 seconds |
| Started | Jun 29 08:28:23 PM PDT 24 |
| Finished | Jun 29 08:30:06 PM PDT 24 |
| Peak memory | 574316 kb |
| Host | smart-d79836fd-cb2d-4b6e-ba95-85345ce2377a |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1626173869 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 81.xbar_smoke_large_delays.1626173869 |
| Directory | /workspace/81.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/81.xbar_smoke_slow_rsp.2093664647 |
| Short name | T2541 |
| Test name | |
| Test status | |
| Simulation time | 5396759166 ps |
| CPU time | 94.43 seconds |
| Started | Jun 29 08:28:26 PM PDT 24 |
| Finished | Jun 29 08:30:01 PM PDT 24 |
| Peak memory | 566040 kb |
| Host | smart-0e09f4eb-e795-4844-83b9-ec745c0f2a0d |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2093664647 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 81.xbar_smoke_slow_rsp.2093664647 |
| Directory | /workspace/81.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/81.xbar_smoke_zero_delays.3148266746 |
| Short name | T1385 |
| Test name | |
| Test status | |
| Simulation time | 48293734 ps |
| CPU time | 7.07 seconds |
| Started | Jun 29 08:28:23 PM PDT 24 |
| Finished | Jun 29 08:28:31 PM PDT 24 |
| Peak memory | 574260 kb |
| Host | smart-f09004b9-a8b0-4b9f-b635-5a2bd1b4f5ee |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3148266746 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 81.xbar_smoke_zero_delay s.3148266746 |
| Directory | /workspace/81.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/81.xbar_stress_all.2244560549 |
| Short name | T2452 |
| Test name | |
| Test status | |
| Simulation time | 6648601918 ps |
| CPU time | 263.5 seconds |
| Started | Jun 29 08:28:23 PM PDT 24 |
| Finished | Jun 29 08:32:46 PM PDT 24 |
| Peak memory | 575512 kb |
| Host | smart-3fe29e09-2b2b-4740-9b8a-32d25c7739dd |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2244560549 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 81.xbar_stress_all.2244560549 |
| Directory | /workspace/81.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/81.xbar_stress_all_with_error.925277107 |
| Short name | T2591 |
| Test name | |
| Test status | |
| Simulation time | 7035354970 ps |
| CPU time | 314.36 seconds |
| Started | Jun 29 08:28:29 PM PDT 24 |
| Finished | Jun 29 08:33:44 PM PDT 24 |
| Peak memory | 574456 kb |
| Host | smart-190bc9d1-8980-4afe-b029-0a84c5d40a16 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=925277107 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 81.xbar_stress_all_with_error.925277107 |
| Directory | /workspace/81.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/81.xbar_stress_all_with_rand_reset.1159077540 |
| Short name | T2312 |
| Test name | |
| Test status | |
| Simulation time | 17933770788 ps |
| CPU time | 819.68 seconds |
| Started | Jun 29 08:28:31 PM PDT 24 |
| Finished | Jun 29 08:42:11 PM PDT 24 |
| Peak memory | 575512 kb |
| Host | smart-d7761eaf-ca33-40b4-85fa-2dcaa350bdc0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1159077540 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 81.xbar_stress_all _with_rand_reset.1159077540 |
| Directory | /workspace/81.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/81.xbar_stress_all_with_reset_error.2452310271 |
| Short name | T2515 |
| Test name | |
| Test status | |
| Simulation time | 209119456 ps |
| CPU time | 85.45 seconds |
| Started | Jun 29 08:28:29 PM PDT 24 |
| Finished | Jun 29 08:29:54 PM PDT 24 |
| Peak memory | 574632 kb |
| Host | smart-ac2f99de-59ab-4eaa-8ee5-60c02dc01d4b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2452310271 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 81.xbar_stress_al l_with_reset_error.2452310271 |
| Directory | /workspace/81.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/81.xbar_unmapped_addr.1302423704 |
| Short name | T2286 |
| Test name | |
| Test status | |
| Simulation time | 54180867 ps |
| CPU time | 9.82 seconds |
| Started | Jun 29 08:28:22 PM PDT 24 |
| Finished | Jun 29 08:28:32 PM PDT 24 |
| Peak memory | 574312 kb |
| Host | smart-93635b1b-3c74-4045-9b9d-3972c305ed20 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1302423704 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 81.xbar_unmapped_addr.1302423704 |
| Directory | /workspace/81.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/82.xbar_access_same_device.3549363240 |
| Short name | T521 |
| Test name | |
| Test status | |
| Simulation time | 1669159454 ps |
| CPU time | 76.61 seconds |
| Started | Jun 29 08:28:29 PM PDT 24 |
| Finished | Jun 29 08:29:46 PM PDT 24 |
| Peak memory | 574240 kb |
| Host | smart-3e9c9c63-25fc-4d2b-af6c-b8c3640a190c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3549363240 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 82.xbar_access_same_device .3549363240 |
| Directory | /workspace/82.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/82.xbar_access_same_device_slow_rsp.1647912743 |
| Short name | T1843 |
| Test name | |
| Test status | |
| Simulation time | 49409391232 ps |
| CPU time | 873.56 seconds |
| Started | Jun 29 08:28:30 PM PDT 24 |
| Finished | Jun 29 08:43:04 PM PDT 24 |
| Peak memory | 575452 kb |
| Host | smart-e835b61f-0fdc-4c76-a20c-1a44ad6b4bf0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1647912743 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 82.xbar_access_same_ device_slow_rsp.1647912743 |
| Directory | /workspace/82.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/82.xbar_error_and_unmapped_addr.2608649298 |
| Short name | T2066 |
| Test name | |
| Test status | |
| Simulation time | 215041812 ps |
| CPU time | 25.47 seconds |
| Started | Jun 29 08:28:31 PM PDT 24 |
| Finished | Jun 29 08:28:57 PM PDT 24 |
| Peak memory | 574260 kb |
| Host | smart-90e3056b-6b7c-45fc-900b-6cdc3bf75a44 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2608649298 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 82.xbar_error_and_unmapped_add r.2608649298 |
| Directory | /workspace/82.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/82.xbar_error_random.2097940020 |
| Short name | T1923 |
| Test name | |
| Test status | |
| Simulation time | 1843021363 ps |
| CPU time | 57.62 seconds |
| Started | Jun 29 08:28:35 PM PDT 24 |
| Finished | Jun 29 08:29:34 PM PDT 24 |
| Peak memory | 573912 kb |
| Host | smart-0ff7260c-8406-49d2-a5fb-b75630715073 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2097940020 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 82.xbar_error_random.2097940020 |
| Directory | /workspace/82.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/82.xbar_random.698721562 |
| Short name | T2460 |
| Test name | |
| Test status | |
| Simulation time | 437090097 ps |
| CPU time | 42.78 seconds |
| Started | Jun 29 08:28:30 PM PDT 24 |
| Finished | Jun 29 08:29:13 PM PDT 24 |
| Peak memory | 574244 kb |
| Host | smart-7226e28d-8b19-40b8-b1b7-8d29abb95e81 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=698721562 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 82.xbar_random.698721562 |
| Directory | /workspace/82.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/82.xbar_random_large_delays.3155260424 |
| Short name | T631 |
| Test name | |
| Test status | |
| Simulation time | 55141506182 ps |
| CPU time | 597.79 seconds |
| Started | Jun 29 08:28:29 PM PDT 24 |
| Finished | Jun 29 08:38:27 PM PDT 24 |
| Peak memory | 575376 kb |
| Host | smart-726fda8d-2f49-4142-bbe4-e62402555aed |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3155260424 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 82.xbar_random_large_delays.3155260424 |
| Directory | /workspace/82.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/82.xbar_random_slow_rsp.2281104773 |
| Short name | T1328 |
| Test name | |
| Test status | |
| Simulation time | 8130746919 ps |
| CPU time | 145.51 seconds |
| Started | Jun 29 08:28:29 PM PDT 24 |
| Finished | Jun 29 08:30:55 PM PDT 24 |
| Peak memory | 575368 kb |
| Host | smart-02f84478-a09f-4149-aa06-0320e4fad804 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2281104773 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 82.xbar_random_slow_rsp.2281104773 |
| Directory | /workspace/82.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/82.xbar_random_zero_delays.2040508466 |
| Short name | T1632 |
| Test name | |
| Test status | |
| Simulation time | 489291270 ps |
| CPU time | 48.75 seconds |
| Started | Jun 29 08:28:30 PM PDT 24 |
| Finished | Jun 29 08:29:19 PM PDT 24 |
| Peak memory | 575300 kb |
| Host | smart-32ad1955-83e3-4762-989d-454cc8d0598d |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2040508466 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 82.xbar_random_zero_del ays.2040508466 |
| Directory | /workspace/82.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/82.xbar_same_source.591734439 |
| Short name | T1522 |
| Test name | |
| Test status | |
| Simulation time | 2747225389 ps |
| CPU time | 91.85 seconds |
| Started | Jun 29 08:28:30 PM PDT 24 |
| Finished | Jun 29 08:30:02 PM PDT 24 |
| Peak memory | 575364 kb |
| Host | smart-bb4232b6-9c2d-4249-8fa3-9bac4ea627e6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=591734439 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 82.xbar_same_source.591734439 |
| Directory | /workspace/82.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/82.xbar_smoke.971307296 |
| Short name | T1881 |
| Test name | |
| Test status | |
| Simulation time | 211543733 ps |
| CPU time | 9.02 seconds |
| Started | Jun 29 08:28:28 PM PDT 24 |
| Finished | Jun 29 08:28:37 PM PDT 24 |
| Peak memory | 574244 kb |
| Host | smart-0d1f11f1-2d0c-4bf4-b9fc-20e475449b13 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=971307296 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 82.xbar_smoke.971307296 |
| Directory | /workspace/82.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/82.xbar_smoke_large_delays.4201396235 |
| Short name | T2398 |
| Test name | |
| Test status | |
| Simulation time | 7207914274 ps |
| CPU time | 80.31 seconds |
| Started | Jun 29 08:28:27 PM PDT 24 |
| Finished | Jun 29 08:29:48 PM PDT 24 |
| Peak memory | 574152 kb |
| Host | smart-b6ffff88-b081-4187-8705-5e858f86995e |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4201396235 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 82.xbar_smoke_large_delays.4201396235 |
| Directory | /workspace/82.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/82.xbar_smoke_slow_rsp.2317045790 |
| Short name | T1327 |
| Test name | |
| Test status | |
| Simulation time | 4866030670 ps |
| CPU time | 85.53 seconds |
| Started | Jun 29 08:28:27 PM PDT 24 |
| Finished | Jun 29 08:29:53 PM PDT 24 |
| Peak memory | 566080 kb |
| Host | smart-f80171e3-9757-432e-9bc1-7ef26f4058e6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2317045790 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 82.xbar_smoke_slow_rsp.2317045790 |
| Directory | /workspace/82.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/82.xbar_smoke_zero_delays.3204357051 |
| Short name | T1395 |
| Test name | |
| Test status | |
| Simulation time | 56235919 ps |
| CPU time | 6.83 seconds |
| Started | Jun 29 08:28:36 PM PDT 24 |
| Finished | Jun 29 08:28:43 PM PDT 24 |
| Peak memory | 574248 kb |
| Host | smart-b3097d42-3de4-4e6d-8320-a44dcbfdcaa2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3204357051 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 82.xbar_smoke_zero_delay s.3204357051 |
| Directory | /workspace/82.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/82.xbar_stress_all.3031895981 |
| Short name | T410 |
| Test name | |
| Test status | |
| Simulation time | 13904100626 ps |
| CPU time | 512.31 seconds |
| Started | Jun 29 08:28:28 PM PDT 24 |
| Finished | Jun 29 08:37:00 PM PDT 24 |
| Peak memory | 575520 kb |
| Host | smart-09df044d-8918-4a18-9cb2-ce5504d4a2f1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3031895981 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 82.xbar_stress_all.3031895981 |
| Directory | /workspace/82.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/82.xbar_stress_all_with_error.2854618128 |
| Short name | T2529 |
| Test name | |
| Test status | |
| Simulation time | 532490780 ps |
| CPU time | 38.15 seconds |
| Started | Jun 29 08:28:35 PM PDT 24 |
| Finished | Jun 29 08:29:14 PM PDT 24 |
| Peak memory | 574500 kb |
| Host | smart-8fb5cd3a-ce9a-4e71-b72e-acff2abdae01 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2854618128 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 82.xbar_stress_all_with_error.2854618128 |
| Directory | /workspace/82.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/82.xbar_stress_all_with_rand_reset.994963184 |
| Short name | T2796 |
| Test name | |
| Test status | |
| Simulation time | 122875132 ps |
| CPU time | 86.31 seconds |
| Started | Jun 29 08:28:31 PM PDT 24 |
| Finished | Jun 29 08:29:58 PM PDT 24 |
| Peak memory | 575444 kb |
| Host | smart-102fff02-4272-4eda-aa05-61658ec5f9b4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=994963184 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_res et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 82.xbar_stress_all_ with_rand_reset.994963184 |
| Directory | /workspace/82.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/82.xbar_stress_all_with_reset_error.701374459 |
| Short name | T810 |
| Test name | |
| Test status | |
| Simulation time | 9462176636 ps |
| CPU time | 360.59 seconds |
| Started | Jun 29 08:28:37 PM PDT 24 |
| Finished | Jun 29 08:34:38 PM PDT 24 |
| Peak memory | 574736 kb |
| Host | smart-1dd4fcb3-1d75-4257-aea8-66588df170d2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=701374459 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 82.xbar_stress_all _with_reset_error.701374459 |
| Directory | /workspace/82.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/82.xbar_unmapped_addr.2337329013 |
| Short name | T2133 |
| Test name | |
| Test status | |
| Simulation time | 197789264 ps |
| CPU time | 27.16 seconds |
| Started | Jun 29 08:28:28 PM PDT 24 |
| Finished | Jun 29 08:28:55 PM PDT 24 |
| Peak memory | 574296 kb |
| Host | smart-640aa1ce-939d-4aa8-8b12-c5911181f4f9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2337329013 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 82.xbar_unmapped_addr.2337329013 |
| Directory | /workspace/82.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/83.xbar_access_same_device.4191526633 |
| Short name | T1724 |
| Test name | |
| Test status | |
| Simulation time | 598211232 ps |
| CPU time | 53.98 seconds |
| Started | Jun 29 08:28:57 PM PDT 24 |
| Finished | Jun 29 08:29:51 PM PDT 24 |
| Peak memory | 575308 kb |
| Host | smart-cda27e81-816e-4215-bf56-c3de8440d46b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4191526633 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 83.xbar_access_same_device .4191526633 |
| Directory | /workspace/83.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/83.xbar_access_same_device_slow_rsp.541515462 |
| Short name | T1475 |
| Test name | |
| Test status | |
| Simulation time | 72045422534 ps |
| CPU time | 1196.48 seconds |
| Started | Jun 29 08:28:56 PM PDT 24 |
| Finished | Jun 29 08:48:53 PM PDT 24 |
| Peak memory | 575468 kb |
| Host | smart-c2fda2df-f727-4455-ac8f-6eafb1bf2026 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=541515462 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 83.xbar_access_same_d evice_slow_rsp.541515462 |
| Directory | /workspace/83.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/83.xbar_error_and_unmapped_addr.1508651943 |
| Short name | T2181 |
| Test name | |
| Test status | |
| Simulation time | 1187287523 ps |
| CPU time | 52.63 seconds |
| Started | Jun 29 08:28:44 PM PDT 24 |
| Finished | Jun 29 08:29:38 PM PDT 24 |
| Peak memory | 574272 kb |
| Host | smart-f81ab5ab-c83f-4018-b7c3-51499b805168 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1508651943 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 83.xbar_error_and_unmapped_add r.1508651943 |
| Directory | /workspace/83.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/83.xbar_error_random.543836009 |
| Short name | T2570 |
| Test name | |
| Test status | |
| Simulation time | 1612666005 ps |
| CPU time | 59.11 seconds |
| Started | Jun 29 08:28:45 PM PDT 24 |
| Finished | Jun 29 08:29:45 PM PDT 24 |
| Peak memory | 574268 kb |
| Host | smart-b92ba963-c388-419e-b714-98b0051fa1a9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=543836009 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 83.xbar_error_random.543836009 |
| Directory | /workspace/83.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/83.xbar_random.1370552652 |
| Short name | T1941 |
| Test name | |
| Test status | |
| Simulation time | 2673808427 ps |
| CPU time | 90.85 seconds |
| Started | Jun 29 08:28:39 PM PDT 24 |
| Finished | Jun 29 08:30:11 PM PDT 24 |
| Peak memory | 574312 kb |
| Host | smart-c6a2b9fb-f7af-40c4-bf2f-90fdb4c932c8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1370552652 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 83.xbar_random.1370552652 |
| Directory | /workspace/83.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/83.xbar_random_large_delays.1980663167 |
| Short name | T1634 |
| Test name | |
| Test status | |
| Simulation time | 7805783582 ps |
| CPU time | 82.1 seconds |
| Started | Jun 29 08:28:39 PM PDT 24 |
| Finished | Jun 29 08:30:02 PM PDT 24 |
| Peak memory | 566112 kb |
| Host | smart-b80c4b9c-be49-44d6-973d-179bc48bcf75 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1980663167 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 83.xbar_random_large_delays.1980663167 |
| Directory | /workspace/83.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/83.xbar_random_slow_rsp.1167238170 |
| Short name | T2102 |
| Test name | |
| Test status | |
| Simulation time | 60680394404 ps |
| CPU time | 1016.79 seconds |
| Started | Jun 29 08:28:36 PM PDT 24 |
| Finished | Jun 29 08:45:34 PM PDT 24 |
| Peak memory | 575316 kb |
| Host | smart-150d05d9-8942-46fc-8bbc-01a42e33174f |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1167238170 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 83.xbar_random_slow_rsp.1167238170 |
| Directory | /workspace/83.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/83.xbar_random_zero_delays.2307082100 |
| Short name | T2406 |
| Test name | |
| Test status | |
| Simulation time | 165473775 ps |
| CPU time | 18.58 seconds |
| Started | Jun 29 08:28:38 PM PDT 24 |
| Finished | Jun 29 08:28:57 PM PDT 24 |
| Peak memory | 574228 kb |
| Host | smart-76f9baae-3ccb-48d2-b879-3bb39e7ae8bb |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2307082100 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 83.xbar_random_zero_del ays.2307082100 |
| Directory | /workspace/83.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/83.xbar_same_source.3067011158 |
| Short name | T1835 |
| Test name | |
| Test status | |
| Simulation time | 254950340 ps |
| CPU time | 21.68 seconds |
| Started | Jun 29 08:28:45 PM PDT 24 |
| Finished | Jun 29 08:29:07 PM PDT 24 |
| Peak memory | 574220 kb |
| Host | smart-8267134e-3dec-4e76-9176-559222f085fd |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3067011158 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 83.xbar_same_source.3067011158 |
| Directory | /workspace/83.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/83.xbar_smoke.2105251418 |
| Short name | T2065 |
| Test name | |
| Test status | |
| Simulation time | 206944275 ps |
| CPU time | 9.74 seconds |
| Started | Jun 29 08:28:39 PM PDT 24 |
| Finished | Jun 29 08:28:49 PM PDT 24 |
| Peak memory | 574260 kb |
| Host | smart-5736ebd1-c707-485e-8686-e0ced0a9030a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2105251418 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 83.xbar_smoke.2105251418 |
| Directory | /workspace/83.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/83.xbar_smoke_large_delays.1632109889 |
| Short name | T1499 |
| Test name | |
| Test status | |
| Simulation time | 9384521253 ps |
| CPU time | 103.49 seconds |
| Started | Jun 29 08:28:39 PM PDT 24 |
| Finished | Jun 29 08:30:23 PM PDT 24 |
| Peak memory | 574340 kb |
| Host | smart-f0c95c1c-cd5b-4859-afca-9b8202c11efd |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1632109889 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 83.xbar_smoke_large_delays.1632109889 |
| Directory | /workspace/83.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/83.xbar_smoke_slow_rsp.2748631056 |
| Short name | T1383 |
| Test name | |
| Test status | |
| Simulation time | 4171998665 ps |
| CPU time | 75.66 seconds |
| Started | Jun 29 08:28:39 PM PDT 24 |
| Finished | Jun 29 08:29:55 PM PDT 24 |
| Peak memory | 574196 kb |
| Host | smart-cdbb7cb7-691f-4777-861a-4920167e7955 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2748631056 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 83.xbar_smoke_slow_rsp.2748631056 |
| Directory | /workspace/83.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/83.xbar_smoke_zero_delays.1952145398 |
| Short name | T2530 |
| Test name | |
| Test status | |
| Simulation time | 43015392 ps |
| CPU time | 6.93 seconds |
| Started | Jun 29 08:28:37 PM PDT 24 |
| Finished | Jun 29 08:28:44 PM PDT 24 |
| Peak memory | 565968 kb |
| Host | smart-ae0acde1-4ea7-41f4-bb21-a0f66d350ee9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1952145398 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 83.xbar_smoke_zero_delay s.1952145398 |
| Directory | /workspace/83.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/83.xbar_stress_all.1779304281 |
| Short name | T2692 |
| Test name | |
| Test status | |
| Simulation time | 15287940501 ps |
| CPU time | 659.44 seconds |
| Started | Jun 29 08:28:49 PM PDT 24 |
| Finished | Jun 29 08:39:49 PM PDT 24 |
| Peak memory | 575520 kb |
| Host | smart-f071999c-a0be-4ad4-93b2-c27dab6f8e6b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1779304281 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 83.xbar_stress_all.1779304281 |
| Directory | /workspace/83.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/83.xbar_stress_all_with_error.2142832512 |
| Short name | T1640 |
| Test name | |
| Test status | |
| Simulation time | 969104699 ps |
| CPU time | 90.2 seconds |
| Started | Jun 29 08:28:45 PM PDT 24 |
| Finished | Jun 29 08:30:16 PM PDT 24 |
| Peak memory | 574544 kb |
| Host | smart-93cd06a4-e0b2-4675-8a3a-bd61fe2c1164 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2142832512 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 83.xbar_stress_all_with_error.2142832512 |
| Directory | /workspace/83.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/83.xbar_stress_all_with_rand_reset.823992643 |
| Short name | T431 |
| Test name | |
| Test status | |
| Simulation time | 441690864 ps |
| CPU time | 213 seconds |
| Started | Jun 29 08:28:46 PM PDT 24 |
| Finished | Jun 29 08:32:19 PM PDT 24 |
| Peak memory | 575472 kb |
| Host | smart-5fe176e4-3996-47d8-9ac3-53cd170ff51b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=823992643 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_res et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 83.xbar_stress_all_ with_rand_reset.823992643 |
| Directory | /workspace/83.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/83.xbar_stress_all_with_reset_error.1170726353 |
| Short name | T2675 |
| Test name | |
| Test status | |
| Simulation time | 6605128729 ps |
| CPU time | 342.43 seconds |
| Started | Jun 29 08:28:43 PM PDT 24 |
| Finished | Jun 29 08:34:26 PM PDT 24 |
| Peak memory | 576452 kb |
| Host | smart-5e73a25f-799c-4976-ad8b-35710f6e1653 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1170726353 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 83.xbar_stress_al l_with_reset_error.1170726353 |
| Directory | /workspace/83.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/83.xbar_unmapped_addr.4100916642 |
| Short name | T1639 |
| Test name | |
| Test status | |
| Simulation time | 124167529 ps |
| CPU time | 16.42 seconds |
| Started | Jun 29 08:28:44 PM PDT 24 |
| Finished | Jun 29 08:29:02 PM PDT 24 |
| Peak memory | 574276 kb |
| Host | smart-f228e687-a740-4cf0-ae6e-a733f0765035 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4100916642 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 83.xbar_unmapped_addr.4100916642 |
| Directory | /workspace/83.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/84.xbar_access_same_device.22495223 |
| Short name | T2430 |
| Test name | |
| Test status | |
| Simulation time | 315506274 ps |
| CPU time | 15.43 seconds |
| Started | Jun 29 08:28:55 PM PDT 24 |
| Finished | Jun 29 08:29:10 PM PDT 24 |
| Peak memory | 575172 kb |
| Host | smart-9d465172-5e4a-42f2-919b-e6382f6bd900 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22495223 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 84.xbar_access_same_device.22495223 |
| Directory | /workspace/84.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/84.xbar_access_same_device_slow_rsp.409746616 |
| Short name | T2038 |
| Test name | |
| Test status | |
| Simulation time | 50617421066 ps |
| CPU time | 863.47 seconds |
| Started | Jun 29 08:28:44 PM PDT 24 |
| Finished | Jun 29 08:43:08 PM PDT 24 |
| Peak memory | 574376 kb |
| Host | smart-58226aa9-e41e-4459-90d4-b0ac073d3f0c |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=409746616 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 84.xbar_access_same_d evice_slow_rsp.409746616 |
| Directory | /workspace/84.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/84.xbar_error_and_unmapped_addr.166224992 |
| Short name | T1481 |
| Test name | |
| Test status | |
| Simulation time | 701959306 ps |
| CPU time | 28.88 seconds |
| Started | Jun 29 08:28:52 PM PDT 24 |
| Finished | Jun 29 08:29:21 PM PDT 24 |
| Peak memory | 574264 kb |
| Host | smart-514dc41d-0308-4834-8d93-3347e5503b82 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=166224992 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 84.xbar_error_and_unmapped_addr .166224992 |
| Directory | /workspace/84.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/84.xbar_error_random.3537681552 |
| Short name | T1324 |
| Test name | |
| Test status | |
| Simulation time | 1542579752 ps |
| CPU time | 52.63 seconds |
| Started | Jun 29 08:28:53 PM PDT 24 |
| Finished | Jun 29 08:29:46 PM PDT 24 |
| Peak memory | 573936 kb |
| Host | smart-8511adf9-4d9e-4526-8c0a-b6e28e5724f4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3537681552 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 84.xbar_error_random.3537681552 |
| Directory | /workspace/84.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/84.xbar_random.896831556 |
| Short name | T2487 |
| Test name | |
| Test status | |
| Simulation time | 279023640 ps |
| CPU time | 29.4 seconds |
| Started | Jun 29 08:28:47 PM PDT 24 |
| Finished | Jun 29 08:29:16 PM PDT 24 |
| Peak memory | 575296 kb |
| Host | smart-e05e2687-41e2-42be-b42a-43aef90c4431 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=896831556 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 84.xbar_random.896831556 |
| Directory | /workspace/84.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/84.xbar_random_large_delays.232257887 |
| Short name | T2191 |
| Test name | |
| Test status | |
| Simulation time | 42738311099 ps |
| CPU time | 436.14 seconds |
| Started | Jun 29 08:28:44 PM PDT 24 |
| Finished | Jun 29 08:36:01 PM PDT 24 |
| Peak memory | 575392 kb |
| Host | smart-aec3e393-a502-4cf8-8ad2-f6598c9866c5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=232257887 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 84.xbar_random_large_delays.232257887 |
| Directory | /workspace/84.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/84.xbar_random_slow_rsp.1704064786 |
| Short name | T2177 |
| Test name | |
| Test status | |
| Simulation time | 13802025195 ps |
| CPU time | 233.58 seconds |
| Started | Jun 29 08:28:56 PM PDT 24 |
| Finished | Jun 29 08:32:50 PM PDT 24 |
| Peak memory | 575404 kb |
| Host | smart-049945a8-1946-4ddf-8119-aa46286c4ff6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1704064786 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 84.xbar_random_slow_rsp.1704064786 |
| Directory | /workspace/84.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/84.xbar_random_zero_delays.4112091846 |
| Short name | T1316 |
| Test name | |
| Test status | |
| Simulation time | 51726449 ps |
| CPU time | 8.25 seconds |
| Started | Jun 29 08:28:44 PM PDT 24 |
| Finished | Jun 29 08:28:53 PM PDT 24 |
| Peak memory | 574288 kb |
| Host | smart-d965427d-0401-4b3d-92a2-7ede26eeb304 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4112091846 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 84.xbar_random_zero_del ays.4112091846 |
| Directory | /workspace/84.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/84.xbar_same_source.4247334655 |
| Short name | T2249 |
| Test name | |
| Test status | |
| Simulation time | 281780597 ps |
| CPU time | 24.37 seconds |
| Started | Jun 29 08:28:51 PM PDT 24 |
| Finished | Jun 29 08:29:16 PM PDT 24 |
| Peak memory | 575304 kb |
| Host | smart-9df873f8-fbe4-43bf-8073-dcc3e7afa709 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4247334655 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 84.xbar_same_source.4247334655 |
| Directory | /workspace/84.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/84.xbar_smoke.3019848463 |
| Short name | T1912 |
| Test name | |
| Test status | |
| Simulation time | 51658048 ps |
| CPU time | 6.92 seconds |
| Started | Jun 29 08:28:44 PM PDT 24 |
| Finished | Jun 29 08:28:52 PM PDT 24 |
| Peak memory | 565980 kb |
| Host | smart-d1ecfdec-098d-4ee5-bf75-f6eeda76ccd2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3019848463 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 84.xbar_smoke.3019848463 |
| Directory | /workspace/84.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/84.xbar_smoke_large_delays.2573303042 |
| Short name | T1925 |
| Test name | |
| Test status | |
| Simulation time | 7881776960 ps |
| CPU time | 88.22 seconds |
| Started | Jun 29 08:28:56 PM PDT 24 |
| Finished | Jun 29 08:30:25 PM PDT 24 |
| Peak memory | 574216 kb |
| Host | smart-20153817-23f7-44e2-b0df-6470b9cefb48 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2573303042 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 84.xbar_smoke_large_delays.2573303042 |
| Directory | /workspace/84.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/84.xbar_smoke_slow_rsp.4259991599 |
| Short name | T1329 |
| Test name | |
| Test status | |
| Simulation time | 4268844938 ps |
| CPU time | 76.58 seconds |
| Started | Jun 29 08:28:55 PM PDT 24 |
| Finished | Jun 29 08:30:12 PM PDT 24 |
| Peak memory | 574200 kb |
| Host | smart-c47ff8d9-9ae2-4816-8d70-de42f44ad874 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4259991599 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 84.xbar_smoke_slow_rsp.4259991599 |
| Directory | /workspace/84.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/84.xbar_smoke_zero_delays.2656968648 |
| Short name | T2481 |
| Test name | |
| Test status | |
| Simulation time | 48655762 ps |
| CPU time | 6.95 seconds |
| Started | Jun 29 08:28:49 PM PDT 24 |
| Finished | Jun 29 08:28:56 PM PDT 24 |
| Peak memory | 574260 kb |
| Host | smart-4beb8225-5e5b-43fe-bced-816c75b95e29 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2656968648 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 84.xbar_smoke_zero_delay s.2656968648 |
| Directory | /workspace/84.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/84.xbar_stress_all.2258905918 |
| Short name | T2625 |
| Test name | |
| Test status | |
| Simulation time | 13238798282 ps |
| CPU time | 581.97 seconds |
| Started | Jun 29 08:28:54 PM PDT 24 |
| Finished | Jun 29 08:38:36 PM PDT 24 |
| Peak memory | 575496 kb |
| Host | smart-edd4216e-8dd1-4021-8f9d-5cf11045eeee |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2258905918 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 84.xbar_stress_all.2258905918 |
| Directory | /workspace/84.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/84.xbar_stress_all_with_error.2658262213 |
| Short name | T2709 |
| Test name | |
| Test status | |
| Simulation time | 6245215780 ps |
| CPU time | 226.28 seconds |
| Started | Jun 29 08:28:51 PM PDT 24 |
| Finished | Jun 29 08:32:38 PM PDT 24 |
| Peak memory | 574672 kb |
| Host | smart-25a033e0-92ce-4b81-945d-f4595a5ef3dc |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2658262213 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 84.xbar_stress_all_with_error.2658262213 |
| Directory | /workspace/84.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/84.xbar_stress_all_with_rand_reset.4043912119 |
| Short name | T547 |
| Test name | |
| Test status | |
| Simulation time | 2232214335 ps |
| CPU time | 342.96 seconds |
| Started | Jun 29 08:28:52 PM PDT 24 |
| Finished | Jun 29 08:34:36 PM PDT 24 |
| Peak memory | 575508 kb |
| Host | smart-7db2ebec-be3d-4b79-9150-84b54cfc0716 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4043912119 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 84.xbar_stress_all _with_rand_reset.4043912119 |
| Directory | /workspace/84.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/84.xbar_stress_all_with_reset_error.474543872 |
| Short name | T817 |
| Test name | |
| Test status | |
| Simulation time | 15152678705 ps |
| CPU time | 775.44 seconds |
| Started | Jun 29 08:28:54 PM PDT 24 |
| Finished | Jun 29 08:41:50 PM PDT 24 |
| Peak memory | 575516 kb |
| Host | smart-57af84de-4ff4-4cea-bf9c-b59466411d5e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=474543872 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 84.xbar_stress_all _with_reset_error.474543872 |
| Directory | /workspace/84.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/84.xbar_unmapped_addr.1424106445 |
| Short name | T2438 |
| Test name | |
| Test status | |
| Simulation time | 1129598646 ps |
| CPU time | 55.14 seconds |
| Started | Jun 29 08:28:53 PM PDT 24 |
| Finished | Jun 29 08:29:48 PM PDT 24 |
| Peak memory | 575368 kb |
| Host | smart-dc8c7e49-66b5-4c04-81d8-1bf4684a80e0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1424106445 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 84.xbar_unmapped_addr.1424106445 |
| Directory | /workspace/84.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/85.xbar_access_same_device.604134031 |
| Short name | T780 |
| Test name | |
| Test status | |
| Simulation time | 1124511624 ps |
| CPU time | 52.22 seconds |
| Started | Jun 29 08:28:59 PM PDT 24 |
| Finished | Jun 29 08:29:52 PM PDT 24 |
| Peak memory | 574256 kb |
| Host | smart-6ab896f8-60f6-4db2-9891-f351cd83eba9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=604134031 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 85.xbar_access_same_device. 604134031 |
| Directory | /workspace/85.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/85.xbar_error_and_unmapped_addr.4111019405 |
| Short name | T1796 |
| Test name | |
| Test status | |
| Simulation time | 78901300 ps |
| CPU time | 10.88 seconds |
| Started | Jun 29 08:29:14 PM PDT 24 |
| Finished | Jun 29 08:29:25 PM PDT 24 |
| Peak memory | 573916 kb |
| Host | smart-278d644c-5e85-42de-ac04-8bad31087873 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4111019405 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 85.xbar_error_and_unmapped_add r.4111019405 |
| Directory | /workspace/85.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/85.xbar_error_random.2079889504 |
| Short name | T2493 |
| Test name | |
| Test status | |
| Simulation time | 723819807 ps |
| CPU time | 29.09 seconds |
| Started | Jun 29 08:29:00 PM PDT 24 |
| Finished | Jun 29 08:29:30 PM PDT 24 |
| Peak memory | 573912 kb |
| Host | smart-7b9a314e-e8ee-4e4a-854b-e3a4880afbac |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2079889504 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 85.xbar_error_random.2079889504 |
| Directory | /workspace/85.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/85.xbar_random.2693420020 |
| Short name | T1787 |
| Test name | |
| Test status | |
| Simulation time | 2717129596 ps |
| CPU time | 87.39 seconds |
| Started | Jun 29 08:29:00 PM PDT 24 |
| Finished | Jun 29 08:30:28 PM PDT 24 |
| Peak memory | 575408 kb |
| Host | smart-df20d2ee-f853-4b30-9a37-2ac665602fcf |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2693420020 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 85.xbar_random.2693420020 |
| Directory | /workspace/85.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/85.xbar_random_large_delays.1157077250 |
| Short name | T2007 |
| Test name | |
| Test status | |
| Simulation time | 41566513073 ps |
| CPU time | 448.4 seconds |
| Started | Jun 29 08:29:00 PM PDT 24 |
| Finished | Jun 29 08:36:29 PM PDT 24 |
| Peak memory | 574304 kb |
| Host | smart-45c493fd-dde9-47d2-b9ad-e09323140a8c |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1157077250 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 85.xbar_random_large_delays.1157077250 |
| Directory | /workspace/85.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/85.xbar_random_slow_rsp.3130343990 |
| Short name | T2440 |
| Test name | |
| Test status | |
| Simulation time | 52636973858 ps |
| CPU time | 914.32 seconds |
| Started | Jun 29 08:29:03 PM PDT 24 |
| Finished | Jun 29 08:44:18 PM PDT 24 |
| Peak memory | 575400 kb |
| Host | smart-7d84b0a7-2e8a-44fb-972f-a1b48784a525 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3130343990 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 85.xbar_random_slow_rsp.3130343990 |
| Directory | /workspace/85.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/85.xbar_random_zero_delays.2797631768 |
| Short name | T1436 |
| Test name | |
| Test status | |
| Simulation time | 43718260 ps |
| CPU time | 7.07 seconds |
| Started | Jun 29 08:29:14 PM PDT 24 |
| Finished | Jun 29 08:29:21 PM PDT 24 |
| Peak memory | 566024 kb |
| Host | smart-665752d2-7226-4133-9aba-ffd9810f2ee9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2797631768 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 85.xbar_random_zero_del ays.2797631768 |
| Directory | /workspace/85.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/85.xbar_same_source.2954627513 |
| Short name | T2606 |
| Test name | |
| Test status | |
| Simulation time | 1539843438 ps |
| CPU time | 45.62 seconds |
| Started | Jun 29 08:28:59 PM PDT 24 |
| Finished | Jun 29 08:29:45 PM PDT 24 |
| Peak memory | 575296 kb |
| Host | smart-2d4005cb-0859-4208-9c49-d858c4787a18 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2954627513 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 85.xbar_same_source.2954627513 |
| Directory | /workspace/85.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/85.xbar_smoke.1692743097 |
| Short name | T1806 |
| Test name | |
| Test status | |
| Simulation time | 190507509 ps |
| CPU time | 9.45 seconds |
| Started | Jun 29 08:28:54 PM PDT 24 |
| Finished | Jun 29 08:29:03 PM PDT 24 |
| Peak memory | 574252 kb |
| Host | smart-b34f420e-cdeb-484b-8b4c-c9dc6092442a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1692743097 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 85.xbar_smoke.1692743097 |
| Directory | /workspace/85.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/85.xbar_smoke_large_delays.2072729940 |
| Short name | T1374 |
| Test name | |
| Test status | |
| Simulation time | 6267571506 ps |
| CPU time | 70.45 seconds |
| Started | Jun 29 08:28:53 PM PDT 24 |
| Finished | Jun 29 08:30:04 PM PDT 24 |
| Peak memory | 566092 kb |
| Host | smart-e1eba70b-ef3c-491f-8da4-df3f5d1982bd |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2072729940 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 85.xbar_smoke_large_delays.2072729940 |
| Directory | /workspace/85.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/85.xbar_smoke_slow_rsp.878756130 |
| Short name | T1733 |
| Test name | |
| Test status | |
| Simulation time | 5161174053 ps |
| CPU time | 81.96 seconds |
| Started | Jun 29 08:28:55 PM PDT 24 |
| Finished | Jun 29 08:30:17 PM PDT 24 |
| Peak memory | 566092 kb |
| Host | smart-40e45df7-0c24-428b-92cd-9a3da1474216 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=878756130 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 85.xbar_smoke_slow_rsp.878756130 |
| Directory | /workspace/85.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/85.xbar_smoke_zero_delays.2359920736 |
| Short name | T1437 |
| Test name | |
| Test status | |
| Simulation time | 48994885 ps |
| CPU time | 6.72 seconds |
| Started | Jun 29 08:28:57 PM PDT 24 |
| Finished | Jun 29 08:29:04 PM PDT 24 |
| Peak memory | 574268 kb |
| Host | smart-8965fe60-b5a6-4dba-af3a-c9424dfba931 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2359920736 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 85.xbar_smoke_zero_delay s.2359920736 |
| Directory | /workspace/85.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/85.xbar_stress_all.3137522087 |
| Short name | T486 |
| Test name | |
| Test status | |
| Simulation time | 13829223427 ps |
| CPU time | 520.44 seconds |
| Started | Jun 29 08:29:14 PM PDT 24 |
| Finished | Jun 29 08:37:55 PM PDT 24 |
| Peak memory | 574468 kb |
| Host | smart-93593b2b-e071-42df-a3e6-b5659fd9ca0b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3137522087 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 85.xbar_stress_all.3137522087 |
| Directory | /workspace/85.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/85.xbar_stress_all_with_error.1443982250 |
| Short name | T635 |
| Test name | |
| Test status | |
| Simulation time | 963170928 ps |
| CPU time | 67.55 seconds |
| Started | Jun 29 08:29:00 PM PDT 24 |
| Finished | Jun 29 08:30:09 PM PDT 24 |
| Peak memory | 574300 kb |
| Host | smart-973f052f-d779-4c19-9694-b61c687d7e5c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1443982250 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 85.xbar_stress_all_with_error.1443982250 |
| Directory | /workspace/85.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/85.xbar_stress_all_with_rand_reset.712116455 |
| Short name | T2457 |
| Test name | |
| Test status | |
| Simulation time | 10968555376 ps |
| CPU time | 607.18 seconds |
| Started | Jun 29 08:29:00 PM PDT 24 |
| Finished | Jun 29 08:39:08 PM PDT 24 |
| Peak memory | 575520 kb |
| Host | smart-beb46ce9-ca12-479c-a6f9-799f30a2fc2b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=712116455 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_res et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 85.xbar_stress_all_ with_rand_reset.712116455 |
| Directory | /workspace/85.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/85.xbar_stress_all_with_reset_error.2368712064 |
| Short name | T1781 |
| Test name | |
| Test status | |
| Simulation time | 1597358709 ps |
| CPU time | 290.74 seconds |
| Started | Jun 29 08:29:01 PM PDT 24 |
| Finished | Jun 29 08:33:53 PM PDT 24 |
| Peak memory | 574440 kb |
| Host | smart-cbc797d4-3330-4d8f-9324-71a13c14e786 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2368712064 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 85.xbar_stress_al l_with_reset_error.2368712064 |
| Directory | /workspace/85.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/85.xbar_unmapped_addr.1214252334 |
| Short name | T522 |
| Test name | |
| Test status | |
| Simulation time | 230329779 ps |
| CPU time | 29.96 seconds |
| Started | Jun 29 08:29:13 PM PDT 24 |
| Finished | Jun 29 08:29:43 PM PDT 24 |
| Peak memory | 575356 kb |
| Host | smart-84130d15-c626-4ab1-8a01-4c8c1178e237 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1214252334 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 85.xbar_unmapped_addr.1214252334 |
| Directory | /workspace/85.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/86.xbar_access_same_device.979439076 |
| Short name | T1500 |
| Test name | |
| Test status | |
| Simulation time | 1624227678 ps |
| CPU time | 68.82 seconds |
| Started | Jun 29 08:29:10 PM PDT 24 |
| Finished | Jun 29 08:30:19 PM PDT 24 |
| Peak memory | 575332 kb |
| Host | smart-21b880e1-aebc-4d02-9ea7-14660ab3e8e9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=979439076 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 86.xbar_access_same_device. 979439076 |
| Directory | /workspace/86.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/86.xbar_access_same_device_slow_rsp.2526357545 |
| Short name | T2348 |
| Test name | |
| Test status | |
| Simulation time | 72703250874 ps |
| CPU time | 1276 seconds |
| Started | Jun 29 08:29:09 PM PDT 24 |
| Finished | Jun 29 08:50:26 PM PDT 24 |
| Peak memory | 574344 kb |
| Host | smart-7da7c3e8-f21f-4a1f-a7d9-25c3bde77e8c |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2526357545 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 86.xbar_access_same_ device_slow_rsp.2526357545 |
| Directory | /workspace/86.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/86.xbar_error_and_unmapped_addr.1146171229 |
| Short name | T2778 |
| Test name | |
| Test status | |
| Simulation time | 113971691 ps |
| CPU time | 15.58 seconds |
| Started | Jun 29 08:29:12 PM PDT 24 |
| Finished | Jun 29 08:29:28 PM PDT 24 |
| Peak memory | 574280 kb |
| Host | smart-cdcc6962-4b90-4b1a-a13e-35223a719c26 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1146171229 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 86.xbar_error_and_unmapped_add r.1146171229 |
| Directory | /workspace/86.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/86.xbar_error_random.3151108978 |
| Short name | T1346 |
| Test name | |
| Test status | |
| Simulation time | 1701976394 ps |
| CPU time | 62.63 seconds |
| Started | Jun 29 08:29:11 PM PDT 24 |
| Finished | Jun 29 08:30:14 PM PDT 24 |
| Peak memory | 574476 kb |
| Host | smart-3d6072c6-ef5e-41ed-8220-7ed3ca01dcb7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3151108978 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 86.xbar_error_random.3151108978 |
| Directory | /workspace/86.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/86.xbar_random.2770311417 |
| Short name | T2057 |
| Test name | |
| Test status | |
| Simulation time | 1523120918 ps |
| CPU time | 62.61 seconds |
| Started | Jun 29 08:29:08 PM PDT 24 |
| Finished | Jun 29 08:30:11 PM PDT 24 |
| Peak memory | 575316 kb |
| Host | smart-84f79a52-d678-4ca3-8714-497c9ff76c78 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2770311417 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 86.xbar_random.2770311417 |
| Directory | /workspace/86.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/86.xbar_random_large_delays.4056051742 |
| Short name | T460 |
| Test name | |
| Test status | |
| Simulation time | 88555397569 ps |
| CPU time | 878.5 seconds |
| Started | Jun 29 08:29:08 PM PDT 24 |
| Finished | Jun 29 08:43:47 PM PDT 24 |
| Peak memory | 575404 kb |
| Host | smart-229804fa-72a7-456f-a9ed-8e8c4b30b760 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4056051742 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 86.xbar_random_large_delays.4056051742 |
| Directory | /workspace/86.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/86.xbar_random_slow_rsp.1380864033 |
| Short name | T2738 |
| Test name | |
| Test status | |
| Simulation time | 25547317027 ps |
| CPU time | 441.41 seconds |
| Started | Jun 29 08:29:09 PM PDT 24 |
| Finished | Jun 29 08:36:30 PM PDT 24 |
| Peak memory | 574320 kb |
| Host | smart-f3ba59ee-60bd-4e00-8fe2-6e8b328a3552 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1380864033 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 86.xbar_random_slow_rsp.1380864033 |
| Directory | /workspace/86.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/86.xbar_random_zero_delays.2370289062 |
| Short name | T556 |
| Test name | |
| Test status | |
| Simulation time | 584026709 ps |
| CPU time | 53.6 seconds |
| Started | Jun 29 08:29:11 PM PDT 24 |
| Finished | Jun 29 08:30:05 PM PDT 24 |
| Peak memory | 575280 kb |
| Host | smart-e9f3058f-e466-4b60-b478-77a9eea7b4a4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2370289062 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 86.xbar_random_zero_del ays.2370289062 |
| Directory | /workspace/86.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/86.xbar_same_source.1187782985 |
| Short name | T1552 |
| Test name | |
| Test status | |
| Simulation time | 1181504903 ps |
| CPU time | 39.31 seconds |
| Started | Jun 29 08:29:08 PM PDT 24 |
| Finished | Jun 29 08:29:48 PM PDT 24 |
| Peak memory | 575264 kb |
| Host | smart-3fbc49b5-73af-4940-ae9a-dd0dc6c7287e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1187782985 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 86.xbar_same_source.1187782985 |
| Directory | /workspace/86.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/86.xbar_smoke.1736314301 |
| Short name | T2072 |
| Test name | |
| Test status | |
| Simulation time | 211151589 ps |
| CPU time | 9.26 seconds |
| Started | Jun 29 08:29:01 PM PDT 24 |
| Finished | Jun 29 08:29:11 PM PDT 24 |
| Peak memory | 574260 kb |
| Host | smart-0f676e52-5b14-4c31-9f9b-d07d76c6fb3b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1736314301 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 86.xbar_smoke.1736314301 |
| Directory | /workspace/86.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/86.xbar_smoke_large_delays.4215120611 |
| Short name | T2175 |
| Test name | |
| Test status | |
| Simulation time | 7845193218 ps |
| CPU time | 79.04 seconds |
| Started | Jun 29 08:29:14 PM PDT 24 |
| Finished | Jun 29 08:30:33 PM PDT 24 |
| Peak memory | 574320 kb |
| Host | smart-c117f130-e736-4e84-9c0e-9d2f3fbead36 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4215120611 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 86.xbar_smoke_large_delays.4215120611 |
| Directory | /workspace/86.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/86.xbar_smoke_slow_rsp.2384061141 |
| Short name | T2157 |
| Test name | |
| Test status | |
| Simulation time | 4045951051 ps |
| CPU time | 70.5 seconds |
| Started | Jun 29 08:29:00 PM PDT 24 |
| Finished | Jun 29 08:30:12 PM PDT 24 |
| Peak memory | 574320 kb |
| Host | smart-f37e9f14-98ee-48aa-8df2-a86ae7143845 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2384061141 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 86.xbar_smoke_slow_rsp.2384061141 |
| Directory | /workspace/86.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/86.xbar_smoke_zero_delays.3568062121 |
| Short name | T1464 |
| Test name | |
| Test status | |
| Simulation time | 48545576 ps |
| CPU time | 6.29 seconds |
| Started | Jun 29 08:29:00 PM PDT 24 |
| Finished | Jun 29 08:29:07 PM PDT 24 |
| Peak memory | 565960 kb |
| Host | smart-f044e457-d1d9-45f3-b754-35d6f3e4c8d8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3568062121 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 86.xbar_smoke_zero_delay s.3568062121 |
| Directory | /workspace/86.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/86.xbar_stress_all.1361938680 |
| Short name | T1778 |
| Test name | |
| Test status | |
| Simulation time | 3449722497 ps |
| CPU time | 138.04 seconds |
| Started | Jun 29 08:29:17 PM PDT 24 |
| Finished | Jun 29 08:31:35 PM PDT 24 |
| Peak memory | 575396 kb |
| Host | smart-5d195592-4fdd-4006-af28-838aa232e193 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1361938680 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 86.xbar_stress_all.1361938680 |
| Directory | /workspace/86.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/86.xbar_stress_all_with_error.2526016710 |
| Short name | T2594 |
| Test name | |
| Test status | |
| Simulation time | 5960544942 ps |
| CPU time | 243.23 seconds |
| Started | Jun 29 08:29:17 PM PDT 24 |
| Finished | Jun 29 08:33:21 PM PDT 24 |
| Peak memory | 574484 kb |
| Host | smart-9c7067dc-e801-4957-b35a-dd7ad34cf69a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2526016710 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 86.xbar_stress_all_with_error.2526016710 |
| Directory | /workspace/86.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/86.xbar_stress_all_with_reset_error.3607947756 |
| Short name | T1997 |
| Test name | |
| Test status | |
| Simulation time | 2784465920 ps |
| CPU time | 198.31 seconds |
| Started | Jun 29 08:29:18 PM PDT 24 |
| Finished | Jun 29 08:32:37 PM PDT 24 |
| Peak memory | 574736 kb |
| Host | smart-24d01085-0b9b-4a23-b6a9-43e9fb56c963 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3607947756 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 86.xbar_stress_al l_with_reset_error.3607947756 |
| Directory | /workspace/86.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/86.xbar_unmapped_addr.2576961576 |
| Short name | T1514 |
| Test name | |
| Test status | |
| Simulation time | 990356531 ps |
| CPU time | 44.72 seconds |
| Started | Jun 29 08:29:09 PM PDT 24 |
| Finished | Jun 29 08:29:54 PM PDT 24 |
| Peak memory | 575344 kb |
| Host | smart-7711f409-9842-4cff-b368-f72b69b88f76 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2576961576 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 86.xbar_unmapped_addr.2576961576 |
| Directory | /workspace/86.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/87.xbar_access_same_device.1921201138 |
| Short name | T1847 |
| Test name | |
| Test status | |
| Simulation time | 784687448 ps |
| CPU time | 69.12 seconds |
| Started | Jun 29 08:29:23 PM PDT 24 |
| Finished | Jun 29 08:30:32 PM PDT 24 |
| Peak memory | 575340 kb |
| Host | smart-c79a8a5b-0843-4b61-9646-fe3a87648e8e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1921201138 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 87.xbar_access_same_device .1921201138 |
| Directory | /workspace/87.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/87.xbar_access_same_device_slow_rsp.1928407726 |
| Short name | T2204 |
| Test name | |
| Test status | |
| Simulation time | 10334108878 ps |
| CPU time | 189.34 seconds |
| Started | Jun 29 08:29:24 PM PDT 24 |
| Finished | Jun 29 08:32:33 PM PDT 24 |
| Peak memory | 574108 kb |
| Host | smart-27edb5e0-2d58-4912-915e-c10226ca2de1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1928407726 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 87.xbar_access_same_ device_slow_rsp.1928407726 |
| Directory | /workspace/87.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/87.xbar_error_and_unmapped_addr.238046077 |
| Short name | T2395 |
| Test name | |
| Test status | |
| Simulation time | 343276953 ps |
| CPU time | 33.77 seconds |
| Started | Jun 29 08:29:27 PM PDT 24 |
| Finished | Jun 29 08:30:01 PM PDT 24 |
| Peak memory | 574272 kb |
| Host | smart-0affc9c4-435c-4e92-94a6-3e2d5f71ff6a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=238046077 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 87.xbar_error_and_unmapped_addr .238046077 |
| Directory | /workspace/87.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/87.xbar_error_random.1042038449 |
| Short name | T2110 |
| Test name | |
| Test status | |
| Simulation time | 2064529176 ps |
| CPU time | 85.36 seconds |
| Started | Jun 29 08:29:26 PM PDT 24 |
| Finished | Jun 29 08:30:52 PM PDT 24 |
| Peak memory | 574076 kb |
| Host | smart-a5493b3d-ba15-470e-9118-aa414caa7bc0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1042038449 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 87.xbar_error_random.1042038449 |
| Directory | /workspace/87.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/87.xbar_random.1856375417 |
| Short name | T2068 |
| Test name | |
| Test status | |
| Simulation time | 1874961067 ps |
| CPU time | 74.97 seconds |
| Started | Jun 29 08:29:24 PM PDT 24 |
| Finished | Jun 29 08:30:39 PM PDT 24 |
| Peak memory | 575308 kb |
| Host | smart-7cccde95-d5e7-4dae-850c-31ccee7f304a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1856375417 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 87.xbar_random.1856375417 |
| Directory | /workspace/87.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/87.xbar_random_large_delays.963963430 |
| Short name | T2251 |
| Test name | |
| Test status | |
| Simulation time | 81156708016 ps |
| CPU time | 864.08 seconds |
| Started | Jun 29 08:29:23 PM PDT 24 |
| Finished | Jun 29 08:43:47 PM PDT 24 |
| Peak memory | 575412 kb |
| Host | smart-87337d21-5163-4a64-bbe4-bcb73f774a3a |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=963963430 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 87.xbar_random_large_delays.963963430 |
| Directory | /workspace/87.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/87.xbar_random_slow_rsp.1311085457 |
| Short name | T2383 |
| Test name | |
| Test status | |
| Simulation time | 51837299187 ps |
| CPU time | 922.27 seconds |
| Started | Jun 29 08:29:23 PM PDT 24 |
| Finished | Jun 29 08:44:46 PM PDT 24 |
| Peak memory | 575432 kb |
| Host | smart-a7659fb1-b17d-478a-bd01-571ba733bc8a |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1311085457 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 87.xbar_random_slow_rsp.1311085457 |
| Directory | /workspace/87.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/87.xbar_random_zero_delays.4087272934 |
| Short name | T1337 |
| Test name | |
| Test status | |
| Simulation time | 100947170 ps |
| CPU time | 11.59 seconds |
| Started | Jun 29 08:29:24 PM PDT 24 |
| Finished | Jun 29 08:29:36 PM PDT 24 |
| Peak memory | 575304 kb |
| Host | smart-577b0123-a18b-41ac-932b-434c9c84e728 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4087272934 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 87.xbar_random_zero_del ays.4087272934 |
| Directory | /workspace/87.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/87.xbar_same_source.1417001105 |
| Short name | T2132 |
| Test name | |
| Test status | |
| Simulation time | 2170648077 ps |
| CPU time | 75.92 seconds |
| Started | Jun 29 08:29:29 PM PDT 24 |
| Finished | Jun 29 08:30:45 PM PDT 24 |
| Peak memory | 575368 kb |
| Host | smart-3015915d-0534-40de-8a2a-ceb2330b5c6b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1417001105 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 87.xbar_same_source.1417001105 |
| Directory | /workspace/87.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/87.xbar_smoke.3823301241 |
| Short name | T2152 |
| Test name | |
| Test status | |
| Simulation time | 154224439 ps |
| CPU time | 8.74 seconds |
| Started | Jun 29 08:29:17 PM PDT 24 |
| Finished | Jun 29 08:29:26 PM PDT 24 |
| Peak memory | 574244 kb |
| Host | smart-d484e8a5-e758-47ee-a97f-862d308521f8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3823301241 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 87.xbar_smoke.3823301241 |
| Directory | /workspace/87.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/87.xbar_smoke_large_delays.4174548277 |
| Short name | T2257 |
| Test name | |
| Test status | |
| Simulation time | 8551163730 ps |
| CPU time | 95.93 seconds |
| Started | Jun 29 08:29:19 PM PDT 24 |
| Finished | Jun 29 08:30:55 PM PDT 24 |
| Peak memory | 566088 kb |
| Host | smart-32908da8-b03a-4e0b-96e6-ef8f26c290a9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4174548277 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 87.xbar_smoke_large_delays.4174548277 |
| Directory | /workspace/87.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/87.xbar_smoke_slow_rsp.2071189418 |
| Short name | T2064 |
| Test name | |
| Test status | |
| Simulation time | 3277929790 ps |
| CPU time | 55.06 seconds |
| Started | Jun 29 08:29:21 PM PDT 24 |
| Finished | Jun 29 08:30:17 PM PDT 24 |
| Peak memory | 566028 kb |
| Host | smart-232d0b52-3f73-4875-9d3d-99a408027573 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2071189418 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 87.xbar_smoke_slow_rsp.2071189418 |
| Directory | /workspace/87.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/87.xbar_smoke_zero_delays.3736629017 |
| Short name | T525 |
| Test name | |
| Test status | |
| Simulation time | 56192132 ps |
| CPU time | 7 seconds |
| Started | Jun 29 08:29:16 PM PDT 24 |
| Finished | Jun 29 08:29:23 PM PDT 24 |
| Peak memory | 574220 kb |
| Host | smart-8e02faa8-a1f5-46cd-83d9-d8008ec0dd17 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3736629017 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 87.xbar_smoke_zero_delay s.3736629017 |
| Directory | /workspace/87.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/87.xbar_stress_all.3065892316 |
| Short name | T2770 |
| Test name | |
| Test status | |
| Simulation time | 8790321507 ps |
| CPU time | 322.87 seconds |
| Started | Jun 29 08:29:33 PM PDT 24 |
| Finished | Jun 29 08:34:56 PM PDT 24 |
| Peak memory | 574468 kb |
| Host | smart-b78108e6-ea38-4834-90e1-8379e67ea1bf |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3065892316 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 87.xbar_stress_all.3065892316 |
| Directory | /workspace/87.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/87.xbar_stress_all_with_error.2747424593 |
| Short name | T1606 |
| Test name | |
| Test status | |
| Simulation time | 2339532715 ps |
| CPU time | 186.3 seconds |
| Started | Jun 29 08:29:34 PM PDT 24 |
| Finished | Jun 29 08:32:40 PM PDT 24 |
| Peak memory | 574456 kb |
| Host | smart-e0518535-c87c-4eab-a6a9-18889e231f75 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2747424593 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 87.xbar_stress_all_with_error.2747424593 |
| Directory | /workspace/87.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/87.xbar_stress_all_with_rand_reset.475438699 |
| Short name | T473 |
| Test name | |
| Test status | |
| Simulation time | 426445059 ps |
| CPU time | 117.88 seconds |
| Started | Jun 29 08:29:34 PM PDT 24 |
| Finished | Jun 29 08:31:32 PM PDT 24 |
| Peak memory | 575428 kb |
| Host | smart-362eba4d-7dc0-4ed0-9bd9-5b0c2233df73 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=475438699 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_res et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 87.xbar_stress_all_ with_rand_reset.475438699 |
| Directory | /workspace/87.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/87.xbar_stress_all_with_reset_error.3007356196 |
| Short name | T1766 |
| Test name | |
| Test status | |
| Simulation time | 178169160 ps |
| CPU time | 48.48 seconds |
| Started | Jun 29 08:29:34 PM PDT 24 |
| Finished | Jun 29 08:30:23 PM PDT 24 |
| Peak memory | 574384 kb |
| Host | smart-884a5484-71c6-43b4-8a79-364a9622e50e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3007356196 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 87.xbar_stress_al l_with_reset_error.3007356196 |
| Directory | /workspace/87.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/87.xbar_unmapped_addr.1595595326 |
| Short name | T1897 |
| Test name | |
| Test status | |
| Simulation time | 80832335 ps |
| CPU time | 6.83 seconds |
| Started | Jun 29 08:29:28 PM PDT 24 |
| Finished | Jun 29 08:29:35 PM PDT 24 |
| Peak memory | 574100 kb |
| Host | smart-ff5485b1-b241-497b-bec5-afceff2d7c51 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1595595326 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 87.xbar_unmapped_addr.1595595326 |
| Directory | /workspace/87.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/88.xbar_access_same_device.48466237 |
| Short name | T794 |
| Test name | |
| Test status | |
| Simulation time | 3181888054 ps |
| CPU time | 135.78 seconds |
| Started | Jun 29 08:29:34 PM PDT 24 |
| Finished | Jun 29 08:31:50 PM PDT 24 |
| Peak memory | 575356 kb |
| Host | smart-0593a7d8-e527-4935-8bb8-3de818991bcf |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48466237 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 88.xbar_access_same_device.48466237 |
| Directory | /workspace/88.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/88.xbar_access_same_device_slow_rsp.2379859331 |
| Short name | T1762 |
| Test name | |
| Test status | |
| Simulation time | 31591265830 ps |
| CPU time | 569.12 seconds |
| Started | Jun 29 08:29:32 PM PDT 24 |
| Finished | Jun 29 08:39:01 PM PDT 24 |
| Peak memory | 575452 kb |
| Host | smart-171d654d-92a1-4fc0-a877-b045dd605946 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2379859331 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 88.xbar_access_same_ device_slow_rsp.2379859331 |
| Directory | /workspace/88.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/88.xbar_error_and_unmapped_addr.120570517 |
| Short name | T1776 |
| Test name | |
| Test status | |
| Simulation time | 209924936 ps |
| CPU time | 29.85 seconds |
| Started | Jun 29 08:29:42 PM PDT 24 |
| Finished | Jun 29 08:30:12 PM PDT 24 |
| Peak memory | 574272 kb |
| Host | smart-9995dae5-b3b9-4556-af11-30c2458369fb |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=120570517 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 88.xbar_error_and_unmapped_addr .120570517 |
| Directory | /workspace/88.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/88.xbar_error_random.2981255165 |
| Short name | T2811 |
| Test name | |
| Test status | |
| Simulation time | 604525019 ps |
| CPU time | 22.96 seconds |
| Started | Jun 29 08:29:33 PM PDT 24 |
| Finished | Jun 29 08:29:56 PM PDT 24 |
| Peak memory | 574476 kb |
| Host | smart-64e8bda9-be4f-4d31-8056-4ad623c1b347 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2981255165 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 88.xbar_error_random.2981255165 |
| Directory | /workspace/88.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/88.xbar_random.343604673 |
| Short name | T2860 |
| Test name | |
| Test status | |
| Simulation time | 219382001 ps |
| CPU time | 21.94 seconds |
| Started | Jun 29 08:29:34 PM PDT 24 |
| Finished | Jun 29 08:29:57 PM PDT 24 |
| Peak memory | 575276 kb |
| Host | smart-d07502b4-884e-4895-9665-0786eaf1e07a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=343604673 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 88.xbar_random.343604673 |
| Directory | /workspace/88.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/88.xbar_random_large_delays.2185788400 |
| Short name | T1932 |
| Test name | |
| Test status | |
| Simulation time | 40606944709 ps |
| CPU time | 395.39 seconds |
| Started | Jun 29 08:29:32 PM PDT 24 |
| Finished | Jun 29 08:36:08 PM PDT 24 |
| Peak memory | 574328 kb |
| Host | smart-a30dbe71-c232-46b8-b4c8-80002d5b3f11 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2185788400 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 88.xbar_random_large_delays.2185788400 |
| Directory | /workspace/88.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/88.xbar_random_slow_rsp.442078814 |
| Short name | T2242 |
| Test name | |
| Test status | |
| Simulation time | 69336744018 ps |
| CPU time | 1179 seconds |
| Started | Jun 29 08:29:33 PM PDT 24 |
| Finished | Jun 29 08:49:12 PM PDT 24 |
| Peak memory | 575432 kb |
| Host | smart-aaa5f9e0-d7a8-4e48-81c8-af558f1cdbf4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=442078814 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 88.xbar_random_slow_rsp.442078814 |
| Directory | /workspace/88.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/88.xbar_random_zero_delays.1344544517 |
| Short name | T1419 |
| Test name | |
| Test status | |
| Simulation time | 103647874 ps |
| CPU time | 12.09 seconds |
| Started | Jun 29 08:29:34 PM PDT 24 |
| Finished | Jun 29 08:29:47 PM PDT 24 |
| Peak memory | 575276 kb |
| Host | smart-3e0ca4d9-9454-4680-8a59-a3944abece73 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1344544517 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 88.xbar_random_zero_del ays.1344544517 |
| Directory | /workspace/88.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/88.xbar_same_source.3729164606 |
| Short name | T2586 |
| Test name | |
| Test status | |
| Simulation time | 102738385 ps |
| CPU time | 11.07 seconds |
| Started | Jun 29 08:29:33 PM PDT 24 |
| Finished | Jun 29 08:29:45 PM PDT 24 |
| Peak memory | 575284 kb |
| Host | smart-81e8284b-5633-48db-abd8-b94139361aa7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3729164606 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 88.xbar_same_source.3729164606 |
| Directory | /workspace/88.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/88.xbar_smoke.3904470784 |
| Short name | T1590 |
| Test name | |
| Test status | |
| Simulation time | 225453719 ps |
| CPU time | 9.61 seconds |
| Started | Jun 29 08:29:35 PM PDT 24 |
| Finished | Jun 29 08:29:45 PM PDT 24 |
| Peak memory | 574260 kb |
| Host | smart-bf786699-3109-4ff6-a2c6-acb24841534c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3904470784 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 88.xbar_smoke.3904470784 |
| Directory | /workspace/88.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/88.xbar_smoke_large_delays.1269045800 |
| Short name | T1907 |
| Test name | |
| Test status | |
| Simulation time | 7663988844 ps |
| CPU time | 80.13 seconds |
| Started | Jun 29 08:29:32 PM PDT 24 |
| Finished | Jun 29 08:30:52 PM PDT 24 |
| Peak memory | 574312 kb |
| Host | smart-57a1c1ff-7340-4392-b91c-121f45a33195 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1269045800 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 88.xbar_smoke_large_delays.1269045800 |
| Directory | /workspace/88.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/88.xbar_smoke_slow_rsp.389508999 |
| Short name | T2247 |
| Test name | |
| Test status | |
| Simulation time | 4950459671 ps |
| CPU time | 86.75 seconds |
| Started | Jun 29 08:29:33 PM PDT 24 |
| Finished | Jun 29 08:31:00 PM PDT 24 |
| Peak memory | 566096 kb |
| Host | smart-23b788df-48e8-4f02-8319-c5af529538db |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=389508999 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 88.xbar_smoke_slow_rsp.389508999 |
| Directory | /workspace/88.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/88.xbar_smoke_zero_delays.640233199 |
| Short name | T2193 |
| Test name | |
| Test status | |
| Simulation time | 51178973 ps |
| CPU time | 7.3 seconds |
| Started | Jun 29 08:29:34 PM PDT 24 |
| Finished | Jun 29 08:29:42 PM PDT 24 |
| Peak memory | 574252 kb |
| Host | smart-cac37ba1-ec31-496c-92b0-e44fbbabedb8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=640233199 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 88.xbar_smoke_zero_delays .640233199 |
| Directory | /workspace/88.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/88.xbar_stress_all_with_error.3397494221 |
| Short name | T1647 |
| Test name | |
| Test status | |
| Simulation time | 1543731525 ps |
| CPU time | 120.96 seconds |
| Started | Jun 29 08:29:41 PM PDT 24 |
| Finished | Jun 29 08:31:42 PM PDT 24 |
| Peak memory | 574640 kb |
| Host | smart-456f8edf-7ad0-47c6-85cc-50e23a50d1b9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3397494221 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 88.xbar_stress_all_with_error.3397494221 |
| Directory | /workspace/88.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/88.xbar_stress_all_with_rand_reset.4115874570 |
| Short name | T820 |
| Test name | |
| Test status | |
| Simulation time | 221344262 ps |
| CPU time | 70.81 seconds |
| Started | Jun 29 08:29:40 PM PDT 24 |
| Finished | Jun 29 08:30:51 PM PDT 24 |
| Peak memory | 575452 kb |
| Host | smart-8ae9623c-d62a-4cb3-b400-0455f09ceff0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4115874570 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 88.xbar_stress_all _with_rand_reset.4115874570 |
| Directory | /workspace/88.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/88.xbar_stress_all_with_reset_error.485016034 |
| Short name | T2095 |
| Test name | |
| Test status | |
| Simulation time | 983215302 ps |
| CPU time | 175.88 seconds |
| Started | Jun 29 08:29:41 PM PDT 24 |
| Finished | Jun 29 08:32:38 PM PDT 24 |
| Peak memory | 574320 kb |
| Host | smart-f13d88b5-c3a8-45bf-9fd7-21208c81fbc0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=485016034 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 88.xbar_stress_all _with_reset_error.485016034 |
| Directory | /workspace/88.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/88.xbar_unmapped_addr.4237402722 |
| Short name | T2622 |
| Test name | |
| Test status | |
| Simulation time | 1346107650 ps |
| CPU time | 59.12 seconds |
| Started | Jun 29 08:29:33 PM PDT 24 |
| Finished | Jun 29 08:30:32 PM PDT 24 |
| Peak memory | 574292 kb |
| Host | smart-21dd21aa-2eb9-4b6d-80db-ca084daa6adf |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4237402722 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 88.xbar_unmapped_addr.4237402722 |
| Directory | /workspace/88.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/89.xbar_access_same_device.1591420419 |
| Short name | T783 |
| Test name | |
| Test status | |
| Simulation time | 2507019209 ps |
| CPU time | 128.48 seconds |
| Started | Jun 29 08:29:41 PM PDT 24 |
| Finished | Jun 29 08:31:50 PM PDT 24 |
| Peak memory | 575360 kb |
| Host | smart-81fcb6c3-0ab0-4ced-adef-da0b573b1f61 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1591420419 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 89.xbar_access_same_device .1591420419 |
| Directory | /workspace/89.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/89.xbar_access_same_device_slow_rsp.1557722676 |
| Short name | T2330 |
| Test name | |
| Test status | |
| Simulation time | 116077555781 ps |
| CPU time | 2106.12 seconds |
| Started | Jun 29 08:29:42 PM PDT 24 |
| Finished | Jun 29 09:04:48 PM PDT 24 |
| Peak memory | 575504 kb |
| Host | smart-3293cffa-85d0-440b-b09e-ad304a7dc7a2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1557722676 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 89.xbar_access_same_ device_slow_rsp.1557722676 |
| Directory | /workspace/89.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/89.xbar_error_and_unmapped_addr.2568364546 |
| Short name | T2548 |
| Test name | |
| Test status | |
| Simulation time | 1308373684 ps |
| CPU time | 58.6 seconds |
| Started | Jun 29 08:29:52 PM PDT 24 |
| Finished | Jun 29 08:30:51 PM PDT 24 |
| Peak memory | 574504 kb |
| Host | smart-81aae381-6e44-402e-8b68-c9c70d66260c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2568364546 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 89.xbar_error_and_unmapped_add r.2568364546 |
| Directory | /workspace/89.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/89.xbar_error_random.3026130012 |
| Short name | T2445 |
| Test name | |
| Test status | |
| Simulation time | 182668349 ps |
| CPU time | 9.79 seconds |
| Started | Jun 29 08:29:40 PM PDT 24 |
| Finished | Jun 29 08:29:50 PM PDT 24 |
| Peak memory | 574228 kb |
| Host | smart-b632d18d-d082-4532-bc07-01035528fc42 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3026130012 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 89.xbar_error_random.3026130012 |
| Directory | /workspace/89.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/89.xbar_random_large_delays.902640238 |
| Short name | T2298 |
| Test name | |
| Test status | |
| Simulation time | 52363516011 ps |
| CPU time | 531.05 seconds |
| Started | Jun 29 08:29:41 PM PDT 24 |
| Finished | Jun 29 08:38:33 PM PDT 24 |
| Peak memory | 575384 kb |
| Host | smart-eacc4d70-aef9-48a1-906a-1cd7b1c6000b |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=902640238 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 89.xbar_random_large_delays.902640238 |
| Directory | /workspace/89.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/89.xbar_random_slow_rsp.3502929151 |
| Short name | T2714 |
| Test name | |
| Test status | |
| Simulation time | 20802517535 ps |
| CPU time | 364.57 seconds |
| Started | Jun 29 08:29:40 PM PDT 24 |
| Finished | Jun 29 08:35:45 PM PDT 24 |
| Peak memory | 575392 kb |
| Host | smart-3f24e3d9-9375-4107-bee9-0007c0901b1b |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3502929151 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 89.xbar_random_slow_rsp.3502929151 |
| Directory | /workspace/89.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/89.xbar_random_zero_delays.923706632 |
| Short name | T2763 |
| Test name | |
| Test status | |
| Simulation time | 440222069 ps |
| CPU time | 41.8 seconds |
| Started | Jun 29 08:29:41 PM PDT 24 |
| Finished | Jun 29 08:30:23 PM PDT 24 |
| Peak memory | 575332 kb |
| Host | smart-a3b2be2d-d41e-4b26-8515-85b99793e334 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=923706632 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 89.xbar_random_zero_dela ys.923706632 |
| Directory | /workspace/89.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/89.xbar_same_source.1070369211 |
| Short name | T529 |
| Test name | |
| Test status | |
| Simulation time | 198245285 ps |
| CPU time | 9.39 seconds |
| Started | Jun 29 08:29:42 PM PDT 24 |
| Finished | Jun 29 08:29:52 PM PDT 24 |
| Peak memory | 574076 kb |
| Host | smart-8a5a23cf-bc9f-4f68-8f1b-5f53a56f314f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1070369211 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 89.xbar_same_source.1070369211 |
| Directory | /workspace/89.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/89.xbar_smoke.3075359447 |
| Short name | T2857 |
| Test name | |
| Test status | |
| Simulation time | 218153935 ps |
| CPU time | 10.16 seconds |
| Started | Jun 29 08:29:40 PM PDT 24 |
| Finished | Jun 29 08:29:50 PM PDT 24 |
| Peak memory | 574264 kb |
| Host | smart-b981aa84-5ac7-4bf9-81f5-336f42494bad |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3075359447 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 89.xbar_smoke.3075359447 |
| Directory | /workspace/89.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/89.xbar_smoke_large_delays.2303635259 |
| Short name | T466 |
| Test name | |
| Test status | |
| Simulation time | 8467737026 ps |
| CPU time | 92.21 seconds |
| Started | Jun 29 08:29:43 PM PDT 24 |
| Finished | Jun 29 08:31:15 PM PDT 24 |
| Peak memory | 574332 kb |
| Host | smart-6c062f22-5549-46ed-989e-6256ffab4ab0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2303635259 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 89.xbar_smoke_large_delays.2303635259 |
| Directory | /workspace/89.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/89.xbar_smoke_slow_rsp.3544276901 |
| Short name | T1428 |
| Test name | |
| Test status | |
| Simulation time | 5287157908 ps |
| CPU time | 91.21 seconds |
| Started | Jun 29 08:29:42 PM PDT 24 |
| Finished | Jun 29 08:31:13 PM PDT 24 |
| Peak memory | 574324 kb |
| Host | smart-7488e93d-0110-48b9-823a-3cf701ca51a8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3544276901 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 89.xbar_smoke_slow_rsp.3544276901 |
| Directory | /workspace/89.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/89.xbar_smoke_zero_delays.27467185 |
| Short name | T1400 |
| Test name | |
| Test status | |
| Simulation time | 54337495 ps |
| CPU time | 7.52 seconds |
| Started | Jun 29 08:29:41 PM PDT 24 |
| Finished | Jun 29 08:29:49 PM PDT 24 |
| Peak memory | 566020 kb |
| Host | smart-fb2dcb33-ae5c-4e97-bc65-5ce691135321 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27467185 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 89.xbar_smoke_zero_delays.27467185 |
| Directory | /workspace/89.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/89.xbar_stress_all.2786685156 |
| Short name | T2255 |
| Test name | |
| Test status | |
| Simulation time | 11771713142 ps |
| CPU time | 447.82 seconds |
| Started | Jun 29 08:29:51 PM PDT 24 |
| Finished | Jun 29 08:37:19 PM PDT 24 |
| Peak memory | 575500 kb |
| Host | smart-1c02a171-6800-4dbc-9533-499e456edb97 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2786685156 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 89.xbar_stress_all.2786685156 |
| Directory | /workspace/89.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/89.xbar_stress_all_with_error.2229910263 |
| Short name | T2735 |
| Test name | |
| Test status | |
| Simulation time | 7297852360 ps |
| CPU time | 271.09 seconds |
| Started | Jun 29 08:29:52 PM PDT 24 |
| Finished | Jun 29 08:34:23 PM PDT 24 |
| Peak memory | 574104 kb |
| Host | smart-18d90d18-c65e-4d0c-84da-87220ebdb30d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2229910263 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 89.xbar_stress_all_with_error.2229910263 |
| Directory | /workspace/89.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/89.xbar_stress_all_with_rand_reset.1037770969 |
| Short name | T2239 |
| Test name | |
| Test status | |
| Simulation time | 3272811338 ps |
| CPU time | 405.45 seconds |
| Started | Jun 29 08:29:53 PM PDT 24 |
| Finished | Jun 29 08:36:39 PM PDT 24 |
| Peak memory | 575428 kb |
| Host | smart-ca2b7241-b6f1-4d7e-a91a-f583fddd0348 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1037770969 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 89.xbar_stress_all _with_rand_reset.1037770969 |
| Directory | /workspace/89.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/89.xbar_stress_all_with_reset_error.686908854 |
| Short name | T1349 |
| Test name | |
| Test status | |
| Simulation time | 86105487 ps |
| CPU time | 8.32 seconds |
| Started | Jun 29 08:29:50 PM PDT 24 |
| Finished | Jun 29 08:29:59 PM PDT 24 |
| Peak memory | 566060 kb |
| Host | smart-19817168-dee5-40f3-81fa-f7be485c4799 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=686908854 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 89.xbar_stress_all _with_reset_error.686908854 |
| Directory | /workspace/89.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/89.xbar_unmapped_addr.1370388655 |
| Short name | T1301 |
| Test name | |
| Test status | |
| Simulation time | 599846468 ps |
| CPU time | 27.7 seconds |
| Started | Jun 29 08:29:51 PM PDT 24 |
| Finished | Jun 29 08:30:19 PM PDT 24 |
| Peak memory | 575328 kb |
| Host | smart-6ca5e260-8f4c-4220-90b9-6f612ca4c443 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1370388655 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 89.xbar_unmapped_addr.1370388655 |
| Directory | /workspace/89.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/9.chip_csr_rw.3910651987 |
| Short name | T442 |
| Test name | |
| Test status | |
| Simulation time | 6556218362 ps |
| CPU time | 652.4 seconds |
| Started | Jun 29 08:14:14 PM PDT 24 |
| Finished | Jun 29 08:25:07 PM PDT 24 |
| Peak memory | 596740 kb |
| Host | smart-77768f0c-8494-4023-b9dd-2ce2433aa0cf |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3910651987 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.chip_csr_rw.3910651987 |
| Directory | /workspace/9.chip_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/9.chip_same_csr_outstanding.3640638756 |
| Short name | T1954 |
| Test name | |
| Test status | |
| Simulation time | 16132458431 ps |
| CPU time | 1818.12 seconds |
| Started | Jun 29 08:13:48 PM PDT 24 |
| Finished | Jun 29 08:44:07 PM PDT 24 |
| Peak memory | 591724 kb |
| Host | smart-69dfe745-722b-4594-8df7-9a72f0b5ee8a |
| User | root |
| Command | /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +run_same_csr_outstanding +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3640638756 -assert nopostproc +UVM_TE STNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb - cm_log /dev/null -cm_name 9.chip_same_csr_outstanding.3640638756 |
| Directory | /workspace/9.chip_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/9.xbar_access_same_device.2772360503 |
| Short name | T799 |
| Test name | |
| Test status | |
| Simulation time | 673783114 ps |
| CPU time | 35.81 seconds |
| Started | Jun 29 08:13:59 PM PDT 24 |
| Finished | Jun 29 08:14:35 PM PDT 24 |
| Peak memory | 575324 kb |
| Host | smart-6b6cb809-4430-4e38-ab73-89d8286fccf6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2772360503 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.xbar_access_same_device. 2772360503 |
| Directory | /workspace/9.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/9.xbar_access_same_device_slow_rsp.3262250589 |
| Short name | T2801 |
| Test name | |
| Test status | |
| Simulation time | 90485341400 ps |
| CPU time | 1694.25 seconds |
| Started | Jun 29 08:13:55 PM PDT 24 |
| Finished | Jun 29 08:42:09 PM PDT 24 |
| Peak memory | 574396 kb |
| Host | smart-96572ca2-ca83-4e23-bd21-b8e3d386e9d7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3262250589 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.xbar_access_same_d evice_slow_rsp.3262250589 |
| Directory | /workspace/9.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/9.xbar_error_and_unmapped_addr.3660914495 |
| Short name | T1750 |
| Test name | |
| Test status | |
| Simulation time | 584839505 ps |
| CPU time | 25.55 seconds |
| Started | Jun 29 08:14:04 PM PDT 24 |
| Finished | Jun 29 08:14:30 PM PDT 24 |
| Peak memory | 574504 kb |
| Host | smart-e106d04c-eb4b-458e-b1f6-28595a7b570b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3660914495 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.xbar_error_and_unmapped_addr .3660914495 |
| Directory | /workspace/9.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/9.xbar_error_random.428764784 |
| Short name | T636 |
| Test name | |
| Test status | |
| Simulation time | 467358723 ps |
| CPU time | 51.85 seconds |
| Started | Jun 29 08:14:04 PM PDT 24 |
| Finished | Jun 29 08:14:56 PM PDT 24 |
| Peak memory | 573936 kb |
| Host | smart-bebc752d-4abd-4a63-b25d-b0f8b400ec5a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=428764784 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.xbar_error_random.428764784 |
| Directory | /workspace/9.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/9.xbar_random.1173334592 |
| Short name | T1363 |
| Test name | |
| Test status | |
| Simulation time | 1766193162 ps |
| CPU time | 71.27 seconds |
| Started | Jun 29 08:13:58 PM PDT 24 |
| Finished | Jun 29 08:15:10 PM PDT 24 |
| Peak memory | 575336 kb |
| Host | smart-f66df289-e430-4f4f-8909-b6a0bb51cd6e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1173334592 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.xbar_random.1173334592 |
| Directory | /workspace/9.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/9.xbar_random_large_delays.3220249217 |
| Short name | T1851 |
| Test name | |
| Test status | |
| Simulation time | 19456838658 ps |
| CPU time | 209.09 seconds |
| Started | Jun 29 08:13:58 PM PDT 24 |
| Finished | Jun 29 08:17:27 PM PDT 24 |
| Peak memory | 575376 kb |
| Host | smart-b4cb8c28-3c83-41a4-a7f8-b26ac904c008 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3220249217 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.xbar_random_large_delays.3220249217 |
| Directory | /workspace/9.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/9.xbar_random_slow_rsp.3114278564 |
| Short name | T2422 |
| Test name | |
| Test status | |
| Simulation time | 43021433196 ps |
| CPU time | 737.12 seconds |
| Started | Jun 29 08:13:54 PM PDT 24 |
| Finished | Jun 29 08:26:12 PM PDT 24 |
| Peak memory | 575360 kb |
| Host | smart-583ae51c-64c4-42c1-a6e8-19c575513a87 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3114278564 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.xbar_random_slow_rsp.3114278564 |
| Directory | /workspace/9.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/9.xbar_random_zero_delays.1352923703 |
| Short name | T1905 |
| Test name | |
| Test status | |
| Simulation time | 311407621 ps |
| CPU time | 28.98 seconds |
| Started | Jun 29 08:13:55 PM PDT 24 |
| Finished | Jun 29 08:14:24 PM PDT 24 |
| Peak memory | 575268 kb |
| Host | smart-f55aa68e-16c1-4b75-8f86-20484d600ca4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1352923703 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.xbar_random_zero_dela ys.1352923703 |
| Directory | /workspace/9.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/9.xbar_same_source.386458021 |
| Short name | T2466 |
| Test name | |
| Test status | |
| Simulation time | 1023120442 ps |
| CPU time | 34.69 seconds |
| Started | Jun 29 08:13:55 PM PDT 24 |
| Finished | Jun 29 08:14:30 PM PDT 24 |
| Peak memory | 575288 kb |
| Host | smart-225f278b-c131-41fb-87c1-a43fb620a63e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=386458021 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.xbar_same_source.386458021 |
| Directory | /workspace/9.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/9.xbar_smoke.30624780 |
| Short name | T2153 |
| Test name | |
| Test status | |
| Simulation time | 182308359 ps |
| CPU time | 9.78 seconds |
| Started | Jun 29 08:13:46 PM PDT 24 |
| Finished | Jun 29 08:13:57 PM PDT 24 |
| Peak memory | 574256 kb |
| Host | smart-abec674e-8b8e-451b-9aa5-8654504d10a2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30624780 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.xbar_smoke.30624780 |
| Directory | /workspace/9.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/9.xbar_smoke_large_delays.3589971929 |
| Short name | T1451 |
| Test name | |
| Test status | |
| Simulation time | 6416137989 ps |
| CPU time | 68.21 seconds |
| Started | Jun 29 08:13:47 PM PDT 24 |
| Finished | Jun 29 08:14:55 PM PDT 24 |
| Peak memory | 574316 kb |
| Host | smart-1473c380-395b-4c9d-983d-6cc25894b329 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3589971929 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.xbar_smoke_large_delays.3589971929 |
| Directory | /workspace/9.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/9.xbar_smoke_slow_rsp.75255258 |
| Short name | T2358 |
| Test name | |
| Test status | |
| Simulation time | 4625296105 ps |
| CPU time | 82.35 seconds |
| Started | Jun 29 08:13:54 PM PDT 24 |
| Finished | Jun 29 08:15:17 PM PDT 24 |
| Peak memory | 566068 kb |
| Host | smart-5ec6680f-1e79-4a06-a6b6-dcf7e4184fab |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75255258 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.xbar_smoke_slow_rsp.75255258 |
| Directory | /workspace/9.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/9.xbar_smoke_zero_delays.3353632524 |
| Short name | T1811 |
| Test name | |
| Test status | |
| Simulation time | 34197686 ps |
| CPU time | 5.7 seconds |
| Started | Jun 29 08:13:49 PM PDT 24 |
| Finished | Jun 29 08:13:55 PM PDT 24 |
| Peak memory | 565936 kb |
| Host | smart-7b264ba2-cf62-44f1-b11b-722867f7e3be |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3353632524 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.xbar_smoke_zero_delays .3353632524 |
| Directory | /workspace/9.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/9.xbar_stress_all.2658219641 |
| Short name | T2115 |
| Test name | |
| Test status | |
| Simulation time | 2441070690 ps |
| CPU time | 98.95 seconds |
| Started | Jun 29 08:14:04 PM PDT 24 |
| Finished | Jun 29 08:15:43 PM PDT 24 |
| Peak memory | 575424 kb |
| Host | smart-1d1c5fae-4c6b-4d0e-acfc-9777331dfb0a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2658219641 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.xbar_stress_all.2658219641 |
| Directory | /workspace/9.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/9.xbar_stress_all_with_error.2313485458 |
| Short name | T1644 |
| Test name | |
| Test status | |
| Simulation time | 2218127345 ps |
| CPU time | 74.21 seconds |
| Started | Jun 29 08:14:04 PM PDT 24 |
| Finished | Jun 29 08:15:19 PM PDT 24 |
| Peak memory | 574572 kb |
| Host | smart-8f82b14f-3879-4383-a029-20d94249df55 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2313485458 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.xbar_stress_all_with_error.2313485458 |
| Directory | /workspace/9.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/9.xbar_stress_all_with_reset_error.464692669 |
| Short name | T2211 |
| Test name | |
| Test status | |
| Simulation time | 3683441163 ps |
| CPU time | 442.38 seconds |
| Started | Jun 29 08:14:04 PM PDT 24 |
| Finished | Jun 29 08:21:27 PM PDT 24 |
| Peak memory | 574452 kb |
| Host | smart-6d371922-2218-4c6e-a5fd-a411ab78bcdc |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=464692669 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.xbar_stress_all_ with_reset_error.464692669 |
| Directory | /workspace/9.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/9.xbar_unmapped_addr.640778547 |
| Short name | T1624 |
| Test name | |
| Test status | |
| Simulation time | 332189736 ps |
| CPU time | 46.22 seconds |
| Started | Jun 29 08:14:06 PM PDT 24 |
| Finished | Jun 29 08:14:53 PM PDT 24 |
| Peak memory | 574316 kb |
| Host | smart-26deee83-69a8-4629-9981-e0fd7b67f3f6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=640778547 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.xbar_unmapped_addr.640778547 |
| Directory | /workspace/9.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/90.xbar_access_same_device.1466546638 |
| Short name | T1409 |
| Test name | |
| Test status | |
| Simulation time | 1705910101 ps |
| CPU time | 73.73 seconds |
| Started | Jun 29 08:29:59 PM PDT 24 |
| Finished | Jun 29 08:31:13 PM PDT 24 |
| Peak memory | 575336 kb |
| Host | smart-8362c312-3ced-4a1d-a27a-63b5f78df6fd |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1466546638 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 90.xbar_access_same_device .1466546638 |
| Directory | /workspace/90.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/90.xbar_access_same_device_slow_rsp.3289818899 |
| Short name | T2795 |
| Test name | |
| Test status | |
| Simulation time | 81874487010 ps |
| CPU time | 1346.05 seconds |
| Started | Jun 29 08:29:59 PM PDT 24 |
| Finished | Jun 29 08:52:26 PM PDT 24 |
| Peak memory | 575440 kb |
| Host | smart-64745055-a018-442c-8db4-7f26a13f2e75 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3289818899 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 90.xbar_access_same_ device_slow_rsp.3289818899 |
| Directory | /workspace/90.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/90.xbar_error_and_unmapped_addr.944066626 |
| Short name | T2357 |
| Test name | |
| Test status | |
| Simulation time | 342300997 ps |
| CPU time | 16.4 seconds |
| Started | Jun 29 08:29:59 PM PDT 24 |
| Finished | Jun 29 08:30:16 PM PDT 24 |
| Peak memory | 573884 kb |
| Host | smart-0c4cbb33-a17b-4722-80c8-becf36a07a0b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=944066626 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 90.xbar_error_and_unmapped_addr .944066626 |
| Directory | /workspace/90.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/90.xbar_error_random.2237687120 |
| Short name | T2630 |
| Test name | |
| Test status | |
| Simulation time | 707097466 ps |
| CPU time | 29.75 seconds |
| Started | Jun 29 08:29:59 PM PDT 24 |
| Finished | Jun 29 08:30:29 PM PDT 24 |
| Peak memory | 574408 kb |
| Host | smart-f71ce231-b53e-492c-b27a-76df4631cf13 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2237687120 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 90.xbar_error_random.2237687120 |
| Directory | /workspace/90.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/90.xbar_random.2577134993 |
| Short name | T515 |
| Test name | |
| Test status | |
| Simulation time | 2310858155 ps |
| CPU time | 91.5 seconds |
| Started | Jun 29 08:29:54 PM PDT 24 |
| Finished | Jun 29 08:31:26 PM PDT 24 |
| Peak memory | 575372 kb |
| Host | smart-d0f9eac4-799d-4edc-88d9-8ef06a0dcbdf |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2577134993 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 90.xbar_random.2577134993 |
| Directory | /workspace/90.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/90.xbar_random_large_delays.191341532 |
| Short name | T2044 |
| Test name | |
| Test status | |
| Simulation time | 99580929359 ps |
| CPU time | 966.63 seconds |
| Started | Jun 29 08:29:52 PM PDT 24 |
| Finished | Jun 29 08:45:59 PM PDT 24 |
| Peak memory | 575440 kb |
| Host | smart-1e2529c6-f0a8-4153-86fb-5af7a6bd0cf7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=191341532 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 90.xbar_random_large_delays.191341532 |
| Directory | /workspace/90.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/90.xbar_random_slow_rsp.1194988688 |
| Short name | T1567 |
| Test name | |
| Test status | |
| Simulation time | 30830709504 ps |
| CPU time | 551.9 seconds |
| Started | Jun 29 08:29:54 PM PDT 24 |
| Finished | Jun 29 08:39:06 PM PDT 24 |
| Peak memory | 574456 kb |
| Host | smart-519fbd30-3ea0-40fd-90fb-95098c04331f |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1194988688 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 90.xbar_random_slow_rsp.1194988688 |
| Directory | /workspace/90.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/90.xbar_random_zero_delays.2734691311 |
| Short name | T1978 |
| Test name | |
| Test status | |
| Simulation time | 562990874 ps |
| CPU time | 46.46 seconds |
| Started | Jun 29 08:29:51 PM PDT 24 |
| Finished | Jun 29 08:30:38 PM PDT 24 |
| Peak memory | 574248 kb |
| Host | smart-e6b5264d-b474-4292-a1e0-d8f208eb3975 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2734691311 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 90.xbar_random_zero_del ays.2734691311 |
| Directory | /workspace/90.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/90.xbar_same_source.2660611874 |
| Short name | T1995 |
| Test name | |
| Test status | |
| Simulation time | 448274813 ps |
| CPU time | 37.15 seconds |
| Started | Jun 29 08:30:00 PM PDT 24 |
| Finished | Jun 29 08:30:37 PM PDT 24 |
| Peak memory | 575288 kb |
| Host | smart-2cfc5e6e-e000-48dc-a37a-33e356c3e687 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2660611874 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 90.xbar_same_source.2660611874 |
| Directory | /workspace/90.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/90.xbar_smoke.1083787946 |
| Short name | T2870 |
| Test name | |
| Test status | |
| Simulation time | 206546178 ps |
| CPU time | 9.31 seconds |
| Started | Jun 29 08:29:51 PM PDT 24 |
| Finished | Jun 29 08:30:01 PM PDT 24 |
| Peak memory | 574220 kb |
| Host | smart-b0d17212-0993-4cef-b1df-5fcd8c866431 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1083787946 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 90.xbar_smoke.1083787946 |
| Directory | /workspace/90.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/90.xbar_smoke_large_delays.1586535319 |
| Short name | T2386 |
| Test name | |
| Test status | |
| Simulation time | 6006103527 ps |
| CPU time | 60.57 seconds |
| Started | Jun 29 08:29:52 PM PDT 24 |
| Finished | Jun 29 08:30:53 PM PDT 24 |
| Peak memory | 574328 kb |
| Host | smart-82c84e80-2da7-4fbe-85a3-13d3fc9cee36 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1586535319 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 90.xbar_smoke_large_delays.1586535319 |
| Directory | /workspace/90.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/90.xbar_smoke_slow_rsp.2122806006 |
| Short name | T1988 |
| Test name | |
| Test status | |
| Simulation time | 5888432984 ps |
| CPU time | 101.35 seconds |
| Started | Jun 29 08:29:52 PM PDT 24 |
| Finished | Jun 29 08:31:34 PM PDT 24 |
| Peak memory | 574320 kb |
| Host | smart-b6548795-af73-4e4a-a343-a6a0f57365b7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2122806006 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 90.xbar_smoke_slow_rsp.2122806006 |
| Directory | /workspace/90.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/90.xbar_smoke_zero_delays.1024721839 |
| Short name | T1425 |
| Test name | |
| Test status | |
| Simulation time | 58671492 ps |
| CPU time | 7.28 seconds |
| Started | Jun 29 08:29:52 PM PDT 24 |
| Finished | Jun 29 08:29:59 PM PDT 24 |
| Peak memory | 566020 kb |
| Host | smart-04828058-bef8-4e28-81e1-5703186a380b |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1024721839 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 90.xbar_smoke_zero_delay s.1024721839 |
| Directory | /workspace/90.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/90.xbar_stress_all.3411899211 |
| Short name | T1823 |
| Test name | |
| Test status | |
| Simulation time | 2167238304 ps |
| CPU time | 188.85 seconds |
| Started | Jun 29 08:29:59 PM PDT 24 |
| Finished | Jun 29 08:33:08 PM PDT 24 |
| Peak memory | 574476 kb |
| Host | smart-b90e9b13-24cc-4f27-9b00-b92f7d454d27 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3411899211 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 90.xbar_stress_all.3411899211 |
| Directory | /workspace/90.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/90.xbar_stress_all_with_error.3176443779 |
| Short name | T2297 |
| Test name | |
| Test status | |
| Simulation time | 8904518023 ps |
| CPU time | 325.87 seconds |
| Started | Jun 29 08:29:58 PM PDT 24 |
| Finished | Jun 29 08:35:25 PM PDT 24 |
| Peak memory | 574720 kb |
| Host | smart-079269c6-a33a-4963-a252-5dc79b8a12f6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3176443779 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 90.xbar_stress_all_with_error.3176443779 |
| Directory | /workspace/90.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/90.xbar_stress_all_with_rand_reset.467187746 |
| Short name | T2036 |
| Test name | |
| Test status | |
| Simulation time | 7426490 ps |
| CPU time | 4.02 seconds |
| Started | Jun 29 08:29:59 PM PDT 24 |
| Finished | Jun 29 08:30:03 PM PDT 24 |
| Peak memory | 564956 kb |
| Host | smart-c455eedb-1bb5-441a-a08a-124266664fe9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=467187746 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_res et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 90.xbar_stress_all_ with_rand_reset.467187746 |
| Directory | /workspace/90.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/90.xbar_stress_all_with_reset_error.1626961663 |
| Short name | T804 |
| Test name | |
| Test status | |
| Simulation time | 2859617533 ps |
| CPU time | 285.29 seconds |
| Started | Jun 29 08:29:58 PM PDT 24 |
| Finished | Jun 29 08:34:43 PM PDT 24 |
| Peak memory | 574500 kb |
| Host | smart-2bb40a50-d0bb-4f25-81cf-46f53bd2b0e6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1626961663 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 90.xbar_stress_al l_with_reset_error.1626961663 |
| Directory | /workspace/90.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/90.xbar_unmapped_addr.4075472112 |
| Short name | T575 |
| Test name | |
| Test status | |
| Simulation time | 1282419118 ps |
| CPU time | 53.19 seconds |
| Started | Jun 29 08:29:57 PM PDT 24 |
| Finished | Jun 29 08:30:51 PM PDT 24 |
| Peak memory | 575368 kb |
| Host | smart-b32f0383-ad85-486d-8c20-0f3bdc346eb2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4075472112 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 90.xbar_unmapped_addr.4075472112 |
| Directory | /workspace/90.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/91.xbar_access_same_device.2578590265 |
| Short name | T772 |
| Test name | |
| Test status | |
| Simulation time | 3041094737 ps |
| CPU time | 134 seconds |
| Started | Jun 29 08:29:58 PM PDT 24 |
| Finished | Jun 29 08:32:13 PM PDT 24 |
| Peak memory | 574312 kb |
| Host | smart-634647c4-935d-4ff1-9bbc-7b571f688d44 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2578590265 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 91.xbar_access_same_device .2578590265 |
| Directory | /workspace/91.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/91.xbar_access_same_device_slow_rsp.2100154943 |
| Short name | T2292 |
| Test name | |
| Test status | |
| Simulation time | 100356253243 ps |
| CPU time | 1801.01 seconds |
| Started | Jun 29 08:30:02 PM PDT 24 |
| Finished | Jun 29 09:00:03 PM PDT 24 |
| Peak memory | 574580 kb |
| Host | smart-941f7555-dd98-4cfd-a8a7-87f70b39b679 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2100154943 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 91.xbar_access_same_ device_slow_rsp.2100154943 |
| Directory | /workspace/91.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/91.xbar_error_and_unmapped_addr.1125406847 |
| Short name | T2075 |
| Test name | |
| Test status | |
| Simulation time | 211403809 ps |
| CPU time | 12.12 seconds |
| Started | Jun 29 08:30:06 PM PDT 24 |
| Finished | Jun 29 08:30:18 PM PDT 24 |
| Peak memory | 573928 kb |
| Host | smart-95cbb619-340f-4172-afba-efc6ec56e949 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1125406847 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 91.xbar_error_and_unmapped_add r.1125406847 |
| Directory | /workspace/91.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/91.xbar_error_random.2114672751 |
| Short name | T1571 |
| Test name | |
| Test status | |
| Simulation time | 1798806696 ps |
| CPU time | 70.4 seconds |
| Started | Jun 29 08:30:06 PM PDT 24 |
| Finished | Jun 29 08:31:16 PM PDT 24 |
| Peak memory | 574484 kb |
| Host | smart-e707a1a8-b3a4-4d3e-9313-5667dc21acc9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2114672751 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 91.xbar_error_random.2114672751 |
| Directory | /workspace/91.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/91.xbar_random.1265196997 |
| Short name | T607 |
| Test name | |
| Test status | |
| Simulation time | 628707816 ps |
| CPU time | 57.64 seconds |
| Started | Jun 29 08:30:02 PM PDT 24 |
| Finished | Jun 29 08:31:00 PM PDT 24 |
| Peak memory | 575316 kb |
| Host | smart-0d194579-42cf-4e0f-b1fa-9d6e9175fae0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1265196997 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 91.xbar_random.1265196997 |
| Directory | /workspace/91.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/91.xbar_random_large_delays.3395734438 |
| Short name | T2160 |
| Test name | |
| Test status | |
| Simulation time | 72667099290 ps |
| CPU time | 832.57 seconds |
| Started | Jun 29 08:30:02 PM PDT 24 |
| Finished | Jun 29 08:43:55 PM PDT 24 |
| Peak memory | 575384 kb |
| Host | smart-034d40ba-a509-4789-beca-f552a1a2f441 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3395734438 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 91.xbar_random_large_delays.3395734438 |
| Directory | /workspace/91.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/91.xbar_random_slow_rsp.3988903415 |
| Short name | T2728 |
| Test name | |
| Test status | |
| Simulation time | 54158751077 ps |
| CPU time | 899.45 seconds |
| Started | Jun 29 08:29:59 PM PDT 24 |
| Finished | Jun 29 08:44:59 PM PDT 24 |
| Peak memory | 574308 kb |
| Host | smart-f45ec796-3a3f-48c1-a3db-8cae2df36bd7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3988903415 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 91.xbar_random_slow_rsp.3988903415 |
| Directory | /workspace/91.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/91.xbar_random_zero_delays.1202678120 |
| Short name | T2634 |
| Test name | |
| Test status | |
| Simulation time | 100858064 ps |
| CPU time | 12.58 seconds |
| Started | Jun 29 08:29:59 PM PDT 24 |
| Finished | Jun 29 08:30:12 PM PDT 24 |
| Peak memory | 575288 kb |
| Host | smart-94a4775e-8a20-4ba2-a64b-bbb875a3b428 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1202678120 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 91.xbar_random_zero_del ays.1202678120 |
| Directory | /workspace/91.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/91.xbar_same_source.2404498746 |
| Short name | T590 |
| Test name | |
| Test status | |
| Simulation time | 340099544 ps |
| CPU time | 27.54 seconds |
| Started | Jun 29 08:30:00 PM PDT 24 |
| Finished | Jun 29 08:30:28 PM PDT 24 |
| Peak memory | 575256 kb |
| Host | smart-34235003-ea84-47b4-9271-794bb30f4487 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2404498746 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 91.xbar_same_source.2404498746 |
| Directory | /workspace/91.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/91.xbar_smoke.624934427 |
| Short name | T2099 |
| Test name | |
| Test status | |
| Simulation time | 180573446 ps |
| CPU time | 8.94 seconds |
| Started | Jun 29 08:29:58 PM PDT 24 |
| Finished | Jun 29 08:30:07 PM PDT 24 |
| Peak memory | 574252 kb |
| Host | smart-2c53dff1-f373-4415-9347-0cfae9b0f5a9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=624934427 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 91.xbar_smoke.624934427 |
| Directory | /workspace/91.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/91.xbar_smoke_large_delays.2334040880 |
| Short name | T1490 |
| Test name | |
| Test status | |
| Simulation time | 8722289794 ps |
| CPU time | 94.01 seconds |
| Started | Jun 29 08:29:59 PM PDT 24 |
| Finished | Jun 29 08:31:34 PM PDT 24 |
| Peak memory | 574280 kb |
| Host | smart-c9face14-230d-4a64-bb48-d898a93c0af2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2334040880 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 91.xbar_smoke_large_delays.2334040880 |
| Directory | /workspace/91.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/91.xbar_smoke_slow_rsp.3746836595 |
| Short name | T2449 |
| Test name | |
| Test status | |
| Simulation time | 4744080544 ps |
| CPU time | 83.19 seconds |
| Started | Jun 29 08:29:57 PM PDT 24 |
| Finished | Jun 29 08:31:21 PM PDT 24 |
| Peak memory | 574192 kb |
| Host | smart-70eb3139-c64e-40ef-ab72-97972ef9d6a8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3746836595 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 91.xbar_smoke_slow_rsp.3746836595 |
| Directory | /workspace/91.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/91.xbar_smoke_zero_delays.4212134381 |
| Short name | T1687 |
| Test name | |
| Test status | |
| Simulation time | 46452219 ps |
| CPU time | 6.52 seconds |
| Started | Jun 29 08:29:59 PM PDT 24 |
| Finished | Jun 29 08:30:06 PM PDT 24 |
| Peak memory | 574260 kb |
| Host | smart-065689e1-2400-4136-9b33-a4cd72e63faf |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4212134381 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 91.xbar_smoke_zero_delay s.4212134381 |
| Directory | /workspace/91.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/91.xbar_stress_all.3887162338 |
| Short name | T453 |
| Test name | |
| Test status | |
| Simulation time | 1475893428 ps |
| CPU time | 113.55 seconds |
| Started | Jun 29 08:30:07 PM PDT 24 |
| Finished | Jun 29 08:32:01 PM PDT 24 |
| Peak memory | 575440 kb |
| Host | smart-bcc0e907-2238-4a00-aa1a-d7822c907064 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3887162338 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 91.xbar_stress_all.3887162338 |
| Directory | /workspace/91.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/91.xbar_stress_all_with_error.1395028942 |
| Short name | T1433 |
| Test name | |
| Test status | |
| Simulation time | 6822062842 ps |
| CPU time | 242.13 seconds |
| Started | Jun 29 08:30:07 PM PDT 24 |
| Finished | Jun 29 08:34:09 PM PDT 24 |
| Peak memory | 574464 kb |
| Host | smart-ec055ce5-d9f4-48ae-b147-00398ce2f3de |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1395028942 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 91.xbar_stress_all_with_error.1395028942 |
| Directory | /workspace/91.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/91.xbar_stress_all_with_rand_reset.3206389234 |
| Short name | T1619 |
| Test name | |
| Test status | |
| Simulation time | 613053814 ps |
| CPU time | 170.84 seconds |
| Started | Jun 29 08:30:06 PM PDT 24 |
| Finished | Jun 29 08:32:57 PM PDT 24 |
| Peak memory | 575444 kb |
| Host | smart-9abd4c8f-ab86-4d97-b00d-6be9d9d40997 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3206389234 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 91.xbar_stress_all _with_rand_reset.3206389234 |
| Directory | /workspace/91.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/91.xbar_stress_all_with_reset_error.1307577167 |
| Short name | T2025 |
| Test name | |
| Test status | |
| Simulation time | 434679750 ps |
| CPU time | 135.54 seconds |
| Started | Jun 29 08:30:06 PM PDT 24 |
| Finished | Jun 29 08:32:21 PM PDT 24 |
| Peak memory | 576468 kb |
| Host | smart-f5f4268d-94a2-48a8-9752-66c209c20228 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1307577167 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 91.xbar_stress_al l_with_reset_error.1307577167 |
| Directory | /workspace/91.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/91.xbar_unmapped_addr.641469979 |
| Short name | T2846 |
| Test name | |
| Test status | |
| Simulation time | 462693977 ps |
| CPU time | 23.15 seconds |
| Started | Jun 29 08:30:05 PM PDT 24 |
| Finished | Jun 29 08:30:29 PM PDT 24 |
| Peak memory | 574280 kb |
| Host | smart-0a760e50-49df-4a83-b425-de6016c3b0e1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=641469979 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 91.xbar_unmapped_addr.641469979 |
| Directory | /workspace/91.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/92.xbar_access_same_device.2683557192 |
| Short name | T2050 |
| Test name | |
| Test status | |
| Simulation time | 1677553391 ps |
| CPU time | 72.3 seconds |
| Started | Jun 29 08:30:16 PM PDT 24 |
| Finished | Jun 29 08:31:29 PM PDT 24 |
| Peak memory | 575328 kb |
| Host | smart-9862fbd9-22c1-4f06-9b76-560320c88d4f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2683557192 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 92.xbar_access_same_device .2683557192 |
| Directory | /workspace/92.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/92.xbar_access_same_device_slow_rsp.2113943525 |
| Short name | T2642 |
| Test name | |
| Test status | |
| Simulation time | 19286226501 ps |
| CPU time | 335.57 seconds |
| Started | Jun 29 08:30:13 PM PDT 24 |
| Finished | Jun 29 08:35:49 PM PDT 24 |
| Peak memory | 575396 kb |
| Host | smart-ab0c98c9-35ce-4920-b7f2-38bf91978169 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2113943525 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 92.xbar_access_same_ device_slow_rsp.2113943525 |
| Directory | /workspace/92.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/92.xbar_error_and_unmapped_addr.4092876745 |
| Short name | T1534 |
| Test name | |
| Test status | |
| Simulation time | 134139763 ps |
| CPU time | 17.36 seconds |
| Started | Jun 29 08:30:15 PM PDT 24 |
| Finished | Jun 29 08:30:33 PM PDT 24 |
| Peak memory | 574496 kb |
| Host | smart-2aa3f1e2-5547-4e39-a2f4-7be2f13bedeb |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4092876745 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 92.xbar_error_and_unmapped_add r.4092876745 |
| Directory | /workspace/92.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/92.xbar_error_random.2435020742 |
| Short name | T1351 |
| Test name | |
| Test status | |
| Simulation time | 2653418239 ps |
| CPU time | 104.99 seconds |
| Started | Jun 29 08:30:17 PM PDT 24 |
| Finished | Jun 29 08:32:03 PM PDT 24 |
| Peak memory | 574336 kb |
| Host | smart-21177aaf-65c3-4310-842c-8b27eea522ef |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2435020742 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 92.xbar_error_random.2435020742 |
| Directory | /workspace/92.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/92.xbar_random.1337943159 |
| Short name | T1710 |
| Test name | |
| Test status | |
| Simulation time | 389699187 ps |
| CPU time | 40.04 seconds |
| Started | Jun 29 08:30:12 PM PDT 24 |
| Finished | Jun 29 08:30:52 PM PDT 24 |
| Peak memory | 575316 kb |
| Host | smart-1c1f5be2-0564-429d-b430-b767f50043cd |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1337943159 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 92.xbar_random.1337943159 |
| Directory | /workspace/92.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/92.xbar_random_large_delays.721466189 |
| Short name | T2584 |
| Test name | |
| Test status | |
| Simulation time | 12847066514 ps |
| CPU time | 129.71 seconds |
| Started | Jun 29 08:30:15 PM PDT 24 |
| Finished | Jun 29 08:32:25 PM PDT 24 |
| Peak memory | 575388 kb |
| Host | smart-3b521a66-b193-4d58-a112-ae0dbd99f621 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=721466189 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 92.xbar_random_large_delays.721466189 |
| Directory | /workspace/92.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/92.xbar_random_slow_rsp.289884304 |
| Short name | T2683 |
| Test name | |
| Test status | |
| Simulation time | 53170491043 ps |
| CPU time | 963.8 seconds |
| Started | Jun 29 08:30:17 PM PDT 24 |
| Finished | Jun 29 08:46:21 PM PDT 24 |
| Peak memory | 575536 kb |
| Host | smart-1cd6df55-5608-4930-9bc0-13251298f5d6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=289884304 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 92.xbar_random_slow_rsp.289884304 |
| Directory | /workspace/92.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/92.xbar_random_zero_delays.2313893688 |
| Short name | T2150 |
| Test name | |
| Test status | |
| Simulation time | 320453644 ps |
| CPU time | 30.21 seconds |
| Started | Jun 29 08:30:14 PM PDT 24 |
| Finished | Jun 29 08:30:45 PM PDT 24 |
| Peak memory | 574184 kb |
| Host | smart-bfd4fb87-122f-4c84-bbf5-b7f38555f49b |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2313893688 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 92.xbar_random_zero_del ays.2313893688 |
| Directory | /workspace/92.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/92.xbar_same_source.1406237215 |
| Short name | T2491 |
| Test name | |
| Test status | |
| Simulation time | 1445113283 ps |
| CPU time | 49.08 seconds |
| Started | Jun 29 08:30:14 PM PDT 24 |
| Finished | Jun 29 08:31:03 PM PDT 24 |
| Peak memory | 575228 kb |
| Host | smart-a7d0542a-fd26-486a-bc53-615d9d396ebf |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1406237215 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 92.xbar_same_source.1406237215 |
| Directory | /workspace/92.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/92.xbar_smoke.1913262874 |
| Short name | T464 |
| Test name | |
| Test status | |
| Simulation time | 191682579 ps |
| CPU time | 9.25 seconds |
| Started | Jun 29 08:30:22 PM PDT 24 |
| Finished | Jun 29 08:30:31 PM PDT 24 |
| Peak memory | 565928 kb |
| Host | smart-61bb589a-0e3d-4d60-8aea-1ded76c80ea8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1913262874 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 92.xbar_smoke.1913262874 |
| Directory | /workspace/92.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/92.xbar_smoke_large_delays.2667140411 |
| Short name | T1478 |
| Test name | |
| Test status | |
| Simulation time | 8626415059 ps |
| CPU time | 91.44 seconds |
| Started | Jun 29 08:30:14 PM PDT 24 |
| Finished | Jun 29 08:31:46 PM PDT 24 |
| Peak memory | 574316 kb |
| Host | smart-b2190af2-37c9-4925-87da-0de9d8d3a247 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2667140411 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 92.xbar_smoke_large_delays.2667140411 |
| Directory | /workspace/92.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/92.xbar_smoke_slow_rsp.422258054 |
| Short name | T1856 |
| Test name | |
| Test status | |
| Simulation time | 5280798273 ps |
| CPU time | 94.88 seconds |
| Started | Jun 29 08:30:13 PM PDT 24 |
| Finished | Jun 29 08:31:48 PM PDT 24 |
| Peak memory | 574204 kb |
| Host | smart-74773a37-4df3-49d9-8433-143a1b8427df |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=422258054 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 92.xbar_smoke_slow_rsp.422258054 |
| Directory | /workspace/92.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/92.xbar_smoke_zero_delays.3426046584 |
| Short name | T1745 |
| Test name | |
| Test status | |
| Simulation time | 55135959 ps |
| CPU time | 7.39 seconds |
| Started | Jun 29 08:30:16 PM PDT 24 |
| Finished | Jun 29 08:30:24 PM PDT 24 |
| Peak memory | 574256 kb |
| Host | smart-0aaf558a-b188-4110-bbfe-c300a51c5e04 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3426046584 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 92.xbar_smoke_zero_delay s.3426046584 |
| Directory | /workspace/92.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/92.xbar_stress_all.1040073659 |
| Short name | T2154 |
| Test name | |
| Test status | |
| Simulation time | 19401496920 ps |
| CPU time | 712.47 seconds |
| Started | Jun 29 08:30:15 PM PDT 24 |
| Finished | Jun 29 08:42:08 PM PDT 24 |
| Peak memory | 575492 kb |
| Host | smart-e00bf7dd-bcda-4e1e-b344-cc93ab50e387 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1040073659 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 92.xbar_stress_all.1040073659 |
| Directory | /workspace/92.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/92.xbar_stress_all_with_error.3461354865 |
| Short name | T2833 |
| Test name | |
| Test status | |
| Simulation time | 7586620732 ps |
| CPU time | 321.99 seconds |
| Started | Jun 29 08:30:22 PM PDT 24 |
| Finished | Jun 29 08:35:44 PM PDT 24 |
| Peak memory | 574432 kb |
| Host | smart-45d85bc5-efbe-4f77-b465-796950c8db4d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3461354865 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 92.xbar_stress_all_with_error.3461354865 |
| Directory | /workspace/92.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/92.xbar_stress_all_with_reset_error.1880879332 |
| Short name | T2872 |
| Test name | |
| Test status | |
| Simulation time | 456971226 ps |
| CPU time | 116.94 seconds |
| Started | Jun 29 08:30:13 PM PDT 24 |
| Finished | Jun 29 08:32:10 PM PDT 24 |
| Peak memory | 574452 kb |
| Host | smart-dc2f921d-c4ad-437b-ad27-f71b44815639 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1880879332 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 92.xbar_stress_al l_with_reset_error.1880879332 |
| Directory | /workspace/92.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/92.xbar_unmapped_addr.4238672698 |
| Short name | T1792 |
| Test name | |
| Test status | |
| Simulation time | 248935521 ps |
| CPU time | 31.54 seconds |
| Started | Jun 29 08:30:14 PM PDT 24 |
| Finished | Jun 29 08:30:46 PM PDT 24 |
| Peak memory | 575348 kb |
| Host | smart-80aa6a66-80f0-4480-b255-26c211cbf9f2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4238672698 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 92.xbar_unmapped_addr.4238672698 |
| Directory | /workspace/92.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/93.xbar_access_same_device.904300908 |
| Short name | T2373 |
| Test name | |
| Test status | |
| Simulation time | 834871651 ps |
| CPU time | 65.6 seconds |
| Started | Jun 29 08:30:25 PM PDT 24 |
| Finished | Jun 29 08:31:31 PM PDT 24 |
| Peak memory | 575332 kb |
| Host | smart-986151b0-f7db-41cb-ab65-23b3cba15ed7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=904300908 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 93.xbar_access_same_device. 904300908 |
| Directory | /workspace/93.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/93.xbar_access_same_device_slow_rsp.2808425920 |
| Short name | T2195 |
| Test name | |
| Test status | |
| Simulation time | 94803932545 ps |
| CPU time | 1655.61 seconds |
| Started | Jun 29 08:30:25 PM PDT 24 |
| Finished | Jun 29 08:58:02 PM PDT 24 |
| Peak memory | 574372 kb |
| Host | smart-c95018ba-e4e3-46b6-bac3-e42beec5ce6c |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2808425920 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 93.xbar_access_same_ device_slow_rsp.2808425920 |
| Directory | /workspace/93.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/93.xbar_error_and_unmapped_addr.1494298787 |
| Short name | T2722 |
| Test name | |
| Test status | |
| Simulation time | 137039993 ps |
| CPU time | 15.42 seconds |
| Started | Jun 29 08:30:24 PM PDT 24 |
| Finished | Jun 29 08:30:41 PM PDT 24 |
| Peak memory | 574500 kb |
| Host | smart-df92be45-40d8-4634-8e0e-4ec26ad44348 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1494298787 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 93.xbar_error_and_unmapped_add r.1494298787 |
| Directory | /workspace/93.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/93.xbar_error_random.2655686924 |
| Short name | T2664 |
| Test name | |
| Test status | |
| Simulation time | 2119220390 ps |
| CPU time | 84.95 seconds |
| Started | Jun 29 08:30:22 PM PDT 24 |
| Finished | Jun 29 08:31:47 PM PDT 24 |
| Peak memory | 573872 kb |
| Host | smart-5b44decf-8657-43d8-a3c0-0ffb50efb15f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2655686924 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 93.xbar_error_random.2655686924 |
| Directory | /workspace/93.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/93.xbar_random.2777018715 |
| Short name | T2345 |
| Test name | |
| Test status | |
| Simulation time | 251283752 ps |
| CPU time | 12.43 seconds |
| Started | Jun 29 08:30:25 PM PDT 24 |
| Finished | Jun 29 08:30:38 PM PDT 24 |
| Peak memory | 574280 kb |
| Host | smart-fb086af5-4e75-4b6a-9ec3-6130a2846e7e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2777018715 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 93.xbar_random.2777018715 |
| Directory | /workspace/93.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/93.xbar_random_large_delays.1671453690 |
| Short name | T572 |
| Test name | |
| Test status | |
| Simulation time | 80943374267 ps |
| CPU time | 883.81 seconds |
| Started | Jun 29 08:30:22 PM PDT 24 |
| Finished | Jun 29 08:45:06 PM PDT 24 |
| Peak memory | 575384 kb |
| Host | smart-4b64a6d7-c04d-4eb5-8266-51c320ea3496 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1671453690 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 93.xbar_random_large_delays.1671453690 |
| Directory | /workspace/93.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/93.xbar_random_slow_rsp.997123112 |
| Short name | T2608 |
| Test name | |
| Test status | |
| Simulation time | 19472750520 ps |
| CPU time | 347.29 seconds |
| Started | Jun 29 08:30:24 PM PDT 24 |
| Finished | Jun 29 08:36:12 PM PDT 24 |
| Peak memory | 575392 kb |
| Host | smart-22e6f470-73e0-4adc-934b-494a6fb54055 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=997123112 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 93.xbar_random_slow_rsp.997123112 |
| Directory | /workspace/93.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/93.xbar_random_zero_delays.1903870883 |
| Short name | T1914 |
| Test name | |
| Test status | |
| Simulation time | 365029919 ps |
| CPU time | 33 seconds |
| Started | Jun 29 08:30:21 PM PDT 24 |
| Finished | Jun 29 08:30:54 PM PDT 24 |
| Peak memory | 575308 kb |
| Host | smart-4a2f85e0-b175-4b88-a2f1-1b18b6de867b |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1903870883 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 93.xbar_random_zero_del ays.1903870883 |
| Directory | /workspace/93.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/93.xbar_same_source.3789083619 |
| Short name | T2117 |
| Test name | |
| Test status | |
| Simulation time | 992050386 ps |
| CPU time | 28.61 seconds |
| Started | Jun 29 08:30:25 PM PDT 24 |
| Finished | Jun 29 08:30:54 PM PDT 24 |
| Peak memory | 575280 kb |
| Host | smart-58cc9ecc-a60a-4293-9f41-40c9b2c8aa9a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3789083619 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 93.xbar_same_source.3789083619 |
| Directory | /workspace/93.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/93.xbar_smoke.526884971 |
| Short name | T2880 |
| Test name | |
| Test status | |
| Simulation time | 43601118 ps |
| CPU time | 6.13 seconds |
| Started | Jun 29 08:30:12 PM PDT 24 |
| Finished | Jun 29 08:30:18 PM PDT 24 |
| Peak memory | 574260 kb |
| Host | smart-4a7affbd-8e82-484d-8b1f-51420ee31aee |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=526884971 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 93.xbar_smoke.526884971 |
| Directory | /workspace/93.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/93.xbar_smoke_large_delays.1919771521 |
| Short name | T1646 |
| Test name | |
| Test status | |
| Simulation time | 6550485842 ps |
| CPU time | 71.82 seconds |
| Started | Jun 29 08:30:22 PM PDT 24 |
| Finished | Jun 29 08:31:34 PM PDT 24 |
| Peak memory | 574300 kb |
| Host | smart-3708401a-8a55-4f2a-be8f-29e2389eaa12 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1919771521 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 93.xbar_smoke_large_delays.1919771521 |
| Directory | /workspace/93.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/93.xbar_smoke_slow_rsp.1207378677 |
| Short name | T1668 |
| Test name | |
| Test status | |
| Simulation time | 6237666147 ps |
| CPU time | 108.26 seconds |
| Started | Jun 29 08:30:14 PM PDT 24 |
| Finished | Jun 29 08:32:02 PM PDT 24 |
| Peak memory | 574324 kb |
| Host | smart-b3cc080a-5e09-46ab-8e93-df19d9c13473 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1207378677 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 93.xbar_smoke_slow_rsp.1207378677 |
| Directory | /workspace/93.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/93.xbar_smoke_zero_delays.4058428128 |
| Short name | T2609 |
| Test name | |
| Test status | |
| Simulation time | 45499866 ps |
| CPU time | 6.66 seconds |
| Started | Jun 29 08:30:18 PM PDT 24 |
| Finished | Jun 29 08:30:25 PM PDT 24 |
| Peak memory | 566012 kb |
| Host | smart-6c5f7c11-ad18-4a6e-910d-950e0607b36e |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4058428128 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 93.xbar_smoke_zero_delay s.4058428128 |
| Directory | /workspace/93.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/93.xbar_stress_all.4213516478 |
| Short name | T2342 |
| Test name | |
| Test status | |
| Simulation time | 1868545368 ps |
| CPU time | 158.48 seconds |
| Started | Jun 29 08:30:24 PM PDT 24 |
| Finished | Jun 29 08:33:04 PM PDT 24 |
| Peak memory | 575456 kb |
| Host | smart-0ce5f647-fa57-4955-904e-871097c8ff6b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4213516478 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 93.xbar_stress_all.4213516478 |
| Directory | /workspace/93.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/93.xbar_stress_all_with_error.825544411 |
| Short name | T2708 |
| Test name | |
| Test status | |
| Simulation time | 842496445 ps |
| CPU time | 95.54 seconds |
| Started | Jun 29 08:30:33 PM PDT 24 |
| Finished | Jun 29 08:32:09 PM PDT 24 |
| Peak memory | 574404 kb |
| Host | smart-cd807f64-21d4-45e5-8b53-805bc99449b8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=825544411 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 93.xbar_stress_all_with_error.825544411 |
| Directory | /workspace/93.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/93.xbar_stress_all_with_reset_error.2772780871 |
| Short name | T633 |
| Test name | |
| Test status | |
| Simulation time | 834816198 ps |
| CPU time | 107.65 seconds |
| Started | Jun 29 08:30:39 PM PDT 24 |
| Finished | Jun 29 08:32:27 PM PDT 24 |
| Peak memory | 574404 kb |
| Host | smart-c47d96f9-9b08-451c-b4da-ca28c5c4ae3a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2772780871 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 93.xbar_stress_al l_with_reset_error.2772780871 |
| Directory | /workspace/93.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/93.xbar_unmapped_addr.1113048981 |
| Short name | T573 |
| Test name | |
| Test status | |
| Simulation time | 1215997663 ps |
| CPU time | 63.08 seconds |
| Started | Jun 29 08:30:22 PM PDT 24 |
| Finished | Jun 29 08:31:26 PM PDT 24 |
| Peak memory | 575380 kb |
| Host | smart-3da92056-2e9f-4026-9f80-204f9139e52c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1113048981 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 93.xbar_unmapped_addr.1113048981 |
| Directory | /workspace/93.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/94.xbar_access_same_device.2840119459 |
| Short name | T1408 |
| Test name | |
| Test status | |
| Simulation time | 1278157767 ps |
| CPU time | 53.95 seconds |
| Started | Jun 29 08:30:30 PM PDT 24 |
| Finished | Jun 29 08:31:24 PM PDT 24 |
| Peak memory | 574220 kb |
| Host | smart-d27893d1-ece2-444d-a25b-fe33169410a5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2840119459 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 94.xbar_access_same_device .2840119459 |
| Directory | /workspace/94.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/94.xbar_access_same_device_slow_rsp.3808914580 |
| Short name | T457 |
| Test name | |
| Test status | |
| Simulation time | 126362173711 ps |
| CPU time | 2220.07 seconds |
| Started | Jun 29 08:30:29 PM PDT 24 |
| Finished | Jun 29 09:07:29 PM PDT 24 |
| Peak memory | 575520 kb |
| Host | smart-2f76252c-c785-4a22-a506-c996b4d7552b |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3808914580 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 94.xbar_access_same_ device_slow_rsp.3808914580 |
| Directory | /workspace/94.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/94.xbar_error_and_unmapped_addr.265414571 |
| Short name | T2650 |
| Test name | |
| Test status | |
| Simulation time | 115639779 ps |
| CPU time | 16.79 seconds |
| Started | Jun 29 08:30:30 PM PDT 24 |
| Finished | Jun 29 08:30:47 PM PDT 24 |
| Peak memory | 574508 kb |
| Host | smart-123c3070-7727-4e3e-a872-43970e393a84 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=265414571 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 94.xbar_error_and_unmapped_addr .265414571 |
| Directory | /workspace/94.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/94.xbar_error_random.2640027483 |
| Short name | T1527 |
| Test name | |
| Test status | |
| Simulation time | 260337123 ps |
| CPU time | 13.41 seconds |
| Started | Jun 29 08:30:29 PM PDT 24 |
| Finished | Jun 29 08:30:43 PM PDT 24 |
| Peak memory | 573928 kb |
| Host | smart-273c9a96-5eee-4bad-aabb-5f2d9f563d52 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2640027483 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 94.xbar_error_random.2640027483 |
| Directory | /workspace/94.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/94.xbar_random.1411726861 |
| Short name | T508 |
| Test name | |
| Test status | |
| Simulation time | 1470690807 ps |
| CPU time | 53.49 seconds |
| Started | Jun 29 08:30:31 PM PDT 24 |
| Finished | Jun 29 08:31:25 PM PDT 24 |
| Peak memory | 575232 kb |
| Host | smart-3cc6d29f-9982-4842-8dca-219d24a1bef6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1411726861 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 94.xbar_random.1411726861 |
| Directory | /workspace/94.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/94.xbar_random_slow_rsp.2174224244 |
| Short name | T1688 |
| Test name | |
| Test status | |
| Simulation time | 28842237035 ps |
| CPU time | 513.89 seconds |
| Started | Jun 29 08:30:39 PM PDT 24 |
| Finished | Jun 29 08:39:13 PM PDT 24 |
| Peak memory | 575356 kb |
| Host | smart-0c196510-21aa-4b2f-af1a-75f94c20b0b0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2174224244 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 94.xbar_random_slow_rsp.2174224244 |
| Directory | /workspace/94.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/94.xbar_random_zero_delays.2672940432 |
| Short name | T593 |
| Test name | |
| Test status | |
| Simulation time | 133440020 ps |
| CPU time | 14.33 seconds |
| Started | Jun 29 08:30:29 PM PDT 24 |
| Finished | Jun 29 08:30:44 PM PDT 24 |
| Peak memory | 574196 kb |
| Host | smart-62a56d14-0bf1-49fd-bb37-6833b0fb495f |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2672940432 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 94.xbar_random_zero_del ays.2672940432 |
| Directory | /workspace/94.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/94.xbar_same_source.4274579353 |
| Short name | T2002 |
| Test name | |
| Test status | |
| Simulation time | 100753581 ps |
| CPU time | 11.2 seconds |
| Started | Jun 29 08:30:39 PM PDT 24 |
| Finished | Jun 29 08:30:51 PM PDT 24 |
| Peak memory | 575156 kb |
| Host | smart-dff324d1-9a92-4633-a867-cd171d49ea49 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4274579353 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 94.xbar_same_source.4274579353 |
| Directory | /workspace/94.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/94.xbar_smoke.889058861 |
| Short name | T1376 |
| Test name | |
| Test status | |
| Simulation time | 202010773 ps |
| CPU time | 9.48 seconds |
| Started | Jun 29 08:30:31 PM PDT 24 |
| Finished | Jun 29 08:30:41 PM PDT 24 |
| Peak memory | 565948 kb |
| Host | smart-9ca98e8e-8b1f-45bc-b018-ff767b5d7219 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=889058861 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 94.xbar_smoke.889058861 |
| Directory | /workspace/94.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/94.xbar_smoke_large_delays.1692619797 |
| Short name | T1816 |
| Test name | |
| Test status | |
| Simulation time | 8782981190 ps |
| CPU time | 102.49 seconds |
| Started | Jun 29 08:30:33 PM PDT 24 |
| Finished | Jun 29 08:32:16 PM PDT 24 |
| Peak memory | 574320 kb |
| Host | smart-6ef163fa-dba5-40d3-9a0b-2ca03b9ad762 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1692619797 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 94.xbar_smoke_large_delays.1692619797 |
| Directory | /workspace/94.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/94.xbar_smoke_slow_rsp.2186316651 |
| Short name | T2302 |
| Test name | |
| Test status | |
| Simulation time | 6833884243 ps |
| CPU time | 114.5 seconds |
| Started | Jun 29 08:30:38 PM PDT 24 |
| Finished | Jun 29 08:32:32 PM PDT 24 |
| Peak memory | 574292 kb |
| Host | smart-bfade5fd-3229-417d-a229-d2f2e69c8345 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2186316651 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 94.xbar_smoke_slow_rsp.2186316651 |
| Directory | /workspace/94.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/94.xbar_smoke_zero_delays.3987160905 |
| Short name | T530 |
| Test name | |
| Test status | |
| Simulation time | 41772370 ps |
| CPU time | 6.13 seconds |
| Started | Jun 29 08:30:29 PM PDT 24 |
| Finished | Jun 29 08:30:36 PM PDT 24 |
| Peak memory | 574260 kb |
| Host | smart-8276daf7-c47d-4c22-9752-9c5da43f483a |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3987160905 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 94.xbar_smoke_zero_delay s.3987160905 |
| Directory | /workspace/94.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/94.xbar_stress_all.2537987040 |
| Short name | T2322 |
| Test name | |
| Test status | |
| Simulation time | 10162723478 ps |
| CPU time | 438.71 seconds |
| Started | Jun 29 08:30:40 PM PDT 24 |
| Finished | Jun 29 08:37:59 PM PDT 24 |
| Peak memory | 574600 kb |
| Host | smart-8bd45595-e5bd-440d-9beb-9d541b3bf158 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2537987040 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 94.xbar_stress_all.2537987040 |
| Directory | /workspace/94.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/94.xbar_stress_all_with_error.274155561 |
| Short name | T637 |
| Test name | |
| Test status | |
| Simulation time | 1085327361 ps |
| CPU time | 84.14 seconds |
| Started | Jun 29 08:30:41 PM PDT 24 |
| Finished | Jun 29 08:32:05 PM PDT 24 |
| Peak memory | 574476 kb |
| Host | smart-d381a17d-8d1b-4f4b-8bf2-4ad3786086df |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=274155561 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 94.xbar_stress_all_with_error.274155561 |
| Directory | /workspace/94.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/94.xbar_stress_all_with_rand_reset.3172984697 |
| Short name | T438 |
| Test name | |
| Test status | |
| Simulation time | 935527089 ps |
| CPU time | 199.01 seconds |
| Started | Jun 29 08:30:38 PM PDT 24 |
| Finished | Jun 29 08:33:57 PM PDT 24 |
| Peak memory | 575452 kb |
| Host | smart-4ed20ed8-a7a0-4d2e-ace9-3e9dfc061dbf |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3172984697 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 94.xbar_stress_all _with_rand_reset.3172984697 |
| Directory | /workspace/94.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/94.xbar_stress_all_with_reset_error.4105377191 |
| Short name | T1749 |
| Test name | |
| Test status | |
| Simulation time | 698098425 ps |
| CPU time | 221.85 seconds |
| Started | Jun 29 08:30:38 PM PDT 24 |
| Finished | Jun 29 08:34:21 PM PDT 24 |
| Peak memory | 574412 kb |
| Host | smart-f45f8fcc-c331-4c15-bd4e-1c025d40f6ca |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4105377191 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 94.xbar_stress_al l_with_reset_error.4105377191 |
| Directory | /workspace/94.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/94.xbar_unmapped_addr.1913571832 |
| Short name | T1393 |
| Test name | |
| Test status | |
| Simulation time | 303793540 ps |
| CPU time | 16.6 seconds |
| Started | Jun 29 08:30:32 PM PDT 24 |
| Finished | Jun 29 08:30:49 PM PDT 24 |
| Peak memory | 575328 kb |
| Host | smart-8b9ca6c5-c39b-492d-86bf-e7144ebce63a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1913571832 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 94.xbar_unmapped_addr.1913571832 |
| Directory | /workspace/94.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/95.xbar_access_same_device.480633950 |
| Short name | T776 |
| Test name | |
| Test status | |
| Simulation time | 2252286349 ps |
| CPU time | 100.23 seconds |
| Started | Jun 29 08:30:45 PM PDT 24 |
| Finished | Jun 29 08:32:25 PM PDT 24 |
| Peak memory | 575400 kb |
| Host | smart-65ab3fe6-7b7f-4532-ab58-48c0157e455c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=480633950 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 95.xbar_access_same_device. 480633950 |
| Directory | /workspace/95.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/95.xbar_access_same_device_slow_rsp.221321538 |
| Short name | T777 |
| Test name | |
| Test status | |
| Simulation time | 89202806515 ps |
| CPU time | 1600.62 seconds |
| Started | Jun 29 08:30:44 PM PDT 24 |
| Finished | Jun 29 08:57:26 PM PDT 24 |
| Peak memory | 574416 kb |
| Host | smart-48e56262-7c8e-4228-b000-00778365df59 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=221321538 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 95.xbar_access_same_d evice_slow_rsp.221321538 |
| Directory | /workspace/95.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/95.xbar_error_and_unmapped_addr.2235194903 |
| Short name | T1366 |
| Test name | |
| Test status | |
| Simulation time | 342930479 ps |
| CPU time | 17.02 seconds |
| Started | Jun 29 08:30:43 PM PDT 24 |
| Finished | Jun 29 08:31:01 PM PDT 24 |
| Peak memory | 574508 kb |
| Host | smart-6020905d-b8d8-40d7-a71c-b6bb81616a83 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2235194903 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 95.xbar_error_and_unmapped_add r.2235194903 |
| Directory | /workspace/95.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/95.xbar_error_random.1861179621 |
| Short name | T2649 |
| Test name | |
| Test status | |
| Simulation time | 580472004 ps |
| CPU time | 48.43 seconds |
| Started | Jun 29 08:30:46 PM PDT 24 |
| Finished | Jun 29 08:31:35 PM PDT 24 |
| Peak memory | 573936 kb |
| Host | smart-adf0b020-3dc0-46f1-a838-26e51a39d258 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1861179621 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 95.xbar_error_random.1861179621 |
| Directory | /workspace/95.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/95.xbar_random.492799059 |
| Short name | T1332 |
| Test name | |
| Test status | |
| Simulation time | 182905484 ps |
| CPU time | 19.93 seconds |
| Started | Jun 29 08:30:37 PM PDT 24 |
| Finished | Jun 29 08:30:57 PM PDT 24 |
| Peak memory | 575320 kb |
| Host | smart-0d2c7c9a-1705-4d93-bc89-252391075c5a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=492799059 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 95.xbar_random.492799059 |
| Directory | /workspace/95.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/95.xbar_random_large_delays.800159729 |
| Short name | T1461 |
| Test name | |
| Test status | |
| Simulation time | 51302162844 ps |
| CPU time | 519.82 seconds |
| Started | Jun 29 08:30:45 PM PDT 24 |
| Finished | Jun 29 08:39:26 PM PDT 24 |
| Peak memory | 575360 kb |
| Host | smart-ee6db4f8-ba0a-45a7-b229-bf32daf25d98 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=800159729 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 95.xbar_random_large_delays.800159729 |
| Directory | /workspace/95.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/95.xbar_random_slow_rsp.3104131621 |
| Short name | T1815 |
| Test name | |
| Test status | |
| Simulation time | 51695988406 ps |
| CPU time | 859.31 seconds |
| Started | Jun 29 08:30:46 PM PDT 24 |
| Finished | Jun 29 08:45:05 PM PDT 24 |
| Peak memory | 574328 kb |
| Host | smart-a4e2ffa4-98cd-4d17-9aea-a676e18f1c60 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3104131621 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 95.xbar_random_slow_rsp.3104131621 |
| Directory | /workspace/95.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/95.xbar_random_zero_delays.1588962807 |
| Short name | T2662 |
| Test name | |
| Test status | |
| Simulation time | 334547609 ps |
| CPU time | 33.35 seconds |
| Started | Jun 29 08:30:44 PM PDT 24 |
| Finished | Jun 29 08:31:18 PM PDT 24 |
| Peak memory | 575312 kb |
| Host | smart-eb9f1b95-b57f-4f9e-97c3-a6f4fccf4780 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1588962807 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 95.xbar_random_zero_del ays.1588962807 |
| Directory | /workspace/95.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/95.xbar_same_source.3533102244 |
| Short name | T2202 |
| Test name | |
| Test status | |
| Simulation time | 498626869 ps |
| CPU time | 38.2 seconds |
| Started | Jun 29 08:30:46 PM PDT 24 |
| Finished | Jun 29 08:31:25 PM PDT 24 |
| Peak memory | 574240 kb |
| Host | smart-86edce2b-f97f-41a0-87e0-602bf8a6c8a3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3533102244 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 95.xbar_same_source.3533102244 |
| Directory | /workspace/95.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/95.xbar_smoke.4147722070 |
| Short name | T2879 |
| Test name | |
| Test status | |
| Simulation time | 204932536 ps |
| CPU time | 10.05 seconds |
| Started | Jun 29 08:30:38 PM PDT 24 |
| Finished | Jun 29 08:30:49 PM PDT 24 |
| Peak memory | 574244 kb |
| Host | smart-fbafde36-7587-4c69-b83d-5016d005f22f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4147722070 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 95.xbar_smoke.4147722070 |
| Directory | /workspace/95.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/95.xbar_smoke_large_delays.2767389572 |
| Short name | T1347 |
| Test name | |
| Test status | |
| Simulation time | 6796083992 ps |
| CPU time | 72.71 seconds |
| Started | Jun 29 08:30:38 PM PDT 24 |
| Finished | Jun 29 08:31:51 PM PDT 24 |
| Peak memory | 566088 kb |
| Host | smart-893835d3-cfb4-43c5-a1e6-e3ea7156b1f2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2767389572 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 95.xbar_smoke_large_delays.2767389572 |
| Directory | /workspace/95.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/95.xbar_smoke_slow_rsp.3613978569 |
| Short name | T1674 |
| Test name | |
| Test status | |
| Simulation time | 5560711939 ps |
| CPU time | 100.29 seconds |
| Started | Jun 29 08:30:39 PM PDT 24 |
| Finished | Jun 29 08:32:20 PM PDT 24 |
| Peak memory | 574328 kb |
| Host | smart-f8bd8bdd-b600-4b37-9316-524869f726d5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3613978569 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 95.xbar_smoke_slow_rsp.3613978569 |
| Directory | /workspace/95.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/95.xbar_smoke_zero_delays.3430542328 |
| Short name | T2746 |
| Test name | |
| Test status | |
| Simulation time | 40844448 ps |
| CPU time | 5.7 seconds |
| Started | Jun 29 08:30:38 PM PDT 24 |
| Finished | Jun 29 08:30:44 PM PDT 24 |
| Peak memory | 574244 kb |
| Host | smart-1ed1e174-13d7-421c-b409-d9df953b8fbb |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3430542328 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 95.xbar_smoke_zero_delay s.3430542328 |
| Directory | /workspace/95.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/95.xbar_stress_all.2677516848 |
| Short name | T2751 |
| Test name | |
| Test status | |
| Simulation time | 8789449478 ps |
| CPU time | 352.08 seconds |
| Started | Jun 29 08:30:46 PM PDT 24 |
| Finished | Jun 29 08:36:38 PM PDT 24 |
| Peak memory | 574460 kb |
| Host | smart-cee76ac0-4dc4-4689-be68-01afb7275a9b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2677516848 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 95.xbar_stress_all.2677516848 |
| Directory | /workspace/95.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/95.xbar_stress_all_with_error.2322356752 |
| Short name | T1820 |
| Test name | |
| Test status | |
| Simulation time | 6873458408 ps |
| CPU time | 222.09 seconds |
| Started | Jun 29 08:30:46 PM PDT 24 |
| Finished | Jun 29 08:34:29 PM PDT 24 |
| Peak memory | 574648 kb |
| Host | smart-ed0bddc4-1c7d-4cf7-9a52-838cb8308a91 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2322356752 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 95.xbar_stress_all_with_error.2322356752 |
| Directory | /workspace/95.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/95.xbar_stress_all_with_rand_reset.2069772528 |
| Short name | T2411 |
| Test name | |
| Test status | |
| Simulation time | 514134847 ps |
| CPU time | 187.35 seconds |
| Started | Jun 29 08:30:43 PM PDT 24 |
| Finished | Jun 29 08:33:51 PM PDT 24 |
| Peak memory | 575444 kb |
| Host | smart-692d8b69-8feb-4be3-8508-5c84dbb621ac |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2069772528 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 95.xbar_stress_all _with_rand_reset.2069772528 |
| Directory | /workspace/95.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/95.xbar_stress_all_with_reset_error.1036420557 |
| Short name | T2158 |
| Test name | |
| Test status | |
| Simulation time | 7760985773 ps |
| CPU time | 471.07 seconds |
| Started | Jun 29 08:30:48 PM PDT 24 |
| Finished | Jun 29 08:38:40 PM PDT 24 |
| Peak memory | 575500 kb |
| Host | smart-171364a5-49a3-44eb-969a-d42c77a59498 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1036420557 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 95.xbar_stress_al l_with_reset_error.1036420557 |
| Directory | /workspace/95.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/95.xbar_unmapped_addr.1539541948 |
| Short name | T2402 |
| Test name | |
| Test status | |
| Simulation time | 111669504 ps |
| CPU time | 15.89 seconds |
| Started | Jun 29 08:30:47 PM PDT 24 |
| Finished | Jun 29 08:31:03 PM PDT 24 |
| Peak memory | 575348 kb |
| Host | smart-e547e516-e589-4fd4-ab81-f0b571ee52e1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1539541948 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 95.xbar_unmapped_addr.1539541948 |
| Directory | /workspace/95.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/96.xbar_access_same_device.620913349 |
| Short name | T1467 |
| Test name | |
| Test status | |
| Simulation time | 1381699434 ps |
| CPU time | 62.37 seconds |
| Started | Jun 29 08:30:54 PM PDT 24 |
| Finished | Jun 29 08:31:57 PM PDT 24 |
| Peak memory | 575304 kb |
| Host | smart-eb5f9e56-8a81-46a2-a1ae-659623164da0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=620913349 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 96.xbar_access_same_device. 620913349 |
| Directory | /workspace/96.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/96.xbar_access_same_device_slow_rsp.1014634215 |
| Short name | T1595 |
| Test name | |
| Test status | |
| Simulation time | 46265702940 ps |
| CPU time | 790.66 seconds |
| Started | Jun 29 08:30:54 PM PDT 24 |
| Finished | Jun 29 08:44:05 PM PDT 24 |
| Peak memory | 575452 kb |
| Host | smart-d72fbc25-76a7-4c58-93cf-1267dba2e951 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1014634215 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 96.xbar_access_same_ device_slow_rsp.1014634215 |
| Directory | /workspace/96.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/96.xbar_error_and_unmapped_addr.1097328821 |
| Short name | T1898 |
| Test name | |
| Test status | |
| Simulation time | 119794265 ps |
| CPU time | 16.36 seconds |
| Started | Jun 29 08:30:55 PM PDT 24 |
| Finished | Jun 29 08:31:12 PM PDT 24 |
| Peak memory | 573868 kb |
| Host | smart-0776c7d9-7d62-4a6b-b435-8a98eccbe4ad |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1097328821 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 96.xbar_error_and_unmapped_add r.1097328821 |
| Directory | /workspace/96.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/96.xbar_error_random.1718297070 |
| Short name | T2883 |
| Test name | |
| Test status | |
| Simulation time | 1340358795 ps |
| CPU time | 51.94 seconds |
| Started | Jun 29 08:30:55 PM PDT 24 |
| Finished | Jun 29 08:31:47 PM PDT 24 |
| Peak memory | 574452 kb |
| Host | smart-3475cdd4-33ff-456b-9100-b665cb7fc66e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1718297070 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 96.xbar_error_random.1718297070 |
| Directory | /workspace/96.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/96.xbar_random.2010042033 |
| Short name | T2643 |
| Test name | |
| Test status | |
| Simulation time | 2045392917 ps |
| CPU time | 81.12 seconds |
| Started | Jun 29 08:30:54 PM PDT 24 |
| Finished | Jun 29 08:32:15 PM PDT 24 |
| Peak memory | 575308 kb |
| Host | smart-5982acd6-aa2a-4f6e-9f86-34c08d13ec2c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2010042033 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 96.xbar_random.2010042033 |
| Directory | /workspace/96.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/96.xbar_random_large_delays.2437829597 |
| Short name | T2375 |
| Test name | |
| Test status | |
| Simulation time | 21649294371 ps |
| CPU time | 230.28 seconds |
| Started | Jun 29 08:30:51 PM PDT 24 |
| Finished | Jun 29 08:34:41 PM PDT 24 |
| Peak memory | 575396 kb |
| Host | smart-67ae9bab-f441-4fa8-a67d-5f50b7df7a77 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2437829597 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 96.xbar_random_large_delays.2437829597 |
| Directory | /workspace/96.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/96.xbar_random_slow_rsp.1379889402 |
| Short name | T1922 |
| Test name | |
| Test status | |
| Simulation time | 32733718320 ps |
| CPU time | 552.95 seconds |
| Started | Jun 29 08:30:56 PM PDT 24 |
| Finished | Jun 29 08:40:10 PM PDT 24 |
| Peak memory | 575412 kb |
| Host | smart-0f4a70f8-f09f-4b7d-9d3b-e949896896a5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1379889402 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 96.xbar_random_slow_rsp.1379889402 |
| Directory | /workspace/96.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/96.xbar_random_zero_delays.3021600473 |
| Short name | T2435 |
| Test name | |
| Test status | |
| Simulation time | 65574202 ps |
| CPU time | 9.11 seconds |
| Started | Jun 29 08:30:52 PM PDT 24 |
| Finished | Jun 29 08:31:02 PM PDT 24 |
| Peak memory | 574244 kb |
| Host | smart-1377f260-6ab4-4dd3-861c-6079c8911e8b |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3021600473 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 96.xbar_random_zero_del ays.3021600473 |
| Directory | /workspace/96.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/96.xbar_same_source.961390635 |
| Short name | T2163 |
| Test name | |
| Test status | |
| Simulation time | 251311040 ps |
| CPU time | 20.82 seconds |
| Started | Jun 29 08:30:52 PM PDT 24 |
| Finished | Jun 29 08:31:14 PM PDT 24 |
| Peak memory | 575300 kb |
| Host | smart-f43e3375-2f54-4d59-a197-583acfa289f1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=961390635 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 96.xbar_same_source.961390635 |
| Directory | /workspace/96.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/96.xbar_smoke.483091081 |
| Short name | T2603 |
| Test name | |
| Test status | |
| Simulation time | 230697119 ps |
| CPU time | 10.57 seconds |
| Started | Jun 29 08:30:54 PM PDT 24 |
| Finished | Jun 29 08:31:05 PM PDT 24 |
| Peak memory | 574096 kb |
| Host | smart-8ad4b2f4-eada-4985-9800-7666b82407c3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=483091081 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 96.xbar_smoke.483091081 |
| Directory | /workspace/96.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/96.xbar_smoke_large_delays.1993481794 |
| Short name | T2436 |
| Test name | |
| Test status | |
| Simulation time | 9473545638 ps |
| CPU time | 99.89 seconds |
| Started | Jun 29 08:30:55 PM PDT 24 |
| Finished | Jun 29 08:32:35 PM PDT 24 |
| Peak memory | 574336 kb |
| Host | smart-cf9454e4-5997-43ac-aec0-0889d42abf24 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1993481794 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 96.xbar_smoke_large_delays.1993481794 |
| Directory | /workspace/96.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/96.xbar_smoke_slow_rsp.1619902429 |
| Short name | T598 |
| Test name | |
| Test status | |
| Simulation time | 5095279790 ps |
| CPU time | 83.72 seconds |
| Started | Jun 29 08:30:53 PM PDT 24 |
| Finished | Jun 29 08:32:17 PM PDT 24 |
| Peak memory | 574204 kb |
| Host | smart-707b4ce0-5472-43ee-b6c8-de939ba032b4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1619902429 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 96.xbar_smoke_slow_rsp.1619902429 |
| Directory | /workspace/96.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/96.xbar_smoke_zero_delays.3118880671 |
| Short name | T2533 |
| Test name | |
| Test status | |
| Simulation time | 52231250 ps |
| CPU time | 7.35 seconds |
| Started | Jun 29 08:30:52 PM PDT 24 |
| Finished | Jun 29 08:31:01 PM PDT 24 |
| Peak memory | 574256 kb |
| Host | smart-9e6bff44-2cd9-4282-9576-a4b812091e82 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3118880671 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 96.xbar_smoke_zero_delay s.3118880671 |
| Directory | /workspace/96.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/96.xbar_stress_all.1779136214 |
| Short name | T461 |
| Test name | |
| Test status | |
| Simulation time | 14203188021 ps |
| CPU time | 526.7 seconds |
| Started | Jun 29 08:30:52 PM PDT 24 |
| Finished | Jun 29 08:39:40 PM PDT 24 |
| Peak memory | 575476 kb |
| Host | smart-108b644c-ed25-4336-9d4d-56c0b07c4be9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1779136214 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 96.xbar_stress_all.1779136214 |
| Directory | /workspace/96.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/96.xbar_stress_all_with_error.189513316 |
| Short name | T2118 |
| Test name | |
| Test status | |
| Simulation time | 6591551678 ps |
| CPU time | 265.82 seconds |
| Started | Jun 29 08:30:53 PM PDT 24 |
| Finished | Jun 29 08:35:20 PM PDT 24 |
| Peak memory | 574376 kb |
| Host | smart-8da1e8de-aa9c-4fc8-a52e-6b3e5668ec7a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=189513316 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 96.xbar_stress_all_with_error.189513316 |
| Directory | /workspace/96.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/96.xbar_stress_all_with_rand_reset.1888617723 |
| Short name | T803 |
| Test name | |
| Test status | |
| Simulation time | 3304600125 ps |
| CPU time | 294.01 seconds |
| Started | Jun 29 08:30:56 PM PDT 24 |
| Finished | Jun 29 08:35:51 PM PDT 24 |
| Peak memory | 575512 kb |
| Host | smart-65345016-676c-42e1-b6b4-82ae7b869ad5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1888617723 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 96.xbar_stress_all _with_rand_reset.1888617723 |
| Directory | /workspace/96.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/96.xbar_stress_all_with_reset_error.3462759769 |
| Short name | T2786 |
| Test name | |
| Test status | |
| Simulation time | 17331837687 ps |
| CPU time | 801.63 seconds |
| Started | Jun 29 08:30:53 PM PDT 24 |
| Finished | Jun 29 08:44:16 PM PDT 24 |
| Peak memory | 575524 kb |
| Host | smart-261fed22-e900-4d2c-8215-87b4d1ead223 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3462759769 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 96.xbar_stress_al l_with_reset_error.3462759769 |
| Directory | /workspace/96.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/96.xbar_unmapped_addr.2417764674 |
| Short name | T1510 |
| Test name | |
| Test status | |
| Simulation time | 803889966 ps |
| CPU time | 40.26 seconds |
| Started | Jun 29 08:30:52 PM PDT 24 |
| Finished | Jun 29 08:31:33 PM PDT 24 |
| Peak memory | 575360 kb |
| Host | smart-3f02d54b-72f2-41a8-b5fc-9ed0a7fddf65 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2417764674 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 96.xbar_unmapped_addr.2417764674 |
| Directory | /workspace/96.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/97.xbar_access_same_device.3072763101 |
| Short name | T2400 |
| Test name | |
| Test status | |
| Simulation time | 656574810 ps |
| CPU time | 32.26 seconds |
| Started | Jun 29 08:31:10 PM PDT 24 |
| Finished | Jun 29 08:31:42 PM PDT 24 |
| Peak memory | 575300 kb |
| Host | smart-d88537c5-cf8a-4081-aaf6-c8d277239d40 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3072763101 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 97.xbar_access_same_device .3072763101 |
| Directory | /workspace/97.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/97.xbar_access_same_device_slow_rsp.1436866486 |
| Short name | T2385 |
| Test name | |
| Test status | |
| Simulation time | 2853827652 ps |
| CPU time | 53.73 seconds |
| Started | Jun 29 08:31:02 PM PDT 24 |
| Finished | Jun 29 08:31:56 PM PDT 24 |
| Peak memory | 574240 kb |
| Host | smart-55d36fa7-293b-47f6-bd1d-ede9f1ce97a6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1436866486 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 97.xbar_access_same_ device_slow_rsp.1436866486 |
| Directory | /workspace/97.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/97.xbar_error_and_unmapped_addr.679433439 |
| Short name | T2768 |
| Test name | |
| Test status | |
| Simulation time | 1159167205 ps |
| CPU time | 47.49 seconds |
| Started | Jun 29 08:31:09 PM PDT 24 |
| Finished | Jun 29 08:31:57 PM PDT 24 |
| Peak memory | 574512 kb |
| Host | smart-ec63aacc-6c0d-482a-877c-b36b22892a3b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=679433439 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 97.xbar_error_and_unmapped_addr .679433439 |
| Directory | /workspace/97.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/97.xbar_error_random.4212395044 |
| Short name | T2023 |
| Test name | |
| Test status | |
| Simulation time | 357573555 ps |
| CPU time | 36.51 seconds |
| Started | Jun 29 08:31:02 PM PDT 24 |
| Finished | Jun 29 08:31:38 PM PDT 24 |
| Peak memory | 574496 kb |
| Host | smart-eed79051-ac0f-4eef-a44b-c07ec22e1f70 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4212395044 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 97.xbar_error_random.4212395044 |
| Directory | /workspace/97.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/97.xbar_random.2965089547 |
| Short name | T1471 |
| Test name | |
| Test status | |
| Simulation time | 366870799 ps |
| CPU time | 37.7 seconds |
| Started | Jun 29 08:31:01 PM PDT 24 |
| Finished | Jun 29 08:31:39 PM PDT 24 |
| Peak memory | 574236 kb |
| Host | smart-4a5dd221-af7d-4ef3-8476-0a0722529a54 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2965089547 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 97.xbar_random.2965089547 |
| Directory | /workspace/97.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/97.xbar_random_large_delays.1225853469 |
| Short name | T1412 |
| Test name | |
| Test status | |
| Simulation time | 14528791783 ps |
| CPU time | 164.83 seconds |
| Started | Jun 29 08:31:04 PM PDT 24 |
| Finished | Jun 29 08:33:49 PM PDT 24 |
| Peak memory | 574316 kb |
| Host | smart-9cf7cd53-5d65-4388-b48e-d23bd0d9702c |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1225853469 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 97.xbar_random_large_delays.1225853469 |
| Directory | /workspace/97.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/97.xbar_random_slow_rsp.3311546257 |
| Short name | T2262 |
| Test name | |
| Test status | |
| Simulation time | 21571055793 ps |
| CPU time | 358.99 seconds |
| Started | Jun 29 08:31:02 PM PDT 24 |
| Finished | Jun 29 08:37:01 PM PDT 24 |
| Peak memory | 575400 kb |
| Host | smart-f6c55218-fb10-4726-981e-462247667204 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3311546257 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 97.xbar_random_slow_rsp.3311546257 |
| Directory | /workspace/97.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/97.xbar_random_zero_delays.73984115 |
| Short name | T2489 |
| Test name | |
| Test status | |
| Simulation time | 398598038 ps |
| CPU time | 43.9 seconds |
| Started | Jun 29 08:31:03 PM PDT 24 |
| Finished | Jun 29 08:31:47 PM PDT 24 |
| Peak memory | 575364 kb |
| Host | smart-096d2672-8315-4354-acdc-10a410b12fd4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73984115 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 97.xbar_random_zero_delay s.73984115 |
| Directory | /workspace/97.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/97.xbar_same_source.3262896300 |
| Short name | T2502 |
| Test name | |
| Test status | |
| Simulation time | 371687726 ps |
| CPU time | 28.87 seconds |
| Started | Jun 29 08:31:05 PM PDT 24 |
| Finished | Jun 29 08:31:34 PM PDT 24 |
| Peak memory | 574240 kb |
| Host | smart-208db777-74f5-4c8f-b377-e12f0dfb2f95 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3262896300 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 97.xbar_same_source.3262896300 |
| Directory | /workspace/97.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/97.xbar_smoke.2858120039 |
| Short name | T1754 |
| Test name | |
| Test status | |
| Simulation time | 229053515 ps |
| CPU time | 10.46 seconds |
| Started | Jun 29 08:30:53 PM PDT 24 |
| Finished | Jun 29 08:31:04 PM PDT 24 |
| Peak memory | 574252 kb |
| Host | smart-118734ee-8649-4762-ad0a-1a4cfee5bbab |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2858120039 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 97.xbar_smoke.2858120039 |
| Directory | /workspace/97.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/97.xbar_smoke_large_delays.3306953421 |
| Short name | T611 |
| Test name | |
| Test status | |
| Simulation time | 10034999933 ps |
| CPU time | 106.38 seconds |
| Started | Jun 29 08:31:07 PM PDT 24 |
| Finished | Jun 29 08:32:53 PM PDT 24 |
| Peak memory | 574232 kb |
| Host | smart-1c4f4452-5966-42d9-aa02-982672507859 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3306953421 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 97.xbar_smoke_large_delays.3306953421 |
| Directory | /workspace/97.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/97.xbar_smoke_slow_rsp.3178580670 |
| Short name | T1734 |
| Test name | |
| Test status | |
| Simulation time | 4669764413 ps |
| CPU time | 82.07 seconds |
| Started | Jun 29 08:31:03 PM PDT 24 |
| Finished | Jun 29 08:32:25 PM PDT 24 |
| Peak memory | 574332 kb |
| Host | smart-23917a28-eded-4253-8a41-2ac59d3b6e4a |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3178580670 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 97.xbar_smoke_slow_rsp.3178580670 |
| Directory | /workspace/97.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/97.xbar_smoke_zero_delays.2979815588 |
| Short name | T1577 |
| Test name | |
| Test status | |
| Simulation time | 51423603 ps |
| CPU time | 7 seconds |
| Started | Jun 29 08:30:52 PM PDT 24 |
| Finished | Jun 29 08:30:59 PM PDT 24 |
| Peak memory | 574272 kb |
| Host | smart-b17080ef-b9fc-42b7-b3f5-a826cdc8c379 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2979815588 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 97.xbar_smoke_zero_delay s.2979815588 |
| Directory | /workspace/97.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/97.xbar_stress_all.1883460945 |
| Short name | T1517 |
| Test name | |
| Test status | |
| Simulation time | 1608184251 ps |
| CPU time | 102.59 seconds |
| Started | Jun 29 08:31:07 PM PDT 24 |
| Finished | Jun 29 08:32:49 PM PDT 24 |
| Peak memory | 575376 kb |
| Host | smart-0de6f353-cc20-4cab-b8c5-eae4a9032cc4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1883460945 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 97.xbar_stress_all.1883460945 |
| Directory | /workspace/97.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/97.xbar_stress_all_with_rand_reset.1505707171 |
| Short name | T2042 |
| Test name | |
| Test status | |
| Simulation time | 5951446877 ps |
| CPU time | 669.37 seconds |
| Started | Jun 29 08:31:12 PM PDT 24 |
| Finished | Jun 29 08:42:22 PM PDT 24 |
| Peak memory | 575520 kb |
| Host | smart-179f673a-b337-4571-aca6-584828066d7d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1505707171 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 97.xbar_stress_all _with_rand_reset.1505707171 |
| Directory | /workspace/97.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/97.xbar_stress_all_with_reset_error.2982819885 |
| Short name | T2729 |
| Test name | |
| Test status | |
| Simulation time | 313756176 ps |
| CPU time | 111.21 seconds |
| Started | Jun 29 08:31:10 PM PDT 24 |
| Finished | Jun 29 08:33:01 PM PDT 24 |
| Peak memory | 576452 kb |
| Host | smart-daf827c2-130a-452d-9fe3-9eebbf0e4352 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2982819885 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 97.xbar_stress_al l_with_reset_error.2982819885 |
| Directory | /workspace/97.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/97.xbar_unmapped_addr.1808679482 |
| Short name | T2270 |
| Test name | |
| Test status | |
| Simulation time | 122161516 ps |
| CPU time | 14.1 seconds |
| Started | Jun 29 08:31:05 PM PDT 24 |
| Finished | Jun 29 08:31:19 PM PDT 24 |
| Peak memory | 574268 kb |
| Host | smart-bbd5f252-bb3d-4ecf-b113-4d5f38837ce7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1808679482 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 97.xbar_unmapped_addr.1808679482 |
| Directory | /workspace/97.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/98.xbar_access_same_device_slow_rsp.1533165564 |
| Short name | T2827 |
| Test name | |
| Test status | |
| Simulation time | 42086201012 ps |
| CPU time | 729.8 seconds |
| Started | Jun 29 08:31:14 PM PDT 24 |
| Finished | Jun 29 08:43:25 PM PDT 24 |
| Peak memory | 575460 kb |
| Host | smart-cbd1a549-8c99-4556-beec-9ccd7d2aab81 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1533165564 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 98.xbar_access_same_ device_slow_rsp.1533165564 |
| Directory | /workspace/98.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/98.xbar_error_and_unmapped_addr.882838259 |
| Short name | T2417 |
| Test name | |
| Test status | |
| Simulation time | 260660678 ps |
| CPU time | 13.88 seconds |
| Started | Jun 29 08:31:10 PM PDT 24 |
| Finished | Jun 29 08:31:24 PM PDT 24 |
| Peak memory | 574508 kb |
| Host | smart-ee7b9378-f8db-4254-a9f8-a65c620b9531 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=882838259 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 98.xbar_error_and_unmapped_addr .882838259 |
| Directory | /workspace/98.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/98.xbar_error_random.4102111190 |
| Short name | T2478 |
| Test name | |
| Test status | |
| Simulation time | 569071228 ps |
| CPU time | 22.71 seconds |
| Started | Jun 29 08:31:11 PM PDT 24 |
| Finished | Jun 29 08:31:34 PM PDT 24 |
| Peak memory | 574472 kb |
| Host | smart-6bb06771-ec93-44bf-8750-92859ec4b271 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4102111190 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 98.xbar_error_random.4102111190 |
| Directory | /workspace/98.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/98.xbar_random.2338002915 |
| Short name | T551 |
| Test name | |
| Test status | |
| Simulation time | 603364102 ps |
| CPU time | 49.7 seconds |
| Started | Jun 29 08:31:10 PM PDT 24 |
| Finished | Jun 29 08:32:00 PM PDT 24 |
| Peak memory | 574248 kb |
| Host | smart-b0deb1d0-b5ce-4be7-9877-cf38c420e191 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2338002915 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 98.xbar_random.2338002915 |
| Directory | /workspace/98.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/98.xbar_random_large_delays.2063906845 |
| Short name | T2755 |
| Test name | |
| Test status | |
| Simulation time | 105763533239 ps |
| CPU time | 1189.93 seconds |
| Started | Jun 29 08:31:14 PM PDT 24 |
| Finished | Jun 29 08:51:05 PM PDT 24 |
| Peak memory | 575444 kb |
| Host | smart-27129096-d1e9-4c19-8172-673eb030f690 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2063906845 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 98.xbar_random_large_delays.2063906845 |
| Directory | /workspace/98.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/98.xbar_random_slow_rsp.4092210481 |
| Short name | T2721 |
| Test name | |
| Test status | |
| Simulation time | 39328689865 ps |
| CPU time | 682.45 seconds |
| Started | Jun 29 08:31:09 PM PDT 24 |
| Finished | Jun 29 08:42:32 PM PDT 24 |
| Peak memory | 574312 kb |
| Host | smart-18fb6286-2204-45e2-9411-fcc779970d0a |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4092210481 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 98.xbar_random_slow_rsp.4092210481 |
| Directory | /workspace/98.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/98.xbar_random_zero_delays.1705988830 |
| Short name | T1846 |
| Test name | |
| Test status | |
| Simulation time | 404075061 ps |
| CPU time | 36.85 seconds |
| Started | Jun 29 08:31:09 PM PDT 24 |
| Finished | Jun 29 08:31:46 PM PDT 24 |
| Peak memory | 574244 kb |
| Host | smart-fe1d083d-25e9-457d-9bee-97750915f8ac |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1705988830 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 98.xbar_random_zero_del ays.1705988830 |
| Directory | /workspace/98.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/98.xbar_same_source.6518621 |
| Short name | T2787 |
| Test name | |
| Test status | |
| Simulation time | 2515204781 ps |
| CPU time | 76.86 seconds |
| Started | Jun 29 08:31:10 PM PDT 24 |
| Finished | Jun 29 08:32:27 PM PDT 24 |
| Peak memory | 575348 kb |
| Host | smart-7d76bcbd-d41c-42c7-ae69-968f129720a0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=6518621 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 98.xbar_same_source.6518621 |
| Directory | /workspace/98.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/98.xbar_smoke.3363720529 |
| Short name | T1713 |
| Test name | |
| Test status | |
| Simulation time | 173508129 ps |
| CPU time | 7.8 seconds |
| Started | Jun 29 08:31:14 PM PDT 24 |
| Finished | Jun 29 08:31:22 PM PDT 24 |
| Peak memory | 574264 kb |
| Host | smart-297ff77b-41d0-41dc-9e61-16b380d93c14 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3363720529 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 98.xbar_smoke.3363720529 |
| Directory | /workspace/98.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/98.xbar_smoke_large_delays.1446729095 |
| Short name | T2423 |
| Test name | |
| Test status | |
| Simulation time | 10078773502 ps |
| CPU time | 107.07 seconds |
| Started | Jun 29 08:31:18 PM PDT 24 |
| Finished | Jun 29 08:33:05 PM PDT 24 |
| Peak memory | 574324 kb |
| Host | smart-bb00b39b-7c96-4f1c-a388-998068e8e0c4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1446729095 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 98.xbar_smoke_large_delays.1446729095 |
| Directory | /workspace/98.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/98.xbar_smoke_slow_rsp.947300660 |
| Short name | T1975 |
| Test name | |
| Test status | |
| Simulation time | 5340991384 ps |
| CPU time | 90.51 seconds |
| Started | Jun 29 08:31:17 PM PDT 24 |
| Finished | Jun 29 08:32:48 PM PDT 24 |
| Peak memory | 574196 kb |
| Host | smart-22ceb22d-f139-4a5f-ad6c-1029623bdbbe |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=947300660 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 98.xbar_smoke_slow_rsp.947300660 |
| Directory | /workspace/98.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/98.xbar_smoke_zero_delays.1345729440 |
| Short name | T1403 |
| Test name | |
| Test status | |
| Simulation time | 50636417 ps |
| CPU time | 6.62 seconds |
| Started | Jun 29 08:31:08 PM PDT 24 |
| Finished | Jun 29 08:31:15 PM PDT 24 |
| Peak memory | 574260 kb |
| Host | smart-bc57713d-0e51-4777-9ac2-7bb95df938c8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1345729440 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 98.xbar_smoke_zero_delay s.1345729440 |
| Directory | /workspace/98.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/98.xbar_stress_all.2755929612 |
| Short name | T1681 |
| Test name | |
| Test status | |
| Simulation time | 3158259039 ps |
| CPU time | 136.48 seconds |
| Started | Jun 29 08:31:10 PM PDT 24 |
| Finished | Jun 29 08:33:27 PM PDT 24 |
| Peak memory | 575500 kb |
| Host | smart-b1b36833-37a2-428f-93ee-1e6557aa177b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2755929612 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 98.xbar_stress_all.2755929612 |
| Directory | /workspace/98.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/98.xbar_stress_all_with_error.1347491750 |
| Short name | T1569 |
| Test name | |
| Test status | |
| Simulation time | 11578065573 ps |
| CPU time | 377.32 seconds |
| Started | Jun 29 08:31:18 PM PDT 24 |
| Finished | Jun 29 08:37:36 PM PDT 24 |
| Peak memory | 574740 kb |
| Host | smart-794deea7-8e48-45ff-be15-5466ea002d22 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1347491750 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 98.xbar_stress_all_with_error.1347491750 |
| Directory | /workspace/98.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/98.xbar_stress_all_with_rand_reset.2880866305 |
| Short name | T1804 |
| Test name | |
| Test status | |
| Simulation time | 143769018 ps |
| CPU time | 56.83 seconds |
| Started | Jun 29 08:31:19 PM PDT 24 |
| Finished | Jun 29 08:32:16 PM PDT 24 |
| Peak memory | 574408 kb |
| Host | smart-8b9c2f9d-2b28-4e2a-9b9f-5e3448f86039 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2880866305 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 98.xbar_stress_all _with_rand_reset.2880866305 |
| Directory | /workspace/98.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/98.xbar_stress_all_with_reset_error.3948198168 |
| Short name | T2419 |
| Test name | |
| Test status | |
| Simulation time | 7834553245 ps |
| CPU time | 408.96 seconds |
| Started | Jun 29 08:31:17 PM PDT 24 |
| Finished | Jun 29 08:38:06 PM PDT 24 |
| Peak memory | 574428 kb |
| Host | smart-c93f9dfa-3cc7-4170-bab5-5317362d0ff0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3948198168 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 98.xbar_stress_al l_with_reset_error.3948198168 |
| Directory | /workspace/98.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/98.xbar_unmapped_addr.3507575841 |
| Short name | T1352 |
| Test name | |
| Test status | |
| Simulation time | 37070183 ps |
| CPU time | 7.22 seconds |
| Started | Jun 29 08:31:09 PM PDT 24 |
| Finished | Jun 29 08:31:16 PM PDT 24 |
| Peak memory | 574224 kb |
| Host | smart-13e191d2-7eb9-40eb-86c2-7f05855d1f43 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3507575841 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 98.xbar_unmapped_addr.3507575841 |
| Directory | /workspace/98.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/99.xbar_access_same_device.903649907 |
| Short name | T2241 |
| Test name | |
| Test status | |
| Simulation time | 2472286783 ps |
| CPU time | 112.1 seconds |
| Started | Jun 29 08:31:18 PM PDT 24 |
| Finished | Jun 29 08:33:11 PM PDT 24 |
| Peak memory | 575348 kb |
| Host | smart-2e527193-fe04-4ced-bcf9-a21508f1896b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=903649907 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 99.xbar_access_same_device. 903649907 |
| Directory | /workspace/99.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/99.xbar_access_same_device_slow_rsp.3497072523 |
| Short name | T2156 |
| Test name | |
| Test status | |
| Simulation time | 89695437626 ps |
| CPU time | 1570.55 seconds |
| Started | Jun 29 08:31:19 PM PDT 24 |
| Finished | Jun 29 08:57:30 PM PDT 24 |
| Peak memory | 575508 kb |
| Host | smart-04b319de-6733-4702-8896-648c3250aa08 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3497072523 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 99.xbar_access_same_ device_slow_rsp.3497072523 |
| Directory | /workspace/99.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/99.xbar_error_and_unmapped_addr.2265973404 |
| Short name | T2602 |
| Test name | |
| Test status | |
| Simulation time | 691120131 ps |
| CPU time | 27.35 seconds |
| Started | Jun 29 08:31:25 PM PDT 24 |
| Finished | Jun 29 08:31:53 PM PDT 24 |
| Peak memory | 574444 kb |
| Host | smart-be523440-40c8-4701-b2d0-2df245932ec1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2265973404 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 99.xbar_error_and_unmapped_add r.2265973404 |
| Directory | /workspace/99.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/99.xbar_error_random.4080134175 |
| Short name | T2056 |
| Test name | |
| Test status | |
| Simulation time | 2078096672 ps |
| CPU time | 82.87 seconds |
| Started | Jun 29 08:31:18 PM PDT 24 |
| Finished | Jun 29 08:32:42 PM PDT 24 |
| Peak memory | 574476 kb |
| Host | smart-35367374-62a6-4af9-b8ef-66fa75e2b09d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4080134175 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 99.xbar_error_random.4080134175 |
| Directory | /workspace/99.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/99.xbar_random.3353082735 |
| Short name | T1542 |
| Test name | |
| Test status | |
| Simulation time | 185875172 ps |
| CPU time | 21.56 seconds |
| Started | Jun 29 08:31:18 PM PDT 24 |
| Finished | Jun 29 08:31:40 PM PDT 24 |
| Peak memory | 574236 kb |
| Host | smart-11e9d56e-006e-4b1f-b568-64ec99f92248 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3353082735 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 99.xbar_random.3353082735 |
| Directory | /workspace/99.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/99.xbar_random_large_delays.3394954870 |
| Short name | T429 |
| Test name | |
| Test status | |
| Simulation time | 56101798367 ps |
| CPU time | 571.19 seconds |
| Started | Jun 29 08:31:18 PM PDT 24 |
| Finished | Jun 29 08:40:49 PM PDT 24 |
| Peak memory | 575404 kb |
| Host | smart-993b4209-19ca-49b7-8d78-b2e451b6274c |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3394954870 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 99.xbar_random_large_delays.3394954870 |
| Directory | /workspace/99.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/99.xbar_random_slow_rsp.3899507028 |
| Short name | T1718 |
| Test name | |
| Test status | |
| Simulation time | 27572191246 ps |
| CPU time | 504.3 seconds |
| Started | Jun 29 08:31:18 PM PDT 24 |
| Finished | Jun 29 08:39:43 PM PDT 24 |
| Peak memory | 575384 kb |
| Host | smart-ede2e6ca-1b85-4375-adcc-7c31dca703d0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3899507028 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 99.xbar_random_slow_rsp.3899507028 |
| Directory | /workspace/99.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/99.xbar_random_zero_delays.1943806665 |
| Short name | T1505 |
| Test name | |
| Test status | |
| Simulation time | 175538328 ps |
| CPU time | 17.31 seconds |
| Started | Jun 29 08:31:18 PM PDT 24 |
| Finished | Jun 29 08:31:36 PM PDT 24 |
| Peak memory | 575292 kb |
| Host | smart-e7347410-7ed1-4d4d-af54-d74a386184de |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1943806665 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 99.xbar_random_zero_del ays.1943806665 |
| Directory | /workspace/99.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/99.xbar_same_source.3095720929 |
| Short name | T491 |
| Test name | |
| Test status | |
| Simulation time | 1222692856 ps |
| CPU time | 37.93 seconds |
| Started | Jun 29 08:31:21 PM PDT 24 |
| Finished | Jun 29 08:31:59 PM PDT 24 |
| Peak memory | 575292 kb |
| Host | smart-364bda32-9f40-4c52-a3ee-d6fbc304af95 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3095720929 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 99.xbar_same_source.3095720929 |
| Directory | /workspace/99.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/99.xbar_smoke.1248409716 |
| Short name | T1861 |
| Test name | |
| Test status | |
| Simulation time | 189587620 ps |
| CPU time | 8.88 seconds |
| Started | Jun 29 08:31:20 PM PDT 24 |
| Finished | Jun 29 08:31:29 PM PDT 24 |
| Peak memory | 574256 kb |
| Host | smart-40e594d2-1a8b-4ac4-9fed-dcb2cae7b137 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1248409716 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 99.xbar_smoke.1248409716 |
| Directory | /workspace/99.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/99.xbar_smoke_large_delays.1230264977 |
| Short name | T1556 |
| Test name | |
| Test status | |
| Simulation time | 8658220279 ps |
| CPU time | 92.86 seconds |
| Started | Jun 29 08:31:17 PM PDT 24 |
| Finished | Jun 29 08:32:50 PM PDT 24 |
| Peak memory | 574320 kb |
| Host | smart-399022aa-a03a-4997-83d2-256fc37265f8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1230264977 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 99.xbar_smoke_large_delays.1230264977 |
| Directory | /workspace/99.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/99.xbar_smoke_slow_rsp.492653537 |
| Short name | T2306 |
| Test name | |
| Test status | |
| Simulation time | 4595197425 ps |
| CPU time | 79.62 seconds |
| Started | Jun 29 08:31:18 PM PDT 24 |
| Finished | Jun 29 08:32:38 PM PDT 24 |
| Peak memory | 574316 kb |
| Host | smart-5e508e6c-305e-4ee5-ac19-15f8ebc81c49 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=492653537 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 99.xbar_smoke_slow_rsp.492653537 |
| Directory | /workspace/99.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/99.xbar_smoke_zero_delays.300017117 |
| Short name | T2260 |
| Test name | |
| Test status | |
| Simulation time | 49780333 ps |
| CPU time | 6.79 seconds |
| Started | Jun 29 08:31:18 PM PDT 24 |
| Finished | Jun 29 08:31:26 PM PDT 24 |
| Peak memory | 574244 kb |
| Host | smart-3ccc7a37-76a0-4595-8621-2d88b3919f01 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=300017117 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 99.xbar_smoke_zero_delays .300017117 |
| Directory | /workspace/99.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/99.xbar_stress_all.2809729836 |
| Short name | T2463 |
| Test name | |
| Test status | |
| Simulation time | 9688722324 ps |
| CPU time | 351.33 seconds |
| Started | Jun 29 08:31:25 PM PDT 24 |
| Finished | Jun 29 08:37:17 PM PDT 24 |
| Peak memory | 574468 kb |
| Host | smart-223e633f-7861-41f0-a17c-9ddd63d08dfc |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2809729836 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 99.xbar_stress_all.2809729836 |
| Directory | /workspace/99.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/99.xbar_stress_all_with_error.1289614211 |
| Short name | T2148 |
| Test name | |
| Test status | |
| Simulation time | 3952641723 ps |
| CPU time | 155.4 seconds |
| Started | Jun 29 08:31:28 PM PDT 24 |
| Finished | Jun 29 08:34:03 PM PDT 24 |
| Peak memory | 574388 kb |
| Host | smart-9da97ebf-f36e-4e44-99fb-707c1f54d3ea |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1289614211 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 99.xbar_stress_all_with_error.1289614211 |
| Directory | /workspace/99.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/99.xbar_stress_all_with_rand_reset.1586170268 |
| Short name | T2176 |
| Test name | |
| Test status | |
| Simulation time | 1221217043 ps |
| CPU time | 141.93 seconds |
| Started | Jun 29 08:31:32 PM PDT 24 |
| Finished | Jun 29 08:33:54 PM PDT 24 |
| Peak memory | 576444 kb |
| Host | smart-869256fb-a974-4976-ad11-af30ab3baa74 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1586170268 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 99.xbar_stress_all _with_rand_reset.1586170268 |
| Directory | /workspace/99.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/99.xbar_stress_all_with_reset_error.674258811 |
| Short name | T2637 |
| Test name | |
| Test status | |
| Simulation time | 8989662856 ps |
| CPU time | 457.02 seconds |
| Started | Jun 29 08:31:25 PM PDT 24 |
| Finished | Jun 29 08:39:03 PM PDT 24 |
| Peak memory | 574504 kb |
| Host | smart-632d3f9b-89c8-4256-a773-1090d10f48d7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=674258811 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 99.xbar_stress_all _with_reset_error.674258811 |
| Directory | /workspace/99.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/99.xbar_unmapped_addr.2550442792 |
| Short name | T1421 |
| Test name | |
| Test status | |
| Simulation time | 1084786105 ps |
| CPU time | 50.53 seconds |
| Started | Jun 29 08:31:28 PM PDT 24 |
| Finished | Jun 29 08:32:19 PM PDT 24 |
| Peak memory | 574264 kb |
| Host | smart-55119f5e-8d4f-46c0-b630-e77892ca8645 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2550442792 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 99.xbar_unmapped_addr.2550442792 |
| Directory | /workspace/99.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/default/0.chip_jtag_mem_access.3167171290 |
| Short name | T76 |
| Test name | |
| Test status | |
| Simulation time | 13261901828 ps |
| CPU time | 1324.26 seconds |
| Started | Jun 29 07:30:25 PM PDT 24 |
| Finished | Jun 29 07:52:29 PM PDT 24 |
| Peak memory | 607288 kb |
| Host | smart-ac2b4fe6-cd51-41b2-a424-624505d056f1 |
| User | root |
| Command | /workspace/default/simv +create_jtag_riscv_map=1 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3167171290 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_jtag_ mem_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_jtag_mem_access.3 167171290 |
| Directory | /workspace/0.chip_jtag_mem_access/latest |
| Test location | /workspace/coverage/default/0.chip_sival_flash_info_access.264280021 |
| Short name | T1035 |
| Test name | |
| Test status | |
| Simulation time | 3588850760 ps |
| CPU time | 363.32 seconds |
| Started | Jun 29 07:42:08 PM PDT 24 |
| Finished | Jun 29 07:48:12 PM PDT 24 |
| Peak memory | 609160 kb |
| Host | smart-b5e1cc77-8e77-40de-9053-d464dd5c8654 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStTestUnlocked0 +sw_build_device=sim_dv +sw_images=flash_ctrl_info_access_lc:1:new_rules,test_rom:0 +c dc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_s eed=264280021 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sival_flash_info_access.264280021 |
| Directory | /workspace/0.chip_sival_flash_info_access/latest |
| Test location | /workspace/coverage/default/0.chip_sw_aes_enc.656357715 |
| Short name | T876 |
| Test name | |
| Test status | |
| Simulation time | 3286403580 ps |
| CPU time | 261.61 seconds |
| Started | Jun 29 07:44:36 PM PDT 24 |
| Finished | Jun 29 07:48:59 PM PDT 24 |
| Peak memory | 607104 kb |
| Host | smart-a42c5f45-de99-4b00-b854-8033f0341498 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=22_000_000 +sw_build_device=sim_dv +sw_images=aes_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=656357715 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage /default.vdb -cm_log /dev/null -cm_name 0.chip_sw_aes_enc.656357715 |
| Directory | /workspace/0.chip_sw_aes_enc/latest |
| Test location | /workspace/coverage/default/0.chip_sw_aes_enc_jitter_en.666461323 |
| Short name | T847 |
| Test name | |
| Test status | |
| Simulation time | 2815772586 ps |
| CPU time | 231.75 seconds |
| Started | Jun 29 07:39:16 PM PDT 24 |
| Finished | Jun 29 07:43:08 PM PDT 24 |
| Peak memory | 607720 kb |
| Host | smart-e7fe54f1-cb67-4c3f-8cc7-48f112bb338c |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=26_000_000 +en_jitter=1 +sw_build_device=sim_dv +sw_images=aes_smoketest:1:new_rules,test_rom:0 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=6664 61323 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_aes_enc_jitter_en.666461323 |
| Directory | /workspace/0.chip_sw_aes_enc_jitter_en/latest |
| Test location | /workspace/coverage/default/0.chip_sw_aes_enc_jitter_en_reduced_freq.3176033813 |
| Short name | T1034 |
| Test name | |
| Test status | |
| Simulation time | 3605147499 ps |
| CPU time | 295.54 seconds |
| Started | Jun 29 07:43:15 PM PDT 24 |
| Finished | Jun 29 07:48:12 PM PDT 24 |
| Peak memory | 609180 kb |
| Host | smart-850c515a-9c30-4f7e-b8c9-f600702a852e |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=26_000_000 +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=aes_smoketest:1:new_rules, test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3176033813 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_aes_enc_jitter_en_reduced_freq.3176033813 |
| Directory | /workspace/0.chip_sw_aes_enc_jitter_en_reduced_freq/latest |
| Test location | /workspace/coverage/default/0.chip_sw_aes_entropy.3753178241 |
| Short name | T926 |
| Test name | |
| Test status | |
| Simulation time | 3168480870 ps |
| CPU time | 257.38 seconds |
| Started | Jun 29 07:46:51 PM PDT 24 |
| Finished | Jun 29 07:51:09 PM PDT 24 |
| Peak memory | 609168 kb |
| Host | smart-bbc85a3c-5d52-42bd-baf8-33fad7fb4933 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=15_000_000 +sw_build_device=sim_dv +sw_images=aes_entropy_test:1:new_rules,test_rom:0 +cdc_instrumentation _enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3753178241 -as sert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove rage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_aes_entropy.3753178241 |
| Directory | /workspace/0.chip_sw_aes_entropy/latest |
| Test location | /workspace/coverage/default/0.chip_sw_aes_idle.2814048439 |
| Short name | T1083 |
| Test name | |
| Test status | |
| Simulation time | 2643054902 ps |
| CPU time | 252.23 seconds |
| Started | Jun 29 07:40:49 PM PDT 24 |
| Finished | Jun 29 07:45:03 PM PDT 24 |
| Peak memory | 609164 kb |
| Host | smart-3e75bc0d-1485-46fb-ac9a-a68d191d704d |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=25_000_000 +sw_build_device=sim_dv +sw_images=aes_idle_test:1:new_rules,test_rom:0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2814048439 -asser t nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag e/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_aes_idle.2814048439 |
| Directory | /workspace/0.chip_sw_aes_idle/latest |
| Test location | /workspace/coverage/default/0.chip_sw_aes_masking_off.19508339 |
| Short name | T941 |
| Test name | |
| Test status | |
| Simulation time | 2830520623 ps |
| CPU time | 327.2 seconds |
| Started | Jun 29 07:39:18 PM PDT 24 |
| Finished | Jun 29 07:44:47 PM PDT 24 |
| Peak memory | 607180 kb |
| Host | smart-dc08bc8b-9df9-4d19-b009-01b29eb89a77 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=aes_masking_off_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19508339 -assert nopostproc +UVM_TESTNAME =chip_base_test +UVM_TEST_SEQ=chip_sw_aes_masking_off_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb - cm_log /dev/null -cm_name 0.chip_sw_aes_masking_off.19508339 |
| Directory | /workspace/0.chip_sw_aes_masking_off/latest |
| Test location | /workspace/coverage/default/0.chip_sw_aes_smoketest.2796376977 |
| Short name | T667 |
| Test name | |
| Test status | |
| Simulation time | 2735849368 ps |
| CPU time | 309.74 seconds |
| Started | Jun 29 07:39:20 PM PDT 24 |
| Finished | Jun 29 07:44:31 PM PDT 24 |
| Peak memory | 606312 kb |
| Host | smart-9b18e59e-b8b2-41dc-8089-335fb63e6d73 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=aes_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2796376977 -assert nopostproc +UVM_TESTNAME=chip _base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_aes_smoketest.2796376977 |
| Directory | /workspace/0.chip_sw_aes_smoketest/latest |
| Test location | /workspace/coverage/default/0.chip_sw_alert_handler_entropy.2733299070 |
| Short name | T1222 |
| Test name | |
| Test status | |
| Simulation time | 3541310048 ps |
| CPU time | 317.68 seconds |
| Started | Jun 29 07:42:21 PM PDT 24 |
| Finished | Jun 29 07:47:40 PM PDT 24 |
| Peak memory | 607464 kb |
| Host | smart-45174a78-1f9d-4130-93d9-80ecd80cfe93 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=alert_handler_entropy_test:1:new_rules,test_ro m:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=2733299070 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_alert_handler_entropy.2733299070 |
| Directory | /workspace/0.chip_sw_alert_handler_entropy/latest |
| Test location | /workspace/coverage/default/0.chip_sw_alert_handler_escalation.3356053358 |
| Short name | T55 |
| Test name | |
| Test status | |
| Simulation time | 5760775984 ps |
| CPU time | 574.88 seconds |
| Started | Jun 29 07:43:37 PM PDT 24 |
| Finished | Jun 29 07:53:13 PM PDT 24 |
| Peak memory | 613740 kb |
| Host | smart-a6e62c98-3b82-4e39-ac2a-fa09fe262928 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=alert_handler_escalation_test:1:new_rules,test _rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb _random_seed=3356053358 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_alert_handler_escalation_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_alert_handler_escalation.3356053358 |
| Directory | /workspace/0.chip_sw_alert_handler_escalation/latest |
| Test location | /workspace/coverage/default/0.chip_sw_alert_handler_lpg_clkoff.1840114159 |
| Short name | T1080 |
| Test name | |
| Test status | |
| Simulation time | 7088360080 ps |
| CPU time | 1631.5 seconds |
| Started | Jun 29 07:46:47 PM PDT 24 |
| Finished | Jun 29 08:14:00 PM PDT 24 |
| Peak memory | 608204 kb |
| Host | smart-161f1b6d-2a15-4efd-9989-c729bd4d5dd5 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +sw_build_device=sim_dv +sw_images=alert_handler_lpg_clkoff_test:1:new_rules,test_r om:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r andom_seed=1840114159 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_alert_handler_lpg_clkoff_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_alert_handler_lpg_clkoff.1840114159 |
| Directory | /workspace/0.chip_sw_alert_handler_lpg_clkoff/latest |
| Test location | /workspace/coverage/default/0.chip_sw_alert_handler_lpg_reset_toggle.175737282 |
| Short name | T366 |
| Test name | |
| Test status | |
| Simulation time | 7316563684 ps |
| CPU time | 1788.39 seconds |
| Started | Jun 29 07:42:11 PM PDT 24 |
| Finished | Jun 29 08:12:00 PM PDT 24 |
| Peak memory | 608228 kb |
| Host | smart-fe9893d6-4b40-4e6f-b025-9b1cce599527 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +sw_build_device=sim_dv +sw_images=alert_handler_lpg_reset_toggle_test:1:new_rules, test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=175737282 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_alert_handler_shorten_ping_wait_cycle_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_alert_handler_lpg_reset_toggle.175737282 |
| Directory | /workspace/0.chip_sw_alert_handler_lpg_reset_toggle/latest |
| Test location | /workspace/coverage/default/0.chip_sw_alert_handler_lpg_sleep_mode_pings.931292247 |
| Short name | T1022 |
| Test name | |
| Test status | |
| Simulation time | 14053608290 ps |
| CPU time | 1649.97 seconds |
| Started | Jun 29 07:44:06 PM PDT 24 |
| Finished | Jun 29 08:11:37 PM PDT 24 |
| Peak memory | 608628 kb |
| Host | smart-87c676f2-52b9-442c-9863-fa0049be2746 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=alert_handler _lpg_sleep_mode_pings_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=931292247 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_alert_hand ler_shorten_ping_wait_cycle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_alert_handler_lpg_sleep_mode_pings.931292247 |
| Directory | /workspace/0.chip_sw_alert_handler_lpg_sleep_mode_pings/latest |
| Test location | /workspace/coverage/default/0.chip_sw_alert_handler_ping_ok.747997125 |
| Short name | T1188 |
| Test name | |
| Test status | |
| Simulation time | 8038793544 ps |
| CPU time | 1500.73 seconds |
| Started | Jun 29 07:39:41 PM PDT 24 |
| Finished | Jun 29 08:04:42 PM PDT 24 |
| Peak memory | 606864 kb |
| Host | smart-eb20d7be-97c2-4e9e-a6df-edd789dc37b0 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=24000000 +sw_build_device=sim_dv +sw_images=alert_handler_ping_ok_test:1:new_rules,test_rom:0 +c dc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_s eed=747997125 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_alert_handler_ping_ok.747997125 |
| Directory | /workspace/0.chip_sw_alert_handler_ping_ok/latest |
| Test location | /workspace/coverage/default/0.chip_sw_alert_handler_ping_timeout.67358576 |
| Short name | T450 |
| Test name | |
| Test status | |
| Simulation time | 5174921336 ps |
| CPU time | 513.86 seconds |
| Started | Jun 29 07:40:21 PM PDT 24 |
| Finished | Jun 29 07:48:55 PM PDT 24 |
| Peak memory | 606912 kb |
| Host | smart-d263903e-a636-42f5-bbbe-cc1b1fc4fa91 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=24000000 +sw_build_device=sim_dv +sw_images=alert_handler_ping_timeout_test:1:new_rules,test_rom :0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=67358576 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_alert_handler_ping_timeout.67358576 |
| Directory | /workspace/0.chip_sw_alert_handler_ping_timeout/latest |
| Test location | /workspace/coverage/default/0.chip_sw_alert_handler_reverse_ping_in_deep_sleep.3696194247 |
| Short name | T1072 |
| Test name | |
| Test status | |
| Simulation time | 255072722466 ps |
| CPU time | 13851.9 seconds |
| Started | Jun 29 07:37:59 PM PDT 24 |
| Finished | Jun 29 11:28:52 PM PDT 24 |
| Peak memory | 608488 kb |
| Host | smart-b8e73658-ec45-4084-b848-df535efb0261 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=300_000_000 +sw_build_device=sim_dv +sw_images=alert_handler_reverse_ping_in_deep_sleep_test:1:n ew_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3696194247 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_alert_handler_reverse_ping_in_deep_sleep.3696194247 |
| Directory | /workspace/0.chip_sw_alert_handler_reverse_ping_in_deep_sleep/latest |
| Test location | /workspace/coverage/default/0.chip_sw_alert_test.2544648161 |
| Short name | T59 |
| Test name | |
| Test status | |
| Simulation time | 3152037300 ps |
| CPU time | 368.89 seconds |
| Started | Jun 29 07:43:20 PM PDT 24 |
| Finished | Jun 29 07:49:29 PM PDT 24 |
| Peak memory | 607132 kb |
| Host | smart-ff2381ec-c88b-428d-bedc-18b3fde534ef |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=alert_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2544648161 -assert nopostproc +UVM_TESTNAME=chip_ba se_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 0.chip_sw_alert_test.2544648161 |
| Directory | /workspace/0.chip_sw_alert_test/latest |
| Test location | /workspace/coverage/default/0.chip_sw_aon_timer_irq.3462814957 |
| Short name | T1082 |
| Test name | |
| Test status | |
| Simulation time | 3314602772 ps |
| CPU time | 437.16 seconds |
| Started | Jun 29 07:42:48 PM PDT 24 |
| Finished | Jun 29 07:50:07 PM PDT 24 |
| Peak memory | 607620 kb |
| Host | smart-45467baa-552b-454f-92e4-256d244cec1a |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=aon_timer_irq_test:1:new_rules,test_rom:0 +cdc_instrumentati on_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3462814957 - assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co verage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_aon_timer_irq.3462814957 |
| Directory | /workspace/0.chip_sw_aon_timer_irq/latest |
| Test location | /workspace/coverage/default/0.chip_sw_aon_timer_sleep_wdog_sleep_pause.2366235468 |
| Short name | T1050 |
| Test name | |
| Test status | |
| Simulation time | 6858732160 ps |
| CPU time | 351.98 seconds |
| Started | Jun 29 07:37:48 PM PDT 24 |
| Finished | Jun 29 07:43:41 PM PDT 24 |
| Peak memory | 608272 kb |
| Host | smart-57d64b46-bb1b-45d8-9871-55e40823b2d0 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=aon_timer_sleep_wdog_sleep_pause_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=2366235468 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_aon_timer_sleep_wdog_sleep_pause.2366235468 |
| Directory | /workspace/0.chip_sw_aon_timer_sleep_wdog_sleep_pause/latest |
| Test location | /workspace/coverage/default/0.chip_sw_aon_timer_smoketest.1083544719 |
| Short name | T942 |
| Test name | |
| Test status | |
| Simulation time | 2252119424 ps |
| CPU time | 242.48 seconds |
| Started | Jun 29 07:44:51 PM PDT 24 |
| Finished | Jun 29 07:48:54 PM PDT 24 |
| Peak memory | 609176 kb |
| Host | smart-0c097326-3349-44f0-a39c-55a0a5496837 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=aon_timer_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1083544719 -assert nopostproc +UVM_TESTNAM E=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 0.chip_sw_aon_timer_smoketest.1083544719 |
| Directory | /workspace/0.chip_sw_aon_timer_smoketest/latest |
| Test location | /workspace/coverage/default/0.chip_sw_aon_timer_wdog_bite_reset.661109234 |
| Short name | T859 |
| Test name | |
| Test status | |
| Simulation time | 8327046504 ps |
| CPU time | 828.95 seconds |
| Started | Jun 29 07:38:34 PM PDT 24 |
| Finished | Jun 29 07:52:23 PM PDT 24 |
| Peak memory | 609232 kb |
| Host | smart-64c21d28-aee6-4662-9d4f-654c395521f8 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=aon_timer_wdog_bite_reset_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 661109234 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_aon_timer_wdog_bite_reset.661109234 |
| Directory | /workspace/0.chip_sw_aon_timer_wdog_bite_reset/latest |
| Test location | /workspace/coverage/default/0.chip_sw_aon_timer_wdog_lc_escalate.3452540512 |
| Short name | T1025 |
| Test name | |
| Test status | |
| Simulation time | 6062331100 ps |
| CPU time | 858.33 seconds |
| Started | Jun 29 07:39:41 PM PDT 24 |
| Finished | Jun 29 07:54:00 PM PDT 24 |
| Peak memory | 609204 kb |
| Host | smart-129c4aaf-ceff-4a58-ad4e-6634b1ccb812 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=aon_timer_wdog_lc_escalate_test:1:new_rules,test_rom:0 +cdc_ instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed =3452540512 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_aon_timer_wdog_lc_escalate.3452540512 |
| Directory | /workspace/0.chip_sw_aon_timer_wdog_lc_escalate/latest |
| Test location | /workspace/coverage/default/0.chip_sw_ast_clk_outputs.2048084144 |
| Short name | T357 |
| Test name | |
| Test status | |
| Simulation time | 7960129020 ps |
| CPU time | 919.6 seconds |
| Started | Jun 29 07:39:03 PM PDT 24 |
| Finished | Jun 29 07:54:23 PM PDT 24 |
| Peak memory | 615068 kb |
| Host | smart-b1260d40-4b15-462f-9549-db231bc538a9 |
| User | root |
| Command | /workspace/default/simv +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=ast_clk_outs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled= 1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2048084144 -assert nopo stproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_ast_clk_outputs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co verage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_ast_clk_outputs.2048084144 |
| Directory | /workspace/0.chip_sw_ast_clk_outputs/latest |
| Test location | /workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_lc.1958881958 |
| Short name | T1220 |
| Test name | |
| Test status | |
| Simulation time | 7302814733 ps |
| CPU time | 570.84 seconds |
| Started | Jun 29 07:40:00 PM PDT 24 |
| Finished | Jun 29 07:49:31 PM PDT 24 |
| Peak memory | 619188 kb |
| Host | smart-7bd9e1c1-7d2c-41f5-9bd0-541528fc2a9e |
| User | root |
| Command | /workspace/default/simv +chip_clock_source=ChipClockSourceExternal48Mhz +sw_build_device=sim_dv +sw_images=clkmgr_external_clk_src_for_lc_test:1:new_r ules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim .tcl +ntb_random_seed=1958881958 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_transition_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_clkmgr_external_clk_src_for_lc.1958881958 |
| Directory | /workspace/0.chip_sw_clkmgr_external_clk_src_for_lc/latest |
| Test location | /workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_fast_dev.272872119 |
| Short name | T256 |
| Test name | |
| Test status | |
| Simulation time | 4233133240 ps |
| CPU time | 605.41 seconds |
| Started | Jun 29 07:39:39 PM PDT 24 |
| Finished | Jun 29 07:49:46 PM PDT 24 |
| Peak memory | 608624 kb |
| Host | smart-c1a86af9-0e67-4d5e-865f-c8e18a88ddf6 |
| User | root |
| Command | /workspace/default/simv +chip_clock_source=ChipClockSourceExternal96Mhz +calibrate_usb_clk=1 +src_dec_state=DecLcStDev +sw_build_device=sim_dv +sw_ima ges=clkmgr_external_clk_src_for_sw_fast_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=272872119 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ= chip_sw_lc_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_cl kmgr_external_clk_src_for_sw_fast_dev.272872119 |
| Directory | /workspace/0.chip_sw_clkmgr_external_clk_src_for_sw_fast_dev/latest |
| Test location | /workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_fast_rma.1295142839 |
| Short name | T1053 |
| Test name | |
| Test status | |
| Simulation time | 4063151728 ps |
| CPU time | 607.23 seconds |
| Started | Jun 29 07:39:43 PM PDT 24 |
| Finished | Jun 29 07:49:52 PM PDT 24 |
| Peak memory | 611864 kb |
| Host | smart-92bc7bd7-eea7-404b-9755-29221ac0f6dd |
| User | root |
| Command | /workspace/default/simv +chip_clock_source=ChipClockSourceExternal96Mhz +calibrate_usb_clk=1 +src_dec_state=DecLcStRma +sw_build_device=sim_dv +sw_ima ges=clkmgr_external_clk_src_for_sw_fast_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1295142839 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ =chip_sw_lc_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_c lkmgr_external_clk_src_for_sw_fast_rma.1295142839 |
| Directory | /workspace/0.chip_sw_clkmgr_external_clk_src_for_sw_fast_rma/latest |
| Test location | /workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0.2959599193 |
| Short name | T1241 |
| Test name | |
| Test status | |
| Simulation time | 4116273000 ps |
| CPU time | 724.83 seconds |
| Started | Jun 29 07:44:02 PM PDT 24 |
| Finished | Jun 29 07:56:08 PM PDT 24 |
| Peak memory | 611936 kb |
| Host | smart-ca481b53-870a-4a40-9959-5a039809593b |
| User | root |
| Command | /workspace/default/simv +chip_clock_source=ChipClockSourceExternal96Mhz +calibrate_usb_clk=1 +src_dec_state=DecLcStTestUnlocked0 +sw_build_device=sim_ dv +sw_images=clkmgr_external_clk_src_for_sw_fast_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2959599193 -assert nopostproc +UVM_TESTNAME=chip_base_test +UV M_TEST_SEQ=chip_sw_lc_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0 .chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0.2959599193 |
| Directory | /workspace/0.chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0/latest |
| Test location | /workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_slow_dev.2261488484 |
| Short name | T1160 |
| Test name | |
| Test status | |
| Simulation time | 4912497144 ps |
| CPU time | 723.64 seconds |
| Started | Jun 29 07:39:06 PM PDT 24 |
| Finished | Jun 29 07:51:11 PM PDT 24 |
| Peak memory | 611944 kb |
| Host | smart-955e3bcc-3ae0-4685-ae54-c147c52d6960 |
| User | root |
| Command | /workspace/default/simv +chip_clock_source=ChipClockSourceExternal48Mhz +calibrate_usb_clk=1 +src_dec_state=DecLcStDev +sw_build_device=sim_dv +sw_ima ges=clkmgr_external_clk_src_for_sw_slow_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2261488484 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ =chip_sw_lc_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_c lkmgr_external_clk_src_for_sw_slow_dev.2261488484 |
| Directory | /workspace/0.chip_sw_clkmgr_external_clk_src_for_sw_slow_dev/latest |
| Test location | /workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_slow_rma.3575432331 |
| Short name | T115 |
| Test name | |
| Test status | |
| Simulation time | 4124422416 ps |
| CPU time | 697.97 seconds |
| Started | Jun 29 07:38:40 PM PDT 24 |
| Finished | Jun 29 07:50:19 PM PDT 24 |
| Peak memory | 611908 kb |
| Host | smart-88c540d9-ae79-457e-9863-80a33410045a |
| User | root |
| Command | /workspace/default/simv +chip_clock_source=ChipClockSourceExternal48Mhz +calibrate_usb_clk=1 +src_dec_state=DecLcStRma +sw_build_device=sim_dv +sw_ima ges=clkmgr_external_clk_src_for_sw_slow_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3575432331 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ =chip_sw_lc_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_c lkmgr_external_clk_src_for_sw_slow_rma.3575432331 |
| Directory | /workspace/0.chip_sw_clkmgr_external_clk_src_for_sw_slow_rma/latest |
| Test location | /workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0.2573825986 |
| Short name | T931 |
| Test name | |
| Test status | |
| Simulation time | 4060569346 ps |
| CPU time | 643.13 seconds |
| Started | Jun 29 07:37:49 PM PDT 24 |
| Finished | Jun 29 07:48:33 PM PDT 24 |
| Peak memory | 611880 kb |
| Host | smart-5f5a90d2-b8da-484b-b84d-112ebdb4dfb0 |
| User | root |
| Command | /workspace/default/simv +chip_clock_source=ChipClockSourceExternal48Mhz +calibrate_usb_clk=1 +src_dec_state=DecLcStTestUnlocked0 +sw_build_device=sim_ dv +sw_images=clkmgr_external_clk_src_for_sw_slow_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2573825986 -assert nopostproc +UVM_TESTNAME=chip_base_test +UV M_TEST_SEQ=chip_sw_lc_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0 .chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0.2573825986 |
| Directory | /workspace/0.chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0/latest |
| Test location | /workspace/coverage/default/0.chip_sw_clkmgr_jitter.1641468522 |
| Short name | T1257 |
| Test name | |
| Test status | |
| Simulation time | 2146852746 ps |
| CPU time | 206.2 seconds |
| Started | Jun 29 07:40:32 PM PDT 24 |
| Finished | Jun 29 07:43:59 PM PDT 24 |
| Peak memory | 607072 kb |
| Host | smart-ec68b8bf-e4f8-455a-a797-8f2618254c3a |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_jitter_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1641468522 -assert nopostproc +UVM_TESTNAME =chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 0.chip_sw_clkmgr_jitter.1641468522 |
| Directory | /workspace/0.chip_sw_clkmgr_jitter/latest |
| Test location | /workspace/coverage/default/0.chip_sw_clkmgr_jitter_frequency.1506387846 |
| Short name | T275 |
| Test name | |
| Test status | |
| Simulation time | 3073737848 ps |
| CPU time | 386.06 seconds |
| Started | Jun 29 07:40:57 PM PDT 24 |
| Finished | Jun 29 07:47:23 PM PDT 24 |
| Peak memory | 607332 kb |
| Host | smart-961f4198-10b5-49e3-afc0-c66b559f6f60 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_jitter_frequency_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1506387846 -assert nopostproc +UV M_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -c m_log /dev/null -cm_name 0.chip_sw_clkmgr_jitter_frequency.1506387846 |
| Directory | /workspace/0.chip_sw_clkmgr_jitter_frequency/latest |
| Test location | /workspace/coverage/default/0.chip_sw_clkmgr_jitter_reduced_freq.158461398 |
| Short name | T952 |
| Test name | |
| Test status | |
| Simulation time | 2535072573 ps |
| CPU time | 222.66 seconds |
| Started | Jun 29 07:39:49 PM PDT 24 |
| Finished | Jun 29 07:43:32 PM PDT 24 |
| Peak memory | 609152 kb |
| Host | smart-7dfc4084-995e-48b9-87c8-727b76d681e4 |
| User | root |
| Command | /workspace/default/simv +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=clkmgr_jitter_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=158461398 -assert nopo stproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defa ult.vdb -cm_log /dev/null -cm_name 0.chip_sw_clkmgr_jitter_reduced_freq.158461398 |
| Directory | /workspace/0.chip_sw_clkmgr_jitter_reduced_freq/latest |
| Test location | /workspace/coverage/default/0.chip_sw_clkmgr_off_aes_trans.148378843 |
| Short name | T856 |
| Test name | |
| Test status | |
| Simulation time | 4791699274 ps |
| CPU time | 373.86 seconds |
| Started | Jun 29 07:40:58 PM PDT 24 |
| Finished | Jun 29 07:47:13 PM PDT 24 |
| Peak memory | 609172 kb |
| Host | smart-69f9cc1c-7a25-4154-a8bd-6e9c1bb16dcd |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_off_aes_trans_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=148378843 -assert nopostproc +UVM_TE STNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo g /dev/null -cm_name 0.chip_sw_clkmgr_off_aes_trans.148378843 |
| Directory | /workspace/0.chip_sw_clkmgr_off_aes_trans/latest |
| Test location | /workspace/coverage/default/0.chip_sw_clkmgr_off_hmac_trans.1299213819 |
| Short name | T842 |
| Test name | |
| Test status | |
| Simulation time | 5592696672 ps |
| CPU time | 452.29 seconds |
| Started | Jun 29 07:39:06 PM PDT 24 |
| Finished | Jun 29 07:46:39 PM PDT 24 |
| Peak memory | 609192 kb |
| Host | smart-62da3f08-d350-497a-8fb6-01967befa54c |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_off_hmac_trans_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1299213819 -assert nopostproc +UVM_ TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_ log /dev/null -cm_name 0.chip_sw_clkmgr_off_hmac_trans.1299213819 |
| Directory | /workspace/0.chip_sw_clkmgr_off_hmac_trans/latest |
| Test location | /workspace/coverage/default/0.chip_sw_clkmgr_off_kmac_trans.3267603697 |
| Short name | T840 |
| Test name | |
| Test status | |
| Simulation time | 5737037750 ps |
| CPU time | 507.24 seconds |
| Started | Jun 29 07:39:44 PM PDT 24 |
| Finished | Jun 29 07:48:11 PM PDT 24 |
| Peak memory | 609192 kb |
| Host | smart-0a1d5fd0-f544-442b-94d7-f1d053f543e2 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_off_kmac_trans_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3267603697 -assert nopostproc +UVM_ TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_ log /dev/null -cm_name 0.chip_sw_clkmgr_off_kmac_trans.3267603697 |
| Directory | /workspace/0.chip_sw_clkmgr_off_kmac_trans/latest |
| Test location | /workspace/coverage/default/0.chip_sw_clkmgr_off_otbn_trans.3363775313 |
| Short name | T977 |
| Test name | |
| Test status | |
| Simulation time | 3994229420 ps |
| CPU time | 424.37 seconds |
| Started | Jun 29 07:41:42 PM PDT 24 |
| Finished | Jun 29 07:48:46 PM PDT 24 |
| Peak memory | 609152 kb |
| Host | smart-f636cefe-2cd9-4ea2-9b2e-6a92c739ce8f |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_off_otbn_trans_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3363775313 -assert nopostproc +UVM_ TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_ log /dev/null -cm_name 0.chip_sw_clkmgr_off_otbn_trans.3363775313 |
| Directory | /workspace/0.chip_sw_clkmgr_off_otbn_trans/latest |
| Test location | /workspace/coverage/default/0.chip_sw_clkmgr_off_peri.963115807 |
| Short name | T1121 |
| Test name | |
| Test status | |
| Simulation time | 9226222872 ps |
| CPU time | 1011.8 seconds |
| Started | Jun 29 07:44:44 PM PDT 24 |
| Finished | Jun 29 08:01:37 PM PDT 24 |
| Peak memory | 609172 kb |
| Host | smart-7b08fbb6-9d52-4725-b97f-cd487c26ba33 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=30_000_000 +sw_build_device=sim_dv +sw_images=clkmgr_off_peri_test:1:new_rules,test_rom:0 +cdc_instrumenta tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=963115807 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/c overage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_clkmgr_off_peri.963115807 |
| Directory | /workspace/0.chip_sw_clkmgr_off_peri/latest |
| Test location | /workspace/coverage/default/0.chip_sw_clkmgr_reset_frequency.3645728211 |
| Short name | T656 |
| Test name | |
| Test status | |
| Simulation time | 2967406074 ps |
| CPU time | 319.54 seconds |
| Started | Jun 29 07:39:33 PM PDT 24 |
| Finished | Jun 29 07:44:53 PM PDT 24 |
| Peak memory | 607116 kb |
| Host | smart-4fc13c27-cbce-4629-9d91-1f280d5aaddb |
| User | root |
| Command | /workspace/default/simv +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=clkmgr_reset_frequency_test:1:new_rules,test_rom:0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3645728211 -a ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov erage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_clkmgr_reset_frequency.3645728211 |
| Directory | /workspace/0.chip_sw_clkmgr_reset_frequency/latest |
| Test location | /workspace/coverage/default/0.chip_sw_clkmgr_sleep_frequency.1947173302 |
| Short name | T360 |
| Test name | |
| Test status | |
| Simulation time | 4614498086 ps |
| CPU time | 604.34 seconds |
| Started | Jun 29 07:44:01 PM PDT 24 |
| Finished | Jun 29 07:54:06 PM PDT 24 |
| Peak memory | 609240 kb |
| Host | smart-2273dd1c-ed89-4561-9084-f4b53f563ddd |
| User | root |
| Command | /workspace/default/simv +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=clkmgr_sleep_frequency_test:1:new_rules,test_rom:0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1947173302 -a ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov erage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_clkmgr_sleep_frequency.1947173302 |
| Directory | /workspace/0.chip_sw_clkmgr_sleep_frequency/latest |
| Test location | /workspace/coverage/default/0.chip_sw_clkmgr_smoketest.2222028057 |
| Short name | T1079 |
| Test name | |
| Test status | |
| Simulation time | 3053055976 ps |
| CPU time | 304.08 seconds |
| Started | Jun 29 07:40:39 PM PDT 24 |
| Finished | Jun 29 07:45:44 PM PDT 24 |
| Peak memory | 607144 kb |
| Host | smart-178034b2-9773-40de-9c0e-a3f80da6b6aa |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2222028057 -assert nopostproc +UVM_TESTNAME=c hip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n ull -cm_name 0.chip_sw_clkmgr_smoketest.2222028057 |
| Directory | /workspace/0.chip_sw_clkmgr_smoketest/latest |
| Test location | /workspace/coverage/default/0.chip_sw_csrng_edn_concurrency_reduced_freq.210093800 |
| Short name | T108 |
| Test name | |
| Test status | |
| Simulation time | 55623873088 ps |
| CPU time | 9597.09 seconds |
| Started | Jun 29 07:45:14 PM PDT 24 |
| Finished | Jun 29 10:25:13 PM PDT 24 |
| Peak memory | 609320 kb |
| Host | smart-208f809d-8281-4b73-90f5-5b8c7bf2bec8 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=360_000_000 +rng_srate_value_min=15 +rng_srate_value_max=20 +cal_sys_clk_70mhz=1 +en_jitter=1 +sw_build_de vice=sim_dv +sw_images=csrng_edn_concurrency_test:1:new_rules,test_rom:0 +accelerate_cold_power_up_time=3 +accelerate_regulators_power_up_time=2 + cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_ seed=210093800 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_csrng_edn_concurrency_reduced_freq.210093800 |
| Directory | /workspace/0.chip_sw_csrng_edn_concurrency_reduced_freq/latest |
| Test location | /workspace/coverage/default/0.chip_sw_csrng_fuse_en_sw_app_read_test.4194824106 |
| Short name | T1211 |
| Test name | |
| Test status | |
| Simulation time | 3467494720 ps |
| CPU time | 418.97 seconds |
| Started | Jun 29 07:38:23 PM PDT 24 |
| Finished | Jun 29 07:45:23 PM PDT 24 |
| Peak memory | 609180 kb |
| Host | smart-5bfb4a38-b0c9-4ec4-92e4-db5856bd7c2f |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=15_000_000 +sw_build_device=sim_dv +sw_images=csrng_fuse_en_sw_app_read:1:new_rules,test_rom:0 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41948 24106 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_entropy_src_fuse_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_csrng_fuse_en_sw_app_read_test.4194824106 |
| Directory | /workspace/0.chip_sw_csrng_fuse_en_sw_app_read_test/latest |
| Test location | /workspace/coverage/default/0.chip_sw_csrng_kat_test.4043496580 |
| Short name | T858 |
| Test name | |
| Test status | |
| Simulation time | 2698865624 ps |
| CPU time | 187.26 seconds |
| Started | Jun 29 07:39:49 PM PDT 24 |
| Finished | Jun 29 07:42:57 PM PDT 24 |
| Peak memory | 607508 kb |
| Host | smart-1bff9c63-0b45-45bb-92d1-e2b2d6337711 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=csrng_kat_test:1:new_rules,test_rom:0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4043496580 -asse rt nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera ge/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_csrng_kat_test.4043496580 |
| Directory | /workspace/0.chip_sw_csrng_kat_test/latest |
| Test location | /workspace/coverage/default/0.chip_sw_csrng_smoketest.1883379261 |
| Short name | T834 |
| Test name | |
| Test status | |
| Simulation time | 2820312912 ps |
| CPU time | 188.36 seconds |
| Started | Jun 29 07:39:56 PM PDT 24 |
| Finished | Jun 29 07:43:05 PM PDT 24 |
| Peak memory | 606264 kb |
| Host | smart-f77b68f4-644b-4791-abfa-15bbfb64ee36 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=csrng_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1883379261 -assert nopostproc +UVM_TESTNAME=ch ip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu ll -cm_name 0.chip_sw_csrng_smoketest.1883379261 |
| Directory | /workspace/0.chip_sw_csrng_smoketest/latest |
| Test location | /workspace/coverage/default/0.chip_sw_data_integrity_escalation.428271711 |
| Short name | T252 |
| Test name | |
| Test status | |
| Simulation time | 5703958612 ps |
| CPU time | 806.59 seconds |
| Started | Jun 29 07:41:29 PM PDT 24 |
| Finished | Jun 29 07:54:56 PM PDT 24 |
| Peak memory | 609272 kb |
| Host | smart-7b19eaef-30aa-4a7c-b8fc-1648a8384298 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=data_integrity_escalation_reset_test:1:new_rules,test_ro m:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=428271711 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_data_integrity_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_data_integrity_escalation.428271711 |
| Directory | /workspace/0.chip_sw_data_integrity_escalation/latest |
| Test location | /workspace/coverage/default/0.chip_sw_edn_auto_mode.552144334 |
| Short name | T1260 |
| Test name | |
| Test status | |
| Simulation time | 4360938940 ps |
| CPU time | 965.8 seconds |
| Started | Jun 29 07:39:56 PM PDT 24 |
| Finished | Jun 29 07:56:03 PM PDT 24 |
| Peak memory | 608132 kb |
| Host | smart-b77fe5b6-7325-42c6-955e-465db9cab9a8 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +rng_srate_value=5 +sw_build_device=sim_dv +sw_images=edn_auto_mode:1:new_rules,test_rom:0 +acc elerate_cold_power_up_time=3 +accelerate_regulators_power_up_time=2 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=552144334 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ= chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_edn_a uto_mode.552144334 |
| Directory | /workspace/0.chip_sw_edn_auto_mode/latest |
| Test location | /workspace/coverage/default/0.chip_sw_edn_entropy_reqs.2795547120 |
| Short name | T1215 |
| Test name | |
| Test status | |
| Simulation time | 6099828860 ps |
| CPU time | 908.96 seconds |
| Started | Jun 29 07:43:24 PM PDT 24 |
| Finished | Jun 29 07:58:35 PM PDT 24 |
| Peak memory | 608608 kb |
| Host | smart-069bd68b-36ea-4747-8d03-20ae49fab920 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=15000000 +rng_srate_value_min=15 +rng_srate_value_max=30 +sw_build_device=sim_dv +sw_images=entropy_src_ed n_reqs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2795547120 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_edn_entropy_reqs.2795547120 |
| Directory | /workspace/0.chip_sw_edn_entropy_reqs/latest |
| Test location | /workspace/coverage/default/0.chip_sw_edn_kat.1002520681 |
| Short name | T955 |
| Test name | |
| Test status | |
| Simulation time | 2853296534 ps |
| CPU time | 604.97 seconds |
| Started | Jun 29 07:39:42 PM PDT 24 |
| Finished | Jun 29 07:49:48 PM PDT 24 |
| Peak memory | 614544 kb |
| Host | smart-87cfacc7-6853-4d43-9901-2f49ed22553d |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +rng_srate_value=5 +disable_assert_edn_output_diff_from_prev=1 +sw_build_device=sim_dv +sw_imag es=edn_kat:1:new_rules,test_rom:0 +accelerate_cold_power_up_time=3 +accelerate_regulators_power_up_time=2 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1002520681 -assert nopostproc +UVM _TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm _log /dev/null -cm_name 0.chip_sw_edn_kat.1002520681 |
| Directory | /workspace/0.chip_sw_edn_kat/latest |
| Test location | /workspace/coverage/default/0.chip_sw_edn_sw_mode.675000594 |
| Short name | T1147 |
| Test name | |
| Test status | |
| Simulation time | 6267236356 ps |
| CPU time | 1743.71 seconds |
| Started | Jun 29 07:37:45 PM PDT 24 |
| Finished | Jun 29 08:06:49 PM PDT 24 |
| Peak memory | 609172 kb |
| Host | smart-d888e5a4-6f9f-47b4-824f-3441c7704d0c |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=edn_sw_mode:1:new_rules,test_rom:0 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=675000594 -assert n opostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/d efault.vdb -cm_log /dev/null -cm_name 0.chip_sw_edn_sw_mode.675000594 |
| Directory | /workspace/0.chip_sw_edn_sw_mode/latest |
| Test location | /workspace/coverage/default/0.chip_sw_entropy_src_ast_rng_req.3978738503 |
| Short name | T892 |
| Test name | |
| Test status | |
| Simulation time | 2385409182 ps |
| CPU time | 311.72 seconds |
| Started | Jun 29 07:38:25 PM PDT 24 |
| Finished | Jun 29 07:43:37 PM PDT 24 |
| Peak memory | 609184 kb |
| Host | smart-915f724b-a04a-421d-8858-bf33adb2fffe |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=15_000_000 +sw_build_device=sim_dv +sw_images=entropy_src_ast_rng_req_test:1:new_rules,test_rom:0 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39 78738503 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_entropy_src_ast_rng_req.3978738503 |
| Directory | /workspace/0.chip_sw_entropy_src_ast_rng_req/latest |
| Test location | /workspace/coverage/default/0.chip_sw_entropy_src_kat_test.3390163002 |
| Short name | T1182 |
| Test name | |
| Test status | |
| Simulation time | 3109094064 ps |
| CPU time | 207.11 seconds |
| Started | Jun 29 07:41:16 PM PDT 24 |
| Finished | Jun 29 07:44:43 PM PDT 24 |
| Peak memory | 609148 kb |
| Host | smart-43a3848f-2878-4a67-87c5-e35f2098b515 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=entropy_src_kat_test:1:new_rules,test_rom:0 +cdc_instrumenta tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3390163002 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/ coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_entropy_src_kat_test.3390163002 |
| Directory | /workspace/0.chip_sw_entropy_src_kat_test/latest |
| Test location | /workspace/coverage/default/0.chip_sw_entropy_src_smoketest.528190780 |
| Short name | T937 |
| Test name | |
| Test status | |
| Simulation time | 4438364440 ps |
| CPU time | 749.27 seconds |
| Started | Jun 29 07:41:23 PM PDT 24 |
| Finished | Jun 29 07:53:54 PM PDT 24 |
| Peak memory | 609184 kb |
| Host | smart-5949c58a-1536-4d53-b791-bfae3a06116f |
| User | root |
| Command | /workspace/default/simv +rng_srate_value_min=15 +rng_srate_value_max=30 +sw_build_device=sim_dv +sw_images=entropy_src_smoketest:1:new_rules,test_rom: 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand om_seed=528190780 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_entropy_src_smoketest.528190780 |
| Directory | /workspace/0.chip_sw_entropy_src_smoketest/latest |
| Test location | /workspace/coverage/default/0.chip_sw_example_concurrency.1218753369 |
| Short name | T895 |
| Test name | |
| Test status | |
| Simulation time | 3294866200 ps |
| CPU time | 231.73 seconds |
| Started | Jun 29 07:38:50 PM PDT 24 |
| Finished | Jun 29 07:42:43 PM PDT 24 |
| Peak memory | 607120 kb |
| Host | smart-adcf10cb-e53b-4ba6-9dcb-e1a405fd4d99 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=example_concurrency_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1218753369 -assert nopostproc +UVM_TE STNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo g /dev/null -cm_name 0.chip_sw_example_concurrency.1218753369 |
| Directory | /workspace/0.chip_sw_example_concurrency/latest |
| Test location | /workspace/coverage/default/0.chip_sw_example_flash.299221309 |
| Short name | T1164 |
| Test name | |
| Test status | |
| Simulation time | 2977563054 ps |
| CPU time | 267.06 seconds |
| Started | Jun 29 07:39:04 PM PDT 24 |
| Finished | Jun 29 07:43:31 PM PDT 24 |
| Peak memory | 609184 kb |
| Host | smart-1b352fd8-eb94-49e7-8df9-a84bf55f24cd |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=example_test_from_flash:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=299221309 -assert nopostproc +UVM_TEST NAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_example_flash.299221309 |
| Directory | /workspace/0.chip_sw_example_flash/latest |
| Test location | /workspace/coverage/default/0.chip_sw_example_manufacturer.2694255600 |
| Short name | T938 |
| Test name | |
| Test status | |
| Simulation time | 2594550144 ps |
| CPU time | 203.07 seconds |
| Started | Jun 29 07:38:12 PM PDT 24 |
| Finished | Jun 29 07:41:35 PM PDT 24 |
| Peak memory | 607164 kb |
| Host | smart-91a8e39b-341a-4156-a5dc-5b809a36384d |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=example_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2694255600 -assert nopostproc +UVM_TESTNAME=chip_ base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_example_manufacturer.2694255600 |
| Directory | /workspace/0.chip_sw_example_manufacturer/latest |
| Test location | /workspace/coverage/default/0.chip_sw_example_rom.208868450 |
| Short name | T1029 |
| Test name | |
| Test status | |
| Simulation time | 2674889336 ps |
| CPU time | 164.55 seconds |
| Started | Jun 29 07:37:14 PM PDT 24 |
| Finished | Jun 29 07:40:00 PM PDT 24 |
| Peak memory | 606732 kb |
| Host | smart-bc063d28-0c10-4b64-823a-1c3882cc0445 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:test_in_rom:new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=208868450 -assert nopostproc +UVM_TESTN AME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log / dev/null -cm_name 0.chip_sw_example_rom.208868450 |
| Directory | /workspace/0.chip_sw_example_rom/latest |
| Test location | /workspace/coverage/default/0.chip_sw_exit_test_unlocked_bootstrap.1251082625 |
| Short name | T18 |
| Test name | |
| Test status | |
| Simulation time | 59043802156 ps |
| CPU time | 11147.5 seconds |
| Started | Jun 29 07:38:07 PM PDT 24 |
| Finished | Jun 29 10:43:56 PM PDT 24 |
| Peak memory | 623280 kb |
| Host | smart-056bf26c-e6eb-41f5-b8c0-2529a804cd51 |
| User | root |
| Command | /workspace/default/simv +flash_program_latency=5 +sw_test_timeout_ns=150_000_000 +sw_build_device=sim_dv +sw_images=exit_test_unlocked_bootstrap:1:new _rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/s im.tcl +ntb_random_seed=1251082625 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_exit_test_unlocked_bootstrap_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_exit_test_unlocked_bootstrap.1251082625 |
| Directory | /workspace/0.chip_sw_exit_test_unlocked_bootstrap/latest |
| Test location | /workspace/coverage/default/0.chip_sw_flash_crash_alert.1241591425 |
| Short name | T973 |
| Test name | |
| Test status | |
| Simulation time | 5621589520 ps |
| CPU time | 759.1 seconds |
| Started | Jun 29 07:38:53 PM PDT 24 |
| Finished | Jun 29 07:51:32 PM PDT 24 |
| Peak memory | 609376 kb |
| Host | smart-49bc59bf-cbe7-4ef3-a0ac-7e41c3f54e13 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=8_000_000 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1: new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tool s/sim.tcl +ntb_random_seed=1241591425 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_flash_host_gnt_err_inj_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_flash_crash_alert.1241591425 |
| Directory | /workspace/0.chip_sw_flash_crash_alert/latest |
| Test location | /workspace/coverage/default/0.chip_sw_flash_ctrl_access.3850356686 |
| Short name | T1028 |
| Test name | |
| Test status | |
| Simulation time | 5106262760 ps |
| CPU time | 1253.05 seconds |
| Started | Jun 29 07:39:53 PM PDT 24 |
| Finished | Jun 29 08:00:47 PM PDT 24 |
| Peak memory | 607132 kb |
| Host | smart-7c1bd399-3309-4d7b-8b58-4da87a41e609 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=flash_ctrl_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3850356686 -assert nopostproc +UVM_TESTNAME=ch ip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu ll -cm_name 0.chip_sw_flash_ctrl_access.3850356686 |
| Directory | /workspace/0.chip_sw_flash_ctrl_access/latest |
| Test location | /workspace/coverage/default/0.chip_sw_flash_ctrl_access_jitter_en.1289052317 |
| Short name | T444 |
| Test name | |
| Test status | |
| Simulation time | 5843781676 ps |
| CPU time | 1027.93 seconds |
| Started | Jun 29 07:43:32 PM PDT 24 |
| Finished | Jun 29 08:00:41 PM PDT 24 |
| Peak memory | 609168 kb |
| Host | smart-95b7c741-30cf-4b33-9b5a-c7fa064bdbb2 |
| User | root |
| Command | /workspace/default/simv +en_jitter=1 +sw_build_device=sim_dv +sw_images=flash_ctrl_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1289052317 -assert nopostproc +UV M_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -c m_log /dev/null -cm_name 0.chip_sw_flash_ctrl_access_jitter_en.1289052317 |
| Directory | /workspace/0.chip_sw_flash_ctrl_access_jitter_en/latest |
| Test location | /workspace/coverage/default/0.chip_sw_flash_ctrl_access_jitter_en_reduced_freq.3970044125 |
| Short name | T943 |
| Test name | |
| Test status | |
| Simulation time | 7201283161 ps |
| CPU time | 1395.35 seconds |
| Started | Jun 29 07:40:56 PM PDT 24 |
| Finished | Jun 29 08:04:12 PM PDT 24 |
| Peak memory | 609180 kb |
| Host | smart-677a1782-a3be-4dab-8700-dd3f0a544bc1 |
| User | root |
| Command | /workspace/default/simv +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=flash_ctrl_test:1:new_rules,test_rom:0 +cdc_instrumentati on_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3970044125 - assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co verage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_flash_ctrl_access_jitter_en_reduced_freq.3970044125 |
| Directory | /workspace/0.chip_sw_flash_ctrl_access_jitter_en_reduced_freq/latest |
| Test location | /workspace/coverage/default/0.chip_sw_flash_ctrl_clock_freqs.1666071985 |
| Short name | T91 |
| Test name | |
| Test status | |
| Simulation time | 5125112168 ps |
| CPU time | 1200.52 seconds |
| Started | Jun 29 07:38:40 PM PDT 24 |
| Finished | Jun 29 07:58:42 PM PDT 24 |
| Peak memory | 607120 kb |
| Host | smart-9dcbe77b-ee42-4586-a555-989ccceb20e0 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=flash_ctrl_clock_freqs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1666071985 -assert nopostproc +UVM _TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm _log /dev/null -cm_name 0.chip_sw_flash_ctrl_clock_freqs.1666071985 |
| Directory | /workspace/0.chip_sw_flash_ctrl_clock_freqs/latest |
| Test location | /workspace/coverage/default/0.chip_sw_flash_ctrl_idle_low_power.1751378645 |
| Short name | T1059 |
| Test name | |
| Test status | |
| Simulation time | 3414222252 ps |
| CPU time | 317.49 seconds |
| Started | Jun 29 07:40:21 PM PDT 24 |
| Finished | Jun 29 07:45:39 PM PDT 24 |
| Peak memory | 607180 kb |
| Host | smart-c9ed32cf-842a-4cd4-a918-4cdb10579fa4 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=flash_ctrl_idle_low_power_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1751378645 -assert nopostproc + UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_flash_ctrl_idle_low_power.1751378645 |
| Directory | /workspace/0.chip_sw_flash_ctrl_idle_low_power/latest |
| Test location | /workspace/coverage/default/0.chip_sw_flash_ctrl_lc_rw_en.2158971671 |
| Short name | T1197 |
| Test name | |
| Test status | |
| Simulation time | 3670998814 ps |
| CPU time | 418.15 seconds |
| Started | Jun 29 07:43:05 PM PDT 24 |
| Finished | Jun 29 07:50:05 PM PDT 24 |
| Peak memory | 609176 kb |
| Host | smart-27c350f0-abf9-43ca-9561-01a4f967a43e |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=flash_ctrl_lc_rw_en_test:1:new_rules,test_rom:0 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21 58971671 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_flash_ctrl_lc_rw_en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_flash_ctrl_lc_rw_en.2158971671 |
| Directory | /workspace/0.chip_sw_flash_ctrl_lc_rw_en/latest |
| Test location | /workspace/coverage/default/0.chip_sw_flash_ctrl_mem_protection.1671303708 |
| Short name | T903 |
| Test name | |
| Test status | |
| Simulation time | 5445523480 ps |
| CPU time | 1246.04 seconds |
| Started | Jun 29 07:44:29 PM PDT 24 |
| Finished | Jun 29 08:05:18 PM PDT 24 |
| Peak memory | 609180 kb |
| Host | smart-ed192e66-4201-4c4e-8192-f733dcedcdf5 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=flash_ctrl_mem_protection_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1671303708 -assert nopostproc + UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_flash_ctrl_mem_protection.1671303708 |
| Directory | /workspace/0.chip_sw_flash_ctrl_mem_protection/latest |
| Test location | /workspace/coverage/default/0.chip_sw_flash_ctrl_ops_jitter_en.2568360854 |
| Short name | T1044 |
| Test name | |
| Test status | |
| Simulation time | 4136087118 ps |
| CPU time | 651.09 seconds |
| Started | Jun 29 07:39:02 PM PDT 24 |
| Finished | Jun 29 07:49:54 PM PDT 24 |
| Peak memory | 609168 kb |
| Host | smart-2835103a-4594-4bfd-aeea-1aee7c264d4a |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=50_000_000 +en_jitter=1 +sw_build_device=sim_dv +sw_images=flash_ctrl_ops_test:1:new_rules,test_rom:0 +cdc _instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see d=2568360854 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_flash_ctrl_ops_jitter_en.2568360854 |
| Directory | /workspace/0.chip_sw_flash_ctrl_ops_jitter_en/latest |
| Test location | /workspace/coverage/default/0.chip_sw_flash_ctrl_ops_jitter_en_reduced_freq.1754599823 |
| Short name | T314 |
| Test name | |
| Test status | |
| Simulation time | 4819507352 ps |
| CPU time | 675.99 seconds |
| Started | Jun 29 07:45:07 PM PDT 24 |
| Finished | Jun 29 07:56:23 PM PDT 24 |
| Peak memory | 609176 kb |
| Host | smart-975367fd-d2c5-4c4b-b22b-aa93643552a0 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=50_000_000 +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=flash_ctrl_ops_test:1:new_ rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si m.tcl +ntb_random_seed=1754599823 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_flash_ctrl_ops_jitter_en_reduced_freq.1754599823 |
| Directory | /workspace/0.chip_sw_flash_ctrl_ops_jitter_en_reduced_freq/latest |
| Test location | /workspace/coverage/default/0.chip_sw_flash_ctrl_write_clear.3777531631 |
| Short name | T874 |
| Test name | |
| Test status | |
| Simulation time | 3017987348 ps |
| CPU time | 353.45 seconds |
| Started | Jun 29 07:41:19 PM PDT 24 |
| Finished | Jun 29 07:47:14 PM PDT 24 |
| Peak memory | 609328 kb |
| Host | smart-006b1643-4105-42f2-8747-974316dde2b9 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=8_000_000 +sw_build_device=sim_dv +sw_images=flash_ctrl_write_clear_test:1:new_rules,test_rom:0 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3777531 631 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_flash_ctrl_write_clear.3777531631 |
| Directory | /workspace/0.chip_sw_flash_ctrl_write_clear/latest |
| Test location | /workspace/coverage/default/0.chip_sw_flash_init_reduced_freq.3379580062 |
| Short name | T211 |
| Test name | |
| Test status | |
| Simulation time | 17797443039 ps |
| CPU time | 2367.45 seconds |
| Started | Jun 29 07:38:38 PM PDT 24 |
| Finished | Jun 29 08:18:07 PM PDT 24 |
| Peak memory | 609280 kb |
| Host | smart-71470c81-c89b-4119-ad28-e48c40a79ebf |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=25_000_000 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=flash_init_test:0:test_in_rom:new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=3379580062 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_flash_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_flash_init_reduced_freq.3379580062 |
| Directory | /workspace/0.chip_sw_flash_init_reduced_freq/latest |
| Test location | /workspace/coverage/default/0.chip_sw_flash_scrambling_smoketest.2070279898 |
| Short name | T358 |
| Test name | |
| Test status | |
| Simulation time | 2479986384 ps |
| CPU time | 219.86 seconds |
| Started | Jun 29 07:44:59 PM PDT 24 |
| Finished | Jun 29 07:48:39 PM PDT 24 |
| Peak memory | 606576 kb |
| Host | smart-bd7124bc-fa7f-4a3b-ad2d-5a2c69c8a033 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=flash_scrambling_smoketest:1:new_rules,flash_scrambling_smoket est_otp_img_rma:4,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=2070279898 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_flash_scrambling_smoketest.2070279898 |
| Directory | /workspace/0.chip_sw_flash_scrambling_smoketest/latest |
| Test location | /workspace/coverage/default/0.chip_sw_gpio_smoketest.2367517508 |
| Short name | T1107 |
| Test name | |
| Test status | |
| Simulation time | 2425616139 ps |
| CPU time | 334.41 seconds |
| Started | Jun 29 07:40:35 PM PDT 24 |
| Finished | Jun 29 07:46:10 PM PDT 24 |
| Peak memory | 607612 kb |
| Host | smart-2502971d-5c57-427c-8bbf-4ac2fc6886a6 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=gpio_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2367517508 -assert nopostproc +UVM_TESTNAME=chi p_base_test +UVM_TEST_SEQ=chip_sw_gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 0.chip_sw_gpio_smoketest.2367517508 |
| Directory | /workspace/0.chip_sw_gpio_smoketest/latest |
| Test location | /workspace/coverage/default/0.chip_sw_hmac_enc_idle.3611169838 |
| Short name | T878 |
| Test name | |
| Test status | |
| Simulation time | 2924421012 ps |
| CPU time | 308.12 seconds |
| Started | Jun 29 07:39:20 PM PDT 24 |
| Finished | Jun 29 07:44:29 PM PDT 24 |
| Peak memory | 607136 kb |
| Host | smart-2f942804-748b-410a-8efa-59f01825d2d3 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=hmac_enc_idle_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3611169838 -assert nopostproc +UVM_TESTNAME =chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 0.chip_sw_hmac_enc_idle.3611169838 |
| Directory | /workspace/0.chip_sw_hmac_enc_idle/latest |
| Test location | /workspace/coverage/default/0.chip_sw_hmac_enc_jitter_en.629370739 |
| Short name | T1105 |
| Test name | |
| Test status | |
| Simulation time | 3162312712 ps |
| CPU time | 267.25 seconds |
| Started | Jun 29 07:41:25 PM PDT 24 |
| Finished | Jun 29 07:45:54 PM PDT 24 |
| Peak memory | 607512 kb |
| Host | smart-5de4399c-1528-4bdb-a744-48851f13da18 |
| User | root |
| Command | /workspace/default/simv +en_jitter=1 +sw_build_device=sim_dv +sw_images=hmac_enc_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=629370739 -assert nopostproc +UVM_T ESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l og /dev/null -cm_name 0.chip_sw_hmac_enc_jitter_en.629370739 |
| Directory | /workspace/0.chip_sw_hmac_enc_jitter_en/latest |
| Test location | /workspace/coverage/default/0.chip_sw_hmac_enc_jitter_en_reduced_freq.3872638063 |
| Short name | T986 |
| Test name | |
| Test status | |
| Simulation time | 3040875704 ps |
| CPU time | 238.03 seconds |
| Started | Jun 29 07:41:42 PM PDT 24 |
| Finished | Jun 29 07:45:41 PM PDT 24 |
| Peak memory | 609176 kb |
| Host | smart-3b7e15b7-2f28-4852-b0b9-25f1f03fc24c |
| User | root |
| Command | /workspace/default/simv +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=hmac_enc_test:1:new_rules,test_rom:0 +cdc_instrumentation _enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3872638063 -as sert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove rage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_hmac_enc_jitter_en_reduced_freq.3872638063 |
| Directory | /workspace/0.chip_sw_hmac_enc_jitter_en_reduced_freq/latest |
| Test location | /workspace/coverage/default/0.chip_sw_hmac_multistream.758434122 |
| Short name | T995 |
| Test name | |
| Test status | |
| Simulation time | 7036237496 ps |
| CPU time | 1526.92 seconds |
| Started | Jun 29 07:37:10 PM PDT 24 |
| Finished | Jun 29 08:02:37 PM PDT 24 |
| Peak memory | 607668 kb |
| Host | smart-cf755f99-dc85-46d8-8281-b94519c2aabf |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=hmac_multistream_functest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=758434122 -assert nopostproc +UVM_TE STNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo g /dev/null -cm_name 0.chip_sw_hmac_multistream.758434122 |
| Directory | /workspace/0.chip_sw_hmac_multistream/latest |
| Test location | /workspace/coverage/default/0.chip_sw_hmac_oneshot.1403068770 |
| Short name | T897 |
| Test name | |
| Test status | |
| Simulation time | 3312209086 ps |
| CPU time | 338.68 seconds |
| Started | Jun 29 07:38:59 PM PDT 24 |
| Finished | Jun 29 07:44:39 PM PDT 24 |
| Peak memory | 607152 kb |
| Host | smart-98d2c4db-9bc3-4df4-98f0-31c195248e8f |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=hmac_functest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1403068770 -assert nopostproc +UVM_TESTNAME=chip _base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_hmac_oneshot.1403068770 |
| Directory | /workspace/0.chip_sw_hmac_oneshot/latest |
| Test location | /workspace/coverage/default/0.chip_sw_hmac_smoketest.4241323295 |
| Short name | T944 |
| Test name | |
| Test status | |
| Simulation time | 3184518378 ps |
| CPU time | 379.28 seconds |
| Started | Jun 29 07:39:48 PM PDT 24 |
| Finished | Jun 29 07:46:08 PM PDT 24 |
| Peak memory | 607268 kb |
| Host | smart-ef8d7d1b-283d-4763-b876-29074b97ad4e |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=hmac_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4241323295 -assert nopostproc +UVM_TESTNAME=chi p_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul l -cm_name 0.chip_sw_hmac_smoketest.4241323295 |
| Directory | /workspace/0.chip_sw_hmac_smoketest/latest |
| Test location | /workspace/coverage/default/0.chip_sw_i2c_device_tx_rx.2162009061 |
| Short name | T192 |
| Test name | |
| Test status | |
| Simulation time | 3853609740 ps |
| CPU time | 549.65 seconds |
| Started | Jun 29 07:40:30 PM PDT 24 |
| Finished | Jun 29 07:49:42 PM PDT 24 |
| Peak memory | 609308 kb |
| Host | smart-7ce8bdd4-931c-447a-86e9-4105d85565d8 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=i2c_device_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2162009061 -assert nopostproc +UVM_TESTN AME=chip_base_test +UVM_TEST_SEQ=chip_sw_i2c_device_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v db -cm_log /dev/null -cm_name 0.chip_sw_i2c_device_tx_rx.2162009061 |
| Directory | /workspace/0.chip_sw_i2c_device_tx_rx/latest |
| Test location | /workspace/coverage/default/0.chip_sw_inject_scramble_seed.2298678643 |
| Short name | T156 |
| Test name | |
| Test status | |
| Simulation time | 65426291752 ps |
| CPU time | 12101.1 seconds |
| Started | Jun 29 07:36:42 PM PDT 24 |
| Finished | Jun 29 10:58:25 PM PDT 24 |
| Peak memory | 624044 kb |
| Host | smart-8ef28b81-e358-400a-b7fd-a283c9c0a4b5 |
| User | root |
| Command | /workspace/default/simv +lc_at_prod=1 +flash_program_latency=5 +sw_test_timeout_ns=150_000_000 +sw_build_device=sim_dv +sw_images=inject_scramble_seed :1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=2298678643 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_inject_scramble_seed_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_inject_scramble_seed.2298678643 |
| Directory | /workspace/0.chip_sw_inject_scramble_seed/latest |
| Test location | /workspace/coverage/default/0.chip_sw_keymgr_key_derivation.649210365 |
| Short name | T882 |
| Test name | |
| Test status | |
| Simulation time | 10776017798 ps |
| CPU time | 2559.64 seconds |
| Started | Jun 29 07:39:35 PM PDT 24 |
| Finished | Jun 29 08:22:16 PM PDT 24 |
| Peak memory | 615676 kb |
| Host | smart-25595526-c1d1-4063-96a7-87c1c804e09b |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=20_000_000 +sw_build_device=sim_dv +sw_images=keymgr_key_derivation_test:1:new_rules,test_rom:0 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=6492 10365 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_keymgr_key_derivation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_keymgr_key_derivation.649210365 |
| Directory | /workspace/0.chip_sw_keymgr_key_derivation/latest |
| Test location | /workspace/coverage/default/0.chip_sw_keymgr_key_derivation_jitter_en.379825390 |
| Short name | T1268 |
| Test name | |
| Test status | |
| Simulation time | 5908082911 ps |
| CPU time | 1040.76 seconds |
| Started | Jun 29 07:38:56 PM PDT 24 |
| Finished | Jun 29 07:56:17 PM PDT 24 |
| Peak memory | 615680 kb |
| Host | smart-c16bd896-cbc4-4a25-816d-3df06c1d4400 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=20_000_000 +en_jitter=1 +sw_build_device=sim_dv +sw_images=keymgr_key_derivation_test:1:new_rules,test_rom :0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=379825390 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_keymgr_key_derivation_vseq +en_cov=1 -cm line+cond+fsm+tg l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_keymgr_key_derivation_jitter_en.379825390 |
| Directory | /workspace/0.chip_sw_keymgr_key_derivation_jitter_en/latest |
| Test location | /workspace/coverage/default/0.chip_sw_keymgr_key_derivation_jitter_en_reduced_freq.1963184418 |
| Short name | T203 |
| Test name | |
| Test status | |
| Simulation time | 12006898691 ps |
| CPU time | 2341.3 seconds |
| Started | Jun 29 07:40:00 PM PDT 24 |
| Finished | Jun 29 08:19:02 PM PDT 24 |
| Peak memory | 615704 kb |
| Host | smart-5506ae03-d7ac-4321-935e-64198be01a32 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=20_000_000 +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=keymgr_key_derivation_test :1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=1963184418 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_keymgr_key_derivation_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_keymgr_key_derivation_jitter_en _reduced_freq.1963184418 |
| Directory | /workspace/0.chip_sw_keymgr_key_derivation_jitter_en_reduced_freq/latest |
| Test location | /workspace/coverage/default/0.chip_sw_keymgr_sideload_kmac.3944308569 |
| Short name | T1016 |
| Test name | |
| Test status | |
| Simulation time | 13112476104 ps |
| CPU time | 2840.2 seconds |
| Started | Jun 29 07:39:56 PM PDT 24 |
| Finished | Jun 29 08:27:17 PM PDT 24 |
| Peak memory | 609212 kb |
| Host | smart-2a359640-e391-47cb-929d-4c70d189161e |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=20_000_000 +sw_build_device=sim_dv +sw_images=keymgr_sideload_kmac_test:1:new_rules,test_rom:0 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39443 08569 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_keymgr_sideload_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_keymgr_sideload_kmac.3944308569 |
| Directory | /workspace/0.chip_sw_keymgr_sideload_kmac/latest |
| Test location | /workspace/coverage/default/0.chip_sw_kmac_app_rom.1640073339 |
| Short name | T1274 |
| Test name | |
| Test status | |
| Simulation time | 2596585384 ps |
| CPU time | 287.34 seconds |
| Started | Jun 29 07:40:05 PM PDT 24 |
| Finished | Jun 29 07:44:54 PM PDT 24 |
| Peak memory | 607132 kb |
| Host | smart-2d50f809-1ff3-4d00-b71a-866f82833912 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=kmac_app_rom_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1640073339 -assert nopostproc +UVM_TESTNAME= chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/ null -cm_name 0.chip_sw_kmac_app_rom.1640073339 |
| Directory | /workspace/0.chip_sw_kmac_app_rom/latest |
| Test location | /workspace/coverage/default/0.chip_sw_kmac_entropy.3002438006 |
| Short name | T1266 |
| Test name | |
| Test status | |
| Simulation time | 2431398098 ps |
| CPU time | 267.88 seconds |
| Started | Jun 29 07:37:52 PM PDT 24 |
| Finished | Jun 29 07:42:21 PM PDT 24 |
| Peak memory | 607364 kb |
| Host | smart-334939b9-757c-4686-87d7-94d8e445bd93 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=kmac_entropy_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3002438006 -assert nopostproc +UVM_TESTNAME= chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/ null -cm_name 0.chip_sw_kmac_entropy.3002438006 |
| Directory | /workspace/0.chip_sw_kmac_entropy/latest |
| Test location | /workspace/coverage/default/0.chip_sw_kmac_idle.2339373412 |
| Short name | T97 |
| Test name | |
| Test status | |
| Simulation time | 2716001630 ps |
| CPU time | 333.07 seconds |
| Started | Jun 29 07:40:08 PM PDT 24 |
| Finished | Jun 29 07:45:42 PM PDT 24 |
| Peak memory | 607132 kb |
| Host | smart-9ccfdd2a-3929-403c-9dc2-8e7a03a76d3c |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=kmac_idle_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2339373412 -assert nopostproc +UVM_TESTNAME=chi p_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul l -cm_name 0.chip_sw_kmac_idle.2339373412 |
| Directory | /workspace/0.chip_sw_kmac_idle/latest |
| Test location | /workspace/coverage/default/0.chip_sw_kmac_mode_cshake.1466880381 |
| Short name | T1273 |
| Test name | |
| Test status | |
| Simulation time | 2674970460 ps |
| CPU time | 257.28 seconds |
| Started | Jun 29 07:39:30 PM PDT 24 |
| Finished | Jun 29 07:43:48 PM PDT 24 |
| Peak memory | 609172 kb |
| Host | smart-d5520c06-06da-406f-ac02-86dec9b4322f |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=kmac_mode_cshake_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1466880381 -assert nopostproc +UVM_TESTN AME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log / dev/null -cm_name 0.chip_sw_kmac_mode_cshake.1466880381 |
| Directory | /workspace/0.chip_sw_kmac_mode_cshake/latest |
| Test location | /workspace/coverage/default/0.chip_sw_kmac_mode_kmac.2716767015 |
| Short name | T1106 |
| Test name | |
| Test status | |
| Simulation time | 3024240880 ps |
| CPU time | 349.93 seconds |
| Started | Jun 29 07:39:32 PM PDT 24 |
| Finished | Jun 29 07:45:22 PM PDT 24 |
| Peak memory | 609168 kb |
| Host | smart-e664fe9b-a62f-4ac8-a416-7b0497e6fe04 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=kmac_mode_kmac_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2716767015 -assert nopostproc +UVM_TESTNAM E=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 0.chip_sw_kmac_mode_kmac.2716767015 |
| Directory | /workspace/0.chip_sw_kmac_mode_kmac/latest |
| Test location | /workspace/coverage/default/0.chip_sw_kmac_mode_kmac_jitter_en.1590226901 |
| Short name | T1115 |
| Test name | |
| Test status | |
| Simulation time | 3062065064 ps |
| CPU time | 263.22 seconds |
| Started | Jun 29 07:38:52 PM PDT 24 |
| Finished | Jun 29 07:43:16 PM PDT 24 |
| Peak memory | 607112 kb |
| Host | smart-8abfaad5-2aac-4741-bc14-53da55daa42c |
| User | root |
| Command | /workspace/default/simv +en_jitter=1 +sw_build_device=sim_dv +sw_images=kmac_mode_kmac_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1590226901 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd b -cm_log /dev/null -cm_name 0.chip_sw_kmac_mode_kmac_jitter_en.1590226901 |
| Directory | /workspace/0.chip_sw_kmac_mode_kmac_jitter_en/latest |
| Test location | /workspace/coverage/default/0.chip_sw_kmac_mode_kmac_jitter_en_reduced_freq.599843208 |
| Short name | T1229 |
| Test name | |
| Test status | |
| Simulation time | 3132097111 ps |
| CPU time | 347.41 seconds |
| Started | Jun 29 07:44:04 PM PDT 24 |
| Finished | Jun 29 07:49:52 PM PDT 24 |
| Peak memory | 609172 kb |
| Host | smart-a06263dd-8fd3-4cb4-9903-9b893c8de704 |
| User | root |
| Command | /workspace/default/simv +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=kmac_mode_kmac_test:1:new_rules,test_rom:0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59984320 8 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace /coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_kmac_mode_kmac_jitter_en_reduced_freq.599843208 |
| Directory | /workspace/0.chip_sw_kmac_mode_kmac_jitter_en_reduced_freq/latest |
| Test location | /workspace/coverage/default/0.chip_sw_kmac_smoketest.2707397030 |
| Short name | T933 |
| Test name | |
| Test status | |
| Simulation time | 2749845824 ps |
| CPU time | 280.71 seconds |
| Started | Jun 29 07:39:13 PM PDT 24 |
| Finished | Jun 29 07:43:54 PM PDT 24 |
| Peak memory | 607144 kb |
| Host | smart-0860cf20-bddf-4971-9a18-29bd6690de1c |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=kmac_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2707397030 -assert nopostproc +UVM_TESTNAME=chi p_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul l -cm_name 0.chip_sw_kmac_smoketest.2707397030 |
| Directory | /workspace/0.chip_sw_kmac_smoketest/latest |
| Test location | /workspace/coverage/default/0.chip_sw_lc_ctrl_otp_hw_cfg0.129006489 |
| Short name | T1095 |
| Test name | |
| Test status | |
| Simulation time | 2972641882 ps |
| CPU time | 255.42 seconds |
| Started | Jun 29 07:45:11 PM PDT 24 |
| Finished | Jun 29 07:49:29 PM PDT 24 |
| Peak memory | 609180 kb |
| Host | smart-28915d96-9a8b-4aac-97fd-d7437770ea0d |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=lc_ctrl_otp_hw_cfg0_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=129006489 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_lc_ctrl_otp_hw_cfg0.129006489 |
| Directory | /workspace/0.chip_sw_lc_ctrl_otp_hw_cfg0/latest |
| Test location | /workspace/coverage/default/0.chip_sw_lc_ctrl_rand_to_scrap.3026776410 |
| Short name | T114 |
| Test name | |
| Test status | |
| Simulation time | 2994801755 ps |
| CPU time | 157.7 seconds |
| Started | Jun 29 07:39:29 PM PDT 24 |
| Finished | Jun 29 07:42:07 PM PDT 24 |
| Peak memory | 617592 kb |
| Host | smart-6170d238-3e42-4496-84a8-d38f39e92229 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=lc_ctrl_scrap_test:1:new_rules,test_rom:0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30267764 10 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_scrap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_lc_ctrl_rand_to_scrap.3026776410 |
| Directory | /workspace/0.chip_sw_lc_ctrl_rand_to_scrap/latest |
| Test location | /workspace/coverage/default/0.chip_sw_lc_ctrl_raw_to_scrap.2391048701 |
| Short name | T182 |
| Test name | |
| Test status | |
| Simulation time | 3255445239 ps |
| CPU time | 130.04 seconds |
| Started | Jun 29 07:38:43 PM PDT 24 |
| Finished | Jun 29 07:40:54 PM PDT 24 |
| Peak memory | 617584 kb |
| Host | smart-38ac818f-3a16-4e10-a0b0-824a6eb71155 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +src_dec_state=DecLcStRaw +sw_build_device=sim_dv +sw_images=lc_ctrl_scrap_test:1:new_rules ,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2391048701 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_scrap_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_lc_ctrl_raw_to_scrap.2391048701 |
| Directory | /workspace/0.chip_sw_lc_ctrl_raw_to_scrap/latest |
| Test location | /workspace/coverage/default/0.chip_sw_lc_ctrl_rma_to_scrap.1163614027 |
| Short name | T1272 |
| Test name | |
| Test status | |
| Simulation time | 2808985984 ps |
| CPU time | 211.22 seconds |
| Started | Jun 29 07:42:57 PM PDT 24 |
| Finished | Jun 29 07:46:30 PM PDT 24 |
| Peak memory | 618060 kb |
| Host | smart-d2dce9cf-ce8d-4c9e-b5f7-a11e60ffa41d |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +src_dec_state=DecLcStRma +sw_build_device=sim_dv +sw_images=lc_ctrl_scrap_test:1:new_rules ,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1163614027 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_scrap_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_lc_ctrl_rma_to_scrap.1163614027 |
| Directory | /workspace/0.chip_sw_lc_ctrl_rma_to_scrap/latest |
| Test location | /workspace/coverage/default/0.chip_sw_lc_ctrl_transition.761907533 |
| Short name | T1155 |
| Test name | |
| Test status | |
| Simulation time | 5141288893 ps |
| CPU time | 662.05 seconds |
| Started | Jun 29 07:43:30 PM PDT 24 |
| Finished | Jun 29 07:54:33 PM PDT 24 |
| Peak memory | 619244 kb |
| Host | smart-9f7967eb-57e8-42af-9dd5-3d7028872645 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=lc_ctrl_transition_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=761907533 -assert nopostproc +UVM_TEST NAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_transition_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul t.vdb -cm_log /dev/null -cm_name 0.chip_sw_lc_ctrl_transition.761907533 |
| Directory | /workspace/0.chip_sw_lc_ctrl_transition/latest |
| Test location | /workspace/coverage/default/0.chip_sw_lc_ctrl_volatile_raw_unlock.2424001443 |
| Short name | T1161 |
| Test name | |
| Test status | |
| Simulation time | 3073250934 ps |
| CPU time | 125.01 seconds |
| Started | Jun 29 07:38:59 PM PDT 24 |
| Finished | Jun 29 07:41:04 PM PDT 24 |
| Peak memory | 615968 kb |
| Host | smart-76b82ca0-eed6-41f6-b549-f76cb21100b0 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStRaw +exp_volatile_raw_unlock_en=0 +sw_build_device=sim_dv +sw_images=lc_ctrl_volatile_raw_unlock_tes t:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/ tools/sim.tcl +ntb_random_seed=2424001443 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_volatile_raw_unlock_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_lc_ctrl_volatile_raw_unlock.2424001443 |
| Directory | /workspace/0.chip_sw_lc_ctrl_volatile_raw_unlock/latest |
| Test location | /workspace/coverage/default/0.chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz.2093143678 |
| Short name | T113 |
| Test name | |
| Test status | |
| Simulation time | 2207087604 ps |
| CPU time | 116.91 seconds |
| Started | Jun 29 07:39:08 PM PDT 24 |
| Finished | Jun 29 07:41:06 PM PDT 24 |
| Peak memory | 614408 kb |
| Host | smart-ee9d49ec-241b-4a96-8b42-058ba323fa1e |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStRaw +chip_clock_source=ChipClockSourceExternal48Mhz +exp_volatile_raw_unlock_en=0 +sw_build_device=s im_dv +sw_images=lc_ctrl_volatile_raw_unlock_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2093143678 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TES T_SEQ=chip_sw_lc_volatile_raw_unlock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz.2093143678 |
| Directory | /workspace/0.chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz/latest |
| Test location | /workspace/coverage/default/0.chip_sw_lc_walkthrough_prod.2993191961 |
| Short name | T216 |
| Test name | |
| Test status | |
| Simulation time | 47992962734 ps |
| CPU time | 6258.19 seconds |
| Started | Jun 29 07:41:44 PM PDT 24 |
| Finished | Jun 29 09:26:05 PM PDT 24 |
| Peak memory | 615004 kb |
| Host | smart-e1cdbfb5-f14f-4849-9417-7e13a1cbb6c7 |
| User | root |
| Command | /workspace/default/simv +flash_program_latency=5 +use_otp_image=OtpTypeLcStRaw +dest_dec_state=DecLcStProd +sw_test_timeout_ns=200_000_000 +sw_build_d evice=sim_dv +sw_images=lc_walkthrough_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2993191961 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ= chip_sw_lc_walkthrough_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chi p_sw_lc_walkthrough_prod.2993191961 |
| Directory | /workspace/0.chip_sw_lc_walkthrough_prod/latest |
| Test location | /workspace/coverage/default/0.chip_sw_lc_walkthrough_prodend.2101674328 |
| Short name | T901 |
| Test name | |
| Test status | |
| Simulation time | 8066858137 ps |
| CPU time | 874.46 seconds |
| Started | Jun 29 07:39:00 PM PDT 24 |
| Finished | Jun 29 07:53:35 PM PDT 24 |
| Peak memory | 617936 kb |
| Host | smart-a9d06adf-506d-4716-8c9d-081a7071bee9 |
| User | root |
| Command | /workspace/default/simv +flash_program_latency=5 +use_otp_image=OtpTypeLcStRaw +dest_dec_state=DecLcStProdEnd +sw_build_device=sim_dv +sw_images=lc_wa lkthrough_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2101674328 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_walkthrough_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_lc_walkthrough_prodend.2101674328 |
| Directory | /workspace/0.chip_sw_lc_walkthrough_prodend/latest |
| Test location | /workspace/coverage/default/0.chip_sw_lc_walkthrough_rma.3360125725 |
| Short name | T1008 |
| Test name | |
| Test status | |
| Simulation time | 46643563464 ps |
| CPU time | 5971.71 seconds |
| Started | Jun 29 07:40:41 PM PDT 24 |
| Finished | Jun 29 09:20:14 PM PDT 24 |
| Peak memory | 615012 kb |
| Host | smart-5b4d536e-d4de-470c-92ec-f1c1918fb52b |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStRaw +dest_dec_state=DecLcStRma +flash_program_latency=5 +sw_test_timeout_ns=200_000_000 +sw_build_de vice=sim_dv +sw_images=lc_walkthrough_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3360125725 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=c hip_sw_lc_walkthrough_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip _sw_lc_walkthrough_rma.3360125725 |
| Directory | /workspace/0.chip_sw_lc_walkthrough_rma/latest |
| Test location | /workspace/coverage/default/0.chip_sw_lc_walkthrough_testunlocks.3871846100 |
| Short name | T929 |
| Test name | |
| Test status | |
| Simulation time | 27434217173 ps |
| CPU time | 2804.95 seconds |
| Started | Jun 29 07:37:57 PM PDT 24 |
| Finished | Jun 29 08:24:43 PM PDT 24 |
| Peak memory | 614888 kb |
| Host | smart-c1689254-038a-4cb0-b22b-3768e4b03a72 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStRaw +dest_dec_state=DecLcStTestUnlock7 +sw_build_device=sim_dv +sw_images=lc_walkthrough_testunlocks _test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=3871846100 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_walkthrough_testunlocks_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_lc_walkthrough_testun locks.3871846100 |
| Directory | /workspace/0.chip_sw_lc_walkthrough_testunlocks/latest |
| Test location | /workspace/coverage/default/0.chip_sw_otbn_ecdsa_op_irq.2653289700 |
| Short name | T861 |
| Test name | |
| Test status | |
| Simulation time | 17225754750 ps |
| CPU time | 4292.56 seconds |
| Started | Jun 29 07:39:21 PM PDT 24 |
| Finished | Jun 29 08:50:55 PM PDT 24 |
| Peak memory | 608144 kb |
| Host | smart-edea14a5-a504-4816-a86a-d2bd36e991d9 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=28_000_000 +rng_srate_value=30 +sw_build_device=sim_dv +sw_images=otbn_ecdsa_op_irq_test:1:new_rules,test_ rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ random_seed=2653289700 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_otbn_ecdsa_op_irq.2653289700 |
| Directory | /workspace/0.chip_sw_otbn_ecdsa_op_irq/latest |
| Test location | /workspace/coverage/default/0.chip_sw_otbn_ecdsa_op_irq_jitter_en.2001316202 |
| Short name | T165 |
| Test name | |
| Test status | |
| Simulation time | 18083055798 ps |
| CPU time | 4574.01 seconds |
| Started | Jun 29 07:37:55 PM PDT 24 |
| Finished | Jun 29 08:54:10 PM PDT 24 |
| Peak memory | 609312 kb |
| Host | smart-9950dc8e-2368-464d-8cf2-349d655784af |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=33_000_000 +rng_srate_value=30 +en_jitter=1 +sw_build_device=sim_dv +sw_images=otbn_ecdsa_op_irq_test:1:ne w_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/ sim.tcl +ntb_random_seed=2001316202 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tg l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_otbn_ecdsa_op_irq_jitter_en.2001316202 |
| Directory | /workspace/0.chip_sw_otbn_ecdsa_op_irq_jitter_en/latest |
| Test location | /workspace/coverage/default/0.chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq.243203174 |
| Short name | T1230 |
| Test name | |
| Test status | |
| Simulation time | 25233711732 ps |
| CPU time | 4313.36 seconds |
| Started | Jun 29 07:40:23 PM PDT 24 |
| Finished | Jun 29 08:52:18 PM PDT 24 |
| Peak memory | 609312 kb |
| Host | smart-756256b2-4fc4-42cd-ab3f-edbc08eff853 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=33_000_000 +rng_srate_value=30 +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=otbn_e cdsa_op_irq_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/ repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=243203174 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_otbn_ecdsa_op_irq_jitter_en_reduc ed_freq.243203174 |
| Directory | /workspace/0.chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq/latest |
| Test location | /workspace/coverage/default/0.chip_sw_otbn_mem_scramble.843500530 |
| Short name | T253 |
| Test name | |
| Test status | |
| Simulation time | 4060721218 ps |
| CPU time | 446.87 seconds |
| Started | Jun 29 07:39:55 PM PDT 24 |
| Finished | Jun 29 07:47:23 PM PDT 24 |
| Peak memory | 609180 kb |
| Host | smart-82b4475a-5bf5-4e01-a3e0-87a73dcf4b82 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=15_000_000 +en_scb_tl_err_chk=0 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=otbn _mem_scramble_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=843500530 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_otbn_mem_scramble.843500530 |
| Directory | /workspace/0.chip_sw_otbn_mem_scramble/latest |
| Test location | /workspace/coverage/default/0.chip_sw_otbn_randomness.4143959177 |
| Short name | T1104 |
| Test name | |
| Test status | |
| Simulation time | 6284150732 ps |
| CPU time | 1024.16 seconds |
| Started | Jun 29 07:40:14 PM PDT 24 |
| Finished | Jun 29 07:57:18 PM PDT 24 |
| Peak memory | 607332 kb |
| Host | smart-a25c8ce6-3e5c-48f0-a454-68ee5b9a49cc |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +rng_srate_value=30 +sw_build_device=sim_dv +sw_images=otbn_randomness_test:1:new_rules,test_ro m:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=4143959177 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_otbn_randomness.4143959177 |
| Directory | /workspace/0.chip_sw_otbn_randomness/latest |
| Test location | /workspace/coverage/default/0.chip_sw_otbn_smoketest.758050859 |
| Short name | T1228 |
| Test name | |
| Test status | |
| Simulation time | 10901144176 ps |
| CPU time | 2288.63 seconds |
| Started | Jun 29 07:38:28 PM PDT 24 |
| Finished | Jun 29 08:16:37 PM PDT 24 |
| Peak memory | 607772 kb |
| Host | smart-14eb92a4-5ec9-49f9-9ec6-8d7868d3a554 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=otbn_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=758050859 -assert nopostproc +UVM_TESTNAME=chip _base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_otbn_smoketest.758050859 |
| Directory | /workspace/0.chip_sw_otbn_smoketest/latest |
| Test location | /workspace/coverage/default/0.chip_sw_otp_ctrl_dai_lock.2792991864 |
| Short name | T1254 |
| Test name | |
| Test status | |
| Simulation time | 27931365864 ps |
| CPU time | 5410.32 seconds |
| Started | Jun 29 07:46:50 PM PDT 24 |
| Finished | Jun 29 09:17:02 PM PDT 24 |
| Peak memory | 609188 kb |
| Host | smart-721efcaa-be64-4bf0-bde2-81515268b700 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=30_000_000 +sw_build_device=sim_dv +sw_images=otp_ctrl_mem_access_test:1:new_rules,test_rom:0 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=279299 1864 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_otp_ctrl_dai_lock.2792991864 |
| Directory | /workspace/0.chip_sw_otp_ctrl_dai_lock/latest |
| Test location | /workspace/coverage/default/0.chip_sw_otp_ctrl_ecc_error_vendor_test.3980915274 |
| Short name | T1190 |
| Test name | |
| Test status | |
| Simulation time | 3458343480 ps |
| CPU time | 341.13 seconds |
| Started | Jun 29 07:38:12 PM PDT 24 |
| Finished | Jun 29 07:43:54 PM PDT 24 |
| Peak memory | 609132 kb |
| Host | smart-f160e55e-d970-4abb-b45f-7e88e99ad085 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=otp_ctrl_vendor_test_ecc_error_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3980915274 -assert nopostp roc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_otp_ctrl_vendor_test_ecc_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_otp_ctrl_ecc_error_vendor_test.3980915274 |
| Directory | /workspace/0.chip_sw_otp_ctrl_ecc_error_vendor_test/latest |
| Test location | /workspace/coverage/default/0.chip_sw_otp_ctrl_lc_signals_dev.4039517756 |
| Short name | T855 |
| Test name | |
| Test status | |
| Simulation time | 6569385896 ps |
| CPU time | 1269.59 seconds |
| Started | Jun 29 07:39:06 PM PDT 24 |
| Finished | Jun 29 08:00:17 PM PDT 24 |
| Peak memory | 608216 kb |
| Host | smart-7265a7ab-0b8c-4c6d-a27a-a52d23f338d5 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStDev +otp_clear_secret2=1 +sw_build_device=sim_dv +sw_images=otp_ctrl_lc_signals_test:1:new_rules,tes t_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +nt b_random_seed=4039517756 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_otp_ctrl_lc_signals_dev.4039517756 |
| Directory | /workspace/0.chip_sw_otp_ctrl_lc_signals_dev/latest |
| Test location | /workspace/coverage/default/0.chip_sw_otp_ctrl_lc_signals_prod.1376740253 |
| Short name | T875 |
| Test name | |
| Test status | |
| Simulation time | 8591743170 ps |
| CPU time | 1208.16 seconds |
| Started | Jun 29 07:39:42 PM PDT 24 |
| Finished | Jun 29 07:59:51 PM PDT 24 |
| Peak memory | 609180 kb |
| Host | smart-8eb5f8dc-9cd8-4d86-95c4-8b389562a40e |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStProd +otp_clear_secret2=1 +sw_build_device=sim_dv +sw_images=otp_ctrl_lc_signals_test:1:new_rules,te st_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n tb_random_seed=1376740253 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_otp_ctrl_lc_signals_prod.1376740253 |
| Directory | /workspace/0.chip_sw_otp_ctrl_lc_signals_prod/latest |
| Test location | /workspace/coverage/default/0.chip_sw_otp_ctrl_lc_signals_rma.490259674 |
| Short name | T918 |
| Test name | |
| Test status | |
| Simulation time | 8655173892 ps |
| CPU time | 1109.77 seconds |
| Started | Jun 29 07:39:42 PM PDT 24 |
| Finished | Jun 29 07:58:13 PM PDT 24 |
| Peak memory | 608208 kb |
| Host | smart-5a1568f9-4e3b-4564-9eb1-fffcc2e32300 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStRma +otp_clear_secret2=1 +sw_build_device=sim_dv +sw_images=otp_ctrl_lc_signals_test:1:new_rules,tes t_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +nt b_random_seed=490259674 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_otp_ctrl_lc_signals_rma.490259674 |
| Directory | /workspace/0.chip_sw_otp_ctrl_lc_signals_rma/latest |
| Test location | /workspace/coverage/default/0.chip_sw_otp_ctrl_lc_signals_test_unlocked0.872759936 |
| Short name | T970 |
| Test name | |
| Test status | |
| Simulation time | 4017430256 ps |
| CPU time | 734.7 seconds |
| Started | Jun 29 07:38:40 PM PDT 24 |
| Finished | Jun 29 07:50:56 PM PDT 24 |
| Peak memory | 609164 kb |
| Host | smart-4ff585e1-6b7f-4bcc-89ed-7fcf9a0705ad |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStTestUnlocked0 +otp_clear_secret2=1 +sw_build_device=sim_dv +sw_images=otp_ctrl_lc_signals_test:1:new _rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/s im.tcl +ntb_random_seed=872759936 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_otp_ctrl_lc_signals_test_unlocked0.872759936 |
| Directory | /workspace/0.chip_sw_otp_ctrl_lc_signals_test_unlocked0/latest |
| Test location | /workspace/coverage/default/0.chip_sw_otp_ctrl_smoketest.1223804314 |
| Short name | T87 |
| Test name | |
| Test status | |
| Simulation time | 2834990964 ps |
| CPU time | 258.51 seconds |
| Started | Jun 29 07:44:04 PM PDT 24 |
| Finished | Jun 29 07:48:22 PM PDT 24 |
| Peak memory | 609188 kb |
| Host | smart-a82fa862-06bd-4db3-857c-704793977956 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=otp_ctrl_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1223804314 -assert nopostproc +UVM_TESTNAME =chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 0.chip_sw_otp_ctrl_smoketest.1223804314 |
| Directory | /workspace/0.chip_sw_otp_ctrl_smoketest/latest |
| Test location | /workspace/coverage/default/0.chip_sw_power_idle_load.2836927375 |
| Short name | T138 |
| Test name | |
| Test status | |
| Simulation time | 4117371816 ps |
| CPU time | 727.87 seconds |
| Started | Jun 29 07:41:23 PM PDT 24 |
| Finished | Jun 29 07:53:32 PM PDT 24 |
| Peak memory | 608156 kb |
| Host | smart-f596fb90-ee58-4d3b-976a-235b14d95fba |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=chip_power_idle_load:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2836927375 -assert nopostproc +UVM_TESTNA ME=chip_base_test +UVM_TEST_SEQ=chip_sw_power_idle_load_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_power_idle_load.2836927375 |
| Directory | /workspace/0.chip_sw_power_idle_load/latest |
| Test location | /workspace/coverage/default/0.chip_sw_pwrmgr_all_reset_reqs.726939500 |
| Short name | T311 |
| Test name | |
| Test status | |
| Simulation time | 10838312930 ps |
| CPU time | 1884.39 seconds |
| Started | Jun 29 07:40:48 PM PDT 24 |
| Finished | Jun 29 08:12:13 PM PDT 24 |
| Peak memory | 609288 kb |
| Host | smart-ed042db8-8b63-4ec1-bd0d-b346bba179e1 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=50_000_000 +sw_build_device=sim_dv +sw_images=pwrmgr_all_reset_reqs_test:1:new_rules,test_rom:0 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=7269 39500 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_deep_sleep_all_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_all_reset_reqs.726939500 |
| Directory | /workspace/0.chip_sw_pwrmgr_all_reset_reqs/latest |
| Test location | /workspace/coverage/default/0.chip_sw_pwrmgr_b2b_sleep_reset_req.395317669 |
| Short name | T1056 |
| Test name | |
| Test status | |
| Simulation time | 30140989708 ps |
| CPU time | 2751.98 seconds |
| Started | Jun 29 07:40:03 PM PDT 24 |
| Finished | Jun 29 08:25:56 PM PDT 24 |
| Peak memory | 607556 kb |
| Host | smart-f76a9bd8-816d-4dc2-8753-2cd49ba8d5c0 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=35_000_000 +sw_build_device=sim_dv +sw_images=pwrmgr_b2b_sleep_reset_test:1:new_rules,test_rom:0 +cdc_inst rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=395 317669 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_repeat_reset_wkup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_b2b_sleep_reset_req.395317669 |
| Directory | /workspace/0.chip_sw_pwrmgr_b2b_sleep_reset_req/latest |
| Test location | /workspace/coverage/default/0.chip_sw_pwrmgr_deep_sleep_all_reset_reqs.2269262958 |
| Short name | T982 |
| Test name | |
| Test status | |
| Simulation time | 14780624280 ps |
| CPU time | 1309.44 seconds |
| Started | Jun 29 07:40:04 PM PDT 24 |
| Finished | Jun 29 08:01:54 PM PDT 24 |
| Peak memory | 609316 kb |
| Host | smart-3cc2b7d9-4aab-4d85-9b9e-b0ab36566538 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=50_000_000 +sw_build_device=sim_dv +sw_images=pwrmgr_deep_sleep_all_reset_reqs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=2269262958 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_deep_sleep_all_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_deep_sleep_all_reset_reqs.2269262958 |
| Directory | /workspace/0.chip_sw_pwrmgr_deep_sleep_all_reset_reqs/latest |
| Test location | /workspace/coverage/default/0.chip_sw_pwrmgr_deep_sleep_all_wake_ups.3356831797 |
| Short name | T95 |
| Test name | |
| Test status | |
| Simulation time | 25577021710 ps |
| CPU time | 1582.88 seconds |
| Started | Jun 29 07:39:53 PM PDT 24 |
| Finished | Jun 29 08:06:17 PM PDT 24 |
| Peak memory | 608716 kb |
| Host | smart-fc533f5e-7eed-405c-94db-4872e7ca3965 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=pwrmgr_deep_sleep_all_wake_ups:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 3356831797 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_pwrmgr_deep_sleep_all_wake_ups_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_deep_sleep_all_wake_ups.3356831797 |
| Directory | /workspace/0.chip_sw_pwrmgr_deep_sleep_all_wake_ups/latest |
| Test location | /workspace/coverage/default/0.chip_sw_pwrmgr_deep_sleep_por_reset.669940080 |
| Short name | T17 |
| Test name | |
| Test status | |
| Simulation time | 8097382616 ps |
| CPU time | 573.87 seconds |
| Started | Jun 29 07:40:05 PM PDT 24 |
| Finished | Jun 29 07:49:39 PM PDT 24 |
| Peak memory | 609244 kb |
| Host | smart-a92c3660-fe49-4ce8-ad60-4fca81662fe9 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_deep_sleep_por_reset_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=669940080 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sleep_por_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/ default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_deep_sleep_por_reset.669940080 |
| Directory | /workspace/0.chip_sw_pwrmgr_deep_sleep_por_reset/latest |
| Test location | /workspace/coverage/default/0.chip_sw_pwrmgr_deep_sleep_power_glitch_reset.1403246477 |
| Short name | T1015 |
| Test name | |
| Test status | |
| Simulation time | 6851287552 ps |
| CPU time | 455.53 seconds |
| Started | Jun 29 07:38:43 PM PDT 24 |
| Finished | Jun 29 07:46:19 PM PDT 24 |
| Peak memory | 614128 kb |
| Host | smart-1c324a20-dd70-41ea-9bc2-db9f0ad4dc6f |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=pwrmgr_deep_sleep_power_glitch_test:1:new_rules,test_rom :0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=1403246477 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_deep_power_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_deep_sleep_power_glitch_reset.1403246477 |
| Directory | /workspace/0.chip_sw_pwrmgr_deep_sleep_power_glitch_reset/latest |
| Test location | /workspace/coverage/default/0.chip_sw_pwrmgr_main_power_glitch_reset.3913627128 |
| Short name | T1069 |
| Test name | |
| Test status | |
| Simulation time | 4480852112 ps |
| CPU time | 512.6 seconds |
| Started | Jun 29 07:38:40 PM PDT 24 |
| Finished | Jun 29 07:47:13 PM PDT 24 |
| Peak memory | 615024 kb |
| Host | smart-806f62ea-c710-4736-90e0-7e417d0838fe |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=pwrmgr_main_power_glitch_test:1:new_rules,test_rom:0 +cd c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se ed=3913627128 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_main_power_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_main_power_glitch_reset.3913627128 |
| Directory | /workspace/0.chip_sw_pwrmgr_main_power_glitch_reset/latest |
| Test location | /workspace/coverage/default/0.chip_sw_pwrmgr_normal_sleep_all_wake_ups.2075138467 |
| Short name | T411 |
| Test name | |
| Test status | |
| Simulation time | 6720760380 ps |
| CPU time | 387.41 seconds |
| Started | Jun 29 07:39:45 PM PDT 24 |
| Finished | Jun 29 07:46:13 PM PDT 24 |
| Peak memory | 608204 kb |
| Host | smart-31cbeee4-3cab-492d-a62b-a13986a6d2d2 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_normal_sleep_all_wake_ups:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2075138467 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_pwrmgr_deep_sleep_all_wake_ups_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_normal_sleep_all_wake_ups.2075138467 |
| Directory | /workspace/0.chip_sw_pwrmgr_normal_sleep_all_wake_ups/latest |
| Test location | /workspace/coverage/default/0.chip_sw_pwrmgr_normal_sleep_por_reset.188489120 |
| Short name | T1170 |
| Test name | |
| Test status | |
| Simulation time | 7112208650 ps |
| CPU time | 527.51 seconds |
| Started | Jun 29 07:36:58 PM PDT 24 |
| Finished | Jun 29 07:45:46 PM PDT 24 |
| Peak memory | 609232 kb |
| Host | smart-53620c7c-975e-4130-a225-92151044a8ea |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_normal_sleep_por_reset_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=188489120 -assert nopostpro c +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sleep_por_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag e/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_normal_sleep_por_reset.188489120 |
| Directory | /workspace/0.chip_sw_pwrmgr_normal_sleep_por_reset/latest |
| Test location | /workspace/coverage/default/0.chip_sw_pwrmgr_random_sleep_all_reset_reqs.3679366753 |
| Short name | T1143 |
| Test name | |
| Test status | |
| Simulation time | 21905259293 ps |
| CPU time | 2279.74 seconds |
| Started | Jun 29 07:38:56 PM PDT 24 |
| Finished | Jun 29 08:16:56 PM PDT 24 |
| Peak memory | 609376 kb |
| Host | smart-43dc6d91-dbe7-437f-92fa-7ae24825d6ec |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=50_000_000 +sw_build_device=sim_dv +sw_images=pwrmgr_random_sleep_all_reset_reqs_test:1:new_rules,test_rom :0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=3679366753 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_deep_sleep_all_reset_vseq +en_cov=1 -cm line+cond+fsm+tg l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_random_sleep_all_reset_reqs.3679366753 |
| Directory | /workspace/0.chip_sw_pwrmgr_random_sleep_all_reset_reqs/latest |
| Test location | /workspace/coverage/default/0.chip_sw_pwrmgr_sleep_disabled.2934952865 |
| Short name | T659 |
| Test name | |
| Test status | |
| Simulation time | 3229153106 ps |
| CPU time | 229.7 seconds |
| Started | Jun 29 07:38:38 PM PDT 24 |
| Finished | Jun 29 07:42:28 PM PDT 24 |
| Peak memory | 609204 kb |
| Host | smart-e11a8732-f759-40e7-a319-d018340c5dbc |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_sleep_disabled_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2934952865 -assert nopostproc +UVM_ TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_ log /dev/null -cm_name 0.chip_sw_pwrmgr_sleep_disabled.2934952865 |
| Directory | /workspace/0.chip_sw_pwrmgr_sleep_disabled/latest |
| Test location | /workspace/coverage/default/0.chip_sw_pwrmgr_sleep_power_glitch_reset.3547666238 |
| Short name | T1043 |
| Test name | |
| Test status | |
| Simulation time | 5081385640 ps |
| CPU time | 480.94 seconds |
| Started | Jun 29 07:38:36 PM PDT 24 |
| Finished | Jun 29 07:46:38 PM PDT 24 |
| Peak memory | 615016 kb |
| Host | smart-bd6d8d0a-a829-475c-9c7c-c0930b38d201 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=pwrmgr_sleep_power_glitch_test:1:new_rules,test_rom:0 +c dc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_s eed=3547666238 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_main_power_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_sleep_power_glitch_reset.3547666238 |
| Directory | /workspace/0.chip_sw_pwrmgr_sleep_power_glitch_reset/latest |
| Test location | /workspace/coverage/default/0.chip_sw_pwrmgr_sleep_wake_5_bug.400136965 |
| Short name | T883 |
| Test name | |
| Test status | |
| Simulation time | 7629716480 ps |
| CPU time | 550.95 seconds |
| Started | Jun 29 07:40:13 PM PDT 24 |
| Finished | Jun 29 07:49:24 PM PDT 24 |
| Peak memory | 609264 kb |
| Host | smart-66a53ccf-28b1-4601-aa45-a5ec51407ecf |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +do_random=1 +sw_build_device=sim_dv +sw_images=pwrmgr_sleep_wake_5_bug_test:1:new_rules,test_r om:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r andom_seed=400136965 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_sleep_wake_5_bug.400136965 |
| Directory | /workspace/0.chip_sw_pwrmgr_sleep_wake_5_bug/latest |
| Test location | /workspace/coverage/default/0.chip_sw_pwrmgr_smoketest.3770520584 |
| Short name | T1013 |
| Test name | |
| Test status | |
| Simulation time | 6595274848 ps |
| CPU time | 484.33 seconds |
| Started | Jun 29 07:41:05 PM PDT 24 |
| Finished | Jun 29 07:49:09 PM PDT 24 |
| Peak memory | 609224 kb |
| Host | smart-0d051577-985c-4468-9a71-26325f07bdc8 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=10000000 +sw_build_device=sim_dv +sw_images=pwrmgr_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3770520584 -asse rt nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera ge/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_smoketest.3770520584 |
| Directory | /workspace/0.chip_sw_pwrmgr_smoketest/latest |
| Test location | /workspace/coverage/default/0.chip_sw_pwrmgr_sysrst_ctrl_reset.4269837005 |
| Short name | T885 |
| Test name | |
| Test status | |
| Simulation time | 7558273227 ps |
| CPU time | 1309.39 seconds |
| Started | Jun 29 07:39:07 PM PDT 24 |
| Finished | Jun 29 08:00:57 PM PDT 24 |
| Peak memory | 608160 kb |
| Host | smart-2252e51c-81e9-482e-ac36-83df8b147ca0 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_sysrst_ctrl_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4269837005 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_sysrst_ctrl_reset.4269837005 |
| Directory | /workspace/0.chip_sw_pwrmgr_sysrst_ctrl_reset/latest |
| Test location | /workspace/coverage/default/0.chip_sw_pwrmgr_usb_clk_disabled_when_active.1532322759 |
| Short name | T147 |
| Test name | |
| Test status | |
| Simulation time | 5044996408 ps |
| CPU time | 518.38 seconds |
| Started | Jun 29 07:39:06 PM PDT 24 |
| Finished | Jun 29 07:47:45 PM PDT 24 |
| Peak memory | 609256 kb |
| Host | smart-e543e830-4554-42b4-9596-d0b12dd11d64 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_usb_clk_disabled_when_active_test:1:new_rules,test_rom:0 +cdc_instrumentation_enable d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1532322759 -assert no postproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de fault.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_usb_clk_disabled_when_active.1532322759 |
| Directory | /workspace/0.chip_sw_pwrmgr_usb_clk_disabled_when_active/latest |
| Test location | /workspace/coverage/default/0.chip_sw_pwrmgr_usbdev_smoketest.1163850457 |
| Short name | T61 |
| Test name | |
| Test status | |
| Simulation time | 5397653500 ps |
| CPU time | 491.3 seconds |
| Started | Jun 29 07:41:42 PM PDT 24 |
| Finished | Jun 29 07:49:55 PM PDT 24 |
| Peak memory | 609252 kb |
| Host | smart-75a8a005-49d2-48f4-88f5-7206f5890564 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_usbdev_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1163850457 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_usbdev_smoketest.1163850457 |
| Directory | /workspace/0.chip_sw_pwrmgr_usbdev_smoketest/latest |
| Test location | /workspace/coverage/default/0.chip_sw_pwrmgr_wdog_reset.2835724799 |
| Short name | T1041 |
| Test name | |
| Test status | |
| Simulation time | 4519263470 ps |
| CPU time | 613.89 seconds |
| Started | Jun 29 07:46:34 PM PDT 24 |
| Finished | Jun 29 07:56:49 PM PDT 24 |
| Peak memory | 609180 kb |
| Host | smart-2ce2bf05-9cb3-4b68-aaed-7d9c58a56704 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=pwrmgr_wdog_reset_reqs_test:1:new_rules,test_rom:0 +cdc_inst rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=283 5724799 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_wdog_reset.2835724799 |
| Directory | /workspace/0.chip_sw_pwrmgr_wdog_reset/latest |
| Test location | /workspace/coverage/default/0.chip_sw_rom_ctrl_integrity_check.210074142 |
| Short name | T385 |
| Test name | |
| Test status | |
| Simulation time | 8683930049 ps |
| CPU time | 735.24 seconds |
| Started | Jun 29 07:38:12 PM PDT 24 |
| Finished | Jun 29 07:50:28 PM PDT 24 |
| Peak memory | 609252 kb |
| Host | smart-8bb61bd2-733b-4fc0-a597-e5a3dd47a6e4 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=rom_ctrl_integrity_check_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=210074142 -assert nopostproc +UV M_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_ctrl_integrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov erage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_rom_ctrl_integrity_check.210074142 |
| Directory | /workspace/0.chip_sw_rom_ctrl_integrity_check/latest |
| Test location | /workspace/coverage/default/0.chip_sw_rstmgr_rst_cnsty_escalation.1796915049 |
| Short name | T259 |
| Test name | |
| Test status | |
| Simulation time | 5410422728 ps |
| CPU time | 779.41 seconds |
| Started | Jun 29 07:38:32 PM PDT 24 |
| Finished | Jun 29 07:51:32 PM PDT 24 |
| Peak memory | 639604 kb |
| Host | smart-41933468-3075-497a-bb77-7f80e10596d3 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 1796915049 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rstmgr_cnsty_fault_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_rstmgr_rst_cnsty_escalation.1796915049 |
| Directory | /workspace/0.chip_sw_rstmgr_rst_cnsty_escalation/latest |
| Test location | /workspace/coverage/default/0.chip_sw_rstmgr_smoketest.965457825 |
| Short name | T1091 |
| Test name | |
| Test status | |
| Simulation time | 3023589340 ps |
| CPU time | 260.17 seconds |
| Started | Jun 29 07:41:31 PM PDT 24 |
| Finished | Jun 29 07:45:52 PM PDT 24 |
| Peak memory | 607128 kb |
| Host | smart-3f934061-2f90-43f6-a3e6-f82a0eb1bad5 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=rstmgr_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=965457825 -assert nopostproc +UVM_TESTNAME=ch ip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu ll -cm_name 0.chip_sw_rstmgr_smoketest.965457825 |
| Directory | /workspace/0.chip_sw_rstmgr_smoketest/latest |
| Test location | /workspace/coverage/default/0.chip_sw_rstmgr_sw_req.2959717661 |
| Short name | T1165 |
| Test name | |
| Test status | |
| Simulation time | 5108673262 ps |
| CPU time | 512.18 seconds |
| Started | Jun 29 07:38:15 PM PDT 24 |
| Finished | Jun 29 07:46:48 PM PDT 24 |
| Peak memory | 607224 kb |
| Host | smart-13025630-b839-44fe-995d-e3bd39de90bd |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=rstmgr_sw_req_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2959717661 -assert nopostproc +UVM_TESTNAME =chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 0.chip_sw_rstmgr_sw_req.2959717661 |
| Directory | /workspace/0.chip_sw_rstmgr_sw_req/latest |
| Test location | /workspace/coverage/default/0.chip_sw_rstmgr_sw_rst.1567623525 |
| Short name | T367 |
| Test name | |
| Test status | |
| Simulation time | 2821122728 ps |
| CPU time | 172.23 seconds |
| Started | Jun 29 07:39:44 PM PDT 24 |
| Finished | Jun 29 07:42:37 PM PDT 24 |
| Peak memory | 609160 kb |
| Host | smart-76d4a91c-bffd-475d-a866-2ae325321a86 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=rstmgr_sw_rst_ctrl_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1567623525 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_rstmgr_sw_rst.1567623525 |
| Directory | /workspace/0.chip_sw_rstmgr_sw_rst/latest |
| Test location | /workspace/coverage/default/0.chip_sw_rv_core_ibex_icache_invalidate.2938458773 |
| Short name | T266 |
| Test name | |
| Test status | |
| Simulation time | 2528048390 ps |
| CPU time | 296.97 seconds |
| Started | Jun 29 07:39:00 PM PDT 24 |
| Finished | Jun 29 07:43:57 PM PDT 24 |
| Peak memory | 609300 kb |
| Host | smart-ee2e9b5b-712a-4fb8-b6de-df64ea676672 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=rv_core_ibex_icache_invalidate_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2938458773 -assert nopostp roc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rv_core_ibex_icache_invalidate_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_rv_core_ibex_icache_invalidate.2938458773 |
| Directory | /workspace/0.chip_sw_rv_core_ibex_icache_invalidate/latest |
| Test location | /workspace/coverage/default/0.chip_sw_rv_core_ibex_lockstep_glitch.3721945651 |
| Short name | T1219 |
| Test name | |
| Test status | |
| Simulation time | 2481486638 ps |
| CPU time | 151.99 seconds |
| Started | Jun 29 07:39:28 PM PDT 24 |
| Finished | Jun 29 07:42:02 PM PDT 24 |
| Peak memory | 639012 kb |
| Host | smart-4e851015-f443-4fc1-aa0c-6ee1af843921 |
| User | root |
| Command | /workspace/default/simv +disable_assert_final_checks +sw_build_device=sim_dv +sw_images=aes_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3721945651 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rv_core_ibex_lockstep_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_rv_core_ibex_lockstep_glitch.3721945651 |
| Directory | /workspace/0.chip_sw_rv_core_ibex_lockstep_glitch/latest |
| Test location | /workspace/coverage/default/0.chip_sw_rv_core_ibex_rnd.2066674895 |
| Short name | T860 |
| Test name | |
| Test status | |
| Simulation time | 5856947056 ps |
| CPU time | 1013.89 seconds |
| Started | Jun 29 07:40:04 PM PDT 24 |
| Finished | Jun 29 07:56:59 PM PDT 24 |
| Peak memory | 609180 kb |
| Host | smart-d7675e91-f399-4382-9327-49f2dad79032 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=20_000_000 +rng_srate_value_max=32 +sw_build_device=sim_dv +sw_images=rv_core_ibex_rnd_test:1:new_rules,te st_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n tb_random_seed=2066674895 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_rv_core_ibex_rnd.2066674895 |
| Directory | /workspace/0.chip_sw_rv_core_ibex_rnd/latest |
| Test location | /workspace/coverage/default/0.chip_sw_rv_dm_access_after_escalation_reset.373809833 |
| Short name | T641 |
| Test name | |
| Test status | |
| Simulation time | 4621330650 ps |
| CPU time | 374.3 seconds |
| Started | Jun 29 07:37:13 PM PDT 24 |
| Finished | Jun 29 07:43:27 PM PDT 24 |
| Peak memory | 618056 kb |
| Host | smart-d6a59cf0-bdb3-45fb-81af-5df4e65f457d |
| User | root |
| Command | /workspace/default/simv +use_jtag_dmi=1 +sw_build_device=sim_dv +sw_images=alert_handler_escalation_test:1:new_rules,test_rom:0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=373809833 -asser t nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rv_dm_access_after_escalation_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_rv_dm_access_after_escalation_reset.373809833 |
| Directory | /workspace/0.chip_sw_rv_dm_access_after_escalation_reset/latest |
| Test location | /workspace/coverage/default/0.chip_sw_rv_plic_smoketest.2416610323 |
| Short name | T869 |
| Test name | |
| Test status | |
| Simulation time | 3299958744 ps |
| CPU time | 239.58 seconds |
| Started | Jun 29 07:39:56 PM PDT 24 |
| Finished | Jun 29 07:43:56 PM PDT 24 |
| Peak memory | 609184 kb |
| Host | smart-ac88b26f-dfa0-403f-932b-3f71e6afed21 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=rv_plic_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2416610323 -assert nopostproc +UVM_TESTNAME= chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/ null -cm_name 0.chip_sw_rv_plic_smoketest.2416610323 |
| Directory | /workspace/0.chip_sw_rv_plic_smoketest/latest |
| Test location | /workspace/coverage/default/0.chip_sw_rv_timer_irq.406146708 |
| Short name | T422 |
| Test name | |
| Test status | |
| Simulation time | 2913006904 ps |
| CPU time | 325.53 seconds |
| Started | Jun 29 07:42:14 PM PDT 24 |
| Finished | Jun 29 07:47:40 PM PDT 24 |
| Peak memory | 607136 kb |
| Host | smart-986428fa-429a-4c23-87eb-8f20068581e2 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=rv_timer_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=406146708 -assert nopostproc +UVM_TESTNAME= chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/ null -cm_name 0.chip_sw_rv_timer_irq.406146708 |
| Directory | /workspace/0.chip_sw_rv_timer_irq/latest |
| Test location | /workspace/coverage/default/0.chip_sw_rv_timer_smoketest.780032114 |
| Short name | T1233 |
| Test name | |
| Test status | |
| Simulation time | 3124748540 ps |
| CPU time | 363.12 seconds |
| Started | Jun 29 07:41:50 PM PDT 24 |
| Finished | Jun 29 07:47:54 PM PDT 24 |
| Peak memory | 609188 kb |
| Host | smart-aee2c2fa-b5fb-44fd-a5d7-b2a0736fa04f |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=rv_timer_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=780032114 -assert nopostproc +UVM_TESTNAME= chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/ null -cm_name 0.chip_sw_rv_timer_smoketest.780032114 |
| Directory | /workspace/0.chip_sw_rv_timer_smoketest/latest |
| Test location | /workspace/coverage/default/0.chip_sw_sensor_ctrl_status.3153836537 |
| Short name | T135 |
| Test name | |
| Test status | |
| Simulation time | 2710440686 ps |
| CPU time | 223.71 seconds |
| Started | Jun 29 07:39:51 PM PDT 24 |
| Finished | Jun 29 07:43:35 PM PDT 24 |
| Peak memory | 608400 kb |
| Host | smart-15248d33-3b07-47e4-8034-11cf960d7350 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=40_000_000 +sw_build_device=sim_dv +sw_images=sensor_ctrl_status_test:1:new_rules,test_rom:0 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3153836 537 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sensor_ctrl_status_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_sensor_ctrl_status.3153836537 |
| Directory | /workspace/0.chip_sw_sensor_ctrl_status/latest |
| Test location | /workspace/coverage/default/0.chip_sw_sleep_pwm_pulses.1568467967 |
| Short name | T1158 |
| Test name | |
| Test status | |
| Simulation time | 10081182618 ps |
| CPU time | 1280.32 seconds |
| Started | Jun 29 07:38:36 PM PDT 24 |
| Finished | Jun 29 07:59:56 PM PDT 24 |
| Peak memory | 608332 kb |
| Host | smart-557826ba-8bbd-4d22-8e37-0387232bef02 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=sleep_pwm_pulses_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1568467967 -assert nopostproc +UVM_TESTN AME=chip_base_test +UVM_TEST_SEQ=chip_sw_pwm_pulses_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm _log /dev/null -cm_name 0.chip_sw_sleep_pwm_pulses.1568467967 |
| Directory | /workspace/0.chip_sw_sleep_pwm_pulses/latest |
| Test location | /workspace/coverage/default/0.chip_sw_sleep_sram_ret_contents_no_scramble.4262861556 |
| Short name | T274 |
| Test name | |
| Test status | |
| Simulation time | 7195773988 ps |
| CPU time | 1067.59 seconds |
| Started | Jun 29 07:40:36 PM PDT 24 |
| Finished | Jun 29 07:58:24 PM PDT 24 |
| Peak memory | 608428 kb |
| Host | smart-d1cd94a2-97f3-41cf-a9be-66b5446e0c84 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=20_000_000 +en_scb_tl_err_chk=0 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=sram _ctrl_sleep_sram_ret_contents_no_scramble_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4262861556 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_S EQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_sl eep_sram_ret_contents_no_scramble.4262861556 |
| Directory | /workspace/0.chip_sw_sleep_sram_ret_contents_no_scramble/latest |
| Test location | /workspace/coverage/default/0.chip_sw_sleep_sram_ret_contents_scramble.117155038 |
| Short name | T250 |
| Test name | |
| Test status | |
| Simulation time | 7441198174 ps |
| CPU time | 725.62 seconds |
| Started | Jun 29 07:38:53 PM PDT 24 |
| Finished | Jun 29 07:50:59 PM PDT 24 |
| Peak memory | 608476 kb |
| Host | smart-e5767725-35e3-40c6-84e5-c8db849cbd62 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=20_000_000 +en_scb_tl_err_chk=0 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=sram _ctrl_sleep_sram_ret_contents_scramble_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=117155038 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=c hip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_sleep_ sram_ret_contents_scramble.117155038 |
| Directory | /workspace/0.chip_sw_sleep_sram_ret_contents_scramble/latest |
| Test location | /workspace/coverage/default/0.chip_sw_spi_device_pass_through.3701675615 |
| Short name | T148 |
| Test name | |
| Test status | |
| Simulation time | 7260716774 ps |
| CPU time | 821.42 seconds |
| Started | Jun 29 07:38:41 PM PDT 24 |
| Finished | Jun 29 07:52:23 PM PDT 24 |
| Peak memory | 624296 kb |
| Host | smart-5bed3a86-6b26-41c4-a887-676732b985fc |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=spi_passthrough_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3701675615 -assert nopostproc +UVM_TESTNA ME=chip_base_test +UVM_TEST_SEQ=chip_sw_spi_passthrough_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_spi_device_pass_through.3701675615 |
| Directory | /workspace/0.chip_sw_spi_device_pass_through/latest |
| Test location | /workspace/coverage/default/0.chip_sw_spi_device_tpm.4100865410 |
| Short name | T48 |
| Test name | |
| Test status | |
| Simulation time | 3011226523 ps |
| CPU time | 315.61 seconds |
| Started | Jun 29 07:39:17 PM PDT 24 |
| Finished | Jun 29 07:44:34 PM PDT 24 |
| Peak memory | 622192 kb |
| Host | smart-31384d37-491a-4ed1-978c-b208339142c6 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=spi_device_tpm_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4100865410 -assert nopostproc +UVM_T ESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_spi_device_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default .vdb -cm_log /dev/null -cm_name 0.chip_sw_spi_device_tpm.4100865410 |
| Directory | /workspace/0.chip_sw_spi_device_tpm/latest |
| Test location | /workspace/coverage/default/0.chip_sw_spi_host_tx_rx.1957243558 |
| Short name | T42 |
| Test name | |
| Test status | |
| Simulation time | 3106451848 ps |
| CPU time | 240.93 seconds |
| Started | Jun 29 07:37:19 PM PDT 24 |
| Finished | Jun 29 07:41:20 PM PDT 24 |
| Peak memory | 607952 kb |
| Host | smart-6b889f78-cda3-434a-913f-2629f7f2d06f |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=spi_host_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1957243558 -assert nopostproc +UVM_TESTNAM E=chip_base_test +UVM_TEST_SEQ=chip_sw_spi_host_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb - cm_log /dev/null -cm_name 0.chip_sw_spi_host_tx_rx.1957243558 |
| Directory | /workspace/0.chip_sw_spi_host_tx_rx/latest |
| Test location | /workspace/coverage/default/0.chip_sw_sram_ctrl_scrambled_access.3421949366 |
| Short name | T1183 |
| Test name | |
| Test status | |
| Simulation time | 5211511192 ps |
| CPU time | 703.14 seconds |
| Started | Jun 29 07:39:37 PM PDT 24 |
| Finished | Jun 29 07:51:21 PM PDT 24 |
| Peak memory | 608788 kb |
| Host | smart-b9b9fc8a-7f1e-4227-b325-ea841a834a1e |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=12_000_000 +en_scb_tl_err_chk=0 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=sram _ctrl_scrambled_access_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3421949366 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sram_ctr l_scrambled_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw _sram_ctrl_scrambled_access.3421949366 |
| Directory | /workspace/0.chip_sw_sram_ctrl_scrambled_access/latest |
| Test location | /workspace/coverage/default/0.chip_sw_sram_ctrl_scrambled_access_jitter_en.1746525366 |
| Short name | T1269 |
| Test name | |
| Test status | |
| Simulation time | 5627216173 ps |
| CPU time | 734.78 seconds |
| Started | Jun 29 07:42:24 PM PDT 24 |
| Finished | Jun 29 07:54:40 PM PDT 24 |
| Peak memory | 608800 kb |
| Host | smart-fb7689fb-39c7-49d4-bd67-d03ccb63405e |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=12_000_000 +bypass_alert_ready_to_end_check=1 +en_jitter=1 +en_scb_tl_err_chk=0 +sw_build_device=sim_dv +s w_images=sram_ctrl_scrambled_access_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1746525366 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chi p_sw_sram_ctrl_scrambled_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n ame 0.chip_sw_sram_ctrl_scrambled_access_jitter_en.1746525366 |
| Directory | /workspace/0.chip_sw_sram_ctrl_scrambled_access_jitter_en/latest |
| Test location | /workspace/coverage/default/0.chip_sw_sram_ctrl_smoketest.574461000 |
| Short name | T936 |
| Test name | |
| Test status | |
| Simulation time | 3130581640 ps |
| CPU time | 214.73 seconds |
| Started | Jun 29 07:41:10 PM PDT 24 |
| Finished | Jun 29 07:44:46 PM PDT 24 |
| Peak memory | 609156 kb |
| Host | smart-a75e6246-d471-4520-8a62-d24c439a24fe |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=sram_ctrl_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=574461000 -assert nopostproc +UVM_TESTNAME =chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 0.chip_sw_sram_ctrl_smoketest.574461000 |
| Directory | /workspace/0.chip_sw_sram_ctrl_smoketest/latest |
| Test location | /workspace/coverage/default/0.chip_sw_sysrst_ctrl_ec_rst_l.254152403 |
| Short name | T1264 |
| Test name | |
| Test status | |
| Simulation time | 20436602206 ps |
| CPU time | 4064.22 seconds |
| Started | Jun 29 07:39:33 PM PDT 24 |
| Finished | Jun 29 08:47:18 PM PDT 24 |
| Peak memory | 609260 kb |
| Host | smart-ba6040a8-83cb-43af-96dd-1e84f34a2d29 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=sysrst_ctrl_ec_rst_l_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=254152403 -assert nopostproc +UVM_TE STNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_ec_rst_l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de fault.vdb -cm_log /dev/null -cm_name 0.chip_sw_sysrst_ctrl_ec_rst_l.254152403 |
| Directory | /workspace/0.chip_sw_sysrst_ctrl_ec_rst_l/latest |
| Test location | /workspace/coverage/default/0.chip_sw_sysrst_ctrl_in_irq.3425142283 |
| Short name | T163 |
| Test name | |
| Test status | |
| Simulation time | 4617674923 ps |
| CPU time | 716.49 seconds |
| Started | Jun 29 07:40:10 PM PDT 24 |
| Finished | Jun 29 07:52:09 PM PDT 24 |
| Peak memory | 612516 kb |
| Host | smart-c13932c6-5e1a-40f7-9773-c9317d1aeb07 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=sysrst_ctrl_in_irq_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3425142283 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_in_irq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau lt.vdb -cm_log /dev/null -cm_name 0.chip_sw_sysrst_ctrl_in_irq.3425142283 |
| Directory | /workspace/0.chip_sw_sysrst_ctrl_in_irq/latest |
| Test location | /workspace/coverage/default/0.chip_sw_sysrst_ctrl_inputs.881546247 |
| Short name | T159 |
| Test name | |
| Test status | |
| Simulation time | 3896725117 ps |
| CPU time | 363.81 seconds |
| Started | Jun 29 07:40:22 PM PDT 24 |
| Finished | Jun 29 07:46:27 PM PDT 24 |
| Peak memory | 612156 kb |
| Host | smart-2e232e06-561e-4729-8133-07ede0a59764 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=sysrst_ctrl_inputs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=881546247 -assert nopostproc +UVM_TEST NAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_inputs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul t.vdb -cm_log /dev/null -cm_name 0.chip_sw_sysrst_ctrl_inputs.881546247 |
| Directory | /workspace/0.chip_sw_sysrst_ctrl_inputs/latest |
| Test location | /workspace/coverage/default/0.chip_sw_sysrst_ctrl_outputs.3220527880 |
| Short name | T161 |
| Test name | |
| Test status | |
| Simulation time | 3781687248 ps |
| CPU time | 291.09 seconds |
| Started | Jun 29 07:39:35 PM PDT 24 |
| Finished | Jun 29 07:44:27 PM PDT 24 |
| Peak memory | 609192 kb |
| Host | smart-92941788-805e-4cbb-9909-2176dae09daf |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=sysrst_ctrl_outputs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3220527880 -assert nopostproc +UVM_TE STNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_outputs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def ault.vdb -cm_log /dev/null -cm_name 0.chip_sw_sysrst_ctrl_outputs.3220527880 |
| Directory | /workspace/0.chip_sw_sysrst_ctrl_outputs/latest |
| Test location | /workspace/coverage/default/0.chip_sw_sysrst_ctrl_reset.244746830 |
| Short name | T30 |
| Test name | |
| Test status | |
| Simulation time | 23235743364 ps |
| CPU time | 2118.96 seconds |
| Started | Jun 29 07:39:36 PM PDT 24 |
| Finished | Jun 29 08:14:57 PM PDT 24 |
| Peak memory | 612632 kb |
| Host | smart-2fece4d5-ed4e-401d-a438-d081a13711f7 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=36_000_000 +sw_build_device=sim_dv +sw_images=sysrst_ctrl_reset_test:1:new_rules,test_rom:0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24474683 0 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_sysrst_ctrl_reset.244746830 |
| Directory | /workspace/0.chip_sw_sysrst_ctrl_reset/latest |
| Test location | /workspace/coverage/default/0.chip_sw_sysrst_ctrl_ulp_z3_wakeup.839375460 |
| Short name | T45 |
| Test name | |
| Test status | |
| Simulation time | 5342257556 ps |
| CPU time | 572.93 seconds |
| Started | Jun 29 07:38:09 PM PDT 24 |
| Finished | Jun 29 07:47:43 PM PDT 24 |
| Peak memory | 609308 kb |
| Host | smart-2634224b-99c8-47e8-be9c-232b31f5fd18 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=sysrst_ctrl_ulp_z3_wakeup_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=839375460 -assert nopostproc +U VM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_ulp_z3_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/c overage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_sysrst_ctrl_ulp_z3_wakeup.839375460 |
| Directory | /workspace/0.chip_sw_sysrst_ctrl_ulp_z3_wakeup/latest |
| Test location | /workspace/coverage/default/0.chip_sw_uart_rand_baudrate.2217261588 |
| Short name | T1046 |
| Test name | |
| Test status | |
| Simulation time | 8769622302 ps |
| CPU time | 1728.06 seconds |
| Started | Jun 29 07:37:43 PM PDT 24 |
| Finished | Jun 29 08:06:33 PM PDT 24 |
| Peak memory | 618888 kb |
| Host | smart-f811abe1-342d-498e-b7f2-5a8344e3b547 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=2217261588 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_uart_rand_baudrate.2217261588 |
| Directory | /workspace/0.chip_sw_uart_rand_baudrate/latest |
| Test location | /workspace/coverage/default/0.chip_sw_uart_smoketest.696794985 |
| Short name | T961 |
| Test name | |
| Test status | |
| Simulation time | 3140798726 ps |
| CPU time | 270.83 seconds |
| Started | Jun 29 07:42:35 PM PDT 24 |
| Finished | Jun 29 07:47:07 PM PDT 24 |
| Peak memory | 609980 kb |
| Host | smart-d81bf67a-6447-4dac-ad11-993eb5afd717 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=uart_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=696794985 -assert nopostproc +UVM_TESTNAME=chip _base_test +UVM_TEST_SEQ=chip_sw_uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 0.chip_sw_uart_smoketest.696794985 |
| Directory | /workspace/0.chip_sw_uart_smoketest/latest |
| Test location | /workspace/coverage/default/0.chip_sw_uart_tx_rx.2682650784 |
| Short name | T1235 |
| Test name | |
| Test status | |
| Simulation time | 4348583680 ps |
| CPU time | 694.44 seconds |
| Started | Jun 29 07:38:49 PM PDT 24 |
| Finished | Jun 29 07:50:24 PM PDT 24 |
| Peak memory | 615888 kb |
| Host | smart-a906a93b-f247-4972-b815-b57d6eb2e78c |
| User | root |
| Command | /workspace/default/simv +uart_idx=0 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2682650784 -a ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_uart_tx_rx.2682650784 |
| Directory | /workspace/0.chip_sw_uart_tx_rx/latest |
| Test location | /workspace/coverage/default/0.chip_sw_uart_tx_rx_bootstrap.3163003697 |
| Short name | T968 |
| Test name | |
| Test status | |
| Simulation time | 78136469364 ps |
| CPU time | 14352.7 seconds |
| Started | Jun 29 07:39:46 PM PDT 24 |
| Finished | Jun 29 11:39:01 PM PDT 24 |
| Peak memory | 632384 kb |
| Host | smart-800896f2-4fb3-4cc0-802f-1c3cbe33ea5e |
| User | root |
| Command | /workspace/default/simv +use_spi_load_bootstrap=1 +calibrate_usb_clk=1 +test_timeout_ns=160_000_000 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test :1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=3163003697 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_uart_tx_rx_bootstrap.3163003697 |
| Directory | /workspace/0.chip_sw_uart_tx_rx_bootstrap/latest |
| Test location | /workspace/coverage/default/0.chip_sw_uart_tx_rx_idx1.1192150036 |
| Short name | T306 |
| Test name | |
| Test status | |
| Simulation time | 4082333126 ps |
| CPU time | 546.52 seconds |
| Started | Jun 29 07:37:17 PM PDT 24 |
| Finished | Jun 29 07:46:24 PM PDT 24 |
| Peak memory | 615884 kb |
| Host | smart-b8158e75-41e3-448a-85ff-fee1c639c125 |
| User | root |
| Command | /workspace/default/simv +uart_idx=1 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1192150036 -a ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_uart_tx_rx_idx1.1192150036 |
| Directory | /workspace/0.chip_sw_uart_tx_rx_idx1/latest |
| Test location | /workspace/coverage/default/0.chip_sw_uart_tx_rx_idx3.2124529356 |
| Short name | T27 |
| Test name | |
| Test status | |
| Simulation time | 4006855638 ps |
| CPU time | 552.07 seconds |
| Started | Jun 29 07:37:08 PM PDT 24 |
| Finished | Jun 29 07:46:20 PM PDT 24 |
| Peak memory | 615868 kb |
| Host | smart-52bee409-380d-450a-a1a6-abc28343f545 |
| User | root |
| Command | /workspace/default/simv +uart_idx=3 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2124529356 -a ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_uart_tx_rx_idx3.2124529356 |
| Directory | /workspace/0.chip_sw_uart_tx_rx_idx3/latest |
| Test location | /workspace/coverage/default/0.chip_sw_usb_ast_clk_calib.3367397595 |
| Short name | T1064 |
| Test name | |
| Test status | |
| Simulation time | 2652181634 ps |
| CPU time | 281.42 seconds |
| Started | Jun 29 07:39:55 PM PDT 24 |
| Finished | Jun 29 07:44:37 PM PDT 24 |
| Peak memory | 607904 kb |
| Host | smart-d7c0c206-dd9b-4f29-a26e-cecad958e942 |
| User | root |
| Command | /workspace/default/simv +usb_max_drift=1 +usb_fast_sof=1 +sw_build_device=sim_dv +sw_images=ast_usb_clk_calib:1:new_rules,test_rom:0 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3367397595 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_usb_ast_clk_calib_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_usb_ast_clk_calib.3367397595 |
| Directory | /workspace/0.chip_sw_usb_ast_clk_calib/latest |
| Test location | /workspace/coverage/default/0.chip_sw_usbdev_dpi.972077375 |
| Short name | T33 |
| Test name | |
| Test status | |
| Simulation time | 12357635910 ps |
| CPU time | 3204.58 seconds |
| Started | Jun 29 07:37:49 PM PDT 24 |
| Finished | Jun 29 08:31:16 PM PDT 24 |
| Peak memory | 609184 kb |
| Host | smart-ed9054ae-c6d6-45eb-9722-aa957293dd91 |
| User | root |
| Command | /workspace/default/simv +uart_idx=0 +calibrate_usb_clk=1 +sw_test_timeout_ns=30_000_000 +sw_build_device=sim_dv +sw_images=usbdev_test:1:new_rules,tes t_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +nt b_random_seed=972077375 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_usbdev_dpi_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_usbdev_dpi.972077375 |
| Directory | /workspace/0.chip_sw_usbdev_dpi/latest |
| Test location | /workspace/coverage/default/0.chip_sw_usbdev_pincfg.2961516244 |
| Short name | T28 |
| Test name | |
| Test status | |
| Simulation time | 32168292904 ps |
| CPU time | 7488.32 seconds |
| Started | Jun 29 07:40:35 PM PDT 24 |
| Finished | Jun 29 09:45:25 PM PDT 24 |
| Peak memory | 607116 kb |
| Host | smart-c4d9cad6-9ce6-4552-8ba6-c7a94cc22a94 |
| User | root |
| Command | /workspace/default/simv +uart_idx=0 +calibrate_usb_clk=1 +sw_test_timeout_ns=100_000_000 +sw_build_device=sim_dv +sw_images=usbdev_pincfg_test:1:new_r ules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim .tcl +ntb_random_seed=2961516244 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_usbdev_dpi_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_usbdev_pincfg.2961516244 |
| Directory | /workspace/0.chip_sw_usbdev_pincfg/latest |
| Test location | /workspace/coverage/default/0.chip_sw_usbdev_pullup.888313903 |
| Short name | T70 |
| Test name | |
| Test status | |
| Simulation time | 2814652350 ps |
| CPU time | 298.76 seconds |
| Started | Jun 29 07:38:32 PM PDT 24 |
| Finished | Jun 29 07:43:31 PM PDT 24 |
| Peak memory | 609176 kb |
| Host | smart-e08865bc-f583-46f0-bfcd-18f5a1bb2a07 |
| User | root |
| Command | /workspace/default/simv +uart_idx=0 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=usbdev_pullup_test:1:new_rules,test_rom:0 +cdc_instrumenta tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=888313903 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_usbdev_dpi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_usbdev_pullup.888313903 |
| Directory | /workspace/0.chip_sw_usbdev_pullup/latest |
| Test location | /workspace/coverage/default/0.chip_sw_usbdev_setuprx.4237103337 |
| Short name | T1078 |
| Test name | |
| Test status | |
| Simulation time | 3524783800 ps |
| CPU time | 485.34 seconds |
| Started | Jun 29 07:37:19 PM PDT 24 |
| Finished | Jun 29 07:45:25 PM PDT 24 |
| Peak memory | 607124 kb |
| Host | smart-f84df809-0d8c-4e6e-9709-2148dfeaf368 |
| User | root |
| Command | /workspace/default/simv +uart_idx=0 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=usbdev_setuprx_test:1:new_rules,test_rom:0 +cdc_instrument ation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=423710333 7 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_usbdev_dpi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_usbdev_setuprx.4237103337 |
| Directory | /workspace/0.chip_sw_usbdev_setuprx/latest |
| Test location | /workspace/coverage/default/0.chip_sw_usbdev_stream.211933522 |
| Short name | T1117 |
| Test name | |
| Test status | |
| Simulation time | 19366899576 ps |
| CPU time | 5074.77 seconds |
| Started | Jun 29 07:39:55 PM PDT 24 |
| Finished | Jun 29 09:04:31 PM PDT 24 |
| Peak memory | 609176 kb |
| Host | smart-a9eb87f2-1752-4922-bed2-5926ead24c37 |
| User | root |
| Command | /workspace/default/simv +uart_idx=0 +calibrate_usb_clk=1 +sw_test_timeout_ns=60_000_000 +sw_build_device=sim_dv +sw_images=usbdev_stream_test:1:new_ru les,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim. tcl +ntb_random_seed=211933522 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_usbdev_stream_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_usbdev_stream.211933522 |
| Directory | /workspace/0.chip_sw_usbdev_stream/latest |
| Test location | /workspace/coverage/default/0.chip_sw_usbdev_vbus.1466542835 |
| Short name | T1256 |
| Test name | |
| Test status | |
| Simulation time | 2519610488 ps |
| CPU time | 311.06 seconds |
| Started | Jun 29 07:38:02 PM PDT 24 |
| Finished | Jun 29 07:43:14 PM PDT 24 |
| Peak memory | 609120 kb |
| Host | smart-f80403f3-ef68-46f1-b90f-a118eb366574 |
| User | root |
| Command | /workspace/default/simv +uart_idx=0 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=usbdev_vbus_test:1:new_rules,test_rom:0 +cdc_instrumentati on_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1466542835 - assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_usbdev_dpi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_usbdev_vbus.1466542835 |
| Directory | /workspace/0.chip_sw_usbdev_vbus/latest |
| Test location | /workspace/coverage/default/0.chip_tap_straps_prod.2584103497 |
| Short name | T1162 |
| Test name | |
| Test status | |
| Simulation time | 8350304711 ps |
| CPU time | 949.07 seconds |
| Started | Jun 29 07:39:28 PM PDT 24 |
| Finished | Jun 29 07:55:18 PM PDT 24 |
| Peak memory | 618236 kb |
| Host | smart-a515d27e-82df-470d-8aec-34172fba5035 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStProd +create_jtag_riscv_map=1 +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:test_in_rom :new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2584103497 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_tap_straps_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_tap_straps_prod.2584103497 |
| Directory | /workspace/0.chip_tap_straps_prod/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_asm_init_dev.3222937883 |
| Short name | T1284 |
| Test name | |
| Test status | |
| Simulation time | 15639789340 ps |
| CPU time | 4883.09 seconds |
| Started | Jun 29 07:48:12 PM PDT 24 |
| Finished | Jun 29 09:09:37 PM PDT 24 |
| Peak memory | 607184 kb |
| Host | smart-3afb1f39-3bf8-4a24-824d-ebda21e05a6b |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeCustom +sw_test_timeout_ns=20000000 +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_prod _key_0:1:ot_flash_binary,otp_img_e2e_bootstrap_entry_dev:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3222937883 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_S EQ=chip_sw_rom_e2e_asm_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_asm_init_dev.3222937883 |
| Directory | /workspace/0.rom_e2e_asm_init_dev/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_asm_init_prod.3899137295 |
| Short name | T899 |
| Test name | |
| Test status | |
| Simulation time | 15554153850 ps |
| CPU time | 4073.83 seconds |
| Started | Jun 29 07:45:17 PM PDT 24 |
| Finished | Jun 29 08:53:12 PM PDT 24 |
| Peak memory | 607908 kb |
| Host | smart-5a5d58cd-06eb-4755-9dfa-05239a551816 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeCustom +sw_test_timeout_ns=20000000 +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_prod _key_0:1:ot_flash_binary,otp_img_e2e_bootstrap_entry_prod:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3899137295 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_ SEQ=chip_sw_rom_e2e_asm_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_asm_init_prod.3899137295 |
| Directory | /workspace/0.rom_e2e_asm_init_prod/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_asm_init_rma.1121772710 |
| Short name | T1061 |
| Test name | |
| Test status | |
| Simulation time | 14515354004 ps |
| CPU time | 4685.87 seconds |
| Started | Jun 29 07:44:57 PM PDT 24 |
| Finished | Jun 29 09:03:04 PM PDT 24 |
| Peak memory | 608212 kb |
| Host | smart-89244ecf-4d9f-4819-aa81-49ce5ab4330a |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeCustom +sw_test_timeout_ns=20000000 +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_prod _key_0:1:ot_flash_binary,otp_img_e2e_bootstrap_entry_rma:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1121772710 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_S EQ=chip_sw_rom_e2e_asm_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_asm_init_rma.1121772710 |
| Directory | /workspace/0.rom_e2e_asm_init_rma/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_asm_init_test_unlocked0.1351709846 |
| Short name | T395 |
| Test name | |
| Test status | |
| Simulation time | 11058493670 ps |
| CPU time | 3238.95 seconds |
| Started | Jun 29 07:44:48 PM PDT 24 |
| Finished | Jun 29 08:38:48 PM PDT 24 |
| Peak memory | 607492 kb |
| Host | smart-e60e9471-1f21-4f72-9c76-bc9f245d3ef3 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeCustom +sw_test_timeout_ns=410_000_000 +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_p rod_key_0:1:ot_flash_binary,otp_img_e2e_bootstrap_entry_test_unlocked0:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY =UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1351709846 -assert nopostproc +UVM_TESTNAME=chip_base_te st +UVM_TEST_SEQ=chip_sw_rom_e2e_asm_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/ null -cm_name 0.rom_e2e_asm_init_test_unlocked0.1351709846 |
| Directory | /workspace/0.rom_e2e_asm_init_test_unlocked0/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_bad_b_good_prod.1874585856 |
| Short name | T1070 |
| Test name | |
| Test status | |
| Simulation time | 24087993666 ps |
| CPU time | 6484.22 seconds |
| Started | Jun 29 07:46:11 PM PDT 24 |
| Finished | Jun 29 09:34:16 PM PDT 24 |
| Peak memory | 607328 kb |
| Host | smart-abf41801-d5c1-4a33-a2ef-9c669802419a |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_corrupted:1: ot_flash_binary:signed:fake_ecdsa_prod_key_0,empty_test_slot_b_fake_ecdsa_prod_key_0:2:ot_flash_binary,otp_img_boot_policy_valid_prod:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=1874585856 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_boot_policy_valid_a_bad_b_good_prod.1874585856 |
| Directory | /workspace/0.rom_e2e_boot_policy_valid_a_bad_b_good_prod/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_bad_b_good_prod_end.2704686919 |
| Short name | T373 |
| Test name | |
| Test status | |
| Simulation time | 24456642680 ps |
| CPU time | 6026.78 seconds |
| Started | Jun 29 07:46:04 PM PDT 24 |
| Finished | Jun 29 09:26:32 PM PDT 24 |
| Peak memory | 608360 kb |
| Host | smart-fa3eedb5-14f7-4650-8380-c447d9f72afc |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_corrupted:1: ot_flash_binary:signed:fake_ecdsa_prod_key_0,empty_test_slot_b_fake_ecdsa_prod_key_0:2:ot_flash_binary,otp_img_boot_policy_valid_prod_end:4,mask_r om:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r andom_seed=2704686919 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_boot_policy_valid_a_bad_b_good_prod_end.2704686919 |
| Directory | /workspace/0.rom_e2e_boot_policy_valid_a_bad_b_good_prod_end/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_bad_b_good_rma.1534633800 |
| Short name | T371 |
| Test name | |
| Test status | |
| Simulation time | 23354255400 ps |
| CPU time | 6098.48 seconds |
| Started | Jun 29 07:45:17 PM PDT 24 |
| Finished | Jun 29 09:26:56 PM PDT 24 |
| Peak memory | 608128 kb |
| Host | smart-38536515-9402-4274-8d8d-d652410ed383 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_corrupted:1: ot_flash_binary:signed:fake_ecdsa_prod_key_0,empty_test_slot_b_fake_ecdsa_prod_key_0:2:ot_flash_binary,otp_img_boot_policy_valid_rma:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=1534633800 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_boot_policy_valid_a_bad_b_good_rma.1534633800 |
| Directory | /workspace/0.rom_e2e_boot_policy_valid_a_bad_b_good_rma/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0.1558198188 |
| Short name | T372 |
| Test name | |
| Test status | |
| Simulation time | 18251630796 ps |
| CPU time | 4903.44 seconds |
| Started | Jun 29 07:42:34 PM PDT 24 |
| Finished | Jun 29 09:04:18 PM PDT 24 |
| Peak memory | 607264 kb |
| Host | smart-a0435ba7-07ef-4e4a-bb95-400fce654ded |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=410_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_corrupted:1: ot_flash_binary:signed:fake_ecdsa_prod_key_0,empty_test_slot_b_fake_ecdsa_prod_key_0:2:ot_flash_binary,otp_img_boot_policy_valid_test_unlocked0:4, mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1558198188 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0.1558198188 |
| Directory | /workspace/0.rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_bad_dev.547154245 |
| Short name | T957 |
| Test name | |
| Test status | |
| Simulation time | 15505856000 ps |
| CPU time | 3954.53 seconds |
| Started | Jun 29 07:44:15 PM PDT 24 |
| Finished | Jun 29 08:50:10 PM PDT 24 |
| Peak memory | 608368 kb |
| Host | smart-a6df4572-5ba2-4df3-bbe3-f3378926a298 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_p rod_key_0:1:ot_flash_binary,empty_test_slot_b_corrupted:2:ot_flash_binary:signed:fake_ecdsa_prod_key_0,otp_img_boot_policy_valid_dev:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=547154245 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_boot_policy_valid_a_good_b_bad_dev.547154245 |
| Directory | /workspace/0.rom_e2e_boot_policy_valid_a_good_b_bad_dev/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_bad_prod.828056491 |
| Short name | T268 |
| Test name | |
| Test status | |
| Simulation time | 15742112184 ps |
| CPU time | 4048.09 seconds |
| Started | Jun 29 07:43:54 PM PDT 24 |
| Finished | Jun 29 08:51:23 PM PDT 24 |
| Peak memory | 608352 kb |
| Host | smart-0465adf0-b816-40cd-8f06-2626f0ad7ef4 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_p rod_key_0:1:ot_flash_binary,empty_test_slot_b_corrupted:2:ot_flash_binary:signed:fake_ecdsa_prod_key_0,otp_img_boot_policy_valid_prod:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=828056491 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_boot_policy_valid_a_good_b_bad_prod.828056491 |
| Directory | /workspace/0.rom_e2e_boot_policy_valid_a_good_b_bad_prod/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_bad_prod_end.1649957689 |
| Short name | T974 |
| Test name | |
| Test status | |
| Simulation time | 15469933350 ps |
| CPU time | 4415.66 seconds |
| Started | Jun 29 07:45:40 PM PDT 24 |
| Finished | Jun 29 08:59:16 PM PDT 24 |
| Peak memory | 607320 kb |
| Host | smart-1b0e00b1-6e64-4cb5-9198-546bfa811126 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_p rod_key_0:1:ot_flash_binary,empty_test_slot_b_corrupted:2:ot_flash_binary:signed:fake_ecdsa_prod_key_0,otp_img_boot_policy_valid_prod_end:4,mask_r om:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r andom_seed=1649957689 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_boot_policy_valid_a_good_b_bad_prod_end.1649957689 |
| Directory | /workspace/0.rom_e2e_boot_policy_valid_a_good_b_bad_prod_end/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_bad_rma.290569230 |
| Short name | T1047 |
| Test name | |
| Test status | |
| Simulation time | 14697210714 ps |
| CPU time | 4120.25 seconds |
| Started | Jun 29 07:51:37 PM PDT 24 |
| Finished | Jun 29 09:00:18 PM PDT 24 |
| Peak memory | 608152 kb |
| Host | smart-3e8e62a9-8a71-448e-bed7-6c607ae5c1eb |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_p rod_key_0:1:ot_flash_binary,empty_test_slot_b_corrupted:2:ot_flash_binary:signed:fake_ecdsa_prod_key_0,otp_img_boot_policy_valid_rma:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=290569230 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_boot_policy_valid_a_good_b_bad_rma.290569230 |
| Directory | /workspace/0.rom_e2e_boot_policy_valid_a_good_b_bad_rma/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0.1133574032 |
| Short name | T53 |
| Test name | |
| Test status | |
| Simulation time | 11559749986 ps |
| CPU time | 3524.7 seconds |
| Started | Jun 29 07:46:38 PM PDT 24 |
| Finished | Jun 29 08:45:23 PM PDT 24 |
| Peak memory | 608180 kb |
| Host | smart-269623a8-44b9-48a6-8e90-4142f7c54054 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=410_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_p rod_key_0:1:ot_flash_binary,empty_test_slot_b_corrupted:2:ot_flash_binary:signed:fake_ecdsa_prod_key_0,otp_img_boot_policy_valid_test_unlocked0:4, mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1133574032 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0.1133574032 |
| Directory | /workspace/0.rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_good_dev.276928859 |
| Short name | T1002 |
| Test name | |
| Test status | |
| Simulation time | 14867442142 ps |
| CPU time | 4007.21 seconds |
| Started | Jun 29 07:44:15 PM PDT 24 |
| Finished | Jun 29 08:51:03 PM PDT 24 |
| Peak memory | 607244 kb |
| Host | smart-b2f1e22f-a6a8-43d8-ab8a-2ac08a87bf3b |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_p rod_key_0:1:ot_flash_binary,empty_test_slot_b_fake_ecdsa_prod_key_0:2:ot_flash_binary,otp_img_boot_policy_valid_dev:4,mask_rom:0 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=276928859 - assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co verage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_boot_policy_valid_a_good_b_good_dev.276928859 |
| Directory | /workspace/0.rom_e2e_boot_policy_valid_a_good_b_good_dev/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_good_prod.2292446787 |
| Short name | T1246 |
| Test name | |
| Test status | |
| Simulation time | 15141630740 ps |
| CPU time | 4619 seconds |
| Started | Jun 29 07:48:25 PM PDT 24 |
| Finished | Jun 29 09:05:25 PM PDT 24 |
| Peak memory | 608296 kb |
| Host | smart-2ba253f8-abd4-4a52-921c-d4f10eb90318 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_p rod_key_0:1:ot_flash_binary,empty_test_slot_b_fake_ecdsa_prod_key_0:2:ot_flash_binary,otp_img_boot_policy_valid_prod:4,mask_rom:0 +cdc_instrumenta tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2292446787 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/ coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_boot_policy_valid_a_good_b_good_prod.2292446787 |
| Directory | /workspace/0.rom_e2e_boot_policy_valid_a_good_b_good_prod/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_good_prod_end.828600188 |
| Short name | T848 |
| Test name | |
| Test status | |
| Simulation time | 15215536400 ps |
| CPU time | 4850.65 seconds |
| Started | Jun 29 07:45:36 PM PDT 24 |
| Finished | Jun 29 09:06:28 PM PDT 24 |
| Peak memory | 608308 kb |
| Host | smart-1e5ba05c-6885-477a-9a31-cabb8edfcba9 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_p rod_key_0:1:ot_flash_binary,empty_test_slot_b_fake_ecdsa_prod_key_0:2:ot_flash_binary,otp_img_boot_policy_valid_prod_end:4,mask_rom:0 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=828600 188 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_boot_policy_valid_a_good_b_good_prod_end.828600188 |
| Directory | /workspace/0.rom_e2e_boot_policy_valid_a_good_b_good_prod_end/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_good_rma.1700570438 |
| Short name | T1280 |
| Test name | |
| Test status | |
| Simulation time | 15008519660 ps |
| CPU time | 4035.33 seconds |
| Started | Jun 29 07:44:29 PM PDT 24 |
| Finished | Jun 29 08:51:45 PM PDT 24 |
| Peak memory | 608260 kb |
| Host | smart-72348480-c831-4cc4-8a2b-f6370102f551 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_p rod_key_0:1:ot_flash_binary,empty_test_slot_b_fake_ecdsa_prod_key_0:2:ot_flash_binary,otp_img_boot_policy_valid_rma:4,mask_rom:0 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1700570438 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/c overage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_boot_policy_valid_a_good_b_good_rma.1700570438 |
| Directory | /workspace/0.rom_e2e_boot_policy_valid_a_good_b_good_rma/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0.4176295028 |
| Short name | T905 |
| Test name | |
| Test status | |
| Simulation time | 11336285368 ps |
| CPU time | 3127.04 seconds |
| Started | Jun 29 07:43:34 PM PDT 24 |
| Finished | Jun 29 08:35:41 PM PDT 24 |
| Peak memory | 608112 kb |
| Host | smart-cb9c0b08-1553-44da-a53a-6b60f5a5bfc2 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=410_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_p rod_key_0:1:ot_flash_binary,empty_test_slot_b_fake_ecdsa_prod_key_0:2:ot_flash_binary,otp_img_boot_policy_valid_test_unlocked0:4,mask_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 4176295028 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0.4176295028 |
| Directory | /workspace/0.rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_jtag_inject_dev.2888276562 |
| Short name | T673 |
| Test name | |
| Test status | |
| Simulation time | 36391972679 ps |
| CPU time | 2882.28 seconds |
| Started | Jun 29 07:40:53 PM PDT 24 |
| Finished | Jun 29 08:28:56 PM PDT 24 |
| Peak memory | 618260 kb |
| Host | smart-c13c4718-07d7-4537-bf68-5056c826ffe8 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=40_000_000 +use_jtag_dmi=1 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=img_dev_exec_di sabled:4,sram_program:5,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2888276562 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_e2e_jtag_inject_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_jtag_inject_dev.2888276562 |
| Directory | /workspace/0.rom_e2e_jtag_inject_dev/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_jtag_inject_rma.2568939590 |
| Short name | T231 |
| Test name | |
| Test status | |
| Simulation time | 31422767605 ps |
| CPU time | 2961.9 seconds |
| Started | Jun 29 07:41:25 PM PDT 24 |
| Finished | Jun 29 08:30:47 PM PDT 24 |
| Peak memory | 617972 kb |
| Host | smart-0db2bada-a3ec-4f40-87d1-e2c689cda354 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=40_000_000 +use_jtag_dmi=1 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=img_rma_exec_di sabled:4,sram_program:5,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2568939590 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_e2e_jtag_inject_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_jtag_inject_rma.2568939590 |
| Directory | /workspace/0.rom_e2e_jtag_inject_rma/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_jtag_inject_test_unlocked0.3849514432 |
| Short name | T440 |
| Test name | |
| Test status | |
| Simulation time | 24650842053 ps |
| CPU time | 3016.57 seconds |
| Started | Jun 29 07:40:03 PM PDT 24 |
| Finished | Jun 29 08:30:21 PM PDT 24 |
| Peak memory | 618112 kb |
| Host | smart-a53e5db1-5bcc-426d-acff-2e3a8859476f |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=40_000_000 +use_jtag_dmi=1 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=img_test_unlock ed0_exec_disabled:4,sram_program:5,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3849514432 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_e2e_jtag_ inject_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_jtag_inject _test_unlocked0.3849514432 |
| Directory | /workspace/0.rom_e2e_jtag_inject_test_unlocked0/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_keymgr_init_rom_ext_invalid_meas.1080724656 |
| Short name | T1118 |
| Test name | |
| Test status | |
| Simulation time | 15600313760 ps |
| CPU time | 4017.35 seconds |
| Started | Jun 29 07:46:49 PM PDT 24 |
| Finished | Jun 29 08:53:47 PM PDT 24 |
| Peak memory | 608340 kb |
| Host | smart-d57bfb77-2c65-4588-a7cc-b961dcebd878 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=40_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=rom_e2e_keymgr_init_otp_invalid _meas:1:new_rules,otp_img_keymgr_otp_invalid_meas:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1080724656 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip _sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_keymgr_in it_rom_ext_invalid_meas.1080724656 |
| Directory | /workspace/0.rom_e2e_keymgr_init_rom_ext_invalid_meas/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_keymgr_init_rom_ext_meas.1922353679 |
| Short name | T1038 |
| Test name | |
| Test status | |
| Simulation time | 14572046612 ps |
| CPU time | 3851.55 seconds |
| Started | Jun 29 07:49:35 PM PDT 24 |
| Finished | Jun 29 08:53:47 PM PDT 24 |
| Peak memory | 608160 kb |
| Host | smart-7190dfb3-eadf-4129-8df6-67790dc40c41 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=40_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=rom_e2e_keymgr_init_otp_meas:1: new_rules,otp_img_keymgr_otp_meas:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1922353679 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_keymgr_init_rom_ext_meas.1922353679 |
| Directory | /workspace/0.rom_e2e_keymgr_init_rom_ext_meas/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_keymgr_init_rom_ext_no_meas.2812891024 |
| Short name | T1226 |
| Test name | |
| Test status | |
| Simulation time | 15063091260 ps |
| CPU time | 4424.27 seconds |
| Started | Jun 29 07:49:19 PM PDT 24 |
| Finished | Jun 29 09:03:04 PM PDT 24 |
| Peak memory | 607328 kb |
| Host | smart-beb6f065-7e48-4b6c-8b39-d00c9367e0cd |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=40_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=rom_e2e_keymgr_init_otp_no_meas :1:new_rules,otp_img_keymgr_otp_no_meas:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2812891024 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_keymgr_init_rom_ext _no_meas.2812891024 |
| Directory | /workspace/0.rom_e2e_keymgr_init_rom_ext_no_meas/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_shutdown_exception_c.3202171993 |
| Short name | T49 |
| Test name | |
| Test status | |
| Simulation time | 14951677771 ps |
| CPU time | 3951.01 seconds |
| Started | Jun 29 07:45:25 PM PDT 24 |
| Finished | Jun 29 08:51:17 PM PDT 24 |
| Peak memory | 607936 kb |
| Host | smart-946276b2-72fb-48db-8e17-bb9fb7a933c9 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=40000000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=rom_e2e_shutdown_exception_c:1:ne w_rules,otp_img_secret2_locked_rma:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3202171993 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_e2e_shu tdown_exception_c_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_ shutdown_exception_c.3202171993 |
| Directory | /workspace/0.rom_e2e_shutdown_exception_c/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_shutdown_output.2223144799 |
| Short name | T1134 |
| Test name | |
| Test status | |
| Simulation time | 29642634379 ps |
| CPU time | 3909.04 seconds |
| Started | Jun 29 07:48:57 PM PDT 24 |
| Finished | Jun 29 08:54:06 PM PDT 24 |
| Peak memory | 609300 kb |
| Host | smart-8a871eb6-33a5-474c-867b-fbab2f5f8628 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=20000000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_unsigned:1:ot_f lash_binary,otp_img_shutdown_output_test_unlocked0:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2223144799 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chi p_sw_rom_e2e_shutdown_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_shutdown_output.2223144799 |
| Directory | /workspace/0.rom_e2e_shutdown_output/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_smoke.1441194339 |
| Short name | T1140 |
| Test name | |
| Test status | |
| Simulation time | 15177312524 ps |
| CPU time | 4149.39 seconds |
| Started | Jun 29 07:44:44 PM PDT 24 |
| Finished | Jun 29 08:53:54 PM PDT 24 |
| Peak memory | 607248 kb |
| Host | smart-aec23317-71fe-4499-a9cd-8ea485be1061 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=40000000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=rom_e2e_smoke:1:new_rules,otp_img _secret2_locked_rma:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_to p/hw/dv/tools/sim.tcl +ntb_random_seed=1441194339 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_smoke.1441194339 |
| Directory | /workspace/0.rom_e2e_smoke/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_static_critical.3382339582 |
| Short name | T1181 |
| Test name | |
| Test status | |
| Simulation time | 16697067920 ps |
| CPU time | 4342.86 seconds |
| Started | Jun 29 07:47:29 PM PDT 24 |
| Finished | Jun 29 08:59:53 PM PDT 24 |
| Peak memory | 608136 kb |
| Host | smart-0c5242c0-2ba8-4e37-8cc3-c04cc5878afb |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=40000000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=rom_e2e_static_critical:1:new_rul es,otp_img_secret2_locked_rma:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3382339582 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_static_critical.3382339582 |
| Directory | /workspace/0.rom_e2e_static_critical/latest |
| Test location | /workspace/coverage/default/0.rom_keymgr_functest.3992314862 |
| Short name | T401 |
| Test name | |
| Test status | |
| Simulation time | 5165234980 ps |
| CPU time | 538.19 seconds |
| Started | Jun 29 07:40:16 PM PDT 24 |
| Finished | Jun 29 07:49:14 PM PDT 24 |
| Peak memory | 608132 kb |
| Host | smart-71a46b71-80b9-4d76-bc6a-525cf6a6bbdc |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=10_000_000 +sw_build_device=sim_dv +sw_images=keymgr_functest:1:new_rules,test_rom:0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3992314862 -ass ert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 0.rom_keymgr_functest.3992314862 |
| Directory | /workspace/0.rom_keymgr_functest/latest |
| Test location | /workspace/coverage/default/0.rom_volatile_raw_unlock.1258527833 |
| Short name | T646 |
| Test name | |
| Test status | |
| Simulation time | 2291109954 ps |
| CPU time | 115.91 seconds |
| Started | Jun 29 07:42:12 PM PDT 24 |
| Finished | Jun 29 07:44:09 PM PDT 24 |
| Peak memory | 614428 kb |
| Host | smart-2ec08482-5d12-47f9-bc9a-ec6ac31c5c66 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=200_000_000 +use_otp_image=OtpTypeLcStRaw +chip_clock_source=ChipClockSourceExternal48Mhz +rom_prod_mode=1 +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_test_key_0:1:ot_flash_binary,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1258527833 -assert nopostproc +UVM_ TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_volatile_raw_unlock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag e/default.vdb -cm_log /dev/null -cm_name 0.rom_volatile_raw_unlock.1258527833 |
| Directory | /workspace/0.rom_volatile_raw_unlock/latest |
| Test location | /workspace/coverage/default/1.chip_jtag_csr_rw.187471254 |
| Short name | T77 |
| Test name | |
| Test status | |
| Simulation time | 4361379440 ps |
| CPU time | 311.55 seconds |
| Started | Jun 29 07:42:06 PM PDT 24 |
| Finished | Jun 29 07:47:18 PM PDT 24 |
| Peak memory | 601748 kb |
| Host | smart-ef987069-10cb-4c54-8b22-6e5e56135a4f |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +csr_rw +create_jtag_riscv_map=1 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=187471254 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TE ST_SEQ=chip_jtag_csr_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.ch ip_jtag_csr_rw.187471254 |
| Directory | /workspace/1.chip_jtag_csr_rw/latest |
| Test location | /workspace/coverage/default/1.chip_jtag_mem_access.4012035443 |
| Short name | T153 |
| Test name | |
| Test status | |
| Simulation time | 13951594098 ps |
| CPU time | 1665.04 seconds |
| Started | Jun 29 07:42:16 PM PDT 24 |
| Finished | Jun 29 08:10:01 PM PDT 24 |
| Peak memory | 606896 kb |
| Host | smart-65d4b22b-c722-4f22-b32a-a35572327518 |
| User | root |
| Command | /workspace/default/simv +create_jtag_riscv_map=1 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4012035443 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_jtag_ mem_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_jtag_mem_access.4 012035443 |
| Directory | /workspace/1.chip_jtag_mem_access/latest |
| Test location | /workspace/coverage/default/1.chip_rv_dm_ndm_reset_req.1209806240 |
| Short name | T388 |
| Test name | |
| Test status | |
| Simulation time | 3797326236 ps |
| CPU time | 498.19 seconds |
| Started | Jun 29 07:50:36 PM PDT 24 |
| Finished | Jun 29 07:58:54 PM PDT 24 |
| Peak memory | 617780 kb |
| Host | smart-bfe48eee-3a39-407d-aa29-4554c5704e8f |
| User | root |
| Command | /workspace/default/simv +en_scb_tl_err_chk=0 +use_jtag_dmi=1 +sw_build_device=sim_dv +sw_images=rv_dm_ndm_reset_req_rma:1:new_rules,test_rom:0 +cdc_in strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1 209806240 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_rv_dm_ndm_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_rv_dm_ndm_reset_req.1209806240 |
| Directory | /workspace/1.chip_rv_dm_ndm_reset_req/latest |
| Test location | /workspace/coverage/default/1.chip_sival_flash_info_access.998905474 |
| Short name | T320 |
| Test name | |
| Test status | |
| Simulation time | 2901526800 ps |
| CPU time | 336.73 seconds |
| Started | Jun 29 07:43:04 PM PDT 24 |
| Finished | Jun 29 07:48:41 PM PDT 24 |
| Peak memory | 607128 kb |
| Host | smart-2f1b7a11-170d-44bc-9072-eadb834a1196 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStTestUnlocked0 +sw_build_device=sim_dv +sw_images=flash_ctrl_info_access_lc:1:new_rules,test_rom:0 +c dc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_s eed=998905474 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sival_flash_info_access.998905474 |
| Directory | /workspace/1.chip_sival_flash_info_access/latest |
| Test location | /workspace/coverage/default/1.chip_sw_adc_ctrl_sleep_debug_cable_wakeup.2662638764 |
| Short name | T339 |
| Test name | |
| Test status | |
| Simulation time | 18127158920 ps |
| CPU time | 607.12 seconds |
| Started | Jun 29 07:44:43 PM PDT 24 |
| Finished | Jun 29 07:54:51 PM PDT 24 |
| Peak memory | 616556 kb |
| Host | smart-da1090c7-eb55-4144-add2-eb5d6b4c75ba |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=adc_ctrl_sleep_debug_cable_wakeup_test:1:new_rules,test_rom: 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand om_seed=2662638764 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_adc_ctrl_sleep_debug_cable_wakeup_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_adc_ctrl_sleep_debug_cable_wakeup.2662638764 |
| Directory | /workspace/1.chip_sw_adc_ctrl_sleep_debug_cable_wakeup/latest |
| Test location | /workspace/coverage/default/1.chip_sw_aes_enc.3636245888 |
| Short name | T1000 |
| Test name | |
| Test status | |
| Simulation time | 2753637572 ps |
| CPU time | 287.11 seconds |
| Started | Jun 29 07:44:54 PM PDT 24 |
| Finished | Jun 29 07:49:41 PM PDT 24 |
| Peak memory | 609192 kb |
| Host | smart-63b589af-922d-4141-ada4-20aec9f1b064 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=22_000_000 +sw_build_device=sim_dv +sw_images=aes_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3636245888 -asser t nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag e/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_aes_enc.3636245888 |
| Directory | /workspace/1.chip_sw_aes_enc/latest |
| Test location | /workspace/coverage/default/1.chip_sw_aes_enc_jitter_en.2479009199 |
| Short name | T829 |
| Test name | |
| Test status | |
| Simulation time | 3086117731 ps |
| CPU time | 251.66 seconds |
| Started | Jun 29 07:44:06 PM PDT 24 |
| Finished | Jun 29 07:48:18 PM PDT 24 |
| Peak memory | 609168 kb |
| Host | smart-17c66566-764d-4521-996d-c386407c52ed |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=26_000_000 +en_jitter=1 +sw_build_device=sim_dv +sw_images=aes_smoketest:1:new_rules,test_rom:0 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2479 009199 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work space/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_aes_enc_jitter_en.2479009199 |
| Directory | /workspace/1.chip_sw_aes_enc_jitter_en/latest |
| Test location | /workspace/coverage/default/1.chip_sw_aes_enc_jitter_en_reduced_freq.138380079 |
| Short name | T996 |
| Test name | |
| Test status | |
| Simulation time | 2870981660 ps |
| CPU time | 243.99 seconds |
| Started | Jun 29 07:51:26 PM PDT 24 |
| Finished | Jun 29 07:55:30 PM PDT 24 |
| Peak memory | 609176 kb |
| Host | smart-b2813152-4a3d-4ca8-af20-8db9c7fc4729 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=26_000_000 +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=aes_smoketest:1:new_rules, test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=138380079 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_aes_enc_jitter_en_reduced_freq.138380079 |
| Directory | /workspace/1.chip_sw_aes_enc_jitter_en_reduced_freq/latest |
| Test location | /workspace/coverage/default/1.chip_sw_aes_entropy.3838151998 |
| Short name | T1133 |
| Test name | |
| Test status | |
| Simulation time | 2421442598 ps |
| CPU time | 229.36 seconds |
| Started | Jun 29 07:45:32 PM PDT 24 |
| Finished | Jun 29 07:49:22 PM PDT 24 |
| Peak memory | 607516 kb |
| Host | smart-4e594eeb-891a-4c72-8ea7-7252eb80a32b |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=15_000_000 +sw_build_device=sim_dv +sw_images=aes_entropy_test:1:new_rules,test_rom:0 +cdc_instrumentation _enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3838151998 -as sert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove rage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_aes_entropy.3838151998 |
| Directory | /workspace/1.chip_sw_aes_entropy/latest |
| Test location | /workspace/coverage/default/1.chip_sw_aes_idle.2693333955 |
| Short name | T1089 |
| Test name | |
| Test status | |
| Simulation time | 2393196176 ps |
| CPU time | 326.17 seconds |
| Started | Jun 29 07:48:41 PM PDT 24 |
| Finished | Jun 29 07:54:08 PM PDT 24 |
| Peak memory | 609160 kb |
| Host | smart-ad5bf144-2ded-4c97-9c3a-5b3948aa9db7 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=25_000_000 +sw_build_device=sim_dv +sw_images=aes_idle_test:1:new_rules,test_rom:0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2693333955 -asser t nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag e/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_aes_idle.2693333955 |
| Directory | /workspace/1.chip_sw_aes_idle/latest |
| Test location | /workspace/coverage/default/1.chip_sw_aes_masking_off.2619670547 |
| Short name | T898 |
| Test name | |
| Test status | |
| Simulation time | 3536779394 ps |
| CPU time | 278.94 seconds |
| Started | Jun 29 07:44:00 PM PDT 24 |
| Finished | Jun 29 07:48:40 PM PDT 24 |
| Peak memory | 609216 kb |
| Host | smart-39f381c9-5cbe-418e-8f17-307d724dd797 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=aes_masking_off_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2619670547 -assert nopostproc +UVM_TESTNA ME=chip_base_test +UVM_TEST_SEQ=chip_sw_aes_masking_off_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_aes_masking_off.2619670547 |
| Directory | /workspace/1.chip_sw_aes_masking_off/latest |
| Test location | /workspace/coverage/default/1.chip_sw_aes_smoketest.2096931930 |
| Short name | T963 |
| Test name | |
| Test status | |
| Simulation time | 2238428536 ps |
| CPU time | 274.29 seconds |
| Started | Jun 29 07:59:19 PM PDT 24 |
| Finished | Jun 29 08:03:54 PM PDT 24 |
| Peak memory | 606280 kb |
| Host | smart-7b51f2ae-a610-4f4f-b1d9-164a07e3dd04 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=aes_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2096931930 -assert nopostproc +UVM_TESTNAME=chip _base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_aes_smoketest.2096931930 |
| Directory | /workspace/1.chip_sw_aes_smoketest/latest |
| Test location | /workspace/coverage/default/1.chip_sw_alert_handler_entropy.693017302 |
| Short name | T1279 |
| Test name | |
| Test status | |
| Simulation time | 2965579481 ps |
| CPU time | 279.84 seconds |
| Started | Jun 29 07:44:41 PM PDT 24 |
| Finished | Jun 29 07:49:21 PM PDT 24 |
| Peak memory | 607852 kb |
| Host | smart-7ca9fc9b-9220-450f-a105-ffae39f27ff5 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=alert_handler_entropy_test:1:new_rules,test_ro m:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=693017302 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_alert_handler_entropy.693017302 |
| Directory | /workspace/1.chip_sw_alert_handler_entropy/latest |
| Test location | /workspace/coverage/default/1.chip_sw_alert_handler_escalation.1338767757 |
| Short name | T993 |
| Test name | |
| Test status | |
| Simulation time | 4867693528 ps |
| CPU time | 449.4 seconds |
| Started | Jun 29 07:46:42 PM PDT 24 |
| Finished | Jun 29 07:54:12 PM PDT 24 |
| Peak memory | 613752 kb |
| Host | smart-6e694e42-a68f-48dc-adea-1ae0c540c24e |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=alert_handler_escalation_test:1:new_rules,test _rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb _random_seed=1338767757 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_alert_handler_escalation_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_alert_handler_escalation.1338767757 |
| Directory | /workspace/1.chip_sw_alert_handler_escalation/latest |
| Test location | /workspace/coverage/default/1.chip_sw_alert_handler_lpg_clkoff.147595282 |
| Short name | T987 |
| Test name | |
| Test status | |
| Simulation time | 7102312054 ps |
| CPU time | 1742.53 seconds |
| Started | Jun 29 07:50:48 PM PDT 24 |
| Finished | Jun 29 08:19:51 PM PDT 24 |
| Peak memory | 608192 kb |
| Host | smart-6645f9cc-384e-4fe3-bc79-8ea6f243a911 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +sw_build_device=sim_dv +sw_images=alert_handler_lpg_clkoff_test:1:new_rules,test_r om:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r andom_seed=147595282 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_alert_handler_lpg_clkoff_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_alert_handler_lpg_clkoff.147595282 |
| Directory | /workspace/1.chip_sw_alert_handler_lpg_clkoff/latest |
| Test location | /workspace/coverage/default/1.chip_sw_alert_handler_lpg_reset_toggle.3542361993 |
| Short name | T863 |
| Test name | |
| Test status | |
| Simulation time | 7231524804 ps |
| CPU time | 1705.81 seconds |
| Started | Jun 29 07:45:09 PM PDT 24 |
| Finished | Jun 29 08:13:35 PM PDT 24 |
| Peak memory | 607916 kb |
| Host | smart-21709901-780c-41e8-bbcc-050a986d9fb8 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +sw_build_device=sim_dv +sw_images=alert_handler_lpg_reset_toggle_test:1:new_rules, test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3542361993 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_alert_handler_shorten_ping_wait_cycle_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_alert_handler_lpg_reset_togg le.3542361993 |
| Directory | /workspace/1.chip_sw_alert_handler_lpg_reset_toggle/latest |
| Test location | /workspace/coverage/default/1.chip_sw_alert_handler_lpg_sleep_mode_pings.1083103088 |
| Short name | T81 |
| Test name | |
| Test status | |
| Simulation time | 13527715048 ps |
| CPU time | 1717.48 seconds |
| Started | Jun 29 07:50:34 PM PDT 24 |
| Finished | Jun 29 08:19:12 PM PDT 24 |
| Peak memory | 608884 kb |
| Host | smart-ac3e2f38-64fa-477a-ad28-e673fa7cc752 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=alert_handler _lpg_sleep_mode_pings_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1083103088 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_alert_han dler_shorten_ping_wait_cycle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_alert_handler_lpg_sleep_mode_pings.1083103088 |
| Directory | /workspace/1.chip_sw_alert_handler_lpg_sleep_mode_pings/latest |
| Test location | /workspace/coverage/default/1.chip_sw_alert_handler_ping_ok.425427689 |
| Short name | T1240 |
| Test name | |
| Test status | |
| Simulation time | 8131217182 ps |
| CPU time | 1568.04 seconds |
| Started | Jun 29 07:49:38 PM PDT 24 |
| Finished | Jun 29 08:15:47 PM PDT 24 |
| Peak memory | 608232 kb |
| Host | smart-540f3945-90fc-4264-9a9f-0d21d671ce04 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=24000000 +sw_build_device=sim_dv +sw_images=alert_handler_ping_ok_test:1:new_rules,test_rom:0 +c dc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_s eed=425427689 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_alert_handler_ping_ok.425427689 |
| Directory | /workspace/1.chip_sw_alert_handler_ping_ok/latest |
| Test location | /workspace/coverage/default/1.chip_sw_alert_handler_ping_timeout.1021501911 |
| Short name | T1096 |
| Test name | |
| Test status | |
| Simulation time | 3778984756 ps |
| CPU time | 300.42 seconds |
| Started | Jun 29 07:46:58 PM PDT 24 |
| Finished | Jun 29 07:51:59 PM PDT 24 |
| Peak memory | 608092 kb |
| Host | smart-bc25c0a1-4b3e-4bb3-9274-eac91cd480ba |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=24000000 +sw_build_device=sim_dv +sw_images=alert_handler_ping_timeout_test:1:new_rules,test_rom :0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=1021501911 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_alert_handler_ping_timeout.1021501911 |
| Directory | /workspace/1.chip_sw_alert_handler_ping_timeout/latest |
| Test location | /workspace/coverage/default/1.chip_sw_aon_timer_irq.4135183666 |
| Short name | T341 |
| Test name | |
| Test status | |
| Simulation time | 4309055492 ps |
| CPU time | 362.01 seconds |
| Started | Jun 29 07:43:54 PM PDT 24 |
| Finished | Jun 29 07:49:57 PM PDT 24 |
| Peak memory | 607092 kb |
| Host | smart-c9fb30f3-e541-458d-8934-c5541be44ae1 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=aon_timer_irq_test:1:new_rules,test_rom:0 +cdc_instrumentati on_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4135183666 - assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co verage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_aon_timer_irq.4135183666 |
| Directory | /workspace/1.chip_sw_aon_timer_irq/latest |
| Test location | /workspace/coverage/default/1.chip_sw_aon_timer_sleep_wdog_sleep_pause.4007110820 |
| Short name | T418 |
| Test name | |
| Test status | |
| Simulation time | 7103831524 ps |
| CPU time | 412.1 seconds |
| Started | Jun 29 07:42:58 PM PDT 24 |
| Finished | Jun 29 07:49:51 PM PDT 24 |
| Peak memory | 609272 kb |
| Host | smart-e97aad2e-c524-4a91-a3c4-dc2294cba6e2 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=aon_timer_sleep_wdog_sleep_pause_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=4007110820 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_aon_timer_sleep_wdog_sleep_pause.4007110820 |
| Directory | /workspace/1.chip_sw_aon_timer_sleep_wdog_sleep_pause/latest |
| Test location | /workspace/coverage/default/1.chip_sw_aon_timer_smoketest.501650154 |
| Short name | T988 |
| Test name | |
| Test status | |
| Simulation time | 2992665022 ps |
| CPU time | 311.46 seconds |
| Started | Jun 29 07:53:04 PM PDT 24 |
| Finished | Jun 29 07:58:16 PM PDT 24 |
| Peak memory | 607104 kb |
| Host | smart-c4a8c52d-cfbe-4ec5-bed4-57beeab50952 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=aon_timer_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=501650154 -assert nopostproc +UVM_TESTNAME =chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 1.chip_sw_aon_timer_smoketest.501650154 |
| Directory | /workspace/1.chip_sw_aon_timer_smoketest/latest |
| Test location | /workspace/coverage/default/1.chip_sw_aon_timer_wdog_bite_reset.3529486741 |
| Short name | T1253 |
| Test name | |
| Test status | |
| Simulation time | 8577221376 ps |
| CPU time | 697.23 seconds |
| Started | Jun 29 07:47:42 PM PDT 24 |
| Finished | Jun 29 07:59:19 PM PDT 24 |
| Peak memory | 608312 kb |
| Host | smart-b60a1529-c693-4fb2-abf5-1c36e14769b8 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=aon_timer_wdog_bite_reset_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 3529486741 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_aon_timer_wdog_bite_reset.3529486741 |
| Directory | /workspace/1.chip_sw_aon_timer_wdog_bite_reset/latest |
| Test location | /workspace/coverage/default/1.chip_sw_aon_timer_wdog_lc_escalate.1553063837 |
| Short name | T394 |
| Test name | |
| Test status | |
| Simulation time | 5496647740 ps |
| CPU time | 646.99 seconds |
| Started | Jun 29 07:43:20 PM PDT 24 |
| Finished | Jun 29 07:54:07 PM PDT 24 |
| Peak memory | 609196 kb |
| Host | smart-e909719d-1414-479c-83a0-367bd0afb11e |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=aon_timer_wdog_lc_escalate_test:1:new_rules,test_rom:0 +cdc_ instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed =1553063837 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_aon_timer_wdog_lc_escalate.1553063837 |
| Directory | /workspace/1.chip_sw_aon_timer_wdog_lc_escalate/latest |
| Test location | /workspace/coverage/default/1.chip_sw_ast_clk_outputs.3541118617 |
| Short name | T989 |
| Test name | |
| Test status | |
| Simulation time | 6804703938 ps |
| CPU time | 1032.2 seconds |
| Started | Jun 29 07:48:42 PM PDT 24 |
| Finished | Jun 29 08:05:55 PM PDT 24 |
| Peak memory | 615024 kb |
| Host | smart-2e0d4ae6-8a41-47ba-9b71-e260abbbe030 |
| User | root |
| Command | /workspace/default/simv +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=ast_clk_outs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled= 1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3541118617 -assert nopo stproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_ast_clk_outputs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co verage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_ast_clk_outputs.3541118617 |
| Directory | /workspace/1.chip_sw_ast_clk_outputs/latest |
| Test location | /workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_lc.588291594 |
| Short name | T877 |
| Test name | |
| Test status | |
| Simulation time | 7645263711 ps |
| CPU time | 603.99 seconds |
| Started | Jun 29 07:49:51 PM PDT 24 |
| Finished | Jun 29 07:59:56 PM PDT 24 |
| Peak memory | 619148 kb |
| Host | smart-b2b57560-47d9-4a6e-8226-7d51beb2088e |
| User | root |
| Command | /workspace/default/simv +chip_clock_source=ChipClockSourceExternal48Mhz +sw_build_device=sim_dv +sw_images=clkmgr_external_clk_src_for_lc_test:1:new_r ules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim .tcl +ntb_random_seed=588291594 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_transition_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_clkmgr_external_clk_src_for_lc.588291594 |
| Directory | /workspace/1.chip_sw_clkmgr_external_clk_src_for_lc/latest |
| Test location | /workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_fast_dev.691374463 |
| Short name | T951 |
| Test name | |
| Test status | |
| Simulation time | 4109726474 ps |
| CPU time | 751.24 seconds |
| Started | Jun 29 07:48:55 PM PDT 24 |
| Finished | Jun 29 08:01:27 PM PDT 24 |
| Peak memory | 608628 kb |
| Host | smart-3a8b4a57-60cc-476e-b5b3-ba5095d910e4 |
| User | root |
| Command | /workspace/default/simv +chip_clock_source=ChipClockSourceExternal96Mhz +calibrate_usb_clk=1 +src_dec_state=DecLcStDev +sw_build_device=sim_dv +sw_ima ges=clkmgr_external_clk_src_for_sw_fast_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=691374463 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ= chip_sw_lc_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_cl kmgr_external_clk_src_for_sw_fast_dev.691374463 |
| Directory | /workspace/1.chip_sw_clkmgr_external_clk_src_for_sw_fast_dev/latest |
| Test location | /workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_fast_rma.985675601 |
| Short name | T1018 |
| Test name | |
| Test status | |
| Simulation time | 4331860640 ps |
| CPU time | 626.16 seconds |
| Started | Jun 29 07:48:27 PM PDT 24 |
| Finished | Jun 29 07:58:53 PM PDT 24 |
| Peak memory | 610804 kb |
| Host | smart-d9e13341-1ed1-46d6-9cb1-de518b0296c2 |
| User | root |
| Command | /workspace/default/simv +chip_clock_source=ChipClockSourceExternal96Mhz +calibrate_usb_clk=1 +src_dec_state=DecLcStRma +sw_build_device=sim_dv +sw_ima ges=clkmgr_external_clk_src_for_sw_fast_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=985675601 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ= chip_sw_lc_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_cl kmgr_external_clk_src_for_sw_fast_rma.985675601 |
| Directory | /workspace/1.chip_sw_clkmgr_external_clk_src_for_sw_fast_rma/latest |
| Test location | /workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0.1356348024 |
| Short name | T868 |
| Test name | |
| Test status | |
| Simulation time | 3293003480 ps |
| CPU time | 668.75 seconds |
| Started | Jun 29 07:49:48 PM PDT 24 |
| Finished | Jun 29 08:00:58 PM PDT 24 |
| Peak memory | 610796 kb |
| Host | smart-8f933f18-fbea-4e50-b9d8-a340d4c5a615 |
| User | root |
| Command | /workspace/default/simv +chip_clock_source=ChipClockSourceExternal96Mhz +calibrate_usb_clk=1 +src_dec_state=DecLcStTestUnlocked0 +sw_build_device=sim_ dv +sw_images=clkmgr_external_clk_src_for_sw_fast_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1356348024 -assert nopostproc +UVM_TESTNAME=chip_base_test +UV M_TEST_SEQ=chip_sw_lc_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1 .chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0.1356348024 |
| Directory | /workspace/1.chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0/latest |
| Test location | /workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_slow_dev.3215489948 |
| Short name | T908 |
| Test name | |
| Test status | |
| Simulation time | 4303095512 ps |
| CPU time | 655.77 seconds |
| Started | Jun 29 07:48:32 PM PDT 24 |
| Finished | Jun 29 07:59:28 PM PDT 24 |
| Peak memory | 608608 kb |
| Host | smart-d73e5c6d-8dba-4881-9420-e63df19ef18e |
| User | root |
| Command | /workspace/default/simv +chip_clock_source=ChipClockSourceExternal48Mhz +calibrate_usb_clk=1 +src_dec_state=DecLcStDev +sw_build_device=sim_dv +sw_ima ges=clkmgr_external_clk_src_for_sw_slow_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3215489948 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ =chip_sw_lc_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_c lkmgr_external_clk_src_for_sw_slow_dev.3215489948 |
| Directory | /workspace/1.chip_sw_clkmgr_external_clk_src_for_sw_slow_dev/latest |
| Test location | /workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_slow_rma.514982242 |
| Short name | T1058 |
| Test name | |
| Test status | |
| Simulation time | 4717903742 ps |
| CPU time | 741.75 seconds |
| Started | Jun 29 07:48:42 PM PDT 24 |
| Finished | Jun 29 08:01:04 PM PDT 24 |
| Peak memory | 609640 kb |
| Host | smart-00629d2a-b9d1-42ee-b0f5-eb6defdfa869 |
| User | root |
| Command | /workspace/default/simv +chip_clock_source=ChipClockSourceExternal48Mhz +calibrate_usb_clk=1 +src_dec_state=DecLcStRma +sw_build_device=sim_dv +sw_ima ges=clkmgr_external_clk_src_for_sw_slow_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=514982242 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ= chip_sw_lc_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_cl kmgr_external_clk_src_for_sw_slow_rma.514982242 |
| Directory | /workspace/1.chip_sw_clkmgr_external_clk_src_for_sw_slow_rma/latest |
| Test location | /workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0.3641208391 |
| Short name | T1009 |
| Test name | |
| Test status | |
| Simulation time | 4321858010 ps |
| CPU time | 887.65 seconds |
| Started | Jun 29 07:49:00 PM PDT 24 |
| Finished | Jun 29 08:03:48 PM PDT 24 |
| Peak memory | 609664 kb |
| Host | smart-3d346f0f-396e-4910-869e-f2a610735262 |
| User | root |
| Command | /workspace/default/simv +chip_clock_source=ChipClockSourceExternal48Mhz +calibrate_usb_clk=1 +src_dec_state=DecLcStTestUnlocked0 +sw_build_device=sim_ dv +sw_images=clkmgr_external_clk_src_for_sw_slow_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3641208391 -assert nopostproc +UVM_TESTNAME=chip_base_test +UV M_TEST_SEQ=chip_sw_lc_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1 .chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0.3641208391 |
| Directory | /workspace/1.chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0/latest |
| Test location | /workspace/coverage/default/1.chip_sw_clkmgr_jitter.3028135102 |
| Short name | T928 |
| Test name | |
| Test status | |
| Simulation time | 2440152429 ps |
| CPU time | 172.3 seconds |
| Started | Jun 29 07:48:03 PM PDT 24 |
| Finished | Jun 29 07:50:55 PM PDT 24 |
| Peak memory | 607132 kb |
| Host | smart-1ad2e6ee-f8d4-476f-bc10-d58b904aebd1 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_jitter_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3028135102 -assert nopostproc +UVM_TESTNAME =chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 1.chip_sw_clkmgr_jitter.3028135102 |
| Directory | /workspace/1.chip_sw_clkmgr_jitter/latest |
| Test location | /workspace/coverage/default/1.chip_sw_clkmgr_jitter_frequency.716082213 |
| Short name | T966 |
| Test name | |
| Test status | |
| Simulation time | 3938367500 ps |
| CPU time | 349.43 seconds |
| Started | Jun 29 07:50:18 PM PDT 24 |
| Finished | Jun 29 07:56:08 PM PDT 24 |
| Peak memory | 607088 kb |
| Host | smart-1ca80584-3b89-4780-9fea-1272551b8146 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_jitter_frequency_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=716082213 -assert nopostproc +UVM _TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm _log /dev/null -cm_name 1.chip_sw_clkmgr_jitter_frequency.716082213 |
| Directory | /workspace/1.chip_sw_clkmgr_jitter_frequency/latest |
| Test location | /workspace/coverage/default/1.chip_sw_clkmgr_jitter_reduced_freq.1398343158 |
| Short name | T949 |
| Test name | |
| Test status | |
| Simulation time | 3539735607 ps |
| CPU time | 198.84 seconds |
| Started | Jun 29 07:51:44 PM PDT 24 |
| Finished | Jun 29 07:55:04 PM PDT 24 |
| Peak memory | 607404 kb |
| Host | smart-0934007b-843c-4e22-b5d3-d5a869b8cea2 |
| User | root |
| Command | /workspace/default/simv +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=clkmgr_jitter_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1398343158 -assert nop ostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def ault.vdb -cm_log /dev/null -cm_name 1.chip_sw_clkmgr_jitter_reduced_freq.1398343158 |
| Directory | /workspace/1.chip_sw_clkmgr_jitter_reduced_freq/latest |
| Test location | /workspace/coverage/default/1.chip_sw_clkmgr_off_aes_trans.563374020 |
| Short name | T846 |
| Test name | |
| Test status | |
| Simulation time | 4773458308 ps |
| CPU time | 456.79 seconds |
| Started | Jun 29 07:48:05 PM PDT 24 |
| Finished | Jun 29 07:55:42 PM PDT 24 |
| Peak memory | 609200 kb |
| Host | smart-d3231074-1026-40db-a955-b2e99c420b50 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_off_aes_trans_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=563374020 -assert nopostproc +UVM_TE STNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo g /dev/null -cm_name 1.chip_sw_clkmgr_off_aes_trans.563374020 |
| Directory | /workspace/1.chip_sw_clkmgr_off_aes_trans/latest |
| Test location | /workspace/coverage/default/1.chip_sw_clkmgr_off_hmac_trans.3733572558 |
| Short name | T990 |
| Test name | |
| Test status | |
| Simulation time | 5596770166 ps |
| CPU time | 511.88 seconds |
| Started | Jun 29 07:49:37 PM PDT 24 |
| Finished | Jun 29 07:58:10 PM PDT 24 |
| Peak memory | 607884 kb |
| Host | smart-b408091e-2317-4c0e-892c-b6a9ea2f6591 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_off_hmac_trans_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3733572558 -assert nopostproc +UVM_ TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_ log /dev/null -cm_name 1.chip_sw_clkmgr_off_hmac_trans.3733572558 |
| Directory | /workspace/1.chip_sw_clkmgr_off_hmac_trans/latest |
| Test location | /workspace/coverage/default/1.chip_sw_clkmgr_off_kmac_trans.1101025038 |
| Short name | T1001 |
| Test name | |
| Test status | |
| Simulation time | 4038976994 ps |
| CPU time | 554.12 seconds |
| Started | Jun 29 07:48:44 PM PDT 24 |
| Finished | Jun 29 07:57:58 PM PDT 24 |
| Peak memory | 607612 kb |
| Host | smart-cde43209-b17c-46ce-b3ea-c895cd2f8901 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_off_kmac_trans_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1101025038 -assert nopostproc +UVM_ TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_ log /dev/null -cm_name 1.chip_sw_clkmgr_off_kmac_trans.1101025038 |
| Directory | /workspace/1.chip_sw_clkmgr_off_kmac_trans/latest |
| Test location | /workspace/coverage/default/1.chip_sw_clkmgr_off_otbn_trans.4164202525 |
| Short name | T1231 |
| Test name | |
| Test status | |
| Simulation time | 4784301048 ps |
| CPU time | 562.87 seconds |
| Started | Jun 29 07:48:04 PM PDT 24 |
| Finished | Jun 29 07:57:27 PM PDT 24 |
| Peak memory | 607904 kb |
| Host | smart-3cb18409-e662-42df-b656-92b07c66f0d5 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_off_otbn_trans_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4164202525 -assert nopostproc +UVM_ TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_ log /dev/null -cm_name 1.chip_sw_clkmgr_off_otbn_trans.4164202525 |
| Directory | /workspace/1.chip_sw_clkmgr_off_otbn_trans/latest |
| Test location | /workspace/coverage/default/1.chip_sw_clkmgr_off_peri.2931436037 |
| Short name | T378 |
| Test name | |
| Test status | |
| Simulation time | 10793052568 ps |
| CPU time | 1294.11 seconds |
| Started | Jun 29 07:48:29 PM PDT 24 |
| Finished | Jun 29 08:10:03 PM PDT 24 |
| Peak memory | 609188 kb |
| Host | smart-f80db96e-95ff-425c-bd38-df45323cb6f3 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=30_000_000 +sw_build_device=sim_dv +sw_images=clkmgr_off_peri_test:1:new_rules,test_rom:0 +cdc_instrumenta tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2931436037 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/ coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_clkmgr_off_peri.2931436037 |
| Directory | /workspace/1.chip_sw_clkmgr_off_peri/latest |
| Test location | /workspace/coverage/default/1.chip_sw_clkmgr_reset_frequency.1563236555 |
| Short name | T975 |
| Test name | |
| Test status | |
| Simulation time | 2751637051 ps |
| CPU time | 371.7 seconds |
| Started | Jun 29 07:49:10 PM PDT 24 |
| Finished | Jun 29 07:55:22 PM PDT 24 |
| Peak memory | 607740 kb |
| Host | smart-031874c1-8b55-4380-b5a5-d0f7b187fd3e |
| User | root |
| Command | /workspace/default/simv +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=clkmgr_reset_frequency_test:1:new_rules,test_rom:0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1563236555 -a ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov erage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_clkmgr_reset_frequency.1563236555 |
| Directory | /workspace/1.chip_sw_clkmgr_reset_frequency/latest |
| Test location | /workspace/coverage/default/1.chip_sw_clkmgr_sleep_frequency.3233493828 |
| Short name | T837 |
| Test name | |
| Test status | |
| Simulation time | 4748649856 ps |
| CPU time | 579.01 seconds |
| Started | Jun 29 07:49:51 PM PDT 24 |
| Finished | Jun 29 07:59:30 PM PDT 24 |
| Peak memory | 609256 kb |
| Host | smart-bbcf9d61-c4a4-43b5-8996-beac77b69e30 |
| User | root |
| Command | /workspace/default/simv +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=clkmgr_sleep_frequency_test:1:new_rules,test_rom:0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3233493828 -a ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov erage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_clkmgr_sleep_frequency.3233493828 |
| Directory | /workspace/1.chip_sw_clkmgr_sleep_frequency/latest |
| Test location | /workspace/coverage/default/1.chip_sw_clkmgr_smoketest.1154404192 |
| Short name | T1042 |
| Test name | |
| Test status | |
| Simulation time | 3108540880 ps |
| CPU time | 323.7 seconds |
| Started | Jun 29 07:52:26 PM PDT 24 |
| Finished | Jun 29 07:57:50 PM PDT 24 |
| Peak memory | 607124 kb |
| Host | smart-d9919c76-c58c-4b61-a398-0bf3af9e7fa8 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1154404192 -assert nopostproc +UVM_TESTNAME=c hip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n ull -cm_name 1.chip_sw_clkmgr_smoketest.1154404192 |
| Directory | /workspace/1.chip_sw_clkmgr_smoketest/latest |
| Test location | /workspace/coverage/default/1.chip_sw_csrng_edn_concurrency.1859879539 |
| Short name | T1281 |
| Test name | |
| Test status | |
| Simulation time | 22270920588 ps |
| CPU time | 5504.99 seconds |
| Started | Jun 29 07:48:31 PM PDT 24 |
| Finished | Jun 29 09:20:17 PM PDT 24 |
| Peak memory | 608200 kb |
| Host | smart-1c93dc8b-67f2-45c7-b761-35f1ab127d2e |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=140_000_000 +rng_srate_value_min=15 +rng_srate_value_max=20 +sw_build_device=sim_dv +sw_images=csrng_edn_c oncurrency_test:1:new_rules,test_rom:0 +accelerate_cold_power_up_time=3 +accelerate_regulators_power_up_time=2 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1859879539 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd b -cm_log /dev/null -cm_name 1.chip_sw_csrng_edn_concurrency.1859879539 |
| Directory | /workspace/1.chip_sw_csrng_edn_concurrency/latest |
| Test location | /workspace/coverage/default/1.chip_sw_csrng_fuse_en_sw_app_read_test.1685148447 |
| Short name | T1020 |
| Test name | |
| Test status | |
| Simulation time | 5053872120 ps |
| CPU time | 534.75 seconds |
| Started | Jun 29 07:51:31 PM PDT 24 |
| Finished | Jun 29 08:00:26 PM PDT 24 |
| Peak memory | 609180 kb |
| Host | smart-ffdb6917-af6f-45d6-95b5-86b895e782b6 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=15_000_000 +sw_build_device=sim_dv +sw_images=csrng_fuse_en_sw_app_read:1:new_rules,test_rom:0 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16851 48447 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_entropy_src_fuse_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_csrng_fuse_en_sw_app_read_test.1685148447 |
| Directory | /workspace/1.chip_sw_csrng_fuse_en_sw_app_read_test/latest |
| Test location | /workspace/coverage/default/1.chip_sw_csrng_kat_test.4294295764 |
| Short name | T415 |
| Test name | |
| Test status | |
| Simulation time | 3089179500 ps |
| CPU time | 197.98 seconds |
| Started | Jun 29 07:51:30 PM PDT 24 |
| Finished | Jun 29 07:54:48 PM PDT 24 |
| Peak memory | 607612 kb |
| Host | smart-7891306d-d6b9-4e87-887d-19e677cf2902 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=csrng_kat_test:1:new_rules,test_rom:0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4294295764 -asse rt nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera ge/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_csrng_kat_test.4294295764 |
| Directory | /workspace/1.chip_sw_csrng_kat_test/latest |
| Test location | /workspace/coverage/default/1.chip_sw_csrng_lc_hw_debug_en_test.4224207162 |
| Short name | T915 |
| Test name | |
| Test status | |
| Simulation time | 7603750980 ps |
| CPU time | 666.47 seconds |
| Started | Jun 29 07:45:31 PM PDT 24 |
| Finished | Jun 29 07:56:38 PM PDT 24 |
| Peak memory | 609172 kb |
| Host | smart-24bb7945-f199-4627-a3e1-aa843ae18098 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=15_000_000 +rng_srate_value_min=15 +use_otp_image=OtpTypeLcStTestUnlocked0 +sw_build_device=sim_dv +sw_ima ges=csrng_lc_hw_debug_en_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4224207162 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_csrng_ lc_hw_debug_en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_csr ng_lc_hw_debug_en_test.4224207162 |
| Directory | /workspace/1.chip_sw_csrng_lc_hw_debug_en_test/latest |
| Test location | /workspace/coverage/default/1.chip_sw_csrng_smoketest.2679183862 |
| Short name | T902 |
| Test name | |
| Test status | |
| Simulation time | 2757038190 ps |
| CPU time | 292.06 seconds |
| Started | Jun 29 07:52:32 PM PDT 24 |
| Finished | Jun 29 07:57:25 PM PDT 24 |
| Peak memory | 607096 kb |
| Host | smart-0b833385-0dba-4953-b8bb-e516d508f825 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=csrng_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2679183862 -assert nopostproc +UVM_TESTNAME=ch ip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu ll -cm_name 1.chip_sw_csrng_smoketest.2679183862 |
| Directory | /workspace/1.chip_sw_csrng_smoketest/latest |
| Test location | /workspace/coverage/default/1.chip_sw_data_integrity_escalation.3805496434 |
| Short name | T1201 |
| Test name | |
| Test status | |
| Simulation time | 5057292000 ps |
| CPU time | 626.34 seconds |
| Started | Jun 29 07:42:00 PM PDT 24 |
| Finished | Jun 29 07:52:27 PM PDT 24 |
| Peak memory | 607500 kb |
| Host | smart-f6edff00-c6f1-45bb-99c1-feaa1caf8db6 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=data_integrity_escalation_reset_test:1:new_rules,test_ro m:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=3805496434 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_data_integrity_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_data_integrity_escalation.3805496434 |
| Directory | /workspace/1.chip_sw_data_integrity_escalation/latest |
| Test location | /workspace/coverage/default/1.chip_sw_edn_auto_mode.1429518992 |
| Short name | T84 |
| Test name | |
| Test status | |
| Simulation time | 4593900280 ps |
| CPU time | 1120.45 seconds |
| Started | Jun 29 07:46:09 PM PDT 24 |
| Finished | Jun 29 08:04:50 PM PDT 24 |
| Peak memory | 608132 kb |
| Host | smart-b356ba17-7038-4935-9c50-536a03027a05 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +rng_srate_value=5 +sw_build_device=sim_dv +sw_images=edn_auto_mode:1:new_rules,test_rom:0 +acc elerate_cold_power_up_time=3 +accelerate_regulators_power_up_time=2 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1429518992 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ =chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_edn_ auto_mode.1429518992 |
| Directory | /workspace/1.chip_sw_edn_auto_mode/latest |
| Test location | /workspace/coverage/default/1.chip_sw_edn_boot_mode.10606427 |
| Short name | T448 |
| Test name | |
| Test status | |
| Simulation time | 3395926224 ps |
| CPU time | 654.4 seconds |
| Started | Jun 29 07:45:35 PM PDT 24 |
| Finished | Jun 29 07:56:30 PM PDT 24 |
| Peak memory | 609308 kb |
| Host | smart-2164b1b6-6308-4eba-a420-4965cd70f376 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +rng_srate_value=5 +sw_build_device=sim_dv +sw_images=edn_boot_mode:1:new_rules,test_rom:0 +acc elerate_cold_power_up_time=3 +accelerate_regulators_power_up_time=2 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10606427 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=c hip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_edn_bo ot_mode.10606427 |
| Directory | /workspace/1.chip_sw_edn_boot_mode/latest |
| Test location | /workspace/coverage/default/1.chip_sw_edn_entropy_reqs.3637312667 |
| Short name | T446 |
| Test name | |
| Test status | |
| Simulation time | 6039373092 ps |
| CPU time | 1321.54 seconds |
| Started | Jun 29 07:53:53 PM PDT 24 |
| Finished | Jun 29 08:15:55 PM PDT 24 |
| Peak memory | 609316 kb |
| Host | smart-ae865035-ae8e-415e-b897-c70bd4b08ddd |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=15000000 +rng_srate_value_min=15 +rng_srate_value_max=30 +sw_build_device=sim_dv +sw_images=entropy_src_ed n_reqs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3637312667 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_edn_entropy_reqs.3637312667 |
| Directory | /workspace/1.chip_sw_edn_entropy_reqs/latest |
| Test location | /workspace/coverage/default/1.chip_sw_edn_kat.4151006754 |
| Short name | T1166 |
| Test name | |
| Test status | |
| Simulation time | 3646872384 ps |
| CPU time | 615.39 seconds |
| Started | Jun 29 07:44:48 PM PDT 24 |
| Finished | Jun 29 07:55:04 PM PDT 24 |
| Peak memory | 614540 kb |
| Host | smart-b0079c31-bfc1-49f6-b348-a57c9566b9d9 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +rng_srate_value=5 +disable_assert_edn_output_diff_from_prev=1 +sw_build_device=sim_dv +sw_imag es=edn_kat:1:new_rules,test_rom:0 +accelerate_cold_power_up_time=3 +accelerate_regulators_power_up_time=2 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4151006754 -assert nopostproc +UVM _TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm _log /dev/null -cm_name 1.chip_sw_edn_kat.4151006754 |
| Directory | /workspace/1.chip_sw_edn_kat/latest |
| Test location | /workspace/coverage/default/1.chip_sw_edn_sw_mode.1507768649 |
| Short name | T994 |
| Test name | |
| Test status | |
| Simulation time | 9647986768 ps |
| CPU time | 2208.14 seconds |
| Started | Jun 29 07:45:22 PM PDT 24 |
| Finished | Jun 29 08:22:10 PM PDT 24 |
| Peak memory | 609156 kb |
| Host | smart-2053132d-0ce4-409a-9e78-a2335310cc5a |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=edn_sw_mode:1:new_rules,test_rom:0 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1507768649 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/ default.vdb -cm_log /dev/null -cm_name 1.chip_sw_edn_sw_mode.1507768649 |
| Directory | /workspace/1.chip_sw_edn_sw_mode/latest |
| Test location | /workspace/coverage/default/1.chip_sw_entropy_src_ast_rng_req.724313640 |
| Short name | T1221 |
| Test name | |
| Test status | |
| Simulation time | 2790289650 ps |
| CPU time | 336.49 seconds |
| Started | Jun 29 07:46:57 PM PDT 24 |
| Finished | Jun 29 07:52:34 PM PDT 24 |
| Peak memory | 607572 kb |
| Host | smart-bd3c7ff4-ec89-42e2-897f-525d49248f8b |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=15_000_000 +sw_build_device=sim_dv +sw_images=entropy_src_ast_rng_req_test:1:new_rules,test_rom:0 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72 4313640 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_entropy_src_ast_rng_req.724313640 |
| Directory | /workspace/1.chip_sw_entropy_src_ast_rng_req/latest |
| Test location | /workspace/coverage/default/1.chip_sw_entropy_src_csrng.3471565195 |
| Short name | T298 |
| Test name | |
| Test status | |
| Simulation time | 7487207850 ps |
| CPU time | 1492.1 seconds |
| Started | Jun 29 07:45:25 PM PDT 24 |
| Finished | Jun 29 08:10:17 PM PDT 24 |
| Peak memory | 609292 kb |
| Host | smart-b46be661-1562-4b08-9de2-a22ffaafe8c3 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=50_000_000 +rng_srate_value_min=15 +rng_srate_value_max=30 +sw_build_device=sim_dv +sw_images=entropy_src_ csrng_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3471565195 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_entropy_src_csrng.3471565195 |
| Directory | /workspace/1.chip_sw_entropy_src_csrng/latest |
| Test location | /workspace/coverage/default/1.chip_sw_entropy_src_kat_test.2469559992 |
| Short name | T1234 |
| Test name | |
| Test status | |
| Simulation time | 2509903560 ps |
| CPU time | 238.3 seconds |
| Started | Jun 29 07:43:59 PM PDT 24 |
| Finished | Jun 29 07:47:57 PM PDT 24 |
| Peak memory | 607116 kb |
| Host | smart-c847c6c3-25a4-41f2-8e3f-e5e94268964d |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=entropy_src_kat_test:1:new_rules,test_rom:0 +cdc_instrumenta tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2469559992 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/ coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_entropy_src_kat_test.2469559992 |
| Directory | /workspace/1.chip_sw_entropy_src_kat_test/latest |
| Test location | /workspace/coverage/default/1.chip_sw_entropy_src_smoketest.4030510114 |
| Short name | T285 |
| Test name | |
| Test status | |
| Simulation time | 3743677480 ps |
| CPU time | 580.54 seconds |
| Started | Jun 29 07:53:11 PM PDT 24 |
| Finished | Jun 29 08:02:52 PM PDT 24 |
| Peak memory | 609204 kb |
| Host | smart-29857bc9-a045-418e-92f1-584a391e44ca |
| User | root |
| Command | /workspace/default/simv +rng_srate_value_min=15 +rng_srate_value_max=30 +sw_build_device=sim_dv +sw_images=entropy_src_smoketest:1:new_rules,test_rom: 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand om_seed=4030510114 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_entropy_src_smoketest.4030510114 |
| Directory | /workspace/1.chip_sw_entropy_src_smoketest/latest |
| Test location | /workspace/coverage/default/1.chip_sw_example_concurrency.1245202382 |
| Short name | T1207 |
| Test name | |
| Test status | |
| Simulation time | 2552005626 ps |
| CPU time | 259.03 seconds |
| Started | Jun 29 07:42:46 PM PDT 24 |
| Finished | Jun 29 07:47:06 PM PDT 24 |
| Peak memory | 609192 kb |
| Host | smart-5d13c8fa-4582-48e8-91c6-2c5d8cdb5498 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=example_concurrency_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1245202382 -assert nopostproc +UVM_TE STNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo g /dev/null -cm_name 1.chip_sw_example_concurrency.1245202382 |
| Directory | /workspace/1.chip_sw_example_concurrency/latest |
| Test location | /workspace/coverage/default/1.chip_sw_example_flash.1118946011 |
| Short name | T921 |
| Test name | |
| Test status | |
| Simulation time | 3233093820 ps |
| CPU time | 264.57 seconds |
| Started | Jun 29 07:39:58 PM PDT 24 |
| Finished | Jun 29 07:44:23 PM PDT 24 |
| Peak memory | 609140 kb |
| Host | smart-ef3a8042-337f-4d75-b158-388700c68ad7 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=example_test_from_flash:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1118946011 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_example_flash.1118946011 |
| Directory | /workspace/1.chip_sw_example_flash/latest |
| Test location | /workspace/coverage/default/1.chip_sw_example_manufacturer.75621288 |
| Short name | T1218 |
| Test name | |
| Test status | |
| Simulation time | 2559024920 ps |
| CPU time | 238.3 seconds |
| Started | Jun 29 07:41:25 PM PDT 24 |
| Finished | Jun 29 07:45:24 PM PDT 24 |
| Peak memory | 607128 kb |
| Host | smart-0518e2bc-acd9-46a4-9399-644a1e333cb5 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=example_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75621288 -assert nopostproc +UVM_TESTNAME=chip_ba se_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 1.chip_sw_example_manufacturer.75621288 |
| Directory | /workspace/1.chip_sw_example_manufacturer/latest |
| Test location | /workspace/coverage/default/1.chip_sw_example_rom.72240574 |
| Short name | T1171 |
| Test name | |
| Test status | |
| Simulation time | 2730460296 ps |
| CPU time | 124.45 seconds |
| Started | Jun 29 07:40:43 PM PDT 24 |
| Finished | Jun 29 07:42:49 PM PDT 24 |
| Peak memory | 607288 kb |
| Host | smart-bb208ed4-0fdc-48ad-9ee6-2554fd21e3e0 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:test_in_rom:new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72240574 -assert nopostproc +UVM_TESTNA ME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 1.chip_sw_example_rom.72240574 |
| Directory | /workspace/1.chip_sw_example_rom/latest |
| Test location | /workspace/coverage/default/1.chip_sw_exit_test_unlocked_bootstrap.1259411548 |
| Short name | T154 |
| Test name | |
| Test status | |
| Simulation time | 59813143655 ps |
| CPU time | 11695 seconds |
| Started | Jun 29 07:41:58 PM PDT 24 |
| Finished | Jun 29 10:56:55 PM PDT 24 |
| Peak memory | 622316 kb |
| Host | smart-d2e45237-8111-4359-914d-11c36b361490 |
| User | root |
| Command | /workspace/default/simv +flash_program_latency=5 +sw_test_timeout_ns=150_000_000 +sw_build_device=sim_dv +sw_images=exit_test_unlocked_bootstrap:1:new _rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/s im.tcl +ntb_random_seed=1259411548 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_exit_test_unlocked_bootstrap_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_exit_test_unlocked_bootstrap.1259411548 |
| Directory | /workspace/1.chip_sw_exit_test_unlocked_bootstrap/latest |
| Test location | /workspace/coverage/default/1.chip_sw_flash_crash_alert.179639905 |
| Short name | T1205 |
| Test name | |
| Test status | |
| Simulation time | 5132208848 ps |
| CPU time | 568.18 seconds |
| Started | Jun 29 07:50:01 PM PDT 24 |
| Finished | Jun 29 07:59:30 PM PDT 24 |
| Peak memory | 608584 kb |
| Host | smart-5c59bade-f4b7-4dcc-93c2-10ec5b50d524 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=8_000_000 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1: new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tool s/sim.tcl +ntb_random_seed=179639905 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_flash_host_gnt_err_inj_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_flash_crash_alert.179639905 |
| Directory | /workspace/1.chip_sw_flash_crash_alert/latest |
| Test location | /workspace/coverage/default/1.chip_sw_flash_ctrl_access.200265824 |
| Short name | T831 |
| Test name | |
| Test status | |
| Simulation time | 5543503060 ps |
| CPU time | 935.69 seconds |
| Started | Jun 29 07:42:54 PM PDT 24 |
| Finished | Jun 29 07:58:30 PM PDT 24 |
| Peak memory | 607132 kb |
| Host | smart-2b10097f-c0e6-4fd1-ac0f-3c87423a49a8 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=flash_ctrl_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=200265824 -assert nopostproc +UVM_TESTNAME=chi p_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul l -cm_name 1.chip_sw_flash_ctrl_access.200265824 |
| Directory | /workspace/1.chip_sw_flash_ctrl_access/latest |
| Test location | /workspace/coverage/default/1.chip_sw_flash_ctrl_access_jitter_en.1828349035 |
| Short name | T1045 |
| Test name | |
| Test status | |
| Simulation time | 6527995607 ps |
| CPU time | 1224.79 seconds |
| Started | Jun 29 07:42:01 PM PDT 24 |
| Finished | Jun 29 08:02:27 PM PDT 24 |
| Peak memory | 609160 kb |
| Host | smart-ab46aeb9-bcdf-4040-9ae1-c8a87b2620ac |
| User | root |
| Command | /workspace/default/simv +en_jitter=1 +sw_build_device=sim_dv +sw_images=flash_ctrl_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1828349035 -assert nopostproc +UV M_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -c m_log /dev/null -cm_name 1.chip_sw_flash_ctrl_access_jitter_en.1828349035 |
| Directory | /workspace/1.chip_sw_flash_ctrl_access_jitter_en/latest |
| Test location | /workspace/coverage/default/1.chip_sw_flash_ctrl_access_jitter_en_reduced_freq.3925820934 |
| Short name | T924 |
| Test name | |
| Test status | |
| Simulation time | 7381618110 ps |
| CPU time | 1165.17 seconds |
| Started | Jun 29 07:51:33 PM PDT 24 |
| Finished | Jun 29 08:10:58 PM PDT 24 |
| Peak memory | 609316 kb |
| Host | smart-7f32fee5-d21b-4462-8f80-743cb638d20a |
| User | root |
| Command | /workspace/default/simv +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=flash_ctrl_test:1:new_rules,test_rom:0 +cdc_instrumentati on_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3925820934 - assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co verage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_flash_ctrl_access_jitter_en_reduced_freq.3925820934 |
| Directory | /workspace/1.chip_sw_flash_ctrl_access_jitter_en_reduced_freq/latest |
| Test location | /workspace/coverage/default/1.chip_sw_flash_ctrl_clock_freqs.3469725739 |
| Short name | T1126 |
| Test name | |
| Test status | |
| Simulation time | 5665225090 ps |
| CPU time | 1113.23 seconds |
| Started | Jun 29 07:43:18 PM PDT 24 |
| Finished | Jun 29 08:01:52 PM PDT 24 |
| Peak memory | 609184 kb |
| Host | smart-da289fed-432d-4176-af5f-20d13bbfe29e |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=flash_ctrl_clock_freqs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3469725739 -assert nopostproc +UVM _TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm _log /dev/null -cm_name 1.chip_sw_flash_ctrl_clock_freqs.3469725739 |
| Directory | /workspace/1.chip_sw_flash_ctrl_clock_freqs/latest |
| Test location | /workspace/coverage/default/1.chip_sw_flash_ctrl_idle_low_power.3991098061 |
| Short name | T964 |
| Test name | |
| Test status | |
| Simulation time | 3975362592 ps |
| CPU time | 369.86 seconds |
| Started | Jun 29 07:45:27 PM PDT 24 |
| Finished | Jun 29 07:51:37 PM PDT 24 |
| Peak memory | 607184 kb |
| Host | smart-504c2703-bccc-4b2e-8d90-58e4f3e8c0fc |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=flash_ctrl_idle_low_power_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3991098061 -assert nopostproc + UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_flash_ctrl_idle_low_power.3991098061 |
| Directory | /workspace/1.chip_sw_flash_ctrl_idle_low_power/latest |
| Test location | /workspace/coverage/default/1.chip_sw_flash_ctrl_mem_protection.3401178411 |
| Short name | T1030 |
| Test name | |
| Test status | |
| Simulation time | 5913808478 ps |
| CPU time | 1457.59 seconds |
| Started | Jun 29 07:58:47 PM PDT 24 |
| Finished | Jun 29 08:23:07 PM PDT 24 |
| Peak memory | 609160 kb |
| Host | smart-76345aef-cbc2-4a81-b458-becd03c8c855 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=flash_ctrl_mem_protection_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3401178411 -assert nopostproc + UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_flash_ctrl_mem_protection.3401178411 |
| Directory | /workspace/1.chip_sw_flash_ctrl_mem_protection/latest |
| Test location | /workspace/coverage/default/1.chip_sw_flash_ctrl_ops.3531169166 |
| Short name | T277 |
| Test name | |
| Test status | |
| Simulation time | 4147431080 ps |
| CPU time | 653.07 seconds |
| Started | Jun 29 07:41:24 PM PDT 24 |
| Finished | Jun 29 07:52:18 PM PDT 24 |
| Peak memory | 607568 kb |
| Host | smart-eaf6658d-ec1a-4cdf-ba82-2bffa1c84f9e |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=50_000_000 +sw_build_device=sim_dv +sw_images=flash_ctrl_ops_test:1:new_rules,test_rom:0 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3531169166 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/c overage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_flash_ctrl_ops.3531169166 |
| Directory | /workspace/1.chip_sw_flash_ctrl_ops/latest |
| Test location | /workspace/coverage/default/1.chip_sw_flash_ctrl_ops_jitter_en.196786033 |
| Short name | T1232 |
| Test name | |
| Test status | |
| Simulation time | 4313342290 ps |
| CPU time | 703.2 seconds |
| Started | Jun 29 07:48:31 PM PDT 24 |
| Finished | Jun 29 08:00:15 PM PDT 24 |
| Peak memory | 609180 kb |
| Host | smart-aacd7b7a-e186-46ce-8d5a-f230d916445e |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=50_000_000 +en_jitter=1 +sw_build_device=sim_dv +sw_images=flash_ctrl_ops_test:1:new_rules,test_rom:0 +cdc _instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see d=196786033 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_flash_ctrl_ops_jitter_en.196786033 |
| Directory | /workspace/1.chip_sw_flash_ctrl_ops_jitter_en/latest |
| Test location | /workspace/coverage/default/1.chip_sw_flash_ctrl_ops_jitter_en_reduced_freq.169105054 |
| Short name | T424 |
| Test name | |
| Test status | |
| Simulation time | 4912271791 ps |
| CPU time | 744.39 seconds |
| Started | Jun 29 07:50:59 PM PDT 24 |
| Finished | Jun 29 08:03:24 PM PDT 24 |
| Peak memory | 609184 kb |
| Host | smart-c87db7c3-4e3c-467b-b3a1-1cf21fa1e4f3 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=50_000_000 +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=flash_ctrl_ops_test:1:new_ rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si m.tcl +ntb_random_seed=169105054 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_flash_ctrl_ops_jitter_en_reduced_freq.169105054 |
| Directory | /workspace/1.chip_sw_flash_ctrl_ops_jitter_en_reduced_freq/latest |
| Test location | /workspace/coverage/default/1.chip_sw_flash_ctrl_write_clear.1354245784 |
| Short name | T909 |
| Test name | |
| Test status | |
| Simulation time | 2584391400 ps |
| CPU time | 362.31 seconds |
| Started | Jun 29 07:50:31 PM PDT 24 |
| Finished | Jun 29 07:56:34 PM PDT 24 |
| Peak memory | 609184 kb |
| Host | smart-5827b74e-2c73-4596-ab72-6a8cc483f67e |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=8_000_000 +sw_build_device=sim_dv +sw_images=flash_ctrl_write_clear_test:1:new_rules,test_rom:0 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1354245 784 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_flash_ctrl_write_clear.1354245784 |
| Directory | /workspace/1.chip_sw_flash_ctrl_write_clear/latest |
| Test location | /workspace/coverage/default/1.chip_sw_flash_init.190288415 |
| Short name | T1086 |
| Test name | |
| Test status | |
| Simulation time | 22245680384 ps |
| CPU time | 1991.26 seconds |
| Started | Jun 29 07:42:42 PM PDT 24 |
| Finished | Jun 29 08:15:55 PM PDT 24 |
| Peak memory | 610184 kb |
| Host | smart-fc7c9b7a-7398-4d51-b947-c43045ab7b54 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=25_000_000 +sw_build_device=sim_dv +sw_images=flash_init_test:0:test_in_rom:new_rules +cdc_instrumentation _enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=190288415 -ass ert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_flash_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace /coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_flash_init.190288415 |
| Directory | /workspace/1.chip_sw_flash_init/latest |
| Test location | /workspace/coverage/default/1.chip_sw_flash_init_reduced_freq.1945104967 |
| Short name | T1224 |
| Test name | |
| Test status | |
| Simulation time | 26789789179 ps |
| CPU time | 2282.86 seconds |
| Started | Jun 29 07:49:54 PM PDT 24 |
| Finished | Jun 29 08:27:59 PM PDT 24 |
| Peak memory | 611712 kb |
| Host | smart-0eaceb97-c0bf-4d62-9849-68e415f34a2c |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=25_000_000 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=flash_init_test:0:test_in_rom:new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=1945104967 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_flash_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_flash_init_reduced_freq.1945104967 |
| Directory | /workspace/1.chip_sw_flash_init_reduced_freq/latest |
| Test location | /workspace/coverage/default/1.chip_sw_flash_scrambling_smoketest.2955536910 |
| Short name | T851 |
| Test name | |
| Test status | |
| Simulation time | 2078911940 ps |
| CPU time | 215.91 seconds |
| Started | Jun 29 08:03:37 PM PDT 24 |
| Finished | Jun 29 08:07:13 PM PDT 24 |
| Peak memory | 606480 kb |
| Host | smart-51db4daa-b84e-461b-ac80-29743132bde8 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=flash_scrambling_smoketest:1:new_rules,flash_scrambling_smoket est_otp_img_rma:4,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=2955536910 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_flash_scrambling_smoketest.2955536910 |
| Directory | /workspace/1.chip_sw_flash_scrambling_smoketest/latest |
| Test location | /workspace/coverage/default/1.chip_sw_gpio.1313241739 |
| Short name | T34 |
| Test name | |
| Test status | |
| Simulation time | 4015762036 ps |
| CPU time | 599.26 seconds |
| Started | Jun 29 07:43:48 PM PDT 24 |
| Finished | Jun 29 07:53:49 PM PDT 24 |
| Peak memory | 607280 kb |
| Host | smart-0d4f02e5-a67f-4266-862d-72c6fbf5c487 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=gpio_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1313241739 -assert nopostproc +UVM_TESTNAME=chip_bas e_test +UVM_TEST_SEQ=chip_sw_gpio_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm _name 1.chip_sw_gpio.1313241739 |
| Directory | /workspace/1.chip_sw_gpio/latest |
| Test location | /workspace/coverage/default/1.chip_sw_gpio_smoketest.4205484685 |
| Short name | T927 |
| Test name | |
| Test status | |
| Simulation time | 3080290181 ps |
| CPU time | 298.61 seconds |
| Started | Jun 29 07:55:03 PM PDT 24 |
| Finished | Jun 29 08:00:03 PM PDT 24 |
| Peak memory | 606584 kb |
| Host | smart-ab632d07-0a0d-4afb-8f64-9ea4d51001cd |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=gpio_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4205484685 -assert nopostproc +UVM_TESTNAME=chi p_base_test +UVM_TEST_SEQ=chip_sw_gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 1.chip_sw_gpio_smoketest.4205484685 |
| Directory | /workspace/1.chip_sw_gpio_smoketest/latest |
| Test location | /workspace/coverage/default/1.chip_sw_hmac_enc.772833928 |
| Short name | T319 |
| Test name | |
| Test status | |
| Simulation time | 3232761994 ps |
| CPU time | 246.26 seconds |
| Started | Jun 29 07:45:31 PM PDT 24 |
| Finished | Jun 29 07:49:38 PM PDT 24 |
| Peak memory | 607140 kb |
| Host | smart-0ce366dc-f1e0-49c8-9677-891521631e4d |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=hmac_enc_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=772833928 -assert nopostproc +UVM_TESTNAME=chip_ base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_hmac_enc.772833928 |
| Directory | /workspace/1.chip_sw_hmac_enc/latest |
| Test location | /workspace/coverage/default/1.chip_sw_hmac_enc_idle.2382233779 |
| Short name | T1236 |
| Test name | |
| Test status | |
| Simulation time | 3053192116 ps |
| CPU time | 254.95 seconds |
| Started | Jun 29 07:46:35 PM PDT 24 |
| Finished | Jun 29 07:50:51 PM PDT 24 |
| Peak memory | 607132 kb |
| Host | smart-b9e00a36-3553-4871-9856-c571b0085af8 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=hmac_enc_idle_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2382233779 -assert nopostproc +UVM_TESTNAME =chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 1.chip_sw_hmac_enc_idle.2382233779 |
| Directory | /workspace/1.chip_sw_hmac_enc_idle/latest |
| Test location | /workspace/coverage/default/1.chip_sw_hmac_enc_jitter_en.1687460453 |
| Short name | T1187 |
| Test name | |
| Test status | |
| Simulation time | 3092119404 ps |
| CPU time | 261.98 seconds |
| Started | Jun 29 07:46:26 PM PDT 24 |
| Finished | Jun 29 07:50:48 PM PDT 24 |
| Peak memory | 609176 kb |
| Host | smart-e20af8d1-edcf-42f2-932f-b312cdded7f3 |
| User | root |
| Command | /workspace/default/simv +en_jitter=1 +sw_build_device=sim_dv +sw_images=hmac_enc_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1687460453 -assert nopostproc +UVM_ TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_ log /dev/null -cm_name 1.chip_sw_hmac_enc_jitter_en.1687460453 |
| Directory | /workspace/1.chip_sw_hmac_enc_jitter_en/latest |
| Test location | /workspace/coverage/default/1.chip_sw_hmac_enc_jitter_en_reduced_freq.4108198885 |
| Short name | T1071 |
| Test name | |
| Test status | |
| Simulation time | 2878255962 ps |
| CPU time | 218.74 seconds |
| Started | Jun 29 07:51:00 PM PDT 24 |
| Finished | Jun 29 07:54:39 PM PDT 24 |
| Peak memory | 609160 kb |
| Host | smart-e19548bb-e1de-49ea-bd60-a1b716b10d97 |
| User | root |
| Command | /workspace/default/simv +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=hmac_enc_test:1:new_rules,test_rom:0 +cdc_instrumentation _enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4108198885 -as sert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove rage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_hmac_enc_jitter_en_reduced_freq.4108198885 |
| Directory | /workspace/1.chip_sw_hmac_enc_jitter_en_reduced_freq/latest |
| Test location | /workspace/coverage/default/1.chip_sw_hmac_multistream.2280458052 |
| Short name | T972 |
| Test name | |
| Test status | |
| Simulation time | 7765725496 ps |
| CPU time | 1791.5 seconds |
| Started | Jun 29 07:45:17 PM PDT 24 |
| Finished | Jun 29 08:15:09 PM PDT 24 |
| Peak memory | 607688 kb |
| Host | smart-912fe5c6-f07c-4a93-b169-4e0764cbe87a |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=hmac_multistream_functest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2280458052 -assert nopostproc +UVM_T ESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l og /dev/null -cm_name 1.chip_sw_hmac_multistream.2280458052 |
| Directory | /workspace/1.chip_sw_hmac_multistream/latest |
| Test location | /workspace/coverage/default/1.chip_sw_hmac_oneshot.1458141464 |
| Short name | T866 |
| Test name | |
| Test status | |
| Simulation time | 3782931880 ps |
| CPU time | 387.03 seconds |
| Started | Jun 29 07:48:46 PM PDT 24 |
| Finished | Jun 29 07:55:13 PM PDT 24 |
| Peak memory | 607284 kb |
| Host | smart-0cc9a4f3-b0e5-4a3b-8015-c354d1749824 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=hmac_functest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1458141464 -assert nopostproc +UVM_TESTNAME=chip _base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_hmac_oneshot.1458141464 |
| Directory | /workspace/1.chip_sw_hmac_oneshot/latest |
| Test location | /workspace/coverage/default/1.chip_sw_hmac_smoketest.2258171157 |
| Short name | T1223 |
| Test name | |
| Test status | |
| Simulation time | 3148537160 ps |
| CPU time | 345.01 seconds |
| Started | Jun 29 07:51:56 PM PDT 24 |
| Finished | Jun 29 07:57:42 PM PDT 24 |
| Peak memory | 607128 kb |
| Host | smart-50a34522-87bb-45b0-8e49-91507ac7c52d |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=hmac_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2258171157 -assert nopostproc +UVM_TESTNAME=chi p_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul l -cm_name 1.chip_sw_hmac_smoketest.2258171157 |
| Directory | /workspace/1.chip_sw_hmac_smoketest/latest |
| Test location | /workspace/coverage/default/1.chip_sw_i2c_device_tx_rx.500998421 |
| Short name | T310 |
| Test name | |
| Test status | |
| Simulation time | 4277842344 ps |
| CPU time | 630.11 seconds |
| Started | Jun 29 07:41:43 PM PDT 24 |
| Finished | Jun 29 07:52:14 PM PDT 24 |
| Peak memory | 609316 kb |
| Host | smart-6cbd6038-39b9-4126-816a-6342d82dd14e |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=i2c_device_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=500998421 -assert nopostproc +UVM_TESTNA ME=chip_base_test +UVM_TEST_SEQ=chip_sw_i2c_device_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd b -cm_log /dev/null -cm_name 1.chip_sw_i2c_device_tx_rx.500998421 |
| Directory | /workspace/1.chip_sw_i2c_device_tx_rx/latest |
| Test location | /workspace/coverage/default/1.chip_sw_i2c_host_tx_rx.308803164 |
| Short name | T309 |
| Test name | |
| Test status | |
| Simulation time | 4916691100 ps |
| CPU time | 839.96 seconds |
| Started | Jun 29 07:41:26 PM PDT 24 |
| Finished | Jun 29 07:55:27 PM PDT 24 |
| Peak memory | 607916 kb |
| Host | smart-a1a4f413-1240-419f-b24d-54bdaef95ca0 |
| User | root |
| Command | /workspace/default/simv +i2c_idx=0 +sw_build_device=sim_dv +sw_images=i2c_host_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=308803164 -assert nopostproc +U VM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_i2c_host_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def ault.vdb -cm_log /dev/null -cm_name 1.chip_sw_i2c_host_tx_rx.308803164 |
| Directory | /workspace/1.chip_sw_i2c_host_tx_rx/latest |
| Test location | /workspace/coverage/default/1.chip_sw_i2c_host_tx_rx_idx1.3063966093 |
| Short name | T292 |
| Test name | |
| Test status | |
| Simulation time | 5082754900 ps |
| CPU time | 944.43 seconds |
| Started | Jun 29 07:42:57 PM PDT 24 |
| Finished | Jun 29 07:58:42 PM PDT 24 |
| Peak memory | 607860 kb |
| Host | smart-3339c87d-54d5-469b-ba17-001f309ecc58 |
| User | root |
| Command | /workspace/default/simv +i2c_idx=1 +sw_build_device=sim_dv +sw_images=i2c_host_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3063966093 -assert nopostproc + UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_i2c_host_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de fault.vdb -cm_log /dev/null -cm_name 1.chip_sw_i2c_host_tx_rx_idx1.3063966093 |
| Directory | /workspace/1.chip_sw_i2c_host_tx_rx_idx1/latest |
| Test location | /workspace/coverage/default/1.chip_sw_i2c_host_tx_rx_idx2.808765608 |
| Short name | T305 |
| Test name | |
| Test status | |
| Simulation time | 4730988032 ps |
| CPU time | 868.97 seconds |
| Started | Jun 29 07:42:10 PM PDT 24 |
| Finished | Jun 29 07:56:39 PM PDT 24 |
| Peak memory | 607228 kb |
| Host | smart-165420a9-9fcc-4fcf-bd21-f3b98c3add28 |
| User | root |
| Command | /workspace/default/simv +i2c_idx=2 +sw_build_device=sim_dv +sw_images=i2c_host_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=808765608 -assert nopostproc +U VM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_i2c_host_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def ault.vdb -cm_log /dev/null -cm_name 1.chip_sw_i2c_host_tx_rx_idx2.808765608 |
| Directory | /workspace/1.chip_sw_i2c_host_tx_rx_idx2/latest |
| Test location | /workspace/coverage/default/1.chip_sw_inject_scramble_seed.3766325255 |
| Short name | T155 |
| Test name | |
| Test status | |
| Simulation time | 62955430961 ps |
| CPU time | 12105.6 seconds |
| Started | Jun 29 07:40:37 PM PDT 24 |
| Finished | Jun 29 11:02:24 PM PDT 24 |
| Peak memory | 624176 kb |
| Host | smart-ea64e983-519c-43ba-b286-8b76e9769da9 |
| User | root |
| Command | /workspace/default/simv +lc_at_prod=1 +flash_program_latency=5 +sw_test_timeout_ns=150_000_000 +sw_build_device=sim_dv +sw_images=inject_scramble_seed :1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=3766325255 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_inject_scramble_seed_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_inject_scramble_seed.3766325255 |
| Directory | /workspace/1.chip_sw_inject_scramble_seed/latest |
| Test location | /workspace/coverage/default/1.chip_sw_keymgr_key_derivation.2734451588 |
| Short name | T871 |
| Test name | |
| Test status | |
| Simulation time | 12759420784 ps |
| CPU time | 2583.12 seconds |
| Started | Jun 29 07:47:55 PM PDT 24 |
| Finished | Jun 29 08:30:59 PM PDT 24 |
| Peak memory | 615644 kb |
| Host | smart-cf0ae29e-60ed-448e-8384-b0975acadc31 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=20_000_000 +sw_build_device=sim_dv +sw_images=keymgr_key_derivation_test:1:new_rules,test_rom:0 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2734 451588 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_keymgr_key_derivation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_keymgr_key_derivation.2734451588 |
| Directory | /workspace/1.chip_sw_keymgr_key_derivation/latest |
| Test location | /workspace/coverage/default/1.chip_sw_keymgr_key_derivation_jitter_en.2267350220 |
| Short name | T1094 |
| Test name | |
| Test status | |
| Simulation time | 11268900478 ps |
| CPU time | 2072.63 seconds |
| Started | Jun 29 07:46:35 PM PDT 24 |
| Finished | Jun 29 08:21:08 PM PDT 24 |
| Peak memory | 615624 kb |
| Host | smart-ed0efcbf-ceeb-4ff8-8bed-2ddc914394a9 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=20_000_000 +en_jitter=1 +sw_build_device=sim_dv +sw_images=keymgr_key_derivation_test:1:new_rules,test_rom :0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=2267350220 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_keymgr_key_derivation_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_keymgr_key_derivation_jitter_en.2267350220 |
| Directory | /workspace/1.chip_sw_keymgr_key_derivation_jitter_en/latest |
| Test location | /workspace/coverage/default/1.chip_sw_keymgr_key_derivation_jitter_en_reduced_freq.3694811130 |
| Short name | T971 |
| Test name | |
| Test status | |
| Simulation time | 7814065500 ps |
| CPU time | 1207.69 seconds |
| Started | Jun 29 07:51:06 PM PDT 24 |
| Finished | Jun 29 08:11:14 PM PDT 24 |
| Peak memory | 615680 kb |
| Host | smart-1d4d0c41-5c83-4c54-8ca7-706f81c59dee |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=20_000_000 +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=keymgr_key_derivation_test :1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=3694811130 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_keymgr_key_derivation_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_keymgr_key_derivation_jitter_en _reduced_freq.3694811130 |
| Directory | /workspace/1.chip_sw_keymgr_key_derivation_jitter_en_reduced_freq/latest |
| Test location | /workspace/coverage/default/1.chip_sw_keymgr_key_derivation_prod.2401076487 |
| Short name | T887 |
| Test name | |
| Test status | |
| Simulation time | 10520755160 ps |
| CPU time | 1677.62 seconds |
| Started | Jun 29 07:46:29 PM PDT 24 |
| Finished | Jun 29 08:14:27 PM PDT 24 |
| Peak memory | 615736 kb |
| Host | smart-d4dbfbe3-ad01-486e-beee-c0369a88c1e5 |
| User | root |
| Command | /workspace/default/simv +lc_at_prod=1 +sw_test_timeout_ns=20_000_000 +sw_build_device=sim_dv +sw_images=keymgr_key_derivation_test:1:new_rules,test_ro m:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=2401076487 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_keymgr_key_derivation_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_keymgr_key_derivation_prod.2401076487 |
| Directory | /workspace/1.chip_sw_keymgr_key_derivation_prod/latest |
| Test location | /workspace/coverage/default/1.chip_sw_keymgr_sideload_otbn.4012645915 |
| Short name | T206 |
| Test name | |
| Test status | |
| Simulation time | 16194056964 ps |
| CPU time | 4579.65 seconds |
| Started | Jun 29 07:47:37 PM PDT 24 |
| Finished | Jun 29 09:03:58 PM PDT 24 |
| Peak memory | 608624 kb |
| Host | smart-e72fd7b9-d865-486c-8449-8ded2308df0f |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=20_000_000 +sw_build_device=sim_dv +sw_images=keymgr_sideload_otbn_test:1:new_rules,test_rom:0 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40126 45915 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_keymgr_sideload_otbn.4012645915 |
| Directory | /workspace/1.chip_sw_keymgr_sideload_otbn/latest |
| Test location | /workspace/coverage/default/1.chip_sw_kmac_app_rom.1485718163 |
| Short name | T1136 |
| Test name | |
| Test status | |
| Simulation time | 2492790144 ps |
| CPU time | 239.36 seconds |
| Started | Jun 29 07:48:03 PM PDT 24 |
| Finished | Jun 29 07:52:02 PM PDT 24 |
| Peak memory | 607132 kb |
| Host | smart-5bae74d0-1d0c-4122-a0ba-ad8cfdb00529 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=kmac_app_rom_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1485718163 -assert nopostproc +UVM_TESTNAME= chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/ null -cm_name 1.chip_sw_kmac_app_rom.1485718163 |
| Directory | /workspace/1.chip_sw_kmac_app_rom/latest |
| Test location | /workspace/coverage/default/1.chip_sw_kmac_entropy.1984229524 |
| Short name | T1216 |
| Test name | |
| Test status | |
| Simulation time | 3059987440 ps |
| CPU time | 300.29 seconds |
| Started | Jun 29 07:42:49 PM PDT 24 |
| Finished | Jun 29 07:47:50 PM PDT 24 |
| Peak memory | 607068 kb |
| Host | smart-b275c06f-031f-4751-bfd2-8cb04d13bdb5 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=kmac_entropy_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1984229524 -assert nopostproc +UVM_TESTNAME= chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/ null -cm_name 1.chip_sw_kmac_entropy.1984229524 |
| Directory | /workspace/1.chip_sw_kmac_entropy/latest |
| Test location | /workspace/coverage/default/1.chip_sw_kmac_idle.3299123310 |
| Short name | T1077 |
| Test name | |
| Test status | |
| Simulation time | 2481429768 ps |
| CPU time | 186.43 seconds |
| Started | Jun 29 07:46:33 PM PDT 24 |
| Finished | Jun 29 07:49:40 PM PDT 24 |
| Peak memory | 607104 kb |
| Host | smart-a1e4a162-1332-44a5-94b6-dcd731bdc376 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=kmac_idle_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3299123310 -assert nopostproc +UVM_TESTNAME=chi p_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul l -cm_name 1.chip_sw_kmac_idle.3299123310 |
| Directory | /workspace/1.chip_sw_kmac_idle/latest |
| Test location | /workspace/coverage/default/1.chip_sw_kmac_mode_cshake.4003439376 |
| Short name | T904 |
| Test name | |
| Test status | |
| Simulation time | 2525746598 ps |
| CPU time | 286.86 seconds |
| Started | Jun 29 07:46:38 PM PDT 24 |
| Finished | Jun 29 07:51:25 PM PDT 24 |
| Peak memory | 607248 kb |
| Host | smart-e686aa66-ce09-4d6c-a45a-21566fda5593 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=kmac_mode_cshake_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4003439376 -assert nopostproc +UVM_TESTN AME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log / dev/null -cm_name 1.chip_sw_kmac_mode_cshake.4003439376 |
| Directory | /workspace/1.chip_sw_kmac_mode_cshake/latest |
| Test location | /workspace/coverage/default/1.chip_sw_kmac_mode_kmac.3686219727 |
| Short name | T984 |
| Test name | |
| Test status | |
| Simulation time | 3098645016 ps |
| CPU time | 297.86 seconds |
| Started | Jun 29 07:47:11 PM PDT 24 |
| Finished | Jun 29 07:52:10 PM PDT 24 |
| Peak memory | 607312 kb |
| Host | smart-84eebe78-9fd4-4014-818a-78bc23a4b5ef |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=kmac_mode_kmac_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3686219727 -assert nopostproc +UVM_TESTNAM E=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 1.chip_sw_kmac_mode_kmac.3686219727 |
| Directory | /workspace/1.chip_sw_kmac_mode_kmac/latest |
| Test location | /workspace/coverage/default/1.chip_sw_kmac_mode_kmac_jitter_en.1463588916 |
| Short name | T935 |
| Test name | |
| Test status | |
| Simulation time | 2751020769 ps |
| CPU time | 240.15 seconds |
| Started | Jun 29 07:46:52 PM PDT 24 |
| Finished | Jun 29 07:50:52 PM PDT 24 |
| Peak memory | 607376 kb |
| Host | smart-551d17c4-df29-444b-87d0-479a868e872d |
| User | root |
| Command | /workspace/default/simv +en_jitter=1 +sw_build_device=sim_dv +sw_images=kmac_mode_kmac_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1463588916 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd b -cm_log /dev/null -cm_name 1.chip_sw_kmac_mode_kmac_jitter_en.1463588916 |
| Directory | /workspace/1.chip_sw_kmac_mode_kmac_jitter_en/latest |
| Test location | /workspace/coverage/default/1.chip_sw_kmac_mode_kmac_jitter_en_reduced_freq.623546866 |
| Short name | T258 |
| Test name | |
| Test status | |
| Simulation time | 2858936056 ps |
| CPU time | 336.84 seconds |
| Started | Jun 29 07:50:46 PM PDT 24 |
| Finished | Jun 29 07:56:23 PM PDT 24 |
| Peak memory | 607312 kb |
| Host | smart-1eefae15-a3dc-4db3-b9fe-52072e790571 |
| User | root |
| Command | /workspace/default/simv +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=kmac_mode_kmac_test:1:new_rules,test_rom:0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62354686 6 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace /coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_kmac_mode_kmac_jitter_en_reduced_freq.623546866 |
| Directory | /workspace/1.chip_sw_kmac_mode_kmac_jitter_en_reduced_freq/latest |
| Test location | /workspace/coverage/default/1.chip_sw_kmac_smoketest.3129018419 |
| Short name | T1122 |
| Test name | |
| Test status | |
| Simulation time | 3059646916 ps |
| CPU time | 282.29 seconds |
| Started | Jun 29 07:55:22 PM PDT 24 |
| Finished | Jun 29 08:00:05 PM PDT 24 |
| Peak memory | 607088 kb |
| Host | smart-95f056b1-ed1a-4922-bdeb-03d993ed634b |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=kmac_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3129018419 -assert nopostproc +UVM_TESTNAME=chi p_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul l -cm_name 1.chip_sw_kmac_smoketest.3129018419 |
| Directory | /workspace/1.chip_sw_kmac_smoketest/latest |
| Test location | /workspace/coverage/default/1.chip_sw_lc_ctrl_otp_hw_cfg0.2711202799 |
| Short name | T900 |
| Test name | |
| Test status | |
| Simulation time | 3042302820 ps |
| CPU time | 252.2 seconds |
| Started | Jun 29 07:44:17 PM PDT 24 |
| Finished | Jun 29 07:48:30 PM PDT 24 |
| Peak memory | 609180 kb |
| Host | smart-a29f581f-d7d0-4a6b-bf62-246e01287763 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=lc_ctrl_otp_hw_cfg0_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2711202799 -assert nopostproc +UVM_TE STNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo g /dev/null -cm_name 1.chip_sw_lc_ctrl_otp_hw_cfg0.2711202799 |
| Directory | /workspace/1.chip_sw_lc_ctrl_otp_hw_cfg0/latest |
| Test location | /workspace/coverage/default/1.chip_sw_lc_ctrl_program_error.1991202349 |
| Short name | T178 |
| Test name | |
| Test status | |
| Simulation time | 4747011044 ps |
| CPU time | 497.62 seconds |
| Started | Jun 29 07:49:43 PM PDT 24 |
| Finished | Jun 29 07:58:01 PM PDT 24 |
| Peak memory | 608744 kb |
| Host | smart-436c955e-a509-4c75-981b-da9f0e9f34d8 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=lc_ctrl_program_error:1:new_rules,test_rom:0 + cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_ seed=1991202349 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_program_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_lc_ctrl_program_error.1991202349 |
| Directory | /workspace/1.chip_sw_lc_ctrl_program_error/latest |
| Test location | /workspace/coverage/default/1.chip_sw_lc_ctrl_rand_to_scrap.701757953 |
| Short name | T1125 |
| Test name | |
| Test status | |
| Simulation time | 3760516837 ps |
| CPU time | 215 seconds |
| Started | Jun 29 07:43:34 PM PDT 24 |
| Finished | Jun 29 07:47:09 PM PDT 24 |
| Peak memory | 617852 kb |
| Host | smart-fdbf9075-e9e7-41f0-b4eb-2fe83f5dfe6b |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=lc_ctrl_scrap_test:1:new_rules,test_rom:0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70175795 3 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_scrap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_lc_ctrl_rand_to_scrap.701757953 |
| Directory | /workspace/1.chip_sw_lc_ctrl_rand_to_scrap/latest |
| Test location | /workspace/coverage/default/1.chip_sw_lc_ctrl_transition.1326816119 |
| Short name | T1152 |
| Test name | |
| Test status | |
| Simulation time | 7370673768 ps |
| CPU time | 476.03 seconds |
| Started | Jun 29 07:43:37 PM PDT 24 |
| Finished | Jun 29 07:51:33 PM PDT 24 |
| Peak memory | 619176 kb |
| Host | smart-17d38905-0849-4e04-b237-f6342f2cc543 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=lc_ctrl_transition_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1326816119 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_transition_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau lt.vdb -cm_log /dev/null -cm_name 1.chip_sw_lc_ctrl_transition.1326816119 |
| Directory | /workspace/1.chip_sw_lc_ctrl_transition/latest |
| Test location | /workspace/coverage/default/1.chip_sw_lc_ctrl_volatile_raw_unlock.3636317535 |
| Short name | T645 |
| Test name | |
| Test status | |
| Simulation time | 2194118700 ps |
| CPU time | 117.21 seconds |
| Started | Jun 29 07:43:03 PM PDT 24 |
| Finished | Jun 29 07:45:01 PM PDT 24 |
| Peak memory | 615976 kb |
| Host | smart-151f7652-b678-4f4d-86cd-253a134dc513 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStRaw +exp_volatile_raw_unlock_en=0 +sw_build_device=sim_dv +sw_images=lc_ctrl_volatile_raw_unlock_tes t:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/ tools/sim.tcl +ntb_random_seed=3636317535 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_volatile_raw_unlock_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_lc_ctrl_volatile_raw_unlock.3636317535 |
| Directory | /workspace/1.chip_sw_lc_ctrl_volatile_raw_unlock/latest |
| Test location | /workspace/coverage/default/1.chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz.15640720 |
| Short name | T647 |
| Test name | |
| Test status | |
| Simulation time | 2802709869 ps |
| CPU time | 117.22 seconds |
| Started | Jun 29 07:44:48 PM PDT 24 |
| Finished | Jun 29 07:46:46 PM PDT 24 |
| Peak memory | 614440 kb |
| Host | smart-64fc9611-5b0c-49d0-9cb1-3f050940e128 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStRaw +chip_clock_source=ChipClockSourceExternal48Mhz +exp_volatile_raw_unlock_en=0 +sw_build_device=s im_dv +sw_images=lc_ctrl_volatile_raw_unlock_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15640720 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_ SEQ=chip_sw_lc_volatile_raw_unlock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 1.chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz.15640720 |
| Directory | /workspace/1.chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz/latest |
| Test location | /workspace/coverage/default/1.chip_sw_lc_walkthrough_dev.1964836485 |
| Short name | T217 |
| Test name | |
| Test status | |
| Simulation time | 46960441552 ps |
| CPU time | 5728.15 seconds |
| Started | Jun 29 07:41:51 PM PDT 24 |
| Finished | Jun 29 09:17:23 PM PDT 24 |
| Peak memory | 618100 kb |
| Host | smart-14ca60e6-662f-4609-8c0f-2b247e535bcd |
| User | root |
| Command | /workspace/default/simv +flash_program_latency=5 +use_otp_image=OtpTypeLcStRaw +dest_dec_state=DecLcStDev +sw_test_timeout_ns=200_000_000 +sw_build_de vice=sim_dv +sw_images=lc_walkthrough_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1964836485 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=c hip_sw_lc_walkthrough_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip _sw_lc_walkthrough_dev.1964836485 |
| Directory | /workspace/1.chip_sw_lc_walkthrough_dev/latest |
| Test location | /workspace/coverage/default/1.chip_sw_lc_walkthrough_prodend.669087296 |
| Short name | T181 |
| Test name | |
| Test status | |
| Simulation time | 8884233749 ps |
| CPU time | 1024.19 seconds |
| Started | Jun 29 07:50:58 PM PDT 24 |
| Finished | Jun 29 08:08:03 PM PDT 24 |
| Peak memory | 616884 kb |
| Host | smart-e7ee6046-64af-4b1b-9519-8836d6b8a12b |
| User | root |
| Command | /workspace/default/simv +flash_program_latency=5 +use_otp_image=OtpTypeLcStRaw +dest_dec_state=DecLcStProdEnd +sw_build_device=sim_dv +sw_images=lc_wa lkthrough_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=669087296 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_walkthrough_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_lc_walkthrough_prodend.669087296 |
| Directory | /workspace/1.chip_sw_lc_walkthrough_prodend/latest |
| Test location | /workspace/coverage/default/1.chip_sw_lc_walkthrough_rma.1068464439 |
| Short name | T212 |
| Test name | |
| Test status | |
| Simulation time | 45709871868 ps |
| CPU time | 5081.2 seconds |
| Started | Jun 29 07:41:12 PM PDT 24 |
| Finished | Jun 29 09:05:54 PM PDT 24 |
| Peak memory | 618088 kb |
| Host | smart-43bb3cf1-d7ee-43c1-9a8e-a5a4f23b9edd |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStRaw +dest_dec_state=DecLcStRma +flash_program_latency=5 +sw_test_timeout_ns=200_000_000 +sw_build_de vice=sim_dv +sw_images=lc_walkthrough_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1068464439 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=c hip_sw_lc_walkthrough_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip _sw_lc_walkthrough_rma.1068464439 |
| Directory | /workspace/1.chip_sw_lc_walkthrough_rma/latest |
| Test location | /workspace/coverage/default/1.chip_sw_lc_walkthrough_testunlocks.1637837288 |
| Short name | T1033 |
| Test name | |
| Test status | |
| Simulation time | 29083616532 ps |
| CPU time | 2290.37 seconds |
| Started | Jun 29 07:46:06 PM PDT 24 |
| Finished | Jun 29 08:24:18 PM PDT 24 |
| Peak memory | 618060 kb |
| Host | smart-98b08ebf-9964-4be1-ba20-d61d2c620db6 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStRaw +dest_dec_state=DecLcStTestUnlock7 +sw_build_device=sim_dv +sw_images=lc_walkthrough_testunlocks _test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=1637837288 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_walkthrough_testunlocks_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_lc_walkthrough_testun locks.1637837288 |
| Directory | /workspace/1.chip_sw_lc_walkthrough_testunlocks/latest |
| Test location | /workspace/coverage/default/1.chip_sw_otbn_ecdsa_op_irq.4036188606 |
| Short name | T164 |
| Test name | |
| Test status | |
| Simulation time | 17238079262 ps |
| CPU time | 3712.24 seconds |
| Started | Jun 29 07:43:43 PM PDT 24 |
| Finished | Jun 29 08:45:36 PM PDT 24 |
| Peak memory | 609316 kb |
| Host | smart-cc6382be-4a05-41e1-abec-238b9c79aec5 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=28_000_000 +rng_srate_value=30 +sw_build_device=sim_dv +sw_images=otbn_ecdsa_op_irq_test:1:new_rules,test_ rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ random_seed=4036188606 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_otbn_ecdsa_op_irq.4036188606 |
| Directory | /workspace/1.chip_sw_otbn_ecdsa_op_irq/latest |
| Test location | /workspace/coverage/default/1.chip_sw_otbn_ecdsa_op_irq_jitter_en.2877640959 |
| Short name | T864 |
| Test name | |
| Test status | |
| Simulation time | 18955144018 ps |
| CPU time | 4963.32 seconds |
| Started | Jun 29 07:48:29 PM PDT 24 |
| Finished | Jun 29 09:11:13 PM PDT 24 |
| Peak memory | 608168 kb |
| Host | smart-2fc7fceb-6e4c-44f4-b8ed-a5914302d80c |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=33_000_000 +rng_srate_value=30 +en_jitter=1 +sw_build_device=sim_dv +sw_images=otbn_ecdsa_op_irq_test:1:ne w_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/ sim.tcl +ntb_random_seed=2877640959 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tg l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_otbn_ecdsa_op_irq_jitter_en.2877640959 |
| Directory | /workspace/1.chip_sw_otbn_ecdsa_op_irq_jitter_en/latest |
| Test location | /workspace/coverage/default/1.chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq.989731371 |
| Short name | T110 |
| Test name | |
| Test status | |
| Simulation time | 24651874511 ps |
| CPU time | 4265.61 seconds |
| Started | Jun 29 07:50:53 PM PDT 24 |
| Finished | Jun 29 09:02:00 PM PDT 24 |
| Peak memory | 609328 kb |
| Host | smart-86865e21-fc02-4f16-91ca-cbdc634dbf0e |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=33_000_000 +rng_srate_value=30 +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=otbn_e cdsa_op_irq_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/ repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=989731371 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_otbn_ecdsa_op_irq_jitter_en_reduc ed_freq.989731371 |
| Directory | /workspace/1.chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq/latest |
| Test location | /workspace/coverage/default/1.chip_sw_otbn_mem_scramble.1929345180 |
| Short name | T82 |
| Test name | |
| Test status | |
| Simulation time | 4074348068 ps |
| CPU time | 636.16 seconds |
| Started | Jun 29 07:44:32 PM PDT 24 |
| Finished | Jun 29 07:55:09 PM PDT 24 |
| Peak memory | 609136 kb |
| Host | smart-de6424f5-a045-4c6a-96f2-b25445688e2f |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=15_000_000 +en_scb_tl_err_chk=0 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=otbn _mem_scramble_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1929345180 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_otbn_mem_scramble.1929345180 |
| Directory | /workspace/1.chip_sw_otbn_mem_scramble/latest |
| Test location | /workspace/coverage/default/1.chip_sw_otbn_randomness.2904338333 |
| Short name | T1090 |
| Test name | |
| Test status | |
| Simulation time | 6375924752 ps |
| CPU time | 951.19 seconds |
| Started | Jun 29 07:48:46 PM PDT 24 |
| Finished | Jun 29 08:04:39 PM PDT 24 |
| Peak memory | 607308 kb |
| Host | smart-5ba07b6f-8b05-4019-9abd-7b8e7f9c9b6b |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +rng_srate_value=30 +sw_build_device=sim_dv +sw_images=otbn_randomness_test:1:new_rules,test_ro m:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=2904338333 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_otbn_randomness.2904338333 |
| Directory | /workspace/1.chip_sw_otbn_randomness/latest |
| Test location | /workspace/coverage/default/1.chip_sw_otbn_smoketest.3779576421 |
| Short name | T1112 |
| Test name | |
| Test status | |
| Simulation time | 10543117800 ps |
| CPU time | 2782.86 seconds |
| Started | Jun 29 07:53:11 PM PDT 24 |
| Finished | Jun 29 08:39:35 PM PDT 24 |
| Peak memory | 607416 kb |
| Host | smart-c93cebcc-13fa-478d-b3f2-f1f1b641e4ef |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=otbn_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3779576421 -assert nopostproc +UVM_TESTNAME=chi p_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul l -cm_name 1.chip_sw_otbn_smoketest.3779576421 |
| Directory | /workspace/1.chip_sw_otbn_smoketest/latest |
| Test location | /workspace/coverage/default/1.chip_sw_otp_ctrl_ecc_error_vendor_test.645342999 |
| Short name | T432 |
| Test name | |
| Test status | |
| Simulation time | 3344943244 ps |
| CPU time | 242.04 seconds |
| Started | Jun 29 07:41:18 PM PDT 24 |
| Finished | Jun 29 07:45:21 PM PDT 24 |
| Peak memory | 609196 kb |
| Host | smart-2be125a6-9244-437b-8ccd-a3aa4e7be503 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=otp_ctrl_vendor_test_ecc_error_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=645342999 -assert nopostpr oc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_otp_ctrl_vendor_test_ecc_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_otp_ctrl_ecc_error_vendor_test.645342999 |
| Directory | /workspace/1.chip_sw_otp_ctrl_ecc_error_vendor_test/latest |
| Test location | /workspace/coverage/default/1.chip_sw_otp_ctrl_lc_signals_dev.1142602461 |
| Short name | T175 |
| Test name | |
| Test status | |
| Simulation time | 6975346312 ps |
| CPU time | 1195.7 seconds |
| Started | Jun 29 07:41:03 PM PDT 24 |
| Finished | Jun 29 08:00:59 PM PDT 24 |
| Peak memory | 609188 kb |
| Host | smart-d909a156-c38a-45c7-bcd6-76e66298a081 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStDev +otp_clear_secret2=1 +sw_build_device=sim_dv +sw_images=otp_ctrl_lc_signals_test:1:new_rules,tes t_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +nt b_random_seed=1142602461 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_otp_ctrl_lc_signals_dev.1142602461 |
| Directory | /workspace/1.chip_sw_otp_ctrl_lc_signals_dev/latest |
| Test location | /workspace/coverage/default/1.chip_sw_otp_ctrl_lc_signals_prod.2898793529 |
| Short name | T914 |
| Test name | |
| Test status | |
| Simulation time | 6895962840 ps |
| CPU time | 1102.54 seconds |
| Started | Jun 29 07:48:04 PM PDT 24 |
| Finished | Jun 29 08:06:27 PM PDT 24 |
| Peak memory | 609192 kb |
| Host | smart-8820e032-9d31-4163-a992-20d81899ac63 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStProd +otp_clear_secret2=1 +sw_build_device=sim_dv +sw_images=otp_ctrl_lc_signals_test:1:new_rules,te st_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n tb_random_seed=2898793529 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_otp_ctrl_lc_signals_prod.2898793529 |
| Directory | /workspace/1.chip_sw_otp_ctrl_lc_signals_prod/latest |
| Test location | /workspace/coverage/default/1.chip_sw_otp_ctrl_lc_signals_rma.1212774774 |
| Short name | T199 |
| Test name | |
| Test status | |
| Simulation time | 6955947810 ps |
| CPU time | 1428.75 seconds |
| Started | Jun 29 07:44:10 PM PDT 24 |
| Finished | Jun 29 08:07:59 PM PDT 24 |
| Peak memory | 609148 kb |
| Host | smart-097ca0c3-3ab6-4e5c-9ecc-5905cc7baa44 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStRma +otp_clear_secret2=1 +sw_build_device=sim_dv +sw_images=otp_ctrl_lc_signals_test:1:new_rules,tes t_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +nt b_random_seed=1212774774 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_otp_ctrl_lc_signals_rma.1212774774 |
| Directory | /workspace/1.chip_sw_otp_ctrl_lc_signals_rma/latest |
| Test location | /workspace/coverage/default/1.chip_sw_otp_ctrl_lc_signals_test_unlocked0.4103054433 |
| Short name | T267 |
| Test name | |
| Test status | |
| Simulation time | 4120465844 ps |
| CPU time | 661.55 seconds |
| Started | Jun 29 07:44:12 PM PDT 24 |
| Finished | Jun 29 07:55:14 PM PDT 24 |
| Peak memory | 609172 kb |
| Host | smart-4a12f061-ca33-4c55-ae3c-77166c547745 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStTestUnlocked0 +otp_clear_secret2=1 +sw_build_device=sim_dv +sw_images=otp_ctrl_lc_signals_test:1:new _rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/s im.tcl +ntb_random_seed=4103054433 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_otp_ctrl_lc_signals_test_unlocked0.4103054433 |
| Directory | /workspace/1.chip_sw_otp_ctrl_lc_signals_test_unlocked0/latest |
| Test location | /workspace/coverage/default/1.chip_sw_otp_ctrl_smoketest.870051321 |
| Short name | T518 |
| Test name | |
| Test status | |
| Simulation time | 3087869936 ps |
| CPU time | 324.73 seconds |
| Started | Jun 29 07:52:52 PM PDT 24 |
| Finished | Jun 29 07:58:17 PM PDT 24 |
| Peak memory | 609168 kb |
| Host | smart-771c5892-bbfc-48e1-bd84-15f11976f9f9 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=otp_ctrl_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=870051321 -assert nopostproc +UVM_TESTNAME= chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/ null -cm_name 1.chip_sw_otp_ctrl_smoketest.870051321 |
| Directory | /workspace/1.chip_sw_otp_ctrl_smoketest/latest |
| Test location | /workspace/coverage/default/1.chip_sw_plic_sw_irq.2796692154 |
| Short name | T86 |
| Test name | |
| Test status | |
| Simulation time | 2930246808 ps |
| CPU time | 395.02 seconds |
| Started | Jun 29 07:48:24 PM PDT 24 |
| Finished | Jun 29 07:54:59 PM PDT 24 |
| Peak memory | 607292 kb |
| Host | smart-99dc0ddf-75ed-4307-819a-63430573a030 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=plic_sw_irq_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2796692154 -assert nopostproc +UVM_TESTNAME=c hip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n ull -cm_name 1.chip_sw_plic_sw_irq.2796692154 |
| Directory | /workspace/1.chip_sw_plic_sw_irq/latest |
| Test location | /workspace/coverage/default/1.chip_sw_power_idle_load.1910921210 |
| Short name | T956 |
| Test name | |
| Test status | |
| Simulation time | 4150848904 ps |
| CPU time | 847.42 seconds |
| Started | Jun 29 07:52:36 PM PDT 24 |
| Finished | Jun 29 08:06:44 PM PDT 24 |
| Peak memory | 607652 kb |
| Host | smart-0301d09d-5b8c-416d-8963-7c986bb5200b |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=chip_power_idle_load:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1910921210 -assert nopostproc +UVM_TESTNA ME=chip_base_test +UVM_TEST_SEQ=chip_sw_power_idle_load_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_power_idle_load.1910921210 |
| Directory | /workspace/1.chip_sw_power_idle_load/latest |
| Test location | /workspace/coverage/default/1.chip_sw_power_sleep_load.238450496 |
| Short name | T668 |
| Test name | |
| Test status | |
| Simulation time | 11149600444 ps |
| CPU time | 667.72 seconds |
| Started | Jun 29 07:51:03 PM PDT 24 |
| Finished | Jun 29 08:02:11 PM PDT 24 |
| Peak memory | 607404 kb |
| Host | smart-9eaaf94e-1435-4637-9e4e-796109583ab9 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=chip_power_sleep_load:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=238450496 -assert nopostproc +UVM_TESTNA ME=chip_base_test +UVM_TEST_SEQ=chip_sw_power_sleep_load_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd b -cm_log /dev/null -cm_name 1.chip_sw_power_sleep_load.238450496 |
| Directory | /workspace/1.chip_sw_power_sleep_load/latest |
| Test location | /workspace/coverage/default/1.chip_sw_pwrmgr_all_reset_reqs.628773245 |
| Short name | T1146 |
| Test name | |
| Test status | |
| Simulation time | 10362031653 ps |
| CPU time | 2403.84 seconds |
| Started | Jun 29 07:42:14 PM PDT 24 |
| Finished | Jun 29 08:22:18 PM PDT 24 |
| Peak memory | 609304 kb |
| Host | smart-1fb02c7c-13c6-4373-b6c3-717eeebe9692 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=50_000_000 +sw_build_device=sim_dv +sw_images=pwrmgr_all_reset_reqs_test:1:new_rules,test_rom:0 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=6287 73245 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_deep_sleep_all_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_all_reset_reqs.628773245 |
| Directory | /workspace/1.chip_sw_pwrmgr_all_reset_reqs/latest |
| Test location | /workspace/coverage/default/1.chip_sw_pwrmgr_b2b_sleep_reset_req.1785973021 |
| Short name | T404 |
| Test name | |
| Test status | |
| Simulation time | 27692057927 ps |
| CPU time | 3251.3 seconds |
| Started | Jun 29 07:47:17 PM PDT 24 |
| Finished | Jun 29 08:41:29 PM PDT 24 |
| Peak memory | 609240 kb |
| Host | smart-a09b1e7c-00c0-4ffa-b905-b06c5dc843a0 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=35_000_000 +sw_build_device=sim_dv +sw_images=pwrmgr_b2b_sleep_reset_test:1:new_rules,test_rom:0 +cdc_inst rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=178 5973021 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_repeat_reset_wkup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_b2b_sleep_reset_req.1785973021 |
| Directory | /workspace/1.chip_sw_pwrmgr_b2b_sleep_reset_req/latest |
| Test location | /workspace/coverage/default/1.chip_sw_pwrmgr_deep_sleep_all_reset_reqs.1283795747 |
| Short name | T1114 |
| Test name | |
| Test status | |
| Simulation time | 18001235962 ps |
| CPU time | 1749.99 seconds |
| Started | Jun 29 07:43:35 PM PDT 24 |
| Finished | Jun 29 08:12:45 PM PDT 24 |
| Peak memory | 609432 kb |
| Host | smart-abb1771d-8a5f-47b3-863f-85b717b26cec |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=50_000_000 +sw_build_device=sim_dv +sw_images=pwrmgr_deep_sleep_all_reset_reqs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=1283795747 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_deep_sleep_all_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_deep_sleep_all_reset_reqs.1283795747 |
| Directory | /workspace/1.chip_sw_pwrmgr_deep_sleep_all_reset_reqs/latest |
| Test location | /workspace/coverage/default/1.chip_sw_pwrmgr_deep_sleep_por_reset.1842280104 |
| Short name | T1278 |
| Test name | |
| Test status | |
| Simulation time | 8639679962 ps |
| CPU time | 832.65 seconds |
| Started | Jun 29 07:45:22 PM PDT 24 |
| Finished | Jun 29 07:59:15 PM PDT 24 |
| Peak memory | 609268 kb |
| Host | smart-37d48502-0634-408b-9877-6f91ce5e4da4 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_deep_sleep_por_reset_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1842280104 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sleep_por_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage /default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_deep_sleep_por_reset.1842280104 |
| Directory | /workspace/1.chip_sw_pwrmgr_deep_sleep_por_reset/latest |
| Test location | /workspace/coverage/default/1.chip_sw_pwrmgr_deep_sleep_power_glitch_reset.2937459282 |
| Short name | T835 |
| Test name | |
| Test status | |
| Simulation time | 6135752554 ps |
| CPU time | 391.72 seconds |
| Started | Jun 29 07:41:48 PM PDT 24 |
| Finished | Jun 29 07:48:20 PM PDT 24 |
| Peak memory | 615124 kb |
| Host | smart-eb49b258-affa-4cec-a323-1083a5d1ab7a |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=pwrmgr_deep_sleep_power_glitch_test:1:new_rules,test_rom :0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=2937459282 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_deep_power_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_deep_sleep_power_glitch_reset.2937459282 |
| Directory | /workspace/1.chip_sw_pwrmgr_deep_sleep_power_glitch_reset/latest |
| Test location | /workspace/coverage/default/1.chip_sw_pwrmgr_full_aon_reset.778428100 |
| Short name | T1101 |
| Test name | |
| Test status | |
| Simulation time | 7667778956 ps |
| CPU time | 584.4 seconds |
| Started | Jun 29 07:43:31 PM PDT 24 |
| Finished | Jun 29 07:53:15 PM PDT 24 |
| Peak memory | 609280 kb |
| Host | smart-b5dbd861-a1ca-4d2a-9201-b13602b85fa9 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=rstmgr_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=778428100 -assert nopostproc +UVM_TESTNAME=ch ip_base_test +UVM_TEST_SEQ=chip_sw_full_aon_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l og /dev/null -cm_name 1.chip_sw_pwrmgr_full_aon_reset.778428100 |
| Directory | /workspace/1.chip_sw_pwrmgr_full_aon_reset/latest |
| Test location | /workspace/coverage/default/1.chip_sw_pwrmgr_lowpower_cancel.2540170871 |
| Short name | T89 |
| Test name | |
| Test status | |
| Simulation time | 3779253678 ps |
| CPU time | 591.38 seconds |
| Started | Jun 29 07:49:24 PM PDT 24 |
| Finished | Jun 29 07:59:16 PM PDT 24 |
| Peak memory | 609252 kb |
| Host | smart-cdd50f86-501c-4807-837c-1372b920e989 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_lowpower_cancel_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2540170871 -assert nopostproc +UVM _TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm _log /dev/null -cm_name 1.chip_sw_pwrmgr_lowpower_cancel.2540170871 |
| Directory | /workspace/1.chip_sw_pwrmgr_lowpower_cancel/latest |
| Test location | /workspace/coverage/default/1.chip_sw_pwrmgr_main_power_glitch_reset.3803554818 |
| Short name | T841 |
| Test name | |
| Test status | |
| Simulation time | 3980480312 ps |
| CPU time | 440.62 seconds |
| Started | Jun 29 07:43:23 PM PDT 24 |
| Finished | Jun 29 07:50:44 PM PDT 24 |
| Peak memory | 614792 kb |
| Host | smart-7b1affd7-a18f-43b8-8fed-545e5303be77 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=pwrmgr_main_power_glitch_test:1:new_rules,test_rom:0 +cd c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se ed=3803554818 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_main_power_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_main_power_glitch_reset.3803554818 |
| Directory | /workspace/1.chip_sw_pwrmgr_main_power_glitch_reset/latest |
| Test location | /workspace/coverage/default/1.chip_sw_pwrmgr_normal_sleep_all_reset_reqs.2558576230 |
| Short name | T1262 |
| Test name | |
| Test status | |
| Simulation time | 13367195871 ps |
| CPU time | 1816.07 seconds |
| Started | Jun 29 07:43:34 PM PDT 24 |
| Finished | Jun 29 08:13:51 PM PDT 24 |
| Peak memory | 609320 kb |
| Host | smart-3b76af3e-cecd-46d4-be96-437cf9e0d9de |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_normal_sleep_all_reset_reqs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2558576230 -assert nop ostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_deep_sleep_all_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_normal_sleep_all_reset_reqs.2558576230 |
| Directory | /workspace/1.chip_sw_pwrmgr_normal_sleep_all_reset_reqs/latest |
| Test location | /workspace/coverage/default/1.chip_sw_pwrmgr_normal_sleep_all_wake_ups.727040372 |
| Short name | T96 |
| Test name | |
| Test status | |
| Simulation time | 7041257068 ps |
| CPU time | 467.09 seconds |
| Started | Jun 29 07:49:38 PM PDT 24 |
| Finished | Jun 29 07:57:25 PM PDT 24 |
| Peak memory | 608224 kb |
| Host | smart-a81d1610-edf1-4af6-9f3f-6c2b2011ef1a |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_normal_sleep_all_wake_ups:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=727040372 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_pwrmgr_deep_sleep_all_wake_ups_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work space/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_normal_sleep_all_wake_ups.727040372 |
| Directory | /workspace/1.chip_sw_pwrmgr_normal_sleep_all_wake_ups/latest |
| Test location | /workspace/coverage/default/1.chip_sw_pwrmgr_normal_sleep_por_reset.3853696795 |
| Short name | T433 |
| Test name | |
| Test status | |
| Simulation time | 6446793488 ps |
| CPU time | 670.22 seconds |
| Started | Jun 29 07:44:47 PM PDT 24 |
| Finished | Jun 29 07:55:58 PM PDT 24 |
| Peak memory | 609240 kb |
| Host | smart-4402c1fd-03ba-45fd-80eb-5e54dea84710 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_normal_sleep_por_reset_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3853696795 -assert nopostpr oc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sleep_por_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera ge/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_normal_sleep_por_reset.3853696795 |
| Directory | /workspace/1.chip_sw_pwrmgr_normal_sleep_por_reset/latest |
| Test location | /workspace/coverage/default/1.chip_sw_pwrmgr_random_sleep_all_reset_reqs.2730971530 |
| Short name | T1116 |
| Test name | |
| Test status | |
| Simulation time | 21400270313 ps |
| CPU time | 2426.22 seconds |
| Started | Jun 29 07:44:16 PM PDT 24 |
| Finished | Jun 29 08:24:43 PM PDT 24 |
| Peak memory | 609376 kb |
| Host | smart-59834fa5-404f-4c52-8e49-7b23f6a15b74 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=50_000_000 +sw_build_device=sim_dv +sw_images=pwrmgr_random_sleep_all_reset_reqs_test:1:new_rules,test_rom :0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=2730971530 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_deep_sleep_all_reset_vseq +en_cov=1 -cm line+cond+fsm+tg l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_random_sleep_all_reset_reqs.2730971530 |
| Directory | /workspace/1.chip_sw_pwrmgr_random_sleep_all_reset_reqs/latest |
| Test location | /workspace/coverage/default/1.chip_sw_pwrmgr_random_sleep_all_wake_ups.974301237 |
| Short name | T1 |
| Test name | |
| Test status | |
| Simulation time | 22336690576 ps |
| CPU time | 1829.33 seconds |
| Started | Jun 29 07:49:52 PM PDT 24 |
| Finished | Jun 29 08:20:23 PM PDT 24 |
| Peak memory | 608712 kb |
| Host | smart-5dcb6542-47d1-442b-82ee-6f470f940c4b |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +do_random=1 +sw_build_device=sim_dv +sw_images=pwrmgr_random_sleep_all_wake_ups:1:new_rules,te st_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n tb_random_seed=974301237 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_pwrmgr_deep_sleep_all_wake_ups_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_random_sleep_all_wake_ups.974301237 |
| Directory | /workspace/1.chip_sw_pwrmgr_random_sleep_all_wake_ups/latest |
| Test location | /workspace/coverage/default/1.chip_sw_pwrmgr_random_sleep_power_glitch_reset.1233283698 |
| Short name | T421 |
| Test name | |
| Test status | |
| Simulation time | 40776822335 ps |
| CPU time | 3327.06 seconds |
| Started | Jun 29 07:46:38 PM PDT 24 |
| Finished | Jun 29 08:42:06 PM PDT 24 |
| Peak memory | 609836 kb |
| Host | smart-70e9315d-3394-4c0c-b11f-e098f5e2590d |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_test_timeout_ns=24_000_000 +sw_build_device=sim_dv +sw_images=pwrmgr_random_sleep_power _glitch_reset_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1233283698 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_random_power_glit ch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_random_s leep_power_glitch_reset.1233283698 |
| Directory | /workspace/1.chip_sw_pwrmgr_random_sleep_power_glitch_reset/latest |
| Test location | /workspace/coverage/default/1.chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up.772096080 |
| Short name | T350 |
| Test name | |
| Test status | |
| Simulation time | 5808620730 ps |
| CPU time | 556.13 seconds |
| Started | Jun 29 07:50:39 PM PDT 24 |
| Finished | Jun 29 07:59:55 PM PDT 24 |
| Peak memory | 608748 kb |
| Host | smart-c7e4bdd2-8acd-428c-baa5-a75d1625310b |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +do_random=1 +sw_build_device=sim_dv +sw_images=pwrmgr_sensor_ctrl_deep_sleep_wake_up:1:new_rul es,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t cl +ntb_random_seed=772096080 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_sensor_ctrl_deep_sl eep_wake_up.772096080 |
| Directory | /workspace/1.chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up/latest |
| Test location | /workspace/coverage/default/1.chip_sw_pwrmgr_sleep_disabled.4183011645 |
| Short name | T657 |
| Test name | |
| Test status | |
| Simulation time | 3051823384 ps |
| CPU time | 245.9 seconds |
| Started | Jun 29 07:44:10 PM PDT 24 |
| Finished | Jun 29 07:48:16 PM PDT 24 |
| Peak memory | 609140 kb |
| Host | smart-4fc3cf25-2ef4-4c8b-aa51-5fabf2c18c80 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_sleep_disabled_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4183011645 -assert nopostproc +UVM_ TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_ log /dev/null -cm_name 1.chip_sw_pwrmgr_sleep_disabled.4183011645 |
| Directory | /workspace/1.chip_sw_pwrmgr_sleep_disabled/latest |
| Test location | /workspace/coverage/default/1.chip_sw_pwrmgr_sleep_power_glitch_reset.1648150615 |
| Short name | T1100 |
| Test name | |
| Test status | |
| Simulation time | 5797653340 ps |
| CPU time | 688.79 seconds |
| Started | Jun 29 07:44:21 PM PDT 24 |
| Finished | Jun 29 07:55:50 PM PDT 24 |
| Peak memory | 615560 kb |
| Host | smart-6e17fa45-97ba-474b-ba9e-98b315a9e8f9 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=pwrmgr_sleep_power_glitch_test:1:new_rules,test_rom:0 +c dc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_s eed=1648150615 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_main_power_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_sleep_power_glitch_reset.1648150615 |
| Directory | /workspace/1.chip_sw_pwrmgr_sleep_power_glitch_reset/latest |
| Test location | /workspace/coverage/default/1.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup.771715234 |
| Short name | T126 |
| Test name | |
| Test status | |
| Simulation time | 5888085164 ps |
| CPU time | 622.23 seconds |
| Started | Jun 29 07:47:36 PM PDT 24 |
| Finished | Jun 29 07:57:58 PM PDT 24 |
| Peak memory | 609220 kb |
| Host | smart-d486422e-26e0-47d6-8d3f-0368f5448544 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=8_000_000 +sw_build_device=sim_dv +sw_images=sensor_ctrl_wakeup_test:1:new_rules,test_rom:0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77171523 4 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace /coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup.771715234 |
| Directory | /workspace/1.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup/latest |
| Test location | /workspace/coverage/default/1.chip_sw_pwrmgr_sleep_wake_5_bug.2326725653 |
| Short name | T967 |
| Test name | |
| Test status | |
| Simulation time | 6112977650 ps |
| CPU time | 530.28 seconds |
| Started | Jun 29 07:49:50 PM PDT 24 |
| Finished | Jun 29 07:58:41 PM PDT 24 |
| Peak memory | 609240 kb |
| Host | smart-7f89c9e6-2763-4a6a-bc95-74035d1f8e06 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +do_random=1 +sw_build_device=sim_dv +sw_images=pwrmgr_sleep_wake_5_bug_test:1:new_rules,test_r om:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r andom_seed=2326725653 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_sleep_wake_5_bug.2326725653 |
| Directory | /workspace/1.chip_sw_pwrmgr_sleep_wake_5_bug/latest |
| Test location | /workspace/coverage/default/1.chip_sw_pwrmgr_smoketest.782478467 |
| Short name | T1176 |
| Test name | |
| Test status | |
| Simulation time | 4892325358 ps |
| CPU time | 509.24 seconds |
| Started | Jun 29 07:51:59 PM PDT 24 |
| Finished | Jun 29 08:00:29 PM PDT 24 |
| Peak memory | 609236 kb |
| Host | smart-794c22a5-0a4a-45d3-8034-57f7bb7c8a73 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=10000000 +sw_build_device=sim_dv +sw_images=pwrmgr_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=782478467 -asser t nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag e/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_smoketest.782478467 |
| Directory | /workspace/1.chip_sw_pwrmgr_smoketest/latest |
| Test location | /workspace/coverage/default/1.chip_sw_pwrmgr_sysrst_ctrl_reset.643165848 |
| Short name | T913 |
| Test name | |
| Test status | |
| Simulation time | 6802297605 ps |
| CPU time | 1348.74 seconds |
| Started | Jun 29 07:42:01 PM PDT 24 |
| Finished | Jun 29 08:04:31 PM PDT 24 |
| Peak memory | 608124 kb |
| Host | smart-120e4daf-bd7d-473d-9b01-fe176b627214 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_sysrst_ctrl_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=643165848 -assert nopostproc +UVM_TEST NAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb - cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_sysrst_ctrl_reset.643165848 |
| Directory | /workspace/1.chip_sw_pwrmgr_sysrst_ctrl_reset/latest |
| Test location | /workspace/coverage/default/1.chip_sw_pwrmgr_usb_clk_disabled_when_active.3990655895 |
| Short name | T146 |
| Test name | |
| Test status | |
| Simulation time | 5091560488 ps |
| CPU time | 610.02 seconds |
| Started | Jun 29 07:42:13 PM PDT 24 |
| Finished | Jun 29 07:52:23 PM PDT 24 |
| Peak memory | 609248 kb |
| Host | smart-bd840fd0-c143-42dd-967b-a811cc4ced2f |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_usb_clk_disabled_when_active_test:1:new_rules,test_rom:0 +cdc_instrumentation_enable d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3990655895 -assert no postproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de fault.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_usb_clk_disabled_when_active.3990655895 |
| Directory | /workspace/1.chip_sw_pwrmgr_usb_clk_disabled_when_active/latest |
| Test location | /workspace/coverage/default/1.chip_sw_pwrmgr_usbdev_smoketest.467452464 |
| Short name | T247 |
| Test name | |
| Test status | |
| Simulation time | 5592825208 ps |
| CPU time | 488.3 seconds |
| Started | Jun 29 07:53:37 PM PDT 24 |
| Finished | Jun 29 08:01:45 PM PDT 24 |
| Peak memory | 607972 kb |
| Host | smart-b36faf82-69de-4812-ba62-bd8555f80e86 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_usbdev_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=467452464 -assert nopostproc +UVM_TEST NAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_usbdev_smoketest.467452464 |
| Directory | /workspace/1.chip_sw_pwrmgr_usbdev_smoketest/latest |
| Test location | /workspace/coverage/default/1.chip_sw_pwrmgr_wdog_reset.3478120344 |
| Short name | T930 |
| Test name | |
| Test status | |
| Simulation time | 3491599320 ps |
| CPU time | 356.33 seconds |
| Started | Jun 29 07:43:54 PM PDT 24 |
| Finished | Jun 29 07:49:50 PM PDT 24 |
| Peak memory | 607104 kb |
| Host | smart-ca3a0b1b-6eac-499c-b46e-3bffd2bb1355 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=pwrmgr_wdog_reset_reqs_test:1:new_rules,test_rom:0 +cdc_inst rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=347 8120344 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_wdog_reset.3478120344 |
| Directory | /workspace/1.chip_sw_pwrmgr_wdog_reset/latest |
| Test location | /workspace/coverage/default/1.chip_sw_rom_ctrl_integrity_check.854689043 |
| Short name | T1270 |
| Test name | |
| Test status | |
| Simulation time | 8240589582 ps |
| CPU time | 654.13 seconds |
| Started | Jun 29 07:47:10 PM PDT 24 |
| Finished | Jun 29 07:58:04 PM PDT 24 |
| Peak memory | 608016 kb |
| Host | smart-24bf2abc-9300-41f7-a898-971dec152fb7 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=rom_ctrl_integrity_check_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=854689043 -assert nopostproc +UV M_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_ctrl_integrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov erage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_rom_ctrl_integrity_check.854689043 |
| Directory | /workspace/1.chip_sw_rom_ctrl_integrity_check/latest |
| Test location | /workspace/coverage/default/1.chip_sw_rstmgr_cpu_info.1425869797 |
| Short name | T238 |
| Test name | |
| Test status | |
| Simulation time | 7157591654 ps |
| CPU time | 827.87 seconds |
| Started | Jun 29 07:43:34 PM PDT 24 |
| Finished | Jun 29 07:57:23 PM PDT 24 |
| Peak memory | 607988 kb |
| Host | smart-2b118eac-05be-4766-aed3-45e6359fd53c |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=rstmgr_cpu_info_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1425869797 -assert nopostproc +UVM_TESTNA ME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 1.chip_sw_rstmgr_cpu_info.1425869797 |
| Directory | /workspace/1.chip_sw_rstmgr_cpu_info/latest |
| Test location | /workspace/coverage/default/1.chip_sw_rstmgr_rst_cnsty_escalation.590358920 |
| Short name | T1149 |
| Test name | |
| Test status | |
| Simulation time | 6106605824 ps |
| CPU time | 617.73 seconds |
| Started | Jun 29 07:41:11 PM PDT 24 |
| Finished | Jun 29 07:51:29 PM PDT 24 |
| Peak memory | 639696 kb |
| Host | smart-df7b500a-87f6-4104-8649-2938b52ee95d |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 590358920 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rstmgr_cnsty_fault_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_rstmgr_rst_cnsty_escalation.590358920 |
| Directory | /workspace/1.chip_sw_rstmgr_rst_cnsty_escalation/latest |
| Test location | /workspace/coverage/default/1.chip_sw_rstmgr_smoketest.686046740 |
| Short name | T435 |
| Test name | |
| Test status | |
| Simulation time | 3374413420 ps |
| CPU time | 337.16 seconds |
| Started | Jun 29 07:54:40 PM PDT 24 |
| Finished | Jun 29 08:00:17 PM PDT 24 |
| Peak memory | 607120 kb |
| Host | smart-d600a34f-161c-430d-ad87-8f930bc42b40 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=rstmgr_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=686046740 -assert nopostproc +UVM_TESTNAME=ch ip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu ll -cm_name 1.chip_sw_rstmgr_smoketest.686046740 |
| Directory | /workspace/1.chip_sw_rstmgr_smoketest/latest |
| Test location | /workspace/coverage/default/1.chip_sw_rstmgr_sw_req.1512050484 |
| Short name | T261 |
| Test name | |
| Test status | |
| Simulation time | 5037110260 ps |
| CPU time | 419.88 seconds |
| Started | Jun 29 07:46:47 PM PDT 24 |
| Finished | Jun 29 07:53:48 PM PDT 24 |
| Peak memory | 607196 kb |
| Host | smart-da211eb8-8956-403c-92af-61cbe8d78756 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=rstmgr_sw_req_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1512050484 -assert nopostproc +UVM_TESTNAME =chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 1.chip_sw_rstmgr_sw_req.1512050484 |
| Directory | /workspace/1.chip_sw_rstmgr_sw_req/latest |
| Test location | /workspace/coverage/default/1.chip_sw_rstmgr_sw_rst.2107175973 |
| Short name | T1156 |
| Test name | |
| Test status | |
| Simulation time | 3035360500 ps |
| CPU time | 245.27 seconds |
| Started | Jun 29 07:44:48 PM PDT 24 |
| Finished | Jun 29 07:48:54 PM PDT 24 |
| Peak memory | 609188 kb |
| Host | smart-aa2209b2-2cb1-4bf9-aea6-14802f771472 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=rstmgr_sw_rst_ctrl_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2107175973 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_rstmgr_sw_rst.2107175973 |
| Directory | /workspace/1.chip_sw_rstmgr_sw_rst/latest |
| Test location | /workspace/coverage/default/1.chip_sw_rv_core_ibex_address_translation.2738195101 |
| Short name | T188 |
| Test name | |
| Test status | |
| Simulation time | 2821801692 ps |
| CPU time | 280.13 seconds |
| Started | Jun 29 07:50:20 PM PDT 24 |
| Finished | Jun 29 07:55:00 PM PDT 24 |
| Peak memory | 607612 kb |
| Host | smart-c2648063-99d9-4ff7-90c7-dd4819b6f292 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=7_000_000 +sw_build_device=sim_dv +sw_images=rv_core_ibex_address_translation_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=2738195101 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_rv_core_ibex_address_translation.2738195101 |
| Directory | /workspace/1.chip_sw_rv_core_ibex_address_translation/latest |
| Test location | /workspace/coverage/default/1.chip_sw_rv_core_ibex_icache_invalidate.3762567310 |
| Short name | T264 |
| Test name | |
| Test status | |
| Simulation time | 2318761000 ps |
| CPU time | 200.96 seconds |
| Started | Jun 29 07:51:34 PM PDT 24 |
| Finished | Jun 29 07:54:56 PM PDT 24 |
| Peak memory | 609188 kb |
| Host | smart-2fe035ad-0e77-44b6-81bb-9c9e320f88e1 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=rv_core_ibex_icache_invalidate_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3762567310 -assert nopostp roc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rv_core_ibex_icache_invalidate_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_rv_core_ibex_icache_invalidate.3762567310 |
| Directory | /workspace/1.chip_sw_rv_core_ibex_icache_invalidate/latest |
| Test location | /workspace/coverage/default/1.chip_sw_rv_core_ibex_nmi_irq.3417717286 |
| Short name | T230 |
| Test name | |
| Test status | |
| Simulation time | 4841392336 ps |
| CPU time | 797.55 seconds |
| Started | Jun 29 07:43:17 PM PDT 24 |
| Finished | Jun 29 07:56:35 PM PDT 24 |
| Peak memory | 607572 kb |
| Host | smart-37fb7710-5d14-40bd-a7b8-14006059d6e2 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=10_000_000 +sw_build_device=sim_dv +sw_images=rv_core_ibex_nmi_irq_test:1:new_rules,test_rom:0 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34177 17286 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_rv_core_ibex_nmi_irq.3417717286 |
| Directory | /workspace/1.chip_sw_rv_core_ibex_nmi_irq/latest |
| Test location | /workspace/coverage/default/1.chip_sw_rv_core_ibex_rnd.1877479529 |
| Short name | T1265 |
| Test name | |
| Test status | |
| Simulation time | 5735068400 ps |
| CPU time | 1074.84 seconds |
| Started | Jun 29 07:48:39 PM PDT 24 |
| Finished | Jun 29 08:06:35 PM PDT 24 |
| Peak memory | 609172 kb |
| Host | smart-57cb3a1d-4af9-4263-a985-d477cc13d0a2 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=20_000_000 +rng_srate_value_max=32 +sw_build_device=sim_dv +sw_images=rv_core_ibex_rnd_test:1:new_rules,te st_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n tb_random_seed=1877479529 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_rv_core_ibex_rnd.1877479529 |
| Directory | /workspace/1.chip_sw_rv_core_ibex_rnd/latest |
| Test location | /workspace/coverage/default/1.chip_sw_rv_dm_access_after_escalation_reset.483646874 |
| Short name | T640 |
| Test name | |
| Test status | |
| Simulation time | 4828977311 ps |
| CPU time | 649.7 seconds |
| Started | Jun 29 07:50:09 PM PDT 24 |
| Finished | Jun 29 08:01:00 PM PDT 24 |
| Peak memory | 618064 kb |
| Host | smart-df0a8c15-45d3-4941-ace8-1a230d647a11 |
| User | root |
| Command | /workspace/default/simv +use_jtag_dmi=1 +sw_build_device=sim_dv +sw_images=alert_handler_escalation_test:1:new_rules,test_rom:0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=483646874 -asser t nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rv_dm_access_after_escalation_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_rv_dm_access_after_escalation_reset.483646874 |
| Directory | /workspace/1.chip_sw_rv_dm_access_after_escalation_reset/latest |
| Test location | /workspace/coverage/default/1.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted.3960491954 |
| Short name | T233 |
| Test name | |
| Test status | |
| Simulation time | 4133355760 ps |
| CPU time | 432.87 seconds |
| Started | Jun 29 07:50:12 PM PDT 24 |
| Finished | Jun 29 07:57:25 PM PDT 24 |
| Peak memory | 617660 kb |
| Host | smart-f58dd432-e31b-4c2a-8f7f-ccb39ec28e79 |
| User | root |
| Command | /workspace/default/simv +use_jtag_dmi=1 +sw_build_device=sim_dv +sw_images=rv_dm_ndm_reset_req_when_cpu_halted_rma:1:new_rules,test_rom:0 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=396049 1954 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rv_dm_ndm_reset_when_cpu_halted_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted.3960491954 |
| Directory | /workspace/1.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted/latest |
| Test location | /workspace/coverage/default/1.chip_sw_rv_plic_smoketest.2065489279 |
| Short name | T270 |
| Test name | |
| Test status | |
| Simulation time | 2978967756 ps |
| CPU time | 291.31 seconds |
| Started | Jun 29 07:52:30 PM PDT 24 |
| Finished | Jun 29 07:57:21 PM PDT 24 |
| Peak memory | 609196 kb |
| Host | smart-1df2bb64-dd36-4462-a88a-b7b039879c7a |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=rv_plic_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2065489279 -assert nopostproc +UVM_TESTNAME= chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/ null -cm_name 1.chip_sw_rv_plic_smoketest.2065489279 |
| Directory | /workspace/1.chip_sw_rv_plic_smoketest/latest |
| Test location | /workspace/coverage/default/1.chip_sw_rv_timer_irq.1162035500 |
| Short name | T419 |
| Test name | |
| Test status | |
| Simulation time | 3661798340 ps |
| CPU time | 309.07 seconds |
| Started | Jun 29 07:43:05 PM PDT 24 |
| Finished | Jun 29 07:48:14 PM PDT 24 |
| Peak memory | 607312 kb |
| Host | smart-5726cdd5-ebec-45d8-91d9-b2e00f2f7451 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=rv_timer_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1162035500 -assert nopostproc +UVM_TESTNAME =chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 1.chip_sw_rv_timer_irq.1162035500 |
| Directory | /workspace/1.chip_sw_rv_timer_irq/latest |
| Test location | /workspace/coverage/default/1.chip_sw_rv_timer_smoketest.2978816707 |
| Short name | T1172 |
| Test name | |
| Test status | |
| Simulation time | 2746658392 ps |
| CPU time | 254.76 seconds |
| Started | Jun 29 07:52:22 PM PDT 24 |
| Finished | Jun 29 07:56:37 PM PDT 24 |
| Peak memory | 607188 kb |
| Host | smart-b601245a-c79a-43fb-90a8-26a7dc41fc16 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=rv_timer_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2978816707 -assert nopostproc +UVM_TESTNAME =chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 1.chip_sw_rv_timer_smoketest.2978816707 |
| Directory | /workspace/1.chip_sw_rv_timer_smoketest/latest |
| Test location | /workspace/coverage/default/1.chip_sw_sensor_ctrl_alert.1014409494 |
| Short name | T121 |
| Test name | |
| Test status | |
| Simulation time | 5750657180 ps |
| CPU time | 594.76 seconds |
| Started | Jun 29 07:48:14 PM PDT 24 |
| Finished | Jun 29 07:58:09 PM PDT 24 |
| Peak memory | 608232 kb |
| Host | smart-82d369d5-d614-4f1c-b650-e1f546ef9d88 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=40_000_000 +sw_build_device=sim_dv +sw_images=sensor_ctrl_alert_test:1:new_rules,test_rom:0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10144094 94 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac e/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_sensor_ctrl_alert.1014409494 |
| Directory | /workspace/1.chip_sw_sensor_ctrl_alert/latest |
| Test location | /workspace/coverage/default/1.chip_sw_sensor_ctrl_status.3649401190 |
| Short name | T328 |
| Test name | |
| Test status | |
| Simulation time | 3229462979 ps |
| CPU time | 267.26 seconds |
| Started | Jun 29 07:48:06 PM PDT 24 |
| Finished | Jun 29 07:52:34 PM PDT 24 |
| Peak memory | 608604 kb |
| Host | smart-ab38e77a-d84a-4197-920b-693e21b9a2b1 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=40_000_000 +sw_build_device=sim_dv +sw_images=sensor_ctrl_status_test:1:new_rules,test_rom:0 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3649401 190 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sensor_ctrl_status_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_sensor_ctrl_status.3649401190 |
| Directory | /workspace/1.chip_sw_sensor_ctrl_status/latest |
| Test location | /workspace/coverage/default/1.chip_sw_sleep_pin_retention.1559646039 |
| Short name | T10 |
| Test name | |
| Test status | |
| Simulation time | 4005025650 ps |
| CPU time | 464.18 seconds |
| Started | Jun 29 07:42:52 PM PDT 24 |
| Finished | Jun 29 07:50:37 PM PDT 24 |
| Peak memory | 608004 kb |
| Host | smart-e6d8c0ad-5831-46e2-b62c-d07346cccc22 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=sleep_pin_retention_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1559646039 -assert nopostproc +UVM_TE STNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sleep_pin_retention_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def ault.vdb -cm_log /dev/null -cm_name 1.chip_sw_sleep_pin_retention.1559646039 |
| Directory | /workspace/1.chip_sw_sleep_pin_retention/latest |
| Test location | /workspace/coverage/default/1.chip_sw_sleep_pwm_pulses.451075492 |
| Short name | T1159 |
| Test name | |
| Test status | |
| Simulation time | 8540763228 ps |
| CPU time | 1507.57 seconds |
| Started | Jun 29 07:41:29 PM PDT 24 |
| Finished | Jun 29 08:06:38 PM PDT 24 |
| Peak memory | 608220 kb |
| Host | smart-1d51a7d5-f374-4f0c-8e65-5d921fc3ad4b |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=sleep_pwm_pulses_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=451075492 -assert nopostproc +UVM_TESTNA ME=chip_base_test +UVM_TEST_SEQ=chip_sw_pwm_pulses_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_ log /dev/null -cm_name 1.chip_sw_sleep_pwm_pulses.451075492 |
| Directory | /workspace/1.chip_sw_sleep_pwm_pulses/latest |
| Test location | /workspace/coverage/default/1.chip_sw_sleep_sram_ret_contents_no_scramble.528535176 |
| Short name | T102 |
| Test name | |
| Test status | |
| Simulation time | 7331385120 ps |
| CPU time | 697.34 seconds |
| Started | Jun 29 07:47:52 PM PDT 24 |
| Finished | Jun 29 07:59:29 PM PDT 24 |
| Peak memory | 609248 kb |
| Host | smart-cb48c7c3-2d2b-4816-b495-e6a264950c92 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=20_000_000 +en_scb_tl_err_chk=0 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=sram _ctrl_sleep_sram_ret_contents_no_scramble_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=528535176 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SE Q=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_sle ep_sram_ret_contents_no_scramble.528535176 |
| Directory | /workspace/1.chip_sw_sleep_sram_ret_contents_no_scramble/latest |
| Test location | /workspace/coverage/default/1.chip_sw_sleep_sram_ret_contents_scramble.997430648 |
| Short name | T1238 |
| Test name | |
| Test status | |
| Simulation time | 9252211248 ps |
| CPU time | 736.68 seconds |
| Started | Jun 29 07:47:32 PM PDT 24 |
| Finished | Jun 29 07:59:49 PM PDT 24 |
| Peak memory | 608468 kb |
| Host | smart-9ddbbeaf-861a-4fbb-8290-b5ef8287b008 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=20_000_000 +en_scb_tl_err_chk=0 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=sram _ctrl_sleep_sram_ret_contents_scramble_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=997430648 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=c hip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_sleep_ sram_ret_contents_scramble.997430648 |
| Directory | /workspace/1.chip_sw_sleep_sram_ret_contents_scramble/latest |
| Test location | /workspace/coverage/default/1.chip_sw_spi_device_pass_through.3683964048 |
| Short name | T151 |
| Test name | |
| Test status | |
| Simulation time | 6156695306 ps |
| CPU time | 654.49 seconds |
| Started | Jun 29 07:42:24 PM PDT 24 |
| Finished | Jun 29 07:53:20 PM PDT 24 |
| Peak memory | 624192 kb |
| Host | smart-e4935210-225d-49d8-ab86-a3928f88ca37 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=spi_passthrough_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3683964048 -assert nopostproc +UVM_TESTNA ME=chip_base_test +UVM_TEST_SEQ=chip_sw_spi_passthrough_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_spi_device_pass_through.3683964048 |
| Directory | /workspace/1.chip_sw_spi_device_pass_through/latest |
| Test location | /workspace/coverage/default/1.chip_sw_spi_device_pass_through_collision.3264625290 |
| Short name | T150 |
| Test name | |
| Test status | |
| Simulation time | 4652808140 ps |
| CPU time | 465.98 seconds |
| Started | Jun 29 07:47:25 PM PDT 24 |
| Finished | Jun 29 07:55:11 PM PDT 24 |
| Peak memory | 624284 kb |
| Host | smart-5332566b-71a8-44c8-ba13-cf3dcbc0a424 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=spi_passthrough_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3264625290 -assert nopostproc +UVM_TESTNA ME=chip_base_test +UVM_TEST_SEQ=chip_sw_spi_passthrough_collision_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/d efault.vdb -cm_log /dev/null -cm_name 1.chip_sw_spi_device_pass_through_collision.3264625290 |
| Directory | /workspace/1.chip_sw_spi_device_pass_through_collision/latest |
| Test location | /workspace/coverage/default/1.chip_sw_spi_device_tpm.957652738 |
| Short name | T46 |
| Test name | |
| Test status | |
| Simulation time | 3570526306 ps |
| CPU time | 329.08 seconds |
| Started | Jun 29 07:41:14 PM PDT 24 |
| Finished | Jun 29 07:46:43 PM PDT 24 |
| Peak memory | 616556 kb |
| Host | smart-e43ad5b6-ef44-4bb4-9f20-759ed339e360 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=spi_device_tpm_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=957652738 -assert nopostproc +UVM_TE STNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_spi_device_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 1.chip_sw_spi_device_tpm.957652738 |
| Directory | /workspace/1.chip_sw_spi_device_tpm/latest |
| Test location | /workspace/coverage/default/1.chip_sw_spi_host_tx_rx.4278008805 |
| Short name | T24 |
| Test name | |
| Test status | |
| Simulation time | 2634697842 ps |
| CPU time | 237.44 seconds |
| Started | Jun 29 07:41:04 PM PDT 24 |
| Finished | Jun 29 07:45:02 PM PDT 24 |
| Peak memory | 607984 kb |
| Host | smart-2536c355-de0d-423b-9bdb-2b34f08f917f |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=spi_host_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4278008805 -assert nopostproc +UVM_TESTNAM E=chip_base_test +UVM_TEST_SEQ=chip_sw_spi_host_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb - cm_log /dev/null -cm_name 1.chip_sw_spi_host_tx_rx.4278008805 |
| Directory | /workspace/1.chip_sw_spi_host_tx_rx/latest |
| Test location | /workspace/coverage/default/1.chip_sw_sram_ctrl_execution_main.3799371017 |
| Short name | T273 |
| Test name | |
| Test status | |
| Simulation time | 6332354559 ps |
| CPU time | 666.83 seconds |
| Started | Jun 29 07:47:24 PM PDT 24 |
| Finished | Jun 29 07:58:32 PM PDT 24 |
| Peak memory | 609184 kb |
| Host | smart-b4b7edc5-3be9-4e35-b5fb-270b41a0f431 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=sram_ctrl_execution_main_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3799371017 -assert nopostproc +U VM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sram_ctrl_execution_main_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co verage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_sram_ctrl_execution_main.3799371017 |
| Directory | /workspace/1.chip_sw_sram_ctrl_execution_main/latest |
| Test location | /workspace/coverage/default/1.chip_sw_sram_ctrl_scrambled_access.2167913854 |
| Short name | T183 |
| Test name | |
| Test status | |
| Simulation time | 3661970840 ps |
| CPU time | 524.04 seconds |
| Started | Jun 29 07:47:06 PM PDT 24 |
| Finished | Jun 29 07:55:51 PM PDT 24 |
| Peak memory | 608512 kb |
| Host | smart-a55ca960-1336-4de6-a19d-e8076982a829 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=12_000_000 +en_scb_tl_err_chk=0 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=sram _ctrl_scrambled_access_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2167913854 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sram_ctr l_scrambled_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw _sram_ctrl_scrambled_access.2167913854 |
| Directory | /workspace/1.chip_sw_sram_ctrl_scrambled_access/latest |
| Test location | /workspace/coverage/default/1.chip_sw_sram_ctrl_scrambled_access_jitter_en.1730006690 |
| Short name | T263 |
| Test name | |
| Test status | |
| Simulation time | 5053288535 ps |
| CPU time | 666.77 seconds |
| Started | Jun 29 07:48:16 PM PDT 24 |
| Finished | Jun 29 07:59:24 PM PDT 24 |
| Peak memory | 608596 kb |
| Host | smart-f3ced254-4619-4bc7-8276-309f07bc4761 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=12_000_000 +bypass_alert_ready_to_end_check=1 +en_jitter=1 +en_scb_tl_err_chk=0 +sw_build_device=sim_dv +s w_images=sram_ctrl_scrambled_access_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1730006690 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chi p_sw_sram_ctrl_scrambled_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n ame 1.chip_sw_sram_ctrl_scrambled_access_jitter_en.1730006690 |
| Directory | /workspace/1.chip_sw_sram_ctrl_scrambled_access_jitter_en/latest |
| Test location | /workspace/coverage/default/1.chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq.1336705579 |
| Short name | T184 |
| Test name | |
| Test status | |
| Simulation time | 5724768109 ps |
| CPU time | 639.22 seconds |
| Started | Jun 29 07:52:51 PM PDT 24 |
| Finished | Jun 29 08:03:31 PM PDT 24 |
| Peak memory | 608564 kb |
| Host | smart-b9f0234f-05f1-46c4-bd42-180eb198fe72 |
| User | root |
| Command | /workspace/default/simv +mem_sel=main +sw_test_timeout_ns=12_000_000 +bypass_alert_ready_to_end_check=1 +en_jitter=1 +en_scb_tl_err_chk=0 +cal_sys_clk _70mhz=1 +sw_build_device=sim_dv +sw_images=sram_ctrl_scrambled_access_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1336705579 -assert nopostproc +UVM_TESTNA ME=chip_base_test +UVM_TEST_SEQ=chip_sw_sram_ctrl_scrambled_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/ default.vdb -cm_log /dev/null -cm_name 1.chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq.1336705579 |
| Directory | /workspace/1.chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq/latest |
| Test location | /workspace/coverage/default/1.chip_sw_sram_ctrl_smoketest.2754546932 |
| Short name | T912 |
| Test name | |
| Test status | |
| Simulation time | 3013200168 ps |
| CPU time | 315.41 seconds |
| Started | Jun 29 07:53:15 PM PDT 24 |
| Finished | Jun 29 07:58:31 PM PDT 24 |
| Peak memory | 609192 kb |
| Host | smart-03eb96ae-b93d-4806-a09e-a1b3dbd67645 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=sram_ctrl_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2754546932 -assert nopostproc +UVM_TESTNAM E=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 1.chip_sw_sram_ctrl_smoketest.2754546932 |
| Directory | /workspace/1.chip_sw_sram_ctrl_smoketest/latest |
| Test location | /workspace/coverage/default/1.chip_sw_sysrst_ctrl_ec_rst_l.558083588 |
| Short name | T31 |
| Test name | |
| Test status | |
| Simulation time | 21209311943 ps |
| CPU time | 3532.4 seconds |
| Started | Jun 29 07:44:34 PM PDT 24 |
| Finished | Jun 29 08:43:28 PM PDT 24 |
| Peak memory | 607316 kb |
| Host | smart-ccec2cf0-1032-4021-9298-b44510b029ce |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=sysrst_ctrl_ec_rst_l_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=558083588 -assert nopostproc +UVM_TE STNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_ec_rst_l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de fault.vdb -cm_log /dev/null -cm_name 1.chip_sw_sysrst_ctrl_ec_rst_l.558083588 |
| Directory | /workspace/1.chip_sw_sysrst_ctrl_ec_rst_l/latest |
| Test location | /workspace/coverage/default/1.chip_sw_sysrst_ctrl_in_irq.3242371955 |
| Short name | T158 |
| Test name | |
| Test status | |
| Simulation time | 4512280005 ps |
| CPU time | 636.15 seconds |
| Started | Jun 29 07:43:02 PM PDT 24 |
| Finished | Jun 29 07:53:40 PM PDT 24 |
| Peak memory | 612508 kb |
| Host | smart-3b0d1d86-ee1f-44df-bdc2-033b080e937c |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=sysrst_ctrl_in_irq_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3242371955 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_in_irq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau lt.vdb -cm_log /dev/null -cm_name 1.chip_sw_sysrst_ctrl_in_irq.3242371955 |
| Directory | /workspace/1.chip_sw_sysrst_ctrl_in_irq/latest |
| Test location | /workspace/coverage/default/1.chip_sw_sysrst_ctrl_inputs.1039602624 |
| Short name | T1255 |
| Test name | |
| Test status | |
| Simulation time | 3285403703 ps |
| CPU time | 265.55 seconds |
| Started | Jun 29 07:44:20 PM PDT 24 |
| Finished | Jun 29 07:48:47 PM PDT 24 |
| Peak memory | 612180 kb |
| Host | smart-2ee01c1b-88e3-4a55-8755-5edbb3ed02ba |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=sysrst_ctrl_inputs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1039602624 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_inputs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau lt.vdb -cm_log /dev/null -cm_name 1.chip_sw_sysrst_ctrl_inputs.1039602624 |
| Directory | /workspace/1.chip_sw_sysrst_ctrl_inputs/latest |
| Test location | /workspace/coverage/default/1.chip_sw_sysrst_ctrl_outputs.2371459511 |
| Short name | T1258 |
| Test name | |
| Test status | |
| Simulation time | 3408513942 ps |
| CPU time | 371.06 seconds |
| Started | Jun 29 07:43:56 PM PDT 24 |
| Finished | Jun 29 07:50:08 PM PDT 24 |
| Peak memory | 609156 kb |
| Host | smart-e02fb3ac-8d72-4773-838a-ed6ee0d49787 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=sysrst_ctrl_outputs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2371459511 -assert nopostproc +UVM_TE STNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_outputs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def ault.vdb -cm_log /dev/null -cm_name 1.chip_sw_sysrst_ctrl_outputs.2371459511 |
| Directory | /workspace/1.chip_sw_sysrst_ctrl_outputs/latest |
| Test location | /workspace/coverage/default/1.chip_sw_sysrst_ctrl_reset.62283501 |
| Short name | T162 |
| Test name | |
| Test status | |
| Simulation time | 22614467434 ps |
| CPU time | 1825.41 seconds |
| Started | Jun 29 07:44:39 PM PDT 24 |
| Finished | Jun 29 08:15:05 PM PDT 24 |
| Peak memory | 612584 kb |
| Host | smart-c30f5b8a-e0e7-4bf0-bc31-b5a212def4c0 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=36_000_000 +sw_build_device=sim_dv +sw_images=sysrst_ctrl_reset_test:1:new_rules,test_rom:0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62283501 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_sysrst_ctrl_reset.62283501 |
| Directory | /workspace/1.chip_sw_sysrst_ctrl_reset/latest |
| Test location | /workspace/coverage/default/1.chip_sw_sysrst_ctrl_ulp_z3_wakeup.4066978015 |
| Short name | T44 |
| Test name | |
| Test status | |
| Simulation time | 5229238704 ps |
| CPU time | 435.16 seconds |
| Started | Jun 29 07:43:06 PM PDT 24 |
| Finished | Jun 29 07:50:22 PM PDT 24 |
| Peak memory | 609308 kb |
| Host | smart-4559ce5a-42bb-4256-bd56-ca89180c4c57 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=sysrst_ctrl_ulp_z3_wakeup_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4066978015 -assert nopostproc + UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_ulp_z3_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/ coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_sysrst_ctrl_ulp_z3_wakeup.4066978015 |
| Directory | /workspace/1.chip_sw_sysrst_ctrl_ulp_z3_wakeup/latest |
| Test location | /workspace/coverage/default/1.chip_sw_uart_rand_baudrate.2778341857 |
| Short name | T271 |
| Test name | |
| Test status | |
| Simulation time | 8562636590 ps |
| CPU time | 1765.3 seconds |
| Started | Jun 29 07:42:12 PM PDT 24 |
| Finished | Jun 29 08:11:38 PM PDT 24 |
| Peak memory | 618324 kb |
| Host | smart-fc07d8b9-0627-41f6-a9de-1d78396a7764 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=2778341857 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_uart_rand_baudrate.2778341857 |
| Directory | /workspace/1.chip_sw_uart_rand_baudrate/latest |
| Test location | /workspace/coverage/default/1.chip_sw_uart_smoketest.134963837 |
| Short name | T1085 |
| Test name | |
| Test status | |
| Simulation time | 2758143976 ps |
| CPU time | 217.52 seconds |
| Started | Jun 29 07:52:48 PM PDT 24 |
| Finished | Jun 29 07:56:26 PM PDT 24 |
| Peak memory | 609984 kb |
| Host | smart-58668705-f1e3-4f7c-8ed6-1a2372608a94 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=uart_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=134963837 -assert nopostproc +UVM_TESTNAME=chip _base_test +UVM_TEST_SEQ=chip_sw_uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 1.chip_sw_uart_smoketest.134963837 |
| Directory | /workspace/1.chip_sw_uart_smoketest/latest |
| Test location | /workspace/coverage/default/1.chip_sw_uart_tx_rx_alt_clk_freq.556479794 |
| Short name | T940 |
| Test name | |
| Test status | |
| Simulation time | 8034849186 ps |
| CPU time | 1692.23 seconds |
| Started | Jun 29 07:41:18 PM PDT 24 |
| Finished | Jun 29 08:09:31 PM PDT 24 |
| Peak memory | 620448 kb |
| Host | smart-b08fb123-c8b6-44ff-b9c2-93d1d1d3628d |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=80_000_000 +chip_clock_source=ChipClockSourceExternal96Mhz +calibrate_usb_clk=1 +sw_build_device=sim_dv +s w_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=556479794 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_ba udrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_uart_tx_rx_ alt_clk_freq.556479794 |
| Directory | /workspace/1.chip_sw_uart_tx_rx_alt_clk_freq/latest |
| Test location | /workspace/coverage/default/1.chip_sw_uart_tx_rx_bootstrap.2589714895 |
| Short name | T1026 |
| Test name | |
| Test status | |
| Simulation time | 78565062720 ps |
| CPU time | 13462 seconds |
| Started | Jun 29 07:42:14 PM PDT 24 |
| Finished | Jun 29 11:26:38 PM PDT 24 |
| Peak memory | 632316 kb |
| Host | smart-ae5529dc-fb8d-42f8-b061-611f393e7ec3 |
| User | root |
| Command | /workspace/default/simv +use_spi_load_bootstrap=1 +calibrate_usb_clk=1 +test_timeout_ns=160_000_000 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test :1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=2589714895 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_uart_tx_rx_bootstrap.2589714895 |
| Directory | /workspace/1.chip_sw_uart_tx_rx_bootstrap/latest |
| Test location | /workspace/coverage/default/1.chip_sw_uart_tx_rx_idx1.1761663795 |
| Short name | T1261 |
| Test name | |
| Test status | |
| Simulation time | 4795151664 ps |
| CPU time | 705.43 seconds |
| Started | Jun 29 07:40:16 PM PDT 24 |
| Finished | Jun 29 07:52:02 PM PDT 24 |
| Peak memory | 615880 kb |
| Host | smart-dd6dc311-bf05-4892-b28b-075a2f58e6e2 |
| User | root |
| Command | /workspace/default/simv +uart_idx=1 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1761663795 -a ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_uart_tx_rx_idx1.1761663795 |
| Directory | /workspace/1.chip_sw_uart_tx_rx_idx1/latest |
| Test location | /workspace/coverage/default/1.chip_sw_uart_tx_rx_idx2.3025700831 |
| Short name | T965 |
| Test name | |
| Test status | |
| Simulation time | 4902934790 ps |
| CPU time | 713.82 seconds |
| Started | Jun 29 07:42:44 PM PDT 24 |
| Finished | Jun 29 07:54:39 PM PDT 24 |
| Peak memory | 615880 kb |
| Host | smart-c23b8580-eca8-415e-b88b-d81dc0db7f1b |
| User | root |
| Command | /workspace/default/simv +uart_idx=2 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3025700831 -a ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_uart_tx_rx_idx2.3025700831 |
| Directory | /workspace/1.chip_sw_uart_tx_rx_idx2/latest |
| Test location | /workspace/coverage/default/1.chip_sw_uart_tx_rx_idx3.1876697184 |
| Short name | T1102 |
| Test name | |
| Test status | |
| Simulation time | 4196229610 ps |
| CPU time | 647.58 seconds |
| Started | Jun 29 07:41:22 PM PDT 24 |
| Finished | Jun 29 07:52:10 PM PDT 24 |
| Peak memory | 615856 kb |
| Host | smart-a2ee924c-f73e-4f44-8a05-d3f7f2213347 |
| User | root |
| Command | /workspace/default/simv +uart_idx=3 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1876697184 -a ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_uart_tx_rx_idx3.1876697184 |
| Directory | /workspace/1.chip_sw_uart_tx_rx_idx3/latest |
| Test location | /workspace/coverage/default/1.chip_tap_straps_dev.2222799160 |
| Short name | T1005 |
| Test name | |
| Test status | |
| Simulation time | 3408200844 ps |
| CPU time | 159.28 seconds |
| Started | Jun 29 07:49:15 PM PDT 24 |
| Finished | Jun 29 07:51:55 PM PDT 24 |
| Peak memory | 618716 kb |
| Host | smart-a2ff3ece-8c25-468f-b370-a2513673800d |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStDev +create_jtag_riscv_map=1 +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:test_in_rom: new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=2222799160 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_tap_straps_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_tap_straps_dev.2222799160 |
| Directory | /workspace/1.chip_tap_straps_dev/latest |
| Test location | /workspace/coverage/default/1.chip_tap_straps_prod.4087808863 |
| Short name | T1163 |
| Test name | |
| Test status | |
| Simulation time | 16669448426 ps |
| CPU time | 1981.78 seconds |
| Started | Jun 29 07:51:19 PM PDT 24 |
| Finished | Jun 29 08:24:22 PM PDT 24 |
| Peak memory | 620348 kb |
| Host | smart-62e80694-1dd0-4b02-8c4b-5bb395d65c98 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStProd +create_jtag_riscv_map=1 +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:test_in_rom :new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4087808863 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_tap_straps_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_tap_straps_prod.4087808863 |
| Directory | /workspace/1.chip_tap_straps_prod/latest |
| Test location | /workspace/coverage/default/1.chip_tap_straps_rma.784532627 |
| Short name | T66 |
| Test name | |
| Test status | |
| Simulation time | 6271567494 ps |
| CPU time | 590.84 seconds |
| Started | Jun 29 07:50:07 PM PDT 24 |
| Finished | Jun 29 07:59:59 PM PDT 24 |
| Peak memory | 620304 kb |
| Host | smart-b82203e0-f7e7-4490-8a81-6b3c8f2a01c7 |
| User | root |
| Command | /workspace/default/simv +create_jtag_riscv_map=1 +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:test_in_rom:new_rules +cdc_instrumentation _enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=784532627 -ass ert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_tap_straps_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co verage/default.vdb -cm_log /dev/null -cm_name 1.chip_tap_straps_rma.784532627 |
| Directory | /workspace/1.chip_tap_straps_rma/latest |
| Test location | /workspace/coverage/default/1.rom_e2e_asm_init_dev.509060595 |
| Short name | T884 |
| Test name | |
| Test status | |
| Simulation time | 15921693518 ps |
| CPU time | 4435.05 seconds |
| Started | Jun 29 07:54:54 PM PDT 24 |
| Finished | Jun 29 09:08:50 PM PDT 24 |
| Peak memory | 608220 kb |
| Host | smart-4cb70671-6183-45f0-88b5-fc37b8e7dd28 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeCustom +sw_test_timeout_ns=20000000 +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_prod _key_0:1:ot_flash_binary,otp_img_e2e_bootstrap_entry_dev:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=509060595 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SE Q=chip_sw_rom_e2e_asm_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1 .rom_e2e_asm_init_dev.509060595 |
| Directory | /workspace/1.rom_e2e_asm_init_dev/latest |
| Test location | /workspace/coverage/default/1.rom_e2e_asm_init_prod.2733922767 |
| Short name | T997 |
| Test name | |
| Test status | |
| Simulation time | 16060558034 ps |
| CPU time | 4326.81 seconds |
| Started | Jun 29 07:56:16 PM PDT 24 |
| Finished | Jun 29 09:08:24 PM PDT 24 |
| Peak memory | 607196 kb |
| Host | smart-31dcbf33-0593-45c2-990c-92f62ab25f1b |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeCustom +sw_test_timeout_ns=20000000 +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_prod _key_0:1:ot_flash_binary,otp_img_e2e_bootstrap_entry_prod:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2733922767 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_ SEQ=chip_sw_rom_e2e_asm_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_e2e_asm_init_prod.2733922767 |
| Directory | /workspace/1.rom_e2e_asm_init_prod/latest |
| Test location | /workspace/coverage/default/1.rom_e2e_asm_init_prod_end.1603894369 |
| Short name | T843 |
| Test name | |
| Test status | |
| Simulation time | 15573618116 ps |
| CPU time | 4219.75 seconds |
| Started | Jun 29 07:56:53 PM PDT 24 |
| Finished | Jun 29 09:07:14 PM PDT 24 |
| Peak memory | 607088 kb |
| Host | smart-96ecedaa-2f8a-416b-9eda-723feac06027 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeCustom +sw_test_timeout_ns=20000000 +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_prod _key_0:1:ot_flash_binary,otp_img_e2e_bootstrap_entry_prod_end:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1603894369 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_T EST_SEQ=chip_sw_rom_e2e_asm_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 1.rom_e2e_asm_init_prod_end.1603894369 |
| Directory | /workspace/1.rom_e2e_asm_init_prod_end/latest |
| Test location | /workspace/coverage/default/1.rom_e2e_asm_init_rma.2344972506 |
| Short name | T1175 |
| Test name | |
| Test status | |
| Simulation time | 14983070161 ps |
| CPU time | 3870.54 seconds |
| Started | Jun 29 07:57:14 PM PDT 24 |
| Finished | Jun 29 09:01:45 PM PDT 24 |
| Peak memory | 607192 kb |
| Host | smart-7d59a7e4-18a3-4a36-a8ba-bd049161e17e |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeCustom +sw_test_timeout_ns=20000000 +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_prod _key_0:1:ot_flash_binary,otp_img_e2e_bootstrap_entry_rma:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2344972506 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_S EQ=chip_sw_rom_e2e_asm_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_e2e_asm_init_rma.2344972506 |
| Directory | /workspace/1.rom_e2e_asm_init_rma/latest |
| Test location | /workspace/coverage/default/1.rom_e2e_asm_init_test_unlocked0.3537381685 |
| Short name | T1153 |
| Test name | |
| Test status | |
| Simulation time | 11516141012 ps |
| CPU time | 3333.89 seconds |
| Started | Jun 29 07:57:21 PM PDT 24 |
| Finished | Jun 29 08:52:56 PM PDT 24 |
| Peak memory | 607408 kb |
| Host | smart-4d3ff91c-f54b-49af-8b92-f82256c8287d |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeCustom +sw_test_timeout_ns=410_000_000 +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_p rod_key_0:1:ot_flash_binary,otp_img_e2e_bootstrap_entry_test_unlocked0:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY =UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3537381685 -assert nopostproc +UVM_TESTNAME=chip_base_te st +UVM_TEST_SEQ=chip_sw_rom_e2e_asm_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/ null -cm_name 1.rom_e2e_asm_init_test_unlocked0.3537381685 |
| Directory | /workspace/1.rom_e2e_asm_init_test_unlocked0/latest |
| Test location | /workspace/coverage/default/1.rom_e2e_keymgr_init_rom_ext_invalid_meas.2126394832 |
| Short name | T947 |
| Test name | |
| Test status | |
| Simulation time | 14876919100 ps |
| CPU time | 3423.33 seconds |
| Started | Jun 29 08:03:55 PM PDT 24 |
| Finished | Jun 29 09:00:59 PM PDT 24 |
| Peak memory | 608112 kb |
| Host | smart-4c6f5ba9-a47d-48b0-afaa-5129bc3da48f |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=40_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=rom_e2e_keymgr_init_otp_invalid _meas:1:new_rules,otp_img_keymgr_otp_invalid_meas:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2126394832 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip _sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_e2e_keymgr_in it_rom_ext_invalid_meas.2126394832 |
| Directory | /workspace/1.rom_e2e_keymgr_init_rom_ext_invalid_meas/latest |
| Test location | /workspace/coverage/default/1.rom_e2e_keymgr_init_rom_ext_meas.487698754 |
| Short name | T839 |
| Test name | |
| Test status | |
| Simulation time | 15114171732 ps |
| CPU time | 3788.57 seconds |
| Started | Jun 29 07:55:48 PM PDT 24 |
| Finished | Jun 29 08:58:57 PM PDT 24 |
| Peak memory | 607220 kb |
| Host | smart-98a8c2a9-3ce5-42c6-8e62-ea202137802a |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=40_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=rom_e2e_keymgr_init_otp_meas:1: new_rules,otp_img_keymgr_otp_meas:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=487698754 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_e2e_keymgr_init_rom_ext_meas.487698754 |
| Directory | /workspace/1.rom_e2e_keymgr_init_rom_ext_meas/latest |
| Test location | /workspace/coverage/default/1.rom_e2e_keymgr_init_rom_ext_no_meas.2875590101 |
| Short name | T872 |
| Test name | |
| Test status | |
| Simulation time | 14817763336 ps |
| CPU time | 3561.11 seconds |
| Started | Jun 29 07:56:50 PM PDT 24 |
| Finished | Jun 29 08:56:12 PM PDT 24 |
| Peak memory | 607332 kb |
| Host | smart-ae8fced7-9c75-4829-a8d5-b197d8f83318 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=40_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=rom_e2e_keymgr_init_otp_no_meas :1:new_rules,otp_img_keymgr_otp_no_meas:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2875590101 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_e2e_keymgr_init_rom_ext _no_meas.2875590101 |
| Directory | /workspace/1.rom_e2e_keymgr_init_rom_ext_no_meas/latest |
| Test location | /workspace/coverage/default/1.rom_e2e_shutdown_exception_c.3680795433 |
| Short name | T1285 |
| Test name | |
| Test status | |
| Simulation time | 14732911654 ps |
| CPU time | 3681.45 seconds |
| Started | Jun 29 07:56:19 PM PDT 24 |
| Finished | Jun 29 08:57:41 PM PDT 24 |
| Peak memory | 607156 kb |
| Host | smart-db985e6e-973a-4063-bb2c-2ed74db81bc8 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=40000000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=rom_e2e_shutdown_exception_c:1:ne w_rules,otp_img_secret2_locked_rma:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3680795433 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_e2e_shu tdown_exception_c_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_e2e_ shutdown_exception_c.3680795433 |
| Directory | /workspace/1.rom_e2e_shutdown_exception_c/latest |
| Test location | /workspace/coverage/default/1.rom_e2e_shutdown_output.482899183 |
| Short name | T50 |
| Test name | |
| Test status | |
| Simulation time | 28107666797 ps |
| CPU time | 4168.32 seconds |
| Started | Jun 29 08:01:18 PM PDT 24 |
| Finished | Jun 29 09:10:47 PM PDT 24 |
| Peak memory | 609020 kb |
| Host | smart-4c86ee2c-2210-42b6-9bc2-1eeb11f94aae |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=20000000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_unsigned:1:ot_f lash_binary,otp_img_shutdown_output_test_unlocked0:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=482899183 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip _sw_rom_e2e_shutdown_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_e2e_shutdown_output.482899183 |
| Directory | /workspace/1.rom_e2e_shutdown_output/latest |
| Test location | /workspace/coverage/default/1.rom_e2e_smoke.3924517 |
| Short name | T1055 |
| Test name | |
| Test status | |
| Simulation time | 15416426660 ps |
| CPU time | 3863.53 seconds |
| Started | Jun 29 08:03:39 PM PDT 24 |
| Finished | Jun 29 09:08:04 PM PDT 24 |
| Peak memory | 608264 kb |
| Host | smart-f6baabe0-8d25-4eb0-90a6-c98366bb6262 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=40000000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=rom_e2e_smoke:1:new_rules,otp_img _secret2_locked_rma:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_to p/hw/dv/tools/sim.tcl +ntb_random_seed=3924517 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_e2e_smoke.3924517 |
| Directory | /workspace/1.rom_e2e_smoke/latest |
| Test location | /workspace/coverage/default/1.rom_e2e_static_critical.1002854269 |
| Short name | T1128 |
| Test name | |
| Test status | |
| Simulation time | 16706303672 ps |
| CPU time | 4569.41 seconds |
| Started | Jun 29 07:55:30 PM PDT 24 |
| Finished | Jun 29 09:11:41 PM PDT 24 |
| Peak memory | 608128 kb |
| Host | smart-82b567c2-0045-43ee-8372-f4f50ec4f597 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=40000000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=rom_e2e_static_critical:1:new_rul es,otp_img_secret2_locked_rma:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1002854269 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_e2e_static_critical.1002854269 |
| Directory | /workspace/1.rom_e2e_static_critical/latest |
| Test location | /workspace/coverage/default/1.rom_keymgr_functest.2087480796 |
| Short name | T849 |
| Test name | |
| Test status | |
| Simulation time | 4451372170 ps |
| CPU time | 721.24 seconds |
| Started | Jun 29 07:51:46 PM PDT 24 |
| Finished | Jun 29 08:03:47 PM PDT 24 |
| Peak memory | 609184 kb |
| Host | smart-71cca1c8-94c5-4f5b-b4c1-05fd1d67e92c |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=10_000_000 +sw_build_device=sim_dv +sw_images=keymgr_functest:1:new_rules,test_rom:0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2087480796 -ass ert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 1.rom_keymgr_functest.2087480796 |
| Directory | /workspace/1.rom_keymgr_functest/latest |
| Test location | /workspace/coverage/default/1.rom_volatile_raw_unlock.2664905692 |
| Short name | T648 |
| Test name | |
| Test status | |
| Simulation time | 2491001794 ps |
| CPU time | 114.73 seconds |
| Started | Jun 29 07:59:41 PM PDT 24 |
| Finished | Jun 29 08:01:36 PM PDT 24 |
| Peak memory | 614420 kb |
| Host | smart-49193c7d-227d-48fa-8cf4-3df8859be85f |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=200_000_000 +use_otp_image=OtpTypeLcStRaw +chip_clock_source=ChipClockSourceExternal48Mhz +rom_prod_mode=1 +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_test_key_0:1:ot_flash_binary,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2664905692 -assert nopostproc +UVM_ TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_volatile_raw_unlock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag e/default.vdb -cm_log /dev/null -cm_name 1.rom_volatile_raw_unlock.2664905692 |
| Directory | /workspace/1.rom_volatile_raw_unlock/latest |
| Test location | /workspace/coverage/default/10.chip_sw_alert_handler_lpg_sleep_mode_alerts.3489676181 |
| Short name | T283 |
| Test name | |
| Test status | |
| Simulation time | 3724487800 ps |
| CPU time | 554.02 seconds |
| Started | Jun 29 08:07:09 PM PDT 24 |
| Finished | Jun 29 08:16:23 PM PDT 24 |
| Peak memory | 647224 kb |
| Host | smart-1f83333d-cd2a-40cb-9176-e8631c9a0c10 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3489676181 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.chip_ sw_alert_handler_lpg_sleep_mode_alerts.3489676181 |
| Directory | /workspace/10.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/10.chip_sw_lc_ctrl_transition.528608975 |
| Short name | T397 |
| Test name | |
| Test status | |
| Simulation time | 9685602208 ps |
| CPU time | 815.67 seconds |
| Started | Jun 29 08:06:16 PM PDT 24 |
| Finished | Jun 29 08:19:52 PM PDT 24 |
| Peak memory | 621152 kb |
| Host | smart-5b94fe58-41bf-4e5a-be08-8ae136f3b0d0 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=lc_ctrl_transition_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=528608975 -assert nopostproc +UVM_TEST NAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_transition_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul t.vdb -cm_log /dev/null -cm_name 10.chip_sw_lc_ctrl_transition.528608975 |
| Directory | /workspace/10.chip_sw_lc_ctrl_transition/latest |
| Test location | /workspace/coverage/default/10.chip_sw_uart_rand_baudrate.1665863509 |
| Short name | T1006 |
| Test name | |
| Test status | |
| Simulation time | 8006283880 ps |
| CPU time | 1532.15 seconds |
| Started | Jun 29 08:07:06 PM PDT 24 |
| Finished | Jun 29 08:32:39 PM PDT 24 |
| Peak memory | 618556 kb |
| Host | smart-ce2f28cf-b97f-406b-92c7-cc25c6ccf569 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=1665863509 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.chip_sw_uart_rand_baudrate.1665863509 |
| Directory | /workspace/10.chip_sw_uart_rand_baudrate/latest |
| Test location | /workspace/coverage/default/11.chip_sw_lc_ctrl_transition.3155273883 |
| Short name | T1048 |
| Test name | |
| Test status | |
| Simulation time | 7017260564 ps |
| CPU time | 482.36 seconds |
| Started | Jun 29 08:06:00 PM PDT 24 |
| Finished | Jun 29 08:14:03 PM PDT 24 |
| Peak memory | 618972 kb |
| Host | smart-b04e100b-57fd-4844-a418-5f9c1f6a563d |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=lc_ctrl_transition_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3155273883 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_transition_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau lt.vdb -cm_log /dev/null -cm_name 11.chip_sw_lc_ctrl_transition.3155273883 |
| Directory | /workspace/11.chip_sw_lc_ctrl_transition/latest |
| Test location | /workspace/coverage/default/11.chip_sw_uart_rand_baudrate.2060084946 |
| Short name | T101 |
| Test name | |
| Test status | |
| Simulation time | 13141507384 ps |
| CPU time | 3280.12 seconds |
| Started | Jun 29 08:07:27 PM PDT 24 |
| Finished | Jun 29 09:02:08 PM PDT 24 |
| Peak memory | 618596 kb |
| Host | smart-20707f7a-9851-4f68-ad71-ff0e64686f27 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=2060084946 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.chip_sw_uart_rand_baudrate.2060084946 |
| Directory | /workspace/11.chip_sw_uart_rand_baudrate/latest |
| Test location | /workspace/coverage/default/12.chip_sw_lc_ctrl_transition.164716326 |
| Short name | T1027 |
| Test name | |
| Test status | |
| Simulation time | 7246101072 ps |
| CPU time | 431.41 seconds |
| Started | Jun 29 08:06:54 PM PDT 24 |
| Finished | Jun 29 08:14:06 PM PDT 24 |
| Peak memory | 619180 kb |
| Host | smart-6a6f0b1e-51a4-4287-b604-9623f16e6a8d |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=lc_ctrl_transition_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=164716326 -assert nopostproc +UVM_TEST NAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_transition_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul t.vdb -cm_log /dev/null -cm_name 12.chip_sw_lc_ctrl_transition.164716326 |
| Directory | /workspace/12.chip_sw_lc_ctrl_transition/latest |
| Test location | /workspace/coverage/default/12.chip_sw_uart_rand_baudrate.1916890879 |
| Short name | T1237 |
| Test name | |
| Test status | |
| Simulation time | 7581137202 ps |
| CPU time | 1433.63 seconds |
| Started | Jun 29 08:06:21 PM PDT 24 |
| Finished | Jun 29 08:30:15 PM PDT 24 |
| Peak memory | 618596 kb |
| Host | smart-05ad4a93-4128-45de-b404-74f95fd4d233 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=1916890879 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.chip_sw_uart_rand_baudrate.1916890879 |
| Directory | /workspace/12.chip_sw_uart_rand_baudrate/latest |
| Test location | /workspace/coverage/default/13.chip_sw_lc_ctrl_transition.1455847654 |
| Short name | T243 |
| Test name | |
| Test status | |
| Simulation time | 11664686458 ps |
| CPU time | 1058.24 seconds |
| Started | Jun 29 08:06:41 PM PDT 24 |
| Finished | Jun 29 08:24:20 PM PDT 24 |
| Peak memory | 621504 kb |
| Host | smart-a60a15af-31db-4549-9b6a-ea486db994e9 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=lc_ctrl_transition_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1455847654 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_transition_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau lt.vdb -cm_log /dev/null -cm_name 13.chip_sw_lc_ctrl_transition.1455847654 |
| Directory | /workspace/13.chip_sw_lc_ctrl_transition/latest |
| Test location | /workspace/coverage/default/13.chip_sw_uart_rand_baudrate.4088726439 |
| Short name | T1010 |
| Test name | |
| Test status | |
| Simulation time | 3653427500 ps |
| CPU time | 705.02 seconds |
| Started | Jun 29 08:08:11 PM PDT 24 |
| Finished | Jun 29 08:19:57 PM PDT 24 |
| Peak memory | 620652 kb |
| Host | smart-99ab25f7-0627-47af-bd1a-ac97b2c3f752 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=4088726439 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.chip_sw_uart_rand_baudrate.4088726439 |
| Directory | /workspace/13.chip_sw_uart_rand_baudrate/latest |
| Test location | /workspace/coverage/default/14.chip_sw_lc_ctrl_transition.1232836959 |
| Short name | T402 |
| Test name | |
| Test status | |
| Simulation time | 9932056520 ps |
| CPU time | 985.64 seconds |
| Started | Jun 29 08:06:07 PM PDT 24 |
| Finished | Jun 29 08:22:34 PM PDT 24 |
| Peak memory | 621004 kb |
| Host | smart-bd19d016-d18e-412c-8653-1a3671285348 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=lc_ctrl_transition_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1232836959 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_transition_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau lt.vdb -cm_log /dev/null -cm_name 14.chip_sw_lc_ctrl_transition.1232836959 |
| Directory | /workspace/14.chip_sw_lc_ctrl_transition/latest |
| Test location | /workspace/coverage/default/14.chip_sw_uart_rand_baudrate.2041373995 |
| Short name | T307 |
| Test name | |
| Test status | |
| Simulation time | 3668639182 ps |
| CPU time | 532.18 seconds |
| Started | Jun 29 08:06:52 PM PDT 24 |
| Finished | Jun 29 08:15:45 PM PDT 24 |
| Peak memory | 618612 kb |
| Host | smart-4d2a5636-450c-4126-b023-c04a3f0d4cda |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=2041373995 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.chip_sw_uart_rand_baudrate.2041373995 |
| Directory | /workspace/14.chip_sw_uart_rand_baudrate/latest |
| Test location | /workspace/coverage/default/15.chip_sw_uart_rand_baudrate.2809965568 |
| Short name | T303 |
| Test name | |
| Test status | |
| Simulation time | 8486270808 ps |
| CPU time | 1592.42 seconds |
| Started | Jun 29 08:07:04 PM PDT 24 |
| Finished | Jun 29 08:33:38 PM PDT 24 |
| Peak memory | 618596 kb |
| Host | smart-b531a5af-1d73-49e1-869c-794d9565b2b9 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=2809965568 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.chip_sw_uart_rand_baudrate.2809965568 |
| Directory | /workspace/15.chip_sw_uart_rand_baudrate/latest |
| Test location | /workspace/coverage/default/16.chip_sw_alert_handler_lpg_sleep_mode_alerts.591239100 |
| Short name | T853 |
| Test name | |
| Test status | |
| Simulation time | 3932368280 ps |
| CPU time | 426.9 seconds |
| Started | Jun 29 08:06:59 PM PDT 24 |
| Finished | Jun 29 08:14:06 PM PDT 24 |
| Peak memory | 615176 kb |
| Host | smart-86228933-773a-4ccc-93db-88516b8b1472 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=591239100 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all _escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.chip_s w_alert_handler_lpg_sleep_mode_alerts.591239100 |
| Directory | /workspace/16.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/16.chip_sw_uart_rand_baudrate.2106498715 |
| Short name | T98 |
| Test name | |
| Test status | |
| Simulation time | 9374869458 ps |
| CPU time | 1596.47 seconds |
| Started | Jun 29 08:07:15 PM PDT 24 |
| Finished | Jun 29 08:33:52 PM PDT 24 |
| Peak memory | 618888 kb |
| Host | smart-b30ba405-93ac-4712-8ffe-e73a2851f614 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=2106498715 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.chip_sw_uart_rand_baudrate.2106498715 |
| Directory | /workspace/16.chip_sw_uart_rand_baudrate/latest |
| Test location | /workspace/coverage/default/17.chip_sw_uart_rand_baudrate.305333318 |
| Short name | T408 |
| Test name | |
| Test status | |
| Simulation time | 13557525800 ps |
| CPU time | 2765.2 seconds |
| Started | Jun 29 08:07:44 PM PDT 24 |
| Finished | Jun 29 08:53:50 PM PDT 24 |
| Peak memory | 618600 kb |
| Host | smart-06393d63-ef06-4f7d-84bd-b42819594f4e |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=305333318 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.chip_sw_uart_rand_baudrate.305333318 |
| Directory | /workspace/17.chip_sw_uart_rand_baudrate/latest |
| Test location | /workspace/coverage/default/18.chip_sw_all_escalation_resets.3245714910 |
| Short name | T240 |
| Test name | |
| Test status | |
| Simulation time | 3850748300 ps |
| CPU time | 609.89 seconds |
| Started | Jun 29 08:07:19 PM PDT 24 |
| Finished | Jun 29 08:17:30 PM PDT 24 |
| Peak memory | 647876 kb |
| Host | smart-53c9f110-10db-49ce-885a-445c820bb444 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 3245714910 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.chip_sw_all_escalation_resets.3245714910 |
| Directory | /workspace/18.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/18.chip_sw_uart_rand_baudrate.3077518085 |
| Short name | T1135 |
| Test name | |
| Test status | |
| Simulation time | 13039911424 ps |
| CPU time | 2986.28 seconds |
| Started | Jun 29 08:08:09 PM PDT 24 |
| Finished | Jun 29 08:57:57 PM PDT 24 |
| Peak memory | 618576 kb |
| Host | smart-978dd9a6-4d16-45db-9836-b4639075e028 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=3077518085 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.chip_sw_uart_rand_baudrate.3077518085 |
| Directory | /workspace/18.chip_sw_uart_rand_baudrate/latest |
| Test location | /workspace/coverage/default/19.chip_sw_alert_handler_lpg_sleep_mode_alerts.4287576839 |
| Short name | T1196 |
| Test name | |
| Test status | |
| Simulation time | 4217523160 ps |
| CPU time | 543.59 seconds |
| Started | Jun 29 08:08:42 PM PDT 24 |
| Finished | Jun 29 08:17:47 PM PDT 24 |
| Peak memory | 642160 kb |
| Host | smart-f1aa3ee1-9f2a-44e7-be58-e6e94612479d |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4287576839 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.chip_ sw_alert_handler_lpg_sleep_mode_alerts.4287576839 |
| Directory | /workspace/19.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/19.chip_sw_all_escalation_resets.1592370238 |
| Short name | T416 |
| Test name | |
| Test status | |
| Simulation time | 4701719412 ps |
| CPU time | 769.99 seconds |
| Started | Jun 29 08:09:42 PM PDT 24 |
| Finished | Jun 29 08:22:33 PM PDT 24 |
| Peak memory | 647952 kb |
| Host | smart-922558cc-dd8e-4c27-bad5-40f875ae2be2 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 1592370238 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.chip_sw_all_escalation_resets.1592370238 |
| Directory | /workspace/19.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/19.chip_sw_uart_rand_baudrate.867225084 |
| Short name | T302 |
| Test name | |
| Test status | |
| Simulation time | 13034199940 ps |
| CPU time | 2620.53 seconds |
| Started | Jun 29 08:09:14 PM PDT 24 |
| Finished | Jun 29 08:52:56 PM PDT 24 |
| Peak memory | 618316 kb |
| Host | smart-72797c1b-efde-4a73-8a0c-ad30a1ea6c11 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=867225084 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.chip_sw_uart_rand_baudrate.867225084 |
| Directory | /workspace/19.chip_sw_uart_rand_baudrate/latest |
| Test location | /workspace/coverage/default/2.chip_jtag_mem_access.545579291 |
| Short name | T152 |
| Test name | |
| Test status | |
| Simulation time | 13200190754 ps |
| CPU time | 1360.85 seconds |
| Started | Jun 29 07:52:39 PM PDT 24 |
| Finished | Jun 29 08:15:20 PM PDT 24 |
| Peak memory | 605296 kb |
| Host | smart-3e4b1840-6c8a-4135-9137-ea5c894b7534 |
| User | root |
| Command | /workspace/default/simv +create_jtag_riscv_map=1 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=545579291 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_jtag_m em_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_jtag_mem_access.545579291 |
| Directory | /workspace/2.chip_jtag_mem_access/latest |
| Test location | /workspace/coverage/default/2.chip_rv_dm_ndm_reset_req.114954136 |
| Short name | T387 |
| Test name | |
| Test status | |
| Simulation time | 4132242904 ps |
| CPU time | 571.17 seconds |
| Started | Jun 29 07:59:51 PM PDT 24 |
| Finished | Jun 29 08:09:23 PM PDT 24 |
| Peak memory | 617764 kb |
| Host | smart-bc40a2a8-f88c-49f9-814c-4a7f4195dcf1 |
| User | root |
| Command | /workspace/default/simv +en_scb_tl_err_chk=0 +use_jtag_dmi=1 +sw_build_device=sim_dv +sw_images=rv_dm_ndm_reset_req_rma:1:new_rules,test_rom:0 +cdc_in strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1 14954136 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_rv_dm_ndm_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_rv_dm_ndm_reset_req.114954136 |
| Directory | /workspace/2.chip_rv_dm_ndm_reset_req/latest |
| Test location | /workspace/coverage/default/2.chip_sival_flash_info_access.3674950995 |
| Short name | T316 |
| Test name | |
| Test status | |
| Simulation time | 3166834610 ps |
| CPU time | 315.23 seconds |
| Started | Jun 29 07:52:46 PM PDT 24 |
| Finished | Jun 29 07:58:02 PM PDT 24 |
| Peak memory | 607112 kb |
| Host | smart-7e475152-2fec-4cd8-8fdd-3f7a25ab3fd0 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStTestUnlocked0 +sw_build_device=sim_dv +sw_images=flash_ctrl_info_access_lc:1:new_rules,test_rom:0 +c dc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_s eed=3674950995 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sival_flash_info_access.3674950995 |
| Directory | /workspace/2.chip_sival_flash_info_access/latest |
| Test location | /workspace/coverage/default/2.chip_sw_adc_ctrl_sleep_debug_cable_wakeup.1765278350 |
| Short name | T106 |
| Test name | |
| Test status | |
| Simulation time | 19946486182 ps |
| CPU time | 620.39 seconds |
| Started | Jun 29 07:56:53 PM PDT 24 |
| Finished | Jun 29 08:07:14 PM PDT 24 |
| Peak memory | 617768 kb |
| Host | smart-542b9407-e6bc-4797-8cf0-cf67c3568cc2 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=adc_ctrl_sleep_debug_cable_wakeup_test:1:new_rules,test_rom: 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand om_seed=1765278350 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_adc_ctrl_sleep_debug_cable_wakeup_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_adc_ctrl_sleep_debug_cable_wakeup.1765278350 |
| Directory | /workspace/2.chip_sw_adc_ctrl_sleep_debug_cable_wakeup/latest |
| Test location | /workspace/coverage/default/2.chip_sw_aes_enc.1504509094 |
| Short name | T1167 |
| Test name | |
| Test status | |
| Simulation time | 3027139856 ps |
| CPU time | 221.62 seconds |
| Started | Jun 29 07:56:52 PM PDT 24 |
| Finished | Jun 29 08:00:34 PM PDT 24 |
| Peak memory | 609140 kb |
| Host | smart-1fe9d1d4-f730-4d32-855f-d1c7fe9312bc |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=22_000_000 +sw_build_device=sim_dv +sw_images=aes_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1504509094 -asser t nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag e/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_aes_enc.1504509094 |
| Directory | /workspace/2.chip_sw_aes_enc/latest |
| Test location | /workspace/coverage/default/2.chip_sw_aes_enc_jitter_en.1968397361 |
| Short name | T1191 |
| Test name | |
| Test status | |
| Simulation time | 2620224667 ps |
| CPU time | 268.96 seconds |
| Started | Jun 29 07:57:36 PM PDT 24 |
| Finished | Jun 29 08:02:06 PM PDT 24 |
| Peak memory | 609200 kb |
| Host | smart-8987c273-89c1-4f0e-bd7b-74bdbe458252 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=26_000_000 +en_jitter=1 +sw_build_device=sim_dv +sw_images=aes_smoketest:1:new_rules,test_rom:0 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1968 397361 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work space/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_aes_enc_jitter_en.1968397361 |
| Directory | /workspace/2.chip_sw_aes_enc_jitter_en/latest |
| Test location | /workspace/coverage/default/2.chip_sw_aes_enc_jitter_en_reduced_freq.1936895463 |
| Short name | T1154 |
| Test name | |
| Test status | |
| Simulation time | 2742125174 ps |
| CPU time | 240.07 seconds |
| Started | Jun 29 08:00:59 PM PDT 24 |
| Finished | Jun 29 08:04:59 PM PDT 24 |
| Peak memory | 609152 kb |
| Host | smart-64dfa5b0-807e-49a5-ab25-da81f5fc180e |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=26_000_000 +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=aes_smoketest:1:new_rules, test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1936895463 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_aes_enc_jitter_en_reduced_freq.1936895463 |
| Directory | /workspace/2.chip_sw_aes_enc_jitter_en_reduced_freq/latest |
| Test location | /workspace/coverage/default/2.chip_sw_aes_entropy.3190252507 |
| Short name | T1271 |
| Test name | |
| Test status | |
| Simulation time | 2917879050 ps |
| CPU time | 304.8 seconds |
| Started | Jun 29 07:56:57 PM PDT 24 |
| Finished | Jun 29 08:02:02 PM PDT 24 |
| Peak memory | 609180 kb |
| Host | smart-56d7a350-d049-48da-8b86-fe195c72510c |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=15_000_000 +sw_build_device=sim_dv +sw_images=aes_entropy_test:1:new_rules,test_rom:0 +cdc_instrumentation _enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3190252507 -as sert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove rage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_aes_entropy.3190252507 |
| Directory | /workspace/2.chip_sw_aes_entropy/latest |
| Test location | /workspace/coverage/default/2.chip_sw_aes_idle.1456699870 |
| Short name | T1193 |
| Test name | |
| Test status | |
| Simulation time | 3195809164 ps |
| CPU time | 219.17 seconds |
| Started | Jun 29 07:58:13 PM PDT 24 |
| Finished | Jun 29 08:01:55 PM PDT 24 |
| Peak memory | 609180 kb |
| Host | smart-54550020-6141-4bac-8905-ec0169343586 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=25_000_000 +sw_build_device=sim_dv +sw_images=aes_idle_test:1:new_rules,test_rom:0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1456699870 -asser t nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag e/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_aes_idle.1456699870 |
| Directory | /workspace/2.chip_sw_aes_idle/latest |
| Test location | /workspace/coverage/default/2.chip_sw_aes_masking_off.1668856292 |
| Short name | T1076 |
| Test name | |
| Test status | |
| Simulation time | 2795361753 ps |
| CPU time | 299.71 seconds |
| Started | Jun 29 07:56:50 PM PDT 24 |
| Finished | Jun 29 08:01:50 PM PDT 24 |
| Peak memory | 609240 kb |
| Host | smart-714b0fd9-4773-4296-b7fc-b95f1c043541 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=aes_masking_off_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1668856292 -assert nopostproc +UVM_TESTNA ME=chip_base_test +UVM_TEST_SEQ=chip_sw_aes_masking_off_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_aes_masking_off.1668856292 |
| Directory | /workspace/2.chip_sw_aes_masking_off/latest |
| Test location | /workspace/coverage/default/2.chip_sw_aes_smoketest.4244707111 |
| Short name | T833 |
| Test name | |
| Test status | |
| Simulation time | 3172959780 ps |
| CPU time | 271.53 seconds |
| Started | Jun 29 08:08:54 PM PDT 24 |
| Finished | Jun 29 08:13:27 PM PDT 24 |
| Peak memory | 607140 kb |
| Host | smart-91eff80f-268a-484f-8695-e139f2b073b3 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=aes_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4244707111 -assert nopostproc +UVM_TESTNAME=chip _base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_aes_smoketest.4244707111 |
| Directory | /workspace/2.chip_sw_aes_smoketest/latest |
| Test location | /workspace/coverage/default/2.chip_sw_alert_handler_entropy.2665254496 |
| Short name | T78 |
| Test name | |
| Test status | |
| Simulation time | 3462064124 ps |
| CPU time | 295.4 seconds |
| Started | Jun 29 07:58:02 PM PDT 24 |
| Finished | Jun 29 08:02:58 PM PDT 24 |
| Peak memory | 607488 kb |
| Host | smart-ff85fb6e-5edd-4dc8-9a53-b2b074758203 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=alert_handler_entropy_test:1:new_rules,test_ro m:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=2665254496 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_alert_handler_entropy.2665254496 |
| Directory | /workspace/2.chip_sw_alert_handler_entropy/latest |
| Test location | /workspace/coverage/default/2.chip_sw_alert_handler_escalation.310904747 |
| Short name | T202 |
| Test name | |
| Test status | |
| Simulation time | 5559059776 ps |
| CPU time | 521.67 seconds |
| Started | Jun 29 07:57:08 PM PDT 24 |
| Finished | Jun 29 08:05:50 PM PDT 24 |
| Peak memory | 617316 kb |
| Host | smart-8ba65a2d-aea7-48e2-8eac-9b506cf5e5e4 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=alert_handler_escalation_test:1:new_rules,test _rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb _random_seed=310904747 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_alert_handler_escalation_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_alert_handler_escalation.310904747 |
| Directory | /workspace/2.chip_sw_alert_handler_escalation/latest |
| Test location | /workspace/coverage/default/2.chip_sw_alert_handler_lpg_clkoff.2278513636 |
| Short name | T445 |
| Test name | |
| Test status | |
| Simulation time | 8227991522 ps |
| CPU time | 2058.07 seconds |
| Started | Jun 29 07:59:03 PM PDT 24 |
| Finished | Jun 29 08:33:22 PM PDT 24 |
| Peak memory | 607904 kb |
| Host | smart-efedd12a-70fa-4c2d-a8d0-b5fd30a45b71 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +sw_build_device=sim_dv +sw_images=alert_handler_lpg_clkoff_test:1:new_rules,test_r om:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r andom_seed=2278513636 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_alert_handler_lpg_clkoff_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_alert_handler_lpg_clkoff.2278513636 |
| Directory | /workspace/2.chip_sw_alert_handler_lpg_clkoff/latest |
| Test location | /workspace/coverage/default/2.chip_sw_alert_handler_lpg_reset_toggle.310943909 |
| Short name | T1200 |
| Test name | |
| Test status | |
| Simulation time | 7539368508 ps |
| CPU time | 1763.35 seconds |
| Started | Jun 29 07:59:51 PM PDT 24 |
| Finished | Jun 29 08:29:15 PM PDT 24 |
| Peak memory | 608228 kb |
| Host | smart-bd2d00b2-a62b-4210-8c60-36a30f6ea6ba |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +sw_build_device=sim_dv +sw_images=alert_handler_lpg_reset_toggle_test:1:new_rules, test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=310943909 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_alert_handler_shorten_ping_wait_cycle_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_alert_handler_lpg_reset_toggle.310943909 |
| Directory | /workspace/2.chip_sw_alert_handler_lpg_reset_toggle/latest |
| Test location | /workspace/coverage/default/2.chip_sw_alert_handler_ping_ok.2185884033 |
| Short name | T1189 |
| Test name | |
| Test status | |
| Simulation time | 8559130744 ps |
| CPU time | 1564.84 seconds |
| Started | Jun 29 07:58:04 PM PDT 24 |
| Finished | Jun 29 08:24:10 PM PDT 24 |
| Peak memory | 608224 kb |
| Host | smart-d71dcdb5-c383-4cde-a0b6-a3e545f51de3 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=24000000 +sw_build_device=sim_dv +sw_images=alert_handler_ping_ok_test:1:new_rules,test_rom:0 +c dc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_s eed=2185884033 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_alert_handler_ping_ok.2185884033 |
| Directory | /workspace/2.chip_sw_alert_handler_ping_ok/latest |
| Test location | /workspace/coverage/default/2.chip_sw_alert_handler_ping_timeout.3397516780 |
| Short name | T1239 |
| Test name | |
| Test status | |
| Simulation time | 5848310000 ps |
| CPU time | 666.14 seconds |
| Started | Jun 29 07:57:56 PM PDT 24 |
| Finished | Jun 29 08:09:03 PM PDT 24 |
| Peak memory | 608160 kb |
| Host | smart-f16131b8-1753-4b3c-8501-dc9ec8b6d797 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=24000000 +sw_build_device=sim_dv +sw_images=alert_handler_ping_timeout_test:1:new_rules,test_rom :0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=3397516780 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_alert_handler_ping_timeout.3397516780 |
| Directory | /workspace/2.chip_sw_alert_handler_ping_timeout/latest |
| Test location | /workspace/coverage/default/2.chip_sw_alert_handler_reverse_ping_in_deep_sleep.574932885 |
| Short name | T169 |
| Test name | |
| Test status | |
| Simulation time | 255853728720 ps |
| CPU time | 12338.6 seconds |
| Started | Jun 29 07:58:38 PM PDT 24 |
| Finished | Jun 29 11:24:19 PM PDT 24 |
| Peak memory | 608788 kb |
| Host | smart-76006d91-e87d-4434-a931-013b6b3ee0fb |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=300_000_000 +sw_build_device=sim_dv +sw_images=alert_handler_reverse_ping_in_deep_sleep_test:1:n ew_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=574932885 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tg l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_alert_handler_reverse_ping_in_deep_sleep.574932885 |
| Directory | /workspace/2.chip_sw_alert_handler_reverse_ping_in_deep_sleep/latest |
| Test location | /workspace/coverage/default/2.chip_sw_alert_test.3389606554 |
| Short name | T60 |
| Test name | |
| Test status | |
| Simulation time | 2863498500 ps |
| CPU time | 483.14 seconds |
| Started | Jun 29 07:57:21 PM PDT 24 |
| Finished | Jun 29 08:05:25 PM PDT 24 |
| Peak memory | 606480 kb |
| Host | smart-6ba730ae-7fa9-4ee1-a7a6-f5f92580a7b3 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=alert_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3389606554 -assert nopostproc +UVM_TESTNAME=chip_ba se_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 2.chip_sw_alert_test.3389606554 |
| Directory | /workspace/2.chip_sw_alert_test/latest |
| Test location | /workspace/coverage/default/2.chip_sw_aon_timer_irq.12325566 |
| Short name | T340 |
| Test name | |
| Test status | |
| Simulation time | 4640015750 ps |
| CPU time | 477.76 seconds |
| Started | Jun 29 07:56:52 PM PDT 24 |
| Finished | Jun 29 08:04:50 PM PDT 24 |
| Peak memory | 609168 kb |
| Host | smart-d5ea817d-957a-4d28-9ce1-586adb914b4e |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=aon_timer_irq_test:1:new_rules,test_rom:0 +cdc_instrumentati on_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12325566 -as sert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove rage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_aon_timer_irq.12325566 |
| Directory | /workspace/2.chip_sw_aon_timer_irq/latest |
| Test location | /workspace/coverage/default/2.chip_sw_aon_timer_sleep_wdog_sleep_pause.3641846475 |
| Short name | T959 |
| Test name | |
| Test status | |
| Simulation time | 6972424028 ps |
| CPU time | 445.76 seconds |
| Started | Jun 29 07:56:51 PM PDT 24 |
| Finished | Jun 29 08:04:17 PM PDT 24 |
| Peak memory | 609244 kb |
| Host | smart-d4969646-cd0d-4c1a-bf34-8377be2f5ee5 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=aon_timer_sleep_wdog_sleep_pause_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=3641846475 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_aon_timer_sleep_wdog_sleep_pause.3641846475 |
| Directory | /workspace/2.chip_sw_aon_timer_sleep_wdog_sleep_pause/latest |
| Test location | /workspace/coverage/default/2.chip_sw_aon_timer_smoketest.2865976739 |
| Short name | T1084 |
| Test name | |
| Test status | |
| Simulation time | 2901746304 ps |
| CPU time | 311.53 seconds |
| Started | Jun 29 08:09:38 PM PDT 24 |
| Finished | Jun 29 08:14:51 PM PDT 24 |
| Peak memory | 609204 kb |
| Host | smart-f1a35806-e291-48b8-985f-036f6e30c545 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=aon_timer_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2865976739 -assert nopostproc +UVM_TESTNAM E=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 2.chip_sw_aon_timer_smoketest.2865976739 |
| Directory | /workspace/2.chip_sw_aon_timer_smoketest/latest |
| Test location | /workspace/coverage/default/2.chip_sw_aon_timer_wdog_bite_reset.3190307715 |
| Short name | T880 |
| Test name | |
| Test status | |
| Simulation time | 10326113566 ps |
| CPU time | 1041.16 seconds |
| Started | Jun 29 07:57:32 PM PDT 24 |
| Finished | Jun 29 08:14:54 PM PDT 24 |
| Peak memory | 607272 kb |
| Host | smart-c229e360-e51f-4828-b34a-16946b1ccef6 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=aon_timer_wdog_bite_reset_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 3190307715 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_aon_timer_wdog_bite_reset.3190307715 |
| Directory | /workspace/2.chip_sw_aon_timer_wdog_bite_reset/latest |
| Test location | /workspace/coverage/default/2.chip_sw_aon_timer_wdog_lc_escalate.716808311 |
| Short name | T287 |
| Test name | |
| Test status | |
| Simulation time | 5191975982 ps |
| CPU time | 651.53 seconds |
| Started | Jun 29 07:58:33 PM PDT 24 |
| Finished | Jun 29 08:09:25 PM PDT 24 |
| Peak memory | 609204 kb |
| Host | smart-9be4863c-99a7-4cbe-b1e2-d9e1b770a1d9 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=aon_timer_wdog_lc_escalate_test:1:new_rules,test_rom:0 +cdc_ instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed =716808311 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_aon_timer_wdog_lc_escalate.716808311 |
| Directory | /workspace/2.chip_sw_aon_timer_wdog_lc_escalate/latest |
| Test location | /workspace/coverage/default/2.chip_sw_ast_clk_outputs.2814335650 |
| Short name | T1282 |
| Test name | |
| Test status | |
| Simulation time | 8778359264 ps |
| CPU time | 1395.81 seconds |
| Started | Jun 29 08:00:52 PM PDT 24 |
| Finished | Jun 29 08:24:08 PM PDT 24 |
| Peak memory | 615068 kb |
| Host | smart-937173a6-91e8-443e-b851-9c6c922b7819 |
| User | root |
| Command | /workspace/default/simv +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=ast_clk_outs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled= 1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2814335650 -assert nopo stproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_ast_clk_outputs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co verage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_ast_clk_outputs.2814335650 |
| Directory | /workspace/2.chip_sw_ast_clk_outputs/latest |
| Test location | /workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_lc.1676148631 |
| Short name | T850 |
| Test name | |
| Test status | |
| Simulation time | 10900608064 ps |
| CPU time | 966.81 seconds |
| Started | Jun 29 08:00:05 PM PDT 24 |
| Finished | Jun 29 08:16:13 PM PDT 24 |
| Peak memory | 619148 kb |
| Host | smart-fd999fb6-6233-4333-bb5f-bedfdc88ea02 |
| User | root |
| Command | /workspace/default/simv +chip_clock_source=ChipClockSourceExternal48Mhz +sw_build_device=sim_dv +sw_images=clkmgr_external_clk_src_for_lc_test:1:new_r ules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim .tcl +ntb_random_seed=1676148631 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_transition_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_clkmgr_external_clk_src_for_lc.1676148631 |
| Directory | /workspace/2.chip_sw_clkmgr_external_clk_src_for_lc/latest |
| Test location | /workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_fast_rma.1858994222 |
| Short name | T99 |
| Test name | |
| Test status | |
| Simulation time | 4644899400 ps |
| CPU time | 904.1 seconds |
| Started | Jun 29 08:00:07 PM PDT 24 |
| Finished | Jun 29 08:15:12 PM PDT 24 |
| Peak memory | 608608 kb |
| Host | smart-64ce67fa-5192-4e59-9c60-f24c7195ee26 |
| User | root |
| Command | /workspace/default/simv +chip_clock_source=ChipClockSourceExternal96Mhz +calibrate_usb_clk=1 +src_dec_state=DecLcStRma +sw_build_device=sim_dv +sw_ima ges=clkmgr_external_clk_src_for_sw_fast_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1858994222 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ =chip_sw_lc_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_c lkmgr_external_clk_src_for_sw_fast_rma.1858994222 |
| Directory | /workspace/2.chip_sw_clkmgr_external_clk_src_for_sw_fast_rma/latest |
| Test location | /workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0.4204273001 |
| Short name | T1157 |
| Test name | |
| Test status | |
| Simulation time | 3811924884 ps |
| CPU time | 545.06 seconds |
| Started | Jun 29 07:59:36 PM PDT 24 |
| Finished | Jun 29 08:08:42 PM PDT 24 |
| Peak memory | 610852 kb |
| Host | smart-8057080a-8a89-44c3-81dd-564f51dcc517 |
| User | root |
| Command | /workspace/default/simv +chip_clock_source=ChipClockSourceExternal96Mhz +calibrate_usb_clk=1 +src_dec_state=DecLcStTestUnlocked0 +sw_build_device=sim_ dv +sw_images=clkmgr_external_clk_src_for_sw_fast_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4204273001 -assert nopostproc +UVM_TESTNAME=chip_base_test +UV M_TEST_SEQ=chip_sw_lc_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2 .chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0.4204273001 |
| Directory | /workspace/2.chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0/latest |
| Test location | /workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_slow_dev.2512856672 |
| Short name | T1065 |
| Test name | |
| Test status | |
| Simulation time | 4759454750 ps |
| CPU time | 781.63 seconds |
| Started | Jun 29 07:59:28 PM PDT 24 |
| Finished | Jun 29 08:12:30 PM PDT 24 |
| Peak memory | 610912 kb |
| Host | smart-b9cad20f-6892-4702-b2ed-116f9bb9e3f9 |
| User | root |
| Command | /workspace/default/simv +chip_clock_source=ChipClockSourceExternal48Mhz +calibrate_usb_clk=1 +src_dec_state=DecLcStDev +sw_build_device=sim_dv +sw_ima ges=clkmgr_external_clk_src_for_sw_slow_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2512856672 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ =chip_sw_lc_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_c lkmgr_external_clk_src_for_sw_slow_dev.2512856672 |
| Directory | /workspace/2.chip_sw_clkmgr_external_clk_src_for_sw_slow_dev/latest |
| Test location | /workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_slow_rma.192208770 |
| Short name | T1249 |
| Test name | |
| Test status | |
| Simulation time | 5075645140 ps |
| CPU time | 687.4 seconds |
| Started | Jun 29 07:59:53 PM PDT 24 |
| Finished | Jun 29 08:11:21 PM PDT 24 |
| Peak memory | 610908 kb |
| Host | smart-c9ff9c59-6258-4f8a-bb20-e196ef8444a8 |
| User | root |
| Command | /workspace/default/simv +chip_clock_source=ChipClockSourceExternal48Mhz +calibrate_usb_clk=1 +src_dec_state=DecLcStRma +sw_build_device=sim_dv +sw_ima ges=clkmgr_external_clk_src_for_sw_slow_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=192208770 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ= chip_sw_lc_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_cl kmgr_external_clk_src_for_sw_slow_rma.192208770 |
| Directory | /workspace/2.chip_sw_clkmgr_external_clk_src_for_sw_slow_rma/latest |
| Test location | /workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0.3536353555 |
| Short name | T917 |
| Test name | |
| Test status | |
| Simulation time | 4565078000 ps |
| CPU time | 701.13 seconds |
| Started | Jun 29 08:00:10 PM PDT 24 |
| Finished | Jun 29 08:11:52 PM PDT 24 |
| Peak memory | 608596 kb |
| Host | smart-7ecdafb2-418c-4b73-a90e-0c64512faf1d |
| User | root |
| Command | /workspace/default/simv +chip_clock_source=ChipClockSourceExternal48Mhz +calibrate_usb_clk=1 +src_dec_state=DecLcStTestUnlocked0 +sw_build_device=sim_ dv +sw_images=clkmgr_external_clk_src_for_sw_slow_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3536353555 -assert nopostproc +UVM_TESTNAME=chip_base_test +UV M_TEST_SEQ=chip_sw_lc_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2 .chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0.3536353555 |
| Directory | /workspace/2.chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0/latest |
| Test location | /workspace/coverage/default/2.chip_sw_clkmgr_jitter.1327577297 |
| Short name | T1111 |
| Test name | |
| Test status | |
| Simulation time | 2685636601 ps |
| CPU time | 195.66 seconds |
| Started | Jun 29 08:01:03 PM PDT 24 |
| Finished | Jun 29 08:04:19 PM PDT 24 |
| Peak memory | 607304 kb |
| Host | smart-4e2b6337-6956-4bbe-91f6-453f38d8d6e1 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_jitter_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1327577297 -assert nopostproc +UVM_TESTNAME =chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 2.chip_sw_clkmgr_jitter.1327577297 |
| Directory | /workspace/2.chip_sw_clkmgr_jitter/latest |
| Test location | /workspace/coverage/default/2.chip_sw_clkmgr_jitter_frequency.3397619346 |
| Short name | T1209 |
| Test name | |
| Test status | |
| Simulation time | 3796271800 ps |
| CPU time | 501.32 seconds |
| Started | Jun 29 08:00:50 PM PDT 24 |
| Finished | Jun 29 08:09:11 PM PDT 24 |
| Peak memory | 609196 kb |
| Host | smart-b1e7edc0-9066-4976-b3fe-419b821c837a |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_jitter_frequency_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3397619346 -assert nopostproc +UV M_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -c m_log /dev/null -cm_name 2.chip_sw_clkmgr_jitter_frequency.3397619346 |
| Directory | /workspace/2.chip_sw_clkmgr_jitter_frequency/latest |
| Test location | /workspace/coverage/default/2.chip_sw_clkmgr_jitter_reduced_freq.476390569 |
| Short name | T1206 |
| Test name | |
| Test status | |
| Simulation time | 2430474594 ps |
| CPU time | 164.78 seconds |
| Started | Jun 29 08:00:40 PM PDT 24 |
| Finished | Jun 29 08:03:26 PM PDT 24 |
| Peak memory | 609156 kb |
| Host | smart-3b359db8-8372-4f84-be60-dedba91b88a5 |
| User | root |
| Command | /workspace/default/simv +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=clkmgr_jitter_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=476390569 -assert nopo stproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defa ult.vdb -cm_log /dev/null -cm_name 2.chip_sw_clkmgr_jitter_reduced_freq.476390569 |
| Directory | /workspace/2.chip_sw_clkmgr_jitter_reduced_freq/latest |
| Test location | /workspace/coverage/default/2.chip_sw_clkmgr_off_aes_trans.2260494686 |
| Short name | T1023 |
| Test name | |
| Test status | |
| Simulation time | 4001097800 ps |
| CPU time | 393.44 seconds |
| Started | Jun 29 07:59:13 PM PDT 24 |
| Finished | Jun 29 08:05:47 PM PDT 24 |
| Peak memory | 609156 kb |
| Host | smart-2f7d06d0-02f5-45f7-b79f-e450ad793ac8 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_off_aes_trans_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2260494686 -assert nopostproc +UVM_T ESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l og /dev/null -cm_name 2.chip_sw_clkmgr_off_aes_trans.2260494686 |
| Directory | /workspace/2.chip_sw_clkmgr_off_aes_trans/latest |
| Test location | /workspace/coverage/default/2.chip_sw_clkmgr_off_hmac_trans.1189795957 |
| Short name | T1054 |
| Test name | |
| Test status | |
| Simulation time | 4854690200 ps |
| CPU time | 456.21 seconds |
| Started | Jun 29 08:00:27 PM PDT 24 |
| Finished | Jun 29 08:08:04 PM PDT 24 |
| Peak memory | 609196 kb |
| Host | smart-e67d8c2f-d6af-4557-93d6-6673069610f9 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_off_hmac_trans_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1189795957 -assert nopostproc +UVM_ TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_ log /dev/null -cm_name 2.chip_sw_clkmgr_off_hmac_trans.1189795957 |
| Directory | /workspace/2.chip_sw_clkmgr_off_hmac_trans/latest |
| Test location | /workspace/coverage/default/2.chip_sw_clkmgr_off_kmac_trans.853754646 |
| Short name | T889 |
| Test name | |
| Test status | |
| Simulation time | 4882448800 ps |
| CPU time | 460.75 seconds |
| Started | Jun 29 07:59:55 PM PDT 24 |
| Finished | Jun 29 08:07:37 PM PDT 24 |
| Peak memory | 609192 kb |
| Host | smart-4342c878-25b0-480d-9e63-750135843944 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_off_kmac_trans_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=853754646 -assert nopostproc +UVM_T ESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l og /dev/null -cm_name 2.chip_sw_clkmgr_off_kmac_trans.853754646 |
| Directory | /workspace/2.chip_sw_clkmgr_off_kmac_trans/latest |
| Test location | /workspace/coverage/default/2.chip_sw_clkmgr_off_otbn_trans.4097351566 |
| Short name | T906 |
| Test name | |
| Test status | |
| Simulation time | 5672779220 ps |
| CPU time | 566.13 seconds |
| Started | Jun 29 07:59:27 PM PDT 24 |
| Finished | Jun 29 08:08:54 PM PDT 24 |
| Peak memory | 609184 kb |
| Host | smart-58010e32-37d8-4af3-a437-2a4074ad6b41 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_off_otbn_trans_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4097351566 -assert nopostproc +UVM_ TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_ log /dev/null -cm_name 2.chip_sw_clkmgr_off_otbn_trans.4097351566 |
| Directory | /workspace/2.chip_sw_clkmgr_off_otbn_trans/latest |
| Test location | /workspace/coverage/default/2.chip_sw_clkmgr_off_peri.3441503536 |
| Short name | T377 |
| Test name | |
| Test status | |
| Simulation time | 9355797904 ps |
| CPU time | 993.78 seconds |
| Started | Jun 29 07:59:58 PM PDT 24 |
| Finished | Jun 29 08:16:32 PM PDT 24 |
| Peak memory | 609200 kb |
| Host | smart-e20819fa-aa44-48b3-b6f8-a175b4f4679e |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=30_000_000 +sw_build_device=sim_dv +sw_images=clkmgr_off_peri_test:1:new_rules,test_rom:0 +cdc_instrumenta tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3441503536 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/ coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_clkmgr_off_peri.3441503536 |
| Directory | /workspace/2.chip_sw_clkmgr_off_peri/latest |
| Test location | /workspace/coverage/default/2.chip_sw_clkmgr_reset_frequency.1443085359 |
| Short name | T1127 |
| Test name | |
| Test status | |
| Simulation time | 3488986116 ps |
| CPU time | 412.71 seconds |
| Started | Jun 29 08:00:24 PM PDT 24 |
| Finished | Jun 29 08:07:17 PM PDT 24 |
| Peak memory | 609188 kb |
| Host | smart-246e378f-667f-4d86-a608-0fc3cad2dfaa |
| User | root |
| Command | /workspace/default/simv +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=clkmgr_reset_frequency_test:1:new_rules,test_rom:0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1443085359 -a ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov erage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_clkmgr_reset_frequency.1443085359 |
| Directory | /workspace/2.chip_sw_clkmgr_reset_frequency/latest |
| Test location | /workspace/coverage/default/2.chip_sw_clkmgr_sleep_frequency.3183854718 |
| Short name | T1139 |
| Test name | |
| Test status | |
| Simulation time | 4720374154 ps |
| CPU time | 595.25 seconds |
| Started | Jun 29 08:01:09 PM PDT 24 |
| Finished | Jun 29 08:11:04 PM PDT 24 |
| Peak memory | 607836 kb |
| Host | smart-febc8303-3344-4663-8efc-0555a4475928 |
| User | root |
| Command | /workspace/default/simv +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=clkmgr_sleep_frequency_test:1:new_rules,test_rom:0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3183854718 -a ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov erage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_clkmgr_sleep_frequency.3183854718 |
| Directory | /workspace/2.chip_sw_clkmgr_sleep_frequency/latest |
| Test location | /workspace/coverage/default/2.chip_sw_clkmgr_smoketest.2284419906 |
| Short name | T1148 |
| Test name | |
| Test status | |
| Simulation time | 3108780136 ps |
| CPU time | 286.19 seconds |
| Started | Jun 29 08:01:47 PM PDT 24 |
| Finished | Jun 29 08:06:34 PM PDT 24 |
| Peak memory | 607124 kb |
| Host | smart-226bdcb2-688a-4179-b836-75d2ca4fcd3b |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2284419906 -assert nopostproc +UVM_TESTNAME=c hip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n ull -cm_name 2.chip_sw_clkmgr_smoketest.2284419906 |
| Directory | /workspace/2.chip_sw_clkmgr_smoketest/latest |
| Test location | /workspace/coverage/default/2.chip_sw_csrng_edn_concurrency.4001515897 |
| Short name | T1123 |
| Test name | |
| Test status | |
| Simulation time | 34818782232 ps |
| CPU time | 8953.03 seconds |
| Started | Jun 29 07:59:59 PM PDT 24 |
| Finished | Jun 29 10:29:13 PM PDT 24 |
| Peak memory | 608424 kb |
| Host | smart-86f0db3b-aab6-41ac-8433-70042052fe29 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=140_000_000 +rng_srate_value_min=15 +rng_srate_value_max=20 +sw_build_device=sim_dv +sw_images=csrng_edn_c oncurrency_test:1:new_rules,test_rom:0 +accelerate_cold_power_up_time=3 +accelerate_regulators_power_up_time=2 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4001515897 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd b -cm_log /dev/null -cm_name 2.chip_sw_csrng_edn_concurrency.4001515897 |
| Directory | /workspace/2.chip_sw_csrng_edn_concurrency/latest |
| Test location | /workspace/coverage/default/2.chip_sw_csrng_fuse_en_sw_app_read_test.149647883 |
| Short name | T189 |
| Test name | |
| Test status | |
| Simulation time | 5203809228 ps |
| CPU time | 618.13 seconds |
| Started | Jun 29 07:57:22 PM PDT 24 |
| Finished | Jun 29 08:07:40 PM PDT 24 |
| Peak memory | 608236 kb |
| Host | smart-c0896d79-426a-4f1b-bd9d-2e349cf1aea7 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=15_000_000 +sw_build_device=sim_dv +sw_images=csrng_fuse_en_sw_app_read:1:new_rules,test_rom:0 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14964 7883 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_entropy_src_fuse_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_csrng_fuse_en_sw_app_read_test.149647883 |
| Directory | /workspace/2.chip_sw_csrng_fuse_en_sw_app_read_test/latest |
| Test location | /workspace/coverage/default/2.chip_sw_csrng_kat_test.333924427 |
| Short name | T1276 |
| Test name | |
| Test status | |
| Simulation time | 3518271212 ps |
| CPU time | 265.46 seconds |
| Started | Jun 29 07:59:15 PM PDT 24 |
| Finished | Jun 29 08:03:41 PM PDT 24 |
| Peak memory | 607516 kb |
| Host | smart-6842579f-4bff-4da7-aaf5-4b5adce6aa80 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=csrng_kat_test:1:new_rules,test_rom:0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=333924427 -asser t nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag e/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_csrng_kat_test.333924427 |
| Directory | /workspace/2.chip_sw_csrng_kat_test/latest |
| Test location | /workspace/coverage/default/2.chip_sw_csrng_lc_hw_debug_en_test.1105064070 |
| Short name | T370 |
| Test name | |
| Test status | |
| Simulation time | 6549318140 ps |
| CPU time | 796.56 seconds |
| Started | Jun 29 07:59:17 PM PDT 24 |
| Finished | Jun 29 08:12:34 PM PDT 24 |
| Peak memory | 608884 kb |
| Host | smart-d14484fc-187b-4020-aace-b21aa1ad7c10 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=15_000_000 +rng_srate_value_min=15 +use_otp_image=OtpTypeLcStTestUnlocked0 +sw_build_device=sim_dv +sw_ima ges=csrng_lc_hw_debug_en_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1105064070 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_csrng_ lc_hw_debug_en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_csr ng_lc_hw_debug_en_test.1105064070 |
| Directory | /workspace/2.chip_sw_csrng_lc_hw_debug_en_test/latest |
| Test location | /workspace/coverage/default/2.chip_sw_csrng_smoketest.1923092511 |
| Short name | T1277 |
| Test name | |
| Test status | |
| Simulation time | 3405496602 ps |
| CPU time | 256.92 seconds |
| Started | Jun 29 08:02:11 PM PDT 24 |
| Finished | Jun 29 08:06:28 PM PDT 24 |
| Peak memory | 606424 kb |
| Host | smart-355b5da1-d9eb-43e8-9298-ce9cb524efbd |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=csrng_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1923092511 -assert nopostproc +UVM_TESTNAME=ch ip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu ll -cm_name 2.chip_sw_csrng_smoketest.1923092511 |
| Directory | /workspace/2.chip_sw_csrng_smoketest/latest |
| Test location | /workspace/coverage/default/2.chip_sw_data_integrity_escalation.306617492 |
| Short name | T1186 |
| Test name | |
| Test status | |
| Simulation time | 4376906268 ps |
| CPU time | 719.7 seconds |
| Started | Jun 29 07:53:32 PM PDT 24 |
| Finished | Jun 29 08:05:33 PM PDT 24 |
| Peak memory | 609268 kb |
| Host | smart-4ccb1efb-b9d2-4cd1-9a6e-923948e2f747 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=data_integrity_escalation_reset_test:1:new_rules,test_ro m:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=306617492 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_data_integrity_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_data_integrity_escalation.306617492 |
| Directory | /workspace/2.chip_sw_data_integrity_escalation/latest |
| Test location | /workspace/coverage/default/2.chip_sw_edn_auto_mode.3956616912 |
| Short name | T1168 |
| Test name | |
| Test status | |
| Simulation time | 5886381672 ps |
| CPU time | 1560.68 seconds |
| Started | Jun 29 07:57:52 PM PDT 24 |
| Finished | Jun 29 08:23:53 PM PDT 24 |
| Peak memory | 609276 kb |
| Host | smart-c2515000-e485-4d58-93e5-1d299037e9d4 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +rng_srate_value=5 +sw_build_device=sim_dv +sw_images=edn_auto_mode:1:new_rules,test_rom:0 +acc elerate_cold_power_up_time=3 +accelerate_regulators_power_up_time=2 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3956616912 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ =chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_edn_ auto_mode.3956616912 |
| Directory | /workspace/2.chip_sw_edn_auto_mode/latest |
| Test location | /workspace/coverage/default/2.chip_sw_edn_boot_mode.168656241 |
| Short name | T449 |
| Test name | |
| Test status | |
| Simulation time | 2896685756 ps |
| CPU time | 652.63 seconds |
| Started | Jun 29 08:00:01 PM PDT 24 |
| Finished | Jun 29 08:10:55 PM PDT 24 |
| Peak memory | 609308 kb |
| Host | smart-0e9045aa-1628-4303-a73d-853e4a60a8bd |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +rng_srate_value=5 +sw_build_device=sim_dv +sw_images=edn_boot_mode:1:new_rules,test_rom:0 +acc elerate_cold_power_up_time=3 +accelerate_regulators_power_up_time=2 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=168656241 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ= chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_edn_b oot_mode.168656241 |
| Directory | /workspace/2.chip_sw_edn_boot_mode/latest |
| Test location | /workspace/coverage/default/2.chip_sw_edn_entropy_reqs.2481472981 |
| Short name | T246 |
| Test name | |
| Test status | |
| Simulation time | 6331462786 ps |
| CPU time | 1512.6 seconds |
| Started | Jun 29 07:59:25 PM PDT 24 |
| Finished | Jun 29 08:24:38 PM PDT 24 |
| Peak memory | 609324 kb |
| Host | smart-2d918d9a-665c-4ebf-a42a-93fa308bd778 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=15000000 +rng_srate_value_min=15 +rng_srate_value_max=30 +sw_build_device=sim_dv +sw_images=entropy_src_ed n_reqs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2481472981 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_edn_entropy_reqs.2481472981 |
| Directory | /workspace/2.chip_sw_edn_entropy_reqs/latest |
| Test location | /workspace/coverage/default/2.chip_sw_edn_entropy_reqs_jitter.3149560283 |
| Short name | T1185 |
| Test name | |
| Test status | |
| Simulation time | 6620350698 ps |
| CPU time | 1403.83 seconds |
| Started | Jun 29 07:58:44 PM PDT 24 |
| Finished | Jun 29 08:22:09 PM PDT 24 |
| Peak memory | 609332 kb |
| Host | smart-dd4a8c27-3da7-4885-ad9b-c9aa88e6bf1b |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=15000000 +rng_srate_value_min=15 +rng_srate_value_max=30 +en_jitter=1 +sw_build_device=sim_dv +sw_images=e ntropy_src_edn_reqs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3149560283 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_edn_entropy_reqs_jitter.3149560283 |
| Directory | /workspace/2.chip_sw_edn_entropy_reqs_jitter/latest |
| Test location | /workspace/coverage/default/2.chip_sw_edn_kat.2206138665 |
| Short name | T1066 |
| Test name | |
| Test status | |
| Simulation time | 3453985240 ps |
| CPU time | 660.29 seconds |
| Started | Jun 29 07:59:01 PM PDT 24 |
| Finished | Jun 29 08:10:02 PM PDT 24 |
| Peak memory | 614524 kb |
| Host | smart-27e15110-f34c-4043-92eb-77aa0176645c |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +rng_srate_value=5 +disable_assert_edn_output_diff_from_prev=1 +sw_build_device=sim_dv +sw_imag es=edn_kat:1:new_rules,test_rom:0 +accelerate_cold_power_up_time=3 +accelerate_regulators_power_up_time=2 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2206138665 -assert nopostproc +UVM _TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm _log /dev/null -cm_name 2.chip_sw_edn_kat.2206138665 |
| Directory | /workspace/2.chip_sw_edn_kat/latest |
| Test location | /workspace/coverage/default/2.chip_sw_edn_sw_mode.2105986627 |
| Short name | T830 |
| Test name | |
| Test status | |
| Simulation time | 5890672112 ps |
| CPU time | 1601.67 seconds |
| Started | Jun 29 07:57:00 PM PDT 24 |
| Finished | Jun 29 08:23:42 PM PDT 24 |
| Peak memory | 609192 kb |
| Host | smart-f82f74c8-f837-471e-97a8-d378599e11d4 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=edn_sw_mode:1:new_rules,test_rom:0 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2105986627 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/ default.vdb -cm_log /dev/null -cm_name 2.chip_sw_edn_sw_mode.2105986627 |
| Directory | /workspace/2.chip_sw_edn_sw_mode/latest |
| Test location | /workspace/coverage/default/2.chip_sw_entropy_src_ast_rng_req.2000610870 |
| Short name | T836 |
| Test name | |
| Test status | |
| Simulation time | 3196718346 ps |
| CPU time | 215.3 seconds |
| Started | Jun 29 07:58:09 PM PDT 24 |
| Finished | Jun 29 08:01:44 PM PDT 24 |
| Peak memory | 609196 kb |
| Host | smart-1d34ee2e-4547-4e17-9cba-f338a4f581da |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=15_000_000 +sw_build_device=sim_dv +sw_images=entropy_src_ast_rng_req_test:1:new_rules,test_rom:0 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20 00610870 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_entropy_src_ast_rng_req.2000610870 |
| Directory | /workspace/2.chip_sw_entropy_src_ast_rng_req/latest |
| Test location | /workspace/coverage/default/2.chip_sw_entropy_src_csrng.1487202329 |
| Short name | T299 |
| Test name | |
| Test status | |
| Simulation time | 6683320536 ps |
| CPU time | 1597.24 seconds |
| Started | Jun 29 08:00:13 PM PDT 24 |
| Finished | Jun 29 08:26:51 PM PDT 24 |
| Peak memory | 609312 kb |
| Host | smart-2dfaabbd-d267-4c80-ac35-4e60fb2a2258 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=50_000_000 +rng_srate_value_min=15 +rng_srate_value_max=30 +sw_build_device=sim_dv +sw_images=entropy_src_ csrng_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1487202329 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_entropy_src_csrng.1487202329 |
| Directory | /workspace/2.chip_sw_entropy_src_csrng/latest |
| Test location | /workspace/coverage/default/2.chip_sw_entropy_src_kat_test.387094512 |
| Short name | T1119 |
| Test name | |
| Test status | |
| Simulation time | 2878989740 ps |
| CPU time | 195.02 seconds |
| Started | Jun 29 07:57:26 PM PDT 24 |
| Finished | Jun 29 08:00:41 PM PDT 24 |
| Peak memory | 609160 kb |
| Host | smart-6f8d9a0e-1398-446f-90f0-d33a6dab784d |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=entropy_src_kat_test:1:new_rules,test_rom:0 +cdc_instrumenta tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=387094512 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/c overage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_entropy_src_kat_test.387094512 |
| Directory | /workspace/2.chip_sw_entropy_src_kat_test/latest |
| Test location | /workspace/coverage/default/2.chip_sw_entropy_src_smoketest.3929171984 |
| Short name | T1150 |
| Test name | |
| Test status | |
| Simulation time | 3100614488 ps |
| CPU time | 518.68 seconds |
| Started | Jun 29 08:02:06 PM PDT 24 |
| Finished | Jun 29 08:10:45 PM PDT 24 |
| Peak memory | 609192 kb |
| Host | smart-db4bac8c-2b85-4663-990a-8c3a952c5290 |
| User | root |
| Command | /workspace/default/simv +rng_srate_value_min=15 +rng_srate_value_max=30 +sw_build_device=sim_dv +sw_images=entropy_src_smoketest:1:new_rules,test_rom: 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand om_seed=3929171984 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_entropy_src_smoketest.3929171984 |
| Directory | /workspace/2.chip_sw_entropy_src_smoketest/latest |
| Test location | /workspace/coverage/default/2.chip_sw_example_concurrency.2784744158 |
| Short name | T1052 |
| Test name | |
| Test status | |
| Simulation time | 3283331958 ps |
| CPU time | 317.13 seconds |
| Started | Jun 29 07:56:58 PM PDT 24 |
| Finished | Jun 29 08:02:15 PM PDT 24 |
| Peak memory | 609144 kb |
| Host | smart-777ee6d3-69dd-46a2-a37c-e3915a7f3984 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=example_concurrency_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2784744158 -assert nopostproc +UVM_TE STNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo g /dev/null -cm_name 2.chip_sw_example_concurrency.2784744158 |
| Directory | /workspace/2.chip_sw_example_concurrency/latest |
| Test location | /workspace/coverage/default/2.chip_sw_example_flash.829049541 |
| Short name | T1250 |
| Test name | |
| Test status | |
| Simulation time | 2822321624 ps |
| CPU time | 291.53 seconds |
| Started | Jun 29 07:56:56 PM PDT 24 |
| Finished | Jun 29 08:01:48 PM PDT 24 |
| Peak memory | 609148 kb |
| Host | smart-f26649b6-61ec-4f4e-a6ef-0dcf4eaf4966 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=example_test_from_flash:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=829049541 -assert nopostproc +UVM_TEST NAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_example_flash.829049541 |
| Directory | /workspace/2.chip_sw_example_flash/latest |
| Test location | /workspace/coverage/default/2.chip_sw_example_manufacturer.2510073566 |
| Short name | T1057 |
| Test name | |
| Test status | |
| Simulation time | 2545229606 ps |
| CPU time | 327.96 seconds |
| Started | Jun 29 07:57:28 PM PDT 24 |
| Finished | Jun 29 08:02:56 PM PDT 24 |
| Peak memory | 607084 kb |
| Host | smart-2c664b90-b426-4a65-a14a-5f80df1751e6 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=example_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2510073566 -assert nopostproc +UVM_TESTNAME=chip_ base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_example_manufacturer.2510073566 |
| Directory | /workspace/2.chip_sw_example_manufacturer/latest |
| Test location | /workspace/coverage/default/2.chip_sw_example_rom.1254616976 |
| Short name | T1141 |
| Test name | |
| Test status | |
| Simulation time | 2566688098 ps |
| CPU time | 154.51 seconds |
| Started | Jun 29 07:52:55 PM PDT 24 |
| Finished | Jun 29 07:55:30 PM PDT 24 |
| Peak memory | 607256 kb |
| Host | smart-e750b228-b201-4145-be74-d8643c4c2516 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:test_in_rom:new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1254616976 -assert nopostproc +UVM_TEST NAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_example_rom.1254616976 |
| Directory | /workspace/2.chip_sw_example_rom/latest |
| Test location | /workspace/coverage/default/2.chip_sw_exit_test_unlocked_bootstrap.446877111 |
| Short name | T68 |
| Test name | |
| Test status | |
| Simulation time | 60137384440 ps |
| CPU time | 11568.7 seconds |
| Started | Jun 29 07:59:22 PM PDT 24 |
| Finished | Jun 29 11:12:12 PM PDT 24 |
| Peak memory | 623488 kb |
| Host | smart-27882214-cb64-451a-a6b6-c73f638a210b |
| User | root |
| Command | /workspace/default/simv +flash_program_latency=5 +sw_test_timeout_ns=150_000_000 +sw_build_device=sim_dv +sw_images=exit_test_unlocked_bootstrap:1:new _rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/s im.tcl +ntb_random_seed=446877111 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_exit_test_unlocked_bootstrap_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_exit_test_unlocked_bootstrap.446877111 |
| Directory | /workspace/2.chip_sw_exit_test_unlocked_bootstrap/latest |
| Test location | /workspace/coverage/default/2.chip_sw_flash_crash_alert.582700865 |
| Short name | T704 |
| Test name | |
| Test status | |
| Simulation time | 6301343778 ps |
| CPU time | 744.15 seconds |
| Started | Jun 29 08:01:45 PM PDT 24 |
| Finished | Jun 29 08:14:10 PM PDT 24 |
| Peak memory | 609380 kb |
| Host | smart-dbef2636-413d-49ec-98eb-081860a9f1f3 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=8_000_000 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1: new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tool s/sim.tcl +ntb_random_seed=582700865 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_flash_host_gnt_err_inj_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_flash_crash_alert.582700865 |
| Directory | /workspace/2.chip_sw_flash_crash_alert/latest |
| Test location | /workspace/coverage/default/2.chip_sw_flash_ctrl_access.3073995747 |
| Short name | T269 |
| Test name | |
| Test status | |
| Simulation time | 5766527848 ps |
| CPU time | 1133.46 seconds |
| Started | Jun 29 07:54:42 PM PDT 24 |
| Finished | Jun 29 08:13:36 PM PDT 24 |
| Peak memory | 607136 kb |
| Host | smart-f91d71b9-6cc6-43bb-b515-45e32777c238 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=flash_ctrl_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3073995747 -assert nopostproc +UVM_TESTNAME=ch ip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu ll -cm_name 2.chip_sw_flash_ctrl_access.3073995747 |
| Directory | /workspace/2.chip_sw_flash_ctrl_access/latest |
| Test location | /workspace/coverage/default/2.chip_sw_flash_ctrl_access_jitter_en.2058848386 |
| Short name | T359 |
| Test name | |
| Test status | |
| Simulation time | 6055917777 ps |
| CPU time | 1177.97 seconds |
| Started | Jun 29 07:54:04 PM PDT 24 |
| Finished | Jun 29 08:13:43 PM PDT 24 |
| Peak memory | 609176 kb |
| Host | smart-7fb6149c-d785-454c-af51-ba663269ad41 |
| User | root |
| Command | /workspace/default/simv +en_jitter=1 +sw_build_device=sim_dv +sw_images=flash_ctrl_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2058848386 -assert nopostproc +UV M_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -c m_log /dev/null -cm_name 2.chip_sw_flash_ctrl_access_jitter_en.2058848386 |
| Directory | /workspace/2.chip_sw_flash_ctrl_access_jitter_en/latest |
| Test location | /workspace/coverage/default/2.chip_sw_flash_ctrl_access_jitter_en_reduced_freq.2501510368 |
| Short name | T932 |
| Test name | |
| Test status | |
| Simulation time | 7396147425 ps |
| CPU time | 1288.93 seconds |
| Started | Jun 29 08:02:01 PM PDT 24 |
| Finished | Jun 29 08:23:30 PM PDT 24 |
| Peak memory | 609196 kb |
| Host | smart-d2f1f800-f89d-4e0b-a650-2e311b2fc01c |
| User | root |
| Command | /workspace/default/simv +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=flash_ctrl_test:1:new_rules,test_rom:0 +cdc_instrumentati on_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2501510368 - assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co verage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_flash_ctrl_access_jitter_en_reduced_freq.2501510368 |
| Directory | /workspace/2.chip_sw_flash_ctrl_access_jitter_en_reduced_freq/latest |
| Test location | /workspace/coverage/default/2.chip_sw_flash_ctrl_clock_freqs.1625080058 |
| Short name | T1110 |
| Test name | |
| Test status | |
| Simulation time | 5348466876 ps |
| CPU time | 964.55 seconds |
| Started | Jun 29 07:54:50 PM PDT 24 |
| Finished | Jun 29 08:10:56 PM PDT 24 |
| Peak memory | 607508 kb |
| Host | smart-b9d5cd59-43af-42f0-a1e3-4eeb67ba4790 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=flash_ctrl_clock_freqs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1625080058 -assert nopostproc +UVM _TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm _log /dev/null -cm_name 2.chip_sw_flash_ctrl_clock_freqs.1625080058 |
| Directory | /workspace/2.chip_sw_flash_ctrl_clock_freqs/latest |
| Test location | /workspace/coverage/default/2.chip_sw_flash_ctrl_idle_low_power.1198895839 |
| Short name | T870 |
| Test name | |
| Test status | |
| Simulation time | 3678010784 ps |
| CPU time | 530.53 seconds |
| Started | Jun 29 08:00:48 PM PDT 24 |
| Finished | Jun 29 08:09:40 PM PDT 24 |
| Peak memory | 607164 kb |
| Host | smart-7aded2f5-920a-4865-a334-a4332a9df110 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=flash_ctrl_idle_low_power_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1198895839 -assert nopostproc + UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_flash_ctrl_idle_low_power.1198895839 |
| Directory | /workspace/2.chip_sw_flash_ctrl_idle_low_power/latest |
| Test location | /workspace/coverage/default/2.chip_sw_flash_ctrl_lc_rw_en.2209867691 |
| Short name | T214 |
| Test name | |
| Test status | |
| Simulation time | 5457273745 ps |
| CPU time | 465.38 seconds |
| Started | Jun 29 07:54:59 PM PDT 24 |
| Finished | Jun 29 08:02:44 PM PDT 24 |
| Peak memory | 609196 kb |
| Host | smart-cf64ee9d-dc9d-46d6-bedb-ff78e77a1ec7 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=flash_ctrl_lc_rw_en_test:1:new_rules,test_rom:0 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22 09867691 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_flash_ctrl_lc_rw_en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_flash_ctrl_lc_rw_en.2209867691 |
| Directory | /workspace/2.chip_sw_flash_ctrl_lc_rw_en/latest |
| Test location | /workspace/coverage/default/2.chip_sw_flash_ctrl_mem_protection.1600007620 |
| Short name | T398 |
| Test name | |
| Test status | |
| Simulation time | 6250798500 ps |
| CPU time | 1271.28 seconds |
| Started | Jun 29 08:05:12 PM PDT 24 |
| Finished | Jun 29 08:26:24 PM PDT 24 |
| Peak memory | 609164 kb |
| Host | smart-d07c663e-67e1-411b-bd94-bee71e598915 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=flash_ctrl_mem_protection_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1600007620 -assert nopostproc + UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_flash_ctrl_mem_protection.1600007620 |
| Directory | /workspace/2.chip_sw_flash_ctrl_mem_protection/latest |
| Test location | /workspace/coverage/default/2.chip_sw_flash_ctrl_ops.1721176280 |
| Short name | T317 |
| Test name | |
| Test status | |
| Simulation time | 4578600344 ps |
| CPU time | 756.61 seconds |
| Started | Jun 29 07:55:47 PM PDT 24 |
| Finished | Jun 29 08:08:24 PM PDT 24 |
| Peak memory | 609148 kb |
| Host | smart-9610e8b7-9d1c-4c08-854b-b603b990c821 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=50_000_000 +sw_build_device=sim_dv +sw_images=flash_ctrl_ops_test:1:new_rules,test_rom:0 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1721176280 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/c overage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_flash_ctrl_ops.1721176280 |
| Directory | /workspace/2.chip_sw_flash_ctrl_ops/latest |
| Test location | /workspace/coverage/default/2.chip_sw_flash_ctrl_ops_jitter_en_reduced_freq.1078711457 |
| Short name | T315 |
| Test name | |
| Test status | |
| Simulation time | 5060738966 ps |
| CPU time | 771.72 seconds |
| Started | Jun 29 08:01:06 PM PDT 24 |
| Finished | Jun 29 08:13:59 PM PDT 24 |
| Peak memory | 609176 kb |
| Host | smart-2d3d62ea-bb42-462d-91a7-fd0d4f713f7d |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=50_000_000 +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=flash_ctrl_ops_test:1:new_ rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si m.tcl +ntb_random_seed=1078711457 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_flash_ctrl_ops_jitter_en_reduced_freq.1078711457 |
| Directory | /workspace/2.chip_sw_flash_ctrl_ops_jitter_en_reduced_freq/latest |
| Test location | /workspace/coverage/default/2.chip_sw_flash_ctrl_write_clear.349334662 |
| Short name | T925 |
| Test name | |
| Test status | |
| Simulation time | 3082432310 ps |
| CPU time | 449.99 seconds |
| Started | Jun 29 08:00:56 PM PDT 24 |
| Finished | Jun 29 08:08:27 PM PDT 24 |
| Peak memory | 607108 kb |
| Host | smart-fcbd576b-9c61-40b2-9217-ae5baa2fe020 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=8_000_000 +sw_build_device=sim_dv +sw_images=flash_ctrl_write_clear_test:1:new_rules,test_rom:0 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3493346 62 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac e/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_flash_ctrl_write_clear.349334662 |
| Directory | /workspace/2.chip_sw_flash_ctrl_write_clear/latest |
| Test location | /workspace/coverage/default/2.chip_sw_flash_init.2897438318 |
| Short name | T180 |
| Test name | |
| Test status | |
| Simulation time | 24062841760 ps |
| CPU time | 2546.25 seconds |
| Started | Jun 29 07:54:25 PM PDT 24 |
| Finished | Jun 29 08:36:52 PM PDT 24 |
| Peak memory | 610736 kb |
| Host | smart-1474f472-c2c8-4759-b012-de89c1301e11 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=25_000_000 +sw_build_device=sim_dv +sw_images=flash_init_test:0:test_in_rom:new_rules +cdc_instrumentation _enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2897438318 -as sert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_flash_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac e/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_flash_init.2897438318 |
| Directory | /workspace/2.chip_sw_flash_init/latest |
| Test location | /workspace/coverage/default/2.chip_sw_flash_init_reduced_freq.2264813070 |
| Short name | T215 |
| Test name | |
| Test status | |
| Simulation time | 22240916350 ps |
| CPU time | 2059.03 seconds |
| Started | Jun 29 08:01:42 PM PDT 24 |
| Finished | Jun 29 08:36:02 PM PDT 24 |
| Peak memory | 610508 kb |
| Host | smart-a6d982dd-fe45-4d3a-8638-215782f5dfbc |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=25_000_000 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=flash_init_test:0:test_in_rom:new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=2264813070 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_flash_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_flash_init_reduced_freq.2264813070 |
| Directory | /workspace/2.chip_sw_flash_init_reduced_freq/latest |
| Test location | /workspace/coverage/default/2.chip_sw_flash_scrambling_smoketest.778064933 |
| Short name | T1177 |
| Test name | |
| Test status | |
| Simulation time | 2777727934 ps |
| CPU time | 201.85 seconds |
| Started | Jun 29 08:07:44 PM PDT 24 |
| Finished | Jun 29 08:11:07 PM PDT 24 |
| Peak memory | 607612 kb |
| Host | smart-7e54c819-ebcc-4d78-839a-c12b8985c766 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=flash_scrambling_smoketest:1:new_rules,flash_scrambling_smoket est_otp_img_rma:4,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=778064933 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_flash_scrambling_smoketest.778064933 |
| Directory | /workspace/2.chip_sw_flash_scrambling_smoketest/latest |
| Test location | /workspace/coverage/default/2.chip_sw_gpio_smoketest.1827870690 |
| Short name | T923 |
| Test name | |
| Test status | |
| Simulation time | 2699023615 ps |
| CPU time | 255.28 seconds |
| Started | Jun 29 08:05:58 PM PDT 24 |
| Finished | Jun 29 08:10:13 PM PDT 24 |
| Peak memory | 607876 kb |
| Host | smart-aa0f7f9a-7b6c-4d2f-a3a7-ed814f09c381 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=gpio_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1827870690 -assert nopostproc +UVM_TESTNAME=chi p_base_test +UVM_TEST_SEQ=chip_sw_gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 2.chip_sw_gpio_smoketest.1827870690 |
| Directory | /workspace/2.chip_sw_gpio_smoketest/latest |
| Test location | /workspace/coverage/default/2.chip_sw_hmac_enc.2496228675 |
| Short name | T1036 |
| Test name | |
| Test status | |
| Simulation time | 3434490608 ps |
| CPU time | 287.65 seconds |
| Started | Jun 29 07:59:47 PM PDT 24 |
| Finished | Jun 29 08:04:35 PM PDT 24 |
| Peak memory | 606360 kb |
| Host | smart-9c423efa-d6de-4838-9b57-c7d64770e161 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=hmac_enc_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2496228675 -assert nopostproc +UVM_TESTNAME=chip _base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_hmac_enc.2496228675 |
| Directory | /workspace/2.chip_sw_hmac_enc/latest |
| Test location | /workspace/coverage/default/2.chip_sw_hmac_enc_idle.1154456437 |
| Short name | T983 |
| Test name | |
| Test status | |
| Simulation time | 2383654708 ps |
| CPU time | 239.19 seconds |
| Started | Jun 29 07:59:54 PM PDT 24 |
| Finished | Jun 29 08:03:54 PM PDT 24 |
| Peak memory | 606312 kb |
| Host | smart-ad4d0871-2ec0-41f1-b725-5bb8004c03a6 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=hmac_enc_idle_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1154456437 -assert nopostproc +UVM_TESTNAME =chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 2.chip_sw_hmac_enc_idle.1154456437 |
| Directory | /workspace/2.chip_sw_hmac_enc_idle/latest |
| Test location | /workspace/coverage/default/2.chip_sw_hmac_enc_jitter_en.2571762929 |
| Short name | T318 |
| Test name | |
| Test status | |
| Simulation time | 2680491977 ps |
| CPU time | 394.47 seconds |
| Started | Jun 29 07:58:15 PM PDT 24 |
| Finished | Jun 29 08:04:50 PM PDT 24 |
| Peak memory | 609176 kb |
| Host | smart-26acb5a4-4e37-448f-bcfa-854b429dd099 |
| User | root |
| Command | /workspace/default/simv +en_jitter=1 +sw_build_device=sim_dv +sw_images=hmac_enc_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2571762929 -assert nopostproc +UVM_ TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_ log /dev/null -cm_name 2.chip_sw_hmac_enc_jitter_en.2571762929 |
| Directory | /workspace/2.chip_sw_hmac_enc_jitter_en/latest |
| Test location | /workspace/coverage/default/2.chip_sw_hmac_enc_jitter_en_reduced_freq.50435007 |
| Short name | T343 |
| Test name | |
| Test status | |
| Simulation time | 3360734753 ps |
| CPU time | 335.83 seconds |
| Started | Jun 29 08:01:27 PM PDT 24 |
| Finished | Jun 29 08:07:04 PM PDT 24 |
| Peak memory | 609348 kb |
| Host | smart-fec705d6-c78b-46b9-88e2-5960f3ba5222 |
| User | root |
| Command | /workspace/default/simv +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=hmac_enc_test:1:new_rules,test_rom:0 +cdc_instrumentation _enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50435007 -asse rt nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera ge/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_hmac_enc_jitter_en_reduced_freq.50435007 |
| Directory | /workspace/2.chip_sw_hmac_enc_jitter_en_reduced_freq/latest |
| Test location | /workspace/coverage/default/2.chip_sw_hmac_multistream.1461257694 |
| Short name | T1081 |
| Test name | |
| Test status | |
| Simulation time | 7780218952 ps |
| CPU time | 1749.56 seconds |
| Started | Jun 29 07:58:44 PM PDT 24 |
| Finished | Jun 29 08:27:55 PM PDT 24 |
| Peak memory | 607792 kb |
| Host | smart-4aa7d203-f977-4b83-a6ff-4991487f9a11 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=hmac_multistream_functest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1461257694 -assert nopostproc +UVM_T ESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l og /dev/null -cm_name 2.chip_sw_hmac_multistream.1461257694 |
| Directory | /workspace/2.chip_sw_hmac_multistream/latest |
| Test location | /workspace/coverage/default/2.chip_sw_hmac_oneshot.4235677547 |
| Short name | T886 |
| Test name | |
| Test status | |
| Simulation time | 3750768008 ps |
| CPU time | 423.64 seconds |
| Started | Jun 29 07:58:16 PM PDT 24 |
| Finished | Jun 29 08:05:19 PM PDT 24 |
| Peak memory | 607124 kb |
| Host | smart-78f83485-7fb7-4e1e-893d-57b497a738b8 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=hmac_functest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4235677547 -assert nopostproc +UVM_TESTNAME=chip _base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_hmac_oneshot.4235677547 |
| Directory | /workspace/2.chip_sw_hmac_oneshot/latest |
| Test location | /workspace/coverage/default/2.chip_sw_hmac_smoketest.3935633396 |
| Short name | T669 |
| Test name | |
| Test status | |
| Simulation time | 3249819090 ps |
| CPU time | 304.6 seconds |
| Started | Jun 29 08:02:21 PM PDT 24 |
| Finished | Jun 29 08:07:26 PM PDT 24 |
| Peak memory | 607136 kb |
| Host | smart-f87dcd91-a711-42e7-a091-4324ac62beea |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=hmac_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3935633396 -assert nopostproc +UVM_TESTNAME=chi p_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul l -cm_name 2.chip_sw_hmac_smoketest.3935633396 |
| Directory | /workspace/2.chip_sw_hmac_smoketest/latest |
| Test location | /workspace/coverage/default/2.chip_sw_i2c_device_tx_rx.2899735715 |
| Short name | T1283 |
| Test name | |
| Test status | |
| Simulation time | 4059513060 ps |
| CPU time | 525.58 seconds |
| Started | Jun 29 07:54:31 PM PDT 24 |
| Finished | Jun 29 08:03:17 PM PDT 24 |
| Peak memory | 609312 kb |
| Host | smart-836e8600-55fc-40d7-9a2a-acd9152c12b9 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=i2c_device_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2899735715 -assert nopostproc +UVM_TESTN AME=chip_base_test +UVM_TEST_SEQ=chip_sw_i2c_device_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v db -cm_log /dev/null -cm_name 2.chip_sw_i2c_device_tx_rx.2899735715 |
| Directory | /workspace/2.chip_sw_i2c_device_tx_rx/latest |
| Test location | /workspace/coverage/default/2.chip_sw_i2c_host_tx_rx.1708682951 |
| Short name | T190 |
| Test name | |
| Test status | |
| Simulation time | 4942275334 ps |
| CPU time | 805.4 seconds |
| Started | Jun 29 07:54:29 PM PDT 24 |
| Finished | Jun 29 08:07:55 PM PDT 24 |
| Peak memory | 608288 kb |
| Host | smart-1485fade-742c-4454-a76a-7d23e9642949 |
| User | root |
| Command | /workspace/default/simv +i2c_idx=0 +sw_build_device=sim_dv +sw_images=i2c_host_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1708682951 -assert nopostproc + UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_i2c_host_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de fault.vdb -cm_log /dev/null -cm_name 2.chip_sw_i2c_host_tx_rx.1708682951 |
| Directory | /workspace/2.chip_sw_i2c_host_tx_rx/latest |
| Test location | /workspace/coverage/default/2.chip_sw_i2c_host_tx_rx_idx1.1692672029 |
| Short name | T293 |
| Test name | |
| Test status | |
| Simulation time | 4481415602 ps |
| CPU time | 921.68 seconds |
| Started | Jun 29 07:54:10 PM PDT 24 |
| Finished | Jun 29 08:09:33 PM PDT 24 |
| Peak memory | 607876 kb |
| Host | smart-f601f88e-5956-4718-8392-278bc65fd9b0 |
| User | root |
| Command | /workspace/default/simv +i2c_idx=1 +sw_build_device=sim_dv +sw_images=i2c_host_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1692672029 -assert nopostproc + UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_i2c_host_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de fault.vdb -cm_log /dev/null -cm_name 2.chip_sw_i2c_host_tx_rx_idx1.1692672029 |
| Directory | /workspace/2.chip_sw_i2c_host_tx_rx_idx1/latest |
| Test location | /workspace/coverage/default/2.chip_sw_i2c_host_tx_rx_idx2.3920734878 |
| Short name | T304 |
| Test name | |
| Test status | |
| Simulation time | 4876084734 ps |
| CPU time | 787.2 seconds |
| Started | Jun 29 07:56:02 PM PDT 24 |
| Finished | Jun 29 08:09:10 PM PDT 24 |
| Peak memory | 607252 kb |
| Host | smart-bd38cb7c-facf-4c44-9fb7-aa9901efef07 |
| User | root |
| Command | /workspace/default/simv +i2c_idx=2 +sw_build_device=sim_dv +sw_images=i2c_host_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3920734878 -assert nopostproc + UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_i2c_host_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de fault.vdb -cm_log /dev/null -cm_name 2.chip_sw_i2c_host_tx_rx_idx2.3920734878 |
| Directory | /workspace/2.chip_sw_i2c_host_tx_rx_idx2/latest |
| Test location | /workspace/coverage/default/2.chip_sw_inject_scramble_seed.1925822876 |
| Short name | T998 |
| Test name | |
| Test status | |
| Simulation time | 64786248439 ps |
| CPU time | 12099.8 seconds |
| Started | Jun 29 07:59:19 PM PDT 24 |
| Finished | Jun 29 11:21:01 PM PDT 24 |
| Peak memory | 624060 kb |
| Host | smart-b1f3cbf5-61fe-4d71-8ab9-6b2753217c0d |
| User | root |
| Command | /workspace/default/simv +lc_at_prod=1 +flash_program_latency=5 +sw_test_timeout_ns=150_000_000 +sw_build_device=sim_dv +sw_images=inject_scramble_seed :1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=1925822876 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_inject_scramble_seed_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_inject_scramble_seed.1925822876 |
| Directory | /workspace/2.chip_sw_inject_scramble_seed/latest |
| Test location | /workspace/coverage/default/2.chip_sw_keymgr_key_derivation.3125815439 |
| Short name | T1267 |
| Test name | |
| Test status | |
| Simulation time | 9766240332 ps |
| CPU time | 1738.07 seconds |
| Started | Jun 29 07:58:28 PM PDT 24 |
| Finished | Jun 29 08:27:26 PM PDT 24 |
| Peak memory | 615568 kb |
| Host | smart-538e3a85-9c01-402f-9132-3bde042f48f9 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=20_000_000 +sw_build_device=sim_dv +sw_images=keymgr_key_derivation_test:1:new_rules,test_rom:0 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3125 815439 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_keymgr_key_derivation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_keymgr_key_derivation.3125815439 |
| Directory | /workspace/2.chip_sw_keymgr_key_derivation/latest |
| Test location | /workspace/coverage/default/2.chip_sw_keymgr_key_derivation_jitter_en.1727979616 |
| Short name | T103 |
| Test name | |
| Test status | |
| Simulation time | 9583166600 ps |
| CPU time | 1995.55 seconds |
| Started | Jun 29 07:58:39 PM PDT 24 |
| Finished | Jun 29 08:31:55 PM PDT 24 |
| Peak memory | 615452 kb |
| Host | smart-3b37d0a4-8c03-4c0b-b0d3-2ac5322f0b23 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=20_000_000 +en_jitter=1 +sw_build_device=sim_dv +sw_images=keymgr_key_derivation_test:1:new_rules,test_rom :0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=1727979616 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_keymgr_key_derivation_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_keymgr_key_derivation_jitter_en.1727979616 |
| Directory | /workspace/2.chip_sw_keymgr_key_derivation_jitter_en/latest |
| Test location | /workspace/coverage/default/2.chip_sw_keymgr_key_derivation_jitter_en_reduced_freq.421993793 |
| Short name | T1203 |
| Test name | |
| Test status | |
| Simulation time | 9153258329 ps |
| CPU time | 1590.22 seconds |
| Started | Jun 29 08:01:10 PM PDT 24 |
| Finished | Jun 29 08:27:41 PM PDT 24 |
| Peak memory | 615716 kb |
| Host | smart-e3d058d4-a281-4040-bf7b-e0e4cbb167cf |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=20_000_000 +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=keymgr_key_derivation_test :1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=421993793 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_keymgr_key_derivation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_keymgr_key_derivation_jitter_en_ reduced_freq.421993793 |
| Directory | /workspace/2.chip_sw_keymgr_key_derivation_jitter_en_reduced_freq/latest |
| Test location | /workspace/coverage/default/2.chip_sw_keymgr_key_derivation_prod.1255850737 |
| Short name | T953 |
| Test name | |
| Test status | |
| Simulation time | 12808413224 ps |
| CPU time | 2547.76 seconds |
| Started | Jun 29 07:58:12 PM PDT 24 |
| Finished | Jun 29 08:40:40 PM PDT 24 |
| Peak memory | 615440 kb |
| Host | smart-e97a19ce-0509-42b1-8387-c56e1f6e6fba |
| User | root |
| Command | /workspace/default/simv +lc_at_prod=1 +sw_test_timeout_ns=20_000_000 +sw_build_device=sim_dv +sw_images=keymgr_key_derivation_test:1:new_rules,test_ro m:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=1255850737 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_keymgr_key_derivation_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_keymgr_key_derivation_prod.1255850737 |
| Directory | /workspace/2.chip_sw_keymgr_key_derivation_prod/latest |
| Test location | /workspace/coverage/default/2.chip_sw_keymgr_sideload_aes.2786029589 |
| Short name | T201 |
| Test name | |
| Test status | |
| Simulation time | 13016902910 ps |
| CPU time | 2312.37 seconds |
| Started | Jun 29 07:59:13 PM PDT 24 |
| Finished | Jun 29 08:37:47 PM PDT 24 |
| Peak memory | 609336 kb |
| Host | smart-d0445806-db3a-414b-98dd-a589beb8d6c4 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=20_000_000 +sw_build_device=sim_dv +sw_images=keymgr_sideload_aes_test:1:new_rules,test_rom:0 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=278602 9589 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_keymgr_sideload_aes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_keymgr_sideload_aes.2786029589 |
| Directory | /workspace/2.chip_sw_keymgr_sideload_aes/latest |
| Test location | /workspace/coverage/default/2.chip_sw_keymgr_sideload_kmac.2190850182 |
| Short name | T1169 |
| Test name | |
| Test status | |
| Simulation time | 9044750800 ps |
| CPU time | 2309.17 seconds |
| Started | Jun 29 07:58:23 PM PDT 24 |
| Finished | Jun 29 08:36:53 PM PDT 24 |
| Peak memory | 609264 kb |
| Host | smart-c2d34262-0924-4cd7-a816-1a72d5c56df7 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=20_000_000 +sw_build_device=sim_dv +sw_images=keymgr_sideload_kmac_test:1:new_rules,test_rom:0 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21908 50182 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_keymgr_sideload_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_keymgr_sideload_kmac.2190850182 |
| Directory | /workspace/2.chip_sw_keymgr_sideload_kmac/latest |
| Test location | /workspace/coverage/default/2.chip_sw_keymgr_sideload_otbn.218901923 |
| Short name | T207 |
| Test name | |
| Test status | |
| Simulation time | 10652281992 ps |
| CPU time | 3815.47 seconds |
| Started | Jun 29 08:00:30 PM PDT 24 |
| Finished | Jun 29 09:04:08 PM PDT 24 |
| Peak memory | 607616 kb |
| Host | smart-ba74ae87-1f72-4dcf-a94b-65d8d748c1e8 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=20_000_000 +sw_build_device=sim_dv +sw_images=keymgr_sideload_otbn_test:1:new_rules,test_rom:0 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21890 1923 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_keymgr_sideload_otbn.218901923 |
| Directory | /workspace/2.chip_sw_keymgr_sideload_otbn/latest |
| Test location | /workspace/coverage/default/2.chip_sw_kmac_app_rom.4134812589 |
| Short name | T384 |
| Test name | |
| Test status | |
| Simulation time | 2260109950 ps |
| CPU time | 246.57 seconds |
| Started | Jun 29 07:58:36 PM PDT 24 |
| Finished | Jun 29 08:02:43 PM PDT 24 |
| Peak memory | 607140 kb |
| Host | smart-cafff7bb-2609-4fde-a2c0-7b560b4d1a4b |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=kmac_app_rom_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4134812589 -assert nopostproc +UVM_TESTNAME= chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/ null -cm_name 2.chip_sw_kmac_app_rom.4134812589 |
| Directory | /workspace/2.chip_sw_kmac_app_rom/latest |
| Test location | /workspace/coverage/default/2.chip_sw_kmac_entropy.1276668525 |
| Short name | T1103 |
| Test name | |
| Test status | |
| Simulation time | 3230305400 ps |
| CPU time | 251.47 seconds |
| Started | Jun 29 07:54:22 PM PDT 24 |
| Finished | Jun 29 07:58:34 PM PDT 24 |
| Peak memory | 607256 kb |
| Host | smart-85eb3109-c512-4ee0-9897-83f8c9f88bec |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=kmac_entropy_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1276668525 -assert nopostproc +UVM_TESTNAME= chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/ null -cm_name 2.chip_sw_kmac_entropy.1276668525 |
| Directory | /workspace/2.chip_sw_kmac_entropy/latest |
| Test location | /workspace/coverage/default/2.chip_sw_kmac_idle.1421183399 |
| Short name | T845 |
| Test name | |
| Test status | |
| Simulation time | 3022681500 ps |
| CPU time | 224.53 seconds |
| Started | Jun 29 07:57:42 PM PDT 24 |
| Finished | Jun 29 08:01:27 PM PDT 24 |
| Peak memory | 607128 kb |
| Host | smart-ef5c8962-6435-452b-9ff3-8913d58e5cd0 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=kmac_idle_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1421183399 -assert nopostproc +UVM_TESTNAME=chi p_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul l -cm_name 2.chip_sw_kmac_idle.1421183399 |
| Directory | /workspace/2.chip_sw_kmac_idle/latest |
| Test location | /workspace/coverage/default/2.chip_sw_kmac_mode_cshake.3894944830 |
| Short name | T286 |
| Test name | |
| Test status | |
| Simulation time | 2846115816 ps |
| CPU time | 322.09 seconds |
| Started | Jun 29 07:58:25 PM PDT 24 |
| Finished | Jun 29 08:03:47 PM PDT 24 |
| Peak memory | 609160 kb |
| Host | smart-3e61eb10-052e-479a-a3eb-4efce72eecaa |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=kmac_mode_cshake_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3894944830 -assert nopostproc +UVM_TESTN AME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log / dev/null -cm_name 2.chip_sw_kmac_mode_cshake.3894944830 |
| Directory | /workspace/2.chip_sw_kmac_mode_cshake/latest |
| Test location | /workspace/coverage/default/2.chip_sw_kmac_mode_kmac.4156708056 |
| Short name | T1017 |
| Test name | |
| Test status | |
| Simulation time | 3341947320 ps |
| CPU time | 303.81 seconds |
| Started | Jun 29 08:00:16 PM PDT 24 |
| Finished | Jun 29 08:05:21 PM PDT 24 |
| Peak memory | 607300 kb |
| Host | smart-b5dc1486-d3b6-43ee-a516-edca39591ed2 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=kmac_mode_kmac_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4156708056 -assert nopostproc +UVM_TESTNAM E=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 2.chip_sw_kmac_mode_kmac.4156708056 |
| Directory | /workspace/2.chip_sw_kmac_mode_kmac/latest |
| Test location | /workspace/coverage/default/2.chip_sw_kmac_mode_kmac_jitter_en.3192139551 |
| Short name | T919 |
| Test name | |
| Test status | |
| Simulation time | 3200494663 ps |
| CPU time | 330.57 seconds |
| Started | Jun 29 07:58:54 PM PDT 24 |
| Finished | Jun 29 08:04:25 PM PDT 24 |
| Peak memory | 609192 kb |
| Host | smart-6898f68c-af84-489f-8ba6-4863368e10c3 |
| User | root |
| Command | /workspace/default/simv +en_jitter=1 +sw_build_device=sim_dv +sw_images=kmac_mode_kmac_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3192139551 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd b -cm_log /dev/null -cm_name 2.chip_sw_kmac_mode_kmac_jitter_en.3192139551 |
| Directory | /workspace/2.chip_sw_kmac_mode_kmac_jitter_en/latest |
| Test location | /workspace/coverage/default/2.chip_sw_kmac_mode_kmac_jitter_en_reduced_freq.1210559236 |
| Short name | T1214 |
| Test name | |
| Test status | |
| Simulation time | 3739966663 ps |
| CPU time | 316.3 seconds |
| Started | Jun 29 08:00:27 PM PDT 24 |
| Finished | Jun 29 08:05:44 PM PDT 24 |
| Peak memory | 609160 kb |
| Host | smart-ace7dc52-8cf6-431f-88cb-88040436a6c6 |
| User | root |
| Command | /workspace/default/simv +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=kmac_mode_kmac_test:1:new_rules,test_rom:0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12105592 36 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac e/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_kmac_mode_kmac_jitter_en_reduced_freq.1210559236 |
| Directory | /workspace/2.chip_sw_kmac_mode_kmac_jitter_en_reduced_freq/latest |
| Test location | /workspace/coverage/default/2.chip_sw_kmac_smoketest.1123022114 |
| Short name | T948 |
| Test name | |
| Test status | |
| Simulation time | 3307120934 ps |
| CPU time | 272.39 seconds |
| Started | Jun 29 08:02:49 PM PDT 24 |
| Finished | Jun 29 08:07:21 PM PDT 24 |
| Peak memory | 607312 kb |
| Host | smart-dae9bcbe-7f12-473f-8d99-14f0d31e7743 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=kmac_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1123022114 -assert nopostproc +UVM_TESTNAME=chi p_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul l -cm_name 2.chip_sw_kmac_smoketest.1123022114 |
| Directory | /workspace/2.chip_sw_kmac_smoketest/latest |
| Test location | /workspace/coverage/default/2.chip_sw_lc_ctrl_otp_hw_cfg0.952216866 |
| Short name | T1192 |
| Test name | |
| Test status | |
| Simulation time | 2735052270 ps |
| CPU time | 230.55 seconds |
| Started | Jun 29 07:55:27 PM PDT 24 |
| Finished | Jun 29 07:59:18 PM PDT 24 |
| Peak memory | 609180 kb |
| Host | smart-39ca13e1-d652-4543-b914-5e43ac3db82a |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=lc_ctrl_otp_hw_cfg0_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=952216866 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_lc_ctrl_otp_hw_cfg0.952216866 |
| Directory | /workspace/2.chip_sw_lc_ctrl_otp_hw_cfg0/latest |
| Test location | /workspace/coverage/default/2.chip_sw_lc_ctrl_program_error.3389152802 |
| Short name | T179 |
| Test name | |
| Test status | |
| Simulation time | 4997673008 ps |
| CPU time | 497.23 seconds |
| Started | Jun 29 07:59:55 PM PDT 24 |
| Finished | Jun 29 08:08:13 PM PDT 24 |
| Peak memory | 608724 kb |
| Host | smart-578c8850-de8a-4c70-a30a-75cdb823e0b7 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=lc_ctrl_program_error:1:new_rules,test_rom:0 + cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_ seed=3389152802 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_program_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_lc_ctrl_program_error.3389152802 |
| Directory | /workspace/2.chip_sw_lc_ctrl_program_error/latest |
| Test location | /workspace/coverage/default/2.chip_sw_lc_ctrl_rand_to_scrap.3236633686 |
| Short name | T649 |
| Test name | |
| Test status | |
| Simulation time | 2952555915 ps |
| CPU time | 151.17 seconds |
| Started | Jun 29 07:55:06 PM PDT 24 |
| Finished | Jun 29 07:57:38 PM PDT 24 |
| Peak memory | 617760 kb |
| Host | smart-1f3e7d6c-ae27-4164-9d02-702ed8ef5ea0 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=lc_ctrl_scrap_test:1:new_rules,test_rom:0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32366336 86 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_scrap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_lc_ctrl_rand_to_scrap.3236633686 |
| Directory | /workspace/2.chip_sw_lc_ctrl_rand_to_scrap/latest |
| Test location | /workspace/coverage/default/2.chip_sw_lc_ctrl_transition.375909665 |
| Short name | T428 |
| Test name | |
| Test status | |
| Simulation time | 6541951326 ps |
| CPU time | 449.84 seconds |
| Started | Jun 29 07:56:00 PM PDT 24 |
| Finished | Jun 29 08:03:30 PM PDT 24 |
| Peak memory | 619184 kb |
| Host | smart-97d127e5-6120-4b7f-bb07-d4c7060b036f |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=lc_ctrl_transition_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=375909665 -assert nopostproc +UVM_TEST NAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_transition_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul t.vdb -cm_log /dev/null -cm_name 2.chip_sw_lc_ctrl_transition.375909665 |
| Directory | /workspace/2.chip_sw_lc_ctrl_transition/latest |
| Test location | /workspace/coverage/default/2.chip_sw_lc_ctrl_volatile_raw_unlock.2522357017 |
| Short name | T173 |
| Test name | |
| Test status | |
| Simulation time | 1865984594 ps |
| CPU time | 117 seconds |
| Started | Jun 29 07:56:22 PM PDT 24 |
| Finished | Jun 29 07:58:19 PM PDT 24 |
| Peak memory | 615904 kb |
| Host | smart-2bdf03e8-ff65-4fcf-b486-14a334d26667 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStRaw +exp_volatile_raw_unlock_en=0 +sw_build_device=sim_dv +sw_images=lc_ctrl_volatile_raw_unlock_tes t:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/ tools/sim.tcl +ntb_random_seed=2522357017 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_volatile_raw_unlock_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_lc_ctrl_volatile_raw_unlock.2522357017 |
| Directory | /workspace/2.chip_sw_lc_ctrl_volatile_raw_unlock/latest |
| Test location | /workspace/coverage/default/2.chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz.3559852836 |
| Short name | T1263 |
| Test name | |
| Test status | |
| Simulation time | 1868693620 ps |
| CPU time | 98.24 seconds |
| Started | Jun 29 07:55:50 PM PDT 24 |
| Finished | Jun 29 07:57:29 PM PDT 24 |
| Peak memory | 614372 kb |
| Host | smart-2ab6bf25-ba25-48b8-a147-7a8aa9b56f43 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStRaw +chip_clock_source=ChipClockSourceExternal48Mhz +exp_volatile_raw_unlock_en=0 +sw_build_device=s im_dv +sw_images=lc_ctrl_volatile_raw_unlock_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3559852836 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TES T_SEQ=chip_sw_lc_volatile_raw_unlock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz.3559852836 |
| Directory | /workspace/2.chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz/latest |
| Test location | /workspace/coverage/default/2.chip_sw_lc_walkthrough_dev.285349702 |
| Short name | T208 |
| Test name | |
| Test status | |
| Simulation time | 49861733480 ps |
| CPU time | 5709.13 seconds |
| Started | Jun 29 07:55:50 PM PDT 24 |
| Finished | Jun 29 09:31:01 PM PDT 24 |
| Peak memory | 615044 kb |
| Host | smart-6a2c6265-5cc5-40ba-b8b6-58f924edd737 |
| User | root |
| Command | /workspace/default/simv +flash_program_latency=5 +use_otp_image=OtpTypeLcStRaw +dest_dec_state=DecLcStDev +sw_test_timeout_ns=200_000_000 +sw_build_de vice=sim_dv +sw_images=lc_walkthrough_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=285349702 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=ch ip_sw_lc_walkthrough_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_ sw_lc_walkthrough_dev.285349702 |
| Directory | /workspace/2.chip_sw_lc_walkthrough_dev/latest |
| Test location | /workspace/coverage/default/2.chip_sw_lc_walkthrough_prod.1372225322 |
| Short name | T1129 |
| Test name | |
| Test status | |
| Simulation time | 51157662087 ps |
| CPU time | 5370.35 seconds |
| Started | Jun 29 07:56:46 PM PDT 24 |
| Finished | Jun 29 09:26:17 PM PDT 24 |
| Peak memory | 615028 kb |
| Host | smart-aaf67738-a11e-49dc-9f0c-84a915562f98 |
| User | root |
| Command | /workspace/default/simv +flash_program_latency=5 +use_otp_image=OtpTypeLcStRaw +dest_dec_state=DecLcStProd +sw_test_timeout_ns=200_000_000 +sw_build_d evice=sim_dv +sw_images=lc_walkthrough_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1372225322 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ= chip_sw_lc_walkthrough_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chi p_sw_lc_walkthrough_prod.1372225322 |
| Directory | /workspace/2.chip_sw_lc_walkthrough_prod/latest |
| Test location | /workspace/coverage/default/2.chip_sw_lc_walkthrough_prodend.136763417 |
| Short name | T893 |
| Test name | |
| Test status | |
| Simulation time | 8998584168 ps |
| CPU time | 1011.33 seconds |
| Started | Jun 29 07:56:19 PM PDT 24 |
| Finished | Jun 29 08:13:11 PM PDT 24 |
| Peak memory | 614916 kb |
| Host | smart-9ad0e42b-8d49-4c3c-9c99-71e0a2911304 |
| User | root |
| Command | /workspace/default/simv +flash_program_latency=5 +use_otp_image=OtpTypeLcStRaw +dest_dec_state=DecLcStProdEnd +sw_build_device=sim_dv +sw_images=lc_wa lkthrough_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=136763417 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_walkthrough_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_lc_walkthrough_prodend.136763417 |
| Directory | /workspace/2.chip_sw_lc_walkthrough_prodend/latest |
| Test location | /workspace/coverage/default/2.chip_sw_lc_walkthrough_rma.1591214181 |
| Short name | T1217 |
| Test name | |
| Test status | |
| Simulation time | 45178325596 ps |
| CPU time | 5207.24 seconds |
| Started | Jun 29 07:56:14 PM PDT 24 |
| Finished | Jun 29 09:23:03 PM PDT 24 |
| Peak memory | 617104 kb |
| Host | smart-07f943d7-eaf7-4dc5-95f2-7a10329d79f0 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStRaw +dest_dec_state=DecLcStRma +flash_program_latency=5 +sw_test_timeout_ns=200_000_000 +sw_build_de vice=sim_dv +sw_images=lc_walkthrough_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1591214181 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=c hip_sw_lc_walkthrough_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip _sw_lc_walkthrough_rma.1591214181 |
| Directory | /workspace/2.chip_sw_lc_walkthrough_rma/latest |
| Test location | /workspace/coverage/default/2.chip_sw_otbn_ecdsa_op_irq.1236736679 |
| Short name | T867 |
| Test name | |
| Test status | |
| Simulation time | 17650515012 ps |
| CPU time | 3937.59 seconds |
| Started | Jun 29 07:57:07 PM PDT 24 |
| Finished | Jun 29 09:02:45 PM PDT 24 |
| Peak memory | 607256 kb |
| Host | smart-0a7f5ce4-7c1b-4711-bcb9-ef15287dbfa0 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=28_000_000 +rng_srate_value=30 +sw_build_device=sim_dv +sw_images=otbn_ecdsa_op_irq_test:1:new_rules,test_ rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ random_seed=1236736679 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_otbn_ecdsa_op_irq.1236736679 |
| Directory | /workspace/2.chip_sw_otbn_ecdsa_op_irq/latest |
| Test location | /workspace/coverage/default/2.chip_sw_otbn_ecdsa_op_irq_jitter_en.332579503 |
| Short name | T1011 |
| Test name | |
| Test status | |
| Simulation time | 18252944301 ps |
| CPU time | 4367.45 seconds |
| Started | Jun 29 07:57:12 PM PDT 24 |
| Finished | Jun 29 09:10:00 PM PDT 24 |
| Peak memory | 609304 kb |
| Host | smart-e4404293-4afe-4939-b208-4cd42d960c2d |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=33_000_000 +rng_srate_value=30 +en_jitter=1 +sw_build_device=sim_dv +sw_images=otbn_ecdsa_op_irq_test:1:ne w_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/ sim.tcl +ntb_random_seed=332579503 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_otbn_ecdsa_op_irq_jitter_en.332579503 |
| Directory | /workspace/2.chip_sw_otbn_ecdsa_op_irq_jitter_en/latest |
| Test location | /workspace/coverage/default/2.chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq.709018643 |
| Short name | T447 |
| Test name | |
| Test status | |
| Simulation time | 24580483181 ps |
| CPU time | 4295.86 seconds |
| Started | Jun 29 08:01:51 PM PDT 24 |
| Finished | Jun 29 09:13:27 PM PDT 24 |
| Peak memory | 609296 kb |
| Host | smart-ec6c18c8-9749-4850-97a8-98cc3e1a0fc5 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=33_000_000 +rng_srate_value=30 +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=otbn_e cdsa_op_irq_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/ repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=709018643 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_otbn_ecdsa_op_irq_jitter_en_reduc ed_freq.709018643 |
| Directory | /workspace/2.chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq/latest |
| Test location | /workspace/coverage/default/2.chip_sw_otbn_mem_scramble.27179138 |
| Short name | T1198 |
| Test name | |
| Test status | |
| Simulation time | 3942856440 ps |
| CPU time | 580.45 seconds |
| Started | Jun 29 07:59:02 PM PDT 24 |
| Finished | Jun 29 08:08:43 PM PDT 24 |
| Peak memory | 607704 kb |
| Host | smart-1b8f100e-24a8-4808-9693-25861188bf14 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=15_000_000 +en_scb_tl_err_chk=0 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=otbn _mem_scramble_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27179138 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_otbn_mem_scramble.27179138 |
| Directory | /workspace/2.chip_sw_otbn_mem_scramble/latest |
| Test location | /workspace/coverage/default/2.chip_sw_otbn_randomness.1048411742 |
| Short name | T862 |
| Test name | |
| Test status | |
| Simulation time | 6255255460 ps |
| CPU time | 1066.28 seconds |
| Started | Jun 29 07:57:28 PM PDT 24 |
| Finished | Jun 29 08:15:15 PM PDT 24 |
| Peak memory | 609388 kb |
| Host | smart-c2ff46d3-6389-4bf4-bfc7-5431be38e1da |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +rng_srate_value=30 +sw_build_device=sim_dv +sw_images=otbn_randomness_test:1:new_rules,test_ro m:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=1048411742 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_otbn_randomness.1048411742 |
| Directory | /workspace/2.chip_sw_otbn_randomness/latest |
| Test location | /workspace/coverage/default/2.chip_sw_otbn_smoketest.313582828 |
| Short name | T396 |
| Test name | |
| Test status | |
| Simulation time | 10778424956 ps |
| CPU time | 2241.51 seconds |
| Started | Jun 29 08:02:19 PM PDT 24 |
| Finished | Jun 29 08:39:41 PM PDT 24 |
| Peak memory | 607256 kb |
| Host | smart-2c5752b5-e9a5-4470-b67b-01b007e35e34 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=otbn_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=313582828 -assert nopostproc +UVM_TESTNAME=chip _base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_otbn_smoketest.313582828 |
| Directory | /workspace/2.chip_sw_otbn_smoketest/latest |
| Test location | /workspace/coverage/default/2.chip_sw_otp_ctrl_ecc_error_vendor_test.2419763105 |
| Short name | T1088 |
| Test name | |
| Test status | |
| Simulation time | 2616320842 ps |
| CPU time | 397.28 seconds |
| Started | Jun 29 07:55:47 PM PDT 24 |
| Finished | Jun 29 08:02:25 PM PDT 24 |
| Peak memory | 609464 kb |
| Host | smart-8c1f3023-d7d8-4a99-a425-96855e8280b5 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=otp_ctrl_vendor_test_ecc_error_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2419763105 -assert nopostp roc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_otp_ctrl_vendor_test_ecc_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_otp_ctrl_ecc_error_vendor_test.2419763105 |
| Directory | /workspace/2.chip_sw_otp_ctrl_ecc_error_vendor_test/latest |
| Test location | /workspace/coverage/default/2.chip_sw_otp_ctrl_lc_signals_dev.840207986 |
| Short name | T200 |
| Test name | |
| Test status | |
| Simulation time | 6300458718 ps |
| CPU time | 1021.95 seconds |
| Started | Jun 29 07:54:48 PM PDT 24 |
| Finished | Jun 29 08:11:50 PM PDT 24 |
| Peak memory | 608204 kb |
| Host | smart-00701ab8-ca0b-4e6a-bffc-fb689b27f310 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStDev +otp_clear_secret2=1 +sw_build_device=sim_dv +sw_images=otp_ctrl_lc_signals_test:1:new_rules,tes t_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +nt b_random_seed=840207986 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_otp_ctrl_lc_signals_dev.840207986 |
| Directory | /workspace/2.chip_sw_otp_ctrl_lc_signals_dev/latest |
| Test location | /workspace/coverage/default/2.chip_sw_otp_ctrl_lc_signals_prod.935202630 |
| Short name | T1014 |
| Test name | |
| Test status | |
| Simulation time | 6817414634 ps |
| CPU time | 1156.04 seconds |
| Started | Jun 29 07:56:26 PM PDT 24 |
| Finished | Jun 29 08:15:43 PM PDT 24 |
| Peak memory | 609184 kb |
| Host | smart-2251ec28-b688-422e-9d68-62eb58bd6408 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStProd +otp_clear_secret2=1 +sw_build_device=sim_dv +sw_images=otp_ctrl_lc_signals_test:1:new_rules,te st_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n tb_random_seed=935202630 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_otp_ctrl_lc_signals_prod.935202630 |
| Directory | /workspace/2.chip_sw_otp_ctrl_lc_signals_prod/latest |
| Test location | /workspace/coverage/default/2.chip_sw_otp_ctrl_lc_signals_rma.2184091032 |
| Short name | T939 |
| Test name | |
| Test status | |
| Simulation time | 8072239484 ps |
| CPU time | 1239.25 seconds |
| Started | Jun 29 07:55:26 PM PDT 24 |
| Finished | Jun 29 08:16:05 PM PDT 24 |
| Peak memory | 608224 kb |
| Host | smart-7528d133-85be-4034-a634-7b04dff8922d |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStRma +otp_clear_secret2=1 +sw_build_device=sim_dv +sw_images=otp_ctrl_lc_signals_test:1:new_rules,tes t_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +nt b_random_seed=2184091032 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_otp_ctrl_lc_signals_rma.2184091032 |
| Directory | /workspace/2.chip_sw_otp_ctrl_lc_signals_rma/latest |
| Test location | /workspace/coverage/default/2.chip_sw_otp_ctrl_lc_signals_test_unlocked0.1018315421 |
| Short name | T985 |
| Test name | |
| Test status | |
| Simulation time | 4390612084 ps |
| CPU time | 761.67 seconds |
| Started | Jun 29 07:54:42 PM PDT 24 |
| Finished | Jun 29 08:07:24 PM PDT 24 |
| Peak memory | 609180 kb |
| Host | smart-8ad0ce22-4073-40b0-b1ba-65a1002a124e |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStTestUnlocked0 +otp_clear_secret2=1 +sw_build_device=sim_dv +sw_images=otp_ctrl_lc_signals_test:1:new _rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/s im.tcl +ntb_random_seed=1018315421 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_otp_ctrl_lc_signals_test_unlocked0.1018315421 |
| Directory | /workspace/2.chip_sw_otp_ctrl_lc_signals_test_unlocked0/latest |
| Test location | /workspace/coverage/default/2.chip_sw_otp_ctrl_smoketest.3336085214 |
| Short name | T1130 |
| Test name | |
| Test status | |
| Simulation time | 2461096846 ps |
| CPU time | 191.76 seconds |
| Started | Jun 29 08:04:01 PM PDT 24 |
| Finished | Jun 29 08:07:13 PM PDT 24 |
| Peak memory | 609192 kb |
| Host | smart-8cf5ee61-e654-4176-88c4-638b2f7ace5d |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=otp_ctrl_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3336085214 -assert nopostproc +UVM_TESTNAME =chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 2.chip_sw_otp_ctrl_smoketest.3336085214 |
| Directory | /workspace/2.chip_sw_otp_ctrl_smoketest/latest |
| Test location | /workspace/coverage/default/2.chip_sw_pattgen_ios.560934222 |
| Short name | T332 |
| Test name | |
| Test status | |
| Simulation time | 3151910192 ps |
| CPU time | 344.29 seconds |
| Started | Jun 29 07:53:10 PM PDT 24 |
| Finished | Jun 29 07:58:55 PM PDT 24 |
| Peak memory | 609244 kb |
| Host | smart-0980b4ac-d4e0-4ea9-9c0e-06a95c8739ed |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=5_000_000 +sw_build_device=sim_dv +sw_images=pattgen_ios_test:1:new_rules,test_rom:0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=560934222 -asse rt nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_patt_ios_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co verage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pattgen_ios.560934222 |
| Directory | /workspace/2.chip_sw_pattgen_ios/latest |
| Test location | /workspace/coverage/default/2.chip_sw_plic_sw_irq.810675297 |
| Short name | T660 |
| Test name | |
| Test status | |
| Simulation time | 3033467468 ps |
| CPU time | 373.86 seconds |
| Started | Jun 29 08:00:45 PM PDT 24 |
| Finished | Jun 29 08:06:59 PM PDT 24 |
| Peak memory | 606360 kb |
| Host | smart-95a8f9d0-9552-4683-ae94-f7c2ee4269ad |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=plic_sw_irq_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=810675297 -assert nopostproc +UVM_TESTNAME=ch ip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu ll -cm_name 2.chip_sw_plic_sw_irq.810675297 |
| Directory | /workspace/2.chip_sw_plic_sw_irq/latest |
| Test location | /workspace/coverage/default/2.chip_sw_power_idle_load.1186505461 |
| Short name | T852 |
| Test name | |
| Test status | |
| Simulation time | 3767496000 ps |
| CPU time | 738.8 seconds |
| Started | Jun 29 08:00:44 PM PDT 24 |
| Finished | Jun 29 08:13:04 PM PDT 24 |
| Peak memory | 607640 kb |
| Host | smart-077db288-17f0-4ebf-be61-914f4ee7bc1a |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=chip_power_idle_load:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1186505461 -assert nopostproc +UVM_TESTNA ME=chip_base_test +UVM_TEST_SEQ=chip_sw_power_idle_load_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_power_idle_load.1186505461 |
| Directory | /workspace/2.chip_sw_power_idle_load/latest |
| Test location | /workspace/coverage/default/2.chip_sw_power_sleep_load.2577475709 |
| Short name | T105 |
| Test name | |
| Test status | |
| Simulation time | 5335878078 ps |
| CPU time | 498.08 seconds |
| Started | Jun 29 08:02:38 PM PDT 24 |
| Finished | Jun 29 08:10:57 PM PDT 24 |
| Peak memory | 608196 kb |
| Host | smart-b475012d-af0b-47f6-a00d-c595c404c75e |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=chip_power_sleep_load:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2577475709 -assert nopostproc +UVM_TESTN AME=chip_base_test +UVM_TEST_SEQ=chip_sw_power_sleep_load_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v db -cm_log /dev/null -cm_name 2.chip_sw_power_sleep_load.2577475709 |
| Directory | /workspace/2.chip_sw_power_sleep_load/latest |
| Test location | /workspace/coverage/default/2.chip_sw_pwrmgr_all_reset_reqs.439436600 |
| Short name | T854 |
| Test name | |
| Test status | |
| Simulation time | 10731853659 ps |
| CPU time | 1525.05 seconds |
| Started | Jun 29 07:56:47 PM PDT 24 |
| Finished | Jun 29 08:22:13 PM PDT 24 |
| Peak memory | 609392 kb |
| Host | smart-4cff8da8-5afb-4ecc-9a55-6000f34ec6cb |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=50_000_000 +sw_build_device=sim_dv +sw_images=pwrmgr_all_reset_reqs_test:1:new_rules,test_rom:0 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4394 36600 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_deep_sleep_all_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_all_reset_reqs.439436600 |
| Directory | /workspace/2.chip_sw_pwrmgr_all_reset_reqs/latest |
| Test location | /workspace/coverage/default/2.chip_sw_pwrmgr_b2b_sleep_reset_req.2231485398 |
| Short name | T1003 |
| Test name | |
| Test status | |
| Simulation time | 23910745544 ps |
| CPU time | 2157.02 seconds |
| Started | Jun 29 07:59:04 PM PDT 24 |
| Finished | Jun 29 08:35:01 PM PDT 24 |
| Peak memory | 608360 kb |
| Host | smart-c561c059-2d98-4163-9b18-b0e26e541125 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=35_000_000 +sw_build_device=sim_dv +sw_images=pwrmgr_b2b_sleep_reset_test:1:new_rules,test_rom:0 +cdc_inst rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=223 1485398 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_repeat_reset_wkup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_b2b_sleep_reset_req.2231485398 |
| Directory | /workspace/2.chip_sw_pwrmgr_b2b_sleep_reset_req/latest |
| Test location | /workspace/coverage/default/2.chip_sw_pwrmgr_deep_sleep_all_reset_reqs.2963213334 |
| Short name | T195 |
| Test name | |
| Test status | |
| Simulation time | 16139041602 ps |
| CPU time | 1759.97 seconds |
| Started | Jun 29 07:57:30 PM PDT 24 |
| Finished | Jun 29 08:26:50 PM PDT 24 |
| Peak memory | 609368 kb |
| Host | smart-936da720-6dcf-42da-b9eb-ca94a48fe211 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=50_000_000 +sw_build_device=sim_dv +sw_images=pwrmgr_deep_sleep_all_reset_reqs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=2963213334 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_deep_sleep_all_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_deep_sleep_all_reset_reqs.2963213334 |
| Directory | /workspace/2.chip_sw_pwrmgr_deep_sleep_all_reset_reqs/latest |
| Test location | /workspace/coverage/default/2.chip_sw_pwrmgr_deep_sleep_all_wake_ups.2465529821 |
| Short name | T93 |
| Test name | |
| Test status | |
| Simulation time | 26579653710 ps |
| CPU time | 1617.11 seconds |
| Started | Jun 29 08:00:47 PM PDT 24 |
| Finished | Jun 29 08:27:44 PM PDT 24 |
| Peak memory | 608716 kb |
| Host | smart-65649568-bc81-409d-be80-88c378e357b8 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=pwrmgr_deep_sleep_all_wake_ups:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 2465529821 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_pwrmgr_deep_sleep_all_wake_ups_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_deep_sleep_all_wake_ups.2465529821 |
| Directory | /workspace/2.chip_sw_pwrmgr_deep_sleep_all_wake_ups/latest |
| Test location | /workspace/coverage/default/2.chip_sw_pwrmgr_deep_sleep_por_reset.4261190233 |
| Short name | T881 |
| Test name | |
| Test status | |
| Simulation time | 8211481320 ps |
| CPU time | 524 seconds |
| Started | Jun 29 07:56:31 PM PDT 24 |
| Finished | Jun 29 08:05:15 PM PDT 24 |
| Peak memory | 609180 kb |
| Host | smart-a248979b-a3f2-45c8-8d28-e5f241f97cbe |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_deep_sleep_por_reset_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4261190233 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sleep_por_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage /default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_deep_sleep_por_reset.4261190233 |
| Directory | /workspace/2.chip_sw_pwrmgr_deep_sleep_por_reset/latest |
| Test location | /workspace/coverage/default/2.chip_sw_pwrmgr_deep_sleep_power_glitch_reset.1376925114 |
| Short name | T392 |
| Test name | |
| Test status | |
| Simulation time | 6563982374 ps |
| CPU time | 413.4 seconds |
| Started | Jun 29 07:55:39 PM PDT 24 |
| Finished | Jun 29 08:02:34 PM PDT 24 |
| Peak memory | 614812 kb |
| Host | smart-e8b94a76-3d49-4c21-a74a-0aed974b1320 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=pwrmgr_deep_sleep_power_glitch_test:1:new_rules,test_rom :0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=1376925114 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_deep_power_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_deep_sleep_power_glitch_reset.1376925114 |
| Directory | /workspace/2.chip_sw_pwrmgr_deep_sleep_power_glitch_reset/latest |
| Test location | /workspace/coverage/default/2.chip_sw_pwrmgr_full_aon_reset.1499065909 |
| Short name | T133 |
| Test name | |
| Test status | |
| Simulation time | 9294356252 ps |
| CPU time | 777.83 seconds |
| Started | Jun 29 07:56:26 PM PDT 24 |
| Finished | Jun 29 08:09:24 PM PDT 24 |
| Peak memory | 608256 kb |
| Host | smart-c743605a-b3f0-4d2c-827f-cd9667799cc6 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=rstmgr_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1499065909 -assert nopostproc +UVM_TESTNAME=c hip_base_test +UVM_TEST_SEQ=chip_sw_full_aon_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_ log /dev/null -cm_name 2.chip_sw_pwrmgr_full_aon_reset.1499065909 |
| Directory | /workspace/2.chip_sw_pwrmgr_full_aon_reset/latest |
| Test location | /workspace/coverage/default/2.chip_sw_pwrmgr_lowpower_cancel.212931096 |
| Short name | T313 |
| Test name | |
| Test status | |
| Simulation time | 4202535412 ps |
| CPU time | 435.21 seconds |
| Started | Jun 29 08:00:11 PM PDT 24 |
| Finished | Jun 29 08:07:27 PM PDT 24 |
| Peak memory | 609228 kb |
| Host | smart-d79043a4-b1a0-4df1-b67a-7be18b999ad6 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_lowpower_cancel_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=212931096 -assert nopostproc +UVM_ TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_ log /dev/null -cm_name 2.chip_sw_pwrmgr_lowpower_cancel.212931096 |
| Directory | /workspace/2.chip_sw_pwrmgr_lowpower_cancel/latest |
| Test location | /workspace/coverage/default/2.chip_sw_pwrmgr_main_power_glitch_reset.4075455375 |
| Short name | T276 |
| Test name | |
| Test status | |
| Simulation time | 4184201148 ps |
| CPU time | 456.12 seconds |
| Started | Jun 29 07:55:58 PM PDT 24 |
| Finished | Jun 29 08:03:35 PM PDT 24 |
| Peak memory | 614768 kb |
| Host | smart-6befcb16-0efc-4bb0-a01e-a19de60df63b |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=pwrmgr_main_power_glitch_test:1:new_rules,test_rom:0 +cd c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se ed=4075455375 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_main_power_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_main_power_glitch_reset.4075455375 |
| Directory | /workspace/2.chip_sw_pwrmgr_main_power_glitch_reset/latest |
| Test location | /workspace/coverage/default/2.chip_sw_pwrmgr_normal_sleep_all_reset_reqs.1253507479 |
| Short name | T954 |
| Test name | |
| Test status | |
| Simulation time | 13053965214 ps |
| CPU time | 1397.35 seconds |
| Started | Jun 29 07:56:19 PM PDT 24 |
| Finished | Jun 29 08:19:37 PM PDT 24 |
| Peak memory | 609000 kb |
| Host | smart-14beba14-52ae-4ab6-8214-fb54fddc773f |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_normal_sleep_all_reset_reqs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1253507479 -assert nop ostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_deep_sleep_all_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_normal_sleep_all_reset_reqs.1253507479 |
| Directory | /workspace/2.chip_sw_pwrmgr_normal_sleep_all_reset_reqs/latest |
| Test location | /workspace/coverage/default/2.chip_sw_pwrmgr_normal_sleep_all_wake_ups.3119156158 |
| Short name | T94 |
| Test name | |
| Test status | |
| Simulation time | 7740923288 ps |
| CPU time | 446.21 seconds |
| Started | Jun 29 08:01:38 PM PDT 24 |
| Finished | Jun 29 08:09:04 PM PDT 24 |
| Peak memory | 608236 kb |
| Host | smart-c6d479d8-64ee-458a-a7ff-6098c67a64fe |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_normal_sleep_all_wake_ups:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3119156158 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_pwrmgr_deep_sleep_all_wake_ups_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_normal_sleep_all_wake_ups.3119156158 |
| Directory | /workspace/2.chip_sw_pwrmgr_normal_sleep_all_wake_ups/latest |
| Test location | /workspace/coverage/default/2.chip_sw_pwrmgr_normal_sleep_por_reset.3487962336 |
| Short name | T832 |
| Test name | |
| Test status | |
| Simulation time | 6583976521 ps |
| CPU time | 726.33 seconds |
| Started | Jun 29 07:57:41 PM PDT 24 |
| Finished | Jun 29 08:09:48 PM PDT 24 |
| Peak memory | 609272 kb |
| Host | smart-16eb8551-6725-488c-b2a2-53216dae8ba8 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_normal_sleep_por_reset_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3487962336 -assert nopostpr oc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sleep_por_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera ge/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_normal_sleep_por_reset.3487962336 |
| Directory | /workspace/2.chip_sw_pwrmgr_normal_sleep_por_reset/latest |
| Test location | /workspace/coverage/default/2.chip_sw_pwrmgr_random_sleep_all_reset_reqs.3686231423 |
| Short name | T979 |
| Test name | |
| Test status | |
| Simulation time | 20416006297 ps |
| CPU time | 2040.88 seconds |
| Started | Jun 29 07:56:40 PM PDT 24 |
| Finished | Jun 29 08:30:42 PM PDT 24 |
| Peak memory | 609192 kb |
| Host | smart-697676d7-ac49-4ab7-ad2c-d3bfa180dff8 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=50_000_000 +sw_build_device=sim_dv +sw_images=pwrmgr_random_sleep_all_reset_reqs_test:1:new_rules,test_rom :0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=3686231423 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_deep_sleep_all_reset_vseq +en_cov=1 -cm line+cond+fsm+tg l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_random_sleep_all_reset_reqs.3686231423 |
| Directory | /workspace/2.chip_sw_pwrmgr_random_sleep_all_reset_reqs/latest |
| Test location | /workspace/coverage/default/2.chip_sw_pwrmgr_random_sleep_all_wake_ups.3725387851 |
| Short name | T3 |
| Test name | |
| Test status | |
| Simulation time | 23679196644 ps |
| CPU time | 1965.81 seconds |
| Started | Jun 29 08:02:51 PM PDT 24 |
| Finished | Jun 29 08:35:37 PM PDT 24 |
| Peak memory | 608704 kb |
| Host | smart-9b2fcfe7-d80c-443d-86ae-e882be51a512 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +do_random=1 +sw_build_device=sim_dv +sw_images=pwrmgr_random_sleep_all_wake_ups:1:new_rules,te st_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n tb_random_seed=3725387851 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_pwrmgr_deep_sleep_all_wake_ups_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_random_sleep_all_wake_ups.3725387851 |
| Directory | /workspace/2.chip_sw_pwrmgr_random_sleep_all_wake_ups/latest |
| Test location | /workspace/coverage/default/2.chip_sw_pwrmgr_random_sleep_power_glitch_reset.984951110 |
| Short name | T950 |
| Test name | |
| Test status | |
| Simulation time | 34162950588 ps |
| CPU time | 3498.39 seconds |
| Started | Jun 29 07:57:58 PM PDT 24 |
| Finished | Jun 29 08:56:17 PM PDT 24 |
| Peak memory | 609864 kb |
| Host | smart-b5cff7d4-918d-4d68-ab40-6cf179bfbb11 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_test_timeout_ns=24_000_000 +sw_build_device=sim_dv +sw_images=pwrmgr_random_sleep_power _glitch_reset_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=984951110 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_random_power_glitc h_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_random_sl eep_power_glitch_reset.984951110 |
| Directory | /workspace/2.chip_sw_pwrmgr_random_sleep_power_glitch_reset/latest |
| Test location | /workspace/coverage/default/2.chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up.1697098458 |
| Short name | T132 |
| Test name | |
| Test status | |
| Simulation time | 5007543540 ps |
| CPU time | 383.13 seconds |
| Started | Jun 29 08:01:27 PM PDT 24 |
| Finished | Jun 29 08:07:51 PM PDT 24 |
| Peak memory | 609284 kb |
| Host | smart-5bf10bdf-5efc-4eae-9a83-6129ce590f8c |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +do_random=1 +sw_build_device=sim_dv +sw_images=pwrmgr_sensor_ctrl_deep_sleep_wake_up:1:new_rul es,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t cl +ntb_random_seed=1697098458 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_sensor_ctrl_deep_s leep_wake_up.1697098458 |
| Directory | /workspace/2.chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up/latest |
| Test location | /workspace/coverage/default/2.chip_sw_pwrmgr_sleep_disabled.3471929669 |
| Short name | T658 |
| Test name | |
| Test status | |
| Simulation time | 3496173228 ps |
| CPU time | 316.92 seconds |
| Started | Jun 29 07:56:34 PM PDT 24 |
| Finished | Jun 29 08:01:51 PM PDT 24 |
| Peak memory | 609188 kb |
| Host | smart-3c308a3f-1599-40c2-87cb-7fd8b6acf278 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_sleep_disabled_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3471929669 -assert nopostproc +UVM_ TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_ log /dev/null -cm_name 2.chip_sw_pwrmgr_sleep_disabled.3471929669 |
| Directory | /workspace/2.chip_sw_pwrmgr_sleep_disabled/latest |
| Test location | /workspace/coverage/default/2.chip_sw_pwrmgr_sleep_power_glitch_reset.2572729323 |
| Short name | T1275 |
| Test name | |
| Test status | |
| Simulation time | 6011834222 ps |
| CPU time | 559.68 seconds |
| Started | Jun 29 07:56:49 PM PDT 24 |
| Finished | Jun 29 08:06:09 PM PDT 24 |
| Peak memory | 615536 kb |
| Host | smart-6cf08d8f-f443-4c72-8a49-3a583fff6605 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=pwrmgr_sleep_power_glitch_test:1:new_rules,test_rom:0 +c dc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_s eed=2572729323 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_main_power_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_sleep_power_glitch_reset.2572729323 |
| Directory | /workspace/2.chip_sw_pwrmgr_sleep_power_glitch_reset/latest |
| Test location | /workspace/coverage/default/2.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup.2307998600 |
| Short name | T122 |
| Test name | |
| Test status | |
| Simulation time | 5384057260 ps |
| CPU time | 514.82 seconds |
| Started | Jun 29 08:00:19 PM PDT 24 |
| Finished | Jun 29 08:08:55 PM PDT 24 |
| Peak memory | 609224 kb |
| Host | smart-d0127814-fa5b-4f04-bf7f-a452690b5862 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=8_000_000 +sw_build_device=sim_dv +sw_images=sensor_ctrl_wakeup_test:1:new_rules,test_rom:0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23079986 00 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac e/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup.2307998600 |
| Directory | /workspace/2.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup/latest |
| Test location | /workspace/coverage/default/2.chip_sw_pwrmgr_sleep_wake_5_bug.4235077179 |
| Short name | T118 |
| Test name | |
| Test status | |
| Simulation time | 6068935184 ps |
| CPU time | 566.3 seconds |
| Started | Jun 29 08:02:49 PM PDT 24 |
| Finished | Jun 29 08:12:16 PM PDT 24 |
| Peak memory | 608428 kb |
| Host | smart-55829b3e-8132-4102-abc7-fcb03ee25719 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +do_random=1 +sw_build_device=sim_dv +sw_images=pwrmgr_sleep_wake_5_bug_test:1:new_rules,test_r om:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r andom_seed=4235077179 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_sleep_wake_5_bug.4235077179 |
| Directory | /workspace/2.chip_sw_pwrmgr_sleep_wake_5_bug/latest |
| Test location | /workspace/coverage/default/2.chip_sw_pwrmgr_smoketest.1053483522 |
| Short name | T1004 |
| Test name | |
| Test status | |
| Simulation time | 6549460616 ps |
| CPU time | 534.12 seconds |
| Started | Jun 29 08:03:00 PM PDT 24 |
| Finished | Jun 29 08:11:54 PM PDT 24 |
| Peak memory | 609220 kb |
| Host | smart-99ff6f93-4719-41e2-8470-aa98e4592e07 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=10000000 +sw_build_device=sim_dv +sw_images=pwrmgr_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1053483522 -asse rt nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera ge/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_smoketest.1053483522 |
| Directory | /workspace/2.chip_sw_pwrmgr_smoketest/latest |
| Test location | /workspace/coverage/default/2.chip_sw_pwrmgr_sysrst_ctrl_reset.687793053 |
| Short name | T865 |
| Test name | |
| Test status | |
| Simulation time | 7063409287 ps |
| CPU time | 1236.72 seconds |
| Started | Jun 29 07:56:03 PM PDT 24 |
| Finished | Jun 29 08:16:41 PM PDT 24 |
| Peak memory | 608292 kb |
| Host | smart-b81eb6da-0bfa-49fd-ad4f-6ea33726e2c1 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_sysrst_ctrl_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=687793053 -assert nopostproc +UVM_TEST NAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb - cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_sysrst_ctrl_reset.687793053 |
| Directory | /workspace/2.chip_sw_pwrmgr_sysrst_ctrl_reset/latest |
| Test location | /workspace/coverage/default/2.chip_sw_pwrmgr_usb_clk_disabled_when_active.2766223248 |
| Short name | T1075 |
| Test name | |
| Test status | |
| Simulation time | 4409658100 ps |
| CPU time | 556.22 seconds |
| Started | Jun 29 07:57:43 PM PDT 24 |
| Finished | Jun 29 08:07:00 PM PDT 24 |
| Peak memory | 609208 kb |
| Host | smart-b0f63cd9-747f-4727-8805-4cc4f8fa05d7 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_usb_clk_disabled_when_active_test:1:new_rules,test_rom:0 +cdc_instrumentation_enable d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2766223248 -assert no postproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de fault.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_usb_clk_disabled_when_active.2766223248 |
| Directory | /workspace/2.chip_sw_pwrmgr_usb_clk_disabled_when_active/latest |
| Test location | /workspace/coverage/default/2.chip_sw_pwrmgr_usbdev_smoketest.1079743136 |
| Short name | T382 |
| Test name | |
| Test status | |
| Simulation time | 6328837898 ps |
| CPU time | 447.46 seconds |
| Started | Jun 29 08:03:58 PM PDT 24 |
| Finished | Jun 29 08:11:27 PM PDT 24 |
| Peak memory | 609252 kb |
| Host | smart-4d75c56e-0935-4cdc-b927-1a23c437ad98 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_usbdev_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1079743136 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_usbdev_smoketest.1079743136 |
| Directory | /workspace/2.chip_sw_pwrmgr_usbdev_smoketest/latest |
| Test location | /workspace/coverage/default/2.chip_sw_pwrmgr_wdog_reset.1065907020 |
| Short name | T873 |
| Test name | |
| Test status | |
| Simulation time | 4664587856 ps |
| CPU time | 801.54 seconds |
| Started | Jun 29 07:58:02 PM PDT 24 |
| Finished | Jun 29 08:11:24 PM PDT 24 |
| Peak memory | 608204 kb |
| Host | smart-5e2d704a-a72d-44e0-8fb7-74d2b05f7924 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=pwrmgr_wdog_reset_reqs_test:1:new_rules,test_rom:0 +cdc_inst rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=106 5907020 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_wdog_reset.1065907020 |
| Directory | /workspace/2.chip_sw_pwrmgr_wdog_reset/latest |
| Test location | /workspace/coverage/default/2.chip_sw_rom_ctrl_integrity_check.492826557 |
| Short name | T383 |
| Test name | |
| Test status | |
| Simulation time | 9641994326 ps |
| CPU time | 471.29 seconds |
| Started | Jun 29 07:58:46 PM PDT 24 |
| Finished | Jun 29 08:06:38 PM PDT 24 |
| Peak memory | 609264 kb |
| Host | smart-5c5a5418-7642-4a6c-9156-294d3d3ca458 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=rom_ctrl_integrity_check_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=492826557 -assert nopostproc +UV M_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_ctrl_integrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov erage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_rom_ctrl_integrity_check.492826557 |
| Directory | /workspace/2.chip_sw_rom_ctrl_integrity_check/latest |
| Test location | /workspace/coverage/default/2.chip_sw_rstmgr_alert_info.846460994 |
| Short name | T296 |
| Test name | |
| Test status | |
| Simulation time | 15234875888 ps |
| CPU time | 2107.24 seconds |
| Started | Jun 29 07:57:12 PM PDT 24 |
| Finished | Jun 29 08:32:20 PM PDT 24 |
| Peak memory | 609196 kb |
| Host | smart-f687242a-3feb-4164-b4da-9eb8423cbf59 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=30_000_000 +en_scb_tl_err_chk=0 +sw_build_device=sim_dv +sw_images=rstmgr_alert_info_test:1:new_rules,test _rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb _random_seed=846460994 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_rstmgr_alert_info.846460994 |
| Directory | /workspace/2.chip_sw_rstmgr_alert_info/latest |
| Test location | /workspace/coverage/default/2.chip_sw_rstmgr_cpu_info.1986218910 |
| Short name | T242 |
| Test name | |
| Test status | |
| Simulation time | 5453515910 ps |
| CPU time | 519.79 seconds |
| Started | Jun 29 07:56:36 PM PDT 24 |
| Finished | Jun 29 08:05:16 PM PDT 24 |
| Peak memory | 608084 kb |
| Host | smart-9989897a-630e-4a72-9e97-f8ebfb07a504 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=rstmgr_cpu_info_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1986218910 -assert nopostproc +UVM_TESTNA ME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 2.chip_sw_rstmgr_cpu_info.1986218910 |
| Directory | /workspace/2.chip_sw_rstmgr_cpu_info/latest |
| Test location | /workspace/coverage/default/2.chip_sw_rstmgr_rst_cnsty_escalation.3096420614 |
| Short name | T336 |
| Test name | |
| Test status | |
| Simulation time | 5673958240 ps |
| CPU time | 645.83 seconds |
| Started | Jun 29 07:54:18 PM PDT 24 |
| Finished | Jun 29 08:05:04 PM PDT 24 |
| Peak memory | 639620 kb |
| Host | smart-5f1bd1c5-3e5b-4f8e-82f5-3fd5555bf52a |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 3096420614 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rstmgr_cnsty_fault_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_rstmgr_rst_cnsty_escalation.3096420614 |
| Directory | /workspace/2.chip_sw_rstmgr_rst_cnsty_escalation/latest |
| Test location | /workspace/coverage/default/2.chip_sw_rstmgr_smoketest.2394595069 |
| Short name | T1225 |
| Test name | |
| Test status | |
| Simulation time | 3097354750 ps |
| CPU time | 212.74 seconds |
| Started | Jun 29 08:02:48 PM PDT 24 |
| Finished | Jun 29 08:06:21 PM PDT 24 |
| Peak memory | 607124 kb |
| Host | smart-0707b410-c564-47a0-aafd-39b6bffd3625 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=rstmgr_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2394595069 -assert nopostproc +UVM_TESTNAME=c hip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n ull -cm_name 2.chip_sw_rstmgr_smoketest.2394595069 |
| Directory | /workspace/2.chip_sw_rstmgr_smoketest/latest |
| Test location | /workspace/coverage/default/2.chip_sw_rstmgr_sw_req.1773125666 |
| Short name | T426 |
| Test name | |
| Test status | |
| Simulation time | 3932339356 ps |
| CPU time | 460.35 seconds |
| Started | Jun 29 07:55:16 PM PDT 24 |
| Finished | Jun 29 08:02:57 PM PDT 24 |
| Peak memory | 607624 kb |
| Host | smart-c75ceb77-cad3-41a7-84c4-10dcefed363c |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=rstmgr_sw_req_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1773125666 -assert nopostproc +UVM_TESTNAME =chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 2.chip_sw_rstmgr_sw_req.1773125666 |
| Directory | /workspace/2.chip_sw_rstmgr_sw_req/latest |
| Test location | /workspace/coverage/default/2.chip_sw_rstmgr_sw_rst.4262713758 |
| Short name | T1109 |
| Test name | |
| Test status | |
| Simulation time | 2943390096 ps |
| CPU time | 205.44 seconds |
| Started | Jun 29 07:55:41 PM PDT 24 |
| Finished | Jun 29 07:59:07 PM PDT 24 |
| Peak memory | 609156 kb |
| Host | smart-5919bb40-b1bb-45e3-9e79-c15eff18c5d8 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=rstmgr_sw_rst_ctrl_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4262713758 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_rstmgr_sw_rst.4262713758 |
| Directory | /workspace/2.chip_sw_rstmgr_sw_rst/latest |
| Test location | /workspace/coverage/default/2.chip_sw_rv_core_ibex_address_translation.2171082639 |
| Short name | T265 |
| Test name | |
| Test status | |
| Simulation time | 2776679062 ps |
| CPU time | 272.73 seconds |
| Started | Jun 29 08:01:39 PM PDT 24 |
| Finished | Jun 29 08:06:12 PM PDT 24 |
| Peak memory | 609176 kb |
| Host | smart-f0f444c0-34ae-4f38-b30e-affa55aaed61 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=7_000_000 +sw_build_device=sim_dv +sw_images=rv_core_ibex_address_translation_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=2171082639 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_rv_core_ibex_address_translation.2171082639 |
| Directory | /workspace/2.chip_sw_rv_core_ibex_address_translation/latest |
| Test location | /workspace/coverage/default/2.chip_sw_rv_core_ibex_icache_invalidate.2315469456 |
| Short name | T187 |
| Test name | |
| Test status | |
| Simulation time | 3502799752 ps |
| CPU time | 299.74 seconds |
| Started | Jun 29 08:01:02 PM PDT 24 |
| Finished | Jun 29 08:06:02 PM PDT 24 |
| Peak memory | 609148 kb |
| Host | smart-b10ca3ca-ac16-4695-abe0-47ba57c14fd4 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=rv_core_ibex_icache_invalidate_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2315469456 -assert nopostp roc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rv_core_ibex_icache_invalidate_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_rv_core_ibex_icache_invalidate.2315469456 |
| Directory | /workspace/2.chip_sw_rv_core_ibex_icache_invalidate/latest |
| Test location | /workspace/coverage/default/2.chip_sw_rv_core_ibex_lockstep_glitch.324278749 |
| Short name | T838 |
| Test name | |
| Test status | |
| Simulation time | 2973946536 ps |
| CPU time | 204.41 seconds |
| Started | Jun 29 08:01:57 PM PDT 24 |
| Finished | Jun 29 08:05:21 PM PDT 24 |
| Peak memory | 642892 kb |
| Host | smart-7b9ae345-0e19-4823-8837-3fffb272d2a7 |
| User | root |
| Command | /workspace/default/simv +disable_assert_final_checks +sw_build_device=sim_dv +sw_images=aes_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=324278749 -assert n opostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rv_core_ibex_lockstep_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_rv_core_ibex_lockstep_glitch.324278749 |
| Directory | /workspace/2.chip_sw_rv_core_ibex_lockstep_glitch/latest |
| Test location | /workspace/coverage/default/2.chip_sw_rv_core_ibex_nmi_irq.4045245341 |
| Short name | T671 |
| Test name | |
| Test status | |
| Simulation time | 4173992160 ps |
| CPU time | 811.49 seconds |
| Started | Jun 29 07:59:19 PM PDT 24 |
| Finished | Jun 29 08:12:52 PM PDT 24 |
| Peak memory | 607296 kb |
| Host | smart-eb944da7-ff1f-4920-9017-6de3c0c5674f |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=10_000_000 +sw_build_device=sim_dv +sw_images=rv_core_ibex_nmi_irq_test:1:new_rules,test_rom:0 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40452 45341 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_rv_core_ibex_nmi_irq.4045245341 |
| Directory | /workspace/2.chip_sw_rv_core_ibex_nmi_irq/latest |
| Test location | /workspace/coverage/default/2.chip_sw_rv_core_ibex_rnd.2764028196 |
| Short name | T1062 |
| Test name | |
| Test status | |
| Simulation time | 5548516968 ps |
| CPU time | 1149.94 seconds |
| Started | Jun 29 07:56:54 PM PDT 24 |
| Finished | Jun 29 08:16:04 PM PDT 24 |
| Peak memory | 609180 kb |
| Host | smart-49c3356f-fe0b-4fa8-8453-ca08ad456bfe |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=20_000_000 +rng_srate_value_max=32 +sw_build_device=sim_dv +sw_images=rv_core_ibex_rnd_test:1:new_rules,te st_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n tb_random_seed=2764028196 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_rv_core_ibex_rnd.2764028196 |
| Directory | /workspace/2.chip_sw_rv_core_ibex_rnd/latest |
| Test location | /workspace/coverage/default/2.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted.468663098 |
| Short name | T1244 |
| Test name | |
| Test status | |
| Simulation time | 3645481448 ps |
| CPU time | 526.34 seconds |
| Started | Jun 29 08:00:14 PM PDT 24 |
| Finished | Jun 29 08:09:01 PM PDT 24 |
| Peak memory | 614876 kb |
| Host | smart-64aa4441-30e0-4f08-9c81-8893d6b6b4f3 |
| User | root |
| Command | /workspace/default/simv +use_jtag_dmi=1 +sw_build_device=sim_dv +sw_images=rv_dm_ndm_reset_req_when_cpu_halted_rma:1:new_rules,test_rom:0 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=468663 098 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rv_dm_ndm_reset_when_cpu_halted_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted.468663098 |
| Directory | /workspace/2.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted/latest |
| Test location | /workspace/coverage/default/2.chip_sw_rv_plic_smoketest.2820677753 |
| Short name | T1032 |
| Test name | |
| Test status | |
| Simulation time | 2952153484 ps |
| CPU time | 339.13 seconds |
| Started | Jun 29 08:03:35 PM PDT 24 |
| Finished | Jun 29 08:09:15 PM PDT 24 |
| Peak memory | 609196 kb |
| Host | smart-b25fafab-9fb5-4008-aa05-9e14073449fe |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=rv_plic_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2820677753 -assert nopostproc +UVM_TESTNAME= chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/ null -cm_name 2.chip_sw_rv_plic_smoketest.2820677753 |
| Directory | /workspace/2.chip_sw_rv_plic_smoketest/latest |
| Test location | /workspace/coverage/default/2.chip_sw_rv_timer_irq.1729488399 |
| Short name | T4 |
| Test name | |
| Test status | |
| Simulation time | 3209574120 ps |
| CPU time | 297.64 seconds |
| Started | Jun 29 07:57:15 PM PDT 24 |
| Finished | Jun 29 08:02:13 PM PDT 24 |
| Peak memory | 606360 kb |
| Host | smart-f62531ec-f6b0-4e23-92af-d3096704f9f7 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=rv_timer_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1729488399 -assert nopostproc +UVM_TESTNAME =chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 2.chip_sw_rv_timer_irq.1729488399 |
| Directory | /workspace/2.chip_sw_rv_timer_irq/latest |
| Test location | /workspace/coverage/default/2.chip_sw_rv_timer_smoketest.81025067 |
| Short name | T229 |
| Test name | |
| Test status | |
| Simulation time | 2782647480 ps |
| CPU time | 258.33 seconds |
| Started | Jun 29 08:02:57 PM PDT 24 |
| Finished | Jun 29 08:07:16 PM PDT 24 |
| Peak memory | 606212 kb |
| Host | smart-4bffb73a-e0fc-41df-9ca1-341afd984553 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=rv_timer_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81025067 -assert nopostproc +UVM_TESTNAME=c hip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n ull -cm_name 2.chip_sw_rv_timer_smoketest.81025067 |
| Directory | /workspace/2.chip_sw_rv_timer_smoketest/latest |
| Test location | /workspace/coverage/default/2.chip_sw_sensor_ctrl_status.2359592598 |
| Short name | T134 |
| Test name | |
| Test status | |
| Simulation time | 2390430908 ps |
| CPU time | 257.14 seconds |
| Started | Jun 29 07:59:00 PM PDT 24 |
| Finished | Jun 29 08:03:18 PM PDT 24 |
| Peak memory | 608396 kb |
| Host | smart-1667d6f5-59b2-41a9-9c43-d677cc32cb90 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=40_000_000 +sw_build_device=sim_dv +sw_images=sensor_ctrl_status_test:1:new_rules,test_rom:0 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2359592 598 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sensor_ctrl_status_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_sensor_ctrl_status.2359592598 |
| Directory | /workspace/2.chip_sw_sensor_ctrl_status/latest |
| Test location | /workspace/coverage/default/2.chip_sw_sleep_pin_retention.217140709 |
| Short name | T11 |
| Test name | |
| Test status | |
| Simulation time | 3638413900 ps |
| CPU time | 354.68 seconds |
| Started | Jun 29 07:55:17 PM PDT 24 |
| Finished | Jun 29 08:01:12 PM PDT 24 |
| Peak memory | 607988 kb |
| Host | smart-a106f03d-601b-4d57-b846-663b07e26e9b |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=sleep_pin_retention_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=217140709 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sleep_pin_retention_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defa ult.vdb -cm_log /dev/null -cm_name 2.chip_sw_sleep_pin_retention.217140709 |
| Directory | /workspace/2.chip_sw_sleep_pin_retention/latest |
| Test location | /workspace/coverage/default/2.chip_sw_sleep_pwm_pulses.2280864684 |
| Short name | T1195 |
| Test name | |
| Test status | |
| Simulation time | 8971850112 ps |
| CPU time | 1145.23 seconds |
| Started | Jun 29 07:53:28 PM PDT 24 |
| Finished | Jun 29 08:12:33 PM PDT 24 |
| Peak memory | 607324 kb |
| Host | smart-455d16ae-5357-4828-96bb-b9d3a8806607 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=sleep_pwm_pulses_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2280864684 -assert nopostproc +UVM_TESTN AME=chip_base_test +UVM_TEST_SEQ=chip_sw_pwm_pulses_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm _log /dev/null -cm_name 2.chip_sw_sleep_pwm_pulses.2280864684 |
| Directory | /workspace/2.chip_sw_sleep_pwm_pulses/latest |
| Test location | /workspace/coverage/default/2.chip_sw_sleep_sram_ret_contents_no_scramble.2696607245 |
| Short name | T1063 |
| Test name | |
| Test status | |
| Simulation time | 7924045008 ps |
| CPU time | 829.35 seconds |
| Started | Jun 29 07:58:43 PM PDT 24 |
| Finished | Jun 29 08:12:33 PM PDT 24 |
| Peak memory | 609260 kb |
| Host | smart-a322f2fc-0ae5-4ae0-9dbd-6bc38b0cc73c |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=20_000_000 +en_scb_tl_err_chk=0 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=sram _ctrl_sleep_sram_ret_contents_no_scramble_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2696607245 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_S EQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_sl eep_sram_ret_contents_no_scramble.2696607245 |
| Directory | /workspace/2.chip_sw_sleep_sram_ret_contents_no_scramble/latest |
| Test location | /workspace/coverage/default/2.chip_sw_sleep_sram_ret_contents_scramble.113848501 |
| Short name | T978 |
| Test name | |
| Test status | |
| Simulation time | 7044562740 ps |
| CPU time | 852.59 seconds |
| Started | Jun 29 07:59:13 PM PDT 24 |
| Finished | Jun 29 08:13:26 PM PDT 24 |
| Peak memory | 609256 kb |
| Host | smart-e7560fb4-c09f-402c-aa6d-85e3fd69843e |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=20_000_000 +en_scb_tl_err_chk=0 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=sram _ctrl_sleep_sram_ret_contents_scramble_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=113848501 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=c hip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_sleep_ sram_ret_contents_scramble.113848501 |
| Directory | /workspace/2.chip_sw_sleep_sram_ret_contents_scramble/latest |
| Test location | /workspace/coverage/default/2.chip_sw_spi_device_pass_through_collision.3205735895 |
| Short name | T23 |
| Test name | |
| Test status | |
| Simulation time | 3973289847 ps |
| CPU time | 572.46 seconds |
| Started | Jun 29 07:54:35 PM PDT 24 |
| Finished | Jun 29 08:04:08 PM PDT 24 |
| Peak memory | 624276 kb |
| Host | smart-91f42f34-82a6-49dc-9d87-007981d22fbb |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=spi_passthrough_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3205735895 -assert nopostproc +UVM_TESTNA ME=chip_base_test +UVM_TEST_SEQ=chip_sw_spi_passthrough_collision_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/d efault.vdb -cm_log /dev/null -cm_name 2.chip_sw_spi_device_pass_through_collision.3205735895 |
| Directory | /workspace/2.chip_sw_spi_device_pass_through_collision/latest |
| Test location | /workspace/coverage/default/2.chip_sw_spi_device_tpm.2776199378 |
| Short name | T47 |
| Test name | |
| Test status | |
| Simulation time | 3585829919 ps |
| CPU time | 410.14 seconds |
| Started | Jun 29 07:54:26 PM PDT 24 |
| Finished | Jun 29 08:01:17 PM PDT 24 |
| Peak memory | 616528 kb |
| Host | smart-47002e48-ff2e-4d9e-a8c0-356fe5e85bcb |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=spi_device_tpm_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2776199378 -assert nopostproc +UVM_T ESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_spi_device_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default .vdb -cm_log /dev/null -cm_name 2.chip_sw_spi_device_tpm.2776199378 |
| Directory | /workspace/2.chip_sw_spi_device_tpm/latest |
| Test location | /workspace/coverage/default/2.chip_sw_sram_ctrl_execution_main.3176607007 |
| Short name | T272 |
| Test name | |
| Test status | |
| Simulation time | 7772156325 ps |
| CPU time | 874.57 seconds |
| Started | Jun 29 07:59:36 PM PDT 24 |
| Finished | Jun 29 08:14:11 PM PDT 24 |
| Peak memory | 608220 kb |
| Host | smart-db035b4c-d9ff-4e5b-a479-e744548643fc |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=sram_ctrl_execution_main_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3176607007 -assert nopostproc +U VM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sram_ctrl_execution_main_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co verage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_sram_ctrl_execution_main.3176607007 |
| Directory | /workspace/2.chip_sw_sram_ctrl_execution_main/latest |
| Test location | /workspace/coverage/default/2.chip_sw_sram_ctrl_scrambled_access.2176283669 |
| Short name | T249 |
| Test name | |
| Test status | |
| Simulation time | 4898138688 ps |
| CPU time | 702.11 seconds |
| Started | Jun 29 07:59:09 PM PDT 24 |
| Finished | Jun 29 08:10:52 PM PDT 24 |
| Peak memory | 608784 kb |
| Host | smart-4806d250-b4a0-4dec-a9f8-8630396bc582 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=12_000_000 +en_scb_tl_err_chk=0 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=sram _ctrl_scrambled_access_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2176283669 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sram_ctr l_scrambled_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw _sram_ctrl_scrambled_access.2176283669 |
| Directory | /workspace/2.chip_sw_sram_ctrl_scrambled_access/latest |
| Test location | /workspace/coverage/default/2.chip_sw_sram_ctrl_scrambled_access_jitter_en.1283897895 |
| Short name | T969 |
| Test name | |
| Test status | |
| Simulation time | 5142213950 ps |
| CPU time | 638.93 seconds |
| Started | Jun 29 08:01:24 PM PDT 24 |
| Finished | Jun 29 08:12:04 PM PDT 24 |
| Peak memory | 608768 kb |
| Host | smart-b0e11cf0-1ac0-4d9b-af33-7a4cd78603c6 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=12_000_000 +bypass_alert_ready_to_end_check=1 +en_jitter=1 +en_scb_tl_err_chk=0 +sw_build_device=sim_dv +s w_images=sram_ctrl_scrambled_access_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1283897895 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chi p_sw_sram_ctrl_scrambled_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n ame 2.chip_sw_sram_ctrl_scrambled_access_jitter_en.1283897895 |
| Directory | /workspace/2.chip_sw_sram_ctrl_scrambled_access_jitter_en/latest |
| Test location | /workspace/coverage/default/2.chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq.3488215410 |
| Short name | T251 |
| Test name | |
| Test status | |
| Simulation time | 5588035894 ps |
| CPU time | 639.92 seconds |
| Started | Jun 29 08:01:13 PM PDT 24 |
| Finished | Jun 29 08:11:54 PM PDT 24 |
| Peak memory | 608184 kb |
| Host | smart-f600c10f-0b3d-4499-b941-84b5aec0c7e3 |
| User | root |
| Command | /workspace/default/simv +mem_sel=main +sw_test_timeout_ns=12_000_000 +bypass_alert_ready_to_end_check=1 +en_jitter=1 +en_scb_tl_err_chk=0 +cal_sys_clk _70mhz=1 +sw_build_device=sim_dv +sw_images=sram_ctrl_scrambled_access_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3488215410 -assert nopostproc +UVM_TESTNA ME=chip_base_test +UVM_TEST_SEQ=chip_sw_sram_ctrl_scrambled_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/ default.vdb -cm_log /dev/null -cm_name 2.chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq.3488215410 |
| Directory | /workspace/2.chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq/latest |
| Test location | /workspace/coverage/default/2.chip_sw_sram_ctrl_smoketest.3655647393 |
| Short name | T441 |
| Test name | |
| Test status | |
| Simulation time | 2951939714 ps |
| CPU time | 212.21 seconds |
| Started | Jun 29 08:02:47 PM PDT 24 |
| Finished | Jun 29 08:06:20 PM PDT 24 |
| Peak memory | 609184 kb |
| Host | smart-9bf5af62-434d-4766-b0d5-244e0227ae08 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=sram_ctrl_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3655647393 -assert nopostproc +UVM_TESTNAM E=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 2.chip_sw_sram_ctrl_smoketest.3655647393 |
| Directory | /workspace/2.chip_sw_sram_ctrl_smoketest/latest |
| Test location | /workspace/coverage/default/2.chip_sw_sysrst_ctrl_ec_rst_l.3536274738 |
| Short name | T193 |
| Test name | |
| Test status | |
| Simulation time | 20633998918 ps |
| CPU time | 4257.44 seconds |
| Started | Jun 29 07:57:40 PM PDT 24 |
| Finished | Jun 29 09:08:39 PM PDT 24 |
| Peak memory | 609256 kb |
| Host | smart-fa141e93-6175-48b9-8da2-f2b3b9532949 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=sysrst_ctrl_ec_rst_l_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3536274738 -assert nopostproc +UVM_T ESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_ec_rst_l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/d efault.vdb -cm_log /dev/null -cm_name 2.chip_sw_sysrst_ctrl_ec_rst_l.3536274738 |
| Directory | /workspace/2.chip_sw_sysrst_ctrl_ec_rst_l/latest |
| Test location | /workspace/coverage/default/2.chip_sw_sysrst_ctrl_in_irq.1604356795 |
| Short name | T157 |
| Test name | |
| Test status | |
| Simulation time | 4981183310 ps |
| CPU time | 662.1 seconds |
| Started | Jun 29 07:56:53 PM PDT 24 |
| Finished | Jun 29 08:07:58 PM PDT 24 |
| Peak memory | 612528 kb |
| Host | smart-62c1218f-b350-466a-bd88-a007f70291e9 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=sysrst_ctrl_in_irq_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1604356795 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_in_irq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau lt.vdb -cm_log /dev/null -cm_name 2.chip_sw_sysrst_ctrl_in_irq.1604356795 |
| Directory | /workspace/2.chip_sw_sysrst_ctrl_in_irq/latest |
| Test location | /workspace/coverage/default/2.chip_sw_sysrst_ctrl_inputs.2385077730 |
| Short name | T160 |
| Test name | |
| Test status | |
| Simulation time | 3049120311 ps |
| CPU time | 270.97 seconds |
| Started | Jun 29 07:57:22 PM PDT 24 |
| Finished | Jun 29 08:01:54 PM PDT 24 |
| Peak memory | 612248 kb |
| Host | smart-b3042043-5be2-44fd-b73f-6f0f621dd856 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=sysrst_ctrl_inputs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2385077730 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_inputs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau lt.vdb -cm_log /dev/null -cm_name 2.chip_sw_sysrst_ctrl_inputs.2385077730 |
| Directory | /workspace/2.chip_sw_sysrst_ctrl_inputs/latest |
| Test location | /workspace/coverage/default/2.chip_sw_sysrst_ctrl_outputs.636405413 |
| Short name | T1137 |
| Test name | |
| Test status | |
| Simulation time | 3108045224 ps |
| CPU time | 341.88 seconds |
| Started | Jun 29 07:56:31 PM PDT 24 |
| Finished | Jun 29 08:02:13 PM PDT 24 |
| Peak memory | 607108 kb |
| Host | smart-aafff089-d8ba-4985-aa79-11236b92ca3c |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=sysrst_ctrl_outputs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=636405413 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_outputs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defa ult.vdb -cm_log /dev/null -cm_name 2.chip_sw_sysrst_ctrl_outputs.636405413 |
| Directory | /workspace/2.chip_sw_sysrst_ctrl_outputs/latest |
| Test location | /workspace/coverage/default/2.chip_sw_sysrst_ctrl_ulp_z3_wakeup.3513751950 |
| Short name | T43 |
| Test name | |
| Test status | |
| Simulation time | 5949564766 ps |
| CPU time | 298.04 seconds |
| Started | Jun 29 07:56:04 PM PDT 24 |
| Finished | Jun 29 08:01:03 PM PDT 24 |
| Peak memory | 608372 kb |
| Host | smart-600fbe71-27d1-41d5-bd2f-739d74cf42ef |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=sysrst_ctrl_ulp_z3_wakeup_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3513751950 -assert nopostproc + UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_ulp_z3_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/ coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_sysrst_ctrl_ulp_z3_wakeup.3513751950 |
| Directory | /workspace/2.chip_sw_sysrst_ctrl_ulp_z3_wakeup/latest |
| Test location | /workspace/coverage/default/2.chip_sw_uart_rand_baudrate.777365564 |
| Short name | T1113 |
| Test name | |
| Test status | |
| Simulation time | 13420256340 ps |
| CPU time | 2772.26 seconds |
| Started | Jun 29 07:53:47 PM PDT 24 |
| Finished | Jun 29 08:40:00 PM PDT 24 |
| Peak memory | 618880 kb |
| Host | smart-ca87ce28-c44a-48d0-845b-1cc00e43f8b1 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=777365564 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_uart_rand_baudrate.777365564 |
| Directory | /workspace/2.chip_sw_uart_rand_baudrate/latest |
| Test location | /workspace/coverage/default/2.chip_sw_uart_smoketest.4102640679 |
| Short name | T1097 |
| Test name | |
| Test status | |
| Simulation time | 3329223418 ps |
| CPU time | 371.73 seconds |
| Started | Jun 29 08:05:13 PM PDT 24 |
| Finished | Jun 29 08:11:25 PM PDT 24 |
| Peak memory | 609960 kb |
| Host | smart-ebcc8fec-05d7-41ac-971f-01a5c3f4a0cb |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=uart_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4102640679 -assert nopostproc +UVM_TESTNAME=chi p_base_test +UVM_TEST_SEQ=chip_sw_uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 2.chip_sw_uart_smoketest.4102640679 |
| Directory | /workspace/2.chip_sw_uart_smoketest/latest |
| Test location | /workspace/coverage/default/2.chip_sw_uart_tx_rx.4218928941 |
| Short name | T393 |
| Test name | |
| Test status | |
| Simulation time | 5083488658 ps |
| CPU time | 807.73 seconds |
| Started | Jun 29 07:53:49 PM PDT 24 |
| Finished | Jun 29 08:07:18 PM PDT 24 |
| Peak memory | 615884 kb |
| Host | smart-c542366d-49e3-4fb3-876f-6c1b1dcd13c9 |
| User | root |
| Command | /workspace/default/simv +uart_idx=0 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4218928941 -a ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_uart_tx_rx.4218928941 |
| Directory | /workspace/2.chip_sw_uart_tx_rx/latest |
| Test location | /workspace/coverage/default/2.chip_sw_uart_tx_rx_alt_clk_freq.1653924315 |
| Short name | T26 |
| Test name | |
| Test status | |
| Simulation time | 7986703383 ps |
| CPU time | 1907.6 seconds |
| Started | Jun 29 07:53:27 PM PDT 24 |
| Finished | Jun 29 08:25:16 PM PDT 24 |
| Peak memory | 620440 kb |
| Host | smart-af14a830-a6bf-4555-9b90-14b207a81bec |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=80_000_000 +chip_clock_source=ChipClockSourceExternal96Mhz +calibrate_usb_clk=1 +sw_build_device=sim_dv +s w_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1653924315 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_b audrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_uart_tx_rx _alt_clk_freq.1653924315 |
| Directory | /workspace/2.chip_sw_uart_tx_rx_alt_clk_freq/latest |
| Test location | /workspace/coverage/default/2.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.3630049902 |
| Short name | T436 |
| Test name | |
| Test status | |
| Simulation time | 4860411757 ps |
| CPU time | 560.81 seconds |
| Started | Jun 29 07:59:07 PM PDT 24 |
| Finished | Jun 29 08:08:29 PM PDT 24 |
| Peak memory | 618888 kb |
| Host | smart-8174288e-048b-453c-b63c-326fbd56adb7 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +chip_clock_source=ChipClockSourceExternal48Mhz +sw_build_device=sim_dv +s w_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3630049902 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_b audrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_uart_tx_rx _alt_clk_freq_low_speed.3630049902 |
| Directory | /workspace/2.chip_sw_uart_tx_rx_alt_clk_freq_low_speed/latest |
| Test location | /workspace/coverage/default/2.chip_sw_uart_tx_rx_bootstrap.66061893 |
| Short name | T1138 |
| Test name | |
| Test status | |
| Simulation time | 77272075696 ps |
| CPU time | 14489.3 seconds |
| Started | Jun 29 07:54:02 PM PDT 24 |
| Finished | Jun 29 11:55:33 PM PDT 24 |
| Peak memory | 632392 kb |
| Host | smart-0d4c6f2d-993a-40d5-ae30-0565bfdc1796 |
| User | root |
| Command | /workspace/default/simv +use_spi_load_bootstrap=1 +calibrate_usb_clk=1 +test_timeout_ns=160_000_000 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test :1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=66061893 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_uart_tx_rx_bootstrap.66061893 |
| Directory | /workspace/2.chip_sw_uart_tx_rx_bootstrap/latest |
| Test location | /workspace/coverage/default/2.chip_sw_uart_tx_rx_idx1.3770843411 |
| Short name | T958 |
| Test name | |
| Test status | |
| Simulation time | 3962529560 ps |
| CPU time | 796.38 seconds |
| Started | Jun 29 07:54:16 PM PDT 24 |
| Finished | Jun 29 08:07:33 PM PDT 24 |
| Peak memory | 615840 kb |
| Host | smart-dc494b97-101e-4f33-a9bd-3ec95d4d160f |
| User | root |
| Command | /workspace/default/simv +uart_idx=1 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3770843411 -a ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_uart_tx_rx_idx1.3770843411 |
| Directory | /workspace/2.chip_sw_uart_tx_rx_idx1/latest |
| Test location | /workspace/coverage/default/2.chip_sw_uart_tx_rx_idx2.1005648941 |
| Short name | T1178 |
| Test name | |
| Test status | |
| Simulation time | 4014583668 ps |
| CPU time | 745.84 seconds |
| Started | Jun 29 07:54:25 PM PDT 24 |
| Finished | Jun 29 08:06:52 PM PDT 24 |
| Peak memory | 615900 kb |
| Host | smart-a8b3c856-4042-496d-bbe8-efe64decf4f7 |
| User | root |
| Command | /workspace/default/simv +uart_idx=2 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1005648941 -a ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_uart_tx_rx_idx2.1005648941 |
| Directory | /workspace/2.chip_sw_uart_tx_rx_idx2/latest |
| Test location | /workspace/coverage/default/2.chip_sw_uart_tx_rx_idx3.3776551246 |
| Short name | T412 |
| Test name | |
| Test status | |
| Simulation time | 4384219826 ps |
| CPU time | 659.95 seconds |
| Started | Jun 29 07:53:12 PM PDT 24 |
| Finished | Jun 29 08:04:13 PM PDT 24 |
| Peak memory | 615884 kb |
| Host | smart-9072c37c-79c5-46b6-83a1-ec8b26c75a50 |
| User | root |
| Command | /workspace/default/simv +uart_idx=3 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3776551246 -a ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_uart_tx_rx_idx3.3776551246 |
| Directory | /workspace/2.chip_sw_uart_tx_rx_idx3/latest |
| Test location | /workspace/coverage/default/2.chip_tap_straps_dev.1373693793 |
| Short name | T644 |
| Test name | |
| Test status | |
| Simulation time | 11332555805 ps |
| CPU time | 1404.66 seconds |
| Started | Jun 29 07:59:53 PM PDT 24 |
| Finished | Jun 29 08:23:19 PM PDT 24 |
| Peak memory | 620376 kb |
| Host | smart-4ea5099c-7e0d-40fe-a98e-3b9ece958878 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStDev +create_jtag_riscv_map=1 +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:test_in_rom: new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=1373693793 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_tap_straps_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_tap_straps_dev.1373693793 |
| Directory | /workspace/2.chip_tap_straps_dev/latest |
| Test location | /workspace/coverage/default/2.chip_tap_straps_prod.770922857 |
| Short name | T1073 |
| Test name | |
| Test status | |
| Simulation time | 13273230854 ps |
| CPU time | 1630.17 seconds |
| Started | Jun 29 08:00:50 PM PDT 24 |
| Finished | Jun 29 08:28:01 PM PDT 24 |
| Peak memory | 620380 kb |
| Host | smart-61b02767-0f91-45a2-8d03-0cd0253c15e5 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStProd +create_jtag_riscv_map=1 +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:test_in_rom :new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=770922857 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_tap_straps_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_tap_straps_prod.770922857 |
| Directory | /workspace/2.chip_tap_straps_prod/latest |
| Test location | /workspace/coverage/default/2.chip_tap_straps_rma.1818946805 |
| Short name | T1180 |
| Test name | |
| Test status | |
| Simulation time | 6186487470 ps |
| CPU time | 598.81 seconds |
| Started | Jun 29 08:00:45 PM PDT 24 |
| Finished | Jun 29 08:10:44 PM PDT 24 |
| Peak memory | 620412 kb |
| Host | smart-7f87fd8b-c241-4e9f-99ff-880232513e61 |
| User | root |
| Command | /workspace/default/simv +create_jtag_riscv_map=1 +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:test_in_rom:new_rules +cdc_instrumentation _enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1818946805 -as sert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_tap_straps_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/c overage/default.vdb -cm_log /dev/null -cm_name 2.chip_tap_straps_rma.1818946805 |
| Directory | /workspace/2.chip_tap_straps_rma/latest |
| Test location | /workspace/coverage/default/2.chip_tap_straps_testunlock0.732032091 |
| Short name | T69 |
| Test name | |
| Test status | |
| Simulation time | 4818180682 ps |
| CPU time | 461.06 seconds |
| Started | Jun 29 07:59:09 PM PDT 24 |
| Finished | Jun 29 08:06:51 PM PDT 24 |
| Peak memory | 618304 kb |
| Host | smart-4bc1c257-d9d6-46d2-adc0-d6cb22a0657c |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStTestUnlocked0 +create_jtag_riscv_map=1 +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:te st_in_rom:new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=732032091 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_tap_straps_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_tap_straps_testunlock0.732032091 |
| Directory | /workspace/2.chip_tap_straps_testunlock0/latest |
| Test location | /workspace/coverage/default/2.rom_e2e_asm_init_dev.1935542138 |
| Short name | T262 |
| Test name | |
| Test status | |
| Simulation time | 15938690781 ps |
| CPU time | 3853.4 seconds |
| Started | Jun 29 08:06:43 PM PDT 24 |
| Finished | Jun 29 09:10:57 PM PDT 24 |
| Peak memory | 607908 kb |
| Host | smart-ce66b95a-42b9-4805-931e-c38443ad6542 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeCustom +sw_test_timeout_ns=20000000 +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_prod _key_0:1:ot_flash_binary,otp_img_e2e_bootstrap_entry_dev:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1935542138 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_S EQ=chip_sw_rom_e2e_asm_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_e2e_asm_init_dev.1935542138 |
| Directory | /workspace/2.rom_e2e_asm_init_dev/latest |
| Test location | /workspace/coverage/default/2.rom_e2e_asm_init_prod.2962055330 |
| Short name | T1208 |
| Test name | |
| Test status | |
| Simulation time | 15680727392 ps |
| CPU time | 3236.51 seconds |
| Started | Jun 29 08:11:28 PM PDT 24 |
| Finished | Jun 29 09:05:25 PM PDT 24 |
| Peak memory | 608224 kb |
| Host | smart-d8ae390f-4988-4ef6-ae91-7959b856fb8f |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeCustom +sw_test_timeout_ns=20000000 +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_prod _key_0:1:ot_flash_binary,otp_img_e2e_bootstrap_entry_prod:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2962055330 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_ SEQ=chip_sw_rom_e2e_asm_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_e2e_asm_init_prod.2962055330 |
| Directory | /workspace/2.rom_e2e_asm_init_prod/latest |
| Test location | /workspace/coverage/default/2.rom_e2e_asm_init_prod_end.2341969566 |
| Short name | T54 |
| Test name | |
| Test status | |
| Simulation time | 15973611808 ps |
| CPU time | 4095.21 seconds |
| Started | Jun 29 08:07:49 PM PDT 24 |
| Finished | Jun 29 09:16:05 PM PDT 24 |
| Peak memory | 607120 kb |
| Host | smart-95ef6da0-c4fd-48cb-b8fe-1d542e1eb479 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeCustom +sw_test_timeout_ns=20000000 +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_prod _key_0:1:ot_flash_binary,otp_img_e2e_bootstrap_entry_prod_end:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2341969566 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_T EST_SEQ=chip_sw_rom_e2e_asm_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 2.rom_e2e_asm_init_prod_end.2341969566 |
| Directory | /workspace/2.rom_e2e_asm_init_prod_end/latest |
| Test location | /workspace/coverage/default/2.rom_e2e_asm_init_rma.3396944141 |
| Short name | T907 |
| Test name | |
| Test status | |
| Simulation time | 15043033839 ps |
| CPU time | 4289.63 seconds |
| Started | Jun 29 08:13:48 PM PDT 24 |
| Finished | Jun 29 09:25:18 PM PDT 24 |
| Peak memory | 608216 kb |
| Host | smart-76404245-c666-42ca-bae4-b57fa0fe3df4 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeCustom +sw_test_timeout_ns=20000000 +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_prod _key_0:1:ot_flash_binary,otp_img_e2e_bootstrap_entry_rma:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3396944141 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_S EQ=chip_sw_rom_e2e_asm_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_e2e_asm_init_rma.3396944141 |
| Directory | /workspace/2.rom_e2e_asm_init_rma/latest |
| Test location | /workspace/coverage/default/2.rom_e2e_asm_init_test_unlocked0.4125312174 |
| Short name | T857 |
| Test name | |
| Test status | |
| Simulation time | 11087498110 ps |
| CPU time | 3365.71 seconds |
| Started | Jun 29 08:05:00 PM PDT 24 |
| Finished | Jun 29 09:01:06 PM PDT 24 |
| Peak memory | 608404 kb |
| Host | smart-6a1a0b08-6dac-422b-bb70-8e4294ef338e |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeCustom +sw_test_timeout_ns=410_000_000 +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_p rod_key_0:1:ot_flash_binary,otp_img_e2e_bootstrap_entry_test_unlocked0:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY =UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4125312174 -assert nopostproc +UVM_TESTNAME=chip_base_te st +UVM_TEST_SEQ=chip_sw_rom_e2e_asm_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/ null -cm_name 2.rom_e2e_asm_init_test_unlocked0.4125312174 |
| Directory | /workspace/2.rom_e2e_asm_init_test_unlocked0/latest |
| Test location | /workspace/coverage/default/2.rom_e2e_keymgr_init_rom_ext_invalid_meas.748492095 |
| Short name | T844 |
| Test name | |
| Test status | |
| Simulation time | 14604802536 ps |
| CPU time | 4229.66 seconds |
| Started | Jun 29 08:06:49 PM PDT 24 |
| Finished | Jun 29 09:17:20 PM PDT 24 |
| Peak memory | 608620 kb |
| Host | smart-008faf1a-995d-4300-ac5a-357460c8c67f |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=40_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=rom_e2e_keymgr_init_otp_invalid _meas:1:new_rules,otp_img_keymgr_otp_invalid_meas:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=748492095 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_ sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_e2e_keymgr_ini t_rom_ext_invalid_meas.748492095 |
| Directory | /workspace/2.rom_e2e_keymgr_init_rom_ext_invalid_meas/latest |
| Test location | /workspace/coverage/default/2.rom_e2e_keymgr_init_rom_ext_meas.4164279035 |
| Short name | T1049 |
| Test name | |
| Test status | |
| Simulation time | 14660015392 ps |
| CPU time | 4715.39 seconds |
| Started | Jun 29 08:09:56 PM PDT 24 |
| Finished | Jun 29 09:28:32 PM PDT 24 |
| Peak memory | 607392 kb |
| Host | smart-4e4ef3df-5dd3-42b0-bcbc-6b75d5b3c1e2 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=40_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=rom_e2e_keymgr_init_otp_meas:1: new_rules,otp_img_keymgr_otp_meas:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4164279035 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_e2e_keymgr_init_rom_ext_meas.4164279035 |
| Directory | /workspace/2.rom_e2e_keymgr_init_rom_ext_meas/latest |
| Test location | /workspace/coverage/default/2.rom_e2e_keymgr_init_rom_ext_no_meas.3836557466 |
| Short name | T945 |
| Test name | |
| Test status | |
| Simulation time | 14727511076 ps |
| CPU time | 4257.75 seconds |
| Started | Jun 29 08:07:04 PM PDT 24 |
| Finished | Jun 29 09:18:02 PM PDT 24 |
| Peak memory | 607332 kb |
| Host | smart-3d4fde3f-158e-4e58-81fa-50f57fbf7e7b |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=40_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=rom_e2e_keymgr_init_otp_no_meas :1:new_rules,otp_img_keymgr_otp_no_meas:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3836557466 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_e2e_keymgr_init_rom_ext _no_meas.3836557466 |
| Directory | /workspace/2.rom_e2e_keymgr_init_rom_ext_no_meas/latest |
| Test location | /workspace/coverage/default/2.rom_e2e_shutdown_exception_c.3348455190 |
| Short name | T1247 |
| Test name | |
| Test status | |
| Simulation time | 14313330520 ps |
| CPU time | 3712.05 seconds |
| Started | Jun 29 08:07:54 PM PDT 24 |
| Finished | Jun 29 09:09:47 PM PDT 24 |
| Peak memory | 607560 kb |
| Host | smart-a27d1f70-c671-474a-8307-02009e66e191 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=40000000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=rom_e2e_shutdown_exception_c:1:ne w_rules,otp_img_secret2_locked_rma:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3348455190 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_e2e_shu tdown_exception_c_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_e2e_ shutdown_exception_c.3348455190 |
| Directory | /workspace/2.rom_e2e_shutdown_exception_c/latest |
| Test location | /workspace/coverage/default/2.rom_e2e_shutdown_output.352762892 |
| Short name | T51 |
| Test name | |
| Test status | |
| Simulation time | 25102897567 ps |
| CPU time | 3267.44 seconds |
| Started | Jun 29 08:07:03 PM PDT 24 |
| Finished | Jun 29 09:01:31 PM PDT 24 |
| Peak memory | 609792 kb |
| Host | smart-90ef01ad-508d-42db-a1f0-b5c5520fa5a4 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=20000000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_unsigned:1:ot_f lash_binary,otp_img_shutdown_output_test_unlocked0:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=352762892 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip _sw_rom_e2e_shutdown_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_e2e_shutdown_output.352762892 |
| Directory | /workspace/2.rom_e2e_shutdown_output/latest |
| Test location | /workspace/coverage/default/2.rom_e2e_smoke.161156348 |
| Short name | T245 |
| Test name | |
| Test status | |
| Simulation time | 15299879888 ps |
| CPU time | 3763.52 seconds |
| Started | Jun 29 08:06:42 PM PDT 24 |
| Finished | Jun 29 09:09:26 PM PDT 24 |
| Peak memory | 608296 kb |
| Host | smart-e69d9657-b7f5-4f88-b902-54fa63ab2a21 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=40000000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=rom_e2e_smoke:1:new_rules,otp_img _secret2_locked_rma:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_to p/hw/dv/tools/sim.tcl +ntb_random_seed=161156348 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_e2e_smoke.161156348 |
| Directory | /workspace/2.rom_e2e_smoke/latest |
| Test location | /workspace/coverage/default/2.rom_e2e_static_critical.2305462607 |
| Short name | T934 |
| Test name | |
| Test status | |
| Simulation time | 16899361668 ps |
| CPU time | 4182.22 seconds |
| Started | Jun 29 08:06:12 PM PDT 24 |
| Finished | Jun 29 09:15:55 PM PDT 24 |
| Peak memory | 607392 kb |
| Host | smart-b8539a86-df64-4504-bf6e-c765af322cba |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=40000000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=rom_e2e_static_critical:1:new_rul es,otp_img_secret2_locked_rma:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2305462607 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_e2e_static_critical.2305462607 |
| Directory | /workspace/2.rom_e2e_static_critical/latest |
| Test location | /workspace/coverage/default/2.rom_keymgr_functest.3709698744 |
| Short name | T1040 |
| Test name | |
| Test status | |
| Simulation time | 4058008500 ps |
| CPU time | 416.06 seconds |
| Started | Jun 29 08:09:53 PM PDT 24 |
| Finished | Jun 29 08:16:50 PM PDT 24 |
| Peak memory | 609200 kb |
| Host | smart-2c6fd729-99ec-4b06-a26e-2dbfd1e96db8 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=10_000_000 +sw_build_device=sim_dv +sw_images=keymgr_functest:1:new_rules,test_rom:0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3709698744 -ass ert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 2.rom_keymgr_functest.3709698744 |
| Directory | /workspace/2.rom_keymgr_functest/latest |
| Test location | /workspace/coverage/default/2.rom_volatile_raw_unlock.438200144 |
| Short name | T406 |
| Test name | |
| Test status | |
| Simulation time | 2286055460 ps |
| CPU time | 127.2 seconds |
| Started | Jun 29 08:10:05 PM PDT 24 |
| Finished | Jun 29 08:12:13 PM PDT 24 |
| Peak memory | 614456 kb |
| Host | smart-fd9ba4c5-37cf-4872-91b1-59ca4a431604 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=200_000_000 +use_otp_image=OtpTypeLcStRaw +chip_clock_source=ChipClockSourceExternal48Mhz +rom_prod_mode=1 +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_test_key_0:1:ot_flash_binary,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=438200144 -assert nopostproc +UVM_T ESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_volatile_raw_unlock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage /default.vdb -cm_log /dev/null -cm_name 2.rom_volatile_raw_unlock.438200144 |
| Directory | /workspace/2.rom_volatile_raw_unlock/latest |
| Test location | /workspace/coverage/default/21.chip_sw_all_escalation_resets.3154553946 |
| Short name | T696 |
| Test name | |
| Test status | |
| Simulation time | 5282970028 ps |
| CPU time | 666.58 seconds |
| Started | Jun 29 08:07:58 PM PDT 24 |
| Finished | Jun 29 08:19:05 PM PDT 24 |
| Peak memory | 615124 kb |
| Host | smart-729d6461-f4aa-4a26-b384-276abb2df95f |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 3154553946 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.chip_sw_all_escalation_resets.3154553946 |
| Directory | /workspace/21.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/24.chip_sw_alert_handler_lpg_sleep_mode_alerts.1363949125 |
| Short name | T737 |
| Test name | |
| Test status | |
| Simulation time | 3689822120 ps |
| CPU time | 371.25 seconds |
| Started | Jun 29 08:09:02 PM PDT 24 |
| Finished | Jun 29 08:15:14 PM PDT 24 |
| Peak memory | 642260 kb |
| Host | smart-721e273c-c96e-4112-b21e-012b11be6ac8 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1363949125 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.chip_ sw_alert_handler_lpg_sleep_mode_alerts.1363949125 |
| Directory | /workspace/24.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/24.chip_sw_all_escalation_resets.3895593294 |
| Short name | T708 |
| Test name | |
| Test status | |
| Simulation time | 4656097444 ps |
| CPU time | 553.66 seconds |
| Started | Jun 29 08:08:13 PM PDT 24 |
| Finished | Jun 29 08:17:27 PM PDT 24 |
| Peak memory | 643552 kb |
| Host | smart-6c66c550-7b12-4669-9601-d4a25f0407f5 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 3895593294 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.chip_sw_all_escalation_resets.3895593294 |
| Directory | /workspace/24.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/25.chip_sw_alert_handler_lpg_sleep_mode_alerts.86555180 |
| Short name | T717 |
| Test name | |
| Test status | |
| Simulation time | 3181429840 ps |
| CPU time | 443.77 seconds |
| Started | Jun 29 08:08:22 PM PDT 24 |
| Finished | Jun 29 08:15:46 PM PDT 24 |
| Peak memory | 647360 kb |
| Host | smart-92416543-2cf5-443a-b0f4-1387e5bb0fe9 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86555180 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_ escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.chip_sw _alert_handler_lpg_sleep_mode_alerts.86555180 |
| Directory | /workspace/25.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/25.chip_sw_all_escalation_resets.415491646 |
| Short name | T324 |
| Test name | |
| Test status | |
| Simulation time | 6266194920 ps |
| CPU time | 968.42 seconds |
| Started | Jun 29 08:08:29 PM PDT 24 |
| Finished | Jun 29 08:24:38 PM PDT 24 |
| Peak memory | 643860 kb |
| Host | smart-da4ce119-c631-4086-8587-2d314f9c99b3 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 415491646 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.chip_sw_all_escalation_resets.415491646 |
| Directory | /workspace/25.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/29.chip_sw_alert_handler_lpg_sleep_mode_alerts.3774627890 |
| Short name | T712 |
| Test name | |
| Test status | |
| Simulation time | 3324453400 ps |
| CPU time | 516.1 seconds |
| Started | Jun 29 08:09:34 PM PDT 24 |
| Finished | Jun 29 08:18:11 PM PDT 24 |
| Peak memory | 642176 kb |
| Host | smart-4767f774-1f28-4871-bb1b-47d5f508a03f |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3774627890 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.chip_ sw_alert_handler_lpg_sleep_mode_alerts.3774627890 |
| Directory | /workspace/29.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/29.chip_sw_all_escalation_resets.1863361965 |
| Short name | T741 |
| Test name | |
| Test status | |
| Simulation time | 4457073066 ps |
| CPU time | 641.38 seconds |
| Started | Jun 29 08:09:47 PM PDT 24 |
| Finished | Jun 29 08:20:29 PM PDT 24 |
| Peak memory | 643376 kb |
| Host | smart-0b873587-f42d-4926-8611-9f9ec0ff6d2b |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 1863361965 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.chip_sw_all_escalation_resets.1863361965 |
| Directory | /workspace/29.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/3.chip_sw_aon_timer_sleep_wdog_sleep_pause.3865404245 |
| Short name | T1245 |
| Test name | |
| Test status | |
| Simulation time | 6323144984 ps |
| CPU time | 395.12 seconds |
| Started | Jun 29 08:03:39 PM PDT 24 |
| Finished | Jun 29 08:10:15 PM PDT 24 |
| Peak memory | 609248 kb |
| Host | smart-fc518431-4375-47cd-94de-24fd0ce986f3 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=aon_timer_sleep_wdog_sleep_pause_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=3865404245 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.chip_sw_aon_timer_sleep_wdog_sleep_pause.3865404245 |
| Directory | /workspace/3.chip_sw_aon_timer_sleep_wdog_sleep_pause/latest |
| Test location | /workspace/coverage/default/3.chip_sw_csrng_edn_concurrency.3813386314 |
| Short name | T427 |
| Test name | |
| Test status | |
| Simulation time | 22258498532 ps |
| CPU time | 5613.98 seconds |
| Started | Jun 29 08:04:19 PM PDT 24 |
| Finished | Jun 29 09:37:53 PM PDT 24 |
| Peak memory | 608384 kb |
| Host | smart-0f6d53a0-364c-4cbb-922a-c96ab5ef51f4 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=140_000_000 +rng_srate_value_min=15 +rng_srate_value_max=20 +sw_build_device=sim_dv +sw_images=csrng_edn_c oncurrency_test:1:new_rules,test_rom:0 +accelerate_cold_power_up_time=3 +accelerate_regulators_power_up_time=2 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3813386314 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd b -cm_log /dev/null -cm_name 3.chip_sw_csrng_edn_concurrency.3813386314 |
| Directory | /workspace/3.chip_sw_csrng_edn_concurrency/latest |
| Test location | /workspace/coverage/default/3.chip_sw_data_integrity_escalation.2912472645 |
| Short name | T254 |
| Test name | |
| Test status | |
| Simulation time | 5257724436 ps |
| CPU time | 909.98 seconds |
| Started | Jun 29 08:03:31 PM PDT 24 |
| Finished | Jun 29 08:18:41 PM PDT 24 |
| Peak memory | 608524 kb |
| Host | smart-74bbcb68-ecba-4652-901a-0d6740beaad7 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=data_integrity_escalation_reset_test:1:new_rules,test_ro m:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=2912472645 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_data_integrity_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.chip_sw_data_integrity_escalation.2912472645 |
| Directory | /workspace/3.chip_sw_data_integrity_escalation/latest |
| Test location | /workspace/coverage/default/3.chip_sw_lc_ctrl_transition.2982536229 |
| Short name | T976 |
| Test name | |
| Test status | |
| Simulation time | 13715428904 ps |
| CPU time | 947.13 seconds |
| Started | Jun 29 08:03:58 PM PDT 24 |
| Finished | Jun 29 08:19:45 PM PDT 24 |
| Peak memory | 619152 kb |
| Host | smart-f644dfae-4f70-4147-9d7b-2deadec3824d |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=lc_ctrl_transition_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2982536229 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_transition_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau lt.vdb -cm_log /dev/null -cm_name 3.chip_sw_lc_ctrl_transition.2982536229 |
| Directory | /workspace/3.chip_sw_lc_ctrl_transition/latest |
| Test location | /workspace/coverage/default/3.chip_sw_uart_rand_baudrate.856757054 |
| Short name | T896 |
| Test name | |
| Test status | |
| Simulation time | 4584634968 ps |
| CPU time | 767.89 seconds |
| Started | Jun 29 08:03:57 PM PDT 24 |
| Finished | Jun 29 08:16:46 PM PDT 24 |
| Peak memory | 618856 kb |
| Host | smart-5c56bb3f-6449-4746-ba3a-b2f3b60ab105 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=856757054 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.chip_sw_uart_rand_baudrate.856757054 |
| Directory | /workspace/3.chip_sw_uart_rand_baudrate/latest |
| Test location | /workspace/coverage/default/3.chip_sw_uart_tx_rx.1693212596 |
| Short name | T891 |
| Test name | |
| Test status | |
| Simulation time | 4421244604 ps |
| CPU time | 648.12 seconds |
| Started | Jun 29 08:03:04 PM PDT 24 |
| Finished | Jun 29 08:13:52 PM PDT 24 |
| Peak memory | 624044 kb |
| Host | smart-60e46d94-b12c-4cfb-b0eb-7c7504199b9e |
| User | root |
| Command | /workspace/default/simv +uart_idx=0 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1693212596 -a ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/default.vdb -cm_log /dev/null -cm_name 3.chip_sw_uart_tx_rx.1693212596 |
| Directory | /workspace/3.chip_sw_uart_tx_rx/latest |
| Test location | /workspace/coverage/default/3.chip_sw_uart_tx_rx_alt_clk_freq.4094811807 |
| Short name | T1099 |
| Test name | |
| Test status | |
| Simulation time | 8179978472 ps |
| CPU time | 1653.92 seconds |
| Started | Jun 29 08:04:34 PM PDT 24 |
| Finished | Jun 29 08:32:08 PM PDT 24 |
| Peak memory | 620424 kb |
| Host | smart-396f3ffd-18fa-4a61-8034-e9202b1ef7ec |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=80_000_000 +chip_clock_source=ChipClockSourceExternal96Mhz +calibrate_usb_clk=1 +sw_build_device=sim_dv +s w_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4094811807 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_b audrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.chip_sw_uart_tx_rx _alt_clk_freq.4094811807 |
| Directory | /workspace/3.chip_sw_uart_tx_rx_alt_clk_freq/latest |
| Test location | /workspace/coverage/default/3.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.756693764 |
| Short name | T1087 |
| Test name | |
| Test status | |
| Simulation time | 3917946586 ps |
| CPU time | 482.34 seconds |
| Started | Jun 29 08:03:40 PM PDT 24 |
| Finished | Jun 29 08:11:44 PM PDT 24 |
| Peak memory | 620440 kb |
| Host | smart-df4f2e42-705d-46bd-99bc-8bf03f5c5466 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +chip_clock_source=ChipClockSourceExternal48Mhz +sw_build_device=sim_dv +s w_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=756693764 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_ba udrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.chip_sw_uart_tx_rx_ alt_clk_freq_low_speed.756693764 |
| Directory | /workspace/3.chip_sw_uart_tx_rx_alt_clk_freq_low_speed/latest |
| Test location | /workspace/coverage/default/3.chip_sw_uart_tx_rx_idx1.727587073 |
| Short name | T1092 |
| Test name | |
| Test status | |
| Simulation time | 4677127204 ps |
| CPU time | 833.54 seconds |
| Started | Jun 29 08:06:27 PM PDT 24 |
| Finished | Jun 29 08:20:22 PM PDT 24 |
| Peak memory | 615880 kb |
| Host | smart-09694906-b081-4cc9-aa4b-bbdc327adc37 |
| User | root |
| Command | /workspace/default/simv +uart_idx=1 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=727587073 -as sert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac e/coverage/default.vdb -cm_log /dev/null -cm_name 3.chip_sw_uart_tx_rx_idx1.727587073 |
| Directory | /workspace/3.chip_sw_uart_tx_rx_idx1/latest |
| Test location | /workspace/coverage/default/3.chip_sw_uart_tx_rx_idx2.36184588 |
| Short name | T1145 |
| Test name | |
| Test status | |
| Simulation time | 4064384444 ps |
| CPU time | 629.91 seconds |
| Started | Jun 29 08:03:44 PM PDT 24 |
| Finished | Jun 29 08:14:15 PM PDT 24 |
| Peak memory | 615884 kb |
| Host | smart-afaf12ad-559a-49eb-b5bc-431ff03ccb7e |
| User | root |
| Command | /workspace/default/simv +uart_idx=2 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36184588 -ass ert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace /coverage/default.vdb -cm_log /dev/null -cm_name 3.chip_sw_uart_tx_rx_idx2.36184588 |
| Directory | /workspace/3.chip_sw_uart_tx_rx_idx2/latest |
| Test location | /workspace/coverage/default/3.chip_sw_uart_tx_rx_idx3.1233570676 |
| Short name | T1124 |
| Test name | |
| Test status | |
| Simulation time | 4734023560 ps |
| CPU time | 740.28 seconds |
| Started | Jun 29 08:02:31 PM PDT 24 |
| Finished | Jun 29 08:14:51 PM PDT 24 |
| Peak memory | 615848 kb |
| Host | smart-d18a2149-f31f-4e97-9eb4-4f1a4f015d17 |
| User | root |
| Command | /workspace/default/simv +uart_idx=3 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1233570676 -a ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/default.vdb -cm_log /dev/null -cm_name 3.chip_sw_uart_tx_rx_idx3.1233570676 |
| Directory | /workspace/3.chip_sw_uart_tx_rx_idx3/latest |
| Test location | /workspace/coverage/default/3.chip_tap_straps_dev.1864283242 |
| Short name | T643 |
| Test name | |
| Test status | |
| Simulation time | 9164233116 ps |
| CPU time | 999.01 seconds |
| Started | Jun 29 08:02:19 PM PDT 24 |
| Finished | Jun 29 08:18:58 PM PDT 24 |
| Peak memory | 620320 kb |
| Host | smart-41619b5b-9395-480f-b221-e416dc1deff5 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStDev +create_jtag_riscv_map=1 +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:test_in_rom: new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=1864283242 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_tap_straps_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.chip_tap_straps_dev.1864283242 |
| Directory | /workspace/3.chip_tap_straps_dev/latest |
| Test location | /workspace/coverage/default/3.chip_tap_straps_prod.670714038 |
| Short name | T1213 |
| Test name | |
| Test status | |
| Simulation time | 2656391573 ps |
| CPU time | 171.89 seconds |
| Started | Jun 29 08:03:16 PM PDT 24 |
| Finished | Jun 29 08:06:09 PM PDT 24 |
| Peak memory | 617092 kb |
| Host | smart-5e20303c-8377-45f6-b036-16d7ef5ccd7f |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStProd +create_jtag_riscv_map=1 +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:test_in_rom :new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=670714038 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_tap_straps_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.chip_tap_straps_prod.670714038 |
| Directory | /workspace/3.chip_tap_straps_prod/latest |
| Test location | /workspace/coverage/default/3.chip_tap_straps_rma.453341668 |
| Short name | T67 |
| Test name | |
| Test status | |
| Simulation time | 6115529311 ps |
| CPU time | 579.38 seconds |
| Started | Jun 29 08:02:31 PM PDT 24 |
| Finished | Jun 29 08:12:10 PM PDT 24 |
| Peak memory | 619628 kb |
| Host | smart-39c0cd6d-93d3-48ff-b8f5-f8fde07c3e41 |
| User | root |
| Command | /workspace/default/simv +create_jtag_riscv_map=1 +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:test_in_rom:new_rules +cdc_instrumentation _enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=453341668 -ass ert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_tap_straps_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co verage/default.vdb -cm_log /dev/null -cm_name 3.chip_tap_straps_rma.453341668 |
| Directory | /workspace/3.chip_tap_straps_rma/latest |
| Test location | /workspace/coverage/default/3.chip_tap_straps_testunlock0.751513133 |
| Short name | T1074 |
| Test name | |
| Test status | |
| Simulation time | 14486835453 ps |
| CPU time | 1385.73 seconds |
| Started | Jun 29 08:03:44 PM PDT 24 |
| Finished | Jun 29 08:26:51 PM PDT 24 |
| Peak memory | 620380 kb |
| Host | smart-83b7dab6-fff6-4f8b-823a-1c472268a4be |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStTestUnlocked0 +create_jtag_riscv_map=1 +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:te st_in_rom:new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=751513133 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_tap_straps_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.chip_tap_straps_testunlock0.751513133 |
| Directory | /workspace/3.chip_tap_straps_testunlock0/latest |
| Test location | /workspace/coverage/default/31.chip_sw_all_escalation_resets.2582919296 |
| Short name | T352 |
| Test name | |
| Test status | |
| Simulation time | 5555036506 ps |
| CPU time | 836.78 seconds |
| Started | Jun 29 08:08:09 PM PDT 24 |
| Finished | Jun 29 08:22:08 PM PDT 24 |
| Peak memory | 643352 kb |
| Host | smart-ff1eb4e0-80fa-4434-9325-58adbe5de2af |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 2582919296 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.chip_sw_all_escalation_resets.2582919296 |
| Directory | /workspace/31.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/32.chip_sw_alert_handler_lpg_sleep_mode_alerts.2283139196 |
| Short name | T280 |
| Test name | |
| Test status | |
| Simulation time | 3851439716 ps |
| CPU time | 472 seconds |
| Started | Jun 29 08:08:56 PM PDT 24 |
| Finished | Jun 29 08:16:48 PM PDT 24 |
| Peak memory | 647192 kb |
| Host | smart-6fbcb2ac-60cd-46e8-be2c-ff94d545d65e |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2283139196 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.chip_ sw_alert_handler_lpg_sleep_mode_alerts.2283139196 |
| Directory | /workspace/32.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/33.chip_sw_all_escalation_resets.3337695796 |
| Short name | T739 |
| Test name | |
| Test status | |
| Simulation time | 4984253840 ps |
| CPU time | 889.19 seconds |
| Started | Jun 29 08:08:47 PM PDT 24 |
| Finished | Jun 29 08:23:37 PM PDT 24 |
| Peak memory | 647948 kb |
| Host | smart-98f4e74e-e013-408b-93e6-4a25b6381010 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 3337695796 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.chip_sw_all_escalation_resets.3337695796 |
| Directory | /workspace/33.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/34.chip_sw_alert_handler_lpg_sleep_mode_alerts.615355078 |
| Short name | T888 |
| Test name | |
| Test status | |
| Simulation time | 3804880956 ps |
| CPU time | 487.13 seconds |
| Started | Jun 29 08:09:57 PM PDT 24 |
| Finished | Jun 29 08:18:05 PM PDT 24 |
| Peak memory | 615180 kb |
| Host | smart-2453ac62-ae51-4c73-a8ea-bf4ffdafe9d7 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=615355078 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all _escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.chip_s w_alert_handler_lpg_sleep_mode_alerts.615355078 |
| Directory | /workspace/34.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/35.chip_sw_alert_handler_lpg_sleep_mode_alerts.2002469945 |
| Short name | T1068 |
| Test name | |
| Test status | |
| Simulation time | 3715006520 ps |
| CPU time | 481.69 seconds |
| Started | Jun 29 08:09:49 PM PDT 24 |
| Finished | Jun 29 08:17:51 PM PDT 24 |
| Peak memory | 616696 kb |
| Host | smart-c8b6c98b-6f83-47d1-aa56-e659091aac99 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2002469945 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.chip_ sw_alert_handler_lpg_sleep_mode_alerts.2002469945 |
| Directory | /workspace/35.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/36.chip_sw_all_escalation_resets.3403939640 |
| Short name | T1120 |
| Test name | |
| Test status | |
| Simulation time | 5613595484 ps |
| CPU time | 588.75 seconds |
| Started | Jun 29 08:08:50 PM PDT 24 |
| Finished | Jun 29 08:18:39 PM PDT 24 |
| Peak memory | 643424 kb |
| Host | smart-7dbb268b-0bdd-4268-b8dc-0ee9edad4458 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 3403939640 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.chip_sw_all_escalation_resets.3403939640 |
| Directory | /workspace/36.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/37.chip_sw_alert_handler_lpg_sleep_mode_alerts.2367475885 |
| Short name | T1142 |
| Test name | |
| Test status | |
| Simulation time | 3309766840 ps |
| CPU time | 360.32 seconds |
| Started | Jun 29 08:09:01 PM PDT 24 |
| Finished | Jun 29 08:15:02 PM PDT 24 |
| Peak memory | 616716 kb |
| Host | smart-492b6c71-8d12-4b1d-901e-8e2cb27e92a5 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2367475885 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.chip_ sw_alert_handler_lpg_sleep_mode_alerts.2367475885 |
| Directory | /workspace/37.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/38.chip_sw_alert_handler_lpg_sleep_mode_alerts.592305825 |
| Short name | T284 |
| Test name | |
| Test status | |
| Simulation time | 3501475772 ps |
| CPU time | 452.72 seconds |
| Started | Jun 29 08:11:16 PM PDT 24 |
| Finished | Jun 29 08:18:50 PM PDT 24 |
| Peak memory | 647228 kb |
| Host | smart-b3a6cd85-de4f-4d6d-9607-62d5741282fc |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=592305825 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all _escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.chip_s w_alert_handler_lpg_sleep_mode_alerts.592305825 |
| Directory | /workspace/38.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/38.chip_sw_all_escalation_resets.1800998136 |
| Short name | T196 |
| Test name | |
| Test status | |
| Simulation time | 5413642350 ps |
| CPU time | 613.66 seconds |
| Started | Jun 29 08:08:45 PM PDT 24 |
| Finished | Jun 29 08:18:59 PM PDT 24 |
| Peak memory | 643456 kb |
| Host | smart-edb03769-e431-4969-bfdb-fe329849ebd1 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 1800998136 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.chip_sw_all_escalation_resets.1800998136 |
| Directory | /workspace/38.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/39.chip_sw_alert_handler_lpg_sleep_mode_alerts.3993139655 |
| Short name | T726 |
| Test name | |
| Test status | |
| Simulation time | 3295202900 ps |
| CPU time | 439.13 seconds |
| Started | Jun 29 08:09:35 PM PDT 24 |
| Finished | Jun 29 08:16:55 PM PDT 24 |
| Peak memory | 642268 kb |
| Host | smart-62bfdce0-1ebc-403d-b6bd-f3abf1ad361b |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3993139655 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.chip_ sw_alert_handler_lpg_sleep_mode_alerts.3993139655 |
| Directory | /workspace/39.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/39.chip_sw_all_escalation_resets.1009937685 |
| Short name | T677 |
| Test name | |
| Test status | |
| Simulation time | 4644801166 ps |
| CPU time | 729.17 seconds |
| Started | Jun 29 08:11:20 PM PDT 24 |
| Finished | Jun 29 08:23:30 PM PDT 24 |
| Peak memory | 647948 kb |
| Host | smart-740298c7-2bb8-44f0-b2be-3845d9f080a1 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 1009937685 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.chip_sw_all_escalation_resets.1009937685 |
| Directory | /workspace/39.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/4.chip_sw_alert_handler_lpg_sleep_mode_alerts.2983886571 |
| Short name | T735 |
| Test name | |
| Test status | |
| Simulation time | 3699396548 ps |
| CPU time | 379.04 seconds |
| Started | Jun 29 08:05:10 PM PDT 24 |
| Finished | Jun 29 08:11:30 PM PDT 24 |
| Peak memory | 647032 kb |
| Host | smart-96831c28-0115-4e90-b590-2c15b92d8cc6 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2983886571 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.chip_s w_alert_handler_lpg_sleep_mode_alerts.2983886571 |
| Directory | /workspace/4.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/4.chip_sw_all_escalation_resets.15656359 |
| Short name | T751 |
| Test name | |
| Test status | |
| Simulation time | 6193274338 ps |
| CPU time | 810.57 seconds |
| Started | Jun 29 08:05:01 PM PDT 24 |
| Finished | Jun 29 08:18:32 PM PDT 24 |
| Peak memory | 643372 kb |
| Host | smart-86d3d136-1a7e-492d-8e6c-8c2c29c01020 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 15656359 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.chip_sw_all_escalation_resets.15656359 |
| Directory | /workspace/4.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/4.chip_sw_aon_timer_sleep_wdog_sleep_pause.2893593821 |
| Short name | T92 |
| Test name | |
| Test status | |
| Simulation time | 7037995376 ps |
| CPU time | 491.55 seconds |
| Started | Jun 29 08:05:42 PM PDT 24 |
| Finished | Jun 29 08:13:54 PM PDT 24 |
| Peak memory | 609240 kb |
| Host | smart-3d9c1b4d-4d9a-46fb-ae15-b87520dc9acd |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=aon_timer_sleep_wdog_sleep_pause_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=2893593821 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.chip_sw_aon_timer_sleep_wdog_sleep_pause.2893593821 |
| Directory | /workspace/4.chip_sw_aon_timer_sleep_wdog_sleep_pause/latest |
| Test location | /workspace/coverage/default/4.chip_sw_lc_ctrl_transition.116248212 |
| Short name | T1174 |
| Test name | |
| Test status | |
| Simulation time | 7203240780 ps |
| CPU time | 548.2 seconds |
| Started | Jun 29 08:04:43 PM PDT 24 |
| Finished | Jun 29 08:13:52 PM PDT 24 |
| Peak memory | 619184 kb |
| Host | smart-c18b4bbe-ce0f-41f8-8643-6de34207c9c3 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=lc_ctrl_transition_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=116248212 -assert nopostproc +UVM_TEST NAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_transition_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul t.vdb -cm_log /dev/null -cm_name 4.chip_sw_lc_ctrl_transition.116248212 |
| Directory | /workspace/4.chip_sw_lc_ctrl_transition/latest |
| Test location | /workspace/coverage/default/4.chip_sw_sensor_ctrl_alert.3803940557 |
| Short name | T120 |
| Test name | |
| Test status | |
| Simulation time | 4659180808 ps |
| CPU time | 592.22 seconds |
| Started | Jun 29 08:05:04 PM PDT 24 |
| Finished | Jun 29 08:14:57 PM PDT 24 |
| Peak memory | 609192 kb |
| Host | smart-5ea9961a-c05e-465f-8a9b-22738b32c066 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=40_000_000 +sw_build_device=sim_dv +sw_images=sensor_ctrl_alert_test:1:new_rules,test_rom:0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38039405 57 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac e/coverage/default.vdb -cm_log /dev/null -cm_name 4.chip_sw_sensor_ctrl_alert.3803940557 |
| Directory | /workspace/4.chip_sw_sensor_ctrl_alert/latest |
| Test location | /workspace/coverage/default/4.chip_sw_uart_rand_baudrate.4126103786 |
| Short name | T999 |
| Test name | |
| Test status | |
| Simulation time | 9281660564 ps |
| CPU time | 2030.19 seconds |
| Started | Jun 29 08:04:08 PM PDT 24 |
| Finished | Jun 29 08:37:59 PM PDT 24 |
| Peak memory | 618892 kb |
| Host | smart-31bce6eb-ca86-460a-9d85-11fafdffa07a |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=4126103786 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.chip_sw_uart_rand_baudrate.4126103786 |
| Directory | /workspace/4.chip_sw_uart_rand_baudrate/latest |
| Test location | /workspace/coverage/default/4.chip_sw_uart_tx_rx.410356677 |
| Short name | T910 |
| Test name | |
| Test status | |
| Simulation time | 4345559056 ps |
| CPU time | 670.91 seconds |
| Started | Jun 29 08:04:54 PM PDT 24 |
| Finished | Jun 29 08:16:06 PM PDT 24 |
| Peak memory | 615888 kb |
| Host | smart-c3ad7e3c-8867-4596-9047-55418a929eb9 |
| User | root |
| Command | /workspace/default/simv +uart_idx=0 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=410356677 -as sert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac e/coverage/default.vdb -cm_log /dev/null -cm_name 4.chip_sw_uart_tx_rx.410356677 |
| Directory | /workspace/4.chip_sw_uart_tx_rx/latest |
| Test location | /workspace/coverage/default/4.chip_sw_uart_tx_rx_alt_clk_freq.2185553366 |
| Short name | T960 |
| Test name | |
| Test status | |
| Simulation time | 4201293104 ps |
| CPU time | 639.35 seconds |
| Started | Jun 29 08:04:33 PM PDT 24 |
| Finished | Jun 29 08:15:13 PM PDT 24 |
| Peak memory | 620440 kb |
| Host | smart-30097f5c-4c03-4d0c-bc00-9016be648844 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=80_000_000 +chip_clock_source=ChipClockSourceExternal96Mhz +calibrate_usb_clk=1 +sw_build_device=sim_dv +s w_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2185553366 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_b audrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.chip_sw_uart_tx_rx _alt_clk_freq.2185553366 |
| Directory | /workspace/4.chip_sw_uart_tx_rx_alt_clk_freq/latest |
| Test location | /workspace/coverage/default/4.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.762998250 |
| Short name | T1060 |
| Test name | |
| Test status | |
| Simulation time | 3376205671 ps |
| CPU time | 442.99 seconds |
| Started | Jun 29 08:04:15 PM PDT 24 |
| Finished | Jun 29 08:11:38 PM PDT 24 |
| Peak memory | 617616 kb |
| Host | smart-3b71e07f-d0cc-41d2-807c-a4ff8ac6c819 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +chip_clock_source=ChipClockSourceExternal48Mhz +sw_build_device=sim_dv +s w_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=762998250 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_ba udrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.chip_sw_uart_tx_rx_ alt_clk_freq_low_speed.762998250 |
| Directory | /workspace/4.chip_sw_uart_tx_rx_alt_clk_freq_low_speed/latest |
| Test location | /workspace/coverage/default/4.chip_sw_uart_tx_rx_idx1.3292670475 |
| Short name | T331 |
| Test name | |
| Test status | |
| Simulation time | 3991461132 ps |
| CPU time | 598.38 seconds |
| Started | Jun 29 08:04:18 PM PDT 24 |
| Finished | Jun 29 08:14:17 PM PDT 24 |
| Peak memory | 615888 kb |
| Host | smart-63ebc7e0-ff2a-4abb-9542-101c3ec199a5 |
| User | root |
| Command | /workspace/default/simv +uart_idx=1 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3292670475 -a ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/default.vdb -cm_log /dev/null -cm_name 4.chip_sw_uart_tx_rx_idx1.3292670475 |
| Directory | /workspace/4.chip_sw_uart_tx_rx_idx1/latest |
| Test location | /workspace/coverage/default/4.chip_sw_uart_tx_rx_idx2.3443146940 |
| Short name | T137 |
| Test name | |
| Test status | |
| Simulation time | 4371528080 ps |
| CPU time | 611.37 seconds |
| Started | Jun 29 08:04:18 PM PDT 24 |
| Finished | Jun 29 08:14:30 PM PDT 24 |
| Peak memory | 615872 kb |
| Host | smart-84847ad8-3a0b-471c-ba08-88c2fff349a9 |
| User | root |
| Command | /workspace/default/simv +uart_idx=2 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3443146940 -a ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/default.vdb -cm_log /dev/null -cm_name 4.chip_sw_uart_tx_rx_idx2.3443146940 |
| Directory | /workspace/4.chip_sw_uart_tx_rx_idx2/latest |
| Test location | /workspace/coverage/default/4.chip_sw_uart_tx_rx_idx3.2095697141 |
| Short name | T879 |
| Test name | |
| Test status | |
| Simulation time | 4310018956 ps |
| CPU time | 572.21 seconds |
| Started | Jun 29 08:06:16 PM PDT 24 |
| Finished | Jun 29 08:15:48 PM PDT 24 |
| Peak memory | 615868 kb |
| Host | smart-2eb9d12d-3df5-47d5-a036-ff632529cebd |
| User | root |
| Command | /workspace/default/simv +uart_idx=3 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2095697141 -a ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/default.vdb -cm_log /dev/null -cm_name 4.chip_sw_uart_tx_rx_idx3.2095697141 |
| Directory | /workspace/4.chip_sw_uart_tx_rx_idx3/latest |
| Test location | /workspace/coverage/default/4.chip_tap_straps_dev.3879062726 |
| Short name | T1243 |
| Test name | |
| Test status | |
| Simulation time | 17119317130 ps |
| CPU time | 1940.23 seconds |
| Started | Jun 29 08:04:36 PM PDT 24 |
| Finished | Jun 29 08:36:57 PM PDT 24 |
| Peak memory | 618152 kb |
| Host | smart-512b7939-8e26-4297-bd17-2a5e51ea4c6e |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStDev +create_jtag_riscv_map=1 +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:test_in_rom: new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=3879062726 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_tap_straps_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.chip_tap_straps_dev.3879062726 |
| Directory | /workspace/4.chip_tap_straps_dev/latest |
| Test location | /workspace/coverage/default/4.chip_tap_straps_prod.3902956147 |
| Short name | T194 |
| Test name | |
| Test status | |
| Simulation time | 2617041192 ps |
| CPU time | 181.08 seconds |
| Started | Jun 29 08:04:33 PM PDT 24 |
| Finished | Jun 29 08:07:35 PM PDT 24 |
| Peak memory | 618504 kb |
| Host | smart-50ec2978-cc9d-4a50-be72-a1530dd8d8d8 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStProd +create_jtag_riscv_map=1 +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:test_in_rom :new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3902956147 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_tap_straps_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.chip_tap_straps_prod.3902956147 |
| Directory | /workspace/4.chip_tap_straps_prod/latest |
| Test location | /workspace/coverage/default/4.chip_tap_straps_rma.1698889321 |
| Short name | T1093 |
| Test name | |
| Test status | |
| Simulation time | 3901682632 ps |
| CPU time | 415.39 seconds |
| Started | Jun 29 08:03:55 PM PDT 24 |
| Finished | Jun 29 08:10:51 PM PDT 24 |
| Peak memory | 620324 kb |
| Host | smart-e7b5ab33-e765-4043-a6c9-8be7019945bb |
| User | root |
| Command | /workspace/default/simv +create_jtag_riscv_map=1 +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:test_in_rom:new_rules +cdc_instrumentation _enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1698889321 -as sert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_tap_straps_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/c overage/default.vdb -cm_log /dev/null -cm_name 4.chip_tap_straps_rma.1698889321 |
| Directory | /workspace/4.chip_tap_straps_rma/latest |
| Test location | /workspace/coverage/default/4.chip_tap_straps_testunlock0.3607468213 |
| Short name | T64 |
| Test name | |
| Test status | |
| Simulation time | 3560249834 ps |
| CPU time | 322.79 seconds |
| Started | Jun 29 08:04:34 PM PDT 24 |
| Finished | Jun 29 08:09:57 PM PDT 24 |
| Peak memory | 620420 kb |
| Host | smart-8d99173c-4b1d-4fc5-8a0e-622279f577ee |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStTestUnlocked0 +create_jtag_riscv_map=1 +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:te st_in_rom:new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3607468213 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_tap_straps_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.chip_tap_straps_testunlock0.3607468213 |
| Directory | /workspace/4.chip_tap_straps_testunlock0/latest |
| Test location | /workspace/coverage/default/40.chip_sw_alert_handler_lpg_sleep_mode_alerts.1289979333 |
| Short name | T763 |
| Test name | |
| Test status | |
| Simulation time | 3911515488 ps |
| CPU time | 401.2 seconds |
| Started | Jun 29 08:09:10 PM PDT 24 |
| Finished | Jun 29 08:15:51 PM PDT 24 |
| Peak memory | 647136 kb |
| Host | smart-40454bb5-c52f-4e68-8a70-76ba4df7606a |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1289979333 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.chip_ sw_alert_handler_lpg_sleep_mode_alerts.1289979333 |
| Directory | /workspace/40.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/43.chip_sw_alert_handler_lpg_sleep_mode_alerts.733030775 |
| Short name | T399 |
| Test name | |
| Test status | |
| Simulation time | 3027735594 ps |
| CPU time | 437.24 seconds |
| Started | Jun 29 08:09:59 PM PDT 24 |
| Finished | Jun 29 08:17:16 PM PDT 24 |
| Peak memory | 642260 kb |
| Host | smart-e19a6e54-40a4-465c-a7fa-8968e846f04f |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=733030775 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all _escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.chip_s w_alert_handler_lpg_sleep_mode_alerts.733030775 |
| Directory | /workspace/43.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/44.chip_sw_alert_handler_lpg_sleep_mode_alerts.3286711164 |
| Short name | T720 |
| Test name | |
| Test status | |
| Simulation time | 3618194472 ps |
| CPU time | 367.01 seconds |
| Started | Jun 29 08:10:31 PM PDT 24 |
| Finished | Jun 29 08:16:39 PM PDT 24 |
| Peak memory | 647136 kb |
| Host | smart-f0bed137-71e3-4ca2-b0b0-ab3a55b4d129 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3286711164 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.chip_ sw_alert_handler_lpg_sleep_mode_alerts.3286711164 |
| Directory | /workspace/44.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/44.chip_sw_all_escalation_resets.829102066 |
| Short name | T695 |
| Test name | |
| Test status | |
| Simulation time | 5212671762 ps |
| CPU time | 616.24 seconds |
| Started | Jun 29 08:11:06 PM PDT 24 |
| Finished | Jun 29 08:21:23 PM PDT 24 |
| Peak memory | 647888 kb |
| Host | smart-522f9f97-c978-4182-9a5a-a4d6722206ea |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 829102066 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.chip_sw_all_escalation_resets.829102066 |
| Directory | /workspace/44.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/45.chip_sw_alert_handler_lpg_sleep_mode_alerts.2313894294 |
| Short name | T698 |
| Test name | |
| Test status | |
| Simulation time | 3240419448 ps |
| CPU time | 381.48 seconds |
| Started | Jun 29 08:09:11 PM PDT 24 |
| Finished | Jun 29 08:15:33 PM PDT 24 |
| Peak memory | 615180 kb |
| Host | smart-8e35b9c3-a3a7-466e-953c-17e74e39840f |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2313894294 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.chip_ sw_alert_handler_lpg_sleep_mode_alerts.2313894294 |
| Directory | /workspace/45.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/45.chip_sw_all_escalation_resets.3351459778 |
| Short name | T434 |
| Test name | |
| Test status | |
| Simulation time | 5728978838 ps |
| CPU time | 604.39 seconds |
| Started | Jun 29 08:11:14 PM PDT 24 |
| Finished | Jun 29 08:21:19 PM PDT 24 |
| Peak memory | 643368 kb |
| Host | smart-39510f14-99ad-41bb-8cdb-6daf2798574f |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 3351459778 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.chip_sw_all_escalation_resets.3351459778 |
| Directory | /workspace/45.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/47.chip_sw_alert_handler_lpg_sleep_mode_alerts.1131639603 |
| Short name | T679 |
| Test name | |
| Test status | |
| Simulation time | 4132445800 ps |
| CPU time | 488.04 seconds |
| Started | Jun 29 08:10:36 PM PDT 24 |
| Finished | Jun 29 08:18:44 PM PDT 24 |
| Peak memory | 647072 kb |
| Host | smart-94e78a03-1b95-4f80-a7ba-f2550e12b742 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1131639603 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.chip_ sw_alert_handler_lpg_sleep_mode_alerts.1131639603 |
| Directory | /workspace/47.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/47.chip_sw_all_escalation_resets.2822601286 |
| Short name | T753 |
| Test name | |
| Test status | |
| Simulation time | 6208142024 ps |
| CPU time | 701.91 seconds |
| Started | Jun 29 08:10:06 PM PDT 24 |
| Finished | Jun 29 08:21:48 PM PDT 24 |
| Peak memory | 647844 kb |
| Host | smart-cb2ef482-dfb7-4f3f-9c07-43c57d7d2b4d |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 2822601286 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.chip_sw_all_escalation_resets.2822601286 |
| Directory | /workspace/47.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/48.chip_sw_alert_handler_lpg_sleep_mode_alerts.599142731 |
| Short name | T991 |
| Test name | |
| Test status | |
| Simulation time | 3646849804 ps |
| CPU time | 402.34 seconds |
| Started | Jun 29 08:10:08 PM PDT 24 |
| Finished | Jun 29 08:16:51 PM PDT 24 |
| Peak memory | 647060 kb |
| Host | smart-4e389597-9dd2-4773-967a-3aa4d45c8b8d |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=599142731 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all _escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.chip_s w_alert_handler_lpg_sleep_mode_alerts.599142731 |
| Directory | /workspace/48.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/49.chip_sw_alert_handler_lpg_sleep_mode_alerts.1966848300 |
| Short name | T279 |
| Test name | |
| Test status | |
| Simulation time | 3133968384 ps |
| CPU time | 431.64 seconds |
| Started | Jun 29 08:11:15 PM PDT 24 |
| Finished | Jun 29 08:18:27 PM PDT 24 |
| Peak memory | 647180 kb |
| Host | smart-016abad2-2035-4512-a8b1-77555ca31a47 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1966848300 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.chip_ sw_alert_handler_lpg_sleep_mode_alerts.1966848300 |
| Directory | /workspace/49.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/49.chip_sw_all_escalation_resets.1842820342 |
| Short name | T690 |
| Test name | |
| Test status | |
| Simulation time | 4960289964 ps |
| CPU time | 719.32 seconds |
| Started | Jun 29 08:10:04 PM PDT 24 |
| Finished | Jun 29 08:22:04 PM PDT 24 |
| Peak memory | 647856 kb |
| Host | smart-3c7d2cca-0e9e-4c60-8aed-fd4676b57c6c |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 1842820342 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.chip_sw_all_escalation_resets.1842820342 |
| Directory | /workspace/49.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/5.chip_sw_alert_handler_lpg_sleep_mode_alerts.2029842467 |
| Short name | T740 |
| Test name | |
| Test status | |
| Simulation time | 4265406050 ps |
| CPU time | 410.55 seconds |
| Started | Jun 29 08:05:18 PM PDT 24 |
| Finished | Jun 29 08:12:09 PM PDT 24 |
| Peak memory | 647036 kb |
| Host | smart-8e138a44-d3d1-4384-a72c-97081eef0244 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2029842467 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.chip_s w_alert_handler_lpg_sleep_mode_alerts.2029842467 |
| Directory | /workspace/5.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/5.chip_sw_csrng_edn_concurrency.292995652 |
| Short name | T992 |
| Test name | |
| Test status | |
| Simulation time | 17330739412 ps |
| CPU time | 3805.22 seconds |
| Started | Jun 29 08:04:39 PM PDT 24 |
| Finished | Jun 29 09:08:05 PM PDT 24 |
| Peak memory | 608388 kb |
| Host | smart-4a2d7124-4b8a-4579-85c3-9d8fb574fbde |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=140_000_000 +rng_srate_value_min=15 +rng_srate_value_max=20 +sw_build_device=sim_dv +sw_images=csrng_edn_c oncurrency_test:1:new_rules,test_rom:0 +accelerate_cold_power_up_time=3 +accelerate_regulators_power_up_time=2 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=292995652 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.chip_sw_csrng_edn_concurrency.292995652 |
| Directory | /workspace/5.chip_sw_csrng_edn_concurrency/latest |
| Test location | /workspace/coverage/default/5.chip_sw_data_integrity_escalation.2217677260 |
| Short name | T405 |
| Test name | |
| Test status | |
| Simulation time | 5138514028 ps |
| CPU time | 666.87 seconds |
| Started | Jun 29 08:05:10 PM PDT 24 |
| Finished | Jun 29 08:16:18 PM PDT 24 |
| Peak memory | 609260 kb |
| Host | smart-48f61b46-0162-4612-b664-761408493b89 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=data_integrity_escalation_reset_test:1:new_rules,test_ro m:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=2217677260 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_data_integrity_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.chip_sw_data_integrity_escalation.2217677260 |
| Directory | /workspace/5.chip_sw_data_integrity_escalation/latest |
| Test location | /workspace/coverage/default/5.chip_sw_lc_ctrl_transition.1878919741 |
| Short name | T344 |
| Test name | |
| Test status | |
| Simulation time | 12889028337 ps |
| CPU time | 1006.15 seconds |
| Started | Jun 29 08:04:36 PM PDT 24 |
| Finished | Jun 29 08:21:23 PM PDT 24 |
| Peak memory | 619188 kb |
| Host | smart-1186fc08-8053-4769-b92e-3e6bfd565dc1 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=lc_ctrl_transition_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1878919741 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_transition_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau lt.vdb -cm_log /dev/null -cm_name 5.chip_sw_lc_ctrl_transition.1878919741 |
| Directory | /workspace/5.chip_sw_lc_ctrl_transition/latest |
| Test location | /workspace/coverage/default/5.chip_sw_uart_rand_baudrate.3020002139 |
| Short name | T1039 |
| Test name | |
| Test status | |
| Simulation time | 13530731464 ps |
| CPU time | 2196.9 seconds |
| Started | Jun 29 08:05:54 PM PDT 24 |
| Finished | Jun 29 08:42:31 PM PDT 24 |
| Peak memory | 618876 kb |
| Host | smart-f64fe9ad-1879-420b-9c2b-dd4bda57efe1 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=3020002139 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.chip_sw_uart_rand_baudrate.3020002139 |
| Directory | /workspace/5.chip_sw_uart_rand_baudrate/latest |
| Test location | /workspace/coverage/default/50.chip_sw_alert_handler_lpg_sleep_mode_alerts.3653162477 |
| Short name | T916 |
| Test name | |
| Test status | |
| Simulation time | 3238347782 ps |
| CPU time | 391.66 seconds |
| Started | Jun 29 08:10:39 PM PDT 24 |
| Finished | Jun 29 08:17:11 PM PDT 24 |
| Peak memory | 616700 kb |
| Host | smart-ad3fb8fd-2164-4684-9cd2-9e87453ec965 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3653162477 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.chip_ sw_alert_handler_lpg_sleep_mode_alerts.3653162477 |
| Directory | /workspace/50.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/50.chip_sw_all_escalation_resets.2585163368 |
| Short name | T650 |
| Test name | |
| Test status | |
| Simulation time | 4944061560 ps |
| CPU time | 606.54 seconds |
| Started | Jun 29 08:09:26 PM PDT 24 |
| Finished | Jun 29 08:19:34 PM PDT 24 |
| Peak memory | 608672 kb |
| Host | smart-c015d163-67f5-443f-aea3-f64a0bd4cb78 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 2585163368 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.chip_sw_all_escalation_resets.2585163368 |
| Directory | /workspace/50.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/51.chip_sw_alert_handler_lpg_sleep_mode_alerts.3272105487 |
| Short name | T403 |
| Test name | |
| Test status | |
| Simulation time | 3405834688 ps |
| CPU time | 409.59 seconds |
| Started | Jun 29 08:15:56 PM PDT 24 |
| Finished | Jun 29 08:22:47 PM PDT 24 |
| Peak memory | 647068 kb |
| Host | smart-9e42633d-16da-4b3d-b3ea-86e44b043400 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3272105487 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.chip_ sw_alert_handler_lpg_sleep_mode_alerts.3272105487 |
| Directory | /workspace/51.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/51.chip_sw_all_escalation_resets.2175525015 |
| Short name | T683 |
| Test name | |
| Test status | |
| Simulation time | 5157202230 ps |
| CPU time | 820.77 seconds |
| Started | Jun 29 08:15:43 PM PDT 24 |
| Finished | Jun 29 08:29:26 PM PDT 24 |
| Peak memory | 643328 kb |
| Host | smart-a941cc37-143d-45fa-9ae3-b5f413cf5cc7 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 2175525015 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.chip_sw_all_escalation_resets.2175525015 |
| Directory | /workspace/51.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/52.chip_sw_alert_handler_lpg_sleep_mode_alerts.1254311397 |
| Short name | T1210 |
| Test name | |
| Test status | |
| Simulation time | 4281209862 ps |
| CPU time | 374.01 seconds |
| Started | Jun 29 08:15:21 PM PDT 24 |
| Finished | Jun 29 08:21:35 PM PDT 24 |
| Peak memory | 616744 kb |
| Host | smart-b3ad6c67-6aaf-4591-b2e4-56ce0443189f |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1254311397 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.chip_ sw_alert_handler_lpg_sleep_mode_alerts.1254311397 |
| Directory | /workspace/52.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/53.chip_sw_alert_handler_lpg_sleep_mode_alerts.69084053 |
| Short name | T1024 |
| Test name | |
| Test status | |
| Simulation time | 4552630964 ps |
| CPU time | 525.56 seconds |
| Started | Jun 29 08:10:37 PM PDT 24 |
| Finished | Jun 29 08:19:23 PM PDT 24 |
| Peak memory | 617000 kb |
| Host | smart-46e6b1f5-baa8-41d8-83c9-3aadde3dcbc5 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69084053 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_ escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.chip_sw _alert_handler_lpg_sleep_mode_alerts.69084053 |
| Directory | /workspace/53.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/53.chip_sw_all_escalation_resets.3353255509 |
| Short name | T355 |
| Test name | |
| Test status | |
| Simulation time | 6188751876 ps |
| CPU time | 712.13 seconds |
| Started | Jun 29 08:11:59 PM PDT 24 |
| Finished | Jun 29 08:23:52 PM PDT 24 |
| Peak memory | 647856 kb |
| Host | smart-2c2e3d16-70a6-49c4-8841-11e71ae7df75 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 3353255509 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.chip_sw_all_escalation_resets.3353255509 |
| Directory | /workspace/53.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/54.chip_sw_alert_handler_lpg_sleep_mode_alerts.77865605 |
| Short name | T681 |
| Test name | |
| Test status | |
| Simulation time | 4467552846 ps |
| CPU time | 387.93 seconds |
| Started | Jun 29 08:14:49 PM PDT 24 |
| Finished | Jun 29 08:21:17 PM PDT 24 |
| Peak memory | 647436 kb |
| Host | smart-6e93b529-9b3f-42a2-b9f6-c0f97753bd12 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77865605 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_ escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.chip_sw _alert_handler_lpg_sleep_mode_alerts.77865605 |
| Directory | /workspace/54.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/54.chip_sw_all_escalation_resets.3597289784 |
| Short name | T743 |
| Test name | |
| Test status | |
| Simulation time | 6543763432 ps |
| CPU time | 698.42 seconds |
| Started | Jun 29 08:11:13 PM PDT 24 |
| Finished | Jun 29 08:22:52 PM PDT 24 |
| Peak memory | 643520 kb |
| Host | smart-03a0c8af-dd69-49a8-8fd4-ed03acd5fc67 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 3597289784 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.chip_sw_all_escalation_resets.3597289784 |
| Directory | /workspace/54.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/55.chip_sw_all_escalation_resets.651761326 |
| Short name | T1007 |
| Test name | |
| Test status | |
| Simulation time | 5014501508 ps |
| CPU time | 669.97 seconds |
| Started | Jun 29 08:10:50 PM PDT 24 |
| Finished | Jun 29 08:22:00 PM PDT 24 |
| Peak memory | 648064 kb |
| Host | smart-59858086-7566-46be-b6b3-0f264bc6bbca |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 651761326 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.chip_sw_all_escalation_resets.651761326 |
| Directory | /workspace/55.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/56.chip_sw_alert_handler_lpg_sleep_mode_alerts.1231279756 |
| Short name | T761 |
| Test name | |
| Test status | |
| Simulation time | 3613496624 ps |
| CPU time | 409.2 seconds |
| Started | Jun 29 08:11:06 PM PDT 24 |
| Finished | Jun 29 08:17:56 PM PDT 24 |
| Peak memory | 647084 kb |
| Host | smart-7c2a7a83-93ae-4aec-a424-f88e5b24cdb4 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1231279756 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.chip_ sw_alert_handler_lpg_sleep_mode_alerts.1231279756 |
| Directory | /workspace/56.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/56.chip_sw_all_escalation_resets.4147036300 |
| Short name | T334 |
| Test name | |
| Test status | |
| Simulation time | 4630183832 ps |
| CPU time | 662.4 seconds |
| Started | Jun 29 08:10:34 PM PDT 24 |
| Finished | Jun 29 08:21:37 PM PDT 24 |
| Peak memory | 643328 kb |
| Host | smart-96116b72-ad4a-489d-a511-b992abcdaea2 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 4147036300 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.chip_sw_all_escalation_resets.4147036300 |
| Directory | /workspace/56.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/57.chip_sw_all_escalation_resets.3011944364 |
| Short name | T707 |
| Test name | |
| Test status | |
| Simulation time | 4247207864 ps |
| CPU time | 526.24 seconds |
| Started | Jun 29 08:10:12 PM PDT 24 |
| Finished | Jun 29 08:18:58 PM PDT 24 |
| Peak memory | 643316 kb |
| Host | smart-e64207f5-8b9c-4089-87e5-910a64e5419d |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 3011944364 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.chip_sw_all_escalation_resets.3011944364 |
| Directory | /workspace/57.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/58.chip_sw_alert_handler_lpg_sleep_mode_alerts.952144246 |
| Short name | T754 |
| Test name | |
| Test status | |
| Simulation time | 3637826300 ps |
| CPU time | 341.61 seconds |
| Started | Jun 29 08:11:55 PM PDT 24 |
| Finished | Jun 29 08:17:37 PM PDT 24 |
| Peak memory | 646932 kb |
| Host | smart-3a10ab16-53c7-4bcd-a1fb-dd4486c65c4d |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=952144246 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all _escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.chip_s w_alert_handler_lpg_sleep_mode_alerts.952144246 |
| Directory | /workspace/58.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/59.chip_sw_all_escalation_resets.3354470555 |
| Short name | T768 |
| Test name | |
| Test status | |
| Simulation time | 5723658630 ps |
| CPU time | 625.81 seconds |
| Started | Jun 29 08:11:05 PM PDT 24 |
| Finished | Jun 29 08:21:31 PM PDT 24 |
| Peak memory | 647872 kb |
| Host | smart-c8ce4077-e183-4439-93ee-273257c83ef7 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 3354470555 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.chip_sw_all_escalation_resets.3354470555 |
| Directory | /workspace/59.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/6.chip_sw_alert_handler_lpg_sleep_mode_alerts.3434529830 |
| Short name | T736 |
| Test name | |
| Test status | |
| Simulation time | 3667087000 ps |
| CPU time | 430.69 seconds |
| Started | Jun 29 08:05:33 PM PDT 24 |
| Finished | Jun 29 08:12:44 PM PDT 24 |
| Peak memory | 647068 kb |
| Host | smart-17ebeb4a-17e3-4adc-bae8-45d06db7dda4 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3434529830 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.chip_s w_alert_handler_lpg_sleep_mode_alerts.3434529830 |
| Directory | /workspace/6.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/6.chip_sw_all_escalation_resets.3850780885 |
| Short name | T700 |
| Test name | |
| Test status | |
| Simulation time | 4505008620 ps |
| CPU time | 797.56 seconds |
| Started | Jun 29 08:04:38 PM PDT 24 |
| Finished | Jun 29 08:17:56 PM PDT 24 |
| Peak memory | 643388 kb |
| Host | smart-91618529-bffb-4f39-b59b-ba817ca4acb8 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 3850780885 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.chip_sw_all_escalation_resets.3850780885 |
| Directory | /workspace/6.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/6.chip_sw_csrng_edn_concurrency.3032267838 |
| Short name | T417 |
| Test name | |
| Test status | |
| Simulation time | 9654246324 ps |
| CPU time | 2431.14 seconds |
| Started | Jun 29 08:05:38 PM PDT 24 |
| Finished | Jun 29 08:46:10 PM PDT 24 |
| Peak memory | 608416 kb |
| Host | smart-a283284f-ebd7-4a2b-b5de-b5e246d6fb22 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=140_000_000 +rng_srate_value_min=15 +rng_srate_value_max=20 +sw_build_device=sim_dv +sw_images=csrng_edn_c oncurrency_test:1:new_rules,test_rom:0 +accelerate_cold_power_up_time=3 +accelerate_regulators_power_up_time=2 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3032267838 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd b -cm_log /dev/null -cm_name 6.chip_sw_csrng_edn_concurrency.3032267838 |
| Directory | /workspace/6.chip_sw_csrng_edn_concurrency/latest |
| Test location | /workspace/coverage/default/6.chip_sw_lc_ctrl_transition.825633191 |
| Short name | T1251 |
| Test name | |
| Test status | |
| Simulation time | 11167947894 ps |
| CPU time | 1236.36 seconds |
| Started | Jun 29 08:05:47 PM PDT 24 |
| Finished | Jun 29 08:26:24 PM PDT 24 |
| Peak memory | 619248 kb |
| Host | smart-568044eb-2634-428b-a19c-61d43b0e1e96 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=lc_ctrl_transition_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=825633191 -assert nopostproc +UVM_TEST NAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_transition_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul t.vdb -cm_log /dev/null -cm_name 6.chip_sw_lc_ctrl_transition.825633191 |
| Directory | /workspace/6.chip_sw_lc_ctrl_transition/latest |
| Test location | /workspace/coverage/default/6.chip_sw_uart_rand_baudrate.399872963 |
| Short name | T1202 |
| Test name | |
| Test status | |
| Simulation time | 7654017760 ps |
| CPU time | 1887.05 seconds |
| Started | Jun 29 08:06:11 PM PDT 24 |
| Finished | Jun 29 08:37:39 PM PDT 24 |
| Peak memory | 618584 kb |
| Host | smart-091e8161-471d-49ea-b93c-e88b683f62f8 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=399872963 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.chip_sw_uart_rand_baudrate.399872963 |
| Directory | /workspace/6.chip_sw_uart_rand_baudrate/latest |
| Test location | /workspace/coverage/default/60.chip_sw_all_escalation_resets.2108385485 |
| Short name | T1184 |
| Test name | |
| Test status | |
| Simulation time | 5761208882 ps |
| CPU time | 609.18 seconds |
| Started | Jun 29 08:11:31 PM PDT 24 |
| Finished | Jun 29 08:21:41 PM PDT 24 |
| Peak memory | 643448 kb |
| Host | smart-a07b1cff-d0ea-48b1-8167-9b971b9ccd28 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 2108385485 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.chip_sw_all_escalation_resets.2108385485 |
| Directory | /workspace/60.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/61.chip_sw_alert_handler_lpg_sleep_mode_alerts.2215164005 |
| Short name | T745 |
| Test name | |
| Test status | |
| Simulation time | 3813613274 ps |
| CPU time | 353.45 seconds |
| Started | Jun 29 08:12:25 PM PDT 24 |
| Finished | Jun 29 08:18:19 PM PDT 24 |
| Peak memory | 647036 kb |
| Host | smart-0b6b4c20-79bc-403c-b9f0-515f04989f5a |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2215164005 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.chip_ sw_alert_handler_lpg_sleep_mode_alerts.2215164005 |
| Directory | /workspace/61.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/61.chip_sw_all_escalation_resets.1491773679 |
| Short name | T723 |
| Test name | |
| Test status | |
| Simulation time | 5704800958 ps |
| CPU time | 810.21 seconds |
| Started | Jun 29 08:10:46 PM PDT 24 |
| Finished | Jun 29 08:24:17 PM PDT 24 |
| Peak memory | 643504 kb |
| Host | smart-ed9758e4-2ba0-437a-8199-5f962946f752 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 1491773679 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.chip_sw_all_escalation_resets.1491773679 |
| Directory | /workspace/61.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/62.chip_sw_alert_handler_lpg_sleep_mode_alerts.1586122244 |
| Short name | T255 |
| Test name | |
| Test status | |
| Simulation time | 3362628796 ps |
| CPU time | 381.61 seconds |
| Started | Jun 29 08:11:13 PM PDT 24 |
| Finished | Jun 29 08:17:35 PM PDT 24 |
| Peak memory | 616900 kb |
| Host | smart-9ae1b821-e89a-409a-9064-8ecd672bd53c |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1586122244 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.chip_ sw_alert_handler_lpg_sleep_mode_alerts.1586122244 |
| Directory | /workspace/62.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/62.chip_sw_all_escalation_resets.2494027445 |
| Short name | T703 |
| Test name | |
| Test status | |
| Simulation time | 6311787672 ps |
| CPU time | 758.65 seconds |
| Started | Jun 29 08:11:26 PM PDT 24 |
| Finished | Jun 29 08:24:05 PM PDT 24 |
| Peak memory | 643296 kb |
| Host | smart-0a899c01-b671-4751-bfbc-3d593a8b429c |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 2494027445 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.chip_sw_all_escalation_resets.2494027445 |
| Directory | /workspace/62.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/63.chip_sw_alert_handler_lpg_sleep_mode_alerts.4207739401 |
| Short name | T727 |
| Test name | |
| Test status | |
| Simulation time | 3261078344 ps |
| CPU time | 455.22 seconds |
| Started | Jun 29 08:13:42 PM PDT 24 |
| Finished | Jun 29 08:21:18 PM PDT 24 |
| Peak memory | 647028 kb |
| Host | smart-09b4a993-3ae4-43c1-940e-189d9bd03de5 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4207739401 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.chip_ sw_alert_handler_lpg_sleep_mode_alerts.4207739401 |
| Directory | /workspace/63.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/63.chip_sw_all_escalation_resets.3525892219 |
| Short name | T221 |
| Test name | |
| Test status | |
| Simulation time | 5611040452 ps |
| CPU time | 614.92 seconds |
| Started | Jun 29 08:12:01 PM PDT 24 |
| Finished | Jun 29 08:22:17 PM PDT 24 |
| Peak memory | 643704 kb |
| Host | smart-c8ca4120-d3e5-4086-8aa4-15f541adee54 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 3525892219 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.chip_sw_all_escalation_resets.3525892219 |
| Directory | /workspace/63.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/65.chip_sw_alert_handler_lpg_sleep_mode_alerts.558802760 |
| Short name | T1179 |
| Test name | |
| Test status | |
| Simulation time | 3180995570 ps |
| CPU time | 424.95 seconds |
| Started | Jun 29 08:11:32 PM PDT 24 |
| Finished | Jun 29 08:18:37 PM PDT 24 |
| Peak memory | 615176 kb |
| Host | smart-d9a01200-c8dd-42a9-b5ed-900b361a0bfc |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=558802760 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all _escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.chip_s w_alert_handler_lpg_sleep_mode_alerts.558802760 |
| Directory | /workspace/65.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/66.chip_sw_alert_handler_lpg_sleep_mode_alerts.1523123970 |
| Short name | T349 |
| Test name | |
| Test status | |
| Simulation time | 3714980660 ps |
| CPU time | 480.34 seconds |
| Started | Jun 29 08:13:44 PM PDT 24 |
| Finished | Jun 29 08:21:45 PM PDT 24 |
| Peak memory | 646948 kb |
| Host | smart-dd812237-6be5-4661-9fbd-acff1b1bb344 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1523123970 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.chip_ sw_alert_handler_lpg_sleep_mode_alerts.1523123970 |
| Directory | /workspace/66.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/66.chip_sw_all_escalation_resets.3175484047 |
| Short name | T88 |
| Test name | |
| Test status | |
| Simulation time | 5555147030 ps |
| CPU time | 569.42 seconds |
| Started | Jun 29 08:12:39 PM PDT 24 |
| Finished | Jun 29 08:22:09 PM PDT 24 |
| Peak memory | 643736 kb |
| Host | smart-807ccf2d-5ca1-4402-9e3f-f6ff25fa2d42 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 3175484047 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.chip_sw_all_escalation_resets.3175484047 |
| Directory | /workspace/66.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/67.chip_sw_alert_handler_lpg_sleep_mode_alerts.537454390 |
| Short name | T1144 |
| Test name | |
| Test status | |
| Simulation time | 3903481136 ps |
| CPU time | 409 seconds |
| Started | Jun 29 08:11:55 PM PDT 24 |
| Finished | Jun 29 08:18:44 PM PDT 24 |
| Peak memory | 642220 kb |
| Host | smart-bd168714-3206-4497-bf32-2d4374df1aa6 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=537454390 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all _escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.chip_s w_alert_handler_lpg_sleep_mode_alerts.537454390 |
| Directory | /workspace/67.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/67.chip_sw_all_escalation_resets.1352598519 |
| Short name | T685 |
| Test name | |
| Test status | |
| Simulation time | 6112445318 ps |
| CPU time | 724.16 seconds |
| Started | Jun 29 08:12:18 PM PDT 24 |
| Finished | Jun 29 08:24:23 PM PDT 24 |
| Peak memory | 643776 kb |
| Host | smart-6898eacc-bdcd-4ae2-9a9f-9576299448a2 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 1352598519 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.chip_sw_all_escalation_resets.1352598519 |
| Directory | /workspace/67.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/68.chip_sw_alert_handler_lpg_sleep_mode_alerts.2042925568 |
| Short name | T725 |
| Test name | |
| Test status | |
| Simulation time | 3364930324 ps |
| CPU time | 470.34 seconds |
| Started | Jun 29 08:12:44 PM PDT 24 |
| Finished | Jun 29 08:20:35 PM PDT 24 |
| Peak memory | 646992 kb |
| Host | smart-316c9f94-7754-4c4b-974e-a5f2b9450c85 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2042925568 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.chip_ sw_alert_handler_lpg_sleep_mode_alerts.2042925568 |
| Directory | /workspace/68.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/68.chip_sw_all_escalation_resets.2240826439 |
| Short name | T765 |
| Test name | |
| Test status | |
| Simulation time | 5027432152 ps |
| CPU time | 760.82 seconds |
| Started | Jun 29 08:11:59 PM PDT 24 |
| Finished | Jun 29 08:24:40 PM PDT 24 |
| Peak memory | 647808 kb |
| Host | smart-e8b0f87e-feec-4614-8888-4f990b671973 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 2240826439 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.chip_sw_all_escalation_resets.2240826439 |
| Directory | /workspace/68.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/69.chip_sw_alert_handler_lpg_sleep_mode_alerts.655169314 |
| Short name | T1131 |
| Test name | |
| Test status | |
| Simulation time | 4392411920 ps |
| CPU time | 488.29 seconds |
| Started | Jun 29 08:14:20 PM PDT 24 |
| Finished | Jun 29 08:22:29 PM PDT 24 |
| Peak memory | 647400 kb |
| Host | smart-8e9a0966-8c4b-4b36-a36f-f12efc530cf6 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=655169314 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all _escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.chip_s w_alert_handler_lpg_sleep_mode_alerts.655169314 |
| Directory | /workspace/69.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/7.chip_sw_alert_handler_lpg_sleep_mode_alerts.2356043233 |
| Short name | T353 |
| Test name | |
| Test status | |
| Simulation time | 3450125470 ps |
| CPU time | 328.72 seconds |
| Started | Jun 29 08:05:23 PM PDT 24 |
| Finished | Jun 29 08:10:52 PM PDT 24 |
| Peak memory | 642164 kb |
| Host | smart-a19e722c-65e3-4795-a3ab-0d53f1612dc3 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2356043233 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.chip_s w_alert_handler_lpg_sleep_mode_alerts.2356043233 |
| Directory | /workspace/7.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/7.chip_sw_all_escalation_resets.1674798326 |
| Short name | T709 |
| Test name | |
| Test status | |
| Simulation time | 4879747976 ps |
| CPU time | 628.58 seconds |
| Started | Jun 29 08:05:04 PM PDT 24 |
| Finished | Jun 29 08:15:33 PM PDT 24 |
| Peak memory | 643596 kb |
| Host | smart-120c309a-e9e8-41fe-90ae-64e5553c96a8 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 1674798326 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.chip_sw_all_escalation_resets.1674798326 |
| Directory | /workspace/7.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/7.chip_sw_csrng_edn_concurrency.3486454078 |
| Short name | T890 |
| Test name | |
| Test status | |
| Simulation time | 35185982708 ps |
| CPU time | 7460.07 seconds |
| Started | Jun 29 08:06:05 PM PDT 24 |
| Finished | Jun 29 10:10:26 PM PDT 24 |
| Peak memory | 608396 kb |
| Host | smart-8d29a024-7fc1-47cc-835e-6317ead69803 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=140_000_000 +rng_srate_value_min=15 +rng_srate_value_max=20 +sw_build_device=sim_dv +sw_images=csrng_edn_c oncurrency_test:1:new_rules,test_rom:0 +accelerate_cold_power_up_time=3 +accelerate_regulators_power_up_time=2 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3486454078 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd b -cm_log /dev/null -cm_name 7.chip_sw_csrng_edn_concurrency.3486454078 |
| Directory | /workspace/7.chip_sw_csrng_edn_concurrency/latest |
| Test location | /workspace/coverage/default/7.chip_sw_lc_ctrl_transition.88602595 |
| Short name | T1012 |
| Test name | |
| Test status | |
| Simulation time | 7075769095 ps |
| CPU time | 756.53 seconds |
| Started | Jun 29 08:06:32 PM PDT 24 |
| Finished | Jun 29 08:19:09 PM PDT 24 |
| Peak memory | 621192 kb |
| Host | smart-06a76b0b-9f7c-4d30-ae82-16caaee74b92 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=lc_ctrl_transition_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=88602595 -assert nopostproc +UVM_TESTN AME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_transition_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default .vdb -cm_log /dev/null -cm_name 7.chip_sw_lc_ctrl_transition.88602595 |
| Directory | /workspace/7.chip_sw_lc_ctrl_transition/latest |
| Test location | /workspace/coverage/default/7.chip_sw_uart_rand_baudrate.929173458 |
| Short name | T922 |
| Test name | |
| Test status | |
| Simulation time | 4028915342 ps |
| CPU time | 648.58 seconds |
| Started | Jun 29 08:05:40 PM PDT 24 |
| Finished | Jun 29 08:16:29 PM PDT 24 |
| Peak memory | 618880 kb |
| Host | smart-d8f3665d-4cb9-4808-bccf-e6b55bebc9af |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=929173458 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.chip_sw_uart_rand_baudrate.929173458 |
| Directory | /workspace/7.chip_sw_uart_rand_baudrate/latest |
| Test location | /workspace/coverage/default/70.chip_sw_all_escalation_resets.4213324127 |
| Short name | T1019 |
| Test name | |
| Test status | |
| Simulation time | 4609553572 ps |
| CPU time | 609.04 seconds |
| Started | Jun 29 08:11:57 PM PDT 24 |
| Finished | Jun 29 08:22:06 PM PDT 24 |
| Peak memory | 615108 kb |
| Host | smart-b0f4702e-79ae-47ac-9336-111583b6b840 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 4213324127 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.chip_sw_all_escalation_resets.4213324127 |
| Directory | /workspace/70.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/71.chip_sw_alert_handler_lpg_sleep_mode_alerts.1964912858 |
| Short name | T347 |
| Test name | |
| Test status | |
| Simulation time | 3520820144 ps |
| CPU time | 453.39 seconds |
| Started | Jun 29 08:13:09 PM PDT 24 |
| Finished | Jun 29 08:20:42 PM PDT 24 |
| Peak memory | 646964 kb |
| Host | smart-b1b66c61-e92f-461c-879d-4b728eabd2f8 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1964912858 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.chip_ sw_alert_handler_lpg_sleep_mode_alerts.1964912858 |
| Directory | /workspace/71.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/71.chip_sw_all_escalation_resets.2833914499 |
| Short name | T333 |
| Test name | |
| Test status | |
| Simulation time | 5319810280 ps |
| CPU time | 571.99 seconds |
| Started | Jun 29 08:12:14 PM PDT 24 |
| Finished | Jun 29 08:21:47 PM PDT 24 |
| Peak memory | 648320 kb |
| Host | smart-c18605d2-a18d-4c58-a30c-97d0d2ff7561 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 2833914499 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.chip_sw_all_escalation_resets.2833914499 |
| Directory | /workspace/71.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/73.chip_sw_alert_handler_lpg_sleep_mode_alerts.2439687291 |
| Short name | T516 |
| Test name | |
| Test status | |
| Simulation time | 3131693736 ps |
| CPU time | 398.16 seconds |
| Started | Jun 29 08:12:51 PM PDT 24 |
| Finished | Jun 29 08:19:29 PM PDT 24 |
| Peak memory | 646976 kb |
| Host | smart-ea288c35-5eb4-44a0-96c0-b542228d7099 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2439687291 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.chip_ sw_alert_handler_lpg_sleep_mode_alerts.2439687291 |
| Directory | /workspace/73.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/73.chip_sw_all_escalation_resets.835682341 |
| Short name | T980 |
| Test name | |
| Test status | |
| Simulation time | 5584253424 ps |
| CPU time | 646.12 seconds |
| Started | Jun 29 08:12:32 PM PDT 24 |
| Finished | Jun 29 08:23:18 PM PDT 24 |
| Peak memory | 615144 kb |
| Host | smart-c5dbaab4-6c42-488e-90c2-87d0fda72375 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 835682341 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.chip_sw_all_escalation_resets.835682341 |
| Directory | /workspace/73.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/74.chip_sw_alert_handler_lpg_sleep_mode_alerts.4068172409 |
| Short name | T750 |
| Test name | |
| Test status | |
| Simulation time | 4037658472 ps |
| CPU time | 444.77 seconds |
| Started | Jun 29 08:12:33 PM PDT 24 |
| Finished | Jun 29 08:19:58 PM PDT 24 |
| Peak memory | 646972 kb |
| Host | smart-861f2f1b-6b26-47f7-a3b9-0ddad30b5c09 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4068172409 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.chip_ sw_alert_handler_lpg_sleep_mode_alerts.4068172409 |
| Directory | /workspace/74.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/74.chip_sw_all_escalation_resets.1729267347 |
| Short name | T981 |
| Test name | |
| Test status | |
| Simulation time | 4365973400 ps |
| CPU time | 747.31 seconds |
| Started | Jun 29 08:12:00 PM PDT 24 |
| Finished | Jun 29 08:24:27 PM PDT 24 |
| Peak memory | 643408 kb |
| Host | smart-ac5523c1-1bb3-4553-9839-c4206b4d4596 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 1729267347 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.chip_sw_all_escalation_resets.1729267347 |
| Directory | /workspace/74.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/75.chip_sw_alert_handler_lpg_sleep_mode_alerts.4223901974 |
| Short name | T1173 |
| Test name | |
| Test status | |
| Simulation time | 3578223990 ps |
| CPU time | 386.25 seconds |
| Started | Jun 29 08:12:27 PM PDT 24 |
| Finished | Jun 29 08:18:53 PM PDT 24 |
| Peak memory | 647028 kb |
| Host | smart-27df493e-c376-4d8d-9d0e-f91699848345 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4223901974 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.chip_ sw_alert_handler_lpg_sleep_mode_alerts.4223901974 |
| Directory | /workspace/75.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/75.chip_sw_all_escalation_resets.95217253 |
| Short name | T1151 |
| Test name | |
| Test status | |
| Simulation time | 5360944184 ps |
| CPU time | 763.81 seconds |
| Started | Jun 29 08:21:16 PM PDT 24 |
| Finished | Jun 29 08:34:01 PM PDT 24 |
| Peak memory | 643476 kb |
| Host | smart-161e6b90-e95d-4371-9714-ddc814929600 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 95217253 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.chip_sw_all_escalation_resets.95217253 |
| Directory | /workspace/75.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/76.chip_sw_alert_handler_lpg_sleep_mode_alerts.4106417312 |
| Short name | T260 |
| Test name | |
| Test status | |
| Simulation time | 4461608546 ps |
| CPU time | 430.18 seconds |
| Started | Jun 29 08:21:28 PM PDT 24 |
| Finished | Jun 29 08:28:39 PM PDT 24 |
| Peak memory | 647216 kb |
| Host | smart-cf453500-a548-436e-9cfa-b439be94b19a |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4106417312 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.chip_ sw_alert_handler_lpg_sleep_mode_alerts.4106417312 |
| Directory | /workspace/76.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/76.chip_sw_all_escalation_resets.106499022 |
| Short name | T733 |
| Test name | |
| Test status | |
| Simulation time | 4823143728 ps |
| CPU time | 617.52 seconds |
| Started | Jun 29 08:12:41 PM PDT 24 |
| Finished | Jun 29 08:22:59 PM PDT 24 |
| Peak memory | 648252 kb |
| Host | smart-1537ef5e-5be8-4301-bb07-f11111751622 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 106499022 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.chip_sw_all_escalation_resets.106499022 |
| Directory | /workspace/76.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/77.chip_sw_alert_handler_lpg_sleep_mode_alerts.2954911249 |
| Short name | T706 |
| Test name | |
| Test status | |
| Simulation time | 3907235912 ps |
| CPU time | 390.89 seconds |
| Started | Jun 29 08:22:25 PM PDT 24 |
| Finished | Jun 29 08:28:57 PM PDT 24 |
| Peak memory | 642320 kb |
| Host | smart-d1ddf82a-f25a-4247-a013-24d354ffbe5d |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2954911249 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.chip_ sw_alert_handler_lpg_sleep_mode_alerts.2954911249 |
| Directory | /workspace/77.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/77.chip_sw_all_escalation_resets.2571290571 |
| Short name | T407 |
| Test name | |
| Test status | |
| Simulation time | 5763073630 ps |
| CPU time | 640.07 seconds |
| Started | Jun 29 08:12:47 PM PDT 24 |
| Finished | Jun 29 08:23:28 PM PDT 24 |
| Peak memory | 643388 kb |
| Host | smart-59f28cc5-52fd-4709-9dad-491afa1d4103 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 2571290571 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.chip_sw_all_escalation_resets.2571290571 |
| Directory | /workspace/77.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/78.chip_sw_alert_handler_lpg_sleep_mode_alerts.930295791 |
| Short name | T692 |
| Test name | |
| Test status | |
| Simulation time | 3394548140 ps |
| CPU time | 436.55 seconds |
| Started | Jun 29 08:23:27 PM PDT 24 |
| Finished | Jun 29 08:30:44 PM PDT 24 |
| Peak memory | 642092 kb |
| Host | smart-4fa4ab6b-6b14-4d4e-af2d-2431bc903561 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=930295791 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all _escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.chip_s w_alert_handler_lpg_sleep_mode_alerts.930295791 |
| Directory | /workspace/78.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/78.chip_sw_all_escalation_resets.309479367 |
| Short name | T755 |
| Test name | |
| Test status | |
| Simulation time | 5031454148 ps |
| CPU time | 588.22 seconds |
| Started | Jun 29 08:12:38 PM PDT 24 |
| Finished | Jun 29 08:22:27 PM PDT 24 |
| Peak memory | 643508 kb |
| Host | smart-78d6e84f-7426-478f-8888-8e4d558c8eba |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 309479367 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.chip_sw_all_escalation_resets.309479367 |
| Directory | /workspace/78.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/79.chip_sw_alert_handler_lpg_sleep_mode_alerts.3171717442 |
| Short name | T1132 |
| Test name | |
| Test status | |
| Simulation time | 4112128500 ps |
| CPU time | 330.52 seconds |
| Started | Jun 29 08:13:46 PM PDT 24 |
| Finished | Jun 29 08:19:17 PM PDT 24 |
| Peak memory | 647024 kb |
| Host | smart-9d2b9d72-de1c-4ed7-9b14-40537fc0f34f |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3171717442 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.chip_ sw_alert_handler_lpg_sleep_mode_alerts.3171717442 |
| Directory | /workspace/79.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/79.chip_sw_all_escalation_resets.1468599899 |
| Short name | T244 |
| Test name | |
| Test status | |
| Simulation time | 5867447864 ps |
| CPU time | 511.46 seconds |
| Started | Jun 29 08:22:54 PM PDT 24 |
| Finished | Jun 29 08:31:26 PM PDT 24 |
| Peak memory | 647976 kb |
| Host | smart-644ebc14-4fa5-469d-bcba-7023785fffc2 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 1468599899 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.chip_sw_all_escalation_resets.1468599899 |
| Directory | /workspace/79.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/8.chip_sw_all_escalation_resets.2223347709 |
| Short name | T1212 |
| Test name | |
| Test status | |
| Simulation time | 4111504112 ps |
| CPU time | 492.7 seconds |
| Started | Jun 29 08:05:41 PM PDT 24 |
| Finished | Jun 29 08:13:54 PM PDT 24 |
| Peak memory | 643312 kb |
| Host | smart-3ae47471-b400-4f2e-9e32-3258e8f09a4e |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 2223347709 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.chip_sw_all_escalation_resets.2223347709 |
| Directory | /workspace/8.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/8.chip_sw_csrng_edn_concurrency.4143343515 |
| Short name | T1021 |
| Test name | |
| Test status | |
| Simulation time | 11784866880 ps |
| CPU time | 2604.73 seconds |
| Started | Jun 29 08:06:02 PM PDT 24 |
| Finished | Jun 29 08:49:28 PM PDT 24 |
| Peak memory | 608416 kb |
| Host | smart-cc7e4769-5451-4abb-a1d9-014188a2e0df |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=140_000_000 +rng_srate_value_min=15 +rng_srate_value_max=20 +sw_build_device=sim_dv +sw_images=csrng_edn_c oncurrency_test:1:new_rules,test_rom:0 +accelerate_cold_power_up_time=3 +accelerate_regulators_power_up_time=2 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4143343515 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd b -cm_log /dev/null -cm_name 8.chip_sw_csrng_edn_concurrency.4143343515 |
| Directory | /workspace/8.chip_sw_csrng_edn_concurrency/latest |
| Test location | /workspace/coverage/default/8.chip_sw_lc_ctrl_transition.3255201508 |
| Short name | T894 |
| Test name | |
| Test status | |
| Simulation time | 9973936889 ps |
| CPU time | 1071.77 seconds |
| Started | Jun 29 08:06:48 PM PDT 24 |
| Finished | Jun 29 08:24:41 PM PDT 24 |
| Peak memory | 621040 kb |
| Host | smart-ee74f7c3-4dc8-40e6-b02d-d41a34be318d |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=lc_ctrl_transition_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3255201508 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_transition_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau lt.vdb -cm_log /dev/null -cm_name 8.chip_sw_lc_ctrl_transition.3255201508 |
| Directory | /workspace/8.chip_sw_lc_ctrl_transition/latest |
| Test location | /workspace/coverage/default/8.chip_sw_uart_rand_baudrate.2996534550 |
| Short name | T1194 |
| Test name | |
| Test status | |
| Simulation time | 4335927200 ps |
| CPU time | 596.74 seconds |
| Started | Jun 29 08:05:02 PM PDT 24 |
| Finished | Jun 29 08:15:00 PM PDT 24 |
| Peak memory | 618856 kb |
| Host | smart-f0d67dfa-d4b4-433c-8b20-9c291dc08263 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=2996534550 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.chip_sw_uart_rand_baudrate.2996534550 |
| Directory | /workspace/8.chip_sw_uart_rand_baudrate/latest |
| Test location | /workspace/coverage/default/80.chip_sw_alert_handler_lpg_sleep_mode_alerts.3081919776 |
| Short name | T1204 |
| Test name | |
| Test status | |
| Simulation time | 4145591044 ps |
| CPU time | 480.74 seconds |
| Started | Jun 29 08:12:47 PM PDT 24 |
| Finished | Jun 29 08:20:48 PM PDT 24 |
| Peak memory | 647012 kb |
| Host | smart-aa73b0c4-f942-427c-a300-c89db5a0895f |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3081919776 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 80.chip_ sw_alert_handler_lpg_sleep_mode_alerts.3081919776 |
| Directory | /workspace/80.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/80.chip_sw_all_escalation_resets.2069308803 |
| Short name | T759 |
| Test name | |
| Test status | |
| Simulation time | 4580500352 ps |
| CPU time | 602.69 seconds |
| Started | Jun 29 08:13:33 PM PDT 24 |
| Finished | Jun 29 08:23:36 PM PDT 24 |
| Peak memory | 643476 kb |
| Host | smart-c5ead7c1-9c41-45a2-8d77-f0e7cda4ed7c |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 2069308803 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 80.chip_sw_all_escalation_resets.2069308803 |
| Directory | /workspace/80.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/81.chip_sw_alert_handler_lpg_sleep_mode_alerts.1292668706 |
| Short name | T248 |
| Test name | |
| Test status | |
| Simulation time | 4464229904 ps |
| CPU time | 488.76 seconds |
| Started | Jun 29 08:13:17 PM PDT 24 |
| Finished | Jun 29 08:21:26 PM PDT 24 |
| Peak memory | 647356 kb |
| Host | smart-fe1829f9-692b-4b88-9c3e-6913d2d4e631 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1292668706 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 81.chip_ sw_alert_handler_lpg_sleep_mode_alerts.1292668706 |
| Directory | /workspace/81.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/82.chip_sw_alert_handler_lpg_sleep_mode_alerts.2583003899 |
| Short name | T705 |
| Test name | |
| Test status | |
| Simulation time | 4031517120 ps |
| CPU time | 468.64 seconds |
| Started | Jun 29 08:13:47 PM PDT 24 |
| Finished | Jun 29 08:21:36 PM PDT 24 |
| Peak memory | 642244 kb |
| Host | smart-ca3895c3-98e7-4522-9c95-2625d8fb4236 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2583003899 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 82.chip_ sw_alert_handler_lpg_sleep_mode_alerts.2583003899 |
| Directory | /workspace/82.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/82.chip_sw_all_escalation_resets.2215835407 |
| Short name | T731 |
| Test name | |
| Test status | |
| Simulation time | 3936154040 ps |
| CPU time | 564.45 seconds |
| Started | Jun 29 08:12:52 PM PDT 24 |
| Finished | Jun 29 08:22:17 PM PDT 24 |
| Peak memory | 643468 kb |
| Host | smart-fc6ee203-32d6-4b17-a4dc-e1ba201ee97f |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 2215835407 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 82.chip_sw_all_escalation_resets.2215835407 |
| Directory | /workspace/82.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/83.chip_sw_alert_handler_lpg_sleep_mode_alerts.3974385600 |
| Short name | T351 |
| Test name | |
| Test status | |
| Simulation time | 3892470288 ps |
| CPU time | 451.49 seconds |
| Started | Jun 29 08:14:30 PM PDT 24 |
| Finished | Jun 29 08:22:02 PM PDT 24 |
| Peak memory | 646964 kb |
| Host | smart-629d0200-66e8-44a8-9123-064ed0d446de |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3974385600 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 83.chip_ sw_alert_handler_lpg_sleep_mode_alerts.3974385600 |
| Directory | /workspace/83.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/83.chip_sw_all_escalation_resets.2389955944 |
| Short name | T691 |
| Test name | |
| Test status | |
| Simulation time | 5749535264 ps |
| CPU time | 695.72 seconds |
| Started | Jun 29 08:13:37 PM PDT 24 |
| Finished | Jun 29 08:25:13 PM PDT 24 |
| Peak memory | 647780 kb |
| Host | smart-efe71628-e28b-426d-b85b-e8b1dce081b5 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 2389955944 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 83.chip_sw_all_escalation_resets.2389955944 |
| Directory | /workspace/83.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/84.chip_sw_alert_handler_lpg_sleep_mode_alerts.956109430 |
| Short name | T282 |
| Test name | |
| Test status | |
| Simulation time | 3944240348 ps |
| CPU time | 537.92 seconds |
| Started | Jun 29 08:14:46 PM PDT 24 |
| Finished | Jun 29 08:23:44 PM PDT 24 |
| Peak memory | 642568 kb |
| Host | smart-972b685b-06e9-4f76-b996-fa1956f9592a |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=956109430 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all _escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 84.chip_s w_alert_handler_lpg_sleep_mode_alerts.956109430 |
| Directory | /workspace/84.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/85.chip_sw_alert_handler_lpg_sleep_mode_alerts.780710888 |
| Short name | T688 |
| Test name | |
| Test status | |
| Simulation time | 3734591610 ps |
| CPU time | 385.69 seconds |
| Started | Jun 29 08:13:43 PM PDT 24 |
| Finished | Jun 29 08:20:09 PM PDT 24 |
| Peak memory | 642312 kb |
| Host | smart-f84adeac-85b0-4d63-9103-6b6279d83f2a |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=780710888 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all _escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 85.chip_s w_alert_handler_lpg_sleep_mode_alerts.780710888 |
| Directory | /workspace/85.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/85.chip_sw_all_escalation_resets.563177420 |
| Short name | T687 |
| Test name | |
| Test status | |
| Simulation time | 4651556542 ps |
| CPU time | 616.89 seconds |
| Started | Jun 29 08:14:21 PM PDT 24 |
| Finished | Jun 29 08:24:38 PM PDT 24 |
| Peak memory | 643384 kb |
| Host | smart-cb30efca-ec58-484e-9b73-3b687d2bf2e2 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 563177420 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 85.chip_sw_all_escalation_resets.563177420 |
| Directory | /workspace/85.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/86.chip_sw_alert_handler_lpg_sleep_mode_alerts.3270659567 |
| Short name | T722 |
| Test name | |
| Test status | |
| Simulation time | 3403036976 ps |
| CPU time | 466.39 seconds |
| Started | Jun 29 08:13:27 PM PDT 24 |
| Finished | Jun 29 08:21:14 PM PDT 24 |
| Peak memory | 647100 kb |
| Host | smart-54eb9421-766f-484f-952a-95351946a20a |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3270659567 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 86.chip_ sw_alert_handler_lpg_sleep_mode_alerts.3270659567 |
| Directory | /workspace/86.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/86.chip_sw_all_escalation_resets.872563925 |
| Short name | T239 |
| Test name | |
| Test status | |
| Simulation time | 5538164928 ps |
| CPU time | 642.67 seconds |
| Started | Jun 29 08:23:49 PM PDT 24 |
| Finished | Jun 29 08:34:32 PM PDT 24 |
| Peak memory | 643672 kb |
| Host | smart-3f410cfa-e981-4ffe-afdb-0a31e506ce87 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 872563925 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 86.chip_sw_all_escalation_resets.872563925 |
| Directory | /workspace/86.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/87.chip_sw_all_escalation_resets.4252985822 |
| Short name | T757 |
| Test name | |
| Test status | |
| Simulation time | 4436042996 ps |
| CPU time | 631.25 seconds |
| Started | Jun 29 08:23:17 PM PDT 24 |
| Finished | Jun 29 08:33:48 PM PDT 24 |
| Peak memory | 643416 kb |
| Host | smart-a821d380-e10f-4c72-885a-a6faf0314093 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 4252985822 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 87.chip_sw_all_escalation_resets.4252985822 |
| Directory | /workspace/87.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/88.chip_sw_alert_handler_lpg_sleep_mode_alerts.895600004 |
| Short name | T1242 |
| Test name | |
| Test status | |
| Simulation time | 4109858668 ps |
| CPU time | 405.54 seconds |
| Started | Jun 29 08:13:59 PM PDT 24 |
| Finished | Jun 29 08:20:44 PM PDT 24 |
| Peak memory | 647012 kb |
| Host | smart-cd66bf7e-4bf3-4bbf-b4da-d9ed13184273 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=895600004 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all _escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 88.chip_s w_alert_handler_lpg_sleep_mode_alerts.895600004 |
| Directory | /workspace/88.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/88.chip_sw_all_escalation_resets.2405986416 |
| Short name | T729 |
| Test name | |
| Test status | |
| Simulation time | 5866492360 ps |
| CPU time | 747.69 seconds |
| Started | Jun 29 08:13:56 PM PDT 24 |
| Finished | Jun 29 08:26:24 PM PDT 24 |
| Peak memory | 647976 kb |
| Host | smart-5aaa5bb2-46fe-4400-835e-23f08a28d40c |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 2405986416 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 88.chip_sw_all_escalation_resets.2405986416 |
| Directory | /workspace/88.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/89.chip_sw_alert_handler_lpg_sleep_mode_alerts.2567068275 |
| Short name | T716 |
| Test name | |
| Test status | |
| Simulation time | 4507429200 ps |
| CPU time | 478.34 seconds |
| Started | Jun 29 08:13:54 PM PDT 24 |
| Finished | Jun 29 08:21:53 PM PDT 24 |
| Peak memory | 647724 kb |
| Host | smart-e49d54f0-c791-4685-96f5-a14c7392ce24 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2567068275 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 89.chip_ sw_alert_handler_lpg_sleep_mode_alerts.2567068275 |
| Directory | /workspace/89.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/89.chip_sw_all_escalation_resets.2120256244 |
| Short name | T354 |
| Test name | |
| Test status | |
| Simulation time | 4725558040 ps |
| CPU time | 662.72 seconds |
| Started | Jun 29 08:13:59 PM PDT 24 |
| Finished | Jun 29 08:25:02 PM PDT 24 |
| Peak memory | 643368 kb |
| Host | smart-505ebfe4-56dd-4f3a-8efd-28ce0f25f60b |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 2120256244 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 89.chip_sw_all_escalation_resets.2120256244 |
| Directory | /workspace/89.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/9.chip_sw_all_escalation_resets.1013714711 |
| Short name | T742 |
| Test name | |
| Test status | |
| Simulation time | 5998425306 ps |
| CPU time | 661.22 seconds |
| Started | Jun 29 08:06:23 PM PDT 24 |
| Finished | Jun 29 08:17:25 PM PDT 24 |
| Peak memory | 643524 kb |
| Host | smart-12258928-32ad-4b66-b257-ced4fa45d353 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 1013714711 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.chip_sw_all_escalation_resets.1013714711 |
| Directory | /workspace/9.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/9.chip_sw_csrng_edn_concurrency.3658983633 |
| Short name | T920 |
| Test name | |
| Test status | |
| Simulation time | 20413842638 ps |
| CPU time | 4752.42 seconds |
| Started | Jun 29 08:06:50 PM PDT 24 |
| Finished | Jun 29 09:26:03 PM PDT 24 |
| Peak memory | 608420 kb |
| Host | smart-64ef00bb-d0b5-4fe5-80b1-b7d18dfe26c3 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=140_000_000 +rng_srate_value_min=15 +rng_srate_value_max=20 +sw_build_device=sim_dv +sw_images=csrng_edn_c oncurrency_test:1:new_rules,test_rom:0 +accelerate_cold_power_up_time=3 +accelerate_regulators_power_up_time=2 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3658983633 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd b -cm_log /dev/null -cm_name 9.chip_sw_csrng_edn_concurrency.3658983633 |
| Directory | /workspace/9.chip_sw_csrng_edn_concurrency/latest |
| Test location | /workspace/coverage/default/9.chip_sw_lc_ctrl_transition.3467736692 |
| Short name | T1259 |
| Test name | |
| Test status | |
| Simulation time | 13477529552 ps |
| CPU time | 1282.73 seconds |
| Started | Jun 29 08:06:10 PM PDT 24 |
| Finished | Jun 29 08:27:34 PM PDT 24 |
| Peak memory | 624140 kb |
| Host | smart-d7ddc9eb-a18e-461b-a19c-6a63915c0ff7 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=lc_ctrl_transition_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3467736692 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_transition_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau lt.vdb -cm_log /dev/null -cm_name 9.chip_sw_lc_ctrl_transition.3467736692 |
| Directory | /workspace/9.chip_sw_lc_ctrl_transition/latest |
| Test location | /workspace/coverage/default/9.chip_sw_uart_rand_baudrate.2396071342 |
| Short name | T413 |
| Test name | |
| Test status | |
| Simulation time | 3989069088 ps |
| CPU time | 545.49 seconds |
| Started | Jun 29 08:06:41 PM PDT 24 |
| Finished | Jun 29 08:15:47 PM PDT 24 |
| Peak memory | 618864 kb |
| Host | smart-6e94dd29-f1f9-4ac3-8b2b-04f6a62bb16f |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=2396071342 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.chip_sw_uart_rand_baudrate.2396071342 |
| Directory | /workspace/9.chip_sw_uart_rand_baudrate/latest |
| Test location | /workspace/coverage/default/90.chip_sw_all_escalation_resets.2527755525 |
| Short name | T699 |
| Test name | |
| Test status | |
| Simulation time | 4504022432 ps |
| CPU time | 651.55 seconds |
| Started | Jun 29 08:14:31 PM PDT 24 |
| Finished | Jun 29 08:25:23 PM PDT 24 |
| Peak memory | 615096 kb |
| Host | smart-3c354d3c-3442-48df-b81e-f803adce78c8 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 2527755525 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 90.chip_sw_all_escalation_resets.2527755525 |
| Directory | /workspace/90.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/92.chip_sw_all_escalation_resets.2411754101 |
| Short name | T651 |
| Test name | |
| Test status | |
| Simulation time | 4172055684 ps |
| CPU time | 577.02 seconds |
| Started | Jun 29 08:13:59 PM PDT 24 |
| Finished | Jun 29 08:23:37 PM PDT 24 |
| Peak memory | 608380 kb |
| Host | smart-9b8ba845-2d26-40fb-a135-f8399f61c724 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 2411754101 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 92.chip_sw_all_escalation_resets.2411754101 |
| Directory | /workspace/92.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/93.chip_sw_all_escalation_resets.4080467629 |
| Short name | T425 |
| Test name | |
| Test status | |
| Simulation time | 4943445396 ps |
| CPU time | 765.89 seconds |
| Started | Jun 29 08:13:58 PM PDT 24 |
| Finished | Jun 29 08:26:44 PM PDT 24 |
| Peak memory | 648188 kb |
| Host | smart-12299c56-c716-4768-bc96-fd68fbaf18a5 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 4080467629 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 93.chip_sw_all_escalation_resets.4080467629 |
| Directory | /workspace/93.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/96.chip_sw_all_escalation_resets.2137948047 |
| Short name | T338 |
| Test name | |
| Test status | |
| Simulation time | 4313393380 ps |
| CPU time | 439.21 seconds |
| Started | Jun 29 08:13:47 PM PDT 24 |
| Finished | Jun 29 08:21:07 PM PDT 24 |
| Peak memory | 643180 kb |
| Host | smart-da0d82e1-d930-4325-afaf-2ffa15a26740 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 2137948047 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 96.chip_sw_all_escalation_resets.2137948047 |
| Directory | /workspace/96.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/97.chip_sw_all_escalation_resets.1232503551 |
| Short name | T323 |
| Test name | |
| Test status | |
| Simulation time | 5781280768 ps |
| CPU time | 559.23 seconds |
| Started | Jun 29 08:13:56 PM PDT 24 |
| Finished | Jun 29 08:23:16 PM PDT 24 |
| Peak memory | 643200 kb |
| Host | smart-c7bbc264-0f8a-4604-85cf-bab72aa7d2ed |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 1232503551 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 97.chip_sw_all_escalation_resets.1232503551 |
| Directory | /workspace/97.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/98.chip_sw_all_escalation_resets.1789691997 |
| Short name | T386 |
| Test name | |
| Test status | |
| Simulation time | 6175984660 ps |
| CPU time | 691.19 seconds |
| Started | Jun 29 08:14:39 PM PDT 24 |
| Finished | Jun 29 08:26:11 PM PDT 24 |
| Peak memory | 648212 kb |
| Host | smart-30d271d0-fb32-4541-a4cf-01ca771ce0ea |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 1789691997 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 98.chip_sw_all_escalation_resets.1789691997 |
| Directory | /workspace/98.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/99.chip_sw_all_escalation_resets.493271350 |
| Short name | T702 |
| Test name | |
| Test status | |
| Simulation time | 4336451642 ps |
| CPU time | 542.45 seconds |
| Started | Jun 29 08:14:27 PM PDT 24 |
| Finished | Jun 29 08:23:30 PM PDT 24 |
| Peak memory | 643568 kb |
| Host | smart-e468e431-e16d-41fd-af14-184c4dd8ec68 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 493271350 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 99.chip_sw_all_escalation_resets.493271350 |
| Directory | /workspace/99.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/pad_ctrl_test_mode/0.chip_padctrl_attributes.2461266009 |
| Short name | T38 |
| Test name | |
| Test status | |
| Simulation time | 3734639658 ps |
| CPU time | 202.51 seconds |
| Started | Jun 29 08:31:28 PM PDT 24 |
| Finished | Jun 29 08:34:51 PM PDT 24 |
| Peak memory | 648532 kb |
| Host | smart-e6279ba5-02ea-4579-9268-930152071084 |
| User | root |
| Command | /workspace/pad_ctrl_test_mode/simv +use_otp_image=OtpTypeLcStProd +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2461266009 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TE ST_SEQ=chip_padctrl_attributes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/pad_ctrl_test_mode.vdb -cm_log /dev/ null -cm_name 0.chip_padctrl_attributes.2461266009 |
| Directory | /workspace/0.chip_padctrl_attributes/latest |
| Test location | /workspace/coverage/pad_ctrl_test_mode/1.chip_padctrl_attributes.1366525154 |
| Short name | T141 |
| Test name | |
| Test status | |
| Simulation time | 4168220232 ps |
| CPU time | 228.35 seconds |
| Started | Jun 29 08:31:28 PM PDT 24 |
| Finished | Jun 29 08:35:17 PM PDT 24 |
| Peak memory | 640312 kb |
| Host | smart-aa2cda30-2369-4220-940c-10843fbc8e49 |
| User | root |
| Command | /workspace/pad_ctrl_test_mode/simv +use_otp_image=OtpTypeLcStProd +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1366525154 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TE ST_SEQ=chip_padctrl_attributes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/pad_ctrl_test_mode.vdb -cm_log /dev/ null -cm_name 1.chip_padctrl_attributes.1366525154 |
| Directory | /workspace/1.chip_padctrl_attributes/latest |
| Test location | /workspace/coverage/pad_ctrl_test_mode/2.chip_padctrl_attributes.140082897 |
| Short name | T142 |
| Test name | |
| Test status | |
| Simulation time | 4467828363 ps |
| CPU time | 173.42 seconds |
| Started | Jun 29 08:31:25 PM PDT 24 |
| Finished | Jun 29 08:34:19 PM PDT 24 |
| Peak memory | 640208 kb |
| Host | smart-b7c5fa62-83c2-492f-8fa5-88001b638ba0 |
| User | root |
| Command | /workspace/pad_ctrl_test_mode/simv +use_otp_image=OtpTypeLcStProd +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=140082897 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TES T_SEQ=chip_padctrl_attributes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/pad_ctrl_test_mode.vdb -cm_log /dev/n ull -cm_name 2.chip_padctrl_attributes.140082897 |
| Directory | /workspace/2.chip_padctrl_attributes/latest |
| Test location | /workspace/coverage/pad_ctrl_test_mode/4.chip_padctrl_attributes.300353921 |
| Short name | T140 |
| Test name | |
| Test status | |
| Simulation time | 5451898585 ps |
| CPU time | 251.16 seconds |
| Started | Jun 29 08:31:28 PM PDT 24 |
| Finished | Jun 29 08:35:39 PM PDT 24 |
| Peak memory | 656704 kb |
| Host | smart-df3eb443-ec54-4614-9d28-aff87fc8ad33 |
| User | root |
| Command | /workspace/pad_ctrl_test_mode/simv +use_otp_image=OtpTypeLcStProd +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=300353921 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TES T_SEQ=chip_padctrl_attributes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/pad_ctrl_test_mode.vdb -cm_log /dev/n ull -cm_name 4.chip_padctrl_attributes.300353921 |
| Directory | /workspace/4.chip_padctrl_attributes/latest |
| Test location | /workspace/coverage/pad_ctrl_test_mode/5.chip_padctrl_attributes.2180374241 |
| Short name | T139 |
| Test name | |
| Test status | |
| Simulation time | 4777138974 ps |
| CPU time | 249.53 seconds |
| Started | Jun 29 08:31:32 PM PDT 24 |
| Finished | Jun 29 08:35:41 PM PDT 24 |
| Peak memory | 640320 kb |
| Host | smart-574d23a9-0589-451f-b233-4aee9ca1c79b |
| User | root |
| Command | /workspace/pad_ctrl_test_mode/simv +use_otp_image=OtpTypeLcStProd +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2180374241 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TE ST_SEQ=chip_padctrl_attributes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/pad_ctrl_test_mode.vdb -cm_log /dev/ null -cm_name 5.chip_padctrl_attributes.2180374241 |
| Directory | /workspace/5.chip_padctrl_attributes/latest |
| Test location | /workspace/coverage/pad_ctrl_test_mode/6.chip_padctrl_attributes.1676048048 |
| Short name | T145 |
| Test name | |
| Test status | |
| Simulation time | 4280010904 ps |
| CPU time | 187.64 seconds |
| Started | Jun 29 08:31:28 PM PDT 24 |
| Finished | Jun 29 08:34:36 PM PDT 24 |
| Peak memory | 640328 kb |
| Host | smart-b5f4a751-a696-4e66-9d37-e6db3e9a1082 |
| User | root |
| Command | /workspace/pad_ctrl_test_mode/simv +use_otp_image=OtpTypeLcStProd +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1676048048 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TE ST_SEQ=chip_padctrl_attributes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/pad_ctrl_test_mode.vdb -cm_log /dev/ null -cm_name 6.chip_padctrl_attributes.1676048048 |
| Directory | /workspace/6.chip_padctrl_attributes/latest |
| Test location | /workspace/coverage/pad_ctrl_test_mode/7.chip_padctrl_attributes.917542695 |
| Short name | T143 |
| Test name | |
| Test status | |
| Simulation time | 5684389990 ps |
| CPU time | 277.05 seconds |
| Started | Jun 29 08:31:28 PM PDT 24 |
| Finished | Jun 29 08:36:05 PM PDT 24 |
| Peak memory | 649216 kb |
| Host | smart-49d59eae-ff6d-4b80-b54d-a6a4a1f1a5af |
| User | root |
| Command | /workspace/pad_ctrl_test_mode/simv +use_otp_image=OtpTypeLcStProd +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=917542695 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TES T_SEQ=chip_padctrl_attributes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/pad_ctrl_test_mode.vdb -cm_log /dev/n ull -cm_name 7.chip_padctrl_attributes.917542695 |
| Directory | /workspace/7.chip_padctrl_attributes/latest |
| Test location | /workspace/coverage/pad_ctrl_test_mode/9.chip_padctrl_attributes.2485069699 |
| Short name | T144 |
| Test name | |
| Test status | |
| Simulation time | 5340143152 ps |
| CPU time | 262.5 seconds |
| Started | Jun 29 08:31:33 PM PDT 24 |
| Finished | Jun 29 08:35:56 PM PDT 24 |
| Peak memory | 640336 kb |
| Host | smart-b42c2b9a-53a8-4fbd-b546-4e1983702232 |
| User | root |
| Command | /workspace/pad_ctrl_test_mode/simv +use_otp_image=OtpTypeLcStProd +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2485069699 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TE ST_SEQ=chip_padctrl_attributes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/pad_ctrl_test_mode.vdb -cm_log /dev/ null -cm_name 9.chip_padctrl_attributes.2485069699 |
| Directory | /workspace/9.chip_padctrl_attributes/latest |
| 0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |