| T918 |
/workspace/coverage/default/1.rom_e2e_keymgr_init_rom_ext_invalid_meas.2539826824 |
|
|
Jun 30 07:52:30 PM PDT 24 |
Jun 30 09:02:42 PM PDT 24 |
14681311880 ps |
| T919 |
/workspace/coverage/default/1.chip_sw_example_flash.313653092 |
|
|
Jun 30 07:41:31 PM PDT 24 |
Jun 30 07:45:22 PM PDT 24 |
2180626720 ps |
| T784 |
/workspace/coverage/default/69.chip_sw_alert_handler_lpg_sleep_mode_alerts.1393736048 |
|
|
Jun 30 08:08:09 PM PDT 24 |
Jun 30 08:15:15 PM PDT 24 |
3516304100 ps |
| T920 |
/workspace/coverage/default/1.chip_sw_aon_timer_sleep_wdog_sleep_pause.1157391922 |
|
|
Jun 30 07:43:57 PM PDT 24 |
Jun 30 07:53:16 PM PDT 24 |
6938714344 ps |
| T921 |
/workspace/coverage/default/1.chip_sw_alert_handler_lpg_clkoff.3672384928 |
|
|
Jun 30 07:45:21 PM PDT 24 |
Jun 30 08:24:44 PM PDT 24 |
8474942104 ps |
| T197 |
/workspace/coverage/default/2.chip_sw_sysrst_ctrl_reset.618459688 |
|
|
Jun 30 07:53:54 PM PDT 24 |
Jun 30 08:22:57 PM PDT 24 |
24264663336 ps |
| T922 |
/workspace/coverage/default/2.chip_sw_alert_handler_ping_timeout.988607250 |
|
|
Jun 30 07:54:12 PM PDT 24 |
Jun 30 08:01:04 PM PDT 24 |
3803876436 ps |
| T923 |
/workspace/coverage/default/1.chip_sw_pwrmgr_b2b_sleep_reset_req.928172849 |
|
|
Jun 30 07:46:49 PM PDT 24 |
Jun 30 08:44:14 PM PDT 24 |
29286368490 ps |
| T728 |
/workspace/coverage/default/75.chip_sw_all_escalation_resets.2042567823 |
|
|
Jun 30 08:08:53 PM PDT 24 |
Jun 30 08:21:31 PM PDT 24 |
6493877448 ps |
| T28 |
/workspace/coverage/default/0.chip_sw_spi_device_pass_through.2161702282 |
|
|
Jun 30 07:28:32 PM PDT 24 |
Jun 30 07:40:01 PM PDT 24 |
5939467097 ps |
| T924 |
/workspace/coverage/default/2.chip_sw_hmac_enc_idle.4004103662 |
|
|
Jun 30 07:54:46 PM PDT 24 |
Jun 30 08:00:12 PM PDT 24 |
2825688868 ps |
| T693 |
/workspace/coverage/default/24.chip_sw_alert_handler_lpg_sleep_mode_alerts.1478243465 |
|
|
Jun 30 08:03:50 PM PDT 24 |
Jun 30 08:09:43 PM PDT 24 |
3981495472 ps |
| T330 |
/workspace/coverage/default/1.chip_sw_pattgen_ios.221819699 |
|
|
Jun 30 07:40:18 PM PDT 24 |
Jun 30 07:44:43 PM PDT 24 |
3387669644 ps |
| T81 |
/workspace/coverage/default/0.chip_jtag_mem_access.1293008461 |
|
|
Jun 30 07:25:58 PM PDT 24 |
Jun 30 07:53:33 PM PDT 24 |
13267277504 ps |
| T265 |
/workspace/coverage/default/2.chip_sw_rom_ctrl_integrity_check.3217396099 |
|
|
Jun 30 07:56:11 PM PDT 24 |
Jun 30 08:07:48 PM PDT 24 |
9305629159 ps |
| T712 |
/workspace/coverage/default/1.chip_sw_clkmgr_reset_frequency.2634750534 |
|
|
Jun 30 07:48:46 PM PDT 24 |
Jun 30 07:57:45 PM PDT 24 |
3861084732 ps |
| T218 |
/workspace/coverage/default/1.chip_sw_lc_walkthrough_prod.299392406 |
|
|
Jun 30 07:42:30 PM PDT 24 |
Jun 30 09:13:28 PM PDT 24 |
47691029857 ps |
| T147 |
/workspace/coverage/default/1.chip_sw_exit_test_unlocked_bootstrap.1554599485 |
|
|
Jun 30 07:39:54 PM PDT 24 |
Jun 30 10:39:02 PM PDT 24 |
58698494856 ps |
| T126 |
/workspace/coverage/default/1.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup.3436214983 |
|
|
Jun 30 07:46:42 PM PDT 24 |
Jun 30 07:55:02 PM PDT 24 |
5474069644 ps |
| T925 |
/workspace/coverage/default/2.chip_sw_pwrmgr_deep_sleep_all_reset_reqs.976802058 |
|
|
Jun 30 07:53:40 PM PDT 24 |
Jun 30 08:23:45 PM PDT 24 |
18123603301 ps |
| T237 |
/workspace/coverage/default/57.chip_sw_alert_handler_lpg_sleep_mode_alerts.1268092005 |
|
|
Jun 30 08:07:18 PM PDT 24 |
Jun 30 08:13:36 PM PDT 24 |
4052224392 ps |
| T284 |
/workspace/coverage/default/1.chip_sw_flash_ctrl_idle_low_power.2328702424 |
|
|
Jun 30 07:43:32 PM PDT 24 |
Jun 30 07:49:19 PM PDT 24 |
3639971420 ps |
| T148 |
/workspace/coverage/default/2.chip_sw_exit_test_unlocked_bootstrap.3764817316 |
|
|
Jun 30 07:50:15 PM PDT 24 |
Jun 30 10:47:38 PM PDT 24 |
58242955192 ps |
| T285 |
/workspace/coverage/default/99.chip_sw_all_escalation_resets.2746117978 |
|
|
Jun 30 08:11:37 PM PDT 24 |
Jun 30 08:24:26 PM PDT 24 |
6632535324 ps |
| T215 |
/workspace/coverage/default/0.chip_sw_keymgr_sideload_aes.930534062 |
|
|
Jun 30 07:30:02 PM PDT 24 |
Jun 30 08:07:50 PM PDT 24 |
12048672512 ps |
| T286 |
/workspace/coverage/default/1.chip_sw_example_concurrency.2384649167 |
|
|
Jun 30 07:40:00 PM PDT 24 |
Jun 30 07:43:51 PM PDT 24 |
2754080620 ps |
| T82 |
/workspace/coverage/default/2.chip_jtag_mem_access.3058290425 |
|
|
Jun 30 07:50:12 PM PDT 24 |
Jun 30 08:14:49 PM PDT 24 |
13506022938 ps |
| T158 |
/workspace/coverage/default/46.chip_sw_all_escalation_resets.4041947803 |
|
|
Jun 30 08:06:12 PM PDT 24 |
Jun 30 08:14:55 PM PDT 24 |
4661345070 ps |
| T287 |
/workspace/coverage/default/2.chip_plic_all_irqs_20.2176045761 |
|
|
Jun 30 07:57:12 PM PDT 24 |
Jun 30 08:09:19 PM PDT 24 |
4964783330 ps |
| T194 |
/workspace/coverage/default/2.chip_sw_inject_scramble_seed.3896238391 |
|
|
Jun 30 07:50:58 PM PDT 24 |
Jun 30 11:03:44 PM PDT 24 |
65828919897 ps |
| T3 |
/workspace/coverage/default/1.chip_sw_sleep_pin_wake.1358396480 |
|
|
Jun 30 07:39:42 PM PDT 24 |
Jun 30 07:47:08 PM PDT 24 |
5643463596 ps |
| T403 |
/workspace/coverage/default/0.chip_sw_pwrmgr_sleep_disabled.3755617818 |
|
|
Jun 30 07:28:41 PM PDT 24 |
Jun 30 07:33:34 PM PDT 24 |
2962656536 ps |
| T14 |
/workspace/coverage/default/2.chip_sw_pwrmgr_deep_sleep_all_wake_ups.518793059 |
|
|
Jun 30 07:57:57 PM PDT 24 |
Jun 30 08:34:49 PM PDT 24 |
23782270720 ps |
| T404 |
/workspace/coverage/default/16.chip_sw_all_escalation_resets.1804093688 |
|
|
Jun 30 08:04:25 PM PDT 24 |
Jun 30 08:16:29 PM PDT 24 |
5770289164 ps |
| T405 |
/workspace/coverage/default/0.chip_sw_clkmgr_sleep_frequency.1343903779 |
|
|
Jun 30 07:32:25 PM PDT 24 |
Jun 30 07:39:56 PM PDT 24 |
4783794502 ps |
| T406 |
/workspace/coverage/default/1.chip_sw_flash_ctrl_clock_freqs.2919735580 |
|
|
Jun 30 07:40:26 PM PDT 24 |
Jun 30 07:56:43 PM PDT 24 |
5931898704 ps |
| T407 |
/workspace/coverage/default/2.chip_sw_otbn_ecdsa_op_irq.3475476276 |
|
|
Jun 30 07:57:30 PM PDT 24 |
Jun 30 08:55:43 PM PDT 24 |
17634618080 ps |
| T262 |
/workspace/coverage/default/0.chip_sw_lc_ctrl_volatile_raw_unlock.3593577413 |
|
|
Jun 30 07:28:51 PM PDT 24 |
Jun 30 07:30:31 PM PDT 24 |
2482010020 ps |
| T408 |
/workspace/coverage/default/4.chip_sw_uart_tx_rx_idx1.1211270751 |
|
|
Jun 30 08:00:09 PM PDT 24 |
Jun 30 08:10:50 PM PDT 24 |
3560897860 ps |
| T409 |
/workspace/coverage/default/14.chip_sw_all_escalation_resets.3522811118 |
|
|
Jun 30 08:01:53 PM PDT 24 |
Jun 30 08:15:28 PM PDT 24 |
5715551282 ps |
| T323 |
/workspace/coverage/default/0.chip_sw_flash_ctrl_ops_jitter_en.2425516723 |
|
|
Jun 30 07:28:28 PM PDT 24 |
Jun 30 07:39:09 PM PDT 24 |
3487641011 ps |
| T926 |
/workspace/coverage/default/0.rom_e2e_asm_init_test_unlocked0.3859307904 |
|
|
Jun 30 07:43:01 PM PDT 24 |
Jun 30 08:47:15 PM PDT 24 |
11658588296 ps |
| T682 |
/workspace/coverage/default/1.chip_sw_power_sleep_load.3793996525 |
|
|
Jun 30 07:48:20 PM PDT 24 |
Jun 30 07:56:27 PM PDT 24 |
9033740224 ps |
| T716 |
/workspace/coverage/default/2.chip_sw_alert_handler_reverse_ping_in_deep_sleep.757570221 |
|
|
Jun 30 07:55:28 PM PDT 24 |
Jun 30 11:32:08 PM PDT 24 |
255232801976 ps |
| T927 |
/workspace/coverage/default/2.chip_sw_alert_handler_entropy.2330592365 |
|
|
Jun 30 07:54:29 PM PDT 24 |
Jun 30 07:59:15 PM PDT 24 |
3021488359 ps |
| T928 |
/workspace/coverage/default/2.chip_sw_example_flash.3817883020 |
|
|
Jun 30 07:49:39 PM PDT 24 |
Jun 30 07:53:21 PM PDT 24 |
3078521320 ps |
| T929 |
/workspace/coverage/default/11.chip_sw_uart_rand_baudrate.1191413129 |
|
|
Jun 30 08:03:27 PM PDT 24 |
Jun 30 08:29:43 PM PDT 24 |
7270793404 ps |
| T266 |
/workspace/coverage/default/1.rom_e2e_shutdown_output.1207787635 |
|
|
Jun 30 07:53:45 PM PDT 24 |
Jun 30 09:10:38 PM PDT 24 |
29624084091 ps |
| T219 |
/workspace/coverage/default/2.chip_sw_lc_walkthrough_dev.1930553388 |
|
|
Jun 30 07:51:57 PM PDT 24 |
Jun 30 09:28:26 PM PDT 24 |
49847468364 ps |
| T930 |
/workspace/coverage/default/0.chip_sw_pwrmgr_b2b_sleep_reset_req.2160648374 |
|
|
Jun 30 07:31:50 PM PDT 24 |
Jun 30 08:13:25 PM PDT 24 |
23865011834 ps |
| T159 |
/workspace/coverage/default/0.chip_sw_otp_ctrl_escalation.1079476446 |
|
|
Jun 30 07:28:32 PM PDT 24 |
Jun 30 07:37:24 PM PDT 24 |
4288944992 ps |
| T931 |
/workspace/coverage/default/60.chip_sw_alert_handler_lpg_sleep_mode_alerts.1599664333 |
|
|
Jun 30 08:07:18 PM PDT 24 |
Jun 30 08:13:44 PM PDT 24 |
3523141304 ps |
| T932 |
/workspace/coverage/default/1.chip_sw_pwrmgr_deep_sleep_por_reset.3318061232 |
|
|
Jun 30 07:42:05 PM PDT 24 |
Jun 30 07:51:30 PM PDT 24 |
9145684796 ps |
| T933 |
/workspace/coverage/default/11.chip_sw_lc_ctrl_transition.2919966914 |
|
|
Jun 30 08:02:54 PM PDT 24 |
Jun 30 08:15:28 PM PDT 24 |
8971871948 ps |
| T934 |
/workspace/coverage/default/79.chip_sw_all_escalation_resets.3959828277 |
|
|
Jun 30 08:09:54 PM PDT 24 |
Jun 30 08:23:38 PM PDT 24 |
4621552808 ps |
| T277 |
/workspace/coverage/default/2.chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq.538594806 |
|
|
Jun 30 07:59:33 PM PDT 24 |
Jun 30 08:08:37 PM PDT 24 |
5382482460 ps |
| T935 |
/workspace/coverage/default/1.chip_sw_gpio_smoketest.2510358176 |
|
|
Jun 30 07:48:54 PM PDT 24 |
Jun 30 07:54:51 PM PDT 24 |
3450295289 ps |
| T729 |
/workspace/coverage/default/33.chip_sw_all_escalation_resets.1069113284 |
|
|
Jun 30 08:06:27 PM PDT 24 |
Jun 30 08:19:14 PM PDT 24 |
4599704856 ps |
| T936 |
/workspace/coverage/default/2.chip_sw_flash_ctrl_access_jitter_en.1219534674 |
|
|
Jun 30 07:51:37 PM PDT 24 |
Jun 30 08:09:44 PM PDT 24 |
6230375058 ps |
| T937 |
/workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_lc.1687656727 |
|
|
Jun 30 07:31:13 PM PDT 24 |
Jun 30 07:47:19 PM PDT 24 |
11195257930 ps |
| T938 |
/workspace/coverage/default/2.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.2493527299 |
|
|
Jun 30 07:50:05 PM PDT 24 |
Jun 30 07:58:31 PM PDT 24 |
4510764207 ps |
| T939 |
/workspace/coverage/default/0.chip_sw_rv_core_ibex_rnd.258742029 |
|
|
Jun 30 07:29:20 PM PDT 24 |
Jun 30 07:46:45 PM PDT 24 |
5199001876 ps |
| T177 |
/workspace/coverage/default/0.chip_sw_csrng_fuse_en_sw_app_read_test.1030941099 |
|
|
Jun 30 07:31:21 PM PDT 24 |
Jun 30 07:39:51 PM PDT 24 |
5088941270 ps |
| T940 |
/workspace/coverage/default/2.rom_e2e_smoke.319635082 |
|
|
Jun 30 08:05:42 PM PDT 24 |
Jun 30 09:02:51 PM PDT 24 |
15068260744 ps |
| T672 |
/workspace/coverage/default/2.rom_volatile_raw_unlock.903786307 |
|
|
Jun 30 07:58:55 PM PDT 24 |
Jun 30 08:00:42 PM PDT 24 |
3007250323 ps |
| T941 |
/workspace/coverage/default/1.chip_sw_hmac_oneshot.10140161 |
|
|
Jun 30 07:45:40 PM PDT 24 |
Jun 30 07:53:24 PM PDT 24 |
3035042962 ps |
| T40 |
/workspace/coverage/default/1.chip_sw_gpio.3644731517 |
|
|
Jun 30 07:42:07 PM PDT 24 |
Jun 30 07:52:51 PM PDT 24 |
4217147412 ps |
| T942 |
/workspace/coverage/default/4.chip_sw_uart_tx_rx_idx2.1388103025 |
|
|
Jun 30 08:02:02 PM PDT 24 |
Jun 30 08:12:46 PM PDT 24 |
3917794520 ps |
| T943 |
/workspace/coverage/default/0.chip_sw_csrng_smoketest.2432074172 |
|
|
Jun 30 07:39:05 PM PDT 24 |
Jun 30 07:42:28 PM PDT 24 |
2736805434 ps |
| T944 |
/workspace/coverage/default/0.chip_sw_pwrmgr_sleep_power_glitch_reset.2211369057 |
|
|
Jun 30 07:29:24 PM PDT 24 |
Jun 30 07:36:58 PM PDT 24 |
5423966020 ps |
| T945 |
/workspace/coverage/default/1.chip_sw_pwrmgr_usb_clk_disabled_when_active.1273584898 |
|
|
Jun 30 07:43:48 PM PDT 24 |
Jun 30 07:53:22 PM PDT 24 |
5299897256 ps |
| T324 |
/workspace/coverage/default/2.chip_sw_flash_ctrl_ops_jitter_en.2078040820 |
|
|
Jun 30 07:50:18 PM PDT 24 |
Jun 30 08:02:02 PM PDT 24 |
4728660574 ps |
| T946 |
/workspace/coverage/default/2.chip_sw_uart_tx_rx_idx2.2554009031 |
|
|
Jun 30 07:49:36 PM PDT 24 |
Jun 30 07:58:05 PM PDT 24 |
4255931580 ps |
| T947 |
/workspace/coverage/default/1.chip_sw_pwrmgr_deep_sleep_power_glitch_reset.1599568959 |
|
|
Jun 30 07:42:36 PM PDT 24 |
Jun 30 07:52:24 PM PDT 24 |
6759412500 ps |
| T948 |
/workspace/coverage/default/0.chip_sw_kmac_mode_kmac_jitter_en.333773648 |
|
|
Jun 30 07:29:33 PM PDT 24 |
Jun 30 07:34:14 PM PDT 24 |
2848554334 ps |
| T766 |
/workspace/coverage/default/20.chip_sw_all_escalation_resets.1271612727 |
|
|
Jun 30 08:07:14 PM PDT 24 |
Jun 30 08:17:10 PM PDT 24 |
4541402110 ps |
| T949 |
/workspace/coverage/default/2.chip_sw_otp_ctrl_lc_signals_dev.653232664 |
|
|
Jun 30 07:52:00 PM PDT 24 |
Jun 30 08:18:47 PM PDT 24 |
8035234312 ps |
| T950 |
/workspace/coverage/default/0.chip_sw_rstmgr_smoketest.1478078922 |
|
|
Jun 30 07:39:23 PM PDT 24 |
Jun 30 07:41:48 PM PDT 24 |
2595635320 ps |
| T951 |
/workspace/coverage/default/2.chip_sw_kmac_mode_kmac.3892930277 |
|
|
Jun 30 07:57:18 PM PDT 24 |
Jun 30 08:02:30 PM PDT 24 |
2856792048 ps |
| T952 |
/workspace/coverage/default/2.chip_sw_sleep_sram_ret_contents_scramble.1559277708 |
|
|
Jun 30 07:56:14 PM PDT 24 |
Jun 30 08:10:18 PM PDT 24 |
7943867082 ps |
| T309 |
/workspace/coverage/default/1.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.1234807741 |
|
|
Jun 30 07:42:42 PM PDT 24 |
Jun 30 08:00:25 PM PDT 24 |
8402666222 ps |
| T953 |
/workspace/coverage/default/3.chip_sw_aon_timer_sleep_wdog_sleep_pause.3909687222 |
|
|
Jun 30 08:01:45 PM PDT 24 |
Jun 30 08:12:02 PM PDT 24 |
7774103932 ps |
| T954 |
/workspace/coverage/default/0.chip_tap_straps_prod.1727476690 |
|
|
Jun 30 07:33:58 PM PDT 24 |
Jun 30 07:42:23 PM PDT 24 |
6088107284 ps |
| T715 |
/workspace/coverage/default/86.chip_sw_alert_handler_lpg_sleep_mode_alerts.3194797763 |
|
|
Jun 30 08:10:43 PM PDT 24 |
Jun 30 08:16:50 PM PDT 24 |
3088604456 ps |
| T955 |
/workspace/coverage/default/1.rom_e2e_shutdown_exception_c.2630339131 |
|
|
Jun 30 07:52:54 PM PDT 24 |
Jun 30 08:59:43 PM PDT 24 |
14010912141 ps |
| T735 |
/workspace/coverage/default/78.chip_sw_all_escalation_resets.4207087923 |
|
|
Jun 30 08:09:14 PM PDT 24 |
Jun 30 08:19:54 PM PDT 24 |
4612487548 ps |
| T149 |
/workspace/coverage/default/0.chip_sw_exit_test_unlocked_bootstrap.707624550 |
|
|
Jun 30 07:32:12 PM PDT 24 |
Jun 30 10:45:50 PM PDT 24 |
59939717440 ps |
| T956 |
/workspace/coverage/default/51.chip_sw_all_escalation_resets.1536822133 |
|
|
Jun 30 08:06:29 PM PDT 24 |
Jun 30 08:16:17 PM PDT 24 |
5991728660 ps |
| T957 |
/workspace/coverage/default/1.chip_sw_flash_crash_alert.1745518387 |
|
|
Jun 30 07:49:13 PM PDT 24 |
Jun 30 07:59:29 PM PDT 24 |
5680554932 ps |
| T349 |
/workspace/coverage/default/1.chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up.3117610326 |
|
|
Jun 30 07:47:28 PM PDT 24 |
Jun 30 07:52:13 PM PDT 24 |
5355722360 ps |
| T46 |
/workspace/coverage/default/0.chip_sw_spi_host_tx_rx.1885285782 |
|
|
Jun 30 07:27:58 PM PDT 24 |
Jun 30 07:33:16 PM PDT 24 |
2980137784 ps |
| T958 |
/workspace/coverage/default/14.chip_sw_lc_ctrl_transition.1789647241 |
|
|
Jun 30 08:04:14 PM PDT 24 |
Jun 30 08:18:40 PM PDT 24 |
11113393206 ps |
| T730 |
/workspace/coverage/default/13.chip_sw_all_escalation_resets.4078158044 |
|
|
Jun 30 08:02:43 PM PDT 24 |
Jun 30 08:14:41 PM PDT 24 |
5964912074 ps |
| T769 |
/workspace/coverage/default/11.chip_sw_all_escalation_resets.577174835 |
|
|
Jun 30 08:03:30 PM PDT 24 |
Jun 30 08:14:03 PM PDT 24 |
4503631720 ps |
| T714 |
/workspace/coverage/default/72.chip_sw_all_escalation_resets.4247061283 |
|
|
Jun 30 08:10:44 PM PDT 24 |
Jun 30 08:24:10 PM PDT 24 |
5422946920 ps |
| T959 |
/workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0.4027659401 |
|
|
Jun 30 07:46:56 PM PDT 24 |
Jun 30 07:59:32 PM PDT 24 |
5075029182 ps |
| T960 |
/workspace/coverage/default/1.chip_sw_aes_masking_off.555866617 |
|
|
Jun 30 07:44:28 PM PDT 24 |
Jun 30 07:48:45 PM PDT 24 |
2890559727 ps |
| T961 |
/workspace/coverage/default/0.chip_sw_pwrmgr_main_power_glitch_reset.2786625017 |
|
|
Jun 30 07:29:03 PM PDT 24 |
Jun 30 07:36:42 PM PDT 24 |
4587150545 ps |
| T962 |
/workspace/coverage/default/2.chip_sw_rstmgr_smoketest.3472744243 |
|
|
Jun 30 08:00:32 PM PDT 24 |
Jun 30 08:03:56 PM PDT 24 |
2696685800 ps |
| T220 |
/workspace/coverage/default/1.chip_sw_lc_walkthrough_dev.936610443 |
|
|
Jun 30 07:42:13 PM PDT 24 |
Jun 30 09:15:09 PM PDT 24 |
48384336220 ps |
| T788 |
/workspace/coverage/default/37.chip_sw_all_escalation_resets.3542474445 |
|
|
Jun 30 08:07:16 PM PDT 24 |
Jun 30 08:16:35 PM PDT 24 |
4835035160 ps |
| T963 |
/workspace/coverage/default/1.chip_sw_alert_handler_ping_ok.3944105382 |
|
|
Jun 30 07:45:25 PM PDT 24 |
Jun 30 08:10:19 PM PDT 24 |
8133920158 ps |
| T736 |
/workspace/coverage/default/3.chip_sw_alert_handler_lpg_sleep_mode_alerts.2892867391 |
|
|
Jun 30 08:00:55 PM PDT 24 |
Jun 30 08:08:08 PM PDT 24 |
4178713796 ps |
| T964 |
/workspace/coverage/default/2.rom_e2e_asm_init_prod_end.2853496293 |
|
|
Jun 30 08:06:54 PM PDT 24 |
Jun 30 09:17:19 PM PDT 24 |
15360153585 ps |
| T111 |
/workspace/coverage/default/2.chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq.3091550463 |
|
|
Jun 30 07:58:24 PM PDT 24 |
Jun 30 09:03:33 PM PDT 24 |
24521884016 ps |
| T965 |
/workspace/coverage/default/1.chip_sw_kmac_mode_kmac.2516266262 |
|
|
Jun 30 07:46:45 PM PDT 24 |
Jun 30 07:51:38 PM PDT 24 |
3630725724 ps |
| T799 |
/workspace/coverage/default/67.chip_sw_all_escalation_resets.2643353126 |
|
|
Jun 30 08:07:41 PM PDT 24 |
Jun 30 08:19:40 PM PDT 24 |
5701971280 ps |
| T233 |
/workspace/coverage/default/7.chip_sw_all_escalation_resets.2233320993 |
|
|
Jun 30 08:02:50 PM PDT 24 |
Jun 30 08:11:29 PM PDT 24 |
4688260800 ps |
| T713 |
/workspace/coverage/default/0.chip_sw_alert_handler_lpg_sleep_mode_pings.183929931 |
|
|
Jun 30 07:28:50 PM PDT 24 |
Jun 30 07:49:40 PM PDT 24 |
13039263852 ps |
| T966 |
/workspace/coverage/default/0.chip_sw_kmac_mode_kmac.1323817465 |
|
|
Jun 30 07:31:12 PM PDT 24 |
Jun 30 07:36:18 PM PDT 24 |
3293700070 ps |
| T776 |
/workspace/coverage/default/73.chip_sw_alert_handler_lpg_sleep_mode_alerts.1149241049 |
|
|
Jun 30 08:09:42 PM PDT 24 |
Jun 30 08:17:00 PM PDT 24 |
3600660512 ps |
| T967 |
/workspace/coverage/default/2.chip_sw_sleep_pwm_pulses.4208508641 |
|
|
Jun 30 07:49:33 PM PDT 24 |
Jun 30 08:14:50 PM PDT 24 |
8249930438 ps |
| T312 |
/workspace/coverage/default/0.chip_sw_i2c_host_tx_rx_idx2.341973563 |
|
|
Jun 30 07:28:46 PM PDT 24 |
Jun 30 07:40:35 PM PDT 24 |
4098954350 ps |
| T968 |
/workspace/coverage/default/0.chip_sw_aes_enc.1711749830 |
|
|
Jun 30 07:28:36 PM PDT 24 |
Jun 30 07:32:52 PM PDT 24 |
3314329916 ps |
| T969 |
/workspace/coverage/default/1.chip_sw_pwrmgr_random_sleep_all_reset_reqs.3206823014 |
|
|
Jun 30 07:42:04 PM PDT 24 |
Jun 30 08:22:34 PM PDT 24 |
21497547327 ps |
| T774 |
/workspace/coverage/default/31.chip_sw_alert_handler_lpg_sleep_mode_alerts.2763815349 |
|
|
Jun 30 08:04:41 PM PDT 24 |
Jun 30 08:11:34 PM PDT 24 |
3745775344 ps |
| T970 |
/workspace/coverage/default/2.chip_sw_flash_ctrl_clock_freqs.232073701 |
|
|
Jun 30 07:50:56 PM PDT 24 |
Jun 30 08:10:38 PM PDT 24 |
5592004875 ps |
| T786 |
/workspace/coverage/default/34.chip_sw_alert_handler_lpg_sleep_mode_alerts.2896792846 |
|
|
Jun 30 08:04:30 PM PDT 24 |
Jun 30 08:12:35 PM PDT 24 |
3637092580 ps |
| T178 |
/workspace/coverage/default/1.chip_sw_csrng_lc_hw_debug_en_test.1387361528 |
|
|
Jun 30 07:46:54 PM PDT 24 |
Jun 30 07:57:31 PM PDT 24 |
5466899564 ps |
| T697 |
/workspace/coverage/default/10.chip_sw_alert_handler_lpg_sleep_mode_alerts.4026304804 |
|
|
Jun 30 08:02:22 PM PDT 24 |
Jun 30 08:09:32 PM PDT 24 |
3253076308 ps |
| T971 |
/workspace/coverage/default/5.chip_sw_lc_ctrl_transition.548423767 |
|
|
Jun 30 08:03:12 PM PDT 24 |
Jun 30 08:18:30 PM PDT 24 |
9040074240 ps |
| T278 |
/workspace/coverage/default/0.chip_sw_data_integrity_escalation.39716587 |
|
|
Jun 30 07:28:27 PM PDT 24 |
Jun 30 07:39:44 PM PDT 24 |
5744108250 ps |
| T972 |
/workspace/coverage/default/0.chip_sw_clkmgr_jitter_reduced_freq.3251326791 |
|
|
Jun 30 07:37:15 PM PDT 24 |
Jun 30 07:39:32 PM PDT 24 |
2719920350 ps |
| T973 |
/workspace/coverage/default/2.chip_sw_ast_clk_outputs.177917577 |
|
|
Jun 30 07:57:40 PM PDT 24 |
Jun 30 08:13:44 PM PDT 24 |
6537899096 ps |
| T198 |
/workspace/coverage/default/0.chip_sw_sysrst_ctrl_reset.32540574 |
|
|
Jun 30 07:27:49 PM PDT 24 |
Jun 30 08:03:20 PM PDT 24 |
25711573736 ps |
| T310 |
/workspace/coverage/default/16.chip_sw_uart_rand_baudrate.2718841137 |
|
|
Jun 30 08:02:33 PM PDT 24 |
Jun 30 08:44:15 PM PDT 24 |
12524194300 ps |
| T670 |
/workspace/coverage/default/1.chip_sw_rv_dm_access_after_escalation_reset.838184939 |
|
|
Jun 30 07:47:53 PM PDT 24 |
Jun 30 07:54:51 PM PDT 24 |
4637715749 ps |
| T974 |
/workspace/coverage/default/0.chip_sw_aes_enc_jitter_en.1825734177 |
|
|
Jun 30 07:29:34 PM PDT 24 |
Jun 30 07:33:08 PM PDT 24 |
2672253581 ps |
| T12 |
/workspace/coverage/default/1.chip_sw_sleep_pin_retention.1147801520 |
|
|
Jun 30 07:41:17 PM PDT 24 |
Jun 30 07:45:54 PM PDT 24 |
3353889384 ps |
| T524 |
/workspace/coverage/default/1.chip_sw_rv_core_ibex_nmi_irq.1679089866 |
|
|
Jun 30 07:44:13 PM PDT 24 |
Jun 30 07:59:29 PM PDT 24 |
5553557236 ps |
| T975 |
/workspace/coverage/default/6.chip_sw_lc_ctrl_transition.828486805 |
|
|
Jun 30 08:01:01 PM PDT 24 |
Jun 30 08:17:11 PM PDT 24 |
11085628375 ps |
| T976 |
/workspace/coverage/default/4.chip_sw_uart_tx_rx_alt_clk_freq.2015639536 |
|
|
Jun 30 08:01:24 PM PDT 24 |
Jun 30 08:27:42 PM PDT 24 |
7605602085 ps |
| T977 |
/workspace/coverage/default/2.chip_sw_power_idle_load.1577992611 |
|
|
Jun 30 07:58:51 PM PDT 24 |
Jun 30 08:11:19 PM PDT 24 |
4028270100 ps |
| T167 |
/workspace/coverage/default/1.chip_sw_lc_ctrl_rand_to_scrap.1597309394 |
|
|
Jun 30 07:42:20 PM PDT 24 |
Jun 30 07:44:50 PM PDT 24 |
3390781169 ps |
| T978 |
/workspace/coverage/default/1.chip_sw_csrng_smoketest.1745943890 |
|
|
Jun 30 07:48:09 PM PDT 24 |
Jun 30 07:51:36 PM PDT 24 |
3138111800 ps |
| T979 |
/workspace/coverage/default/2.chip_sw_clkmgr_off_otbn_trans.1423468724 |
|
|
Jun 30 07:56:29 PM PDT 24 |
Jun 30 08:02:49 PM PDT 24 |
3800560696 ps |
| T980 |
/workspace/coverage/default/4.chip_sw_aon_timer_sleep_wdog_sleep_pause.2740723118 |
|
|
Jun 30 08:02:17 PM PDT 24 |
Jun 30 08:09:07 PM PDT 24 |
7085745344 ps |
| T981 |
/workspace/coverage/default/0.chip_sw_alert_handler_ping_timeout.1087403770 |
|
|
Jun 30 07:28:52 PM PDT 24 |
Jun 30 07:38:54 PM PDT 24 |
5695791192 ps |
| T982 |
/workspace/coverage/default/0.chip_sw_clkmgr_jitter_frequency.533466557 |
|
|
Jun 30 07:31:54 PM PDT 24 |
Jun 30 07:38:20 PM PDT 24 |
4046341368 ps |
| T425 |
/workspace/coverage/default/46.chip_sw_alert_handler_lpg_sleep_mode_alerts.459392976 |
|
|
Jun 30 08:05:31 PM PDT 24 |
Jun 30 08:12:15 PM PDT 24 |
3690959280 ps |
| T983 |
/workspace/coverage/default/1.rom_e2e_keymgr_init_rom_ext_meas.2790836908 |
|
|
Jun 30 07:52:59 PM PDT 24 |
Jun 30 09:00:18 PM PDT 24 |
14600678696 ps |
| T52 |
/workspace/coverage/default/1.chip_sw_spi_device_tpm.1803168331 |
|
|
Jun 30 07:41:12 PM PDT 24 |
Jun 30 07:46:24 PM PDT 24 |
3458603178 ps |
| T234 |
/workspace/coverage/default/2.chip_sw_rstmgr_cpu_info.778691314 |
|
|
Jun 30 07:52:48 PM PDT 24 |
Jun 30 08:01:45 PM PDT 24 |
5089689666 ps |
| T984 |
/workspace/coverage/default/1.chip_sw_lc_walkthrough_prodend.1216852609 |
|
|
Jun 30 07:42:54 PM PDT 24 |
Jun 30 08:01:13 PM PDT 24 |
9682403125 ps |
| T753 |
/workspace/coverage/default/9.chip_sw_all_escalation_resets.1103075259 |
|
|
Jun 30 08:01:01 PM PDT 24 |
Jun 30 08:09:39 PM PDT 24 |
4171214360 ps |
| T985 |
/workspace/coverage/default/18.chip_sw_uart_rand_baudrate.518246602 |
|
|
Jun 30 08:02:47 PM PDT 24 |
Jun 30 08:49:31 PM PDT 24 |
13088460384 ps |
| T673 |
/workspace/coverage/default/0.rom_volatile_raw_unlock.1928726678 |
|
|
Jun 30 07:39:11 PM PDT 24 |
Jun 30 07:41:04 PM PDT 24 |
2181128629 ps |
| T986 |
/workspace/coverage/default/2.chip_sw_alert_handler_escalation.2521803216 |
|
|
Jun 30 07:53:49 PM PDT 24 |
Jun 30 08:02:31 PM PDT 24 |
4704476778 ps |
| T987 |
/workspace/coverage/default/0.chip_sw_keymgr_sideload_kmac.4003557498 |
|
|
Jun 30 07:29:39 PM PDT 24 |
Jun 30 07:56:21 PM PDT 24 |
9992063726 ps |
| T988 |
/workspace/coverage/default/0.chip_sw_pwrmgr_deep_sleep_power_glitch_reset.1056729687 |
|
|
Jun 30 07:28:41 PM PDT 24 |
Jun 30 07:37:22 PM PDT 24 |
7577286446 ps |
| T989 |
/workspace/coverage/default/0.rom_keymgr_functest.145246990 |
|
|
Jun 30 07:38:47 PM PDT 24 |
Jun 30 07:50:29 PM PDT 24 |
4816265536 ps |
| T990 |
/workspace/coverage/default/0.rom_e2e_keymgr_init_rom_ext_no_meas.1025511436 |
|
|
Jun 30 07:43:11 PM PDT 24 |
Jun 30 08:52:45 PM PDT 24 |
15566909456 ps |
| T242 |
/workspace/coverage/default/2.chip_sw_plic_sw_irq.3559726034 |
|
|
Jun 30 07:57:53 PM PDT 24 |
Jun 30 08:03:15 PM PDT 24 |
2965527162 ps |
| T991 |
/workspace/coverage/default/1.rom_e2e_asm_init_prod.1548792277 |
|
|
Jun 30 07:52:42 PM PDT 24 |
Jun 30 09:00:13 PM PDT 24 |
15949436954 ps |
| T992 |
/workspace/coverage/default/9.chip_sw_csrng_edn_concurrency.223199026 |
|
|
Jun 30 08:02:45 PM PDT 24 |
Jun 30 09:40:22 PM PDT 24 |
24776764804 ps |
| T709 |
/workspace/coverage/default/0.chip_sw_alert_handler_lpg_sleep_mode_alerts.2904564960 |
|
|
Jun 30 07:29:44 PM PDT 24 |
Jun 30 07:36:10 PM PDT 24 |
3505414574 ps |
| T767 |
/workspace/coverage/default/41.chip_sw_alert_handler_lpg_sleep_mode_alerts.2970381021 |
|
|
Jun 30 08:05:28 PM PDT 24 |
Jun 30 08:11:39 PM PDT 24 |
3935470100 ps |
| T303 |
/workspace/coverage/default/0.chip_sw_i2c_host_tx_rx_idx1.1289676580 |
|
|
Jun 30 07:32:52 PM PDT 24 |
Jun 30 07:46:58 PM PDT 24 |
5166908886 ps |
| T224 |
/workspace/coverage/default/1.chip_sw_flash_init_reduced_freq.4220863924 |
|
|
Jun 30 07:46:57 PM PDT 24 |
Jun 30 08:30:54 PM PDT 24 |
24994747721 ps |
| T993 |
/workspace/coverage/default/2.chip_sw_edn_kat.3066408048 |
|
|
Jun 30 07:54:00 PM PDT 24 |
Jun 30 08:05:10 PM PDT 24 |
3141043000 ps |
| T994 |
/workspace/coverage/default/0.chip_sw_keymgr_key_derivation_jitter_en.3533185658 |
|
|
Jun 30 07:30:21 PM PDT 24 |
Jun 30 08:14:35 PM PDT 24 |
11882268323 ps |
| T376 |
/workspace/coverage/default/1.chip_sw_rstmgr_sw_rst.1576619124 |
|
|
Jun 30 07:40:54 PM PDT 24 |
Jun 30 07:43:31 PM PDT 24 |
2909555840 ps |
| T675 |
/workspace/coverage/default/2.chip_sw_pwrmgr_sleep_disabled.3162254493 |
|
|
Jun 30 07:53:59 PM PDT 24 |
Jun 30 07:57:34 PM PDT 24 |
3164892516 ps |
| T995 |
/workspace/coverage/default/69.chip_sw_all_escalation_resets.1487200101 |
|
|
Jun 30 08:08:45 PM PDT 24 |
Jun 30 08:19:04 PM PDT 24 |
5133066508 ps |
| T996 |
/workspace/coverage/default/0.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.487846718 |
|
|
Jun 30 07:32:04 PM PDT 24 |
Jun 30 07:55:50 PM PDT 24 |
8757850473 ps |
| T768 |
/workspace/coverage/default/89.chip_sw_alert_handler_lpg_sleep_mode_alerts.3438496580 |
|
|
Jun 30 08:11:10 PM PDT 24 |
Jun 30 08:16:58 PM PDT 24 |
3283769300 ps |
| T997 |
/workspace/coverage/default/0.rom_e2e_keymgr_init_rom_ext_meas.326783812 |
|
|
Jun 30 07:43:05 PM PDT 24 |
Jun 30 08:53:52 PM PDT 24 |
14798304976 ps |
| T87 |
/workspace/coverage/default/0.chip_sw_usbdev_vbus.1114925458 |
|
|
Jun 30 07:29:14 PM PDT 24 |
Jun 30 07:33:51 PM PDT 24 |
3344599140 ps |
| T998 |
/workspace/coverage/default/0.rom_e2e_static_critical.2341162255 |
|
|
Jun 30 07:43:42 PM PDT 24 |
Jun 30 09:02:15 PM PDT 24 |
16929082788 ps |
| T726 |
/workspace/coverage/default/80.chip_sw_alert_handler_lpg_sleep_mode_alerts.2283588738 |
|
|
Jun 30 08:09:16 PM PDT 24 |
Jun 30 08:18:05 PM PDT 24 |
3874127820 ps |
| T304 |
/workspace/coverage/default/0.chip_sw_rstmgr_alert_info.4288352128 |
|
|
Jun 30 07:27:41 PM PDT 24 |
Jun 30 07:45:34 PM PDT 24 |
9651204470 ps |
| T999 |
/workspace/coverage/default/2.chip_sw_uart_tx_rx_idx3.9202636 |
|
|
Jun 30 07:50:37 PM PDT 24 |
Jun 30 08:00:09 PM PDT 24 |
4233011496 ps |
| T1000 |
/workspace/coverage/default/19.chip_sw_uart_rand_baudrate.3218387520 |
|
|
Jun 30 08:06:40 PM PDT 24 |
Jun 30 08:14:23 PM PDT 24 |
4084973350 ps |
| T350 |
/workspace/coverage/default/0.chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up.2952723697 |
|
|
Jun 30 07:33:44 PM PDT 24 |
Jun 30 07:43:45 PM PDT 24 |
7381149054 ps |
| T108 |
/workspace/coverage/default/0.chip_sw_csrng_edn_concurrency_reduced_freq.1852261359 |
|
|
Jun 30 07:35:34 PM PDT 24 |
Jun 30 10:34:23 PM PDT 24 |
63372393432 ps |
| T1001 |
/workspace/coverage/default/0.chip_sw_kmac_app_rom.1309158989 |
|
|
Jun 30 07:29:48 PM PDT 24 |
Jun 30 07:33:50 PM PDT 24 |
2449041560 ps |
| T526 |
/workspace/coverage/default/1.chip_sw_pwrmgr_all_reset_reqs.2029548612 |
|
|
Jun 30 07:42:22 PM PDT 24 |
Jun 30 08:07:09 PM PDT 24 |
10429436582 ps |
| T748 |
/workspace/coverage/default/88.chip_sw_all_escalation_resets.1292594749 |
|
|
Jun 30 08:10:05 PM PDT 24 |
Jun 30 08:22:33 PM PDT 24 |
5635553178 ps |
| T1002 |
/workspace/coverage/default/2.chip_sw_clkmgr_off_peri.754975568 |
|
|
Jun 30 07:56:20 PM PDT 24 |
Jun 30 08:16:13 PM PDT 24 |
11750938268 ps |
| T1003 |
/workspace/coverage/default/2.chip_sw_otp_ctrl_lc_signals_rma.3288305826 |
|
|
Jun 30 07:51:24 PM PDT 24 |
Jun 30 08:12:03 PM PDT 24 |
8098779848 ps |
| T1004 |
/workspace/coverage/default/2.rom_e2e_shutdown_output.1844595631 |
|
|
Jun 30 08:02:23 PM PDT 24 |
Jun 30 08:59:35 PM PDT 24 |
28464129875 ps |
| T1005 |
/workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_slow_rma.1669594782 |
|
|
Jun 30 07:32:14 PM PDT 24 |
Jun 30 07:42:29 PM PDT 24 |
5317319374 ps |
| T1006 |
/workspace/coverage/default/53.chip_sw_alert_handler_lpg_sleep_mode_alerts.3975706535 |
|
|
Jun 30 08:07:28 PM PDT 24 |
Jun 30 08:13:43 PM PDT 24 |
3488884424 ps |
| T1007 |
/workspace/coverage/default/0.chip_sw_otp_ctrl_dai_lock.2216260829 |
|
|
Jun 30 07:28:01 PM PDT 24 |
Jun 30 09:14:44 PM PDT 24 |
28278260744 ps |
| T1008 |
/workspace/coverage/default/1.chip_sw_lc_walkthrough_testunlocks.1528725748 |
|
|
Jun 30 07:43:23 PM PDT 24 |
Jun 30 08:21:54 PM PDT 24 |
24165008920 ps |
| T1009 |
/workspace/coverage/default/1.rom_e2e_asm_init_rma.1260535567 |
|
|
Jun 30 07:53:12 PM PDT 24 |
Jun 30 08:57:32 PM PDT 24 |
15176824523 ps |
| T1010 |
/workspace/coverage/default/0.chip_sw_sleep_pwm_pulses.3440038114 |
|
|
Jun 30 07:28:53 PM PDT 24 |
Jun 30 07:52:36 PM PDT 24 |
9984818430 ps |
| T1011 |
/workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_slow_dev.2832403784 |
|
|
Jun 30 07:46:46 PM PDT 24 |
Jun 30 07:58:41 PM PDT 24 |
5536311368 ps |
| T1012 |
/workspace/coverage/default/0.chip_sw_example_flash.3796969602 |
|
|
Jun 30 07:28:24 PM PDT 24 |
Jun 30 07:33:21 PM PDT 24 |
3162081060 ps |
| T1013 |
/workspace/coverage/default/4.chip_tap_straps_prod.161532755 |
|
|
Jun 30 08:00:55 PM PDT 24 |
Jun 30 08:03:17 PM PDT 24 |
2405800910 ps |
| T1014 |
/workspace/coverage/default/1.chip_sw_hmac_multistream.2031417328 |
|
|
Jun 30 07:45:19 PM PDT 24 |
Jun 30 08:18:20 PM PDT 24 |
7753890368 ps |
| T760 |
/workspace/coverage/default/93.chip_sw_all_escalation_resets.1792200146 |
|
|
Jun 30 08:10:31 PM PDT 24 |
Jun 30 08:18:37 PM PDT 24 |
4257217520 ps |
| T1015 |
/workspace/coverage/default/0.chip_sw_aes_smoketest.3056849838 |
|
|
Jun 30 07:40:35 PM PDT 24 |
Jun 30 07:44:14 PM PDT 24 |
2638605118 ps |
| T1016 |
/workspace/coverage/default/2.chip_sw_kmac_smoketest.3509023988 |
|
|
Jun 30 07:59:05 PM PDT 24 |
Jun 30 08:04:13 PM PDT 24 |
3314672660 ps |
| T1017 |
/workspace/coverage/default/2.chip_tap_straps_dev.1155849983 |
|
|
Jun 30 07:57:14 PM PDT 24 |
Jun 30 08:09:05 PM PDT 24 |
6355174774 ps |
| T1018 |
/workspace/coverage/default/2.chip_sw_aon_timer_smoketest.3460481145 |
|
|
Jun 30 08:00:13 PM PDT 24 |
Jun 30 08:06:53 PM PDT 24 |
3330695332 ps |
| T761 |
/workspace/coverage/default/8.chip_sw_alert_handler_lpg_sleep_mode_alerts.786288645 |
|
|
Jun 30 08:03:38 PM PDT 24 |
Jun 30 08:09:53 PM PDT 24 |
3710676144 ps |
| T138 |
/workspace/coverage/default/2.chip_sw_pwrmgr_full_aon_reset.645491303 |
|
|
Jun 30 07:52:24 PM PDT 24 |
Jun 30 08:02:44 PM PDT 24 |
7482619785 ps |
| T1019 |
/workspace/coverage/default/3.chip_sw_uart_rand_baudrate.3415958781 |
|
|
Jun 30 08:01:39 PM PDT 24 |
Jun 30 08:54:58 PM PDT 24 |
13577091090 ps |
| T227 |
/workspace/coverage/default/2.chip_sw_lc_walkthrough_prod.2572693524 |
|
|
Jun 30 07:52:30 PM PDT 24 |
Jun 30 09:28:52 PM PDT 24 |
49695455962 ps |
| T711 |
/workspace/coverage/default/8.chip_sw_all_escalation_resets.880441451 |
|
|
Jun 30 08:02:00 PM PDT 24 |
Jun 30 08:12:45 PM PDT 24 |
5803163436 ps |
| T674 |
/workspace/coverage/default/1.rom_volatile_raw_unlock.2716357923 |
|
|
Jun 30 07:49:06 PM PDT 24 |
Jun 30 07:50:57 PM PDT 24 |
2582605337 ps |
| T698 |
/workspace/coverage/default/38.chip_sw_alert_handler_lpg_sleep_mode_alerts.1929459142 |
|
|
Jun 30 08:05:01 PM PDT 24 |
Jun 30 08:12:34 PM PDT 24 |
4233521600 ps |
| T1020 |
/workspace/coverage/default/1.chip_sw_otp_ctrl_lc_signals_dev.574605046 |
|
|
Jun 30 07:42:26 PM PDT 24 |
Jun 30 08:02:19 PM PDT 24 |
7697173784 ps |
| T1021 |
/workspace/coverage/default/7.chip_sw_lc_ctrl_transition.1229192695 |
|
|
Jun 30 08:01:45 PM PDT 24 |
Jun 30 08:16:27 PM PDT 24 |
12577820924 ps |
| T247 |
/workspace/coverage/default/0.rom_e2e_jtag_inject_rma.15402530 |
|
|
Jun 30 07:38:44 PM PDT 24 |
Jun 30 08:27:26 PM PDT 24 |
27190914427 ps |
| T1022 |
/workspace/coverage/default/0.chip_sw_example_rom.596235494 |
|
|
Jun 30 07:26:43 PM PDT 24 |
Jun 30 07:28:51 PM PDT 24 |
2384364952 ps |
| T1023 |
/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_bad_prod.3270510185 |
|
|
Jun 30 07:40:37 PM PDT 24 |
Jun 30 08:56:47 PM PDT 24 |
15335120872 ps |
| T1024 |
/workspace/coverage/default/2.chip_sw_clkmgr_off_kmac_trans.3039880581 |
|
|
Jun 30 07:57:33 PM PDT 24 |
Jun 30 08:06:06 PM PDT 24 |
5075931280 ps |
| T1025 |
/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0.1243630889 |
|
|
Jun 30 07:41:11 PM PDT 24 |
Jun 30 08:39:39 PM PDT 24 |
11688530192 ps |
| T1026 |
/workspace/coverage/default/2.chip_sw_uart_tx_rx.3604258553 |
|
|
Jun 30 07:51:06 PM PDT 24 |
Jun 30 08:02:16 PM PDT 24 |
3686404638 ps |
| T705 |
/workspace/coverage/default/23.chip_sw_all_escalation_resets.1210342368 |
|
|
Jun 30 08:04:36 PM PDT 24 |
Jun 30 08:13:51 PM PDT 24 |
4919121800 ps |
| T109 |
/workspace/coverage/default/2.chip_sw_csrng_edn_concurrency_reduced_freq.1869751255 |
|
|
Jun 30 07:58:49 PM PDT 24 |
Jun 30 09:00:21 PM PDT 24 |
24743472310 ps |
| T1027 |
/workspace/coverage/default/1.chip_sw_pwrmgr_normal_sleep_all_reset_reqs.1544010336 |
|
|
Jun 30 07:44:31 PM PDT 24 |
Jun 30 08:05:44 PM PDT 24 |
11912525672 ps |
| T301 |
/workspace/coverage/default/0.chip_plic_all_irqs_20.4010092810 |
|
|
Jun 30 07:31:47 PM PDT 24 |
Jun 30 07:49:35 PM PDT 24 |
4803016004 ps |
| T525 |
/workspace/coverage/default/2.chip_sw_rv_core_ibex_nmi_irq.1694322094 |
|
|
Jun 30 07:53:10 PM PDT 24 |
Jun 30 08:06:38 PM PDT 24 |
4091640440 ps |
| T1028 |
/workspace/coverage/default/4.chip_sw_uart_tx_rx_idx3.2758212890 |
|
|
Jun 30 08:00:57 PM PDT 24 |
Jun 30 08:12:34 PM PDT 24 |
4980130430 ps |
| T1029 |
/workspace/coverage/default/0.chip_sw_kmac_mode_cshake.4126727847 |
|
|
Jun 30 07:30:03 PM PDT 24 |
Jun 30 07:34:08 PM PDT 24 |
3081752056 ps |
| T1030 |
/workspace/coverage/default/0.chip_sw_pwrmgr_all_reset_reqs.2472241295 |
|
|
Jun 30 07:28:59 PM PDT 24 |
Jun 30 07:57:17 PM PDT 24 |
10516354516 ps |
| T1031 |
/workspace/coverage/default/2.chip_sw_aes_entropy.3577763653 |
|
|
Jun 30 07:59:00 PM PDT 24 |
Jun 30 08:04:06 PM PDT 24 |
3224225496 ps |
| T1032 |
/workspace/coverage/default/0.chip_sw_aes_entropy.328924286 |
|
|
Jun 30 07:31:24 PM PDT 24 |
Jun 30 07:36:08 PM PDT 24 |
2710107844 ps |
| T742 |
/workspace/coverage/default/30.chip_sw_all_escalation_resets.2479044177 |
|
|
Jun 30 08:04:28 PM PDT 24 |
Jun 30 08:16:35 PM PDT 24 |
4814656674 ps |
| T754 |
/workspace/coverage/default/35.chip_sw_alert_handler_lpg_sleep_mode_alerts.693244415 |
|
|
Jun 30 08:07:26 PM PDT 24 |
Jun 30 08:13:57 PM PDT 24 |
3766834822 ps |
| T1033 |
/workspace/coverage/default/0.chip_sw_rstmgr_sw_req.80290425 |
|
|
Jun 30 07:28:42 PM PDT 24 |
Jun 30 07:33:49 PM PDT 24 |
2746201408 ps |
| T1034 |
/workspace/coverage/default/0.chip_sw_hmac_smoketest.3684280268 |
|
|
Jun 30 07:39:31 PM PDT 24 |
Jun 30 07:45:17 PM PDT 24 |
2735839750 ps |
| T173 |
/workspace/coverage/default/1.chip_sw_sram_ctrl_execution_main.196603904 |
|
|
Jun 30 07:46:22 PM PDT 24 |
Jun 30 08:04:53 PM PDT 24 |
7223612147 ps |
| T775 |
/workspace/coverage/default/74.chip_sw_all_escalation_resets.3932948587 |
|
|
Jun 30 08:09:04 PM PDT 24 |
Jun 30 08:19:07 PM PDT 24 |
5961074344 ps |
| T1035 |
/workspace/coverage/default/8.chip_sw_lc_ctrl_transition.1491080718 |
|
|
Jun 30 08:02:50 PM PDT 24 |
Jun 30 08:23:54 PM PDT 24 |
12590427463 ps |
| T737 |
/workspace/coverage/default/79.chip_sw_alert_handler_lpg_sleep_mode_alerts.3165213207 |
|
|
Jun 30 08:09:22 PM PDT 24 |
Jun 30 08:16:14 PM PDT 24 |
3202121868 ps |
| T1036 |
/workspace/coverage/default/2.chip_sw_example_concurrency.409546998 |
|
|
Jun 30 07:49:45 PM PDT 24 |
Jun 30 07:54:12 PM PDT 24 |
2724893400 ps |
| T23 |
/workspace/coverage/default/0.chip_sw_sleep_pin_mio_dio_val.3789747234 |
|
|
Jun 30 07:32:44 PM PDT 24 |
Jun 30 07:38:07 PM PDT 24 |
3031148339 ps |
| T160 |
/workspace/coverage/default/10.chip_sw_all_escalation_resets.1372723624 |
|
|
Jun 30 08:02:47 PM PDT 24 |
Jun 30 08:14:58 PM PDT 24 |
5491276008 ps |
| T168 |
/workspace/coverage/default/0.chip_sw_lc_ctrl_rma_to_scrap.3653870265 |
|
|
Jun 30 07:29:37 PM PDT 24 |
Jun 30 07:32:20 PM PDT 24 |
3256596356 ps |
| T279 |
/workspace/coverage/default/1.chip_sw_sram_ctrl_scrambled_access.4265676610 |
|
|
Jun 30 07:46:46 PM PDT 24 |
Jun 30 07:59:35 PM PDT 24 |
5019706040 ps |
| T15 |
/workspace/coverage/default/1.chip_sw_pwrmgr_normal_sleep_all_wake_ups.2089507449 |
|
|
Jun 30 07:47:07 PM PDT 24 |
Jun 30 07:53:19 PM PDT 24 |
6656927912 ps |
| T1037 |
/workspace/coverage/default/84.chip_sw_all_escalation_resets.871830269 |
|
|
Jun 30 08:09:55 PM PDT 24 |
Jun 30 08:22:31 PM PDT 24 |
5745284400 ps |
| T734 |
/workspace/coverage/default/91.chip_sw_all_escalation_resets.1739170188 |
|
|
Jun 30 08:11:32 PM PDT 24 |
Jun 30 08:23:12 PM PDT 24 |
5357689080 ps |
| T10 |
/workspace/coverage/default/0.chip_sw_pwrmgr_random_sleep_all_wake_ups.2191563032 |
|
|
Jun 30 07:34:06 PM PDT 24 |
Jun 30 07:56:18 PM PDT 24 |
19785749560 ps |
| T192 |
/workspace/coverage/default/0.chip_jtag_csr_rw.1070151465 |
|
|
Jun 30 07:25:47 PM PDT 24 |
Jun 30 08:10:38 PM PDT 24 |
20144325704 ps |
| T1038 |
/workspace/coverage/default/1.chip_sw_flash_ctrl_access_jitter_en_reduced_freq.97475520 |
|
|
Jun 30 07:47:49 PM PDT 24 |
Jun 30 08:08:46 PM PDT 24 |
7428022539 ps |
| T1039 |
/workspace/coverage/default/0.chip_sw_uart_tx_rx_bootstrap.450670506 |
|
|
Jun 30 07:28:14 PM PDT 24 |
Jun 30 11:17:10 PM PDT 24 |
78821420606 ps |
| T789 |
/workspace/coverage/default/40.chip_sw_alert_handler_lpg_sleep_mode_alerts.946624921 |
|
|
Jun 30 08:05:16 PM PDT 24 |
Jun 30 08:13:13 PM PDT 24 |
3860023656 ps |
| T777 |
/workspace/coverage/default/15.chip_sw_alert_handler_lpg_sleep_mode_alerts.1634079063 |
|
|
Jun 30 08:05:05 PM PDT 24 |
Jun 30 08:12:27 PM PDT 24 |
3703882330 ps |
| T63 |
/workspace/coverage/default/1.chip_sw_alert_test.1976237774 |
|
|
Jun 30 07:45:59 PM PDT 24 |
Jun 30 07:51:31 PM PDT 24 |
3361922588 ps |
| T1040 |
/workspace/coverage/default/2.chip_sw_lc_ctrl_otp_hw_cfg0.3336369447 |
|
|
Jun 30 07:53:49 PM PDT 24 |
Jun 30 07:59:12 PM PDT 24 |
3180262200 ps |
| T787 |
/workspace/coverage/default/84.chip_sw_alert_handler_lpg_sleep_mode_alerts.1176930498 |
|
|
Jun 30 08:10:22 PM PDT 24 |
Jun 30 08:16:43 PM PDT 24 |
3502937144 ps |
| T1041 |
/workspace/coverage/default/2.chip_sw_flash_ctrl_access_jitter_en_reduced_freq.1321400621 |
|
|
Jun 30 07:59:49 PM PDT 24 |
Jun 30 08:24:00 PM PDT 24 |
7550533975 ps |
| T1042 |
/workspace/coverage/default/0.chip_sw_pwrmgr_usbdev_smoketest.2429818096 |
|
|
Jun 30 07:38:52 PM PDT 24 |
Jun 30 07:48:03 PM PDT 24 |
6335706604 ps |
| T139 |
/workspace/coverage/default/0.chip_sw_sensor_ctrl_status.1371692101 |
|
|
Jun 30 07:30:40 PM PDT 24 |
Jun 30 07:35:04 PM PDT 24 |
3261607902 ps |
| T740 |
/workspace/coverage/default/62.chip_sw_alert_handler_lpg_sleep_mode_alerts.2049022503 |
|
|
Jun 30 08:07:48 PM PDT 24 |
Jun 30 08:13:34 PM PDT 24 |
3802527560 ps |