| T1185 |
/workspace/coverage/default/0.chip_sw_alert_handler_escalation.3569967954 |
|
|
Jun 30 07:29:02 PM PDT 24 |
Jun 30 07:39:08 PM PDT 24 |
5370339894 ps |
| T1186 |
/workspace/coverage/default/4.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.1806967167 |
|
|
Jun 30 08:02:58 PM PDT 24 |
Jun 30 08:22:02 PM PDT 24 |
8577298948 ps |
| T1187 |
/workspace/coverage/default/2.chip_sw_hmac_multistream.2364172349 |
|
|
Jun 30 07:56:45 PM PDT 24 |
Jun 30 08:24:18 PM PDT 24 |
7222110570 ps |
| T1188 |
/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_bad_dev.2964826532 |
|
|
Jun 30 07:41:42 PM PDT 24 |
Jun 30 08:55:13 PM PDT 24 |
15767728792 ps |
| T1189 |
/workspace/coverage/default/1.chip_sw_kmac_mode_kmac_jitter_en_reduced_freq.2178403249 |
|
|
Jun 30 07:49:08 PM PDT 24 |
Jun 30 07:53:44 PM PDT 24 |
3082299026 ps |
| T1190 |
/workspace/coverage/default/1.chip_sw_clkmgr_sleep_frequency.902703993 |
|
|
Jun 30 07:48:09 PM PDT 24 |
Jun 30 07:58:15 PM PDT 24 |
4250636656 ps |
| T1191 |
/workspace/coverage/default/1.chip_sw_alert_handler_lpg_reset_toggle.1144809942 |
|
|
Jun 30 07:45:01 PM PDT 24 |
Jun 30 08:13:19 PM PDT 24 |
7215925912 ps |
| T1192 |
/workspace/coverage/default/0.chip_sw_otp_ctrl_lc_signals_dev.1731791912 |
|
|
Jun 30 07:29:57 PM PDT 24 |
Jun 30 07:51:55 PM PDT 24 |
7016206280 ps |
| T780 |
/workspace/coverage/default/42.chip_sw_all_escalation_resets.4162705097 |
|
|
Jun 30 08:05:41 PM PDT 24 |
Jun 30 08:16:46 PM PDT 24 |
4932651526 ps |
| T1193 |
/workspace/coverage/default/0.chip_sw_rstmgr_rst_cnsty_escalation.3905545294 |
|
|
Jun 30 07:28:15 PM PDT 24 |
Jun 30 07:38:12 PM PDT 24 |
5325492224 ps |
| T222 |
/workspace/coverage/default/1.chip_sw_flash_init.1993189437 |
|
|
Jun 30 07:40:51 PM PDT 24 |
Jun 30 08:14:37 PM PDT 24 |
24915800865 ps |
| T1194 |
/workspace/coverage/default/6.chip_sw_csrng_edn_concurrency.4125634192 |
|
|
Jun 30 08:01:18 PM PDT 24 |
Jun 30 09:07:07 PM PDT 24 |
16293455556 ps |
| T744 |
/workspace/coverage/default/86.chip_sw_all_escalation_resets.1112335752 |
|
|
Jun 30 08:09:50 PM PDT 24 |
Jun 30 08:20:27 PM PDT 24 |
4671619916 ps |
| T313 |
/workspace/coverage/default/1.chip_sw_i2c_host_tx_rx_idx2.3974886647 |
|
|
Jun 30 07:40:52 PM PDT 24 |
Jun 30 07:51:41 PM PDT 24 |
4923581532 ps |
| T1195 |
/workspace/coverage/default/0.chip_sw_ast_clk_outputs.1202147958 |
|
|
Jun 30 07:33:27 PM PDT 24 |
Jun 30 07:52:53 PM PDT 24 |
7535787362 ps |
| T755 |
/workspace/coverage/default/27.chip_sw_alert_handler_lpg_sleep_mode_alerts.792884368 |
|
|
Jun 30 08:06:08 PM PDT 24 |
Jun 30 08:12:17 PM PDT 24 |
3825455880 ps |
| T797 |
/workspace/coverage/default/50.chip_sw_alert_handler_lpg_sleep_mode_alerts.2879435869 |
|
|
Jun 30 08:07:50 PM PDT 24 |
Jun 30 08:16:12 PM PDT 24 |
3952666180 ps |
| T1196 |
/workspace/coverage/default/2.chip_sw_sram_ctrl_smoketest.2189265141 |
|
|
Jun 30 08:01:20 PM PDT 24 |
Jun 30 08:04:23 PM PDT 24 |
2266523918 ps |
| T1197 |
/workspace/coverage/default/4.chip_sw_uart_tx_rx.2917181982 |
|
|
Jun 30 08:00:09 PM PDT 24 |
Jun 30 08:10:24 PM PDT 24 |
3915396476 ps |
| T387 |
/workspace/coverage/default/0.chip_sw_pwrmgr_deep_sleep_all_wake_ups.1236683746 |
|
|
Jun 30 07:34:07 PM PDT 24 |
Jun 30 08:16:07 PM PDT 24 |
25830783208 ps |
| T1198 |
/workspace/coverage/default/0.chip_sw_pwrmgr_deep_sleep_all_reset_reqs.1004453188 |
|
|
Jun 30 07:28:23 PM PDT 24 |
Jun 30 07:54:22 PM PDT 24 |
13368117933 ps |
| T47 |
/workspace/coverage/default/2.chip_sw_spi_host_tx_rx.3819279971 |
|
|
Jun 30 07:49:59 PM PDT 24 |
Jun 30 07:55:16 PM PDT 24 |
2446283580 ps |
| T782 |
/workspace/coverage/default/42.chip_sw_alert_handler_lpg_sleep_mode_alerts.2452423994 |
|
|
Jun 30 08:05:33 PM PDT 24 |
Jun 30 08:12:08 PM PDT 24 |
4110964730 ps |
| T1199 |
/workspace/coverage/default/0.chip_sw_csrng_kat_test.4289935377 |
|
|
Jun 30 07:28:25 PM PDT 24 |
Jun 30 07:33:22 PM PDT 24 |
3269768088 ps |
| T1200 |
/workspace/coverage/default/0.chip_sw_csrng_lc_hw_debug_en_test.2153394908 |
|
|
Jun 30 07:30:37 PM PDT 24 |
Jun 30 07:41:02 PM PDT 24 |
5563409384 ps |
| T1201 |
/workspace/coverage/default/2.chip_sw_otp_ctrl_lc_signals_test_unlocked0.3409979752 |
|
|
Jun 30 07:51:57 PM PDT 24 |
Jun 30 08:04:31 PM PDT 24 |
5082481420 ps |
| T305 |
/workspace/coverage/default/2.chip_sw_rstmgr_alert_info.1034922345 |
|
|
Jun 30 07:52:31 PM PDT 24 |
Jun 30 08:28:25 PM PDT 24 |
16612941364 ps |
| T1202 |
/workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0.570655545 |
|
|
Jun 30 07:56:17 PM PDT 24 |
Jun 30 08:10:18 PM PDT 24 |
3901693562 ps |
| T1203 |
/workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_slow_dev.1811115149 |
|
|
Jun 30 07:58:07 PM PDT 24 |
Jun 30 08:09:24 PM PDT 24 |
4093337318 ps |
| T1204 |
/workspace/coverage/default/2.rom_e2e_keymgr_init_rom_ext_meas.899086897 |
|
|
Jun 30 08:04:46 PM PDT 24 |
Jun 30 09:11:59 PM PDT 24 |
14850867564 ps |
| T1205 |
/workspace/coverage/default/0.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted.3323682120 |
|
|
Jun 30 07:34:09 PM PDT 24 |
Jun 30 07:42:32 PM PDT 24 |
4578669284 ps |
| T427 |
/workspace/coverage/default/74.chip_sw_alert_handler_lpg_sleep_mode_alerts.980502574 |
|
|
Jun 30 08:08:50 PM PDT 24 |
Jun 30 08:16:09 PM PDT 24 |
3362202920 ps |
| T1206 |
/workspace/coverage/default/1.chip_sw_clkmgr_off_otbn_trans.2135593476 |
|
|
Jun 30 07:46:26 PM PDT 24 |
Jun 30 07:53:49 PM PDT 24 |
3997579294 ps |
| T785 |
/workspace/coverage/default/82.chip_sw_alert_handler_lpg_sleep_mode_alerts.2975425534 |
|
|
Jun 30 08:10:10 PM PDT 24 |
Jun 30 08:16:33 PM PDT 24 |
3106575656 ps |
| T1207 |
/workspace/coverage/default/6.chip_sw_uart_rand_baudrate.2805100152 |
|
|
Jun 30 08:02:58 PM PDT 24 |
Jun 30 08:33:50 PM PDT 24 |
8184984224 ps |
| T1208 |
/workspace/coverage/default/2.chip_sw_csrng_lc_hw_debug_en_test.1723262565 |
|
|
Jun 30 07:56:38 PM PDT 24 |
Jun 30 08:09:07 PM PDT 24 |
6453265000 ps |
| T1209 |
/workspace/coverage/default/1.chip_sw_aes_entropy.1050230520 |
|
|
Jun 30 07:44:30 PM PDT 24 |
Jun 30 07:49:56 PM PDT 24 |
3224194648 ps |
| T50 |
/workspace/coverage/default/0.chip_sw_sysrst_ctrl_ulp_z3_wakeup.1773152650 |
|
|
Jun 30 07:29:02 PM PDT 24 |
Jun 30 07:37:51 PM PDT 24 |
6379418380 ps |
| T74 |
/workspace/coverage/default/0.chip_sw_usbdev_aon_pullup.3104657027 |
|
|
Jun 30 07:27:22 PM PDT 24 |
Jun 30 07:34:44 PM PDT 24 |
3297512824 ps |
| T1210 |
/workspace/coverage/default/3.chip_sw_uart_tx_rx.2700897803 |
|
|
Jun 30 07:59:19 PM PDT 24 |
Jun 30 08:10:53 PM PDT 24 |
4412985508 ps |
| T1211 |
/workspace/coverage/default/1.chip_sw_alert_handler_escalation.1780348727 |
|
|
Jun 30 07:44:03 PM PDT 24 |
Jun 30 07:52:39 PM PDT 24 |
5893362494 ps |
| T1212 |
/workspace/coverage/default/1.chip_sw_kmac_app_rom.2943033008 |
|
|
Jun 30 07:46:03 PM PDT 24 |
Jun 30 07:51:08 PM PDT 24 |
3522159230 ps |
| T1213 |
/workspace/coverage/default/0.chip_sw_sram_ctrl_smoketest.2241965616 |
|
|
Jun 30 07:39:57 PM PDT 24 |
Jun 30 07:43:35 PM PDT 24 |
3278302440 ps |
| T1214 |
/workspace/coverage/default/2.chip_sw_pwrmgr_sleep_power_glitch_reset.1335422564 |
|
|
Jun 30 07:52:33 PM PDT 24 |
Jun 30 08:02:40 PM PDT 24 |
4308192920 ps |
| T1215 |
/workspace/coverage/default/4.chip_sw_uart_rand_baudrate.192937109 |
|
|
Jun 30 08:01:46 PM PDT 24 |
Jun 30 08:27:17 PM PDT 24 |
8052318552 ps |
| T334 |
/workspace/coverage/default/0.chip_sw_pattgen_ios.1210914689 |
|
|
Jun 30 07:28:43 PM PDT 24 |
Jun 30 07:32:29 PM PDT 24 |
3296794400 ps |
| T1216 |
/workspace/coverage/default/3.chip_sw_uart_tx_rx_idx1.2327197607 |
|
|
Jun 30 08:00:52 PM PDT 24 |
Jun 30 08:13:43 PM PDT 24 |
4302474400 ps |
| T1217 |
/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_good_prod.3893934945 |
|
|
Jun 30 07:41:01 PM PDT 24 |
Jun 30 09:01:43 PM PDT 24 |
15697970634 ps |
| T1218 |
/workspace/coverage/default/1.chip_sw_uart_tx_rx_idx3.1755993566 |
|
|
Jun 30 07:40:45 PM PDT 24 |
Jun 30 07:50:37 PM PDT 24 |
4494836482 ps |
| T1219 |
/workspace/coverage/default/2.chip_sw_kmac_mode_cshake.4263558247 |
|
|
Jun 30 07:55:37 PM PDT 24 |
Jun 30 07:59:40 PM PDT 24 |
2942376000 ps |
| T351 |
/workspace/coverage/default/2.chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up.1298514005 |
|
|
Jun 30 07:58:14 PM PDT 24 |
Jun 30 08:07:10 PM PDT 24 |
6373427336 ps |
| T1220 |
/workspace/coverage/default/1.chip_sw_aes_smoketest.445737522 |
|
|
Jun 30 07:48:32 PM PDT 24 |
Jun 30 07:53:52 PM PDT 24 |
3228367628 ps |
| T1221 |
/workspace/coverage/default/0.chip_sw_example_manufacturer.3510803998 |
|
|
Jun 30 07:29:29 PM PDT 24 |
Jun 30 07:35:02 PM PDT 24 |
2749576992 ps |
| T202 |
/workspace/coverage/default/0.chip_sw_sysrst_ctrl_outputs.2456656481 |
|
|
Jun 30 07:28:46 PM PDT 24 |
Jun 30 07:34:29 PM PDT 24 |
3731044476 ps |
| T1222 |
/workspace/coverage/default/0.chip_sival_flash_info_access.949879133 |
|
|
Jun 30 07:28:31 PM PDT 24 |
Jun 30 07:33:23 PM PDT 24 |
3251352740 ps |
| T1223 |
/workspace/coverage/default/0.chip_sw_sleep_sram_ret_contents_no_scramble.203778794 |
|
|
Jun 30 07:33:43 PM PDT 24 |
Jun 30 07:46:20 PM PDT 24 |
7306983824 ps |
| T1224 |
/workspace/coverage/default/0.chip_sw_rv_plic_smoketest.295007611 |
|
|
Jun 30 07:41:30 PM PDT 24 |
Jun 30 07:46:16 PM PDT 24 |
3628620360 ps |
| T1225 |
/workspace/coverage/default/1.chip_sw_sleep_sram_ret_contents_scramble.3672894458 |
|
|
Jun 30 07:45:29 PM PDT 24 |
Jun 30 08:01:44 PM PDT 24 |
8379430388 ps |
| T699 |
/workspace/coverage/default/48.chip_sw_alert_handler_lpg_sleep_mode_alerts.639616173 |
|
|
Jun 30 08:06:22 PM PDT 24 |
Jun 30 08:13:05 PM PDT 24 |
3343487482 ps |
| T1226 |
/workspace/coverage/default/1.chip_sw_pwrmgr_normal_sleep_por_reset.1583122567 |
|
|
Jun 30 07:43:11 PM PDT 24 |
Jun 30 07:52:38 PM PDT 24 |
5703807620 ps |
| T701 |
/workspace/coverage/default/4.chip_sw_all_escalation_resets.1435325983 |
|
|
Jun 30 08:02:57 PM PDT 24 |
Jun 30 08:13:03 PM PDT 24 |
4465435500 ps |
| T778 |
/workspace/coverage/default/37.chip_sw_alert_handler_lpg_sleep_mode_alerts.2826712235 |
|
|
Jun 30 08:05:11 PM PDT 24 |
Jun 30 08:12:13 PM PDT 24 |
3345916516 ps |
| T1227 |
/workspace/coverage/default/1.chip_sw_rv_timer_smoketest.768447714 |
|
|
Jun 30 07:49:02 PM PDT 24 |
Jun 30 07:53:22 PM PDT 24 |
3097874080 ps |
| T1228 |
/workspace/coverage/default/1.chip_sw_pwrmgr_smoketest.1084683571 |
|
|
Jun 30 07:48:51 PM PDT 24 |
Jun 30 07:56:26 PM PDT 24 |
5697363398 ps |
| T1229 |
/workspace/coverage/default/2.chip_sw_lc_ctrl_volatile_raw_unlock.16765716 |
|
|
Jun 30 07:51:51 PM PDT 24 |
Jun 30 07:53:38 PM PDT 24 |
2345678513 ps |
| T1230 |
/workspace/coverage/default/0.chip_sw_entropy_src_smoketest.2553654955 |
|
|
Jun 30 07:38:59 PM PDT 24 |
Jun 30 07:47:34 PM PDT 24 |
4005921480 ps |
| T1231 |
/workspace/coverage/default/1.chip_sw_kmac_mode_kmac_jitter_en.1259859883 |
|
|
Jun 30 07:45:55 PM PDT 24 |
Jun 30 07:50:46 PM PDT 24 |
2979758045 ps |
| T1232 |
/workspace/coverage/default/0.chip_sw_pwrmgr_normal_sleep_por_reset.981174941 |
|
|
Jun 30 07:31:02 PM PDT 24 |
Jun 30 07:41:49 PM PDT 24 |
7116461972 ps |
| T1233 |
/workspace/coverage/default/1.chip_sw_alert_handler_entropy.2552886306 |
|
|
Jun 30 07:44:30 PM PDT 24 |
Jun 30 07:50:59 PM PDT 24 |
2973131615 ps |
| T226 |
/workspace/coverage/default/0.chip_sw_flash_init_reduced_freq.2299601093 |
|
|
Jun 30 07:34:43 PM PDT 24 |
Jun 30 08:09:14 PM PDT 24 |
26026902077 ps |
| T362 |
/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_bad_b_good_dev.868010568 |
|
|
Jun 30 07:40:48 PM PDT 24 |
Jun 30 09:18:17 PM PDT 24 |
24574675046 ps |
| T41 |
/workspace/coverage/default/0.chip_sw_gpio.1151001688 |
|
|
Jun 30 07:29:29 PM PDT 24 |
Jun 30 07:38:03 PM PDT 24 |
4514152188 ps |
| T1234 |
/workspace/coverage/default/2.chip_sw_example_manufacturer.2564080179 |
|
|
Jun 30 07:51:30 PM PDT 24 |
Jun 30 07:55:26 PM PDT 24 |
2119430836 ps |
| T1235 |
/workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_slow_rma.985943439 |
|
|
Jun 30 07:47:59 PM PDT 24 |
Jun 30 08:01:57 PM PDT 24 |
4604913024 ps |
| T1236 |
/workspace/coverage/default/1.chip_sw_csrng_kat_test.2409245051 |
|
|
Jun 30 07:45:17 PM PDT 24 |
Jun 30 07:49:32 PM PDT 24 |
2862444042 ps |
| T253 |
/workspace/coverage/default/38.chip_sw_all_escalation_resets.418685872 |
|
|
Jun 30 08:05:32 PM PDT 24 |
Jun 30 08:15:22 PM PDT 24 |
5309176516 ps |
| T795 |
/workspace/coverage/default/39.chip_sw_alert_handler_lpg_sleep_mode_alerts.1977055330 |
|
|
Jun 30 08:05:30 PM PDT 24 |
Jun 30 08:13:04 PM PDT 24 |
3601017266 ps |
| T1237 |
/workspace/coverage/default/47.chip_sw_alert_handler_lpg_sleep_mode_alerts.2882936653 |
|
|
Jun 30 08:06:29 PM PDT 24 |
Jun 30 08:13:36 PM PDT 24 |
4135806672 ps |
| T1238 |
/workspace/coverage/default/1.chip_sw_otp_ctrl_lc_signals_rma.3019712376 |
|
|
Jun 30 07:42:31 PM PDT 24 |
Jun 30 08:04:13 PM PDT 24 |
8058757400 ps |
| T1239 |
/workspace/coverage/default/73.chip_sw_all_escalation_resets.884056478 |
|
|
Jun 30 08:08:54 PM PDT 24 |
Jun 30 08:19:11 PM PDT 24 |
5999214002 ps |
| T1240 |
/workspace/coverage/default/0.rom_e2e_asm_init_prod_end.4171644235 |
|
|
Jun 30 07:42:51 PM PDT 24 |
Jun 30 09:00:53 PM PDT 24 |
16055207583 ps |
| T1241 |
/workspace/coverage/default/1.chip_sw_flash_ctrl_write_clear.933341638 |
|
|
Jun 30 07:47:09 PM PDT 24 |
Jun 30 07:55:32 PM PDT 24 |
3822614800 ps |
| T1242 |
/workspace/coverage/default/2.chip_sw_hmac_oneshot.1331080520 |
|
|
Jun 30 07:57:04 PM PDT 24 |
Jun 30 08:04:11 PM PDT 24 |
3049696138 ps |
| T25 |
/workspace/coverage/default/1.chip_sw_sleep_pin_mio_dio_val.3446945893 |
|
|
Jun 30 07:39:39 PM PDT 24 |
Jun 30 07:44:20 PM PDT 24 |
3188367195 ps |
| T1243 |
/workspace/coverage/default/2.chip_sw_kmac_app_rom.2693923577 |
|
|
Jun 30 07:56:44 PM PDT 24 |
Jun 30 08:01:22 PM PDT 24 |
3250184968 ps |
| T1244 |
/workspace/coverage/default/1.rom_e2e_asm_init_prod_end.1339384409 |
|
|
Jun 30 07:53:30 PM PDT 24 |
Jun 30 09:00:08 PM PDT 24 |
16021142760 ps |
| T1245 |
/workspace/coverage/default/2.chip_sw_pwrmgr_random_sleep_all_reset_reqs.368500115 |
|
|
Jun 30 07:53:45 PM PDT 24 |
Jun 30 08:38:46 PM PDT 24 |
28089451156 ps |
| T1246 |
/workspace/coverage/default/59.chip_sw_alert_handler_lpg_sleep_mode_alerts.2882626556 |
|
|
Jun 30 08:07:57 PM PDT 24 |
Jun 30 08:14:52 PM PDT 24 |
3677989720 ps |
| T1247 |
/workspace/coverage/default/1.chip_sw_clkmgr_off_kmac_trans.295222132 |
|
|
Jun 30 07:45:45 PM PDT 24 |
Jun 30 07:54:15 PM PDT 24 |
5516460398 ps |
| T1248 |
/workspace/coverage/default/1.chip_sw_edn_entropy_reqs_jitter.2669124588 |
|
|
Jun 30 07:45:25 PM PDT 24 |
Jun 30 08:10:12 PM PDT 24 |
7029828006 ps |
| T300 |
/workspace/coverage/default/2.chip_plic_all_irqs_0.949393141 |
|
|
Jun 30 07:57:47 PM PDT 24 |
Jun 30 08:20:23 PM PDT 24 |
6252931040 ps |
| T1249 |
/workspace/coverage/default/0.chip_sw_aon_timer_sleep_wdog_sleep_pause.2388966665 |
|
|
Jun 30 07:28:28 PM PDT 24 |
Jun 30 07:33:29 PM PDT 24 |
6683341580 ps |
| T175 |
/workspace/coverage/default/1.chip_sw_flash_rma_unlocked.453523797 |
|
|
Jun 30 07:41:08 PM PDT 24 |
Jun 30 09:09:50 PM PDT 24 |
44414353332 ps |
| T1250 |
/workspace/coverage/default/11.chip_sw_alert_handler_lpg_sleep_mode_alerts.3198760259 |
|
|
Jun 30 08:01:42 PM PDT 24 |
Jun 30 08:09:35 PM PDT 24 |
4016814340 ps |
| T137 |
/workspace/coverage/default/4.chip_sw_sensor_ctrl_alert.2780150360 |
|
|
Jun 30 08:02:21 PM PDT 24 |
Jun 30 08:13:28 PM PDT 24 |
4643277832 ps |
| T388 |
/workspace/coverage/default/1.chip_sw_pwrmgr_deep_sleep_all_wake_ups.2549249953 |
|
|
Jun 30 07:47:58 PM PDT 24 |
Jun 30 08:23:15 PM PDT 24 |
26836048350 ps |
| T1251 |
/workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_fast_rma.3811046320 |
|
|
Jun 30 07:56:44 PM PDT 24 |
Jun 30 08:06:09 PM PDT 24 |
3988093572 ps |
| T223 |
/workspace/coverage/default/0.chip_sw_lc_walkthrough_rma.4868362 |
|
|
Jun 30 07:29:15 PM PDT 24 |
Jun 30 09:10:06 PM PDT 24 |
47312656700 ps |
| T321 |
/workspace/coverage/default/2.chip_sw_pwrmgr_lowpower_cancel.747234782 |
|
|
Jun 30 07:58:44 PM PDT 24 |
Jun 30 08:07:24 PM PDT 24 |
4270259400 ps |
| T1252 |
/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_bad_b_good_rma.3341796948 |
|
|
Jun 30 07:42:09 PM PDT 24 |
Jun 30 09:22:35 PM PDT 24 |
23252042900 ps |
| T1253 |
/workspace/coverage/default/1.chip_sw_clkmgr_off_aes_trans.3662923798 |
|
|
Jun 30 07:47:50 PM PDT 24 |
Jun 30 07:58:12 PM PDT 24 |
5127340712 ps |
| T1254 |
/workspace/coverage/default/1.chip_sw_rstmgr_smoketest.1733573364 |
|
|
Jun 30 07:48:29 PM PDT 24 |
Jun 30 07:51:47 PM PDT 24 |
2702438046 ps |
| T1255 |
/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_good_prod_end.1979893768 |
|
|
Jun 30 07:39:29 PM PDT 24 |
Jun 30 08:55:49 PM PDT 24 |
15126425100 ps |
| T1256 |
/workspace/coverage/default/1.chip_sw_sleep_pwm_pulses.2018794109 |
|
|
Jun 30 07:40:56 PM PDT 24 |
Jun 30 08:05:25 PM PDT 24 |
9837481998 ps |
| T189 |
/workspace/coverage/default/2.chip_sw_spi_device_pass_through_collision.1937068078 |
|
|
Jun 30 07:50:30 PM PDT 24 |
Jun 30 08:03:51 PM PDT 24 |
4816386509 ps |
| T1257 |
/workspace/coverage/default/2.chip_sw_clkmgr_smoketest.3652738440 |
|
|
Jun 30 08:00:08 PM PDT 24 |
Jun 30 08:03:22 PM PDT 24 |
3344914780 ps |
| T1258 |
/workspace/coverage/default/15.chip_sw_uart_rand_baudrate.1437388547 |
|
|
Jun 30 08:02:02 PM PDT 24 |
Jun 30 08:31:57 PM PDT 24 |
8919602520 ps |
| T1259 |
/workspace/coverage/default/1.chip_sw_otp_ctrl_ecc_error_vendor_test.2301050976 |
|
|
Jun 30 07:41:59 PM PDT 24 |
Jun 30 07:46:34 PM PDT 24 |
2938887471 ps |
| T1260 |
/workspace/coverage/default/2.chip_sw_clkmgr_reset_frequency.2664837526 |
|
|
Jun 30 07:56:33 PM PDT 24 |
Jun 30 08:04:28 PM PDT 24 |
3345900296 ps |
| T1261 |
/workspace/coverage/default/1.rom_e2e_keymgr_init_rom_ext_no_meas.1867241126 |
|
|
Jun 30 07:52:21 PM PDT 24 |
Jun 30 09:19:44 PM PDT 24 |
14636463224 ps |
| T1262 |
/workspace/coverage/default/3.chip_tap_straps_prod.1656295126 |
|
|
Jun 30 07:59:30 PM PDT 24 |
Jun 30 08:02:44 PM PDT 24 |
2780983167 ps |
| T772 |
/workspace/coverage/default/21.chip_sw_all_escalation_resets.717811091 |
|
|
Jun 30 08:03:53 PM PDT 24 |
Jun 30 08:13:23 PM PDT 24 |
5414189320 ps |
| T694 |
/workspace/coverage/default/85.chip_sw_alert_handler_lpg_sleep_mode_alerts.3321427097 |
|
|
Jun 30 08:09:54 PM PDT 24 |
Jun 30 08:17:37 PM PDT 24 |
4036799470 ps |
| T1263 |
/workspace/coverage/default/1.chip_sw_rstmgr_rst_cnsty_escalation.3973674748 |
|
|
Jun 30 07:40:43 PM PDT 24 |
Jun 30 07:49:59 PM PDT 24 |
5396077876 ps |
| T1264 |
/workspace/coverage/default/2.chip_tap_straps_rma.2267533085 |
|
|
Jun 30 07:58:14 PM PDT 24 |
Jun 30 08:05:39 PM PDT 24 |
4836082103 ps |
| T741 |
/workspace/coverage/default/21.chip_sw_alert_handler_lpg_sleep_mode_alerts.1966623700 |
|
|
Jun 30 08:04:03 PM PDT 24 |
Jun 30 08:12:45 PM PDT 24 |
4226497450 ps |
| T1265 |
/workspace/coverage/default/1.chip_sw_aon_timer_smoketest.1624741138 |
|
|
Jun 30 07:49:14 PM PDT 24 |
Jun 30 07:54:00 PM PDT 24 |
2884827960 ps |
| T356 |
/workspace/coverage/default/1.chip_sw_i2c_host_tx_rx_idx1.2829459026 |
|
|
Jun 30 07:41:06 PM PDT 24 |
Jun 30 07:52:47 PM PDT 24 |
5397919144 ps |
| T1266 |
/workspace/coverage/default/2.chip_sw_flash_init.3106558342 |
|
|
Jun 30 07:49:38 PM PDT 24 |
Jun 30 08:24:40 PM PDT 24 |
21818943396 ps |
| T1267 |
/workspace/coverage/default/0.chip_sw_clkmgr_off_aes_trans.3792970174 |
|
|
Jun 30 07:35:10 PM PDT 24 |
Jun 30 07:43:14 PM PDT 24 |
4266518616 ps |
| T1268 |
/workspace/coverage/default/0.chip_sw_hmac_oneshot.2232860538 |
|
|
Jun 30 07:30:17 PM PDT 24 |
Jun 30 07:36:03 PM PDT 24 |
2585573992 ps |
| T1269 |
/workspace/coverage/default/2.chip_sw_pwrmgr_normal_sleep_all_reset_reqs.322511676 |
|
|
Jun 30 07:52:15 PM PDT 24 |
Jun 30 08:10:12 PM PDT 24 |
12269501951 ps |
| T127 |
/workspace/coverage/default/0.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup.1678041662 |
|
|
Jun 30 07:31:40 PM PDT 24 |
Jun 30 07:39:37 PM PDT 24 |
5453116808 ps |
| T1270 |
/workspace/coverage/default/2.chip_sw_uart_tx_rx_alt_clk_freq.4283243825 |
|
|
Jun 30 07:50:28 PM PDT 24 |
Jun 30 08:04:43 PM PDT 24 |
3999420859 ps |
| T1271 |
/workspace/coverage/default/0.chip_sw_otbn_ecdsa_op_irq.614211516 |
|
|
Jun 30 07:28:28 PM PDT 24 |
Jun 30 08:35:40 PM PDT 24 |
16814645080 ps |
| T1272 |
/workspace/coverage/default/0.chip_sw_sleep_sram_ret_contents_scramble.2489117125 |
|
|
Jun 30 07:30:49 PM PDT 24 |
Jun 30 07:45:02 PM PDT 24 |
7511560428 ps |
| T758 |
/workspace/coverage/default/16.chip_sw_alert_handler_lpg_sleep_mode_alerts.3334428684 |
|
|
Jun 30 08:03:10 PM PDT 24 |
Jun 30 08:10:18 PM PDT 24 |
3562289744 ps |
| T1273 |
/workspace/coverage/default/2.chip_sw_csrng_kat_test.4191214981 |
|
|
Jun 30 07:54:35 PM PDT 24 |
Jun 30 07:59:07 PM PDT 24 |
2826618704 ps |
| T1274 |
/workspace/coverage/default/4.chip_sw_data_integrity_escalation.2579604007 |
|
|
Jun 30 07:59:40 PM PDT 24 |
Jun 30 08:13:16 PM PDT 24 |
5830627604 ps |
| T1275 |
/workspace/coverage/default/2.chip_sw_otbn_ecdsa_op_irq_jitter_en.1436646961 |
|
|
Jun 30 07:57:22 PM PDT 24 |
Jun 30 08:55:34 PM PDT 24 |
18476972484 ps |
| T1276 |
/workspace/coverage/default/2.chip_sw_alert_handler_ping_ok.78208899 |
|
|
Jun 30 07:54:38 PM PDT 24 |
Jun 30 08:16:29 PM PDT 24 |
7675878882 ps |
| T1277 |
/workspace/coverage/default/0.chip_sw_keymgr_key_derivation.2531141 |
|
|
Jun 30 07:29:02 PM PDT 24 |
Jun 30 07:56:47 PM PDT 24 |
9197577052 ps |
| T1278 |
/workspace/coverage/default/1.chip_sw_kmac_smoketest.2149689949 |
|
|
Jun 30 07:48:43 PM PDT 24 |
Jun 30 07:53:33 PM PDT 24 |
2490789024 ps |
| T1279 |
/workspace/coverage/default/2.chip_sw_keymgr_key_derivation_prod.3962779296 |
|
|
Jun 30 07:55:49 PM PDT 24 |
Jun 30 08:33:00 PM PDT 24 |
10415179098 ps |
| T1280 |
/workspace/coverage/default/1.chip_sw_alert_handler_ping_timeout.1837001216 |
|
|
Jun 30 07:44:54 PM PDT 24 |
Jun 30 07:51:37 PM PDT 24 |
4009631544 ps |
| T1281 |
/workspace/coverage/default/0.chip_sw_sysrst_ctrl_inputs.3356678000 |
|
|
Jun 30 07:30:42 PM PDT 24 |
Jun 30 07:36:16 PM PDT 24 |
2895125227 ps |
| T1282 |
/workspace/coverage/default/2.chip_sw_hmac_enc_jitter_en.4145611847 |
|
|
Jun 30 07:55:35 PM PDT 24 |
Jun 30 07:59:05 PM PDT 24 |
2892063284 ps |
| T749 |
/workspace/coverage/default/87.chip_sw_alert_handler_lpg_sleep_mode_alerts.574074733 |
|
|
Jun 30 08:10:34 PM PDT 24 |
Jun 30 08:17:30 PM PDT 24 |
3729605272 ps |
| T37 |
/workspace/coverage/default/0.chip_sw_usbdev_dpi.4010563014 |
|
|
Jun 30 07:27:21 PM PDT 24 |
Jun 30 08:25:04 PM PDT 24 |
12017384120 ps |
| T1283 |
/workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_fast_rma.3793761582 |
|
|
Jun 30 07:46:33 PM PDT 24 |
Jun 30 07:57:01 PM PDT 24 |
4617313960 ps |
| T1284 |
/workspace/coverage/default/2.chip_sw_pwrmgr_deep_sleep_power_glitch_reset.2479890288 |
|
|
Jun 30 07:53:34 PM PDT 24 |
Jun 30 08:00:37 PM PDT 24 |
7325113608 ps |
| T1285 |
/workspace/coverage/default/2.chip_sw_power_sleep_load.705634314 |
|
|
Jun 30 08:00:26 PM PDT 24 |
Jun 30 08:14:19 PM PDT 24 |
10687630320 ps |
| T1286 |
/workspace/coverage/default/2.chip_tap_straps_prod.416145496 |
|
|
Jun 30 07:57:18 PM PDT 24 |
Jun 30 08:09:02 PM PDT 24 |
6387410866 ps |
| T92 |
/workspace/coverage/default/92.chip_sw_all_escalation_resets.2706944541 |
|
|
Jun 30 08:10:15 PM PDT 24 |
Jun 30 08:18:44 PM PDT 24 |
5874597268 ps |
| T1287 |
/workspace/coverage/default/1.chip_sw_uart_rand_baudrate.4233527861 |
|
|
Jun 30 07:42:35 PM PDT 24 |
Jun 30 07:51:30 PM PDT 24 |
4397876576 ps |
| T692 |
/workspace/coverage/default/96.chip_sw_all_escalation_resets.2419608156 |
|
|
Jun 30 08:10:55 PM PDT 24 |
Jun 30 08:23:26 PM PDT 24 |
4386119178 ps |
| T302 |
/workspace/coverage/default/1.chip_plic_all_irqs_20.1142344153 |
|
|
Jun 30 07:46:39 PM PDT 24 |
Jun 30 07:59:02 PM PDT 24 |
4338043504 ps |
| T1288 |
/workspace/coverage/default/0.chip_sw_aon_timer_wdog_lc_escalate.621477205 |
|
|
Jun 30 07:28:32 PM PDT 24 |
Jun 30 07:39:13 PM PDT 24 |
5095466728 ps |
| T152 |
/workspace/coverage/default/2.chip_plic_all_irqs_10.2275048608 |
|
|
Jun 30 07:56:11 PM PDT 24 |
Jun 30 08:06:53 PM PDT 24 |
4760440954 ps |
| T1289 |
/workspace/coverage/default/0.chip_sw_aes_idle.593466498 |
|
|
Jun 30 07:28:23 PM PDT 24 |
Jun 30 07:33:12 PM PDT 24 |
2666579524 ps |
| T254 |
/workspace/coverage/default/0.chip_sw_rstmgr_cpu_info.146623464 |
|
|
Jun 30 07:29:33 PM PDT 24 |
Jun 30 07:40:02 PM PDT 24 |
4560493320 ps |
| T1290 |
/workspace/coverage/default/2.chip_sival_flash_info_access.2024488965 |
|
|
Jun 30 07:50:06 PM PDT 24 |
Jun 30 07:56:35 PM PDT 24 |
3360205306 ps |
| T1291 |
/workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_fast_dev.1521109792 |
|
|
Jun 30 07:57:01 PM PDT 24 |
Jun 30 08:08:11 PM PDT 24 |
4562164784 ps |
| T1292 |
/workspace/coverage/default/0.chip_sw_power_sleep_load.147090220 |
|
|
Jun 30 07:34:41 PM PDT 24 |
Jun 30 07:45:20 PM PDT 24 |
10261052696 ps |
| T1293 |
/workspace/coverage/default/1.chip_sw_uart_tx_rx_alt_clk_freq.2453521565 |
|
|
Jun 30 07:41:23 PM PDT 24 |
Jun 30 08:10:11 PM PDT 24 |
8527534337 ps |
| T1294 |
/workspace/coverage/default/2.chip_sw_pwrmgr_all_reset_reqs.1060020943 |
|
|
Jun 30 07:52:32 PM PDT 24 |
Jun 30 08:18:49 PM PDT 24 |
10318394348 ps |
| T364 |
/workspace/coverage/default/0.chip_sw_rv_core_ibex_lockstep_glitch.3252439331 |
|
|
Jun 30 07:34:53 PM PDT 24 |
Jun 30 07:37:46 PM PDT 24 |
3287281680 ps |
| T190 |
/workspace/coverage/default/1.chip_sw_spi_device_pass_through.1755092385 |
|
|
Jun 30 07:41:24 PM PDT 24 |
Jun 30 08:00:48 PM PDT 24 |
7546497121 ps |
| T793 |
/workspace/coverage/default/9.chip_sw_alert_handler_lpg_sleep_mode_alerts.283578546 |
|
|
Jun 30 08:04:32 PM PDT 24 |
Jun 30 08:13:44 PM PDT 24 |
4329173284 ps |
| T1295 |
/workspace/coverage/default/10.chip_sw_uart_rand_baudrate.2459624075 |
|
|
Jun 30 08:03:04 PM PDT 24 |
Jun 30 08:36:24 PM PDT 24 |
8419363188 ps |
| T318 |
/workspace/coverage/default/2.chip_sw_i2c_device_tx_rx.335485557 |
|
|
Jun 30 07:50:43 PM PDT 24 |
Jun 30 07:57:49 PM PDT 24 |
3489162344 ps |
| T721 |
/workspace/coverage/default/55.chip_sw_all_escalation_resets.3799658231 |
|
|
Jun 30 08:07:18 PM PDT 24 |
Jun 30 08:17:43 PM PDT 24 |
5637327688 ps |
| T1296 |
/workspace/coverage/default/0.chip_sw_uart_tx_rx_idx3.1518877601 |
|
|
Jun 30 07:31:21 PM PDT 24 |
Jun 30 07:40:45 PM PDT 24 |
3725829280 ps |
| T695 |
/workspace/coverage/default/63.chip_sw_all_escalation_resets.1164008498 |
|
|
Jun 30 08:07:24 PM PDT 24 |
Jun 30 08:18:57 PM PDT 24 |
5044386400 ps |
| T1297 |
/workspace/coverage/default/1.chip_sw_pwrmgr_sleep_disabled.2898288023 |
|
|
Jun 30 07:42:03 PM PDT 24 |
Jun 30 07:46:46 PM PDT 24 |
3035752728 ps |
| T770 |
/workspace/coverage/default/32.chip_sw_alert_handler_lpg_sleep_mode_alerts.1938082883 |
|
|
Jun 30 08:05:28 PM PDT 24 |
Jun 30 08:11:37 PM PDT 24 |
3638683552 ps |
| T128 |
/workspace/coverage/default/2.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup.2782521957 |
|
|
Jun 30 07:57:53 PM PDT 24 |
Jun 30 08:06:05 PM PDT 24 |
5822770192 ps |
| T1298 |
/workspace/coverage/default/1.chip_sw_aon_timer_wdog_bite_reset.1630552700 |
|
|
Jun 30 07:43:48 PM PDT 24 |
Jun 30 07:55:09 PM PDT 24 |
7297954736 ps |
| T1299 |
/workspace/coverage/default/0.chip_sw_clkmgr_reset_frequency.3024212778 |
|
|
Jun 30 07:32:03 PM PDT 24 |
Jun 30 07:39:05 PM PDT 24 |
4071564376 ps |
| T53 |
/workspace/coverage/default/2.chip_sw_spi_device_tpm.1441847535 |
|
|
Jun 30 07:51:06 PM PDT 24 |
Jun 30 07:57:17 PM PDT 24 |
3050074918 ps |
| T1300 |
/workspace/coverage/default/0.chip_sw_flash_ctrl_access_jitter_en.115461192 |
|
|
Jun 30 07:28:03 PM PDT 24 |
Jun 30 07:47:31 PM PDT 24 |
5374567787 ps |
| T1301 |
/workspace/coverage/default/1.chip_sw_otbn_randomness.1117776828 |
|
|
Jun 30 07:44:23 PM PDT 24 |
Jun 30 08:00:49 PM PDT 24 |
6112207272 ps |
| T1302 |
/workspace/coverage/default/2.chip_sw_keymgr_key_derivation_jitter_en.762382329 |
|
|
Jun 30 07:55:37 PM PDT 24 |
Jun 30 08:24:38 PM PDT 24 |
8803616383 ps |
| T319 |
/workspace/coverage/default/1.chip_sw_pwrmgr_lowpower_cancel.454408293 |
|
|
Jun 30 07:46:23 PM PDT 24 |
Jun 30 07:52:46 PM PDT 24 |
3510151044 ps |
| T1303 |
/workspace/coverage/default/36.chip_sw_alert_handler_lpg_sleep_mode_alerts.2322792954 |
|
|
Jun 30 08:04:16 PM PDT 24 |
Jun 30 08:10:41 PM PDT 24 |
4048840050 ps |
| T1304 |
/workspace/coverage/default/0.chip_sw_flash_init.1212621715 |
|
|
Jun 30 07:29:53 PM PDT 24 |
Jun 30 08:05:35 PM PDT 24 |
21560305572 ps |
| T1305 |
/workspace/coverage/default/2.chip_sw_sysrst_ctrl_inputs.5259948 |
|
|
Jun 30 07:56:08 PM PDT 24 |
Jun 30 07:59:37 PM PDT 24 |
2804527221 ps |
| T1306 |
/workspace/coverage/default/2.chip_sw_example_rom.4078847058 |
|
|
Jun 30 07:51:03 PM PDT 24 |
Jun 30 07:53:41 PM PDT 24 |
2612947340 ps |
| T1307 |
/workspace/coverage/default/0.chip_sw_kmac_idle.4076800314 |
|
|
Jun 30 07:30:34 PM PDT 24 |
Jun 30 07:34:42 PM PDT 24 |
2887417032 ps |
| T1308 |
/workspace/coverage/default/1.chip_sw_sensor_ctrl_status.3011904669 |
|
|
Jun 30 07:48:56 PM PDT 24 |
Jun 30 07:52:56 PM PDT 24 |
3082284446 ps |
| T1309 |
/workspace/coverage/default/61.chip_sw_all_escalation_resets.2438013691 |
|
|
Jun 30 08:06:47 PM PDT 24 |
Jun 30 08:19:42 PM PDT 24 |
4563133962 ps |
| T1310 |
/workspace/coverage/default/0.chip_sw_uart_tx_rx.1901931895 |
|
|
Jun 30 07:27:09 PM PDT 24 |
Jun 30 07:37:13 PM PDT 24 |
4681523748 ps |
| T752 |
/workspace/coverage/default/19.chip_sw_alert_handler_lpg_sleep_mode_alerts.1008405725 |
|
|
Jun 30 08:03:54 PM PDT 24 |
Jun 30 08:09:28 PM PDT 24 |
3993247350 ps |
| T1311 |
/workspace/coverage/default/0.chip_sw_alert_handler_lpg_reset_toggle.1548082397 |
|
|
Jun 30 07:28:58 PM PDT 24 |
Jun 30 07:58:55 PM PDT 24 |
7865316216 ps |
| T1312 |
/workspace/coverage/default/94.chip_sw_all_escalation_resets.2769271526 |
|
|
Jun 30 08:10:34 PM PDT 24 |
Jun 30 08:21:37 PM PDT 24 |
5276038120 ps |
| T1313 |
/workspace/coverage/default/1.chip_sw_pwrmgr_full_aon_reset.2547981829 |
|
|
Jun 30 07:41:29 PM PDT 24 |
Jun 30 07:46:52 PM PDT 24 |
8604419211 ps |
| T1314 |
/workspace/coverage/default/1.rom_e2e_asm_init_dev.2953313825 |
|
|
Jun 30 07:54:45 PM PDT 24 |
Jun 30 09:02:38 PM PDT 24 |
15007058274 ps |
| T1315 |
/workspace/coverage/default/1.chip_sw_keymgr_sideload_kmac.2465793688 |
|
|
Jun 30 07:46:18 PM PDT 24 |
Jun 30 08:10:28 PM PDT 24 |
7283024800 ps |
| T1316 |
/workspace/coverage/default/0.chip_sw_otp_ctrl_lc_signals_prod.100687310 |
|
|
Jun 30 07:28:47 PM PDT 24 |
Jun 30 07:48:44 PM PDT 24 |
7213500680 ps |
| T1317 |
/workspace/coverage/default/0.chip_sw_flash_ctrl_mem_protection.129932288 |
|
|
Jun 30 07:35:53 PM PDT 24 |
Jun 30 07:54:07 PM PDT 24 |
6129609088 ps |
| T1318 |
/workspace/coverage/default/2.chip_sw_rv_timer_smoketest.2879225118 |
|
|
Jun 30 08:00:17 PM PDT 24 |
Jun 30 08:04:28 PM PDT 24 |
2972238000 ps |
| T756 |
/workspace/coverage/default/18.chip_sw_alert_handler_lpg_sleep_mode_alerts.3715289924 |
|
|
Jun 30 08:03:38 PM PDT 24 |
Jun 30 08:10:46 PM PDT 24 |
3425785308 ps |
| T392 |
/workspace/coverage/default/0.chip_sw_pwrmgr_normal_sleep_all_wake_ups.206800209 |
|
|
Jun 30 07:36:13 PM PDT 24 |
Jun 30 07:44:33 PM PDT 24 |
7672213800 ps |
| T1319 |
/workspace/coverage/default/2.chip_sw_hmac_enc.2447039057 |
|
|
Jun 30 07:55:11 PM PDT 24 |
Jun 30 08:00:56 PM PDT 24 |
3141501452 ps |
| T75 |
/workspace/coverage/default/0.chip_sw_usbdev_pincfg.2935282687 |
|
|
Jun 30 07:27:53 PM PDT 24 |
Jun 30 09:34:40 PM PDT 24 |
31671859432 ps |
| T1320 |
/workspace/coverage/default/0.chip_sw_usbdev_setuprx.2067245461 |
|
|
Jun 30 07:27:46 PM PDT 24 |
Jun 30 07:37:33 PM PDT 24 |
4167623402 ps |
| T290 |
/workspace/coverage/default/0.chip_sw_rv_core_ibex_address_translation.1076212065 |
|
|
Jun 30 07:34:02 PM PDT 24 |
Jun 30 07:39:00 PM PDT 24 |
2739901430 ps |
| T1321 |
/workspace/coverage/default/1.rom_e2e_asm_init_test_unlocked0.3862783865 |
|
|
Jun 30 07:52:50 PM PDT 24 |
Jun 30 08:48:35 PM PDT 24 |
11393401639 ps |
| T1322 |
/workspace/coverage/default/2.chip_sw_otbn_randomness.2234343636 |
|
|
Jun 30 07:57:26 PM PDT 24 |
Jun 30 08:13:36 PM PDT 24 |
5723959824 ps |
| T1323 |
/workspace/coverage/default/44.chip_sw_all_escalation_resets.1836812310 |
|
|
Jun 30 08:05:43 PM PDT 24 |
Jun 30 08:16:32 PM PDT 24 |
5104922936 ps |
| T783 |
/workspace/coverage/default/47.chip_sw_all_escalation_resets.1127388745 |
|
|
Jun 30 08:08:29 PM PDT 24 |
Jun 30 08:19:05 PM PDT 24 |
6298037500 ps |
| T1324 |
/workspace/coverage/default/1.chip_sw_lc_ctrl_transition.3785441081 |
|
|
Jun 30 07:41:42 PM PDT 24 |
Jun 30 08:01:56 PM PDT 24 |
13411157122 ps |
| T747 |
/workspace/coverage/default/77.chip_sw_all_escalation_resets.4063834294 |
|
|
Jun 30 08:08:57 PM PDT 24 |
Jun 30 08:19:00 PM PDT 24 |
5593187902 ps |
| T1325 |
/workspace/coverage/default/18.chip_sw_all_escalation_resets.1894290453 |
|
|
Jun 30 08:06:25 PM PDT 24 |
Jun 30 08:14:19 PM PDT 24 |
4958139760 ps |
| T1326 |
/workspace/coverage/default/2.chip_sw_rstmgr_sw_rst.3396285822 |
|
|
Jun 30 07:53:11 PM PDT 24 |
Jun 30 07:56:52 PM PDT 24 |
2576250856 ps |
| T1327 |
/workspace/coverage/default/2.rom_e2e_asm_init_dev.1485762023 |
|
|
Jun 30 08:06:57 PM PDT 24 |
Jun 30 09:15:44 PM PDT 24 |
15452432691 ps |
| T1328 |
/workspace/coverage/default/1.chip_sw_entropy_src_smoketest.663894531 |
|
|
Jun 30 07:49:52 PM PDT 24 |
Jun 30 08:00:48 PM PDT 24 |
3441130436 ps |
| T1329 |
/workspace/coverage/default/0.chip_sw_pwrmgr_full_aon_reset.4285931940 |
|
|
Jun 30 07:29:11 PM PDT 24 |
Jun 30 07:36:03 PM PDT 24 |
9041518828 ps |
| T1330 |
/workspace/coverage/default/0.chip_sw_lc_ctrl_raw_to_scrap.238445902 |
|
|
Jun 30 07:31:26 PM PDT 24 |
Jun 30 07:33:17 PM PDT 24 |
2868103352 ps |
| T1331 |
/workspace/coverage/default/1.chip_sw_edn_sw_mode.2537719419 |
|
|
Jun 30 07:45:45 PM PDT 24 |
Jun 30 08:28:32 PM PDT 24 |
10307826292 ps |
| T1332 |
/workspace/coverage/default/28.chip_sw_alert_handler_lpg_sleep_mode_alerts.138885689 |
|
|
Jun 30 08:06:05 PM PDT 24 |
Jun 30 08:11:25 PM PDT 24 |
3917788206 ps |
| T1333 |
/workspace/coverage/default/0.chip_sw_flash_ctrl_write_clear.3307543142 |
|
|
Jun 30 07:34:43 PM PDT 24 |
Jun 30 07:40:31 PM PDT 24 |
2918111224 ps |
| T342 |
/workspace/coverage/default/0.chip_sw_aon_timer_irq.3684977698 |
|
|
Jun 30 07:27:53 PM PDT 24 |
Jun 30 07:35:41 PM PDT 24 |
4130018040 ps |
| T76 |
/workspace/coverage/default/0.chip_sw_usbdev_pullup.2029831261 |
|
|
Jun 30 07:28:46 PM PDT 24 |
Jun 30 07:32:58 PM PDT 24 |
3358268680 ps |
| T1334 |
/workspace/coverage/default/1.chip_sw_clkmgr_jitter.1843826231 |
|
|
Jun 30 07:47:28 PM PDT 24 |
Jun 30 07:51:39 PM PDT 24 |
3506434603 ps |
| T9 |
/workspace/coverage/default/2.chip_rv_dm_ndm_reset_req.3472912974 |
|
|
Jun 30 07:58:12 PM PDT 24 |
Jun 30 08:07:48 PM PDT 24 |
4725135474 ps |
| T1335 |
/workspace/coverage/default/3.chip_sw_all_escalation_resets.1373850617 |
|
|
Jun 30 08:00:40 PM PDT 24 |
Jun 30 08:13:01 PM PDT 24 |
4992974384 ps |
| T1336 |
/workspace/coverage/default/2.chip_sw_uart_smoketest.2378535248 |
|
|
Jun 30 08:00:18 PM PDT 24 |
Jun 30 08:05:22 PM PDT 24 |
3112886340 ps |
| T292 |
/workspace/coverage/default/0.chip_sw_sram_ctrl_execution_main.1062162974 |
|
|
Jun 30 07:33:36 PM PDT 24 |
Jun 30 07:48:55 PM PDT 24 |
8619190144 ps |
| T1337 |
/workspace/coverage/default/2.chip_sw_clkmgr_sleep_frequency.1266452083 |
|
|
Jun 30 07:56:56 PM PDT 24 |
Jun 30 08:09:09 PM PDT 24 |
4795376584 ps |
| T1338 |
/workspace/coverage/default/0.chip_sw_example_concurrency.2437082064 |
|
|
Jun 30 07:32:26 PM PDT 24 |
Jun 30 07:37:32 PM PDT 24 |
3575158800 ps |
| T1339 |
/workspace/coverage/default/58.chip_sw_all_escalation_resets.1997086282 |
|
|
Jun 30 08:07:54 PM PDT 24 |
Jun 30 08:17:49 PM PDT 24 |
4688763140 ps |
| T1340 |
/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_bad_b_good_prod_end.1765003948 |
|
|
Jun 30 07:42:38 PM PDT 24 |
Jun 30 09:22:53 PM PDT 24 |
24401216078 ps |
| T1341 |
/workspace/coverage/default/0.chip_sw_pwrmgr_normal_sleep_all_reset_reqs.3361091185 |
|
|
Jun 30 07:31:19 PM PDT 24 |
Jun 30 07:56:11 PM PDT 24 |
12278462577 ps |
| T191 |
/workspace/coverage/default/2.chip_sw_spi_device_pass_through.3350659773 |
|
|
Jun 30 07:50:26 PM PDT 24 |
Jun 30 08:01:25 PM PDT 24 |
6245894095 ps |
| T293 |
/workspace/coverage/default/2.chip_sw_sram_ctrl_execution_main.1978667087 |
|
|
Jun 30 07:56:41 PM PDT 24 |
Jun 30 08:14:12 PM PDT 24 |
6903711027 ps |
| T779 |
/workspace/coverage/default/78.chip_sw_alert_handler_lpg_sleep_mode_alerts.592375352 |
|
|
Jun 30 08:09:41 PM PDT 24 |
Jun 30 08:16:22 PM PDT 24 |
3396855720 ps |
| T77 |
/workspace/coverage/cover_reg_top/33.xbar_random.1318077054 |
|
|
Jun 30 08:17:59 PM PDT 24 |
Jun 30 08:19:07 PM PDT 24 |
1015626348 ps |
| T78 |
/workspace/coverage/cover_reg_top/41.xbar_smoke_slow_rsp.319140339 |
|
|
Jun 30 08:19:46 PM PDT 24 |
Jun 30 08:21:23 PM PDT 24 |
5388338213 ps |
| T79 |
/workspace/coverage/cover_reg_top/82.xbar_stress_all.4233286664 |
|
|
Jun 30 08:27:17 PM PDT 24 |
Jun 30 08:31:24 PM PDT 24 |
6590314285 ps |
| T83 |
/workspace/coverage/cover_reg_top/7.xbar_random_slow_rsp.1323355291 |
|
|
Jun 30 08:10:11 PM PDT 24 |
Jun 30 08:20:54 PM PDT 24 |
36628914223 ps |
| T131 |
/workspace/coverage/cover_reg_top/4.chip_csr_hw_reset.3936065740 |
|
|
Jun 30 08:08:40 PM PDT 24 |
Jun 30 08:13:39 PM PDT 24 |
4407299602 ps |
| T240 |
/workspace/coverage/cover_reg_top/12.xbar_smoke_zero_delays.1317824662 |
|
|
Jun 30 08:12:18 PM PDT 24 |
Jun 30 08:12:25 PM PDT 24 |
52529333 ps |
| T540 |
/workspace/coverage/cover_reg_top/1.chip_csr_bit_bash.819602427 |
|
|
Jun 30 08:05:08 PM PDT 24 |
Jun 30 09:03:41 PM PDT 24 |
31419093696 ps |
| T538 |
/workspace/coverage/cover_reg_top/49.xbar_smoke_slow_rsp.3089329036 |
|
|
Jun 30 08:21:22 PM PDT 24 |
Jun 30 08:23:07 PM PDT 24 |
6194577197 ps |
| T531 |
/workspace/coverage/cover_reg_top/54.xbar_random_slow_rsp.1903051643 |
|
|
Jun 30 08:22:19 PM PDT 24 |
Jun 30 08:37:48 PM PDT 24 |
52360459548 ps |
| T239 |
/workspace/coverage/cover_reg_top/74.xbar_stress_all.223432972 |
|
|
Jun 30 08:25:56 PM PDT 24 |
Jun 30 08:28:29 PM PDT 24 |
4744021780 ps |
| T535 |
/workspace/coverage/cover_reg_top/96.xbar_unmapped_addr.367797513 |
|
|
Jun 30 08:29:36 PM PDT 24 |
Jun 30 08:30:37 PM PDT 24 |
1373524164 ps |
| T536 |
/workspace/coverage/cover_reg_top/68.xbar_random_large_delays.137138303 |
|
|
Jun 30 08:24:38 PM PDT 24 |
Jun 30 08:29:00 PM PDT 24 |
24159826010 ps |
| T537 |
/workspace/coverage/cover_reg_top/85.xbar_smoke_large_delays.3058817649 |
|
|
Jun 30 08:27:36 PM PDT 24 |
Jun 30 08:28:38 PM PDT 24 |
5827838731 ps |
| T523 |
/workspace/coverage/cover_reg_top/3.xbar_random_large_delays.3835779958 |
|
|
Jun 30 08:07:29 PM PDT 24 |
Jun 30 08:26:08 PM PDT 24 |
99373032623 ps |
| T434 |
/workspace/coverage/cover_reg_top/4.xbar_stress_all_with_reset_error.3998060820 |
|
|
Jun 30 08:08:30 PM PDT 24 |
Jun 30 08:09:44 PM PDT 24 |
173698203 ps |
| T539 |
/workspace/coverage/cover_reg_top/0.xbar_access_same_device.2594522587 |
|
|
Jun 30 08:04:35 PM PDT 24 |
Jun 30 08:06:01 PM PDT 24 |
1641630249 ps |
| T347 |
/workspace/coverage/cover_reg_top/9.chip_csr_rw.3700782371 |
|
|
Jun 30 08:11:21 PM PDT 24 |
Jun 30 08:16:50 PM PDT 24 |
4002998560 ps |
| T534 |
/workspace/coverage/cover_reg_top/17.xbar_random_large_delays.629362720 |
|
|
Jun 30 08:14:13 PM PDT 24 |
Jun 30 08:17:51 PM PDT 24 |
21762863483 ps |
| T532 |
/workspace/coverage/cover_reg_top/97.xbar_random.2958955746 |
|
|
Jun 30 08:29:42 PM PDT 24 |
Jun 30 08:30:15 PM PDT 24 |
328647061 ps |
| T493 |
/workspace/coverage/cover_reg_top/48.xbar_random.2768824224 |
|
|
Jun 30 08:21:08 PM PDT 24 |
Jun 30 08:21:37 PM PDT 24 |
627096444 ps |
| T435 |
/workspace/coverage/cover_reg_top/58.xbar_stress_all_with_error.2014527663 |
|
|
Jun 30 08:22:56 PM PDT 24 |
Jun 30 08:24:56 PM PDT 24 |
1163058013 ps |
| T530 |
/workspace/coverage/cover_reg_top/0.chip_tl_errors.2218417567 |
|
|
Jun 30 08:04:05 PM PDT 24 |
Jun 30 08:08:00 PM PDT 24 |
2871951600 ps |
| T1342 |
/workspace/coverage/cover_reg_top/99.xbar_smoke_large_delays.351557460 |
|
|
Jun 30 08:30:04 PM PDT 24 |
Jun 30 08:32:03 PM PDT 24 |
11027745941 ps |